1ed367e6cSBorislav Petkov /* SandyBridge-EP/IvyTown uncore support */ 2ed367e6cSBorislav Petkov #include "uncore.h" 3ed367e6cSBorislav Petkov 468ce4a0dSKan Liang /* SNB-EP pci bus to socket mapping */ 568ce4a0dSKan Liang #define SNBEP_CPUNODEID 0x40 668ce4a0dSKan Liang #define SNBEP_GIDNIDMAP 0x54 768ce4a0dSKan Liang 8ed367e6cSBorislav Petkov /* SNB-EP Box level control */ 9ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0) 10ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1) 11ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_FRZ (1 << 8) 12ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16) 13ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ 14ed367e6cSBorislav Petkov SNBEP_PMON_BOX_CTL_RST_CTRS | \ 15ed367e6cSBorislav Petkov SNBEP_PMON_BOX_CTL_FRZ_EN) 16ed367e6cSBorislav Petkov /* SNB-EP event control */ 17ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff 18ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00 19ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_RST (1 << 17) 20ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EDGE_DET (1 << 18) 21ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) 22ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EN (1 << 22) 23ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_INVERT (1 << 23) 24ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000 25ed367e6cSBorislav Petkov #define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 26ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 27ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 28ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 29ed367e6cSBorislav Petkov SNBEP_PMON_CTL_TRESH_MASK) 30ed367e6cSBorislav Petkov 31ed367e6cSBorislav Petkov /* SNB-EP Ubox event control */ 32ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000 33ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \ 34ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 35ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 36ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 37ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 38ed367e6cSBorislav Petkov SNBEP_U_MSR_PMON_CTL_TRESH_MASK) 39ed367e6cSBorislav Petkov 40ed367e6cSBorislav Petkov #define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19) 41ed367e6cSBorislav Petkov #define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 42ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 43ed367e6cSBorislav Petkov 44ed367e6cSBorislav Petkov /* SNB-EP PCU event control */ 45ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000 46ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000 47ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30) 48ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31) 49ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 50ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 51ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 52ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 53ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 54ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 55ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 56ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 57ed367e6cSBorislav Petkov 58ed367e6cSBorislav Petkov #define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \ 59ed367e6cSBorislav Petkov (SNBEP_PMON_RAW_EVENT_MASK | \ 60ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EV_SEL_EXT) 61ed367e6cSBorislav Petkov 62ed367e6cSBorislav Petkov /* SNB-EP pci control register */ 63ed367e6cSBorislav Petkov #define SNBEP_PCI_PMON_BOX_CTL 0xf4 64ed367e6cSBorislav Petkov #define SNBEP_PCI_PMON_CTL0 0xd8 65ed367e6cSBorislav Petkov /* SNB-EP pci counter register */ 66ed367e6cSBorislav Petkov #define SNBEP_PCI_PMON_CTR0 0xa0 67ed367e6cSBorislav Petkov 68ed367e6cSBorislav Petkov /* SNB-EP home agent register */ 69ed367e6cSBorislav Petkov #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40 70ed367e6cSBorislav Petkov #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44 71ed367e6cSBorislav Petkov #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48 72ed367e6cSBorislav Petkov /* SNB-EP memory controller register */ 73ed367e6cSBorislav Petkov #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0 74ed367e6cSBorislav Petkov #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0 75ed367e6cSBorislav Petkov /* SNB-EP QPI register */ 76ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228 77ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c 78ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238 79ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c 80ed367e6cSBorislav Petkov 81ed367e6cSBorislav Petkov /* SNB-EP Ubox register */ 82ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_CTR0 0xc16 83ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_CTL0 0xc10 84ed367e6cSBorislav Petkov 85ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08 86ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09 87ed367e6cSBorislav Petkov 88ed367e6cSBorislav Petkov /* SNB-EP Cbo register */ 89ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_CTR0 0xd16 90ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_CTL0 0xd10 91ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04 92ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14 93ed367e6cSBorislav Petkov #define SNBEP_CBO_MSR_OFFSET 0x20 94ed367e6cSBorislav Petkov 95ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f 96ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00 97ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000 98ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000 99ed367e6cSBorislav Petkov 100ed367e6cSBorislav Petkov #define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \ 101ed367e6cSBorislav Petkov .event = (e), \ 102ed367e6cSBorislav Petkov .msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \ 103ed367e6cSBorislav Petkov .config_mask = (m), \ 104ed367e6cSBorislav Petkov .idx = (i) \ 105ed367e6cSBorislav Petkov } 106ed367e6cSBorislav Petkov 107ed367e6cSBorislav Petkov /* SNB-EP PCU register */ 108ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTR0 0xc36 109ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL0 0xc30 110ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24 111ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34 112ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff 113ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc 114ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd 115ed367e6cSBorislav Petkov 116ed367e6cSBorislav Petkov /* IVBEP event control */ 117ed367e6cSBorislav Petkov #define IVBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ 118ed367e6cSBorislav Petkov SNBEP_PMON_BOX_CTL_RST_CTRS) 119ed367e6cSBorislav Petkov #define IVBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 120ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 121ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 122ed367e6cSBorislav Petkov SNBEP_PMON_CTL_TRESH_MASK) 123ed367e6cSBorislav Petkov /* IVBEP Ubox */ 124ed367e6cSBorislav Petkov #define IVBEP_U_MSR_PMON_GLOBAL_CTL 0xc00 125ed367e6cSBorislav Petkov #define IVBEP_U_PMON_GLOBAL_FRZ_ALL (1 << 31) 126ed367e6cSBorislav Petkov #define IVBEP_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29) 127ed367e6cSBorislav Petkov 128ed367e6cSBorislav Petkov #define IVBEP_U_MSR_PMON_RAW_EVENT_MASK \ 129ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 130ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 131ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 132ed367e6cSBorislav Petkov SNBEP_U_MSR_PMON_CTL_TRESH_MASK) 133ed367e6cSBorislav Petkov /* IVBEP Cbo */ 134ed367e6cSBorislav Petkov #define IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK (IVBEP_PMON_RAW_EVENT_MASK | \ 135ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 136ed367e6cSBorislav Petkov 137ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0) 138ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5) 139ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17) 140ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32) 141ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52) 142ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 143ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 144ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 145ed367e6cSBorislav Petkov 146ed367e6cSBorislav Petkov /* IVBEP home agent */ 147ed367e6cSBorislav Petkov #define IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16) 148ed367e6cSBorislav Petkov #define IVBEP_HA_PCI_PMON_RAW_EVENT_MASK \ 149ed367e6cSBorislav Petkov (IVBEP_PMON_RAW_EVENT_MASK | \ 150ed367e6cSBorislav Petkov IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST) 151ed367e6cSBorislav Petkov /* IVBEP PCU */ 152ed367e6cSBorislav Petkov #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 153ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 154ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 155ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 156ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 157ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 158ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 159ed367e6cSBorislav Petkov /* IVBEP QPI */ 160ed367e6cSBorislav Petkov #define IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK \ 161ed367e6cSBorislav Petkov (IVBEP_PMON_RAW_EVENT_MASK | \ 162ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EV_SEL_EXT) 163ed367e6cSBorislav Petkov 164ed367e6cSBorislav Petkov #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \ 165ed367e6cSBorislav Petkov ((1ULL << (n)) - 1))) 166ed367e6cSBorislav Petkov 167ed367e6cSBorislav Petkov /* Haswell-EP Ubox */ 168ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_CTR0 0x709 169ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_CTL0 0x705 170ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_FILTER 0x707 171ed367e6cSBorislav Petkov 172ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703 173ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704 174ed367e6cSBorislav Petkov 175ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0) 176ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1) 177ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_BOX_FILTER_MASK \ 178ed367e6cSBorislav Petkov (HSWEP_U_MSR_PMON_BOX_FILTER_TID | \ 179ed367e6cSBorislav Petkov HSWEP_U_MSR_PMON_BOX_FILTER_CID) 180ed367e6cSBorislav Petkov 181ed367e6cSBorislav Petkov /* Haswell-EP CBo */ 182ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_CTR0 0xe08 183ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_CTL0 0xe01 184ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00 185ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05 186ed367e6cSBorislav Petkov #define HSWEP_CBO_MSR_OFFSET 0x10 187ed367e6cSBorislav Petkov 188ed367e6cSBorislav Petkov 189ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0) 190ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6) 191ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17) 192ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32) 193ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52) 194ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 195ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 196ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 197ed367e6cSBorislav Petkov 198ed367e6cSBorislav Petkov 199ed367e6cSBorislav Petkov /* Haswell-EP Sbox */ 200ed367e6cSBorislav Petkov #define HSWEP_S0_MSR_PMON_CTR0 0x726 201ed367e6cSBorislav Petkov #define HSWEP_S0_MSR_PMON_CTL0 0x721 202ed367e6cSBorislav Petkov #define HSWEP_S0_MSR_PMON_BOX_CTL 0x720 203ed367e6cSBorislav Petkov #define HSWEP_SBOX_MSR_OFFSET 0xa 204ed367e6cSBorislav Petkov #define HSWEP_S_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 205ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 206ed367e6cSBorislav Petkov 207ed367e6cSBorislav Petkov /* Haswell-EP PCU */ 208ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_CTR0 0x717 209ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_CTL0 0x711 210ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710 211ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715 212ed367e6cSBorislav Petkov 213ed367e6cSBorislav Petkov /* KNL Ubox */ 214ed367e6cSBorislav Petkov #define KNL_U_MSR_PMON_RAW_EVENT_MASK \ 215ed367e6cSBorislav Petkov (SNBEP_U_MSR_PMON_RAW_EVENT_MASK | \ 216ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 217ed367e6cSBorislav Petkov /* KNL CHA */ 218ed367e6cSBorislav Petkov #define KNL_CHA_MSR_OFFSET 0xc 219ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_CTL_QOR (1 << 16) 220ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_RAW_EVENT_MASK \ 221ed367e6cSBorislav Petkov (SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK | \ 222ed367e6cSBorislav Petkov KNL_CHA_MSR_PMON_CTL_QOR) 223ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff 224ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE (7 << 18) 225ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32) 226ec336c87Shchrzani #define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE (0x1ULL << 32) 227ec336c87Shchrzani #define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE (0x1ULL << 33) 228ec336c87Shchrzani #define KNL_CHA_MSR_PMON_BOX_FILTER_NNC (0x1ULL << 37) 229ed367e6cSBorislav Petkov 230ed367e6cSBorislav Petkov /* KNL EDC/MC UCLK */ 231ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400 232ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_CTL0 0x420 233ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_BOX_CTL 0x430 234ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c 235ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454 236ed367e6cSBorislav Petkov #define KNL_PMON_FIXED_CTL_EN 0x1 237ed367e6cSBorislav Petkov 238ed367e6cSBorislav Petkov /* KNL EDC */ 239ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00 240ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20 241ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30 242ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c 243ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44 244ed367e6cSBorislav Petkov 245ed367e6cSBorislav Petkov /* KNL MC */ 246ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00 247ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20 248ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30 249ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c 250ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44 251ed367e6cSBorislav Petkov 252ed367e6cSBorislav Petkov /* KNL IRP */ 253ed367e6cSBorislav Petkov #define KNL_IRP_PCI_PMON_BOX_CTL 0xf0 254ed367e6cSBorislav Petkov #define KNL_IRP_PCI_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 255ed367e6cSBorislav Petkov KNL_CHA_MSR_PMON_CTL_QOR) 256ed367e6cSBorislav Petkov /* KNL PCU */ 257ed367e6cSBorislav Petkov #define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f 258ed367e6cSBorislav Petkov #define KNL_PCU_PMON_CTL_USE_OCC_CTR (1 << 7) 259ed367e6cSBorislav Petkov #define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000 260ed367e6cSBorislav Petkov #define KNL_PCU_MSR_PMON_RAW_EVENT_MASK \ 261ed367e6cSBorislav Petkov (KNL_PCU_PMON_CTL_EV_SEL_MASK | \ 262ed367e6cSBorislav Petkov KNL_PCU_PMON_CTL_USE_OCC_CTR | \ 263ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 264ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 265ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN | \ 266ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 267ed367e6cSBorislav Petkov KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \ 268ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 269ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 270ed367e6cSBorislav Petkov 271cd34cd97SKan Liang /* SKX pci bus to socket mapping */ 272cd34cd97SKan Liang #define SKX_CPUNODEID 0xc0 273cd34cd97SKan Liang #define SKX_GIDNIDMAP 0xd4 274cd34cd97SKan Liang 275cd34cd97SKan Liang /* SKX CHA */ 276cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_TID (0x1ffULL << 0) 277cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_LINK (0xfULL << 9) 278cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_STATE (0x3ffULL << 17) 279cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_REM (0x1ULL << 32) 280cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_LOC (0x1ULL << 33) 281cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC (0x1ULL << 35) 282cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_NM (0x1ULL << 36) 283cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM (0x1ULL << 37) 284cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 (0x3ffULL << 41) 285cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 (0x3ffULL << 51) 286cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 287cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 288cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 289cd34cd97SKan Liang 290cd34cd97SKan Liang /* SKX IIO */ 291cd34cd97SKan Liang #define SKX_IIO0_MSR_PMON_CTL0 0xa48 292cd34cd97SKan Liang #define SKX_IIO0_MSR_PMON_CTR0 0xa41 293cd34cd97SKan Liang #define SKX_IIO0_MSR_PMON_BOX_CTL 0xa40 294cd34cd97SKan Liang #define SKX_IIO_MSR_OFFSET 0x20 295cd34cd97SKan Liang 296cd34cd97SKan Liang #define SKX_PMON_CTL_TRESH_MASK (0xff << 24) 297cd34cd97SKan Liang #define SKX_PMON_CTL_TRESH_MASK_EXT (0xf) 298cd34cd97SKan Liang #define SKX_PMON_CTL_CH_MASK (0xff << 4) 299cd34cd97SKan Liang #define SKX_PMON_CTL_FC_MASK (0x7 << 12) 300cd34cd97SKan Liang #define SKX_IIO_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 301cd34cd97SKan Liang SNBEP_PMON_CTL_UMASK_MASK | \ 302cd34cd97SKan Liang SNBEP_PMON_CTL_EDGE_DET | \ 303cd34cd97SKan Liang SNBEP_PMON_CTL_INVERT | \ 304cd34cd97SKan Liang SKX_PMON_CTL_TRESH_MASK) 305cd34cd97SKan Liang #define SKX_IIO_PMON_RAW_EVENT_MASK_EXT (SKX_PMON_CTL_TRESH_MASK_EXT | \ 306cd34cd97SKan Liang SKX_PMON_CTL_CH_MASK | \ 307cd34cd97SKan Liang SKX_PMON_CTL_FC_MASK) 308cd34cd97SKan Liang 309cd34cd97SKan Liang /* SKX IRP */ 310cd34cd97SKan Liang #define SKX_IRP0_MSR_PMON_CTL0 0xa5b 311cd34cd97SKan Liang #define SKX_IRP0_MSR_PMON_CTR0 0xa59 312cd34cd97SKan Liang #define SKX_IRP0_MSR_PMON_BOX_CTL 0xa58 313cd34cd97SKan Liang #define SKX_IRP_MSR_OFFSET 0x20 314cd34cd97SKan Liang 315cd34cd97SKan Liang /* SKX UPI */ 316cd34cd97SKan Liang #define SKX_UPI_PCI_PMON_CTL0 0x350 317cd34cd97SKan Liang #define SKX_UPI_PCI_PMON_CTR0 0x318 318cd34cd97SKan Liang #define SKX_UPI_PCI_PMON_BOX_CTL 0x378 319b3625980SStephane Eranian #define SKX_UPI_CTL_UMASK_EXT 0xffefff 320cd34cd97SKan Liang 321cd34cd97SKan Liang /* SKX M2M */ 322cd34cd97SKan Liang #define SKX_M2M_PCI_PMON_CTL0 0x228 323cd34cd97SKan Liang #define SKX_M2M_PCI_PMON_CTR0 0x200 324cd34cd97SKan Liang #define SKX_M2M_PCI_PMON_BOX_CTL 0x258 325cd34cd97SKan Liang 326ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 327ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6"); 328ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); 329ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7"); 330ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 331b3625980SStephane Eranian DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55"); 332ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16"); 333ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 334ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); 335ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 336cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35"); 337ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31"); 338ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29"); 339ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28"); 340ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15"); 341ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); 342ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); 343ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31"); 344cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43"); 345cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46"); 346ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); 347ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0"); 348ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5"); 349ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8"); 350ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5"); 351ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8"); 352ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8"); 353ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12"); 354ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); 355ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47"); 356ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); 357ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22"); 358ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23"); 359ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state4, filter_state, "config1:18-20"); 360cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_state5, filter_state, "config1:17-26"); 361cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_rem, filter_rem, "config1:32"); 362cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_loc, filter_loc, "config1:33"); 363cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_nm, filter_nm, "config1:36"); 364cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_not_nm, filter_not_nm, "config1:37"); 365ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_local, filter_local, "config1:33"); 366ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_all_op, filter_all_op, "config1:35"); 367ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nnm, filter_nnm, "config1:37"); 368ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); 369ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60"); 370ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_opc3, filter_opc, "config1:41-60"); 371cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_opc_0, filter_opc0, "config1:41-50"); 372cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_opc_1, filter_opc1, "config1:51-60"); 373ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62"); 374ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61"); 375ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63"); 376ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7"); 377ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15"); 378ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23"); 379ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31"); 380ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51"); 381ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35"); 382ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31"); 383ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17"); 384ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12"); 385ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8"); 386ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4"); 387ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31"); 388ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63"); 389ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51"); 390ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35"); 391ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31"); 392ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17"); 393ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12"); 394ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8"); 395ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4"); 396ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31"); 397ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63"); 398ed367e6cSBorislav Petkov 399ed367e6cSBorislav Petkov static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box) 400ed367e6cSBorislav Petkov { 401ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 402ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 403ed367e6cSBorislav Petkov u32 config = 0; 404ed367e6cSBorislav Petkov 405ed367e6cSBorislav Petkov if (!pci_read_config_dword(pdev, box_ctl, &config)) { 406ed367e6cSBorislav Petkov config |= SNBEP_PMON_BOX_CTL_FRZ; 407ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, config); 408ed367e6cSBorislav Petkov } 409ed367e6cSBorislav Petkov } 410ed367e6cSBorislav Petkov 411ed367e6cSBorislav Petkov static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box) 412ed367e6cSBorislav Petkov { 413ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 414ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 415ed367e6cSBorislav Petkov u32 config = 0; 416ed367e6cSBorislav Petkov 417ed367e6cSBorislav Petkov if (!pci_read_config_dword(pdev, box_ctl, &config)) { 418ed367e6cSBorislav Petkov config &= ~SNBEP_PMON_BOX_CTL_FRZ; 419ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, config); 420ed367e6cSBorislav Petkov } 421ed367e6cSBorislav Petkov } 422ed367e6cSBorislav Petkov 423ed367e6cSBorislav Petkov static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) 424ed367e6cSBorislav Petkov { 425ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 426ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 427ed367e6cSBorislav Petkov 428ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 429ed367e6cSBorislav Petkov } 430ed367e6cSBorislav Petkov 431ed367e6cSBorislav Petkov static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event) 432ed367e6cSBorislav Petkov { 433ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 434ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 435ed367e6cSBorislav Petkov 436ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, hwc->config); 437ed367e6cSBorislav Petkov } 438ed367e6cSBorislav Petkov 439ed367e6cSBorislav Petkov static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event) 440ed367e6cSBorislav Petkov { 441ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 442ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 443ed367e6cSBorislav Petkov u64 count = 0; 444ed367e6cSBorislav Petkov 445ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); 446ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); 447ed367e6cSBorislav Petkov 448ed367e6cSBorislav Petkov return count; 449ed367e6cSBorislav Petkov } 450ed367e6cSBorislav Petkov 451ed367e6cSBorislav Petkov static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) 452ed367e6cSBorislav Petkov { 453ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 454ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 455ed367e6cSBorislav Petkov 456ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT); 457ed367e6cSBorislav Petkov } 458ed367e6cSBorislav Petkov 459ed367e6cSBorislav Petkov static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) 460ed367e6cSBorislav Petkov { 461ed367e6cSBorislav Petkov u64 config; 462ed367e6cSBorislav Petkov unsigned msr; 463ed367e6cSBorislav Petkov 464ed367e6cSBorislav Petkov msr = uncore_msr_box_ctl(box); 465ed367e6cSBorislav Petkov if (msr) { 466ed367e6cSBorislav Petkov rdmsrl(msr, config); 467ed367e6cSBorislav Petkov config |= SNBEP_PMON_BOX_CTL_FRZ; 468ed367e6cSBorislav Petkov wrmsrl(msr, config); 469ed367e6cSBorislav Petkov } 470ed367e6cSBorislav Petkov } 471ed367e6cSBorislav Petkov 472ed367e6cSBorislav Petkov static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box) 473ed367e6cSBorislav Petkov { 474ed367e6cSBorislav Petkov u64 config; 475ed367e6cSBorislav Petkov unsigned msr; 476ed367e6cSBorislav Petkov 477ed367e6cSBorislav Petkov msr = uncore_msr_box_ctl(box); 478ed367e6cSBorislav Petkov if (msr) { 479ed367e6cSBorislav Petkov rdmsrl(msr, config); 480ed367e6cSBorislav Petkov config &= ~SNBEP_PMON_BOX_CTL_FRZ; 481ed367e6cSBorislav Petkov wrmsrl(msr, config); 482ed367e6cSBorislav Petkov } 483ed367e6cSBorislav Petkov } 484ed367e6cSBorislav Petkov 485ed367e6cSBorislav Petkov static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 486ed367e6cSBorislav Petkov { 487ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 488ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 489ed367e6cSBorislav Petkov 490ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) 491ed367e6cSBorislav Petkov wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); 492ed367e6cSBorislav Petkov 493ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 494ed367e6cSBorislav Petkov } 495ed367e6cSBorislav Petkov 496ed367e6cSBorislav Petkov static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box, 497ed367e6cSBorislav Petkov struct perf_event *event) 498ed367e6cSBorislav Petkov { 499ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 500ed367e6cSBorislav Petkov 501ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config); 502ed367e6cSBorislav Petkov } 503ed367e6cSBorislav Petkov 504ed367e6cSBorislav Petkov static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) 505ed367e6cSBorislav Petkov { 506ed367e6cSBorislav Petkov unsigned msr = uncore_msr_box_ctl(box); 507ed367e6cSBorislav Petkov 508ed367e6cSBorislav Petkov if (msr) 509ed367e6cSBorislav Petkov wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); 510ed367e6cSBorislav Petkov } 511ed367e6cSBorislav Petkov 512ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_formats_attr[] = { 513ed367e6cSBorislav Petkov &format_attr_event.attr, 514ed367e6cSBorislav Petkov &format_attr_umask.attr, 515ed367e6cSBorislav Petkov &format_attr_edge.attr, 516ed367e6cSBorislav Petkov &format_attr_inv.attr, 517ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 518ed367e6cSBorislav Petkov NULL, 519ed367e6cSBorislav Petkov }; 520ed367e6cSBorislav Petkov 521ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_ubox_formats_attr[] = { 522ed367e6cSBorislav Petkov &format_attr_event.attr, 523ed367e6cSBorislav Petkov &format_attr_umask.attr, 524ed367e6cSBorislav Petkov &format_attr_edge.attr, 525ed367e6cSBorislav Petkov &format_attr_inv.attr, 526ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 527ed367e6cSBorislav Petkov NULL, 528ed367e6cSBorislav Petkov }; 529ed367e6cSBorislav Petkov 530ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_cbox_formats_attr[] = { 531ed367e6cSBorislav Petkov &format_attr_event.attr, 532ed367e6cSBorislav Petkov &format_attr_umask.attr, 533ed367e6cSBorislav Petkov &format_attr_edge.attr, 534ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 535ed367e6cSBorislav Petkov &format_attr_inv.attr, 536ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 537ed367e6cSBorislav Petkov &format_attr_filter_tid.attr, 538ed367e6cSBorislav Petkov &format_attr_filter_nid.attr, 539ed367e6cSBorislav Petkov &format_attr_filter_state.attr, 540ed367e6cSBorislav Petkov &format_attr_filter_opc.attr, 541ed367e6cSBorislav Petkov NULL, 542ed367e6cSBorislav Petkov }; 543ed367e6cSBorislav Petkov 544ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_pcu_formats_attr[] = { 545cb225252SKan Liang &format_attr_event.attr, 546ed367e6cSBorislav Petkov &format_attr_occ_sel.attr, 547ed367e6cSBorislav Petkov &format_attr_edge.attr, 548ed367e6cSBorislav Petkov &format_attr_inv.attr, 549ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 550ed367e6cSBorislav Petkov &format_attr_occ_invert.attr, 551ed367e6cSBorislav Petkov &format_attr_occ_edge.attr, 552ed367e6cSBorislav Petkov &format_attr_filter_band0.attr, 553ed367e6cSBorislav Petkov &format_attr_filter_band1.attr, 554ed367e6cSBorislav Petkov &format_attr_filter_band2.attr, 555ed367e6cSBorislav Petkov &format_attr_filter_band3.attr, 556ed367e6cSBorislav Petkov NULL, 557ed367e6cSBorislav Petkov }; 558ed367e6cSBorislav Petkov 559ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_qpi_formats_attr[] = { 560ed367e6cSBorislav Petkov &format_attr_event_ext.attr, 561ed367e6cSBorislav Petkov &format_attr_umask.attr, 562ed367e6cSBorislav Petkov &format_attr_edge.attr, 563ed367e6cSBorislav Petkov &format_attr_inv.attr, 564ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 565ed367e6cSBorislav Petkov &format_attr_match_rds.attr, 566ed367e6cSBorislav Petkov &format_attr_match_rnid30.attr, 567ed367e6cSBorislav Petkov &format_attr_match_rnid4.attr, 568ed367e6cSBorislav Petkov &format_attr_match_dnid.attr, 569ed367e6cSBorislav Petkov &format_attr_match_mc.attr, 570ed367e6cSBorislav Petkov &format_attr_match_opc.attr, 571ed367e6cSBorislav Petkov &format_attr_match_vnw.attr, 572ed367e6cSBorislav Petkov &format_attr_match0.attr, 573ed367e6cSBorislav Petkov &format_attr_match1.attr, 574ed367e6cSBorislav Petkov &format_attr_mask_rds.attr, 575ed367e6cSBorislav Petkov &format_attr_mask_rnid30.attr, 576ed367e6cSBorislav Petkov &format_attr_mask_rnid4.attr, 577ed367e6cSBorislav Petkov &format_attr_mask_dnid.attr, 578ed367e6cSBorislav Petkov &format_attr_mask_mc.attr, 579ed367e6cSBorislav Petkov &format_attr_mask_opc.attr, 580ed367e6cSBorislav Petkov &format_attr_mask_vnw.attr, 581ed367e6cSBorislav Petkov &format_attr_mask0.attr, 582ed367e6cSBorislav Petkov &format_attr_mask1.attr, 583ed367e6cSBorislav Petkov NULL, 584ed367e6cSBorislav Petkov }; 585ed367e6cSBorislav Petkov 586ed367e6cSBorislav Petkov static struct uncore_event_desc snbep_uncore_imc_events[] = { 587ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 588ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), 589ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 590ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 591ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), 592ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 593ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 594ed367e6cSBorislav Petkov { /* end: all zeroes */ }, 595ed367e6cSBorislav Petkov }; 596ed367e6cSBorislav Petkov 597ed367e6cSBorislav Petkov static struct uncore_event_desc snbep_uncore_qpi_events[] = { 598ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"), 599ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"), 600ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"), 601ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"), 602ed367e6cSBorislav Petkov { /* end: all zeroes */ }, 603ed367e6cSBorislav Petkov }; 604ed367e6cSBorislav Petkov 605ed367e6cSBorislav Petkov static struct attribute_group snbep_uncore_format_group = { 606ed367e6cSBorislav Petkov .name = "format", 607ed367e6cSBorislav Petkov .attrs = snbep_uncore_formats_attr, 608ed367e6cSBorislav Petkov }; 609ed367e6cSBorislav Petkov 610ed367e6cSBorislav Petkov static struct attribute_group snbep_uncore_ubox_format_group = { 611ed367e6cSBorislav Petkov .name = "format", 612ed367e6cSBorislav Petkov .attrs = snbep_uncore_ubox_formats_attr, 613ed367e6cSBorislav Petkov }; 614ed367e6cSBorislav Petkov 615ed367e6cSBorislav Petkov static struct attribute_group snbep_uncore_cbox_format_group = { 616ed367e6cSBorislav Petkov .name = "format", 617ed367e6cSBorislav Petkov .attrs = snbep_uncore_cbox_formats_attr, 618ed367e6cSBorislav Petkov }; 619ed367e6cSBorislav Petkov 620ed367e6cSBorislav Petkov static struct attribute_group snbep_uncore_pcu_format_group = { 621ed367e6cSBorislav Petkov .name = "format", 622ed367e6cSBorislav Petkov .attrs = snbep_uncore_pcu_formats_attr, 623ed367e6cSBorislav Petkov }; 624ed367e6cSBorislav Petkov 625ed367e6cSBorislav Petkov static struct attribute_group snbep_uncore_qpi_format_group = { 626ed367e6cSBorislav Petkov .name = "format", 627ed367e6cSBorislav Petkov .attrs = snbep_uncore_qpi_formats_attr, 628ed367e6cSBorislav Petkov }; 629ed367e6cSBorislav Petkov 630ed367e6cSBorislav Petkov #define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 631ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, \ 632ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, \ 633ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, \ 634ed367e6cSBorislav Petkov .enable_event = snbep_uncore_msr_enable_event, \ 635ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter 636ed367e6cSBorislav Petkov 637ed367e6cSBorislav Petkov #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 638ed367e6cSBorislav Petkov __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \ 639ed367e6cSBorislav Petkov .init_box = snbep_uncore_msr_init_box \ 640ed367e6cSBorislav Petkov 641ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_msr_ops = { 642ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 643ed367e6cSBorislav Petkov }; 644ed367e6cSBorislav Petkov 645ed367e6cSBorislav Petkov #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \ 646ed367e6cSBorislav Petkov .init_box = snbep_uncore_pci_init_box, \ 647ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, \ 648ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, \ 649ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, \ 650ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter 651ed367e6cSBorislav Petkov 652ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_pci_ops = { 653ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_OPS_COMMON_INIT(), 654ed367e6cSBorislav Petkov .enable_event = snbep_uncore_pci_enable_event, \ 655ed367e6cSBorislav Petkov }; 656ed367e6cSBorislav Petkov 657ed367e6cSBorislav Petkov static struct event_constraint snbep_uncore_cbox_constraints[] = { 658ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x1), 659ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x02, 0x3), 660ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x04, 0x3), 661ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x05, 0x3), 662ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x07, 0x3), 663ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x3), 664ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 665ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 666ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x3), 667ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1b, 0xc), 668ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1c, 0xc), 669ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1d, 0xc), 670ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1e, 0xc), 6711134c2b5SPeter Zijlstra UNCORE_EVENT_CONSTRAINT(0x1f, 0xe), 672ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 673ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 674ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 675ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 676ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 677ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 678ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x35, 0x3), 679ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 680ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 681ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 682ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 683ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), 684ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 685ed367e6cSBorislav Petkov }; 686ed367e6cSBorislav Petkov 687ed367e6cSBorislav Petkov static struct event_constraint snbep_uncore_r2pcie_constraints[] = { 688ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 689ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 690ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x1), 691ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 692ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 693ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 694ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 695ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 696ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 697ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 698ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 699ed367e6cSBorislav Petkov }; 700ed367e6cSBorislav Petkov 701ed367e6cSBorislav Petkov static struct event_constraint snbep_uncore_r3qpi_constraints[] = { 702ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 703ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 704ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 705ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 706ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 707ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 708ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 709ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 710ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 711ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 712ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 713ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 714ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 715ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2a, 0x3), 716ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), 717ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 718ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 719ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 720ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 721ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x30, 0x3), 722ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 723ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 724ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 725ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 726ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 727ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 728ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 729ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 730ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 731ed367e6cSBorislav Petkov }; 732ed367e6cSBorislav Petkov 733ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_ubox = { 734ed367e6cSBorislav Petkov .name = "ubox", 735ed367e6cSBorislav Petkov .num_counters = 2, 736ed367e6cSBorislav Petkov .num_boxes = 1, 737ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 738ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 739ed367e6cSBorislav Petkov .perf_ctr = SNBEP_U_MSR_PMON_CTR0, 740ed367e6cSBorislav Petkov .event_ctl = SNBEP_U_MSR_PMON_CTL0, 741ed367e6cSBorislav Petkov .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 742ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, 743ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, 744ed367e6cSBorislav Petkov .ops = &snbep_uncore_msr_ops, 745ed367e6cSBorislav Petkov .format_group = &snbep_uncore_ubox_format_group, 746ed367e6cSBorislav Petkov }; 747ed367e6cSBorislav Petkov 748ed367e6cSBorislav Petkov static struct extra_reg snbep_uncore_cbox_extra_regs[] = { 749ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 750ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 751ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 752ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6), 753ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 754ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6), 755ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 756ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6), 757ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6), 758ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8), 759ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8), 760ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa), 761ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa), 762ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2), 763ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2), 764ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2), 765ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2), 766ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8), 767ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8), 768ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa), 769ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa), 770ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2), 771ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2), 772ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2), 773ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2), 774ed367e6cSBorislav Petkov EVENT_EXTRA_END 775ed367e6cSBorislav Petkov }; 776ed367e6cSBorislav Petkov 777ed367e6cSBorislav Petkov static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event) 778ed367e6cSBorislav Petkov { 779ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 780ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 781ed367e6cSBorislav Petkov int i; 782ed367e6cSBorislav Petkov 783ed367e6cSBorislav Petkov if (uncore_box_is_fake(box)) 784ed367e6cSBorislav Petkov return; 785ed367e6cSBorislav Petkov 786ed367e6cSBorislav Petkov for (i = 0; i < 5; i++) { 787ed367e6cSBorislav Petkov if (reg1->alloc & (0x1 << i)) 788ed367e6cSBorislav Petkov atomic_sub(1 << (i * 6), &er->ref); 789ed367e6cSBorislav Petkov } 790ed367e6cSBorislav Petkov reg1->alloc = 0; 791ed367e6cSBorislav Petkov } 792ed367e6cSBorislav Petkov 793ed367e6cSBorislav Petkov static struct event_constraint * 794ed367e6cSBorislav Petkov __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event, 795ed367e6cSBorislav Petkov u64 (*cbox_filter_mask)(int fields)) 796ed367e6cSBorislav Petkov { 797ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 798ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 799ed367e6cSBorislav Petkov int i, alloc = 0; 800ed367e6cSBorislav Petkov unsigned long flags; 801ed367e6cSBorislav Petkov u64 mask; 802ed367e6cSBorislav Petkov 803ed367e6cSBorislav Petkov if (reg1->idx == EXTRA_REG_NONE) 804ed367e6cSBorislav Petkov return NULL; 805ed367e6cSBorislav Petkov 806ed367e6cSBorislav Petkov raw_spin_lock_irqsave(&er->lock, flags); 807ed367e6cSBorislav Petkov for (i = 0; i < 5; i++) { 808ed367e6cSBorislav Petkov if (!(reg1->idx & (0x1 << i))) 809ed367e6cSBorislav Petkov continue; 810ed367e6cSBorislav Petkov if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) 811ed367e6cSBorislav Petkov continue; 812ed367e6cSBorislav Petkov 813ed367e6cSBorislav Petkov mask = cbox_filter_mask(0x1 << i); 814ed367e6cSBorislav Petkov if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) || 815ed367e6cSBorislav Petkov !((reg1->config ^ er->config) & mask)) { 816ed367e6cSBorislav Petkov atomic_add(1 << (i * 6), &er->ref); 817ed367e6cSBorislav Petkov er->config &= ~mask; 818ed367e6cSBorislav Petkov er->config |= reg1->config & mask; 819ed367e6cSBorislav Petkov alloc |= (0x1 << i); 820ed367e6cSBorislav Petkov } else { 821ed367e6cSBorislav Petkov break; 822ed367e6cSBorislav Petkov } 823ed367e6cSBorislav Petkov } 824ed367e6cSBorislav Petkov raw_spin_unlock_irqrestore(&er->lock, flags); 825ed367e6cSBorislav Petkov if (i < 5) 826ed367e6cSBorislav Petkov goto fail; 827ed367e6cSBorislav Petkov 828ed367e6cSBorislav Petkov if (!uncore_box_is_fake(box)) 829ed367e6cSBorislav Petkov reg1->alloc |= alloc; 830ed367e6cSBorislav Petkov 831ed367e6cSBorislav Petkov return NULL; 832ed367e6cSBorislav Petkov fail: 833ed367e6cSBorislav Petkov for (; i >= 0; i--) { 834ed367e6cSBorislav Petkov if (alloc & (0x1 << i)) 835ed367e6cSBorislav Petkov atomic_sub(1 << (i * 6), &er->ref); 836ed367e6cSBorislav Petkov } 837ed367e6cSBorislav Petkov return &uncore_constraint_empty; 838ed367e6cSBorislav Petkov } 839ed367e6cSBorislav Petkov 840ed367e6cSBorislav Petkov static u64 snbep_cbox_filter_mask(int fields) 841ed367e6cSBorislav Petkov { 842ed367e6cSBorislav Petkov u64 mask = 0; 843ed367e6cSBorislav Petkov 844ed367e6cSBorislav Petkov if (fields & 0x1) 845ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID; 846ed367e6cSBorislav Petkov if (fields & 0x2) 847ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID; 848ed367e6cSBorislav Petkov if (fields & 0x4) 849ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE; 850ed367e6cSBorislav Petkov if (fields & 0x8) 851ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC; 852ed367e6cSBorislav Petkov 853ed367e6cSBorislav Petkov return mask; 854ed367e6cSBorislav Petkov } 855ed367e6cSBorislav Petkov 856ed367e6cSBorislav Petkov static struct event_constraint * 857ed367e6cSBorislav Petkov snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 858ed367e6cSBorislav Petkov { 859ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask); 860ed367e6cSBorislav Petkov } 861ed367e6cSBorislav Petkov 862ed367e6cSBorislav Petkov static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 863ed367e6cSBorislav Petkov { 864ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 865ed367e6cSBorislav Petkov struct extra_reg *er; 866ed367e6cSBorislav Petkov int idx = 0; 867ed367e6cSBorislav Petkov 868ed367e6cSBorislav Petkov for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) { 869ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 870ed367e6cSBorislav Petkov continue; 871ed367e6cSBorislav Petkov idx |= er->idx; 872ed367e6cSBorislav Petkov } 873ed367e6cSBorislav Petkov 874ed367e6cSBorislav Petkov if (idx) { 875ed367e6cSBorislav Petkov reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + 876ed367e6cSBorislav Petkov SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 877ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx); 878ed367e6cSBorislav Petkov reg1->idx = idx; 879ed367e6cSBorislav Petkov } 880ed367e6cSBorislav Petkov return 0; 881ed367e6cSBorislav Petkov } 882ed367e6cSBorislav Petkov 883ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_cbox_ops = { 884ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 885ed367e6cSBorislav Petkov .hw_config = snbep_cbox_hw_config, 886ed367e6cSBorislav Petkov .get_constraint = snbep_cbox_get_constraint, 887ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 888ed367e6cSBorislav Petkov }; 889ed367e6cSBorislav Petkov 890ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_cbox = { 891ed367e6cSBorislav Petkov .name = "cbox", 892ed367e6cSBorislav Petkov .num_counters = 4, 893ed367e6cSBorislav Petkov .num_boxes = 8, 894ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 895ed367e6cSBorislav Petkov .event_ctl = SNBEP_C0_MSR_PMON_CTL0, 896ed367e6cSBorislav Petkov .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, 897ed367e6cSBorislav Petkov .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 898ed367e6cSBorislav Petkov .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, 899ed367e6cSBorislav Petkov .msr_offset = SNBEP_CBO_MSR_OFFSET, 900ed367e6cSBorislav Petkov .num_shared_regs = 1, 901ed367e6cSBorislav Petkov .constraints = snbep_uncore_cbox_constraints, 902ed367e6cSBorislav Petkov .ops = &snbep_uncore_cbox_ops, 903ed367e6cSBorislav Petkov .format_group = &snbep_uncore_cbox_format_group, 904ed367e6cSBorislav Petkov }; 905ed367e6cSBorislav Petkov 906ed367e6cSBorislav Petkov static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify) 907ed367e6cSBorislav Petkov { 908ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 909ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 910ed367e6cSBorislav Petkov u64 config = reg1->config; 911ed367e6cSBorislav Petkov 912ed367e6cSBorislav Petkov if (new_idx > reg1->idx) 913ed367e6cSBorislav Petkov config <<= 8 * (new_idx - reg1->idx); 914ed367e6cSBorislav Petkov else 915ed367e6cSBorislav Petkov config >>= 8 * (reg1->idx - new_idx); 916ed367e6cSBorislav Petkov 917ed367e6cSBorislav Petkov if (modify) { 918ed367e6cSBorislav Petkov hwc->config += new_idx - reg1->idx; 919ed367e6cSBorislav Petkov reg1->config = config; 920ed367e6cSBorislav Petkov reg1->idx = new_idx; 921ed367e6cSBorislav Petkov } 922ed367e6cSBorislav Petkov return config; 923ed367e6cSBorislav Petkov } 924ed367e6cSBorislav Petkov 925ed367e6cSBorislav Petkov static struct event_constraint * 926ed367e6cSBorislav Petkov snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 927ed367e6cSBorislav Petkov { 928ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 929ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 930ed367e6cSBorislav Petkov unsigned long flags; 931ed367e6cSBorislav Petkov int idx = reg1->idx; 932ed367e6cSBorislav Petkov u64 mask, config1 = reg1->config; 933ed367e6cSBorislav Petkov bool ok = false; 934ed367e6cSBorislav Petkov 935ed367e6cSBorislav Petkov if (reg1->idx == EXTRA_REG_NONE || 936ed367e6cSBorislav Petkov (!uncore_box_is_fake(box) && reg1->alloc)) 937ed367e6cSBorislav Petkov return NULL; 938ed367e6cSBorislav Petkov again: 939ed367e6cSBorislav Petkov mask = 0xffULL << (idx * 8); 940ed367e6cSBorislav Petkov raw_spin_lock_irqsave(&er->lock, flags); 941ed367e6cSBorislav Petkov if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) || 942ed367e6cSBorislav Petkov !((config1 ^ er->config) & mask)) { 943ed367e6cSBorislav Petkov atomic_add(1 << (idx * 8), &er->ref); 944ed367e6cSBorislav Petkov er->config &= ~mask; 945ed367e6cSBorislav Petkov er->config |= config1 & mask; 946ed367e6cSBorislav Petkov ok = true; 947ed367e6cSBorislav Petkov } 948ed367e6cSBorislav Petkov raw_spin_unlock_irqrestore(&er->lock, flags); 949ed367e6cSBorislav Petkov 950ed367e6cSBorislav Petkov if (!ok) { 951ed367e6cSBorislav Petkov idx = (idx + 1) % 4; 952ed367e6cSBorislav Petkov if (idx != reg1->idx) { 953ed367e6cSBorislav Petkov config1 = snbep_pcu_alter_er(event, idx, false); 954ed367e6cSBorislav Petkov goto again; 955ed367e6cSBorislav Petkov } 956ed367e6cSBorislav Petkov return &uncore_constraint_empty; 957ed367e6cSBorislav Petkov } 958ed367e6cSBorislav Petkov 959ed367e6cSBorislav Petkov if (!uncore_box_is_fake(box)) { 960ed367e6cSBorislav Petkov if (idx != reg1->idx) 961ed367e6cSBorislav Petkov snbep_pcu_alter_er(event, idx, true); 962ed367e6cSBorislav Petkov reg1->alloc = 1; 963ed367e6cSBorislav Petkov } 964ed367e6cSBorislav Petkov return NULL; 965ed367e6cSBorislav Petkov } 966ed367e6cSBorislav Petkov 967ed367e6cSBorislav Petkov static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event) 968ed367e6cSBorislav Petkov { 969ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 970ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 971ed367e6cSBorislav Petkov 972ed367e6cSBorislav Petkov if (uncore_box_is_fake(box) || !reg1->alloc) 973ed367e6cSBorislav Petkov return; 974ed367e6cSBorislav Petkov 975ed367e6cSBorislav Petkov atomic_sub(1 << (reg1->idx * 8), &er->ref); 976ed367e6cSBorislav Petkov reg1->alloc = 0; 977ed367e6cSBorislav Petkov } 978ed367e6cSBorislav Petkov 979ed367e6cSBorislav Petkov static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 980ed367e6cSBorislav Petkov { 981ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 982ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 983ed367e6cSBorislav Petkov int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 984ed367e6cSBorislav Petkov 985ed367e6cSBorislav Petkov if (ev_sel >= 0xb && ev_sel <= 0xe) { 986ed367e6cSBorislav Petkov reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; 987ed367e6cSBorislav Petkov reg1->idx = ev_sel - 0xb; 988ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); 989ed367e6cSBorislav Petkov } 990ed367e6cSBorislav Petkov return 0; 991ed367e6cSBorislav Petkov } 992ed367e6cSBorislav Petkov 993ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_pcu_ops = { 994ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 995ed367e6cSBorislav Petkov .hw_config = snbep_pcu_hw_config, 996ed367e6cSBorislav Petkov .get_constraint = snbep_pcu_get_constraint, 997ed367e6cSBorislav Petkov .put_constraint = snbep_pcu_put_constraint, 998ed367e6cSBorislav Petkov }; 999ed367e6cSBorislav Petkov 1000ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_pcu = { 1001ed367e6cSBorislav Petkov .name = "pcu", 1002ed367e6cSBorislav Petkov .num_counters = 4, 1003ed367e6cSBorislav Petkov .num_boxes = 1, 1004ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1005ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, 1006ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, 1007ed367e6cSBorislav Petkov .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 1008ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, 1009ed367e6cSBorislav Petkov .num_shared_regs = 1, 1010ed367e6cSBorislav Petkov .ops = &snbep_uncore_pcu_ops, 1011ed367e6cSBorislav Petkov .format_group = &snbep_uncore_pcu_format_group, 1012ed367e6cSBorislav Petkov }; 1013ed367e6cSBorislav Petkov 1014ed367e6cSBorislav Petkov static struct intel_uncore_type *snbep_msr_uncores[] = { 1015ed367e6cSBorislav Petkov &snbep_uncore_ubox, 1016ed367e6cSBorislav Petkov &snbep_uncore_cbox, 1017ed367e6cSBorislav Petkov &snbep_uncore_pcu, 1018ed367e6cSBorislav Petkov NULL, 1019ed367e6cSBorislav Petkov }; 1020ed367e6cSBorislav Petkov 1021ed367e6cSBorislav Petkov void snbep_uncore_cpu_init(void) 1022ed367e6cSBorislav Petkov { 1023ed367e6cSBorislav Petkov if (snbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 1024ed367e6cSBorislav Petkov snbep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 1025ed367e6cSBorislav Petkov uncore_msr_uncores = snbep_msr_uncores; 1026ed367e6cSBorislav Petkov } 1027ed367e6cSBorislav Petkov 1028ed367e6cSBorislav Petkov enum { 1029ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER, 1030ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER, 1031ed367e6cSBorislav Petkov HSWEP_PCI_PCU_3, 1032ed367e6cSBorislav Petkov }; 1033ed367e6cSBorislav Petkov 1034ed367e6cSBorislav Petkov static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1035ed367e6cSBorislav Petkov { 1036ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1037ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1038ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 1039ed367e6cSBorislav Petkov 1040ed367e6cSBorislav Petkov if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) { 1041ed367e6cSBorislav Petkov reg1->idx = 0; 1042ed367e6cSBorislav Petkov reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0; 1043ed367e6cSBorislav Petkov reg1->config = event->attr.config1; 1044ed367e6cSBorislav Petkov reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0; 1045ed367e6cSBorislav Petkov reg2->config = event->attr.config2; 1046ed367e6cSBorislav Petkov } 1047ed367e6cSBorislav Petkov return 0; 1048ed367e6cSBorislav Petkov } 1049ed367e6cSBorislav Petkov 1050ed367e6cSBorislav Petkov static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1051ed367e6cSBorislav Petkov { 1052ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1053ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1054ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1055ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 1056ed367e6cSBorislav Petkov 1057ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) { 1058ed367e6cSBorislav Petkov int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER; 1059cf6d445fSThomas Gleixner int pkg = topology_phys_to_logical_pkg(box->pci_phys_id); 1060cf6d445fSThomas Gleixner struct pci_dev *filter_pdev = uncore_extra_pci_dev[pkg].dev[idx]; 1061cf6d445fSThomas Gleixner 1062ed367e6cSBorislav Petkov if (filter_pdev) { 1063ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg1->reg, 1064ed367e6cSBorislav Petkov (u32)reg1->config); 1065ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg1->reg + 4, 1066ed367e6cSBorislav Petkov (u32)(reg1->config >> 32)); 1067ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg2->reg, 1068ed367e6cSBorislav Petkov (u32)reg2->config); 1069ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg2->reg + 4, 1070ed367e6cSBorislav Petkov (u32)(reg2->config >> 32)); 1071ed367e6cSBorislav Petkov } 1072ed367e6cSBorislav Petkov } 1073ed367e6cSBorislav Petkov 1074ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1075ed367e6cSBorislav Petkov } 1076ed367e6cSBorislav Petkov 1077ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_qpi_ops = { 1078ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_OPS_COMMON_INIT(), 1079ed367e6cSBorislav Petkov .enable_event = snbep_qpi_enable_event, 1080ed367e6cSBorislav Petkov .hw_config = snbep_qpi_hw_config, 1081ed367e6cSBorislav Petkov .get_constraint = uncore_get_constraint, 1082ed367e6cSBorislav Petkov .put_constraint = uncore_put_constraint, 1083ed367e6cSBorislav Petkov }; 1084ed367e6cSBorislav Petkov 1085ed367e6cSBorislav Petkov #define SNBEP_UNCORE_PCI_COMMON_INIT() \ 1086ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, \ 1087ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, \ 1088ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \ 1089ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ 1090ed367e6cSBorislav Petkov .ops = &snbep_uncore_pci_ops, \ 1091ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group 1092ed367e6cSBorislav Petkov 1093ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_ha = { 1094ed367e6cSBorislav Petkov .name = "ha", 1095ed367e6cSBorislav Petkov .num_counters = 4, 1096ed367e6cSBorislav Petkov .num_boxes = 1, 1097ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1098ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1099ed367e6cSBorislav Petkov }; 1100ed367e6cSBorislav Petkov 1101ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_imc = { 1102ed367e6cSBorislav Petkov .name = "imc", 1103ed367e6cSBorislav Petkov .num_counters = 4, 1104ed367e6cSBorislav Petkov .num_boxes = 4, 1105ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1106ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1107ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 1108ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 1109ed367e6cSBorislav Petkov .event_descs = snbep_uncore_imc_events, 1110ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1111ed367e6cSBorislav Petkov }; 1112ed367e6cSBorislav Petkov 1113ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_qpi = { 1114ed367e6cSBorislav Petkov .name = "qpi", 1115ed367e6cSBorislav Petkov .num_counters = 4, 1116ed367e6cSBorislav Petkov .num_boxes = 2, 1117ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1118ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 1119ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 1120ed367e6cSBorislav Petkov .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 1121ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1122ed367e6cSBorislav Petkov .num_shared_regs = 1, 1123ed367e6cSBorislav Petkov .ops = &snbep_uncore_qpi_ops, 1124ed367e6cSBorislav Petkov .event_descs = snbep_uncore_qpi_events, 1125ed367e6cSBorislav Petkov .format_group = &snbep_uncore_qpi_format_group, 1126ed367e6cSBorislav Petkov }; 1127ed367e6cSBorislav Petkov 1128ed367e6cSBorislav Petkov 1129ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_r2pcie = { 1130ed367e6cSBorislav Petkov .name = "r2pcie", 1131ed367e6cSBorislav Petkov .num_counters = 4, 1132ed367e6cSBorislav Petkov .num_boxes = 1, 1133ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1134ed367e6cSBorislav Petkov .constraints = snbep_uncore_r2pcie_constraints, 1135ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1136ed367e6cSBorislav Petkov }; 1137ed367e6cSBorislav Petkov 1138ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_r3qpi = { 1139ed367e6cSBorislav Petkov .name = "r3qpi", 1140ed367e6cSBorislav Petkov .num_counters = 3, 1141ed367e6cSBorislav Petkov .num_boxes = 2, 1142ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1143ed367e6cSBorislav Petkov .constraints = snbep_uncore_r3qpi_constraints, 1144ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1145ed367e6cSBorislav Petkov }; 1146ed367e6cSBorislav Petkov 1147ed367e6cSBorislav Petkov enum { 1148ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_HA, 1149ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_IMC, 1150ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_QPI, 1151ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_R2PCIE, 1152ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_R3QPI, 1153ed367e6cSBorislav Petkov }; 1154ed367e6cSBorislav Petkov 1155ed367e6cSBorislav Petkov static struct intel_uncore_type *snbep_pci_uncores[] = { 1156ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha, 1157ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc, 1158ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi, 1159ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie, 1160ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi, 1161ed367e6cSBorislav Petkov NULL, 1162ed367e6cSBorislav Petkov }; 1163ed367e6cSBorislav Petkov 1164ed367e6cSBorislav Petkov static const struct pci_device_id snbep_uncore_pci_ids[] = { 1165ed367e6cSBorislav Petkov { /* Home Agent */ 1166ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA), 1167ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0), 1168ed367e6cSBorislav Petkov }, 1169ed367e6cSBorislav Petkov { /* MC Channel 0 */ 1170ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0), 1171ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0), 1172ed367e6cSBorislav Petkov }, 1173ed367e6cSBorislav Petkov { /* MC Channel 1 */ 1174ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1), 1175ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1), 1176ed367e6cSBorislav Petkov }, 1177ed367e6cSBorislav Petkov { /* MC Channel 2 */ 1178ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2), 1179ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2), 1180ed367e6cSBorislav Petkov }, 1181ed367e6cSBorislav Petkov { /* MC Channel 3 */ 1182ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3), 1183ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3), 1184ed367e6cSBorislav Petkov }, 1185ed367e6cSBorislav Petkov { /* QPI Port 0 */ 1186ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0), 1187ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0), 1188ed367e6cSBorislav Petkov }, 1189ed367e6cSBorislav Petkov { /* QPI Port 1 */ 1190ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1), 1191ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1), 1192ed367e6cSBorislav Petkov }, 1193ed367e6cSBorislav Petkov { /* R2PCIe */ 1194ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE), 1195ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0), 1196ed367e6cSBorislav Petkov }, 1197ed367e6cSBorislav Petkov { /* R3QPI Link 0 */ 1198ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0), 1199ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0), 1200ed367e6cSBorislav Petkov }, 1201ed367e6cSBorislav Petkov { /* R3QPI Link 1 */ 1202ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1), 1203ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1), 1204ed367e6cSBorislav Petkov }, 1205ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1206ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86), 1207ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1208ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER), 1209ed367e6cSBorislav Petkov }, 1210ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1211ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96), 1212ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1213ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER), 1214ed367e6cSBorislav Petkov }, 1215ed367e6cSBorislav Petkov { /* end: all zeroes */ } 1216ed367e6cSBorislav Petkov }; 1217ed367e6cSBorislav Petkov 1218ed367e6cSBorislav Petkov static struct pci_driver snbep_uncore_pci_driver = { 1219ed367e6cSBorislav Petkov .name = "snbep_uncore", 1220ed367e6cSBorislav Petkov .id_table = snbep_uncore_pci_ids, 1221ed367e6cSBorislav Petkov }; 1222ed367e6cSBorislav Petkov 1223ed367e6cSBorislav Petkov /* 1224ed367e6cSBorislav Petkov * build pci bus to socket mapping 1225ed367e6cSBorislav Petkov */ 122668ce4a0dSKan Liang static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool reverse) 1227ed367e6cSBorislav Petkov { 1228ed367e6cSBorislav Petkov struct pci_dev *ubox_dev = NULL; 1229ed367e6cSBorislav Petkov int i, bus, nodeid, segment; 1230ed367e6cSBorislav Petkov struct pci2phy_map *map; 1231ed367e6cSBorislav Petkov int err = 0; 1232ed367e6cSBorislav Petkov u32 config = 0; 1233ed367e6cSBorislav Petkov 1234ed367e6cSBorislav Petkov while (1) { 1235ed367e6cSBorislav Petkov /* find the UBOX device */ 1236ed367e6cSBorislav Petkov ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev); 1237ed367e6cSBorislav Petkov if (!ubox_dev) 1238ed367e6cSBorislav Petkov break; 1239ed367e6cSBorislav Petkov bus = ubox_dev->bus->number; 1240ed367e6cSBorislav Petkov /* get the Node ID of the local register */ 124168ce4a0dSKan Liang err = pci_read_config_dword(ubox_dev, nodeid_loc, &config); 1242ed367e6cSBorislav Petkov if (err) 1243ed367e6cSBorislav Petkov break; 1244ed367e6cSBorislav Petkov nodeid = config; 1245ed367e6cSBorislav Petkov /* get the Node ID mapping */ 124668ce4a0dSKan Liang err = pci_read_config_dword(ubox_dev, idmap_loc, &config); 1247ed367e6cSBorislav Petkov if (err) 1248ed367e6cSBorislav Petkov break; 1249ed367e6cSBorislav Petkov 1250ed367e6cSBorislav Petkov segment = pci_domain_nr(ubox_dev->bus); 1251ed367e6cSBorislav Petkov raw_spin_lock(&pci2phy_map_lock); 1252ed367e6cSBorislav Petkov map = __find_pci2phy_map(segment); 1253ed367e6cSBorislav Petkov if (!map) { 1254ed367e6cSBorislav Petkov raw_spin_unlock(&pci2phy_map_lock); 1255ed367e6cSBorislav Petkov err = -ENOMEM; 1256ed367e6cSBorislav Petkov break; 1257ed367e6cSBorislav Petkov } 1258ed367e6cSBorislav Petkov 1259ed367e6cSBorislav Petkov /* 1260ed367e6cSBorislav Petkov * every three bits in the Node ID mapping register maps 1261ed367e6cSBorislav Petkov * to a particular node. 1262ed367e6cSBorislav Petkov */ 1263ed367e6cSBorislav Petkov for (i = 0; i < 8; i++) { 1264ed367e6cSBorislav Petkov if (nodeid == ((config >> (3 * i)) & 0x7)) { 1265ed367e6cSBorislav Petkov map->pbus_to_physid[bus] = i; 1266ed367e6cSBorislav Petkov break; 1267ed367e6cSBorislav Petkov } 1268ed367e6cSBorislav Petkov } 1269ed367e6cSBorislav Petkov raw_spin_unlock(&pci2phy_map_lock); 1270ed367e6cSBorislav Petkov } 1271ed367e6cSBorislav Petkov 1272ed367e6cSBorislav Petkov if (!err) { 1273ed367e6cSBorislav Petkov /* 1274ed367e6cSBorislav Petkov * For PCI bus with no UBOX device, find the next bus 1275ed367e6cSBorislav Petkov * that has UBOX device and use its mapping. 1276ed367e6cSBorislav Petkov */ 1277ed367e6cSBorislav Petkov raw_spin_lock(&pci2phy_map_lock); 1278ed367e6cSBorislav Petkov list_for_each_entry(map, &pci2phy_map_head, list) { 1279ed367e6cSBorislav Petkov i = -1; 128068ce4a0dSKan Liang if (reverse) { 1281ed367e6cSBorislav Petkov for (bus = 255; bus >= 0; bus--) { 1282ed367e6cSBorislav Petkov if (map->pbus_to_physid[bus] >= 0) 1283ed367e6cSBorislav Petkov i = map->pbus_to_physid[bus]; 1284ed367e6cSBorislav Petkov else 1285ed367e6cSBorislav Petkov map->pbus_to_physid[bus] = i; 1286ed367e6cSBorislav Petkov } 128768ce4a0dSKan Liang } else { 128868ce4a0dSKan Liang for (bus = 0; bus <= 255; bus++) { 128968ce4a0dSKan Liang if (map->pbus_to_physid[bus] >= 0) 129068ce4a0dSKan Liang i = map->pbus_to_physid[bus]; 129168ce4a0dSKan Liang else 129268ce4a0dSKan Liang map->pbus_to_physid[bus] = i; 129368ce4a0dSKan Liang } 129468ce4a0dSKan Liang } 1295ed367e6cSBorislav Petkov } 1296ed367e6cSBorislav Petkov raw_spin_unlock(&pci2phy_map_lock); 1297ed367e6cSBorislav Petkov } 1298ed367e6cSBorislav Petkov 1299ed367e6cSBorislav Petkov pci_dev_put(ubox_dev); 1300ed367e6cSBorislav Petkov 1301ed367e6cSBorislav Petkov return err ? pcibios_err_to_errno(err) : 0; 1302ed367e6cSBorislav Petkov } 1303ed367e6cSBorislav Petkov 1304ed367e6cSBorislav Petkov int snbep_uncore_pci_init(void) 1305ed367e6cSBorislav Petkov { 130668ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x3ce0, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 1307ed367e6cSBorislav Petkov if (ret) 1308ed367e6cSBorislav Petkov return ret; 1309ed367e6cSBorislav Petkov uncore_pci_uncores = snbep_pci_uncores; 1310ed367e6cSBorislav Petkov uncore_pci_driver = &snbep_uncore_pci_driver; 1311ed367e6cSBorislav Petkov return 0; 1312ed367e6cSBorislav Petkov } 1313ed367e6cSBorislav Petkov /* end of Sandy Bridge-EP uncore support */ 1314ed367e6cSBorislav Petkov 1315ed367e6cSBorislav Petkov /* IvyTown uncore support */ 1316ed367e6cSBorislav Petkov static void ivbep_uncore_msr_init_box(struct intel_uncore_box *box) 1317ed367e6cSBorislav Petkov { 1318ed367e6cSBorislav Petkov unsigned msr = uncore_msr_box_ctl(box); 1319ed367e6cSBorislav Petkov if (msr) 1320ed367e6cSBorislav Petkov wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT); 1321ed367e6cSBorislav Petkov } 1322ed367e6cSBorislav Petkov 1323ed367e6cSBorislav Petkov static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box) 1324ed367e6cSBorislav Petkov { 1325ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1326ed367e6cSBorislav Petkov 1327ed367e6cSBorislav Petkov pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 1328ed367e6cSBorislav Petkov } 1329ed367e6cSBorislav Petkov 1330ed367e6cSBorislav Petkov #define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 1331ed367e6cSBorislav Petkov .init_box = ivbep_uncore_msr_init_box, \ 1332ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, \ 1333ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, \ 1334ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, \ 1335ed367e6cSBorislav Petkov .enable_event = snbep_uncore_msr_enable_event, \ 1336ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter 1337ed367e6cSBorislav Petkov 1338ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_msr_ops = { 1339ed367e6cSBorislav Petkov IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1340ed367e6cSBorislav Petkov }; 1341ed367e6cSBorislav Petkov 1342ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_pci_ops = { 1343ed367e6cSBorislav Petkov .init_box = ivbep_uncore_pci_init_box, 1344ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 1345ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 1346ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, 1347ed367e6cSBorislav Petkov .enable_event = snbep_uncore_pci_enable_event, 1348ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter, 1349ed367e6cSBorislav Petkov }; 1350ed367e6cSBorislav Petkov 1351ed367e6cSBorislav Petkov #define IVBEP_UNCORE_PCI_COMMON_INIT() \ 1352ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, \ 1353ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, \ 1354ed367e6cSBorislav Petkov .event_mask = IVBEP_PMON_RAW_EVENT_MASK, \ 1355ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ 1356ed367e6cSBorislav Petkov .ops = &ivbep_uncore_pci_ops, \ 1357ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_format_group 1358ed367e6cSBorislav Petkov 1359ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_formats_attr[] = { 1360ed367e6cSBorislav Petkov &format_attr_event.attr, 1361ed367e6cSBorislav Petkov &format_attr_umask.attr, 1362ed367e6cSBorislav Petkov &format_attr_edge.attr, 1363ed367e6cSBorislav Petkov &format_attr_inv.attr, 1364ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1365ed367e6cSBorislav Petkov NULL, 1366ed367e6cSBorislav Petkov }; 1367ed367e6cSBorislav Petkov 1368ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_ubox_formats_attr[] = { 1369ed367e6cSBorislav Petkov &format_attr_event.attr, 1370ed367e6cSBorislav Petkov &format_attr_umask.attr, 1371ed367e6cSBorislav Petkov &format_attr_edge.attr, 1372ed367e6cSBorislav Petkov &format_attr_inv.attr, 1373ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 1374ed367e6cSBorislav Petkov NULL, 1375ed367e6cSBorislav Petkov }; 1376ed367e6cSBorislav Petkov 1377ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_cbox_formats_attr[] = { 1378ed367e6cSBorislav Petkov &format_attr_event.attr, 1379ed367e6cSBorislav Petkov &format_attr_umask.attr, 1380ed367e6cSBorislav Petkov &format_attr_edge.attr, 1381ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 1382ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1383ed367e6cSBorislav Petkov &format_attr_filter_tid.attr, 1384ed367e6cSBorislav Petkov &format_attr_filter_link.attr, 1385ed367e6cSBorislav Petkov &format_attr_filter_state2.attr, 1386ed367e6cSBorislav Petkov &format_attr_filter_nid2.attr, 1387ed367e6cSBorislav Petkov &format_attr_filter_opc2.attr, 1388ed367e6cSBorislav Petkov &format_attr_filter_nc.attr, 1389ed367e6cSBorislav Petkov &format_attr_filter_c6.attr, 1390ed367e6cSBorislav Petkov &format_attr_filter_isoc.attr, 1391ed367e6cSBorislav Petkov NULL, 1392ed367e6cSBorislav Petkov }; 1393ed367e6cSBorislav Petkov 1394ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_pcu_formats_attr[] = { 1395cb225252SKan Liang &format_attr_event.attr, 1396ed367e6cSBorislav Petkov &format_attr_occ_sel.attr, 1397ed367e6cSBorislav Petkov &format_attr_edge.attr, 1398ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 1399ed367e6cSBorislav Petkov &format_attr_occ_invert.attr, 1400ed367e6cSBorislav Petkov &format_attr_occ_edge.attr, 1401ed367e6cSBorislav Petkov &format_attr_filter_band0.attr, 1402ed367e6cSBorislav Petkov &format_attr_filter_band1.attr, 1403ed367e6cSBorislav Petkov &format_attr_filter_band2.attr, 1404ed367e6cSBorislav Petkov &format_attr_filter_band3.attr, 1405ed367e6cSBorislav Petkov NULL, 1406ed367e6cSBorislav Petkov }; 1407ed367e6cSBorislav Petkov 1408ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_qpi_formats_attr[] = { 1409ed367e6cSBorislav Petkov &format_attr_event_ext.attr, 1410ed367e6cSBorislav Petkov &format_attr_umask.attr, 1411ed367e6cSBorislav Petkov &format_attr_edge.attr, 1412ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1413ed367e6cSBorislav Petkov &format_attr_match_rds.attr, 1414ed367e6cSBorislav Petkov &format_attr_match_rnid30.attr, 1415ed367e6cSBorislav Petkov &format_attr_match_rnid4.attr, 1416ed367e6cSBorislav Petkov &format_attr_match_dnid.attr, 1417ed367e6cSBorislav Petkov &format_attr_match_mc.attr, 1418ed367e6cSBorislav Petkov &format_attr_match_opc.attr, 1419ed367e6cSBorislav Petkov &format_attr_match_vnw.attr, 1420ed367e6cSBorislav Petkov &format_attr_match0.attr, 1421ed367e6cSBorislav Petkov &format_attr_match1.attr, 1422ed367e6cSBorislav Petkov &format_attr_mask_rds.attr, 1423ed367e6cSBorislav Petkov &format_attr_mask_rnid30.attr, 1424ed367e6cSBorislav Petkov &format_attr_mask_rnid4.attr, 1425ed367e6cSBorislav Petkov &format_attr_mask_dnid.attr, 1426ed367e6cSBorislav Petkov &format_attr_mask_mc.attr, 1427ed367e6cSBorislav Petkov &format_attr_mask_opc.attr, 1428ed367e6cSBorislav Petkov &format_attr_mask_vnw.attr, 1429ed367e6cSBorislav Petkov &format_attr_mask0.attr, 1430ed367e6cSBorislav Petkov &format_attr_mask1.attr, 1431ed367e6cSBorislav Petkov NULL, 1432ed367e6cSBorislav Petkov }; 1433ed367e6cSBorislav Petkov 1434ed367e6cSBorislav Petkov static struct attribute_group ivbep_uncore_format_group = { 1435ed367e6cSBorislav Petkov .name = "format", 1436ed367e6cSBorislav Petkov .attrs = ivbep_uncore_formats_attr, 1437ed367e6cSBorislav Petkov }; 1438ed367e6cSBorislav Petkov 1439ed367e6cSBorislav Petkov static struct attribute_group ivbep_uncore_ubox_format_group = { 1440ed367e6cSBorislav Petkov .name = "format", 1441ed367e6cSBorislav Petkov .attrs = ivbep_uncore_ubox_formats_attr, 1442ed367e6cSBorislav Petkov }; 1443ed367e6cSBorislav Petkov 1444ed367e6cSBorislav Petkov static struct attribute_group ivbep_uncore_cbox_format_group = { 1445ed367e6cSBorislav Petkov .name = "format", 1446ed367e6cSBorislav Petkov .attrs = ivbep_uncore_cbox_formats_attr, 1447ed367e6cSBorislav Petkov }; 1448ed367e6cSBorislav Petkov 1449ed367e6cSBorislav Petkov static struct attribute_group ivbep_uncore_pcu_format_group = { 1450ed367e6cSBorislav Petkov .name = "format", 1451ed367e6cSBorislav Petkov .attrs = ivbep_uncore_pcu_formats_attr, 1452ed367e6cSBorislav Petkov }; 1453ed367e6cSBorislav Petkov 1454ed367e6cSBorislav Petkov static struct attribute_group ivbep_uncore_qpi_format_group = { 1455ed367e6cSBorislav Petkov .name = "format", 1456ed367e6cSBorislav Petkov .attrs = ivbep_uncore_qpi_formats_attr, 1457ed367e6cSBorislav Petkov }; 1458ed367e6cSBorislav Petkov 1459ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_ubox = { 1460ed367e6cSBorislav Petkov .name = "ubox", 1461ed367e6cSBorislav Petkov .num_counters = 2, 1462ed367e6cSBorislav Petkov .num_boxes = 1, 1463ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1464ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1465ed367e6cSBorislav Petkov .perf_ctr = SNBEP_U_MSR_PMON_CTR0, 1466ed367e6cSBorislav Petkov .event_ctl = SNBEP_U_MSR_PMON_CTL0, 1467ed367e6cSBorislav Petkov .event_mask = IVBEP_U_MSR_PMON_RAW_EVENT_MASK, 1468ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, 1469ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, 1470ed367e6cSBorislav Petkov .ops = &ivbep_uncore_msr_ops, 1471ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_ubox_format_group, 1472ed367e6cSBorislav Petkov }; 1473ed367e6cSBorislav Petkov 1474ed367e6cSBorislav Petkov static struct extra_reg ivbep_uncore_cbox_extra_regs[] = { 1475ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 1476ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 1477ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2), 1478ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 1479ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc), 1480ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc), 1481ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 1482ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc), 1483ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 1484ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc), 1485ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 1486ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc), 1487ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10), 1488ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10), 1489ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10), 1490ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10), 1491ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18), 1492ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18), 1493ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8), 1494ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8), 1495ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8), 1496ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8), 1497ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10), 1498ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10), 1499ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10), 1500ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10), 1501ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10), 1502ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10), 1503ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18), 1504ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18), 1505ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8), 1506ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8), 1507ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8), 1508ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8), 1509ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10), 1510ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10), 1511ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8), 1512ed367e6cSBorislav Petkov EVENT_EXTRA_END 1513ed367e6cSBorislav Petkov }; 1514ed367e6cSBorislav Petkov 1515ed367e6cSBorislav Petkov static u64 ivbep_cbox_filter_mask(int fields) 1516ed367e6cSBorislav Petkov { 1517ed367e6cSBorislav Petkov u64 mask = 0; 1518ed367e6cSBorislav Petkov 1519ed367e6cSBorislav Petkov if (fields & 0x1) 1520ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_TID; 1521ed367e6cSBorislav Petkov if (fields & 0x2) 1522ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK; 1523ed367e6cSBorislav Petkov if (fields & 0x4) 1524ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE; 1525ed367e6cSBorislav Petkov if (fields & 0x8) 1526ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NID; 1527ed367e6cSBorislav Petkov if (fields & 0x10) { 1528ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC; 1529ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NC; 1530ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_C6; 1531ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC; 1532ed367e6cSBorislav Petkov } 1533ed367e6cSBorislav Petkov 1534ed367e6cSBorislav Petkov return mask; 1535ed367e6cSBorislav Petkov } 1536ed367e6cSBorislav Petkov 1537ed367e6cSBorislav Petkov static struct event_constraint * 1538ed367e6cSBorislav Petkov ivbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 1539ed367e6cSBorislav Petkov { 1540ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, ivbep_cbox_filter_mask); 1541ed367e6cSBorislav Petkov } 1542ed367e6cSBorislav Petkov 1543ed367e6cSBorislav Petkov static int ivbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1544ed367e6cSBorislav Petkov { 1545ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1546ed367e6cSBorislav Petkov struct extra_reg *er; 1547ed367e6cSBorislav Petkov int idx = 0; 1548ed367e6cSBorislav Petkov 1549ed367e6cSBorislav Petkov for (er = ivbep_uncore_cbox_extra_regs; er->msr; er++) { 1550ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 1551ed367e6cSBorislav Petkov continue; 1552ed367e6cSBorislav Petkov idx |= er->idx; 1553ed367e6cSBorislav Petkov } 1554ed367e6cSBorislav Petkov 1555ed367e6cSBorislav Petkov if (idx) { 1556ed367e6cSBorislav Petkov reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + 1557ed367e6cSBorislav Petkov SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 1558ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx); 1559ed367e6cSBorislav Petkov reg1->idx = idx; 1560ed367e6cSBorislav Petkov } 1561ed367e6cSBorislav Petkov return 0; 1562ed367e6cSBorislav Petkov } 1563ed367e6cSBorislav Petkov 1564ed367e6cSBorislav Petkov static void ivbep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1565ed367e6cSBorislav Petkov { 1566ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1567ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1568ed367e6cSBorislav Petkov 1569ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) { 1570ed367e6cSBorislav Petkov u64 filter = uncore_shared_reg_config(box, 0); 1571ed367e6cSBorislav Petkov wrmsrl(reg1->reg, filter & 0xffffffff); 1572ed367e6cSBorislav Petkov wrmsrl(reg1->reg + 6, filter >> 32); 1573ed367e6cSBorislav Petkov } 1574ed367e6cSBorislav Petkov 1575ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1576ed367e6cSBorislav Petkov } 1577ed367e6cSBorislav Petkov 1578ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_cbox_ops = { 1579ed367e6cSBorislav Petkov .init_box = ivbep_uncore_msr_init_box, 1580ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, 1581ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, 1582ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, 1583ed367e6cSBorislav Petkov .enable_event = ivbep_cbox_enable_event, 1584ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter, 1585ed367e6cSBorislav Petkov .hw_config = ivbep_cbox_hw_config, 1586ed367e6cSBorislav Petkov .get_constraint = ivbep_cbox_get_constraint, 1587ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 1588ed367e6cSBorislav Petkov }; 1589ed367e6cSBorislav Petkov 1590ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_cbox = { 1591ed367e6cSBorislav Petkov .name = "cbox", 1592ed367e6cSBorislav Petkov .num_counters = 4, 1593ed367e6cSBorislav Petkov .num_boxes = 15, 1594ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1595ed367e6cSBorislav Petkov .event_ctl = SNBEP_C0_MSR_PMON_CTL0, 1596ed367e6cSBorislav Petkov .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, 1597ed367e6cSBorislav Petkov .event_mask = IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 1598ed367e6cSBorislav Petkov .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, 1599ed367e6cSBorislav Petkov .msr_offset = SNBEP_CBO_MSR_OFFSET, 1600ed367e6cSBorislav Petkov .num_shared_regs = 1, 1601ed367e6cSBorislav Petkov .constraints = snbep_uncore_cbox_constraints, 1602ed367e6cSBorislav Petkov .ops = &ivbep_uncore_cbox_ops, 1603ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_cbox_format_group, 1604ed367e6cSBorislav Petkov }; 1605ed367e6cSBorislav Petkov 1606ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_pcu_ops = { 1607ed367e6cSBorislav Petkov IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1608ed367e6cSBorislav Petkov .hw_config = snbep_pcu_hw_config, 1609ed367e6cSBorislav Petkov .get_constraint = snbep_pcu_get_constraint, 1610ed367e6cSBorislav Petkov .put_constraint = snbep_pcu_put_constraint, 1611ed367e6cSBorislav Petkov }; 1612ed367e6cSBorislav Petkov 1613ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_pcu = { 1614ed367e6cSBorislav Petkov .name = "pcu", 1615ed367e6cSBorislav Petkov .num_counters = 4, 1616ed367e6cSBorislav Petkov .num_boxes = 1, 1617ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1618ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, 1619ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, 1620ed367e6cSBorislav Petkov .event_mask = IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 1621ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, 1622ed367e6cSBorislav Petkov .num_shared_regs = 1, 1623ed367e6cSBorislav Petkov .ops = &ivbep_uncore_pcu_ops, 1624ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_pcu_format_group, 1625ed367e6cSBorislav Petkov }; 1626ed367e6cSBorislav Petkov 1627ed367e6cSBorislav Petkov static struct intel_uncore_type *ivbep_msr_uncores[] = { 1628ed367e6cSBorislav Petkov &ivbep_uncore_ubox, 1629ed367e6cSBorislav Petkov &ivbep_uncore_cbox, 1630ed367e6cSBorislav Petkov &ivbep_uncore_pcu, 1631ed367e6cSBorislav Petkov NULL, 1632ed367e6cSBorislav Petkov }; 1633ed367e6cSBorislav Petkov 1634ed367e6cSBorislav Petkov void ivbep_uncore_cpu_init(void) 1635ed367e6cSBorislav Petkov { 1636ed367e6cSBorislav Petkov if (ivbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 1637ed367e6cSBorislav Petkov ivbep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 1638ed367e6cSBorislav Petkov uncore_msr_uncores = ivbep_msr_uncores; 1639ed367e6cSBorislav Petkov } 1640ed367e6cSBorislav Petkov 1641ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_ha = { 1642ed367e6cSBorislav Petkov .name = "ha", 1643ed367e6cSBorislav Petkov .num_counters = 4, 1644ed367e6cSBorislav Petkov .num_boxes = 2, 1645ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1646ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1647ed367e6cSBorislav Petkov }; 1648ed367e6cSBorislav Petkov 1649ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_imc = { 1650ed367e6cSBorislav Petkov .name = "imc", 1651ed367e6cSBorislav Petkov .num_counters = 4, 1652ed367e6cSBorislav Petkov .num_boxes = 8, 1653ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1654ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1655ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 1656ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 1657ed367e6cSBorislav Petkov .event_descs = snbep_uncore_imc_events, 1658ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1659ed367e6cSBorislav Petkov }; 1660ed367e6cSBorislav Petkov 1661ed367e6cSBorislav Petkov /* registers in IRP boxes are not properly aligned */ 1662ed367e6cSBorislav Petkov static unsigned ivbep_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4}; 1663ed367e6cSBorislav Petkov static unsigned ivbep_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0}; 1664ed367e6cSBorislav Petkov 1665ed367e6cSBorislav Petkov static void ivbep_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1666ed367e6cSBorislav Petkov { 1667ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1668ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1669ed367e6cSBorislav Petkov 1670ed367e6cSBorislav Petkov pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], 1671ed367e6cSBorislav Petkov hwc->config | SNBEP_PMON_CTL_EN); 1672ed367e6cSBorislav Petkov } 1673ed367e6cSBorislav Petkov 1674ed367e6cSBorislav Petkov static void ivbep_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event) 1675ed367e6cSBorislav Petkov { 1676ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1677ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1678ed367e6cSBorislav Petkov 1679ed367e6cSBorislav Petkov pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], hwc->config); 1680ed367e6cSBorislav Petkov } 1681ed367e6cSBorislav Petkov 1682ed367e6cSBorislav Petkov static u64 ivbep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) 1683ed367e6cSBorislav Petkov { 1684ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1685ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1686ed367e6cSBorislav Petkov u64 count = 0; 1687ed367e6cSBorislav Petkov 1688ed367e6cSBorislav Petkov pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx], (u32 *)&count); 1689ed367e6cSBorislav Petkov pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1); 1690ed367e6cSBorislav Petkov 1691ed367e6cSBorislav Petkov return count; 1692ed367e6cSBorislav Petkov } 1693ed367e6cSBorislav Petkov 1694ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_irp_ops = { 1695ed367e6cSBorislav Petkov .init_box = ivbep_uncore_pci_init_box, 1696ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 1697ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 1698ed367e6cSBorislav Petkov .disable_event = ivbep_uncore_irp_disable_event, 1699ed367e6cSBorislav Petkov .enable_event = ivbep_uncore_irp_enable_event, 1700ed367e6cSBorislav Petkov .read_counter = ivbep_uncore_irp_read_counter, 1701ed367e6cSBorislav Petkov }; 1702ed367e6cSBorislav Petkov 1703ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_irp = { 1704ed367e6cSBorislav Petkov .name = "irp", 1705ed367e6cSBorislav Petkov .num_counters = 4, 1706ed367e6cSBorislav Petkov .num_boxes = 1, 1707ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1708ed367e6cSBorislav Petkov .event_mask = IVBEP_PMON_RAW_EVENT_MASK, 1709ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1710ed367e6cSBorislav Petkov .ops = &ivbep_uncore_irp_ops, 1711ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_format_group, 1712ed367e6cSBorislav Petkov }; 1713ed367e6cSBorislav Petkov 1714ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_qpi_ops = { 1715ed367e6cSBorislav Petkov .init_box = ivbep_uncore_pci_init_box, 1716ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 1717ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 1718ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, 1719ed367e6cSBorislav Petkov .enable_event = snbep_qpi_enable_event, 1720ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter, 1721ed367e6cSBorislav Petkov .hw_config = snbep_qpi_hw_config, 1722ed367e6cSBorislav Petkov .get_constraint = uncore_get_constraint, 1723ed367e6cSBorislav Petkov .put_constraint = uncore_put_constraint, 1724ed367e6cSBorislav Petkov }; 1725ed367e6cSBorislav Petkov 1726ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_qpi = { 1727ed367e6cSBorislav Petkov .name = "qpi", 1728ed367e6cSBorislav Petkov .num_counters = 4, 1729ed367e6cSBorislav Petkov .num_boxes = 3, 1730ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1731ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 1732ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 1733ed367e6cSBorislav Petkov .event_mask = IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 1734ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1735ed367e6cSBorislav Petkov .num_shared_regs = 1, 1736ed367e6cSBorislav Petkov .ops = &ivbep_uncore_qpi_ops, 1737ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_qpi_format_group, 1738ed367e6cSBorislav Petkov }; 1739ed367e6cSBorislav Petkov 1740ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_r2pcie = { 1741ed367e6cSBorislav Petkov .name = "r2pcie", 1742ed367e6cSBorislav Petkov .num_counters = 4, 1743ed367e6cSBorislav Petkov .num_boxes = 1, 1744ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1745ed367e6cSBorislav Petkov .constraints = snbep_uncore_r2pcie_constraints, 1746ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1747ed367e6cSBorislav Petkov }; 1748ed367e6cSBorislav Petkov 1749ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_r3qpi = { 1750ed367e6cSBorislav Petkov .name = "r3qpi", 1751ed367e6cSBorislav Petkov .num_counters = 3, 1752ed367e6cSBorislav Petkov .num_boxes = 2, 1753ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1754ed367e6cSBorislav Petkov .constraints = snbep_uncore_r3qpi_constraints, 1755ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1756ed367e6cSBorislav Petkov }; 1757ed367e6cSBorislav Petkov 1758ed367e6cSBorislav Petkov enum { 1759ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_HA, 1760ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_IMC, 1761ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_IRP, 1762ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_QPI, 1763ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_R2PCIE, 1764ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_R3QPI, 1765ed367e6cSBorislav Petkov }; 1766ed367e6cSBorislav Petkov 1767ed367e6cSBorislav Petkov static struct intel_uncore_type *ivbep_pci_uncores[] = { 1768ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_HA] = &ivbep_uncore_ha, 1769ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_IMC] = &ivbep_uncore_imc, 1770ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_IRP] = &ivbep_uncore_irp, 1771ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_QPI] = &ivbep_uncore_qpi, 1772ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_R2PCIE] = &ivbep_uncore_r2pcie, 1773ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_R3QPI] = &ivbep_uncore_r3qpi, 1774ed367e6cSBorislav Petkov NULL, 1775ed367e6cSBorislav Petkov }; 1776ed367e6cSBorislav Petkov 1777ed367e6cSBorislav Petkov static const struct pci_device_id ivbep_uncore_pci_ids[] = { 1778ed367e6cSBorislav Petkov { /* Home Agent 0 */ 1779ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30), 1780ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 0), 1781ed367e6cSBorislav Petkov }, 1782ed367e6cSBorislav Petkov { /* Home Agent 1 */ 1783ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38), 1784ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 1), 1785ed367e6cSBorislav Petkov }, 1786ed367e6cSBorislav Petkov { /* MC0 Channel 0 */ 1787ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4), 1788ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 0), 1789ed367e6cSBorislav Petkov }, 1790ed367e6cSBorislav Petkov { /* MC0 Channel 1 */ 1791ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5), 1792ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 1), 1793ed367e6cSBorislav Petkov }, 1794ed367e6cSBorislav Petkov { /* MC0 Channel 3 */ 1795ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0), 1796ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 2), 1797ed367e6cSBorislav Petkov }, 1798ed367e6cSBorislav Petkov { /* MC0 Channel 4 */ 1799ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1), 1800ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 3), 1801ed367e6cSBorislav Petkov }, 1802ed367e6cSBorislav Petkov { /* MC1 Channel 0 */ 1803ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4), 1804ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 4), 1805ed367e6cSBorislav Petkov }, 1806ed367e6cSBorislav Petkov { /* MC1 Channel 1 */ 1807ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5), 1808ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 5), 1809ed367e6cSBorislav Petkov }, 1810ed367e6cSBorislav Petkov { /* MC1 Channel 3 */ 1811ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0), 1812ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 6), 1813ed367e6cSBorislav Petkov }, 1814ed367e6cSBorislav Petkov { /* MC1 Channel 4 */ 1815ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1), 1816ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 7), 1817ed367e6cSBorislav Petkov }, 1818ed367e6cSBorislav Petkov { /* IRP */ 1819ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39), 1820ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IRP, 0), 1821ed367e6cSBorislav Petkov }, 1822ed367e6cSBorislav Petkov { /* QPI0 Port 0 */ 1823ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32), 1824ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 0), 1825ed367e6cSBorislav Petkov }, 1826ed367e6cSBorislav Petkov { /* QPI0 Port 1 */ 1827ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33), 1828ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 1), 1829ed367e6cSBorislav Petkov }, 1830ed367e6cSBorislav Petkov { /* QPI1 Port 2 */ 1831ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a), 1832ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 2), 1833ed367e6cSBorislav Petkov }, 1834ed367e6cSBorislav Petkov { /* R2PCIe */ 1835ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34), 1836ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R2PCIE, 0), 1837ed367e6cSBorislav Petkov }, 1838ed367e6cSBorislav Petkov { /* R3QPI0 Link 0 */ 1839ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36), 1840ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 0), 1841ed367e6cSBorislav Petkov }, 1842ed367e6cSBorislav Petkov { /* R3QPI0 Link 1 */ 1843ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37), 1844ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 1), 1845ed367e6cSBorislav Petkov }, 1846ed367e6cSBorislav Petkov { /* R3QPI1 Link 2 */ 1847ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e), 1848ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 2), 1849ed367e6cSBorislav Petkov }, 1850ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1851ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86), 1852ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1853ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER), 1854ed367e6cSBorislav Petkov }, 1855ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1856ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96), 1857ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1858ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER), 1859ed367e6cSBorislav Petkov }, 1860ed367e6cSBorislav Petkov { /* end: all zeroes */ } 1861ed367e6cSBorislav Petkov }; 1862ed367e6cSBorislav Petkov 1863ed367e6cSBorislav Petkov static struct pci_driver ivbep_uncore_pci_driver = { 1864ed367e6cSBorislav Petkov .name = "ivbep_uncore", 1865ed367e6cSBorislav Petkov .id_table = ivbep_uncore_pci_ids, 1866ed367e6cSBorislav Petkov }; 1867ed367e6cSBorislav Petkov 1868ed367e6cSBorislav Petkov int ivbep_uncore_pci_init(void) 1869ed367e6cSBorislav Petkov { 187068ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x0e1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 1871ed367e6cSBorislav Petkov if (ret) 1872ed367e6cSBorislav Petkov return ret; 1873ed367e6cSBorislav Petkov uncore_pci_uncores = ivbep_pci_uncores; 1874ed367e6cSBorislav Petkov uncore_pci_driver = &ivbep_uncore_pci_driver; 1875ed367e6cSBorislav Petkov return 0; 1876ed367e6cSBorislav Petkov } 1877ed367e6cSBorislav Petkov /* end of IvyTown uncore support */ 1878ed367e6cSBorislav Petkov 1879ed367e6cSBorislav Petkov /* KNL uncore support */ 1880ed367e6cSBorislav Petkov static struct attribute *knl_uncore_ubox_formats_attr[] = { 1881ed367e6cSBorislav Petkov &format_attr_event.attr, 1882ed367e6cSBorislav Petkov &format_attr_umask.attr, 1883ed367e6cSBorislav Petkov &format_attr_edge.attr, 1884ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 1885ed367e6cSBorislav Petkov &format_attr_inv.attr, 1886ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 1887ed367e6cSBorislav Petkov NULL, 1888ed367e6cSBorislav Petkov }; 1889ed367e6cSBorislav Petkov 1890ed367e6cSBorislav Petkov static struct attribute_group knl_uncore_ubox_format_group = { 1891ed367e6cSBorislav Petkov .name = "format", 1892ed367e6cSBorislav Petkov .attrs = knl_uncore_ubox_formats_attr, 1893ed367e6cSBorislav Petkov }; 1894ed367e6cSBorislav Petkov 1895ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_ubox = { 1896ed367e6cSBorislav Petkov .name = "ubox", 1897ed367e6cSBorislav Petkov .num_counters = 2, 1898ed367e6cSBorislav Petkov .num_boxes = 1, 1899ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1900ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1901ed367e6cSBorislav Petkov .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 1902ed367e6cSBorislav Petkov .event_ctl = HSWEP_U_MSR_PMON_CTL0, 1903ed367e6cSBorislav Petkov .event_mask = KNL_U_MSR_PMON_RAW_EVENT_MASK, 1904ed367e6cSBorislav Petkov .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 1905ed367e6cSBorislav Petkov .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 1906ed367e6cSBorislav Petkov .ops = &snbep_uncore_msr_ops, 1907ed367e6cSBorislav Petkov .format_group = &knl_uncore_ubox_format_group, 1908ed367e6cSBorislav Petkov }; 1909ed367e6cSBorislav Petkov 1910ed367e6cSBorislav Petkov static struct attribute *knl_uncore_cha_formats_attr[] = { 1911ed367e6cSBorislav Petkov &format_attr_event.attr, 1912ed367e6cSBorislav Petkov &format_attr_umask.attr, 1913ed367e6cSBorislav Petkov &format_attr_qor.attr, 1914ed367e6cSBorislav Petkov &format_attr_edge.attr, 1915ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 1916ed367e6cSBorislav Petkov &format_attr_inv.attr, 1917ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1918ed367e6cSBorislav Petkov &format_attr_filter_tid4.attr, 1919ed367e6cSBorislav Petkov &format_attr_filter_link3.attr, 1920ed367e6cSBorislav Petkov &format_attr_filter_state4.attr, 1921ed367e6cSBorislav Petkov &format_attr_filter_local.attr, 1922ed367e6cSBorislav Petkov &format_attr_filter_all_op.attr, 1923ed367e6cSBorislav Petkov &format_attr_filter_nnm.attr, 1924ed367e6cSBorislav Petkov &format_attr_filter_opc3.attr, 1925ed367e6cSBorislav Petkov &format_attr_filter_nc.attr, 1926ed367e6cSBorislav Petkov &format_attr_filter_isoc.attr, 1927ed367e6cSBorislav Petkov NULL, 1928ed367e6cSBorislav Petkov }; 1929ed367e6cSBorislav Petkov 1930ed367e6cSBorislav Petkov static struct attribute_group knl_uncore_cha_format_group = { 1931ed367e6cSBorislav Petkov .name = "format", 1932ed367e6cSBorislav Petkov .attrs = knl_uncore_cha_formats_attr, 1933ed367e6cSBorislav Petkov }; 1934ed367e6cSBorislav Petkov 1935ed367e6cSBorislav Petkov static struct event_constraint knl_uncore_cha_constraints[] = { 1936ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 1937ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), 1938ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 1939ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 1940ed367e6cSBorislav Petkov }; 1941ed367e6cSBorislav Petkov 1942ed367e6cSBorislav Petkov static struct extra_reg knl_uncore_cha_extra_regs[] = { 1943ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 1944ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 1945ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2), 1946ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4), 1947ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4), 1948ed367e6cSBorislav Petkov EVENT_EXTRA_END 1949ed367e6cSBorislav Petkov }; 1950ed367e6cSBorislav Petkov 1951ed367e6cSBorislav Petkov static u64 knl_cha_filter_mask(int fields) 1952ed367e6cSBorislav Petkov { 1953ed367e6cSBorislav Petkov u64 mask = 0; 1954ed367e6cSBorislav Petkov 1955ed367e6cSBorislav Petkov if (fields & 0x1) 1956ed367e6cSBorislav Petkov mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID; 1957ed367e6cSBorislav Petkov if (fields & 0x2) 1958ed367e6cSBorislav Petkov mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE; 1959ed367e6cSBorislav Petkov if (fields & 0x4) 1960ed367e6cSBorislav Petkov mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP; 1961ed367e6cSBorislav Petkov return mask; 1962ed367e6cSBorislav Petkov } 1963ed367e6cSBorislav Petkov 1964ed367e6cSBorislav Petkov static struct event_constraint * 1965ed367e6cSBorislav Petkov knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 1966ed367e6cSBorislav Petkov { 1967ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, knl_cha_filter_mask); 1968ed367e6cSBorislav Petkov } 1969ed367e6cSBorislav Petkov 1970ed367e6cSBorislav Petkov static int knl_cha_hw_config(struct intel_uncore_box *box, 1971ed367e6cSBorislav Petkov struct perf_event *event) 1972ed367e6cSBorislav Petkov { 1973ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1974ed367e6cSBorislav Petkov struct extra_reg *er; 1975ed367e6cSBorislav Petkov int idx = 0; 1976ed367e6cSBorislav Petkov 1977ed367e6cSBorislav Petkov for (er = knl_uncore_cha_extra_regs; er->msr; er++) { 1978ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 1979ed367e6cSBorislav Petkov continue; 1980ed367e6cSBorislav Petkov idx |= er->idx; 1981ed367e6cSBorislav Petkov } 1982ed367e6cSBorislav Petkov 1983ed367e6cSBorislav Petkov if (idx) { 1984ed367e6cSBorislav Petkov reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 1985ed367e6cSBorislav Petkov KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx; 1986ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & knl_cha_filter_mask(idx); 1987ec336c87Shchrzani 1988ec336c87Shchrzani reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE; 1989ec336c87Shchrzani reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE; 1990ec336c87Shchrzani reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC; 1991ed367e6cSBorislav Petkov reg1->idx = idx; 1992ed367e6cSBorislav Petkov } 1993ed367e6cSBorislav Petkov return 0; 1994ed367e6cSBorislav Petkov } 1995ed367e6cSBorislav Petkov 1996ed367e6cSBorislav Petkov static void hswep_cbox_enable_event(struct intel_uncore_box *box, 1997ed367e6cSBorislav Petkov struct perf_event *event); 1998ed367e6cSBorislav Petkov 1999ed367e6cSBorislav Petkov static struct intel_uncore_ops knl_uncore_cha_ops = { 2000ed367e6cSBorislav Petkov .init_box = snbep_uncore_msr_init_box, 2001ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, 2002ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, 2003ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, 2004ed367e6cSBorislav Petkov .enable_event = hswep_cbox_enable_event, 2005ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter, 2006ed367e6cSBorislav Petkov .hw_config = knl_cha_hw_config, 2007ed367e6cSBorislav Petkov .get_constraint = knl_cha_get_constraint, 2008ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 2009ed367e6cSBorislav Petkov }; 2010ed367e6cSBorislav Petkov 2011ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_cha = { 2012ed367e6cSBorislav Petkov .name = "cha", 2013ed367e6cSBorislav Petkov .num_counters = 4, 2014ed367e6cSBorislav Petkov .num_boxes = 38, 2015ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2016ed367e6cSBorislav Petkov .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 2017ed367e6cSBorislav Petkov .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 2018ed367e6cSBorislav Petkov .event_mask = KNL_CHA_MSR_PMON_RAW_EVENT_MASK, 2019ed367e6cSBorislav Petkov .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 2020ed367e6cSBorislav Petkov .msr_offset = KNL_CHA_MSR_OFFSET, 2021ed367e6cSBorislav Petkov .num_shared_regs = 1, 2022ed367e6cSBorislav Petkov .constraints = knl_uncore_cha_constraints, 2023ed367e6cSBorislav Petkov .ops = &knl_uncore_cha_ops, 2024ed367e6cSBorislav Petkov .format_group = &knl_uncore_cha_format_group, 2025ed367e6cSBorislav Petkov }; 2026ed367e6cSBorislav Petkov 2027ed367e6cSBorislav Petkov static struct attribute *knl_uncore_pcu_formats_attr[] = { 2028ed367e6cSBorislav Petkov &format_attr_event2.attr, 2029ed367e6cSBorislav Petkov &format_attr_use_occ_ctr.attr, 2030ed367e6cSBorislav Petkov &format_attr_occ_sel.attr, 2031ed367e6cSBorislav Petkov &format_attr_edge.attr, 2032ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 2033ed367e6cSBorislav Petkov &format_attr_inv.attr, 2034ed367e6cSBorislav Petkov &format_attr_thresh6.attr, 2035ed367e6cSBorislav Petkov &format_attr_occ_invert.attr, 2036ed367e6cSBorislav Petkov &format_attr_occ_edge_det.attr, 2037ed367e6cSBorislav Petkov NULL, 2038ed367e6cSBorislav Petkov }; 2039ed367e6cSBorislav Petkov 2040ed367e6cSBorislav Petkov static struct attribute_group knl_uncore_pcu_format_group = { 2041ed367e6cSBorislav Petkov .name = "format", 2042ed367e6cSBorislav Petkov .attrs = knl_uncore_pcu_formats_attr, 2043ed367e6cSBorislav Petkov }; 2044ed367e6cSBorislav Petkov 2045ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_pcu = { 2046ed367e6cSBorislav Petkov .name = "pcu", 2047ed367e6cSBorislav Petkov .num_counters = 4, 2048ed367e6cSBorislav Petkov .num_boxes = 1, 2049ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2050ed367e6cSBorislav Petkov .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 2051ed367e6cSBorislav Petkov .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 2052ed367e6cSBorislav Petkov .event_mask = KNL_PCU_MSR_PMON_RAW_EVENT_MASK, 2053ed367e6cSBorislav Petkov .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 2054ed367e6cSBorislav Petkov .ops = &snbep_uncore_msr_ops, 2055ed367e6cSBorislav Petkov .format_group = &knl_uncore_pcu_format_group, 2056ed367e6cSBorislav Petkov }; 2057ed367e6cSBorislav Petkov 2058ed367e6cSBorislav Petkov static struct intel_uncore_type *knl_msr_uncores[] = { 2059ed367e6cSBorislav Petkov &knl_uncore_ubox, 2060ed367e6cSBorislav Petkov &knl_uncore_cha, 2061ed367e6cSBorislav Petkov &knl_uncore_pcu, 2062ed367e6cSBorislav Petkov NULL, 2063ed367e6cSBorislav Petkov }; 2064ed367e6cSBorislav Petkov 2065ed367e6cSBorislav Petkov void knl_uncore_cpu_init(void) 2066ed367e6cSBorislav Petkov { 2067ed367e6cSBorislav Petkov uncore_msr_uncores = knl_msr_uncores; 2068ed367e6cSBorislav Petkov } 2069ed367e6cSBorislav Petkov 2070ed367e6cSBorislav Petkov static void knl_uncore_imc_enable_box(struct intel_uncore_box *box) 2071ed367e6cSBorislav Petkov { 2072ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 2073ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 2074ed367e6cSBorislav Petkov 2075ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, 0); 2076ed367e6cSBorislav Petkov } 2077ed367e6cSBorislav Petkov 2078ed367e6cSBorislav Petkov static void knl_uncore_imc_enable_event(struct intel_uncore_box *box, 2079ed367e6cSBorislav Petkov struct perf_event *event) 2080ed367e6cSBorislav Petkov { 2081ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 2082ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2083ed367e6cSBorislav Petkov 2084ed367e6cSBorislav Petkov if ((event->attr.config & SNBEP_PMON_CTL_EV_SEL_MASK) 2085ed367e6cSBorislav Petkov == UNCORE_FIXED_EVENT) 2086ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, 2087ed367e6cSBorislav Petkov hwc->config | KNL_PMON_FIXED_CTL_EN); 2088ed367e6cSBorislav Petkov else 2089ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, 2090ed367e6cSBorislav Petkov hwc->config | SNBEP_PMON_CTL_EN); 2091ed367e6cSBorislav Petkov } 2092ed367e6cSBorislav Petkov 2093ed367e6cSBorislav Petkov static struct intel_uncore_ops knl_uncore_imc_ops = { 2094ed367e6cSBorislav Petkov .init_box = snbep_uncore_pci_init_box, 2095ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 2096ed367e6cSBorislav Petkov .enable_box = knl_uncore_imc_enable_box, 2097ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter, 2098ed367e6cSBorislav Petkov .enable_event = knl_uncore_imc_enable_event, 2099ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, 2100ed367e6cSBorislav Petkov }; 2101ed367e6cSBorislav Petkov 2102ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_imc_uclk = { 2103ed367e6cSBorislav Petkov .name = "imc_uclk", 2104ed367e6cSBorislav Petkov .num_counters = 4, 2105ed367e6cSBorislav Petkov .num_boxes = 2, 2106ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2107ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2108ed367e6cSBorislav Petkov .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW, 2109ed367e6cSBorislav Petkov .event_ctl = KNL_UCLK_MSR_PMON_CTL0, 2110ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2111ed367e6cSBorislav Petkov .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW, 2112ed367e6cSBorislav Petkov .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL, 2113ed367e6cSBorislav Petkov .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL, 2114ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2115ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2116ed367e6cSBorislav Petkov }; 2117ed367e6cSBorislav Petkov 2118ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_imc_dclk = { 2119ed367e6cSBorislav Petkov .name = "imc", 2120ed367e6cSBorislav Petkov .num_counters = 4, 2121ed367e6cSBorislav Petkov .num_boxes = 6, 2122ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2123ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2124ed367e6cSBorislav Petkov .perf_ctr = KNL_MC0_CH0_MSR_PMON_CTR0_LOW, 2125ed367e6cSBorislav Petkov .event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0, 2126ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2127ed367e6cSBorislav Petkov .fixed_ctr = KNL_MC0_CH0_MSR_PMON_FIXED_LOW, 2128ed367e6cSBorislav Petkov .fixed_ctl = KNL_MC0_CH0_MSR_PMON_FIXED_CTL, 2129ed367e6cSBorislav Petkov .box_ctl = KNL_MC0_CH0_MSR_PMON_BOX_CTL, 2130ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2131ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2132ed367e6cSBorislav Petkov }; 2133ed367e6cSBorislav Petkov 2134ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_edc_uclk = { 2135ed367e6cSBorislav Petkov .name = "edc_uclk", 2136ed367e6cSBorislav Petkov .num_counters = 4, 2137ed367e6cSBorislav Petkov .num_boxes = 8, 2138ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2139ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2140ed367e6cSBorislav Petkov .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW, 2141ed367e6cSBorislav Petkov .event_ctl = KNL_UCLK_MSR_PMON_CTL0, 2142ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2143ed367e6cSBorislav Petkov .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW, 2144ed367e6cSBorislav Petkov .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL, 2145ed367e6cSBorislav Petkov .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL, 2146ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2147ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2148ed367e6cSBorislav Petkov }; 2149ed367e6cSBorislav Petkov 2150ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_edc_eclk = { 2151ed367e6cSBorislav Petkov .name = "edc_eclk", 2152ed367e6cSBorislav Petkov .num_counters = 4, 2153ed367e6cSBorislav Petkov .num_boxes = 8, 2154ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2155ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2156ed367e6cSBorislav Petkov .perf_ctr = KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW, 2157ed367e6cSBorislav Petkov .event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0, 2158ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2159ed367e6cSBorislav Petkov .fixed_ctr = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW, 2160ed367e6cSBorislav Petkov .fixed_ctl = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL, 2161ed367e6cSBorislav Petkov .box_ctl = KNL_EDC0_ECLK_MSR_PMON_BOX_CTL, 2162ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2163ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2164ed367e6cSBorislav Petkov }; 2165ed367e6cSBorislav Petkov 2166ed367e6cSBorislav Petkov static struct event_constraint knl_uncore_m2pcie_constraints[] = { 2167ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 2168ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2169ed367e6cSBorislav Petkov }; 2170ed367e6cSBorislav Petkov 2171ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_m2pcie = { 2172ed367e6cSBorislav Petkov .name = "m2pcie", 2173ed367e6cSBorislav Petkov .num_counters = 4, 2174ed367e6cSBorislav Petkov .num_boxes = 1, 2175ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2176ed367e6cSBorislav Petkov .constraints = knl_uncore_m2pcie_constraints, 2177ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2178ed367e6cSBorislav Petkov }; 2179ed367e6cSBorislav Petkov 2180ed367e6cSBorislav Petkov static struct attribute *knl_uncore_irp_formats_attr[] = { 2181ed367e6cSBorislav Petkov &format_attr_event.attr, 2182ed367e6cSBorislav Petkov &format_attr_umask.attr, 2183ed367e6cSBorislav Petkov &format_attr_qor.attr, 2184ed367e6cSBorislav Petkov &format_attr_edge.attr, 2185ed367e6cSBorislav Petkov &format_attr_inv.attr, 2186ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 2187ed367e6cSBorislav Petkov NULL, 2188ed367e6cSBorislav Petkov }; 2189ed367e6cSBorislav Petkov 2190ed367e6cSBorislav Petkov static struct attribute_group knl_uncore_irp_format_group = { 2191ed367e6cSBorislav Petkov .name = "format", 2192ed367e6cSBorislav Petkov .attrs = knl_uncore_irp_formats_attr, 2193ed367e6cSBorislav Petkov }; 2194ed367e6cSBorislav Petkov 2195ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_irp = { 2196ed367e6cSBorislav Petkov .name = "irp", 2197ed367e6cSBorislav Petkov .num_counters = 2, 2198ed367e6cSBorislav Petkov .num_boxes = 1, 2199ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2200ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 2201ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 2202ed367e6cSBorislav Petkov .event_mask = KNL_IRP_PCI_PMON_RAW_EVENT_MASK, 2203ed367e6cSBorislav Petkov .box_ctl = KNL_IRP_PCI_PMON_BOX_CTL, 2204ed367e6cSBorislav Petkov .ops = &snbep_uncore_pci_ops, 2205ed367e6cSBorislav Petkov .format_group = &knl_uncore_irp_format_group, 2206ed367e6cSBorislav Petkov }; 2207ed367e6cSBorislav Petkov 2208ed367e6cSBorislav Petkov enum { 2209ed367e6cSBorislav Petkov KNL_PCI_UNCORE_MC_UCLK, 2210ed367e6cSBorislav Petkov KNL_PCI_UNCORE_MC_DCLK, 2211ed367e6cSBorislav Petkov KNL_PCI_UNCORE_EDC_UCLK, 2212ed367e6cSBorislav Petkov KNL_PCI_UNCORE_EDC_ECLK, 2213ed367e6cSBorislav Petkov KNL_PCI_UNCORE_M2PCIE, 2214ed367e6cSBorislav Petkov KNL_PCI_UNCORE_IRP, 2215ed367e6cSBorislav Petkov }; 2216ed367e6cSBorislav Petkov 2217ed367e6cSBorislav Petkov static struct intel_uncore_type *knl_pci_uncores[] = { 2218ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_MC_UCLK] = &knl_uncore_imc_uclk, 2219ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_MC_DCLK] = &knl_uncore_imc_dclk, 2220ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_EDC_UCLK] = &knl_uncore_edc_uclk, 2221ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_EDC_ECLK] = &knl_uncore_edc_eclk, 2222ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_M2PCIE] = &knl_uncore_m2pcie, 2223ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_IRP] = &knl_uncore_irp, 2224ed367e6cSBorislav Petkov NULL, 2225ed367e6cSBorislav Petkov }; 2226ed367e6cSBorislav Petkov 2227ed367e6cSBorislav Petkov /* 2228ed367e6cSBorislav Petkov * KNL uses a common PCI device ID for multiple instances of an Uncore PMU 2229ed367e6cSBorislav Petkov * device type. prior to KNL, each instance of a PMU device type had a unique 2230ed367e6cSBorislav Petkov * device ID. 2231ed367e6cSBorislav Petkov * 2232ed367e6cSBorislav Petkov * PCI Device ID Uncore PMU Devices 2233ed367e6cSBorislav Petkov * ---------------------------------- 2234ed367e6cSBorislav Petkov * 0x7841 MC0 UClk, MC1 UClk 2235ed367e6cSBorislav Petkov * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2, 2236ed367e6cSBorislav Petkov * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2 2237ed367e6cSBorislav Petkov * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk, 2238ed367e6cSBorislav Petkov * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk 2239ed367e6cSBorislav Petkov * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk, 2240ed367e6cSBorislav Petkov * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk 2241ed367e6cSBorislav Petkov * 0x7817 M2PCIe 2242ed367e6cSBorislav Petkov * 0x7814 IRP 2243ed367e6cSBorislav Petkov */ 2244ed367e6cSBorislav Petkov 2245ed367e6cSBorislav Petkov static const struct pci_device_id knl_uncore_pci_ids[] = { 2246a54fa079SKan Liang { /* MC0 UClk */ 2247ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841), 2248a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 0, KNL_PCI_UNCORE_MC_UCLK, 0), 2249ed367e6cSBorislav Petkov }, 2250a54fa079SKan Liang { /* MC1 UClk */ 2251a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841), 2252a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 0, KNL_PCI_UNCORE_MC_UCLK, 1), 2253a54fa079SKan Liang }, 2254a54fa079SKan Liang { /* MC0 DClk CH 0 */ 2255ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2256a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 2, KNL_PCI_UNCORE_MC_DCLK, 0), 2257ed367e6cSBorislav Petkov }, 2258a54fa079SKan Liang { /* MC0 DClk CH 1 */ 2259a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2260a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 3, KNL_PCI_UNCORE_MC_DCLK, 1), 2261a54fa079SKan Liang }, 2262a54fa079SKan Liang { /* MC0 DClk CH 2 */ 2263a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2264a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 4, KNL_PCI_UNCORE_MC_DCLK, 2), 2265a54fa079SKan Liang }, 2266a54fa079SKan Liang { /* MC1 DClk CH 0 */ 2267a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2268a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 2, KNL_PCI_UNCORE_MC_DCLK, 3), 2269a54fa079SKan Liang }, 2270a54fa079SKan Liang { /* MC1 DClk CH 1 */ 2271a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2272a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 3, KNL_PCI_UNCORE_MC_DCLK, 4), 2273a54fa079SKan Liang }, 2274a54fa079SKan Liang { /* MC1 DClk CH 2 */ 2275a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2276a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 4, KNL_PCI_UNCORE_MC_DCLK, 5), 2277a54fa079SKan Liang }, 2278a54fa079SKan Liang { /* EDC0 UClk */ 2279ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2280a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, KNL_PCI_UNCORE_EDC_UCLK, 0), 2281ed367e6cSBorislav Petkov }, 2282a54fa079SKan Liang { /* EDC1 UClk */ 2283a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2284a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, KNL_PCI_UNCORE_EDC_UCLK, 1), 2285a54fa079SKan Liang }, 2286a54fa079SKan Liang { /* EDC2 UClk */ 2287a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2288a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(17, 0, KNL_PCI_UNCORE_EDC_UCLK, 2), 2289a54fa079SKan Liang }, 2290a54fa079SKan Liang { /* EDC3 UClk */ 2291a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2292a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 0, KNL_PCI_UNCORE_EDC_UCLK, 3), 2293a54fa079SKan Liang }, 2294a54fa079SKan Liang { /* EDC4 UClk */ 2295a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2296a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(19, 0, KNL_PCI_UNCORE_EDC_UCLK, 4), 2297a54fa079SKan Liang }, 2298a54fa079SKan Liang { /* EDC5 UClk */ 2299a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2300a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(20, 0, KNL_PCI_UNCORE_EDC_UCLK, 5), 2301a54fa079SKan Liang }, 2302a54fa079SKan Liang { /* EDC6 UClk */ 2303a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2304a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 0, KNL_PCI_UNCORE_EDC_UCLK, 6), 2305a54fa079SKan Liang }, 2306a54fa079SKan Liang { /* EDC7 UClk */ 2307a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2308a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 0, KNL_PCI_UNCORE_EDC_UCLK, 7), 2309a54fa079SKan Liang }, 2310a54fa079SKan Liang { /* EDC0 EClk */ 2311ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2312a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(24, 2, KNL_PCI_UNCORE_EDC_ECLK, 0), 2313a54fa079SKan Liang }, 2314a54fa079SKan Liang { /* EDC1 EClk */ 2315a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2316a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(25, 2, KNL_PCI_UNCORE_EDC_ECLK, 1), 2317a54fa079SKan Liang }, 2318a54fa079SKan Liang { /* EDC2 EClk */ 2319a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2320a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(26, 2, KNL_PCI_UNCORE_EDC_ECLK, 2), 2321a54fa079SKan Liang }, 2322a54fa079SKan Liang { /* EDC3 EClk */ 2323a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2324a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(27, 2, KNL_PCI_UNCORE_EDC_ECLK, 3), 2325a54fa079SKan Liang }, 2326a54fa079SKan Liang { /* EDC4 EClk */ 2327a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2328a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(28, 2, KNL_PCI_UNCORE_EDC_ECLK, 4), 2329a54fa079SKan Liang }, 2330a54fa079SKan Liang { /* EDC5 EClk */ 2331a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2332a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(29, 2, KNL_PCI_UNCORE_EDC_ECLK, 5), 2333a54fa079SKan Liang }, 2334a54fa079SKan Liang { /* EDC6 EClk */ 2335a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2336a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(30, 2, KNL_PCI_UNCORE_EDC_ECLK, 6), 2337a54fa079SKan Liang }, 2338a54fa079SKan Liang { /* EDC7 EClk */ 2339a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2340a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(31, 2, KNL_PCI_UNCORE_EDC_ECLK, 7), 2341ed367e6cSBorislav Petkov }, 2342ed367e6cSBorislav Petkov { /* M2PCIe */ 2343ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817), 2344ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0), 2345ed367e6cSBorislav Petkov }, 2346ed367e6cSBorislav Petkov { /* IRP */ 2347ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814), 2348ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0), 2349ed367e6cSBorislav Petkov }, 2350ed367e6cSBorislav Petkov { /* end: all zeroes */ } 2351ed367e6cSBorislav Petkov }; 2352ed367e6cSBorislav Petkov 2353ed367e6cSBorislav Petkov static struct pci_driver knl_uncore_pci_driver = { 2354ed367e6cSBorislav Petkov .name = "knl_uncore", 2355ed367e6cSBorislav Petkov .id_table = knl_uncore_pci_ids, 2356ed367e6cSBorislav Petkov }; 2357ed367e6cSBorislav Petkov 2358ed367e6cSBorislav Petkov int knl_uncore_pci_init(void) 2359ed367e6cSBorislav Petkov { 2360ed367e6cSBorislav Petkov int ret; 2361ed367e6cSBorislav Petkov 2362ed367e6cSBorislav Petkov /* All KNL PCI based PMON units are on the same PCI bus except IRP */ 2363ed367e6cSBorislav Petkov ret = snb_pci2phy_map_init(0x7814); /* IRP */ 2364ed367e6cSBorislav Petkov if (ret) 2365ed367e6cSBorislav Petkov return ret; 2366ed367e6cSBorislav Petkov ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */ 2367ed367e6cSBorislav Petkov if (ret) 2368ed367e6cSBorislav Petkov return ret; 2369ed367e6cSBorislav Petkov uncore_pci_uncores = knl_pci_uncores; 2370ed367e6cSBorislav Petkov uncore_pci_driver = &knl_uncore_pci_driver; 2371ed367e6cSBorislav Petkov return 0; 2372ed367e6cSBorislav Petkov } 2373ed367e6cSBorislav Petkov 2374ed367e6cSBorislav Petkov /* end of KNL uncore support */ 2375ed367e6cSBorislav Petkov 2376ed367e6cSBorislav Petkov /* Haswell-EP uncore support */ 2377ed367e6cSBorislav Petkov static struct attribute *hswep_uncore_ubox_formats_attr[] = { 2378ed367e6cSBorislav Petkov &format_attr_event.attr, 2379ed367e6cSBorislav Petkov &format_attr_umask.attr, 2380ed367e6cSBorislav Petkov &format_attr_edge.attr, 2381ed367e6cSBorislav Petkov &format_attr_inv.attr, 2382ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 2383ed367e6cSBorislav Petkov &format_attr_filter_tid2.attr, 2384ed367e6cSBorislav Petkov &format_attr_filter_cid.attr, 2385ed367e6cSBorislav Petkov NULL, 2386ed367e6cSBorislav Petkov }; 2387ed367e6cSBorislav Petkov 2388ed367e6cSBorislav Petkov static struct attribute_group hswep_uncore_ubox_format_group = { 2389ed367e6cSBorislav Petkov .name = "format", 2390ed367e6cSBorislav Petkov .attrs = hswep_uncore_ubox_formats_attr, 2391ed367e6cSBorislav Petkov }; 2392ed367e6cSBorislav Petkov 2393ed367e6cSBorislav Petkov static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2394ed367e6cSBorislav Petkov { 2395ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2396ed367e6cSBorislav Petkov reg1->reg = HSWEP_U_MSR_PMON_FILTER; 2397ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK; 2398ed367e6cSBorislav Petkov reg1->idx = 0; 2399ed367e6cSBorislav Petkov return 0; 2400ed367e6cSBorislav Petkov } 2401ed367e6cSBorislav Petkov 2402ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_ubox_ops = { 2403ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2404ed367e6cSBorislav Petkov .hw_config = hswep_ubox_hw_config, 2405ed367e6cSBorislav Petkov .get_constraint = uncore_get_constraint, 2406ed367e6cSBorislav Petkov .put_constraint = uncore_put_constraint, 2407ed367e6cSBorislav Petkov }; 2408ed367e6cSBorislav Petkov 2409ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_ubox = { 2410ed367e6cSBorislav Petkov .name = "ubox", 2411ed367e6cSBorislav Petkov .num_counters = 2, 2412ed367e6cSBorislav Petkov .num_boxes = 1, 2413ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 2414ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2415ed367e6cSBorislav Petkov .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 2416ed367e6cSBorislav Petkov .event_ctl = HSWEP_U_MSR_PMON_CTL0, 2417ed367e6cSBorislav Petkov .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 2418ed367e6cSBorislav Petkov .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 2419ed367e6cSBorislav Petkov .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 2420ed367e6cSBorislav Petkov .num_shared_regs = 1, 2421ed367e6cSBorislav Petkov .ops = &hswep_uncore_ubox_ops, 2422ed367e6cSBorislav Petkov .format_group = &hswep_uncore_ubox_format_group, 2423ed367e6cSBorislav Petkov }; 2424ed367e6cSBorislav Petkov 2425ed367e6cSBorislav Petkov static struct attribute *hswep_uncore_cbox_formats_attr[] = { 2426ed367e6cSBorislav Petkov &format_attr_event.attr, 2427ed367e6cSBorislav Petkov &format_attr_umask.attr, 2428ed367e6cSBorislav Petkov &format_attr_edge.attr, 2429ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 2430ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 2431ed367e6cSBorislav Petkov &format_attr_filter_tid3.attr, 2432ed367e6cSBorislav Petkov &format_attr_filter_link2.attr, 2433ed367e6cSBorislav Petkov &format_attr_filter_state3.attr, 2434ed367e6cSBorislav Petkov &format_attr_filter_nid2.attr, 2435ed367e6cSBorislav Petkov &format_attr_filter_opc2.attr, 2436ed367e6cSBorislav Petkov &format_attr_filter_nc.attr, 2437ed367e6cSBorislav Petkov &format_attr_filter_c6.attr, 2438ed367e6cSBorislav Petkov &format_attr_filter_isoc.attr, 2439ed367e6cSBorislav Petkov NULL, 2440ed367e6cSBorislav Petkov }; 2441ed367e6cSBorislav Petkov 2442ed367e6cSBorislav Petkov static struct attribute_group hswep_uncore_cbox_format_group = { 2443ed367e6cSBorislav Petkov .name = "format", 2444ed367e6cSBorislav Petkov .attrs = hswep_uncore_cbox_formats_attr, 2445ed367e6cSBorislav Petkov }; 2446ed367e6cSBorislav Petkov 2447ed367e6cSBorislav Petkov static struct event_constraint hswep_uncore_cbox_constraints[] = { 2448ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x1), 2449ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x1), 2450ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 2451ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 2452ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 2453ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), 2454ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3e, 0x1), 2455ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2456ed367e6cSBorislav Petkov }; 2457ed367e6cSBorislav Petkov 2458ed367e6cSBorislav Petkov static struct extra_reg hswep_uncore_cbox_extra_regs[] = { 2459ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 2460ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 2461ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 2462ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 2463ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 2464ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 2465ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4), 2466ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4), 2467ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8), 2468ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8), 2469ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8), 2470ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8), 2471ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8), 2472ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8), 2473ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12), 2474ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10), 2475ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18), 2476ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8), 2477ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8), 2478ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8), 2479ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18), 2480ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8), 2481ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10), 2482ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10), 2483ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10), 2484ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10), 2485ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10), 2486ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10), 2487ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18), 2488ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8), 2489ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8), 2490ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18), 2491ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8), 2492ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10), 2493ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10), 2494ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10), 2495ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10), 2496ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8), 2497ed367e6cSBorislav Petkov EVENT_EXTRA_END 2498ed367e6cSBorislav Petkov }; 2499ed367e6cSBorislav Petkov 2500ed367e6cSBorislav Petkov static u64 hswep_cbox_filter_mask(int fields) 2501ed367e6cSBorislav Petkov { 2502ed367e6cSBorislav Petkov u64 mask = 0; 2503ed367e6cSBorislav Petkov if (fields & 0x1) 2504ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID; 2505ed367e6cSBorislav Petkov if (fields & 0x2) 2506ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK; 2507ed367e6cSBorislav Petkov if (fields & 0x4) 2508ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE; 2509ed367e6cSBorislav Petkov if (fields & 0x8) 2510ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID; 2511ed367e6cSBorislav Petkov if (fields & 0x10) { 2512ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC; 2513ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC; 2514ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6; 2515ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC; 2516ed367e6cSBorislav Petkov } 2517ed367e6cSBorislav Petkov return mask; 2518ed367e6cSBorislav Petkov } 2519ed367e6cSBorislav Petkov 2520ed367e6cSBorislav Petkov static struct event_constraint * 2521ed367e6cSBorislav Petkov hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 2522ed367e6cSBorislav Petkov { 2523ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, hswep_cbox_filter_mask); 2524ed367e6cSBorislav Petkov } 2525ed367e6cSBorislav Petkov 2526ed367e6cSBorislav Petkov static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2527ed367e6cSBorislav Petkov { 2528ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2529ed367e6cSBorislav Petkov struct extra_reg *er; 2530ed367e6cSBorislav Petkov int idx = 0; 2531ed367e6cSBorislav Petkov 2532ed367e6cSBorislav Petkov for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) { 2533ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 2534ed367e6cSBorislav Petkov continue; 2535ed367e6cSBorislav Petkov idx |= er->idx; 2536ed367e6cSBorislav Petkov } 2537ed367e6cSBorislav Petkov 2538ed367e6cSBorislav Petkov if (idx) { 2539ed367e6cSBorislav Petkov reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 2540ed367e6cSBorislav Petkov HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 2541ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx); 2542ed367e6cSBorislav Petkov reg1->idx = idx; 2543ed367e6cSBorislav Petkov } 2544ed367e6cSBorislav Petkov return 0; 2545ed367e6cSBorislav Petkov } 2546ed367e6cSBorislav Petkov 2547ed367e6cSBorislav Petkov static void hswep_cbox_enable_event(struct intel_uncore_box *box, 2548ed367e6cSBorislav Petkov struct perf_event *event) 2549ed367e6cSBorislav Petkov { 2550ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2551ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 2552ed367e6cSBorislav Petkov 2553ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) { 2554ed367e6cSBorislav Petkov u64 filter = uncore_shared_reg_config(box, 0); 2555ed367e6cSBorislav Petkov wrmsrl(reg1->reg, filter & 0xffffffff); 2556ed367e6cSBorislav Petkov wrmsrl(reg1->reg + 1, filter >> 32); 2557ed367e6cSBorislav Petkov } 2558ed367e6cSBorislav Petkov 2559ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 2560ed367e6cSBorislav Petkov } 2561ed367e6cSBorislav Petkov 2562ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_cbox_ops = { 2563ed367e6cSBorislav Petkov .init_box = snbep_uncore_msr_init_box, 2564ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, 2565ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, 2566ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, 2567ed367e6cSBorislav Petkov .enable_event = hswep_cbox_enable_event, 2568ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter, 2569ed367e6cSBorislav Petkov .hw_config = hswep_cbox_hw_config, 2570ed367e6cSBorislav Petkov .get_constraint = hswep_cbox_get_constraint, 2571ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 2572ed367e6cSBorislav Petkov }; 2573ed367e6cSBorislav Petkov 2574ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_cbox = { 2575ed367e6cSBorislav Petkov .name = "cbox", 2576ed367e6cSBorislav Petkov .num_counters = 4, 2577ed367e6cSBorislav Petkov .num_boxes = 18, 2578ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2579ed367e6cSBorislav Petkov .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 2580ed367e6cSBorislav Petkov .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 2581ed367e6cSBorislav Petkov .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 2582ed367e6cSBorislav Petkov .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 2583ed367e6cSBorislav Petkov .msr_offset = HSWEP_CBO_MSR_OFFSET, 2584ed367e6cSBorislav Petkov .num_shared_regs = 1, 2585ed367e6cSBorislav Petkov .constraints = hswep_uncore_cbox_constraints, 2586ed367e6cSBorislav Petkov .ops = &hswep_uncore_cbox_ops, 2587ed367e6cSBorislav Petkov .format_group = &hswep_uncore_cbox_format_group, 2588ed367e6cSBorislav Petkov }; 2589ed367e6cSBorislav Petkov 2590ed367e6cSBorislav Petkov /* 2591ed367e6cSBorislav Petkov * Write SBOX Initialization register bit by bit to avoid spurious #GPs 2592ed367e6cSBorislav Petkov */ 2593ed367e6cSBorislav Petkov static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box) 2594ed367e6cSBorislav Petkov { 2595ed367e6cSBorislav Petkov unsigned msr = uncore_msr_box_ctl(box); 2596ed367e6cSBorislav Petkov 2597ed367e6cSBorislav Petkov if (msr) { 2598ed367e6cSBorislav Petkov u64 init = SNBEP_PMON_BOX_CTL_INT; 2599ed367e6cSBorislav Petkov u64 flags = 0; 2600ed367e6cSBorislav Petkov int i; 2601ed367e6cSBorislav Petkov 2602ed367e6cSBorislav Petkov for_each_set_bit(i, (unsigned long *)&init, 64) { 2603ed367e6cSBorislav Petkov flags |= (1ULL << i); 2604ed367e6cSBorislav Petkov wrmsrl(msr, flags); 2605ed367e6cSBorislav Petkov } 2606ed367e6cSBorislav Petkov } 2607ed367e6cSBorislav Petkov } 2608ed367e6cSBorislav Petkov 2609ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = { 2610ed367e6cSBorislav Petkov __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2611ed367e6cSBorislav Petkov .init_box = hswep_uncore_sbox_msr_init_box 2612ed367e6cSBorislav Petkov }; 2613ed367e6cSBorislav Petkov 2614ed367e6cSBorislav Petkov static struct attribute *hswep_uncore_sbox_formats_attr[] = { 2615ed367e6cSBorislav Petkov &format_attr_event.attr, 2616ed367e6cSBorislav Petkov &format_attr_umask.attr, 2617ed367e6cSBorislav Petkov &format_attr_edge.attr, 2618ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 2619ed367e6cSBorislav Petkov &format_attr_inv.attr, 2620ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 2621ed367e6cSBorislav Petkov NULL, 2622ed367e6cSBorislav Petkov }; 2623ed367e6cSBorislav Petkov 2624ed367e6cSBorislav Petkov static struct attribute_group hswep_uncore_sbox_format_group = { 2625ed367e6cSBorislav Petkov .name = "format", 2626ed367e6cSBorislav Petkov .attrs = hswep_uncore_sbox_formats_attr, 2627ed367e6cSBorislav Petkov }; 2628ed367e6cSBorislav Petkov 2629ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_sbox = { 2630ed367e6cSBorislav Petkov .name = "sbox", 2631ed367e6cSBorislav Petkov .num_counters = 4, 2632ed367e6cSBorislav Petkov .num_boxes = 4, 2633ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 2634ed367e6cSBorislav Petkov .event_ctl = HSWEP_S0_MSR_PMON_CTL0, 2635ed367e6cSBorislav Petkov .perf_ctr = HSWEP_S0_MSR_PMON_CTR0, 2636ed367e6cSBorislav Petkov .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 2637ed367e6cSBorislav Petkov .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL, 2638ed367e6cSBorislav Petkov .msr_offset = HSWEP_SBOX_MSR_OFFSET, 2639ed367e6cSBorislav Petkov .ops = &hswep_uncore_sbox_msr_ops, 2640ed367e6cSBorislav Petkov .format_group = &hswep_uncore_sbox_format_group, 2641ed367e6cSBorislav Petkov }; 2642ed367e6cSBorislav Petkov 2643ed367e6cSBorislav Petkov static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2644ed367e6cSBorislav Petkov { 2645ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2646ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 2647ed367e6cSBorislav Petkov int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 2648ed367e6cSBorislav Petkov 2649ed367e6cSBorislav Petkov if (ev_sel >= 0xb && ev_sel <= 0xe) { 2650ed367e6cSBorislav Petkov reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER; 2651ed367e6cSBorislav Petkov reg1->idx = ev_sel - 0xb; 2652ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & (0xff << reg1->idx); 2653ed367e6cSBorislav Petkov } 2654ed367e6cSBorislav Petkov return 0; 2655ed367e6cSBorislav Petkov } 2656ed367e6cSBorislav Petkov 2657ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_pcu_ops = { 2658ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2659ed367e6cSBorislav Petkov .hw_config = hswep_pcu_hw_config, 2660ed367e6cSBorislav Petkov .get_constraint = snbep_pcu_get_constraint, 2661ed367e6cSBorislav Petkov .put_constraint = snbep_pcu_put_constraint, 2662ed367e6cSBorislav Petkov }; 2663ed367e6cSBorislav Petkov 2664ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_pcu = { 2665ed367e6cSBorislav Petkov .name = "pcu", 2666ed367e6cSBorislav Petkov .num_counters = 4, 2667ed367e6cSBorislav Petkov .num_boxes = 1, 2668ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2669ed367e6cSBorislav Petkov .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 2670ed367e6cSBorislav Petkov .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 2671ed367e6cSBorislav Petkov .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 2672ed367e6cSBorislav Petkov .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 2673ed367e6cSBorislav Petkov .num_shared_regs = 1, 2674ed367e6cSBorislav Petkov .ops = &hswep_uncore_pcu_ops, 2675ed367e6cSBorislav Petkov .format_group = &snbep_uncore_pcu_format_group, 2676ed367e6cSBorislav Petkov }; 2677ed367e6cSBorislav Petkov 2678ed367e6cSBorislav Petkov static struct intel_uncore_type *hswep_msr_uncores[] = { 2679ed367e6cSBorislav Petkov &hswep_uncore_ubox, 2680ed367e6cSBorislav Petkov &hswep_uncore_cbox, 2681ed367e6cSBorislav Petkov &hswep_uncore_sbox, 2682ed367e6cSBorislav Petkov &hswep_uncore_pcu, 2683ed367e6cSBorislav Petkov NULL, 2684ed367e6cSBorislav Petkov }; 2685ed367e6cSBorislav Petkov 2686ed367e6cSBorislav Petkov void hswep_uncore_cpu_init(void) 2687ed367e6cSBorislav Petkov { 26886d6daa20SPrarit Bhargava int pkg = boot_cpu_data.logical_proc_id; 2689cf6d445fSThomas Gleixner 2690ed367e6cSBorislav Petkov if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 2691ed367e6cSBorislav Petkov hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 2692ed367e6cSBorislav Petkov 2693ed367e6cSBorislav Petkov /* Detect 6-8 core systems with only two SBOXes */ 2694cf6d445fSThomas Gleixner if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) { 2695ed367e6cSBorislav Petkov u32 capid4; 2696ed367e6cSBorislav Petkov 2697cf6d445fSThomas Gleixner pci_read_config_dword(uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3], 2698ed367e6cSBorislav Petkov 0x94, &capid4); 2699ed367e6cSBorislav Petkov if (((capid4 >> 6) & 0x3) == 0) 2700ed367e6cSBorislav Petkov hswep_uncore_sbox.num_boxes = 2; 2701ed367e6cSBorislav Petkov } 2702ed367e6cSBorislav Petkov 2703ed367e6cSBorislav Petkov uncore_msr_uncores = hswep_msr_uncores; 2704ed367e6cSBorislav Petkov } 2705ed367e6cSBorislav Petkov 2706ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_ha = { 2707ed367e6cSBorislav Petkov .name = "ha", 270810e9e7bdSKan Liang .num_counters = 4, 2709ed367e6cSBorislav Petkov .num_boxes = 2, 2710ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2711ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2712ed367e6cSBorislav Petkov }; 2713ed367e6cSBorislav Petkov 2714ed367e6cSBorislav Petkov static struct uncore_event_desc hswep_uncore_imc_events[] = { 2715ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"), 2716ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), 2717ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 2718ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 2719ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), 2720ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 2721ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 2722ed367e6cSBorislav Petkov { /* end: all zeroes */ }, 2723ed367e6cSBorislav Petkov }; 2724ed367e6cSBorislav Petkov 2725ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_imc = { 2726ed367e6cSBorislav Petkov .name = "imc", 272710e9e7bdSKan Liang .num_counters = 4, 2728ed367e6cSBorislav Petkov .num_boxes = 8, 2729ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2730ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2731ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 2732ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 2733ed367e6cSBorislav Petkov .event_descs = hswep_uncore_imc_events, 2734ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2735ed367e6cSBorislav Petkov }; 2736ed367e6cSBorislav Petkov 2737ed367e6cSBorislav Petkov static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8}; 2738ed367e6cSBorislav Petkov 2739ed367e6cSBorislav Petkov static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) 2740ed367e6cSBorislav Petkov { 2741ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 2742ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2743ed367e6cSBorislav Petkov u64 count = 0; 2744ed367e6cSBorislav Petkov 2745ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count); 2746ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1); 2747ed367e6cSBorislav Petkov 2748ed367e6cSBorislav Petkov return count; 2749ed367e6cSBorislav Petkov } 2750ed367e6cSBorislav Petkov 2751ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_irp_ops = { 2752ed367e6cSBorislav Petkov .init_box = snbep_uncore_pci_init_box, 2753ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 2754ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 2755ed367e6cSBorislav Petkov .disable_event = ivbep_uncore_irp_disable_event, 2756ed367e6cSBorislav Petkov .enable_event = ivbep_uncore_irp_enable_event, 2757ed367e6cSBorislav Petkov .read_counter = hswep_uncore_irp_read_counter, 2758ed367e6cSBorislav Petkov }; 2759ed367e6cSBorislav Petkov 2760ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_irp = { 2761ed367e6cSBorislav Petkov .name = "irp", 2762ed367e6cSBorislav Petkov .num_counters = 4, 2763ed367e6cSBorislav Petkov .num_boxes = 1, 2764ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2765ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2766ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 2767ed367e6cSBorislav Petkov .ops = &hswep_uncore_irp_ops, 2768ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2769ed367e6cSBorislav Petkov }; 2770ed367e6cSBorislav Petkov 2771ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_qpi = { 2772ed367e6cSBorislav Petkov .name = "qpi", 277310e9e7bdSKan Liang .num_counters = 4, 2774ed367e6cSBorislav Petkov .num_boxes = 3, 2775ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2776ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 2777ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 2778ed367e6cSBorislav Petkov .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 2779ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 2780ed367e6cSBorislav Petkov .num_shared_regs = 1, 2781ed367e6cSBorislav Petkov .ops = &snbep_uncore_qpi_ops, 2782ed367e6cSBorislav Petkov .format_group = &snbep_uncore_qpi_format_group, 2783ed367e6cSBorislav Petkov }; 2784ed367e6cSBorislav Petkov 2785ed367e6cSBorislav Petkov static struct event_constraint hswep_uncore_r2pcie_constraints[] = { 2786ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 2787ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 2788ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 2789ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x1), 2790ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x24, 0x1), 2791ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x1), 2792ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 2793ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x27, 0x1), 2794ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 2795ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 2796ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2a, 0x1), 2797ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), 2798ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 2799ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 2800ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 2801ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 2802ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 2803ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x35, 0x3), 2804ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2805ed367e6cSBorislav Petkov }; 2806ed367e6cSBorislav Petkov 2807ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_r2pcie = { 2808ed367e6cSBorislav Petkov .name = "r2pcie", 2809ed367e6cSBorislav Petkov .num_counters = 4, 2810ed367e6cSBorislav Petkov .num_boxes = 1, 2811ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2812ed367e6cSBorislav Petkov .constraints = hswep_uncore_r2pcie_constraints, 2813ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2814ed367e6cSBorislav Petkov }; 2815ed367e6cSBorislav Petkov 2816ed367e6cSBorislav Petkov static struct event_constraint hswep_uncore_r3qpi_constraints[] = { 2817ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x3), 2818ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x07, 0x7), 2819ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x08, 0x7), 2820ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x7), 2821ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), 2822ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), 2823ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 2824ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 2825ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 2826ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 2827ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 2828ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x15, 0x3), 2829ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), 2830ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 2831ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 2832ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 2833ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 2834ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 2835ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 2836ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 2837ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 2838ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 2839ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 2840ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 2841ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 2842ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 2843ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 2844ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 2845ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 2846ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 2847ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 2848ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 2849ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 2850ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2851ed367e6cSBorislav Petkov }; 2852ed367e6cSBorislav Petkov 2853ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_r3qpi = { 2854ed367e6cSBorislav Petkov .name = "r3qpi", 285510e9e7bdSKan Liang .num_counters = 3, 2856ed367e6cSBorislav Petkov .num_boxes = 3, 2857ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 2858ed367e6cSBorislav Petkov .constraints = hswep_uncore_r3qpi_constraints, 2859ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2860ed367e6cSBorislav Petkov }; 2861ed367e6cSBorislav Petkov 2862ed367e6cSBorislav Petkov enum { 2863ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_HA, 2864ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_IMC, 2865ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_IRP, 2866ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_QPI, 2867ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_R2PCIE, 2868ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_R3QPI, 2869ed367e6cSBorislav Petkov }; 2870ed367e6cSBorislav Petkov 2871ed367e6cSBorislav Petkov static struct intel_uncore_type *hswep_pci_uncores[] = { 2872ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_HA] = &hswep_uncore_ha, 2873ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_IMC] = &hswep_uncore_imc, 2874ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_IRP] = &hswep_uncore_irp, 2875ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_QPI] = &hswep_uncore_qpi, 2876ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_R2PCIE] = &hswep_uncore_r2pcie, 2877ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_R3QPI] = &hswep_uncore_r3qpi, 2878ed367e6cSBorislav Petkov NULL, 2879ed367e6cSBorislav Petkov }; 2880ed367e6cSBorislav Petkov 2881ed367e6cSBorislav Petkov static const struct pci_device_id hswep_uncore_pci_ids[] = { 2882ed367e6cSBorislav Petkov { /* Home Agent 0 */ 2883ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30), 2884ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0), 2885ed367e6cSBorislav Petkov }, 2886ed367e6cSBorislav Petkov { /* Home Agent 1 */ 2887ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38), 2888ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 1), 2889ed367e6cSBorislav Petkov }, 2890ed367e6cSBorislav Petkov { /* MC0 Channel 0 */ 2891ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0), 2892ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0), 2893ed367e6cSBorislav Petkov }, 2894ed367e6cSBorislav Petkov { /* MC0 Channel 1 */ 2895ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1), 2896ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1), 2897ed367e6cSBorislav Petkov }, 2898ed367e6cSBorislav Petkov { /* MC0 Channel 2 */ 2899ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4), 2900ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2), 2901ed367e6cSBorislav Petkov }, 2902ed367e6cSBorislav Petkov { /* MC0 Channel 3 */ 2903ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5), 2904ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3), 2905ed367e6cSBorislav Petkov }, 2906ed367e6cSBorislav Petkov { /* MC1 Channel 0 */ 2907ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0), 2908ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4), 2909ed367e6cSBorislav Petkov }, 2910ed367e6cSBorislav Petkov { /* MC1 Channel 1 */ 2911ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1), 2912ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5), 2913ed367e6cSBorislav Petkov }, 2914ed367e6cSBorislav Petkov { /* MC1 Channel 2 */ 2915ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4), 2916ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6), 2917ed367e6cSBorislav Petkov }, 2918ed367e6cSBorislav Petkov { /* MC1 Channel 3 */ 2919ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5), 2920ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7), 2921ed367e6cSBorislav Petkov }, 2922ed367e6cSBorislav Petkov { /* IRP */ 2923ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39), 2924ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0), 2925ed367e6cSBorislav Petkov }, 2926ed367e6cSBorislav Petkov { /* QPI0 Port 0 */ 2927ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32), 2928ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0), 2929ed367e6cSBorislav Petkov }, 2930ed367e6cSBorislav Petkov { /* QPI0 Port 1 */ 2931ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33), 2932ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 1), 2933ed367e6cSBorislav Petkov }, 2934ed367e6cSBorislav Petkov { /* QPI1 Port 2 */ 2935ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a), 2936ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 2), 2937ed367e6cSBorislav Petkov }, 2938ed367e6cSBorislav Petkov { /* R2PCIe */ 2939ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34), 2940ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0), 2941ed367e6cSBorislav Petkov }, 2942ed367e6cSBorislav Petkov { /* R3QPI0 Link 0 */ 2943ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36), 2944ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0), 2945ed367e6cSBorislav Petkov }, 2946ed367e6cSBorislav Petkov { /* R3QPI0 Link 1 */ 2947ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37), 2948ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 1), 2949ed367e6cSBorislav Petkov }, 2950ed367e6cSBorislav Petkov { /* R3QPI1 Link 2 */ 2951ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e), 2952ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 2), 2953ed367e6cSBorislav Petkov }, 2954ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 2955ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86), 2956ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2957ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER), 2958ed367e6cSBorislav Petkov }, 2959ed367e6cSBorislav Petkov { /* QPI Port 1 filter */ 2960ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96), 2961ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2962ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER), 2963ed367e6cSBorislav Petkov }, 2964ed367e6cSBorislav Petkov { /* PCU.3 (for Capability registers) */ 2965ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fc0), 2966ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2967ed367e6cSBorislav Petkov HSWEP_PCI_PCU_3), 2968ed367e6cSBorislav Petkov }, 2969ed367e6cSBorislav Petkov { /* end: all zeroes */ } 2970ed367e6cSBorislav Petkov }; 2971ed367e6cSBorislav Petkov 2972ed367e6cSBorislav Petkov static struct pci_driver hswep_uncore_pci_driver = { 2973ed367e6cSBorislav Petkov .name = "hswep_uncore", 2974ed367e6cSBorislav Petkov .id_table = hswep_uncore_pci_ids, 2975ed367e6cSBorislav Petkov }; 2976ed367e6cSBorislav Petkov 2977ed367e6cSBorislav Petkov int hswep_uncore_pci_init(void) 2978ed367e6cSBorislav Petkov { 297968ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x2f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 2980ed367e6cSBorislav Petkov if (ret) 2981ed367e6cSBorislav Petkov return ret; 2982ed367e6cSBorislav Petkov uncore_pci_uncores = hswep_pci_uncores; 2983ed367e6cSBorislav Petkov uncore_pci_driver = &hswep_uncore_pci_driver; 2984ed367e6cSBorislav Petkov return 0; 2985ed367e6cSBorislav Petkov } 2986ed367e6cSBorislav Petkov /* end of Haswell-EP uncore support */ 2987ed367e6cSBorislav Petkov 2988ed367e6cSBorislav Petkov /* BDX uncore support */ 2989ed367e6cSBorislav Petkov 2990ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_ubox = { 2991ed367e6cSBorislav Petkov .name = "ubox", 2992ed367e6cSBorislav Petkov .num_counters = 2, 2993ed367e6cSBorislav Petkov .num_boxes = 1, 2994ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2995ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2996ed367e6cSBorislav Petkov .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 2997ed367e6cSBorislav Petkov .event_ctl = HSWEP_U_MSR_PMON_CTL0, 2998ed367e6cSBorislav Petkov .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 2999ed367e6cSBorislav Petkov .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 3000ed367e6cSBorislav Petkov .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 3001ed367e6cSBorislav Petkov .num_shared_regs = 1, 3002ed367e6cSBorislav Petkov .ops = &ivbep_uncore_msr_ops, 3003ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_ubox_format_group, 3004ed367e6cSBorislav Petkov }; 3005ed367e6cSBorislav Petkov 3006ed367e6cSBorislav Petkov static struct event_constraint bdx_uncore_cbox_constraints[] = { 3007ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x3), 3008ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 3009ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 3010ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3e, 0x1), 3011ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 3012ed367e6cSBorislav Petkov }; 3013ed367e6cSBorislav Petkov 3014ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_cbox = { 3015ed367e6cSBorislav Petkov .name = "cbox", 3016ed367e6cSBorislav Petkov .num_counters = 4, 3017ed367e6cSBorislav Petkov .num_boxes = 24, 3018ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3019ed367e6cSBorislav Petkov .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 3020ed367e6cSBorislav Petkov .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 3021ed367e6cSBorislav Petkov .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 3022ed367e6cSBorislav Petkov .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 3023ed367e6cSBorislav Petkov .msr_offset = HSWEP_CBO_MSR_OFFSET, 3024ed367e6cSBorislav Petkov .num_shared_regs = 1, 3025ed367e6cSBorislav Petkov .constraints = bdx_uncore_cbox_constraints, 3026ed367e6cSBorislav Petkov .ops = &hswep_uncore_cbox_ops, 3027ed367e6cSBorislav Petkov .format_group = &hswep_uncore_cbox_format_group, 3028ed367e6cSBorislav Petkov }; 3029ed367e6cSBorislav Petkov 3030ed367e6cSBorislav Petkov static struct intel_uncore_type *bdx_msr_uncores[] = { 3031ed367e6cSBorislav Petkov &bdx_uncore_ubox, 3032ed367e6cSBorislav Petkov &bdx_uncore_cbox, 3033ed367e6cSBorislav Petkov &hswep_uncore_pcu, 3034ed367e6cSBorislav Petkov NULL, 3035ed367e6cSBorislav Petkov }; 3036ed367e6cSBorislav Petkov 3037ed367e6cSBorislav Petkov void bdx_uncore_cpu_init(void) 3038ed367e6cSBorislav Petkov { 3039ed367e6cSBorislav Petkov if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 3040ed367e6cSBorislav Petkov bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 3041ed367e6cSBorislav Petkov uncore_msr_uncores = bdx_msr_uncores; 3042ed367e6cSBorislav Petkov } 3043ed367e6cSBorislav Petkov 3044ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_ha = { 3045ed367e6cSBorislav Petkov .name = "ha", 3046ed367e6cSBorislav Petkov .num_counters = 4, 3047ed367e6cSBorislav Petkov .num_boxes = 2, 3048ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3049ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3050ed367e6cSBorislav Petkov }; 3051ed367e6cSBorislav Petkov 3052ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_imc = { 3053ed367e6cSBorislav Petkov .name = "imc", 305410e9e7bdSKan Liang .num_counters = 4, 3055ed367e6cSBorislav Petkov .num_boxes = 8, 3056ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3057ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 3058ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 3059ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 3060ed367e6cSBorislav Petkov .event_descs = hswep_uncore_imc_events, 3061ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3062ed367e6cSBorislav Petkov }; 3063ed367e6cSBorislav Petkov 3064ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_irp = { 3065ed367e6cSBorislav Petkov .name = "irp", 3066ed367e6cSBorislav Petkov .num_counters = 4, 3067ed367e6cSBorislav Petkov .num_boxes = 1, 3068ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3069ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3070ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3071ed367e6cSBorislav Petkov .ops = &hswep_uncore_irp_ops, 3072ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 3073ed367e6cSBorislav Petkov }; 3074ed367e6cSBorislav Petkov 3075ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_qpi = { 3076ed367e6cSBorislav Petkov .name = "qpi", 3077ed367e6cSBorislav Petkov .num_counters = 4, 3078ed367e6cSBorislav Petkov .num_boxes = 3, 3079ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3080ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 3081ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 3082ed367e6cSBorislav Petkov .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 3083ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3084ed367e6cSBorislav Petkov .num_shared_regs = 1, 3085ed367e6cSBorislav Petkov .ops = &snbep_uncore_qpi_ops, 3086ed367e6cSBorislav Petkov .format_group = &snbep_uncore_qpi_format_group, 3087ed367e6cSBorislav Petkov }; 3088ed367e6cSBorislav Petkov 3089ed367e6cSBorislav Petkov static struct event_constraint bdx_uncore_r2pcie_constraints[] = { 3090ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3091ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3092ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3093ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x1), 3094ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x1), 3095ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3096ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3097ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3098ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3099ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 3100ed367e6cSBorislav Petkov }; 3101ed367e6cSBorislav Petkov 3102ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_r2pcie = { 3103ed367e6cSBorislav Petkov .name = "r2pcie", 3104ed367e6cSBorislav Petkov .num_counters = 4, 3105ed367e6cSBorislav Petkov .num_boxes = 1, 3106ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3107ed367e6cSBorislav Petkov .constraints = bdx_uncore_r2pcie_constraints, 3108ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3109ed367e6cSBorislav Petkov }; 3110ed367e6cSBorislav Petkov 3111ed367e6cSBorislav Petkov static struct event_constraint bdx_uncore_r3qpi_constraints[] = { 3112ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x7), 3113ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x07, 0x7), 3114ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x08, 0x7), 3115ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x7), 3116ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), 3117ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), 3118ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3119ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3120ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3121ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 3122ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x15, 0x3), 3123ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), 3124ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 3125ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 3126ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 3127ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 3128ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 3129ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3130ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3131ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 3132ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3133ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3134ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 3135ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 3136ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 3137ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 3138ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 3139ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 3140ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 3141ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 3142ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 3143ed367e6cSBorislav Petkov }; 3144ed367e6cSBorislav Petkov 3145ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_r3qpi = { 3146ed367e6cSBorislav Petkov .name = "r3qpi", 3147ed367e6cSBorislav Petkov .num_counters = 3, 3148ed367e6cSBorislav Petkov .num_boxes = 3, 3149ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3150ed367e6cSBorislav Petkov .constraints = bdx_uncore_r3qpi_constraints, 3151ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3152ed367e6cSBorislav Petkov }; 3153ed367e6cSBorislav Petkov 3154ed367e6cSBorislav Petkov enum { 3155ed367e6cSBorislav Petkov BDX_PCI_UNCORE_HA, 3156ed367e6cSBorislav Petkov BDX_PCI_UNCORE_IMC, 3157ed367e6cSBorislav Petkov BDX_PCI_UNCORE_IRP, 3158ed367e6cSBorislav Petkov BDX_PCI_UNCORE_QPI, 3159ed367e6cSBorislav Petkov BDX_PCI_UNCORE_R2PCIE, 3160ed367e6cSBorislav Petkov BDX_PCI_UNCORE_R3QPI, 3161ed367e6cSBorislav Petkov }; 3162ed367e6cSBorislav Petkov 3163ed367e6cSBorislav Petkov static struct intel_uncore_type *bdx_pci_uncores[] = { 3164ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha, 3165ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc, 3166ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp, 3167ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_QPI] = &bdx_uncore_qpi, 3168ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie, 3169ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_R3QPI] = &bdx_uncore_r3qpi, 3170ed367e6cSBorislav Petkov NULL, 3171ed367e6cSBorislav Petkov }; 3172ed367e6cSBorislav Petkov 3173ed367e6cSBorislav Petkov static const struct pci_device_id bdx_uncore_pci_ids[] = { 3174ed367e6cSBorislav Petkov { /* Home Agent 0 */ 3175ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30), 3176ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0), 3177ed367e6cSBorislav Petkov }, 3178ed367e6cSBorislav Petkov { /* Home Agent 1 */ 3179ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38), 3180ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 1), 3181ed367e6cSBorislav Petkov }, 3182ed367e6cSBorislav Petkov { /* MC0 Channel 0 */ 3183ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0), 3184ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0), 3185ed367e6cSBorislav Petkov }, 3186ed367e6cSBorislav Petkov { /* MC0 Channel 1 */ 3187ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1), 3188ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1), 3189ed367e6cSBorislav Petkov }, 3190ed367e6cSBorislav Petkov { /* MC0 Channel 2 */ 3191ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4), 3192ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 2), 3193ed367e6cSBorislav Petkov }, 3194ed367e6cSBorislav Petkov { /* MC0 Channel 3 */ 3195ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5), 3196ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 3), 3197ed367e6cSBorislav Petkov }, 3198ed367e6cSBorislav Petkov { /* MC1 Channel 0 */ 3199ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0), 3200ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 4), 3201ed367e6cSBorislav Petkov }, 3202ed367e6cSBorislav Petkov { /* MC1 Channel 1 */ 3203ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1), 3204ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 5), 3205ed367e6cSBorislav Petkov }, 3206ed367e6cSBorislav Petkov { /* MC1 Channel 2 */ 3207ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4), 3208ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 6), 3209ed367e6cSBorislav Petkov }, 3210ed367e6cSBorislav Petkov { /* MC1 Channel 3 */ 3211ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5), 3212ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 7), 3213ed367e6cSBorislav Petkov }, 3214ed367e6cSBorislav Petkov { /* IRP */ 3215ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39), 3216ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0), 3217ed367e6cSBorislav Petkov }, 3218ed367e6cSBorislav Petkov { /* QPI0 Port 0 */ 3219ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32), 3220ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0), 3221ed367e6cSBorislav Petkov }, 3222ed367e6cSBorislav Petkov { /* QPI0 Port 1 */ 3223ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33), 3224ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 1), 3225ed367e6cSBorislav Petkov }, 3226ed367e6cSBorislav Petkov { /* QPI1 Port 2 */ 3227ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a), 3228ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 2), 3229ed367e6cSBorislav Petkov }, 3230ed367e6cSBorislav Petkov { /* R2PCIe */ 3231ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34), 3232ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0), 3233ed367e6cSBorislav Petkov }, 3234ed367e6cSBorislav Petkov { /* R3QPI0 Link 0 */ 3235ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36), 3236ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0), 3237ed367e6cSBorislav Petkov }, 3238ed367e6cSBorislav Petkov { /* R3QPI0 Link 1 */ 3239ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37), 3240ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 1), 3241ed367e6cSBorislav Petkov }, 3242ed367e6cSBorislav Petkov { /* R3QPI1 Link 2 */ 3243ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e), 3244ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 2), 3245ed367e6cSBorislav Petkov }, 3246ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 3247ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86), 3248ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 0), 3249ed367e6cSBorislav Petkov }, 3250ed367e6cSBorislav Petkov { /* QPI Port 1 filter */ 3251ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96), 3252ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1), 3253ed367e6cSBorislav Petkov }, 3254ed367e6cSBorislav Petkov { /* QPI Port 2 filter */ 3255ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46), 3256ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2), 3257ed367e6cSBorislav Petkov }, 3258ed367e6cSBorislav Petkov { /* end: all zeroes */ } 3259ed367e6cSBorislav Petkov }; 3260ed367e6cSBorislav Petkov 3261ed367e6cSBorislav Petkov static struct pci_driver bdx_uncore_pci_driver = { 3262ed367e6cSBorislav Petkov .name = "bdx_uncore", 3263ed367e6cSBorislav Petkov .id_table = bdx_uncore_pci_ids, 3264ed367e6cSBorislav Petkov }; 3265ed367e6cSBorislav Petkov 3266ed367e6cSBorislav Petkov int bdx_uncore_pci_init(void) 3267ed367e6cSBorislav Petkov { 326868ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x6f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 3269ed367e6cSBorislav Petkov 3270ed367e6cSBorislav Petkov if (ret) 3271ed367e6cSBorislav Petkov return ret; 3272ed367e6cSBorislav Petkov uncore_pci_uncores = bdx_pci_uncores; 3273ed367e6cSBorislav Petkov uncore_pci_driver = &bdx_uncore_pci_driver; 3274ed367e6cSBorislav Petkov return 0; 3275ed367e6cSBorislav Petkov } 3276ed367e6cSBorislav Petkov 3277ed367e6cSBorislav Petkov /* end of BDX uncore support */ 3278cd34cd97SKan Liang 3279cd34cd97SKan Liang /* SKX uncore support */ 3280cd34cd97SKan Liang 3281cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_ubox = { 3282cd34cd97SKan Liang .name = "ubox", 3283cd34cd97SKan Liang .num_counters = 2, 3284cd34cd97SKan Liang .num_boxes = 1, 3285cd34cd97SKan Liang .perf_ctr_bits = 48, 3286cd34cd97SKan Liang .fixed_ctr_bits = 48, 3287cd34cd97SKan Liang .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 3288cd34cd97SKan Liang .event_ctl = HSWEP_U_MSR_PMON_CTL0, 3289cd34cd97SKan Liang .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 3290cd34cd97SKan Liang .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 3291cd34cd97SKan Liang .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 3292cd34cd97SKan Liang .ops = &ivbep_uncore_msr_ops, 3293cd34cd97SKan Liang .format_group = &ivbep_uncore_ubox_format_group, 3294cd34cd97SKan Liang }; 3295cd34cd97SKan Liang 3296cd34cd97SKan Liang static struct attribute *skx_uncore_cha_formats_attr[] = { 3297cd34cd97SKan Liang &format_attr_event.attr, 3298cd34cd97SKan Liang &format_attr_umask.attr, 3299cd34cd97SKan Liang &format_attr_edge.attr, 3300cd34cd97SKan Liang &format_attr_tid_en.attr, 3301cd34cd97SKan Liang &format_attr_inv.attr, 3302cd34cd97SKan Liang &format_attr_thresh8.attr, 3303cd34cd97SKan Liang &format_attr_filter_tid4.attr, 3304cd34cd97SKan Liang &format_attr_filter_state5.attr, 3305cd34cd97SKan Liang &format_attr_filter_rem.attr, 3306cd34cd97SKan Liang &format_attr_filter_loc.attr, 3307cd34cd97SKan Liang &format_attr_filter_nm.attr, 3308cd34cd97SKan Liang &format_attr_filter_all_op.attr, 3309cd34cd97SKan Liang &format_attr_filter_not_nm.attr, 3310cd34cd97SKan Liang &format_attr_filter_opc_0.attr, 3311cd34cd97SKan Liang &format_attr_filter_opc_1.attr, 3312cd34cd97SKan Liang &format_attr_filter_nc.attr, 3313cd34cd97SKan Liang &format_attr_filter_isoc.attr, 3314cd34cd97SKan Liang NULL, 3315cd34cd97SKan Liang }; 3316cd34cd97SKan Liang 3317cd34cd97SKan Liang static struct attribute_group skx_uncore_chabox_format_group = { 3318cd34cd97SKan Liang .name = "format", 3319cd34cd97SKan Liang .attrs = skx_uncore_cha_formats_attr, 3320cd34cd97SKan Liang }; 3321cd34cd97SKan Liang 3322cd34cd97SKan Liang static struct event_constraint skx_uncore_chabox_constraints[] = { 3323cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 3324cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 3325cd34cd97SKan Liang EVENT_CONSTRAINT_END 3326cd34cd97SKan Liang }; 3327cd34cd97SKan Liang 3328cd34cd97SKan Liang static struct extra_reg skx_uncore_cha_extra_regs[] = { 3329cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 3330cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 3331cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 3332cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 3333c3f02682SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x3134, 0xffff, 0x4), 3334c3f02682SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4), 33358aa7b7b4SStephane Eranian SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8), 33368aa7b7b4SStephane Eranian SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8), 3337ba883b4aSStephane Eranian EVENT_EXTRA_END 3338cd34cd97SKan Liang }; 3339cd34cd97SKan Liang 3340cd34cd97SKan Liang static u64 skx_cha_filter_mask(int fields) 3341cd34cd97SKan Liang { 3342cd34cd97SKan Liang u64 mask = 0; 3343cd34cd97SKan Liang 3344cd34cd97SKan Liang if (fields & 0x1) 3345cd34cd97SKan Liang mask |= SKX_CHA_MSR_PMON_BOX_FILTER_TID; 3346cd34cd97SKan Liang if (fields & 0x2) 3347cd34cd97SKan Liang mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LINK; 3348cd34cd97SKan Liang if (fields & 0x4) 3349cd34cd97SKan Liang mask |= SKX_CHA_MSR_PMON_BOX_FILTER_STATE; 33508aa7b7b4SStephane Eranian if (fields & 0x8) { 33518aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_REM; 33528aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LOC; 33538aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC; 33548aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NM; 33558aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM; 33568aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC0; 33578aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC1; 33588aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NC; 33598aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ISOC; 33608aa7b7b4SStephane Eranian } 3361cd34cd97SKan Liang return mask; 3362cd34cd97SKan Liang } 3363cd34cd97SKan Liang 3364cd34cd97SKan Liang static struct event_constraint * 3365cd34cd97SKan Liang skx_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 3366cd34cd97SKan Liang { 3367cd34cd97SKan Liang return __snbep_cbox_get_constraint(box, event, skx_cha_filter_mask); 3368cd34cd97SKan Liang } 3369cd34cd97SKan Liang 3370cd34cd97SKan Liang static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 3371cd34cd97SKan Liang { 3372cd34cd97SKan Liang struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 3373cd34cd97SKan Liang struct extra_reg *er; 3374cd34cd97SKan Liang int idx = 0; 3375cd34cd97SKan Liang 3376cd34cd97SKan Liang for (er = skx_uncore_cha_extra_regs; er->msr; er++) { 3377cd34cd97SKan Liang if (er->event != (event->hw.config & er->config_mask)) 3378cd34cd97SKan Liang continue; 3379cd34cd97SKan Liang idx |= er->idx; 3380cd34cd97SKan Liang } 3381cd34cd97SKan Liang 3382cd34cd97SKan Liang if (idx) { 3383cd34cd97SKan Liang reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 3384cd34cd97SKan Liang HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 3385cd34cd97SKan Liang reg1->config = event->attr.config1 & skx_cha_filter_mask(idx); 3386cd34cd97SKan Liang reg1->idx = idx; 3387cd34cd97SKan Liang } 3388cd34cd97SKan Liang return 0; 3389cd34cd97SKan Liang } 3390cd34cd97SKan Liang 3391cd34cd97SKan Liang static struct intel_uncore_ops skx_uncore_chabox_ops = { 3392cd34cd97SKan Liang /* There is no frz_en for chabox ctl */ 3393cd34cd97SKan Liang .init_box = ivbep_uncore_msr_init_box, 3394cd34cd97SKan Liang .disable_box = snbep_uncore_msr_disable_box, 3395cd34cd97SKan Liang .enable_box = snbep_uncore_msr_enable_box, 3396cd34cd97SKan Liang .disable_event = snbep_uncore_msr_disable_event, 3397cd34cd97SKan Liang .enable_event = hswep_cbox_enable_event, 3398cd34cd97SKan Liang .read_counter = uncore_msr_read_counter, 3399cd34cd97SKan Liang .hw_config = skx_cha_hw_config, 3400cd34cd97SKan Liang .get_constraint = skx_cha_get_constraint, 3401cd34cd97SKan Liang .put_constraint = snbep_cbox_put_constraint, 3402cd34cd97SKan Liang }; 3403cd34cd97SKan Liang 3404cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_chabox = { 3405cd34cd97SKan Liang .name = "cha", 3406cd34cd97SKan Liang .num_counters = 4, 3407cd34cd97SKan Liang .perf_ctr_bits = 48, 3408cd34cd97SKan Liang .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 3409cd34cd97SKan Liang .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 3410cd34cd97SKan Liang .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 3411cd34cd97SKan Liang .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 3412cd34cd97SKan Liang .msr_offset = HSWEP_CBO_MSR_OFFSET, 3413cd34cd97SKan Liang .num_shared_regs = 1, 3414cd34cd97SKan Liang .constraints = skx_uncore_chabox_constraints, 3415cd34cd97SKan Liang .ops = &skx_uncore_chabox_ops, 3416cd34cd97SKan Liang .format_group = &skx_uncore_chabox_format_group, 3417cd34cd97SKan Liang }; 3418cd34cd97SKan Liang 3419cd34cd97SKan Liang static struct attribute *skx_uncore_iio_formats_attr[] = { 3420cd34cd97SKan Liang &format_attr_event.attr, 3421cd34cd97SKan Liang &format_attr_umask.attr, 3422cd34cd97SKan Liang &format_attr_edge.attr, 3423cd34cd97SKan Liang &format_attr_inv.attr, 3424cd34cd97SKan Liang &format_attr_thresh9.attr, 3425cd34cd97SKan Liang &format_attr_ch_mask.attr, 3426cd34cd97SKan Liang &format_attr_fc_mask.attr, 3427cd34cd97SKan Liang NULL, 3428cd34cd97SKan Liang }; 3429cd34cd97SKan Liang 3430cd34cd97SKan Liang static struct attribute_group skx_uncore_iio_format_group = { 3431cd34cd97SKan Liang .name = "format", 3432cd34cd97SKan Liang .attrs = skx_uncore_iio_formats_attr, 3433cd34cd97SKan Liang }; 3434cd34cd97SKan Liang 3435cd34cd97SKan Liang static struct event_constraint skx_uncore_iio_constraints[] = { 3436cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x83, 0x3), 3437cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x88, 0xc), 3438cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x95, 0xc), 3439cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0xc0, 0xc), 3440cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0xc5, 0xc), 3441cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0xd4, 0xc), 3442cd34cd97SKan Liang EVENT_CONSTRAINT_END 3443cd34cd97SKan Liang }; 3444cd34cd97SKan Liang 3445cd34cd97SKan Liang static void skx_iio_enable_event(struct intel_uncore_box *box, 3446cd34cd97SKan Liang struct perf_event *event) 3447cd34cd97SKan Liang { 3448cd34cd97SKan Liang struct hw_perf_event *hwc = &event->hw; 3449cd34cd97SKan Liang 3450cd34cd97SKan Liang wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 3451cd34cd97SKan Liang } 3452cd34cd97SKan Liang 3453cd34cd97SKan Liang static struct intel_uncore_ops skx_uncore_iio_ops = { 3454cd34cd97SKan Liang .init_box = ivbep_uncore_msr_init_box, 3455cd34cd97SKan Liang .disable_box = snbep_uncore_msr_disable_box, 3456cd34cd97SKan Liang .enable_box = snbep_uncore_msr_enable_box, 3457cd34cd97SKan Liang .disable_event = snbep_uncore_msr_disable_event, 3458cd34cd97SKan Liang .enable_event = skx_iio_enable_event, 3459cd34cd97SKan Liang .read_counter = uncore_msr_read_counter, 3460cd34cd97SKan Liang }; 3461cd34cd97SKan Liang 3462cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_iio = { 3463cd34cd97SKan Liang .name = "iio", 3464cd34cd97SKan Liang .num_counters = 4, 3465cd34cd97SKan Liang .num_boxes = 5, 3466cd34cd97SKan Liang .perf_ctr_bits = 48, 3467cd34cd97SKan Liang .event_ctl = SKX_IIO0_MSR_PMON_CTL0, 3468cd34cd97SKan Liang .perf_ctr = SKX_IIO0_MSR_PMON_CTR0, 3469cd34cd97SKan Liang .event_mask = SKX_IIO_PMON_RAW_EVENT_MASK, 3470cd34cd97SKan Liang .event_mask_ext = SKX_IIO_PMON_RAW_EVENT_MASK_EXT, 3471cd34cd97SKan Liang .box_ctl = SKX_IIO0_MSR_PMON_BOX_CTL, 3472cd34cd97SKan Liang .msr_offset = SKX_IIO_MSR_OFFSET, 3473cd34cd97SKan Liang .constraints = skx_uncore_iio_constraints, 3474cd34cd97SKan Liang .ops = &skx_uncore_iio_ops, 3475cd34cd97SKan Liang .format_group = &skx_uncore_iio_format_group, 3476cd34cd97SKan Liang }; 3477cd34cd97SKan Liang 3478cd34cd97SKan Liang static struct attribute *skx_uncore_formats_attr[] = { 3479cd34cd97SKan Liang &format_attr_event.attr, 3480cd34cd97SKan Liang &format_attr_umask.attr, 3481cd34cd97SKan Liang &format_attr_edge.attr, 3482cd34cd97SKan Liang &format_attr_inv.attr, 3483cd34cd97SKan Liang &format_attr_thresh8.attr, 3484cd34cd97SKan Liang NULL, 3485cd34cd97SKan Liang }; 3486cd34cd97SKan Liang 3487cd34cd97SKan Liang static struct attribute_group skx_uncore_format_group = { 3488cd34cd97SKan Liang .name = "format", 3489cd34cd97SKan Liang .attrs = skx_uncore_formats_attr, 3490cd34cd97SKan Liang }; 3491cd34cd97SKan Liang 3492cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_irp = { 3493cd34cd97SKan Liang .name = "irp", 3494cd34cd97SKan Liang .num_counters = 2, 3495cd34cd97SKan Liang .num_boxes = 5, 3496cd34cd97SKan Liang .perf_ctr_bits = 48, 3497cd34cd97SKan Liang .event_ctl = SKX_IRP0_MSR_PMON_CTL0, 3498cd34cd97SKan Liang .perf_ctr = SKX_IRP0_MSR_PMON_CTR0, 3499cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3500cd34cd97SKan Liang .box_ctl = SKX_IRP0_MSR_PMON_BOX_CTL, 3501cd34cd97SKan Liang .msr_offset = SKX_IRP_MSR_OFFSET, 3502cd34cd97SKan Liang .ops = &skx_uncore_iio_ops, 3503cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3504cd34cd97SKan Liang }; 3505cd34cd97SKan Liang 3506bab4e569SKan Liang static struct attribute *skx_uncore_pcu_formats_attr[] = { 3507bab4e569SKan Liang &format_attr_event.attr, 3508bab4e569SKan Liang &format_attr_umask.attr, 3509bab4e569SKan Liang &format_attr_edge.attr, 3510bab4e569SKan Liang &format_attr_inv.attr, 3511bab4e569SKan Liang &format_attr_thresh8.attr, 3512bab4e569SKan Liang &format_attr_occ_invert.attr, 3513bab4e569SKan Liang &format_attr_occ_edge_det.attr, 3514bab4e569SKan Liang &format_attr_filter_band0.attr, 3515bab4e569SKan Liang &format_attr_filter_band1.attr, 3516bab4e569SKan Liang &format_attr_filter_band2.attr, 3517bab4e569SKan Liang &format_attr_filter_band3.attr, 3518bab4e569SKan Liang NULL, 3519bab4e569SKan Liang }; 3520bab4e569SKan Liang 3521bab4e569SKan Liang static struct attribute_group skx_uncore_pcu_format_group = { 3522bab4e569SKan Liang .name = "format", 3523bab4e569SKan Liang .attrs = skx_uncore_pcu_formats_attr, 3524bab4e569SKan Liang }; 3525bab4e569SKan Liang 3526cd34cd97SKan Liang static struct intel_uncore_ops skx_uncore_pcu_ops = { 3527cd34cd97SKan Liang IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 3528cd34cd97SKan Liang .hw_config = hswep_pcu_hw_config, 3529cd34cd97SKan Liang .get_constraint = snbep_pcu_get_constraint, 3530cd34cd97SKan Liang .put_constraint = snbep_pcu_put_constraint, 3531cd34cd97SKan Liang }; 3532cd34cd97SKan Liang 3533cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_pcu = { 3534cd34cd97SKan Liang .name = "pcu", 3535cd34cd97SKan Liang .num_counters = 4, 3536cd34cd97SKan Liang .num_boxes = 1, 3537cd34cd97SKan Liang .perf_ctr_bits = 48, 3538cd34cd97SKan Liang .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 3539cd34cd97SKan Liang .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 3540cd34cd97SKan Liang .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 3541cd34cd97SKan Liang .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 3542cd34cd97SKan Liang .num_shared_regs = 1, 3543cd34cd97SKan Liang .ops = &skx_uncore_pcu_ops, 3544bab4e569SKan Liang .format_group = &skx_uncore_pcu_format_group, 3545cd34cd97SKan Liang }; 3546cd34cd97SKan Liang 3547cd34cd97SKan Liang static struct intel_uncore_type *skx_msr_uncores[] = { 3548cd34cd97SKan Liang &skx_uncore_ubox, 3549cd34cd97SKan Liang &skx_uncore_chabox, 3550cd34cd97SKan Liang &skx_uncore_iio, 3551cd34cd97SKan Liang &skx_uncore_irp, 3552cd34cd97SKan Liang &skx_uncore_pcu, 3553cd34cd97SKan Liang NULL, 3554cd34cd97SKan Liang }; 3555cd34cd97SKan Liang 3556cd34cd97SKan Liang static int skx_count_chabox(void) 3557cd34cd97SKan Liang { 3558cd34cd97SKan Liang struct pci_dev *chabox_dev = NULL; 3559cd34cd97SKan Liang int bus, count = 0; 3560cd34cd97SKan Liang 3561cd34cd97SKan Liang while (1) { 3562cd34cd97SKan Liang chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev); 3563cd34cd97SKan Liang if (!chabox_dev) 3564cd34cd97SKan Liang break; 3565cd34cd97SKan Liang if (count == 0) 3566cd34cd97SKan Liang bus = chabox_dev->bus->number; 3567cd34cd97SKan Liang if (bus != chabox_dev->bus->number) 3568cd34cd97SKan Liang break; 3569cd34cd97SKan Liang count++; 3570cd34cd97SKan Liang } 3571cd34cd97SKan Liang 3572cd34cd97SKan Liang pci_dev_put(chabox_dev); 3573cd34cd97SKan Liang return count; 3574cd34cd97SKan Liang } 3575cd34cd97SKan Liang 3576cd34cd97SKan Liang void skx_uncore_cpu_init(void) 3577cd34cd97SKan Liang { 3578cd34cd97SKan Liang skx_uncore_chabox.num_boxes = skx_count_chabox(); 3579cd34cd97SKan Liang uncore_msr_uncores = skx_msr_uncores; 3580cd34cd97SKan Liang } 3581cd34cd97SKan Liang 3582cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_imc = { 3583cd34cd97SKan Liang .name = "imc", 3584cd34cd97SKan Liang .num_counters = 4, 3585cd34cd97SKan Liang .num_boxes = 6, 3586cd34cd97SKan Liang .perf_ctr_bits = 48, 3587cd34cd97SKan Liang .fixed_ctr_bits = 48, 3588cd34cd97SKan Liang .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 3589cd34cd97SKan Liang .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 3590cd34cd97SKan Liang .event_descs = hswep_uncore_imc_events, 3591cd34cd97SKan Liang .perf_ctr = SNBEP_PCI_PMON_CTR0, 3592cd34cd97SKan Liang .event_ctl = SNBEP_PCI_PMON_CTL0, 3593cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3594cd34cd97SKan Liang .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3595cd34cd97SKan Liang .ops = &ivbep_uncore_pci_ops, 3596cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3597cd34cd97SKan Liang }; 3598cd34cd97SKan Liang 3599cd34cd97SKan Liang static struct attribute *skx_upi_uncore_formats_attr[] = { 3600cd34cd97SKan Liang &format_attr_event_ext.attr, 3601cd34cd97SKan Liang &format_attr_umask_ext.attr, 3602cd34cd97SKan Liang &format_attr_edge.attr, 3603cd34cd97SKan Liang &format_attr_inv.attr, 3604cd34cd97SKan Liang &format_attr_thresh8.attr, 3605cd34cd97SKan Liang NULL, 3606cd34cd97SKan Liang }; 3607cd34cd97SKan Liang 3608cd34cd97SKan Liang static struct attribute_group skx_upi_uncore_format_group = { 3609cd34cd97SKan Liang .name = "format", 3610cd34cd97SKan Liang .attrs = skx_upi_uncore_formats_attr, 3611cd34cd97SKan Liang }; 3612cd34cd97SKan Liang 3613cd34cd97SKan Liang static void skx_upi_uncore_pci_init_box(struct intel_uncore_box *box) 3614cd34cd97SKan Liang { 3615cd34cd97SKan Liang struct pci_dev *pdev = box->pci_dev; 3616cd34cd97SKan Liang 3617cd34cd97SKan Liang __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 3618cd34cd97SKan Liang pci_write_config_dword(pdev, SKX_UPI_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 3619cd34cd97SKan Liang } 3620cd34cd97SKan Liang 3621cd34cd97SKan Liang static struct intel_uncore_ops skx_upi_uncore_pci_ops = { 3622cd34cd97SKan Liang .init_box = skx_upi_uncore_pci_init_box, 3623cd34cd97SKan Liang .disable_box = snbep_uncore_pci_disable_box, 3624cd34cd97SKan Liang .enable_box = snbep_uncore_pci_enable_box, 3625cd34cd97SKan Liang .disable_event = snbep_uncore_pci_disable_event, 3626cd34cd97SKan Liang .enable_event = snbep_uncore_pci_enable_event, 3627cd34cd97SKan Liang .read_counter = snbep_uncore_pci_read_counter, 3628cd34cd97SKan Liang }; 3629cd34cd97SKan Liang 3630cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_upi = { 3631cd34cd97SKan Liang .name = "upi", 3632cd34cd97SKan Liang .num_counters = 4, 3633cd34cd97SKan Liang .num_boxes = 3, 3634cd34cd97SKan Liang .perf_ctr_bits = 48, 3635cd34cd97SKan Liang .perf_ctr = SKX_UPI_PCI_PMON_CTR0, 3636cd34cd97SKan Liang .event_ctl = SKX_UPI_PCI_PMON_CTL0, 3637b3625980SStephane Eranian .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3638b3625980SStephane Eranian .event_mask_ext = SKX_UPI_CTL_UMASK_EXT, 3639cd34cd97SKan Liang .box_ctl = SKX_UPI_PCI_PMON_BOX_CTL, 3640cd34cd97SKan Liang .ops = &skx_upi_uncore_pci_ops, 3641cd34cd97SKan Liang .format_group = &skx_upi_uncore_format_group, 3642cd34cd97SKan Liang }; 3643cd34cd97SKan Liang 3644cd34cd97SKan Liang static void skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box) 3645cd34cd97SKan Liang { 3646cd34cd97SKan Liang struct pci_dev *pdev = box->pci_dev; 3647cd34cd97SKan Liang 3648cd34cd97SKan Liang __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 3649cd34cd97SKan Liang pci_write_config_dword(pdev, SKX_M2M_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 3650cd34cd97SKan Liang } 3651cd34cd97SKan Liang 3652cd34cd97SKan Liang static struct intel_uncore_ops skx_m2m_uncore_pci_ops = { 3653cd34cd97SKan Liang .init_box = skx_m2m_uncore_pci_init_box, 3654cd34cd97SKan Liang .disable_box = snbep_uncore_pci_disable_box, 3655cd34cd97SKan Liang .enable_box = snbep_uncore_pci_enable_box, 3656cd34cd97SKan Liang .disable_event = snbep_uncore_pci_disable_event, 3657cd34cd97SKan Liang .enable_event = snbep_uncore_pci_enable_event, 3658cd34cd97SKan Liang .read_counter = snbep_uncore_pci_read_counter, 3659cd34cd97SKan Liang }; 3660cd34cd97SKan Liang 3661cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_m2m = { 3662cd34cd97SKan Liang .name = "m2m", 3663cd34cd97SKan Liang .num_counters = 4, 3664cd34cd97SKan Liang .num_boxes = 2, 3665cd34cd97SKan Liang .perf_ctr_bits = 48, 3666cd34cd97SKan Liang .perf_ctr = SKX_M2M_PCI_PMON_CTR0, 3667cd34cd97SKan Liang .event_ctl = SKX_M2M_PCI_PMON_CTL0, 3668cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3669cd34cd97SKan Liang .box_ctl = SKX_M2M_PCI_PMON_BOX_CTL, 3670cd34cd97SKan Liang .ops = &skx_m2m_uncore_pci_ops, 3671cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3672cd34cd97SKan Liang }; 3673cd34cd97SKan Liang 3674cd34cd97SKan Liang static struct event_constraint skx_uncore_m2pcie_constraints[] = { 3675cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 3676cd34cd97SKan Liang EVENT_CONSTRAINT_END 3677cd34cd97SKan Liang }; 3678cd34cd97SKan Liang 3679cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_m2pcie = { 3680cd34cd97SKan Liang .name = "m2pcie", 3681cd34cd97SKan Liang .num_counters = 4, 3682cd34cd97SKan Liang .num_boxes = 4, 3683cd34cd97SKan Liang .perf_ctr_bits = 48, 3684cd34cd97SKan Liang .constraints = skx_uncore_m2pcie_constraints, 3685cd34cd97SKan Liang .perf_ctr = SNBEP_PCI_PMON_CTR0, 3686cd34cd97SKan Liang .event_ctl = SNBEP_PCI_PMON_CTL0, 3687cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3688cd34cd97SKan Liang .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3689cd34cd97SKan Liang .ops = &ivbep_uncore_pci_ops, 3690cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3691cd34cd97SKan Liang }; 3692cd34cd97SKan Liang 3693cd34cd97SKan Liang static struct event_constraint skx_uncore_m3upi_constraints[] = { 3694cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x1d, 0x1), 3695cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x1e, 0x1), 3696cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x40, 0x7), 3697cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x4e, 0x7), 3698cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x4f, 0x7), 3699cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x50, 0x7), 3700cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x51, 0x7), 3701cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x52, 0x7), 3702cd34cd97SKan Liang EVENT_CONSTRAINT_END 3703cd34cd97SKan Liang }; 3704cd34cd97SKan Liang 3705cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_m3upi = { 3706cd34cd97SKan Liang .name = "m3upi", 3707cd34cd97SKan Liang .num_counters = 3, 3708cd34cd97SKan Liang .num_boxes = 3, 3709cd34cd97SKan Liang .perf_ctr_bits = 48, 3710cd34cd97SKan Liang .constraints = skx_uncore_m3upi_constraints, 3711cd34cd97SKan Liang .perf_ctr = SNBEP_PCI_PMON_CTR0, 3712cd34cd97SKan Liang .event_ctl = SNBEP_PCI_PMON_CTL0, 3713cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3714cd34cd97SKan Liang .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3715cd34cd97SKan Liang .ops = &ivbep_uncore_pci_ops, 3716cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3717cd34cd97SKan Liang }; 3718cd34cd97SKan Liang 3719cd34cd97SKan Liang enum { 3720cd34cd97SKan Liang SKX_PCI_UNCORE_IMC, 3721cd34cd97SKan Liang SKX_PCI_UNCORE_M2M, 3722cd34cd97SKan Liang SKX_PCI_UNCORE_UPI, 3723cd34cd97SKan Liang SKX_PCI_UNCORE_M2PCIE, 3724cd34cd97SKan Liang SKX_PCI_UNCORE_M3UPI, 3725cd34cd97SKan Liang }; 3726cd34cd97SKan Liang 3727cd34cd97SKan Liang static struct intel_uncore_type *skx_pci_uncores[] = { 3728cd34cd97SKan Liang [SKX_PCI_UNCORE_IMC] = &skx_uncore_imc, 3729cd34cd97SKan Liang [SKX_PCI_UNCORE_M2M] = &skx_uncore_m2m, 3730cd34cd97SKan Liang [SKX_PCI_UNCORE_UPI] = &skx_uncore_upi, 3731cd34cd97SKan Liang [SKX_PCI_UNCORE_M2PCIE] = &skx_uncore_m2pcie, 3732cd34cd97SKan Liang [SKX_PCI_UNCORE_M3UPI] = &skx_uncore_m3upi, 3733cd34cd97SKan Liang NULL, 3734cd34cd97SKan Liang }; 3735cd34cd97SKan Liang 3736cd34cd97SKan Liang static const struct pci_device_id skx_uncore_pci_ids[] = { 3737cd34cd97SKan Liang { /* MC0 Channel 0 */ 3738cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042), 3739cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 2, SKX_PCI_UNCORE_IMC, 0), 3740cd34cd97SKan Liang }, 3741cd34cd97SKan Liang { /* MC0 Channel 1 */ 3742cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046), 3743cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 6, SKX_PCI_UNCORE_IMC, 1), 3744cd34cd97SKan Liang }, 3745cd34cd97SKan Liang { /* MC0 Channel 2 */ 3746cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a), 3747cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 2, SKX_PCI_UNCORE_IMC, 2), 3748cd34cd97SKan Liang }, 3749cd34cd97SKan Liang { /* MC1 Channel 0 */ 3750cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042), 3751cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 2, SKX_PCI_UNCORE_IMC, 3), 3752cd34cd97SKan Liang }, 3753cd34cd97SKan Liang { /* MC1 Channel 1 */ 3754cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046), 3755cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 6, SKX_PCI_UNCORE_IMC, 4), 3756cd34cd97SKan Liang }, 3757cd34cd97SKan Liang { /* MC1 Channel 2 */ 3758cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a), 3759cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 2, SKX_PCI_UNCORE_IMC, 5), 3760cd34cd97SKan Liang }, 3761cd34cd97SKan Liang { /* M2M0 */ 3762cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066), 3763cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 0, SKX_PCI_UNCORE_M2M, 0), 3764cd34cd97SKan Liang }, 3765cd34cd97SKan Liang { /* M2M1 */ 3766cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066), 3767cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 0, SKX_PCI_UNCORE_M2M, 1), 3768cd34cd97SKan Liang }, 3769cd34cd97SKan Liang { /* UPI0 Link 0 */ 3770cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 3771cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, SKX_PCI_UNCORE_UPI, 0), 3772cd34cd97SKan Liang }, 3773cd34cd97SKan Liang { /* UPI0 Link 1 */ 3774cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 3775cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, SKX_PCI_UNCORE_UPI, 1), 3776cd34cd97SKan Liang }, 3777cd34cd97SKan Liang { /* UPI1 Link 2 */ 3778cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 3779cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, SKX_PCI_UNCORE_UPI, 2), 3780cd34cd97SKan Liang }, 3781cd34cd97SKan Liang { /* M2PCIe 0 */ 3782cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3783cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 1, SKX_PCI_UNCORE_M2PCIE, 0), 3784cd34cd97SKan Liang }, 3785cd34cd97SKan Liang { /* M2PCIe 1 */ 3786cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3787cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 1, SKX_PCI_UNCORE_M2PCIE, 1), 3788cd34cd97SKan Liang }, 3789cd34cd97SKan Liang { /* M2PCIe 2 */ 3790cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3791cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(23, 1, SKX_PCI_UNCORE_M2PCIE, 2), 3792cd34cd97SKan Liang }, 3793cd34cd97SKan Liang { /* M2PCIe 3 */ 3794cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3795cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 5, SKX_PCI_UNCORE_M2PCIE, 3), 3796cd34cd97SKan Liang }, 3797cd34cd97SKan Liang { /* M3UPI0 Link 0 */ 3798cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204C), 3799cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 0, SKX_PCI_UNCORE_M3UPI, 0), 3800cd34cd97SKan Liang }, 3801cd34cd97SKan Liang { /* M3UPI0 Link 1 */ 3802cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D), 3803cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 1, SKX_PCI_UNCORE_M3UPI, 1), 3804cd34cd97SKan Liang }, 3805cd34cd97SKan Liang { /* M3UPI1 Link 2 */ 3806cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204C), 3807cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 4, SKX_PCI_UNCORE_M3UPI, 2), 3808cd34cd97SKan Liang }, 3809cd34cd97SKan Liang { /* end: all zeroes */ } 3810cd34cd97SKan Liang }; 3811cd34cd97SKan Liang 3812cd34cd97SKan Liang 3813cd34cd97SKan Liang static struct pci_driver skx_uncore_pci_driver = { 3814cd34cd97SKan Liang .name = "skx_uncore", 3815cd34cd97SKan Liang .id_table = skx_uncore_pci_ids, 3816cd34cd97SKan Liang }; 3817cd34cd97SKan Liang 3818cd34cd97SKan Liang int skx_uncore_pci_init(void) 3819cd34cd97SKan Liang { 3820cd34cd97SKan Liang /* need to double check pci address */ 3821cd34cd97SKan Liang int ret = snbep_pci2phy_map_init(0x2014, SKX_CPUNODEID, SKX_GIDNIDMAP, false); 3822cd34cd97SKan Liang 3823cd34cd97SKan Liang if (ret) 3824cd34cd97SKan Liang return ret; 3825cd34cd97SKan Liang 3826cd34cd97SKan Liang uncore_pci_uncores = skx_pci_uncores; 3827cd34cd97SKan Liang uncore_pci_driver = &skx_uncore_pci_driver; 3828cd34cd97SKan Liang return 0; 3829cd34cd97SKan Liang } 3830cd34cd97SKan Liang 3831cd34cd97SKan Liang /* end of SKX uncore support */ 3832