1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2ed367e6cSBorislav Petkov /* SandyBridge-EP/IvyTown uncore support */ 3ed367e6cSBorislav Petkov #include "uncore.h" 4ed367e6cSBorislav Petkov 568ce4a0dSKan Liang /* SNB-EP pci bus to socket mapping */ 668ce4a0dSKan Liang #define SNBEP_CPUNODEID 0x40 768ce4a0dSKan Liang #define SNBEP_GIDNIDMAP 0x54 868ce4a0dSKan Liang 9ed367e6cSBorislav Petkov /* SNB-EP Box level control */ 10ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0) 11ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1) 12ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_FRZ (1 << 8) 13ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16) 14ed367e6cSBorislav Petkov #define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ 15ed367e6cSBorislav Petkov SNBEP_PMON_BOX_CTL_RST_CTRS | \ 16ed367e6cSBorislav Petkov SNBEP_PMON_BOX_CTL_FRZ_EN) 17ed367e6cSBorislav Petkov /* SNB-EP event control */ 18ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff 19ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00 20ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_RST (1 << 17) 21ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EDGE_DET (1 << 18) 22ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) 23ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_EN (1 << 22) 24ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_INVERT (1 << 23) 25ed367e6cSBorislav Petkov #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000 26ed367e6cSBorislav Petkov #define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 27ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 28ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 29ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 30ed367e6cSBorislav Petkov SNBEP_PMON_CTL_TRESH_MASK) 31ed367e6cSBorislav Petkov 32ed367e6cSBorislav Petkov /* SNB-EP Ubox event control */ 33ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000 34ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \ 35ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 36ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 37ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 38ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 39ed367e6cSBorislav Petkov SNBEP_U_MSR_PMON_CTL_TRESH_MASK) 40ed367e6cSBorislav Petkov 41ed367e6cSBorislav Petkov #define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19) 42ed367e6cSBorislav Petkov #define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 43ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 44ed367e6cSBorislav Petkov 45ed367e6cSBorislav Petkov /* SNB-EP PCU event control */ 46ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000 47ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000 48ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30) 49ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31) 50ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 51ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 52ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 53ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 54ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 55ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 56ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 57ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 58ed367e6cSBorislav Petkov 59ed367e6cSBorislav Petkov #define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \ 60ed367e6cSBorislav Petkov (SNBEP_PMON_RAW_EVENT_MASK | \ 61ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EV_SEL_EXT) 62ed367e6cSBorislav Petkov 63ed367e6cSBorislav Petkov /* SNB-EP pci control register */ 64ed367e6cSBorislav Petkov #define SNBEP_PCI_PMON_BOX_CTL 0xf4 65ed367e6cSBorislav Petkov #define SNBEP_PCI_PMON_CTL0 0xd8 66ed367e6cSBorislav Petkov /* SNB-EP pci counter register */ 67ed367e6cSBorislav Petkov #define SNBEP_PCI_PMON_CTR0 0xa0 68ed367e6cSBorislav Petkov 69ed367e6cSBorislav Petkov /* SNB-EP home agent register */ 70ed367e6cSBorislav Petkov #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40 71ed367e6cSBorislav Petkov #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44 72ed367e6cSBorislav Petkov #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48 73ed367e6cSBorislav Petkov /* SNB-EP memory controller register */ 74ed367e6cSBorislav Petkov #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0 75ed367e6cSBorislav Petkov #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0 76ed367e6cSBorislav Petkov /* SNB-EP QPI register */ 77ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228 78ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c 79ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238 80ed367e6cSBorislav Petkov #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c 81ed367e6cSBorislav Petkov 82ed367e6cSBorislav Petkov /* SNB-EP Ubox register */ 83ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_CTR0 0xc16 84ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_CTL0 0xc10 85ed367e6cSBorislav Petkov 86ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08 87ed367e6cSBorislav Petkov #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09 88ed367e6cSBorislav Petkov 89ed367e6cSBorislav Petkov /* SNB-EP Cbo register */ 90ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_CTR0 0xd16 91ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_CTL0 0xd10 92ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04 93ed367e6cSBorislav Petkov #define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14 94ed367e6cSBorislav Petkov #define SNBEP_CBO_MSR_OFFSET 0x20 95ed367e6cSBorislav Petkov 96ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f 97ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00 98ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000 99ed367e6cSBorislav Petkov #define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000 100ed367e6cSBorislav Petkov 101ed367e6cSBorislav Petkov #define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \ 102ed367e6cSBorislav Petkov .event = (e), \ 103ed367e6cSBorislav Petkov .msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \ 104ed367e6cSBorislav Petkov .config_mask = (m), \ 105ed367e6cSBorislav Petkov .idx = (i) \ 106ed367e6cSBorislav Petkov } 107ed367e6cSBorislav Petkov 108ed367e6cSBorislav Petkov /* SNB-EP PCU register */ 109ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTR0 0xc36 110ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_CTL0 0xc30 111ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24 112ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34 113ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff 114ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc 115ed367e6cSBorislav Petkov #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd 116ed367e6cSBorislav Petkov 117ed367e6cSBorislav Petkov /* IVBEP event control */ 118ed367e6cSBorislav Petkov #define IVBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ 119ed367e6cSBorislav Petkov SNBEP_PMON_BOX_CTL_RST_CTRS) 120ed367e6cSBorislav Petkov #define IVBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 121ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 122ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 123ed367e6cSBorislav Petkov SNBEP_PMON_CTL_TRESH_MASK) 124ed367e6cSBorislav Petkov /* IVBEP Ubox */ 125ed367e6cSBorislav Petkov #define IVBEP_U_MSR_PMON_GLOBAL_CTL 0xc00 126ed367e6cSBorislav Petkov #define IVBEP_U_PMON_GLOBAL_FRZ_ALL (1 << 31) 127ed367e6cSBorislav Petkov #define IVBEP_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29) 128ed367e6cSBorislav Petkov 129ed367e6cSBorislav Petkov #define IVBEP_U_MSR_PMON_RAW_EVENT_MASK \ 130ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 131ed367e6cSBorislav Petkov SNBEP_PMON_CTL_UMASK_MASK | \ 132ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 133ed367e6cSBorislav Petkov SNBEP_U_MSR_PMON_CTL_TRESH_MASK) 134ed367e6cSBorislav Petkov /* IVBEP Cbo */ 135ed367e6cSBorislav Petkov #define IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK (IVBEP_PMON_RAW_EVENT_MASK | \ 136ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 137ed367e6cSBorislav Petkov 138ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0) 139ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5) 140ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17) 141ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32) 142ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52) 143ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 144ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 145ed367e6cSBorislav Petkov #define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 146ed367e6cSBorislav Petkov 147ed367e6cSBorislav Petkov /* IVBEP home agent */ 148ed367e6cSBorislav Petkov #define IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16) 149ed367e6cSBorislav Petkov #define IVBEP_HA_PCI_PMON_RAW_EVENT_MASK \ 150ed367e6cSBorislav Petkov (IVBEP_PMON_RAW_EVENT_MASK | \ 151ed367e6cSBorislav Petkov IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST) 152ed367e6cSBorislav Petkov /* IVBEP PCU */ 153ed367e6cSBorislav Petkov #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 154ed367e6cSBorislav Petkov (SNBEP_PMON_CTL_EV_SEL_MASK | \ 155ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 156ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 157ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 158ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 159ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 160ed367e6cSBorislav Petkov /* IVBEP QPI */ 161ed367e6cSBorislav Petkov #define IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK \ 162ed367e6cSBorislav Petkov (IVBEP_PMON_RAW_EVENT_MASK | \ 163ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EV_SEL_EXT) 164ed367e6cSBorislav Petkov 165ed367e6cSBorislav Petkov #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \ 166ed367e6cSBorislav Petkov ((1ULL << (n)) - 1))) 167ed367e6cSBorislav Petkov 168ed367e6cSBorislav Petkov /* Haswell-EP Ubox */ 169ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_CTR0 0x709 170ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_CTL0 0x705 171ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_FILTER 0x707 172ed367e6cSBorislav Petkov 173ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703 174ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704 175ed367e6cSBorislav Petkov 176ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0) 177ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1) 178ed367e6cSBorislav Petkov #define HSWEP_U_MSR_PMON_BOX_FILTER_MASK \ 179ed367e6cSBorislav Petkov (HSWEP_U_MSR_PMON_BOX_FILTER_TID | \ 180ed367e6cSBorislav Petkov HSWEP_U_MSR_PMON_BOX_FILTER_CID) 181ed367e6cSBorislav Petkov 182ed367e6cSBorislav Petkov /* Haswell-EP CBo */ 183ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_CTR0 0xe08 184ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_CTL0 0xe01 185ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00 186ed367e6cSBorislav Petkov #define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05 187ed367e6cSBorislav Petkov #define HSWEP_CBO_MSR_OFFSET 0x10 188ed367e6cSBorislav Petkov 189ed367e6cSBorislav Petkov 190ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0) 191ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6) 192ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17) 193ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32) 194ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52) 195ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 196ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 197ed367e6cSBorislav Petkov #define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 198ed367e6cSBorislav Petkov 199ed367e6cSBorislav Petkov 200ed367e6cSBorislav Petkov /* Haswell-EP Sbox */ 201ed367e6cSBorislav Petkov #define HSWEP_S0_MSR_PMON_CTR0 0x726 202ed367e6cSBorislav Petkov #define HSWEP_S0_MSR_PMON_CTL0 0x721 203ed367e6cSBorislav Petkov #define HSWEP_S0_MSR_PMON_BOX_CTL 0x720 204ed367e6cSBorislav Petkov #define HSWEP_SBOX_MSR_OFFSET 0xa 205ed367e6cSBorislav Petkov #define HSWEP_S_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 206ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 207ed367e6cSBorislav Petkov 208ed367e6cSBorislav Petkov /* Haswell-EP PCU */ 209ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_CTR0 0x717 210ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_CTL0 0x711 211ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710 212ed367e6cSBorislav Petkov #define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715 213ed367e6cSBorislav Petkov 214ed367e6cSBorislav Petkov /* KNL Ubox */ 215ed367e6cSBorislav Petkov #define KNL_U_MSR_PMON_RAW_EVENT_MASK \ 216ed367e6cSBorislav Petkov (SNBEP_U_MSR_PMON_RAW_EVENT_MASK | \ 217ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN) 218ed367e6cSBorislav Petkov /* KNL CHA */ 219ed367e6cSBorislav Petkov #define KNL_CHA_MSR_OFFSET 0xc 220ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_CTL_QOR (1 << 16) 221ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_RAW_EVENT_MASK \ 222ed367e6cSBorislav Petkov (SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK | \ 223ed367e6cSBorislav Petkov KNL_CHA_MSR_PMON_CTL_QOR) 224ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff 225ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE (7 << 18) 226ed367e6cSBorislav Petkov #define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32) 227ec336c87Shchrzani #define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE (0x1ULL << 32) 228ec336c87Shchrzani #define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE (0x1ULL << 33) 229ec336c87Shchrzani #define KNL_CHA_MSR_PMON_BOX_FILTER_NNC (0x1ULL << 37) 230ed367e6cSBorislav Petkov 231ed367e6cSBorislav Petkov /* KNL EDC/MC UCLK */ 232ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400 233ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_CTL0 0x420 234ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_BOX_CTL 0x430 235ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c 236ed367e6cSBorislav Petkov #define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454 237ed367e6cSBorislav Petkov #define KNL_PMON_FIXED_CTL_EN 0x1 238ed367e6cSBorislav Petkov 239ed367e6cSBorislav Petkov /* KNL EDC */ 240ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00 241ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20 242ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30 243ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c 244ed367e6cSBorislav Petkov #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44 245ed367e6cSBorislav Petkov 246ed367e6cSBorislav Petkov /* KNL MC */ 247ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00 248ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20 249ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30 250ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c 251ed367e6cSBorislav Petkov #define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44 252ed367e6cSBorislav Petkov 253ed367e6cSBorislav Petkov /* KNL IRP */ 254ed367e6cSBorislav Petkov #define KNL_IRP_PCI_PMON_BOX_CTL 0xf0 255ed367e6cSBorislav Petkov #define KNL_IRP_PCI_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 256ed367e6cSBorislav Petkov KNL_CHA_MSR_PMON_CTL_QOR) 257ed367e6cSBorislav Petkov /* KNL PCU */ 258ed367e6cSBorislav Petkov #define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f 259ed367e6cSBorislav Petkov #define KNL_PCU_PMON_CTL_USE_OCC_CTR (1 << 7) 260ed367e6cSBorislav Petkov #define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000 261ed367e6cSBorislav Petkov #define KNL_PCU_MSR_PMON_RAW_EVENT_MASK \ 262ed367e6cSBorislav Petkov (KNL_PCU_PMON_CTL_EV_SEL_MASK | \ 263ed367e6cSBorislav Petkov KNL_PCU_PMON_CTL_USE_OCC_CTR | \ 264ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 265ed367e6cSBorislav Petkov SNBEP_PMON_CTL_EDGE_DET | \ 266ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN | \ 267ed367e6cSBorislav Petkov SNBEP_PMON_CTL_INVERT | \ 268ed367e6cSBorislav Petkov KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \ 269ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 270ed367e6cSBorislav Petkov SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 271ed367e6cSBorislav Petkov 272cd34cd97SKan Liang /* SKX pci bus to socket mapping */ 273cd34cd97SKan Liang #define SKX_CPUNODEID 0xc0 274cd34cd97SKan Liang #define SKX_GIDNIDMAP 0xd4 275cd34cd97SKan Liang 276cd34cd97SKan Liang /* SKX CHA */ 277cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_TID (0x1ffULL << 0) 278cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_LINK (0xfULL << 9) 279cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_STATE (0x3ffULL << 17) 280cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_REM (0x1ULL << 32) 281cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_LOC (0x1ULL << 33) 282cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC (0x1ULL << 35) 283cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_NM (0x1ULL << 36) 284cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM (0x1ULL << 37) 285cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 (0x3ffULL << 41) 286cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 (0x3ffULL << 51) 287cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 288cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 289cd34cd97SKan Liang #define SKX_CHA_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 290cd34cd97SKan Liang 291cd34cd97SKan Liang /* SKX IIO */ 292cd34cd97SKan Liang #define SKX_IIO0_MSR_PMON_CTL0 0xa48 293cd34cd97SKan Liang #define SKX_IIO0_MSR_PMON_CTR0 0xa41 294cd34cd97SKan Liang #define SKX_IIO0_MSR_PMON_BOX_CTL 0xa40 295cd34cd97SKan Liang #define SKX_IIO_MSR_OFFSET 0x20 296cd34cd97SKan Liang 297cd34cd97SKan Liang #define SKX_PMON_CTL_TRESH_MASK (0xff << 24) 298cd34cd97SKan Liang #define SKX_PMON_CTL_TRESH_MASK_EXT (0xf) 299cd34cd97SKan Liang #define SKX_PMON_CTL_CH_MASK (0xff << 4) 300cd34cd97SKan Liang #define SKX_PMON_CTL_FC_MASK (0x7 << 12) 301cd34cd97SKan Liang #define SKX_IIO_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 302cd34cd97SKan Liang SNBEP_PMON_CTL_UMASK_MASK | \ 303cd34cd97SKan Liang SNBEP_PMON_CTL_EDGE_DET | \ 304cd34cd97SKan Liang SNBEP_PMON_CTL_INVERT | \ 305cd34cd97SKan Liang SKX_PMON_CTL_TRESH_MASK) 306cd34cd97SKan Liang #define SKX_IIO_PMON_RAW_EVENT_MASK_EXT (SKX_PMON_CTL_TRESH_MASK_EXT | \ 307cd34cd97SKan Liang SKX_PMON_CTL_CH_MASK | \ 308cd34cd97SKan Liang SKX_PMON_CTL_FC_MASK) 309cd34cd97SKan Liang 310cd34cd97SKan Liang /* SKX IRP */ 311cd34cd97SKan Liang #define SKX_IRP0_MSR_PMON_CTL0 0xa5b 312cd34cd97SKan Liang #define SKX_IRP0_MSR_PMON_CTR0 0xa59 313cd34cd97SKan Liang #define SKX_IRP0_MSR_PMON_BOX_CTL 0xa58 314cd34cd97SKan Liang #define SKX_IRP_MSR_OFFSET 0x20 315cd34cd97SKan Liang 316cd34cd97SKan Liang /* SKX UPI */ 317cd34cd97SKan Liang #define SKX_UPI_PCI_PMON_CTL0 0x350 318cd34cd97SKan Liang #define SKX_UPI_PCI_PMON_CTR0 0x318 319cd34cd97SKan Liang #define SKX_UPI_PCI_PMON_BOX_CTL 0x378 320b3625980SStephane Eranian #define SKX_UPI_CTL_UMASK_EXT 0xffefff 321cd34cd97SKan Liang 322cd34cd97SKan Liang /* SKX M2M */ 323cd34cd97SKan Liang #define SKX_M2M_PCI_PMON_CTL0 0x228 324cd34cd97SKan Liang #define SKX_M2M_PCI_PMON_CTR0 0x200 325cd34cd97SKan Liang #define SKX_M2M_PCI_PMON_BOX_CTL 0x258 326cd34cd97SKan Liang 327210cc5f9SKan Liang /* SNR Ubox */ 328210cc5f9SKan Liang #define SNR_U_MSR_PMON_CTR0 0x1f98 329210cc5f9SKan Liang #define SNR_U_MSR_PMON_CTL0 0x1f91 330210cc5f9SKan Liang #define SNR_U_MSR_PMON_UCLK_FIXED_CTL 0x1f93 331210cc5f9SKan Liang #define SNR_U_MSR_PMON_UCLK_FIXED_CTR 0x1f94 332210cc5f9SKan Liang 333210cc5f9SKan Liang /* SNR CHA */ 334210cc5f9SKan Liang #define SNR_CHA_RAW_EVENT_MASK_EXT 0x3ffffff 335210cc5f9SKan Liang #define SNR_CHA_MSR_PMON_CTL0 0x1c01 336210cc5f9SKan Liang #define SNR_CHA_MSR_PMON_CTR0 0x1c08 337210cc5f9SKan Liang #define SNR_CHA_MSR_PMON_BOX_CTL 0x1c00 338210cc5f9SKan Liang #define SNR_C0_MSR_PMON_BOX_FILTER0 0x1c05 339210cc5f9SKan Liang 340210cc5f9SKan Liang 341210cc5f9SKan Liang /* SNR IIO */ 342210cc5f9SKan Liang #define SNR_IIO_MSR_PMON_CTL0 0x1e08 343210cc5f9SKan Liang #define SNR_IIO_MSR_PMON_CTR0 0x1e01 344210cc5f9SKan Liang #define SNR_IIO_MSR_PMON_BOX_CTL 0x1e00 345210cc5f9SKan Liang #define SNR_IIO_MSR_OFFSET 0x10 346210cc5f9SKan Liang #define SNR_IIO_PMON_RAW_EVENT_MASK_EXT 0x7ffff 347210cc5f9SKan Liang 348210cc5f9SKan Liang /* SNR IRP */ 349210cc5f9SKan Liang #define SNR_IRP0_MSR_PMON_CTL0 0x1ea8 350210cc5f9SKan Liang #define SNR_IRP0_MSR_PMON_CTR0 0x1ea1 351210cc5f9SKan Liang #define SNR_IRP0_MSR_PMON_BOX_CTL 0x1ea0 352210cc5f9SKan Liang #define SNR_IRP_MSR_OFFSET 0x10 353210cc5f9SKan Liang 354210cc5f9SKan Liang /* SNR M2PCIE */ 355210cc5f9SKan Liang #define SNR_M2PCIE_MSR_PMON_CTL0 0x1e58 356210cc5f9SKan Liang #define SNR_M2PCIE_MSR_PMON_CTR0 0x1e51 357210cc5f9SKan Liang #define SNR_M2PCIE_MSR_PMON_BOX_CTL 0x1e50 358210cc5f9SKan Liang #define SNR_M2PCIE_MSR_OFFSET 0x10 359210cc5f9SKan Liang 360210cc5f9SKan Liang /* SNR PCU */ 361210cc5f9SKan Liang #define SNR_PCU_MSR_PMON_CTL0 0x1ef1 362210cc5f9SKan Liang #define SNR_PCU_MSR_PMON_CTR0 0x1ef8 363210cc5f9SKan Liang #define SNR_PCU_MSR_PMON_BOX_CTL 0x1ef0 364210cc5f9SKan Liang #define SNR_PCU_MSR_PMON_BOX_FILTER 0x1efc 365210cc5f9SKan Liang 366210cc5f9SKan Liang /* SNR M2M */ 367210cc5f9SKan Liang #define SNR_M2M_PCI_PMON_CTL0 0x468 368210cc5f9SKan Liang #define SNR_M2M_PCI_PMON_CTR0 0x440 369210cc5f9SKan Liang #define SNR_M2M_PCI_PMON_BOX_CTL 0x438 370210cc5f9SKan Liang #define SNR_M2M_PCI_PMON_UMASK_EXT 0xff 371210cc5f9SKan Liang 372210cc5f9SKan Liang /* SNR PCIE3 */ 373210cc5f9SKan Liang #define SNR_PCIE3_PCI_PMON_CTL0 0x508 374210cc5f9SKan Liang #define SNR_PCIE3_PCI_PMON_CTR0 0x4e8 375210cc5f9SKan Liang #define SNR_PCIE3_PCI_PMON_BOX_CTL 0x4e4 376210cc5f9SKan Liang 377ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 378ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6"); 379ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); 380ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7"); 381ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 382b3625980SStephane Eranian DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55"); 383210cc5f9SKan Liang DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57"); 384210cc5f9SKan Liang DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39"); 385ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16"); 386ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 387ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); 388ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 389cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35"); 390ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31"); 391ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29"); 392ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28"); 393ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15"); 394ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); 395ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); 396ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31"); 397cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43"); 398210cc5f9SKan Liang DEFINE_UNCORE_FORMAT_ATTR(ch_mask2, ch_mask, "config:36-47"); 399cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46"); 400210cc5f9SKan Liang DEFINE_UNCORE_FORMAT_ATTR(fc_mask2, fc_mask, "config:48-50"); 401ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); 402ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0"); 403ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5"); 404ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8"); 405210cc5f9SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_tid5, filter_tid, "config1:0-9"); 406ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5"); 407ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8"); 408ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8"); 409ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12"); 410ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); 411ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47"); 412ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); 413ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22"); 414ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23"); 415ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_state4, filter_state, "config1:18-20"); 416cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_state5, filter_state, "config1:17-26"); 417cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_rem, filter_rem, "config1:32"); 418cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_loc, filter_loc, "config1:33"); 419cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_nm, filter_nm, "config1:36"); 420cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_not_nm, filter_not_nm, "config1:37"); 421ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_local, filter_local, "config1:33"); 422ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_all_op, filter_all_op, "config1:35"); 423ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nnm, filter_nnm, "config1:37"); 424ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); 425ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60"); 426ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_opc3, filter_opc, "config1:41-60"); 427cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_opc_0, filter_opc0, "config1:41-50"); 428cd34cd97SKan Liang DEFINE_UNCORE_FORMAT_ATTR(filter_opc_1, filter_opc1, "config1:51-60"); 429ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62"); 430ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61"); 431ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63"); 432ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7"); 433ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15"); 434ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23"); 435ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31"); 436ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51"); 437ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35"); 438ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31"); 439ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17"); 440ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12"); 441ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8"); 442ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4"); 443ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31"); 444ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63"); 445ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51"); 446ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35"); 447ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31"); 448ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17"); 449ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12"); 450ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8"); 451ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4"); 452ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31"); 453ed367e6cSBorislav Petkov DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63"); 454ed367e6cSBorislav Petkov 455ed367e6cSBorislav Petkov static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box) 456ed367e6cSBorislav Petkov { 457ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 458ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 459ed367e6cSBorislav Petkov u32 config = 0; 460ed367e6cSBorislav Petkov 461ed367e6cSBorislav Petkov if (!pci_read_config_dword(pdev, box_ctl, &config)) { 462ed367e6cSBorislav Petkov config |= SNBEP_PMON_BOX_CTL_FRZ; 463ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, config); 464ed367e6cSBorislav Petkov } 465ed367e6cSBorislav Petkov } 466ed367e6cSBorislav Petkov 467ed367e6cSBorislav Petkov static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box) 468ed367e6cSBorislav Petkov { 469ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 470ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 471ed367e6cSBorislav Petkov u32 config = 0; 472ed367e6cSBorislav Petkov 473ed367e6cSBorislav Petkov if (!pci_read_config_dword(pdev, box_ctl, &config)) { 474ed367e6cSBorislav Petkov config &= ~SNBEP_PMON_BOX_CTL_FRZ; 475ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, config); 476ed367e6cSBorislav Petkov } 477ed367e6cSBorislav Petkov } 478ed367e6cSBorislav Petkov 479ed367e6cSBorislav Petkov static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) 480ed367e6cSBorislav Petkov { 481ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 482ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 483ed367e6cSBorislav Petkov 484ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 485ed367e6cSBorislav Petkov } 486ed367e6cSBorislav Petkov 487ed367e6cSBorislav Petkov static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event) 488ed367e6cSBorislav Petkov { 489ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 490ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 491ed367e6cSBorislav Petkov 492ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, hwc->config); 493ed367e6cSBorislav Petkov } 494ed367e6cSBorislav Petkov 495ed367e6cSBorislav Petkov static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event) 496ed367e6cSBorislav Petkov { 497ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 498ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 499ed367e6cSBorislav Petkov u64 count = 0; 500ed367e6cSBorislav Petkov 501ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); 502ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); 503ed367e6cSBorislav Petkov 504ed367e6cSBorislav Petkov return count; 505ed367e6cSBorislav Petkov } 506ed367e6cSBorislav Petkov 507ed367e6cSBorislav Petkov static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) 508ed367e6cSBorislav Petkov { 509ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 510ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 511ed367e6cSBorislav Petkov 512ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT); 513ed367e6cSBorislav Petkov } 514ed367e6cSBorislav Petkov 515ed367e6cSBorislav Petkov static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) 516ed367e6cSBorislav Petkov { 517ed367e6cSBorislav Petkov u64 config; 518ed367e6cSBorislav Petkov unsigned msr; 519ed367e6cSBorislav Petkov 520ed367e6cSBorislav Petkov msr = uncore_msr_box_ctl(box); 521ed367e6cSBorislav Petkov if (msr) { 522ed367e6cSBorislav Petkov rdmsrl(msr, config); 523ed367e6cSBorislav Petkov config |= SNBEP_PMON_BOX_CTL_FRZ; 524ed367e6cSBorislav Petkov wrmsrl(msr, config); 525ed367e6cSBorislav Petkov } 526ed367e6cSBorislav Petkov } 527ed367e6cSBorislav Petkov 528ed367e6cSBorislav Petkov static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box) 529ed367e6cSBorislav Petkov { 530ed367e6cSBorislav Petkov u64 config; 531ed367e6cSBorislav Petkov unsigned msr; 532ed367e6cSBorislav Petkov 533ed367e6cSBorislav Petkov msr = uncore_msr_box_ctl(box); 534ed367e6cSBorislav Petkov if (msr) { 535ed367e6cSBorislav Petkov rdmsrl(msr, config); 536ed367e6cSBorislav Petkov config &= ~SNBEP_PMON_BOX_CTL_FRZ; 537ed367e6cSBorislav Petkov wrmsrl(msr, config); 538ed367e6cSBorislav Petkov } 539ed367e6cSBorislav Petkov } 540ed367e6cSBorislav Petkov 541ed367e6cSBorislav Petkov static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 542ed367e6cSBorislav Petkov { 543ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 544ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 545ed367e6cSBorislav Petkov 546ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) 547ed367e6cSBorislav Petkov wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); 548ed367e6cSBorislav Petkov 549ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 550ed367e6cSBorislav Petkov } 551ed367e6cSBorislav Petkov 552ed367e6cSBorislav Petkov static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box, 553ed367e6cSBorislav Petkov struct perf_event *event) 554ed367e6cSBorislav Petkov { 555ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 556ed367e6cSBorislav Petkov 557ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config); 558ed367e6cSBorislav Petkov } 559ed367e6cSBorislav Petkov 560ed367e6cSBorislav Petkov static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) 561ed367e6cSBorislav Petkov { 562ed367e6cSBorislav Petkov unsigned msr = uncore_msr_box_ctl(box); 563ed367e6cSBorislav Petkov 564ed367e6cSBorislav Petkov if (msr) 565ed367e6cSBorislav Petkov wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); 566ed367e6cSBorislav Petkov } 567ed367e6cSBorislav Petkov 568ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_formats_attr[] = { 569ed367e6cSBorislav Petkov &format_attr_event.attr, 570ed367e6cSBorislav Petkov &format_attr_umask.attr, 571ed367e6cSBorislav Petkov &format_attr_edge.attr, 572ed367e6cSBorislav Petkov &format_attr_inv.attr, 573ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 574ed367e6cSBorislav Petkov NULL, 575ed367e6cSBorislav Petkov }; 576ed367e6cSBorislav Petkov 577ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_ubox_formats_attr[] = { 578ed367e6cSBorislav Petkov &format_attr_event.attr, 579ed367e6cSBorislav Petkov &format_attr_umask.attr, 580ed367e6cSBorislav Petkov &format_attr_edge.attr, 581ed367e6cSBorislav Petkov &format_attr_inv.attr, 582ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 583ed367e6cSBorislav Petkov NULL, 584ed367e6cSBorislav Petkov }; 585ed367e6cSBorislav Petkov 586ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_cbox_formats_attr[] = { 587ed367e6cSBorislav Petkov &format_attr_event.attr, 588ed367e6cSBorislav Petkov &format_attr_umask.attr, 589ed367e6cSBorislav Petkov &format_attr_edge.attr, 590ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 591ed367e6cSBorislav Petkov &format_attr_inv.attr, 592ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 593ed367e6cSBorislav Petkov &format_attr_filter_tid.attr, 594ed367e6cSBorislav Petkov &format_attr_filter_nid.attr, 595ed367e6cSBorislav Petkov &format_attr_filter_state.attr, 596ed367e6cSBorislav Petkov &format_attr_filter_opc.attr, 597ed367e6cSBorislav Petkov NULL, 598ed367e6cSBorislav Petkov }; 599ed367e6cSBorislav Petkov 600ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_pcu_formats_attr[] = { 601cb225252SKan Liang &format_attr_event.attr, 602ed367e6cSBorislav Petkov &format_attr_occ_sel.attr, 603ed367e6cSBorislav Petkov &format_attr_edge.attr, 604ed367e6cSBorislav Petkov &format_attr_inv.attr, 605ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 606ed367e6cSBorislav Petkov &format_attr_occ_invert.attr, 607ed367e6cSBorislav Petkov &format_attr_occ_edge.attr, 608ed367e6cSBorislav Petkov &format_attr_filter_band0.attr, 609ed367e6cSBorislav Petkov &format_attr_filter_band1.attr, 610ed367e6cSBorislav Petkov &format_attr_filter_band2.attr, 611ed367e6cSBorislav Petkov &format_attr_filter_band3.attr, 612ed367e6cSBorislav Petkov NULL, 613ed367e6cSBorislav Petkov }; 614ed367e6cSBorislav Petkov 615ed367e6cSBorislav Petkov static struct attribute *snbep_uncore_qpi_formats_attr[] = { 616ed367e6cSBorislav Petkov &format_attr_event_ext.attr, 617ed367e6cSBorislav Petkov &format_attr_umask.attr, 618ed367e6cSBorislav Petkov &format_attr_edge.attr, 619ed367e6cSBorislav Petkov &format_attr_inv.attr, 620ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 621ed367e6cSBorislav Petkov &format_attr_match_rds.attr, 622ed367e6cSBorislav Petkov &format_attr_match_rnid30.attr, 623ed367e6cSBorislav Petkov &format_attr_match_rnid4.attr, 624ed367e6cSBorislav Petkov &format_attr_match_dnid.attr, 625ed367e6cSBorislav Petkov &format_attr_match_mc.attr, 626ed367e6cSBorislav Petkov &format_attr_match_opc.attr, 627ed367e6cSBorislav Petkov &format_attr_match_vnw.attr, 628ed367e6cSBorislav Petkov &format_attr_match0.attr, 629ed367e6cSBorislav Petkov &format_attr_match1.attr, 630ed367e6cSBorislav Petkov &format_attr_mask_rds.attr, 631ed367e6cSBorislav Petkov &format_attr_mask_rnid30.attr, 632ed367e6cSBorislav Petkov &format_attr_mask_rnid4.attr, 633ed367e6cSBorislav Petkov &format_attr_mask_dnid.attr, 634ed367e6cSBorislav Petkov &format_attr_mask_mc.attr, 635ed367e6cSBorislav Petkov &format_attr_mask_opc.attr, 636ed367e6cSBorislav Petkov &format_attr_mask_vnw.attr, 637ed367e6cSBorislav Petkov &format_attr_mask0.attr, 638ed367e6cSBorislav Petkov &format_attr_mask1.attr, 639ed367e6cSBorislav Petkov NULL, 640ed367e6cSBorislav Petkov }; 641ed367e6cSBorislav Petkov 642ed367e6cSBorislav Petkov static struct uncore_event_desc snbep_uncore_imc_events[] = { 643ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 644ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), 645ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 646ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 647ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), 648ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 649ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 650ed367e6cSBorislav Petkov { /* end: all zeroes */ }, 651ed367e6cSBorislav Petkov }; 652ed367e6cSBorislav Petkov 653ed367e6cSBorislav Petkov static struct uncore_event_desc snbep_uncore_qpi_events[] = { 654ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"), 655ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"), 656ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"), 657ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"), 658ed367e6cSBorislav Petkov { /* end: all zeroes */ }, 659ed367e6cSBorislav Petkov }; 660ed367e6cSBorislav Petkov 66145bd07adSArvind Yadav static const struct attribute_group snbep_uncore_format_group = { 662ed367e6cSBorislav Petkov .name = "format", 663ed367e6cSBorislav Petkov .attrs = snbep_uncore_formats_attr, 664ed367e6cSBorislav Petkov }; 665ed367e6cSBorislav Petkov 66645bd07adSArvind Yadav static const struct attribute_group snbep_uncore_ubox_format_group = { 667ed367e6cSBorislav Petkov .name = "format", 668ed367e6cSBorislav Petkov .attrs = snbep_uncore_ubox_formats_attr, 669ed367e6cSBorislav Petkov }; 670ed367e6cSBorislav Petkov 67145bd07adSArvind Yadav static const struct attribute_group snbep_uncore_cbox_format_group = { 672ed367e6cSBorislav Petkov .name = "format", 673ed367e6cSBorislav Petkov .attrs = snbep_uncore_cbox_formats_attr, 674ed367e6cSBorislav Petkov }; 675ed367e6cSBorislav Petkov 67645bd07adSArvind Yadav static const struct attribute_group snbep_uncore_pcu_format_group = { 677ed367e6cSBorislav Petkov .name = "format", 678ed367e6cSBorislav Petkov .attrs = snbep_uncore_pcu_formats_attr, 679ed367e6cSBorislav Petkov }; 680ed367e6cSBorislav Petkov 68145bd07adSArvind Yadav static const struct attribute_group snbep_uncore_qpi_format_group = { 682ed367e6cSBorislav Petkov .name = "format", 683ed367e6cSBorislav Petkov .attrs = snbep_uncore_qpi_formats_attr, 684ed367e6cSBorislav Petkov }; 685ed367e6cSBorislav Petkov 686ed367e6cSBorislav Petkov #define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 687ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, \ 688ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, \ 689ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, \ 690ed367e6cSBorislav Petkov .enable_event = snbep_uncore_msr_enable_event, \ 691ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter 692ed367e6cSBorislav Petkov 693ed367e6cSBorislav Petkov #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 694ed367e6cSBorislav Petkov __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \ 695ed367e6cSBorislav Petkov .init_box = snbep_uncore_msr_init_box \ 696ed367e6cSBorislav Petkov 697ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_msr_ops = { 698ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 699ed367e6cSBorislav Petkov }; 700ed367e6cSBorislav Petkov 701ed367e6cSBorislav Petkov #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \ 702ed367e6cSBorislav Petkov .init_box = snbep_uncore_pci_init_box, \ 703ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, \ 704ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, \ 705ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, \ 706ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter 707ed367e6cSBorislav Petkov 708ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_pci_ops = { 709ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_OPS_COMMON_INIT(), 710ed367e6cSBorislav Petkov .enable_event = snbep_uncore_pci_enable_event, \ 711ed367e6cSBorislav Petkov }; 712ed367e6cSBorislav Petkov 713ed367e6cSBorislav Petkov static struct event_constraint snbep_uncore_cbox_constraints[] = { 714ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x1), 715ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x02, 0x3), 716ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x04, 0x3), 717ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x05, 0x3), 718ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x07, 0x3), 719ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x3), 720ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 721ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 722ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x3), 723ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1b, 0xc), 724ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1c, 0xc), 725ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1d, 0xc), 726ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1e, 0xc), 7271134c2b5SPeter Zijlstra UNCORE_EVENT_CONSTRAINT(0x1f, 0xe), 728ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 729ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 730ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 731ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 732ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 733ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 734ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x35, 0x3), 735ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 736ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 737ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 738ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 739ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), 740ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 741ed367e6cSBorislav Petkov }; 742ed367e6cSBorislav Petkov 743ed367e6cSBorislav Petkov static struct event_constraint snbep_uncore_r2pcie_constraints[] = { 744ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 745ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 746ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x1), 747ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 748ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 749ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 750ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 751ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 752ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 753ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 754ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 755ed367e6cSBorislav Petkov }; 756ed367e6cSBorislav Petkov 757ed367e6cSBorislav Petkov static struct event_constraint snbep_uncore_r3qpi_constraints[] = { 758ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 759ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 760ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 761ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 762ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 763ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 764ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 765ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 766ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 767ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 768ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 769ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 770ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 771ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2a, 0x3), 772ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), 773ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 774ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 775ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 776ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 777ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x30, 0x3), 778ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 779ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 780ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 781ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 782ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 783ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 784ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 785ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 786ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 787ed367e6cSBorislav Petkov }; 788ed367e6cSBorislav Petkov 789ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_ubox = { 790ed367e6cSBorislav Petkov .name = "ubox", 791ed367e6cSBorislav Petkov .num_counters = 2, 792ed367e6cSBorislav Petkov .num_boxes = 1, 793ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 794ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 795ed367e6cSBorislav Petkov .perf_ctr = SNBEP_U_MSR_PMON_CTR0, 796ed367e6cSBorislav Petkov .event_ctl = SNBEP_U_MSR_PMON_CTL0, 797ed367e6cSBorislav Petkov .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 798ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, 799ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, 800ed367e6cSBorislav Petkov .ops = &snbep_uncore_msr_ops, 801ed367e6cSBorislav Petkov .format_group = &snbep_uncore_ubox_format_group, 802ed367e6cSBorislav Petkov }; 803ed367e6cSBorislav Petkov 804ed367e6cSBorislav Petkov static struct extra_reg snbep_uncore_cbox_extra_regs[] = { 805ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 806ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 807ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 808ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6), 809ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 810ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6), 811ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 812ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6), 813ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6), 814ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8), 815ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8), 816ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa), 817ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa), 818ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2), 819ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2), 820ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2), 821ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2), 822ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8), 823ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8), 824ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa), 825ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa), 826ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2), 827ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2), 828ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2), 829ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2), 830ed367e6cSBorislav Petkov EVENT_EXTRA_END 831ed367e6cSBorislav Petkov }; 832ed367e6cSBorislav Petkov 833ed367e6cSBorislav Petkov static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event) 834ed367e6cSBorislav Petkov { 835ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 836ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 837ed367e6cSBorislav Petkov int i; 838ed367e6cSBorislav Petkov 839ed367e6cSBorislav Petkov if (uncore_box_is_fake(box)) 840ed367e6cSBorislav Petkov return; 841ed367e6cSBorislav Petkov 842ed367e6cSBorislav Petkov for (i = 0; i < 5; i++) { 843ed367e6cSBorislav Petkov if (reg1->alloc & (0x1 << i)) 844ed367e6cSBorislav Petkov atomic_sub(1 << (i * 6), &er->ref); 845ed367e6cSBorislav Petkov } 846ed367e6cSBorislav Petkov reg1->alloc = 0; 847ed367e6cSBorislav Petkov } 848ed367e6cSBorislav Petkov 849ed367e6cSBorislav Petkov static struct event_constraint * 850ed367e6cSBorislav Petkov __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event, 851ed367e6cSBorislav Petkov u64 (*cbox_filter_mask)(int fields)) 852ed367e6cSBorislav Petkov { 853ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 854ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 855ed367e6cSBorislav Petkov int i, alloc = 0; 856ed367e6cSBorislav Petkov unsigned long flags; 857ed367e6cSBorislav Petkov u64 mask; 858ed367e6cSBorislav Petkov 859ed367e6cSBorislav Petkov if (reg1->idx == EXTRA_REG_NONE) 860ed367e6cSBorislav Petkov return NULL; 861ed367e6cSBorislav Petkov 862ed367e6cSBorislav Petkov raw_spin_lock_irqsave(&er->lock, flags); 863ed367e6cSBorislav Petkov for (i = 0; i < 5; i++) { 864ed367e6cSBorislav Petkov if (!(reg1->idx & (0x1 << i))) 865ed367e6cSBorislav Petkov continue; 866ed367e6cSBorislav Petkov if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) 867ed367e6cSBorislav Petkov continue; 868ed367e6cSBorislav Petkov 869ed367e6cSBorislav Petkov mask = cbox_filter_mask(0x1 << i); 870ed367e6cSBorislav Petkov if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) || 871ed367e6cSBorislav Petkov !((reg1->config ^ er->config) & mask)) { 872ed367e6cSBorislav Petkov atomic_add(1 << (i * 6), &er->ref); 873ed367e6cSBorislav Petkov er->config &= ~mask; 874ed367e6cSBorislav Petkov er->config |= reg1->config & mask; 875ed367e6cSBorislav Petkov alloc |= (0x1 << i); 876ed367e6cSBorislav Petkov } else { 877ed367e6cSBorislav Petkov break; 878ed367e6cSBorislav Petkov } 879ed367e6cSBorislav Petkov } 880ed367e6cSBorislav Petkov raw_spin_unlock_irqrestore(&er->lock, flags); 881ed367e6cSBorislav Petkov if (i < 5) 882ed367e6cSBorislav Petkov goto fail; 883ed367e6cSBorislav Petkov 884ed367e6cSBorislav Petkov if (!uncore_box_is_fake(box)) 885ed367e6cSBorislav Petkov reg1->alloc |= alloc; 886ed367e6cSBorislav Petkov 887ed367e6cSBorislav Petkov return NULL; 888ed367e6cSBorislav Petkov fail: 889ed367e6cSBorislav Petkov for (; i >= 0; i--) { 890ed367e6cSBorislav Petkov if (alloc & (0x1 << i)) 891ed367e6cSBorislav Petkov atomic_sub(1 << (i * 6), &er->ref); 892ed367e6cSBorislav Petkov } 893ed367e6cSBorislav Petkov return &uncore_constraint_empty; 894ed367e6cSBorislav Petkov } 895ed367e6cSBorislav Petkov 896ed367e6cSBorislav Petkov static u64 snbep_cbox_filter_mask(int fields) 897ed367e6cSBorislav Petkov { 898ed367e6cSBorislav Petkov u64 mask = 0; 899ed367e6cSBorislav Petkov 900ed367e6cSBorislav Petkov if (fields & 0x1) 901ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID; 902ed367e6cSBorislav Petkov if (fields & 0x2) 903ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID; 904ed367e6cSBorislav Petkov if (fields & 0x4) 905ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE; 906ed367e6cSBorislav Petkov if (fields & 0x8) 907ed367e6cSBorislav Petkov mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC; 908ed367e6cSBorislav Petkov 909ed367e6cSBorislav Petkov return mask; 910ed367e6cSBorislav Petkov } 911ed367e6cSBorislav Petkov 912ed367e6cSBorislav Petkov static struct event_constraint * 913ed367e6cSBorislav Petkov snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 914ed367e6cSBorislav Petkov { 915ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask); 916ed367e6cSBorislav Petkov } 917ed367e6cSBorislav Petkov 918ed367e6cSBorislav Petkov static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 919ed367e6cSBorislav Petkov { 920ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 921ed367e6cSBorislav Petkov struct extra_reg *er; 922ed367e6cSBorislav Petkov int idx = 0; 923ed367e6cSBorislav Petkov 924ed367e6cSBorislav Petkov for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) { 925ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 926ed367e6cSBorislav Petkov continue; 927ed367e6cSBorislav Petkov idx |= er->idx; 928ed367e6cSBorislav Petkov } 929ed367e6cSBorislav Petkov 930ed367e6cSBorislav Petkov if (idx) { 931ed367e6cSBorislav Petkov reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + 932ed367e6cSBorislav Petkov SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 933ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx); 934ed367e6cSBorislav Petkov reg1->idx = idx; 935ed367e6cSBorislav Petkov } 936ed367e6cSBorislav Petkov return 0; 937ed367e6cSBorislav Petkov } 938ed367e6cSBorislav Petkov 939ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_cbox_ops = { 940ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 941ed367e6cSBorislav Petkov .hw_config = snbep_cbox_hw_config, 942ed367e6cSBorislav Petkov .get_constraint = snbep_cbox_get_constraint, 943ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 944ed367e6cSBorislav Petkov }; 945ed367e6cSBorislav Petkov 946ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_cbox = { 947ed367e6cSBorislav Petkov .name = "cbox", 948ed367e6cSBorislav Petkov .num_counters = 4, 949ed367e6cSBorislav Petkov .num_boxes = 8, 950ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 951ed367e6cSBorislav Petkov .event_ctl = SNBEP_C0_MSR_PMON_CTL0, 952ed367e6cSBorislav Petkov .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, 953ed367e6cSBorislav Petkov .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 954ed367e6cSBorislav Petkov .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, 955ed367e6cSBorislav Petkov .msr_offset = SNBEP_CBO_MSR_OFFSET, 956ed367e6cSBorislav Petkov .num_shared_regs = 1, 957ed367e6cSBorislav Petkov .constraints = snbep_uncore_cbox_constraints, 958ed367e6cSBorislav Petkov .ops = &snbep_uncore_cbox_ops, 959ed367e6cSBorislav Petkov .format_group = &snbep_uncore_cbox_format_group, 960ed367e6cSBorislav Petkov }; 961ed367e6cSBorislav Petkov 962ed367e6cSBorislav Petkov static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify) 963ed367e6cSBorislav Petkov { 964ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 965ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 966ed367e6cSBorislav Petkov u64 config = reg1->config; 967ed367e6cSBorislav Petkov 968ed367e6cSBorislav Petkov if (new_idx > reg1->idx) 969ed367e6cSBorislav Petkov config <<= 8 * (new_idx - reg1->idx); 970ed367e6cSBorislav Petkov else 971ed367e6cSBorislav Petkov config >>= 8 * (reg1->idx - new_idx); 972ed367e6cSBorislav Petkov 973ed367e6cSBorislav Petkov if (modify) { 974ed367e6cSBorislav Petkov hwc->config += new_idx - reg1->idx; 975ed367e6cSBorislav Petkov reg1->config = config; 976ed367e6cSBorislav Petkov reg1->idx = new_idx; 977ed367e6cSBorislav Petkov } 978ed367e6cSBorislav Petkov return config; 979ed367e6cSBorislav Petkov } 980ed367e6cSBorislav Petkov 981ed367e6cSBorislav Petkov static struct event_constraint * 982ed367e6cSBorislav Petkov snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 983ed367e6cSBorislav Petkov { 984ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 985ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 986ed367e6cSBorislav Petkov unsigned long flags; 987ed367e6cSBorislav Petkov int idx = reg1->idx; 988ed367e6cSBorislav Petkov u64 mask, config1 = reg1->config; 989ed367e6cSBorislav Petkov bool ok = false; 990ed367e6cSBorislav Petkov 991ed367e6cSBorislav Petkov if (reg1->idx == EXTRA_REG_NONE || 992ed367e6cSBorislav Petkov (!uncore_box_is_fake(box) && reg1->alloc)) 993ed367e6cSBorislav Petkov return NULL; 994ed367e6cSBorislav Petkov again: 995ed367e6cSBorislav Petkov mask = 0xffULL << (idx * 8); 996ed367e6cSBorislav Petkov raw_spin_lock_irqsave(&er->lock, flags); 997ed367e6cSBorislav Petkov if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) || 998ed367e6cSBorislav Petkov !((config1 ^ er->config) & mask)) { 999ed367e6cSBorislav Petkov atomic_add(1 << (idx * 8), &er->ref); 1000ed367e6cSBorislav Petkov er->config &= ~mask; 1001ed367e6cSBorislav Petkov er->config |= config1 & mask; 1002ed367e6cSBorislav Petkov ok = true; 1003ed367e6cSBorislav Petkov } 1004ed367e6cSBorislav Petkov raw_spin_unlock_irqrestore(&er->lock, flags); 1005ed367e6cSBorislav Petkov 1006ed367e6cSBorislav Petkov if (!ok) { 1007ed367e6cSBorislav Petkov idx = (idx + 1) % 4; 1008ed367e6cSBorislav Petkov if (idx != reg1->idx) { 1009ed367e6cSBorislav Petkov config1 = snbep_pcu_alter_er(event, idx, false); 1010ed367e6cSBorislav Petkov goto again; 1011ed367e6cSBorislav Petkov } 1012ed367e6cSBorislav Petkov return &uncore_constraint_empty; 1013ed367e6cSBorislav Petkov } 1014ed367e6cSBorislav Petkov 1015ed367e6cSBorislav Petkov if (!uncore_box_is_fake(box)) { 1016ed367e6cSBorislav Petkov if (idx != reg1->idx) 1017ed367e6cSBorislav Petkov snbep_pcu_alter_er(event, idx, true); 1018ed367e6cSBorislav Petkov reg1->alloc = 1; 1019ed367e6cSBorislav Petkov } 1020ed367e6cSBorislav Petkov return NULL; 1021ed367e6cSBorislav Petkov } 1022ed367e6cSBorislav Petkov 1023ed367e6cSBorislav Petkov static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event) 1024ed367e6cSBorislav Petkov { 1025ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1026ed367e6cSBorislav Petkov struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 1027ed367e6cSBorislav Petkov 1028ed367e6cSBorislav Petkov if (uncore_box_is_fake(box) || !reg1->alloc) 1029ed367e6cSBorislav Petkov return; 1030ed367e6cSBorislav Petkov 1031ed367e6cSBorislav Petkov atomic_sub(1 << (reg1->idx * 8), &er->ref); 1032ed367e6cSBorislav Petkov reg1->alloc = 0; 1033ed367e6cSBorislav Petkov } 1034ed367e6cSBorislav Petkov 1035ed367e6cSBorislav Petkov static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1036ed367e6cSBorislav Petkov { 1037ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1038ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1039ed367e6cSBorislav Petkov int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 1040ed367e6cSBorislav Petkov 1041ed367e6cSBorislav Petkov if (ev_sel >= 0xb && ev_sel <= 0xe) { 1042ed367e6cSBorislav Petkov reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; 1043ed367e6cSBorislav Petkov reg1->idx = ev_sel - 0xb; 1044ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); 1045ed367e6cSBorislav Petkov } 1046ed367e6cSBorislav Petkov return 0; 1047ed367e6cSBorislav Petkov } 1048ed367e6cSBorislav Petkov 1049ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_pcu_ops = { 1050ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1051ed367e6cSBorislav Petkov .hw_config = snbep_pcu_hw_config, 1052ed367e6cSBorislav Petkov .get_constraint = snbep_pcu_get_constraint, 1053ed367e6cSBorislav Petkov .put_constraint = snbep_pcu_put_constraint, 1054ed367e6cSBorislav Petkov }; 1055ed367e6cSBorislav Petkov 1056ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_pcu = { 1057ed367e6cSBorislav Petkov .name = "pcu", 1058ed367e6cSBorislav Petkov .num_counters = 4, 1059ed367e6cSBorislav Petkov .num_boxes = 1, 1060ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1061ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, 1062ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, 1063ed367e6cSBorislav Petkov .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 1064ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, 1065ed367e6cSBorislav Petkov .num_shared_regs = 1, 1066ed367e6cSBorislav Petkov .ops = &snbep_uncore_pcu_ops, 1067ed367e6cSBorislav Petkov .format_group = &snbep_uncore_pcu_format_group, 1068ed367e6cSBorislav Petkov }; 1069ed367e6cSBorislav Petkov 1070ed367e6cSBorislav Petkov static struct intel_uncore_type *snbep_msr_uncores[] = { 1071ed367e6cSBorislav Petkov &snbep_uncore_ubox, 1072ed367e6cSBorislav Petkov &snbep_uncore_cbox, 1073ed367e6cSBorislav Petkov &snbep_uncore_pcu, 1074ed367e6cSBorislav Petkov NULL, 1075ed367e6cSBorislav Petkov }; 1076ed367e6cSBorislav Petkov 1077ed367e6cSBorislav Petkov void snbep_uncore_cpu_init(void) 1078ed367e6cSBorislav Petkov { 1079ed367e6cSBorislav Petkov if (snbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 1080ed367e6cSBorislav Petkov snbep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 1081ed367e6cSBorislav Petkov uncore_msr_uncores = snbep_msr_uncores; 1082ed367e6cSBorislav Petkov } 1083ed367e6cSBorislav Petkov 1084ed367e6cSBorislav Petkov enum { 1085ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER, 1086ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER, 1087156c8b58SKan Liang BDX_PCI_QPI_PORT2_FILTER, 1088ed367e6cSBorislav Petkov HSWEP_PCI_PCU_3, 1089ed367e6cSBorislav Petkov }; 1090ed367e6cSBorislav Petkov 1091ed367e6cSBorislav Petkov static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1092ed367e6cSBorislav Petkov { 1093ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1094ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1095ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 1096ed367e6cSBorislav Petkov 1097ed367e6cSBorislav Petkov if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) { 1098ed367e6cSBorislav Petkov reg1->idx = 0; 1099ed367e6cSBorislav Petkov reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0; 1100ed367e6cSBorislav Petkov reg1->config = event->attr.config1; 1101ed367e6cSBorislav Petkov reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0; 1102ed367e6cSBorislav Petkov reg2->config = event->attr.config2; 1103ed367e6cSBorislav Petkov } 1104ed367e6cSBorislav Petkov return 0; 1105ed367e6cSBorislav Petkov } 1106ed367e6cSBorislav Petkov 1107ed367e6cSBorislav Petkov static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1108ed367e6cSBorislav Petkov { 1109ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1110ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1111ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1112ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 1113ed367e6cSBorislav Petkov 1114ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) { 1115ed367e6cSBorislav Petkov int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER; 1116b0529b9cSKan Liang int die = box->dieid; 1117b0529b9cSKan Liang struct pci_dev *filter_pdev = uncore_extra_pci_dev[die].dev[idx]; 1118cf6d445fSThomas Gleixner 1119ed367e6cSBorislav Petkov if (filter_pdev) { 1120ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg1->reg, 1121ed367e6cSBorislav Petkov (u32)reg1->config); 1122ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg1->reg + 4, 1123ed367e6cSBorislav Petkov (u32)(reg1->config >> 32)); 1124ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg2->reg, 1125ed367e6cSBorislav Petkov (u32)reg2->config); 1126ed367e6cSBorislav Petkov pci_write_config_dword(filter_pdev, reg2->reg + 4, 1127ed367e6cSBorislav Petkov (u32)(reg2->config >> 32)); 1128ed367e6cSBorislav Petkov } 1129ed367e6cSBorislav Petkov } 1130ed367e6cSBorislav Petkov 1131ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1132ed367e6cSBorislav Petkov } 1133ed367e6cSBorislav Petkov 1134ed367e6cSBorislav Petkov static struct intel_uncore_ops snbep_uncore_qpi_ops = { 1135ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_OPS_COMMON_INIT(), 1136ed367e6cSBorislav Petkov .enable_event = snbep_qpi_enable_event, 1137ed367e6cSBorislav Petkov .hw_config = snbep_qpi_hw_config, 1138ed367e6cSBorislav Petkov .get_constraint = uncore_get_constraint, 1139ed367e6cSBorislav Petkov .put_constraint = uncore_put_constraint, 1140ed367e6cSBorislav Petkov }; 1141ed367e6cSBorislav Petkov 1142ed367e6cSBorislav Petkov #define SNBEP_UNCORE_PCI_COMMON_INIT() \ 1143ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, \ 1144ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, \ 1145ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \ 1146ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ 1147ed367e6cSBorislav Petkov .ops = &snbep_uncore_pci_ops, \ 1148ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group 1149ed367e6cSBorislav Petkov 1150ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_ha = { 1151ed367e6cSBorislav Petkov .name = "ha", 1152ed367e6cSBorislav Petkov .num_counters = 4, 1153ed367e6cSBorislav Petkov .num_boxes = 1, 1154ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1155ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1156ed367e6cSBorislav Petkov }; 1157ed367e6cSBorislav Petkov 1158ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_imc = { 1159ed367e6cSBorislav Petkov .name = "imc", 1160ed367e6cSBorislav Petkov .num_counters = 4, 1161ed367e6cSBorislav Petkov .num_boxes = 4, 1162ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1163ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1164ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 1165ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 1166ed367e6cSBorislav Petkov .event_descs = snbep_uncore_imc_events, 1167ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1168ed367e6cSBorislav Petkov }; 1169ed367e6cSBorislav Petkov 1170ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_qpi = { 1171ed367e6cSBorislav Petkov .name = "qpi", 1172ed367e6cSBorislav Petkov .num_counters = 4, 1173ed367e6cSBorislav Petkov .num_boxes = 2, 1174ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1175ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 1176ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 1177ed367e6cSBorislav Petkov .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 1178ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1179ed367e6cSBorislav Petkov .num_shared_regs = 1, 1180ed367e6cSBorislav Petkov .ops = &snbep_uncore_qpi_ops, 1181ed367e6cSBorislav Petkov .event_descs = snbep_uncore_qpi_events, 1182ed367e6cSBorislav Petkov .format_group = &snbep_uncore_qpi_format_group, 1183ed367e6cSBorislav Petkov }; 1184ed367e6cSBorislav Petkov 1185ed367e6cSBorislav Petkov 1186ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_r2pcie = { 1187ed367e6cSBorislav Petkov .name = "r2pcie", 1188ed367e6cSBorislav Petkov .num_counters = 4, 1189ed367e6cSBorislav Petkov .num_boxes = 1, 1190ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1191ed367e6cSBorislav Petkov .constraints = snbep_uncore_r2pcie_constraints, 1192ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1193ed367e6cSBorislav Petkov }; 1194ed367e6cSBorislav Petkov 1195ed367e6cSBorislav Petkov static struct intel_uncore_type snbep_uncore_r3qpi = { 1196ed367e6cSBorislav Petkov .name = "r3qpi", 1197ed367e6cSBorislav Petkov .num_counters = 3, 1198ed367e6cSBorislav Petkov .num_boxes = 2, 1199ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1200ed367e6cSBorislav Petkov .constraints = snbep_uncore_r3qpi_constraints, 1201ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 1202ed367e6cSBorislav Petkov }; 1203ed367e6cSBorislav Petkov 1204ed367e6cSBorislav Petkov enum { 1205ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_HA, 1206ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_IMC, 1207ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_QPI, 1208ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_R2PCIE, 1209ed367e6cSBorislav Petkov SNBEP_PCI_UNCORE_R3QPI, 1210ed367e6cSBorislav Petkov }; 1211ed367e6cSBorislav Petkov 1212ed367e6cSBorislav Petkov static struct intel_uncore_type *snbep_pci_uncores[] = { 1213ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha, 1214ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc, 1215ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi, 1216ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie, 1217ed367e6cSBorislav Petkov [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi, 1218ed367e6cSBorislav Petkov NULL, 1219ed367e6cSBorislav Petkov }; 1220ed367e6cSBorislav Petkov 1221ed367e6cSBorislav Petkov static const struct pci_device_id snbep_uncore_pci_ids[] = { 1222ed367e6cSBorislav Petkov { /* Home Agent */ 1223ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA), 1224ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0), 1225ed367e6cSBorislav Petkov }, 1226ed367e6cSBorislav Petkov { /* MC Channel 0 */ 1227ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0), 1228ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0), 1229ed367e6cSBorislav Petkov }, 1230ed367e6cSBorislav Petkov { /* MC Channel 1 */ 1231ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1), 1232ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1), 1233ed367e6cSBorislav Petkov }, 1234ed367e6cSBorislav Petkov { /* MC Channel 2 */ 1235ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2), 1236ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2), 1237ed367e6cSBorislav Petkov }, 1238ed367e6cSBorislav Petkov { /* MC Channel 3 */ 1239ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3), 1240ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3), 1241ed367e6cSBorislav Petkov }, 1242ed367e6cSBorislav Petkov { /* QPI Port 0 */ 1243ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0), 1244ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0), 1245ed367e6cSBorislav Petkov }, 1246ed367e6cSBorislav Petkov { /* QPI Port 1 */ 1247ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1), 1248ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1), 1249ed367e6cSBorislav Petkov }, 1250ed367e6cSBorislav Petkov { /* R2PCIe */ 1251ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE), 1252ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0), 1253ed367e6cSBorislav Petkov }, 1254ed367e6cSBorislav Petkov { /* R3QPI Link 0 */ 1255ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0), 1256ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0), 1257ed367e6cSBorislav Petkov }, 1258ed367e6cSBorislav Petkov { /* R3QPI Link 1 */ 1259ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1), 1260ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1), 1261ed367e6cSBorislav Petkov }, 1262ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1263ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86), 1264ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1265ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER), 1266ed367e6cSBorislav Petkov }, 1267ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1268ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96), 1269ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1270ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER), 1271ed367e6cSBorislav Petkov }, 1272ed367e6cSBorislav Petkov { /* end: all zeroes */ } 1273ed367e6cSBorislav Petkov }; 1274ed367e6cSBorislav Petkov 1275ed367e6cSBorislav Petkov static struct pci_driver snbep_uncore_pci_driver = { 1276ed367e6cSBorislav Petkov .name = "snbep_uncore", 1277ed367e6cSBorislav Petkov .id_table = snbep_uncore_pci_ids, 1278ed367e6cSBorislav Petkov }; 1279ed367e6cSBorislav Petkov 12809e63a789SKan Liang #define NODE_ID_MASK 0x7 12819e63a789SKan Liang 1282ed367e6cSBorislav Petkov /* 1283ed367e6cSBorislav Petkov * build pci bus to socket mapping 1284ed367e6cSBorislav Petkov */ 128568ce4a0dSKan Liang static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool reverse) 1286ed367e6cSBorislav Petkov { 1287ed367e6cSBorislav Petkov struct pci_dev *ubox_dev = NULL; 1288ed367e6cSBorislav Petkov int i, bus, nodeid, segment; 1289ed367e6cSBorislav Petkov struct pci2phy_map *map; 1290ed367e6cSBorislav Petkov int err = 0; 1291ed367e6cSBorislav Petkov u32 config = 0; 1292ed367e6cSBorislav Petkov 1293ed367e6cSBorislav Petkov while (1) { 1294ed367e6cSBorislav Petkov /* find the UBOX device */ 1295ed367e6cSBorislav Petkov ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev); 1296ed367e6cSBorislav Petkov if (!ubox_dev) 1297ed367e6cSBorislav Petkov break; 1298ed367e6cSBorislav Petkov bus = ubox_dev->bus->number; 1299ed367e6cSBorislav Petkov /* get the Node ID of the local register */ 130068ce4a0dSKan Liang err = pci_read_config_dword(ubox_dev, nodeid_loc, &config); 1301ed367e6cSBorislav Petkov if (err) 1302ed367e6cSBorislav Petkov break; 13039e63a789SKan Liang nodeid = config & NODE_ID_MASK; 1304ed367e6cSBorislav Petkov /* get the Node ID mapping */ 130568ce4a0dSKan Liang err = pci_read_config_dword(ubox_dev, idmap_loc, &config); 1306ed367e6cSBorislav Petkov if (err) 1307ed367e6cSBorislav Petkov break; 1308ed367e6cSBorislav Petkov 1309ed367e6cSBorislav Petkov segment = pci_domain_nr(ubox_dev->bus); 1310ed367e6cSBorislav Petkov raw_spin_lock(&pci2phy_map_lock); 1311ed367e6cSBorislav Petkov map = __find_pci2phy_map(segment); 1312ed367e6cSBorislav Petkov if (!map) { 1313ed367e6cSBorislav Petkov raw_spin_unlock(&pci2phy_map_lock); 1314ed367e6cSBorislav Petkov err = -ENOMEM; 1315ed367e6cSBorislav Petkov break; 1316ed367e6cSBorislav Petkov } 1317ed367e6cSBorislav Petkov 1318ed367e6cSBorislav Petkov /* 1319ed367e6cSBorislav Petkov * every three bits in the Node ID mapping register maps 1320ed367e6cSBorislav Petkov * to a particular node. 1321ed367e6cSBorislav Petkov */ 1322ed367e6cSBorislav Petkov for (i = 0; i < 8; i++) { 1323ed367e6cSBorislav Petkov if (nodeid == ((config >> (3 * i)) & 0x7)) { 1324ed367e6cSBorislav Petkov map->pbus_to_physid[bus] = i; 1325ed367e6cSBorislav Petkov break; 1326ed367e6cSBorislav Petkov } 1327ed367e6cSBorislav Petkov } 1328ed367e6cSBorislav Petkov raw_spin_unlock(&pci2phy_map_lock); 1329ed367e6cSBorislav Petkov } 1330ed367e6cSBorislav Petkov 1331ed367e6cSBorislav Petkov if (!err) { 1332ed367e6cSBorislav Petkov /* 1333ed367e6cSBorislav Petkov * For PCI bus with no UBOX device, find the next bus 1334ed367e6cSBorislav Petkov * that has UBOX device and use its mapping. 1335ed367e6cSBorislav Petkov */ 1336ed367e6cSBorislav Petkov raw_spin_lock(&pci2phy_map_lock); 1337ed367e6cSBorislav Petkov list_for_each_entry(map, &pci2phy_map_head, list) { 1338ed367e6cSBorislav Petkov i = -1; 133968ce4a0dSKan Liang if (reverse) { 1340ed367e6cSBorislav Petkov for (bus = 255; bus >= 0; bus--) { 1341ed367e6cSBorislav Petkov if (map->pbus_to_physid[bus] >= 0) 1342ed367e6cSBorislav Petkov i = map->pbus_to_physid[bus]; 1343ed367e6cSBorislav Petkov else 1344ed367e6cSBorislav Petkov map->pbus_to_physid[bus] = i; 1345ed367e6cSBorislav Petkov } 134668ce4a0dSKan Liang } else { 134768ce4a0dSKan Liang for (bus = 0; bus <= 255; bus++) { 134868ce4a0dSKan Liang if (map->pbus_to_physid[bus] >= 0) 134968ce4a0dSKan Liang i = map->pbus_to_physid[bus]; 135068ce4a0dSKan Liang else 135168ce4a0dSKan Liang map->pbus_to_physid[bus] = i; 135268ce4a0dSKan Liang } 135368ce4a0dSKan Liang } 1354ed367e6cSBorislav Petkov } 1355ed367e6cSBorislav Petkov raw_spin_unlock(&pci2phy_map_lock); 1356ed367e6cSBorislav Petkov } 1357ed367e6cSBorislav Petkov 1358ed367e6cSBorislav Petkov pci_dev_put(ubox_dev); 1359ed367e6cSBorislav Petkov 1360ed367e6cSBorislav Petkov return err ? pcibios_err_to_errno(err) : 0; 1361ed367e6cSBorislav Petkov } 1362ed367e6cSBorislav Petkov 1363ed367e6cSBorislav Petkov int snbep_uncore_pci_init(void) 1364ed367e6cSBorislav Petkov { 136568ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x3ce0, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 1366ed367e6cSBorislav Petkov if (ret) 1367ed367e6cSBorislav Petkov return ret; 1368ed367e6cSBorislav Petkov uncore_pci_uncores = snbep_pci_uncores; 1369ed367e6cSBorislav Petkov uncore_pci_driver = &snbep_uncore_pci_driver; 1370ed367e6cSBorislav Petkov return 0; 1371ed367e6cSBorislav Petkov } 1372ed367e6cSBorislav Petkov /* end of Sandy Bridge-EP uncore support */ 1373ed367e6cSBorislav Petkov 1374ed367e6cSBorislav Petkov /* IvyTown uncore support */ 1375ed367e6cSBorislav Petkov static void ivbep_uncore_msr_init_box(struct intel_uncore_box *box) 1376ed367e6cSBorislav Petkov { 1377ed367e6cSBorislav Petkov unsigned msr = uncore_msr_box_ctl(box); 1378ed367e6cSBorislav Petkov if (msr) 1379ed367e6cSBorislav Petkov wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT); 1380ed367e6cSBorislav Petkov } 1381ed367e6cSBorislav Petkov 1382ed367e6cSBorislav Petkov static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box) 1383ed367e6cSBorislav Petkov { 1384ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1385ed367e6cSBorislav Petkov 1386ed367e6cSBorislav Petkov pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 1387ed367e6cSBorislav Petkov } 1388ed367e6cSBorislav Petkov 1389ed367e6cSBorislav Petkov #define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 1390ed367e6cSBorislav Petkov .init_box = ivbep_uncore_msr_init_box, \ 1391ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, \ 1392ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, \ 1393ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, \ 1394ed367e6cSBorislav Petkov .enable_event = snbep_uncore_msr_enable_event, \ 1395ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter 1396ed367e6cSBorislav Petkov 1397ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_msr_ops = { 1398ed367e6cSBorislav Petkov IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1399ed367e6cSBorislav Petkov }; 1400ed367e6cSBorislav Petkov 1401ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_pci_ops = { 1402ed367e6cSBorislav Petkov .init_box = ivbep_uncore_pci_init_box, 1403ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 1404ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 1405ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, 1406ed367e6cSBorislav Petkov .enable_event = snbep_uncore_pci_enable_event, 1407ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter, 1408ed367e6cSBorislav Petkov }; 1409ed367e6cSBorislav Petkov 1410ed367e6cSBorislav Petkov #define IVBEP_UNCORE_PCI_COMMON_INIT() \ 1411ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, \ 1412ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, \ 1413ed367e6cSBorislav Petkov .event_mask = IVBEP_PMON_RAW_EVENT_MASK, \ 1414ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ 1415ed367e6cSBorislav Petkov .ops = &ivbep_uncore_pci_ops, \ 1416ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_format_group 1417ed367e6cSBorislav Petkov 1418ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_formats_attr[] = { 1419ed367e6cSBorislav Petkov &format_attr_event.attr, 1420ed367e6cSBorislav Petkov &format_attr_umask.attr, 1421ed367e6cSBorislav Petkov &format_attr_edge.attr, 1422ed367e6cSBorislav Petkov &format_attr_inv.attr, 1423ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1424ed367e6cSBorislav Petkov NULL, 1425ed367e6cSBorislav Petkov }; 1426ed367e6cSBorislav Petkov 1427ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_ubox_formats_attr[] = { 1428ed367e6cSBorislav Petkov &format_attr_event.attr, 1429ed367e6cSBorislav Petkov &format_attr_umask.attr, 1430ed367e6cSBorislav Petkov &format_attr_edge.attr, 1431ed367e6cSBorislav Petkov &format_attr_inv.attr, 1432ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 1433ed367e6cSBorislav Petkov NULL, 1434ed367e6cSBorislav Petkov }; 1435ed367e6cSBorislav Petkov 1436ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_cbox_formats_attr[] = { 1437ed367e6cSBorislav Petkov &format_attr_event.attr, 1438ed367e6cSBorislav Petkov &format_attr_umask.attr, 1439ed367e6cSBorislav Petkov &format_attr_edge.attr, 1440ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 1441ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1442ed367e6cSBorislav Petkov &format_attr_filter_tid.attr, 1443ed367e6cSBorislav Petkov &format_attr_filter_link.attr, 1444ed367e6cSBorislav Petkov &format_attr_filter_state2.attr, 1445ed367e6cSBorislav Petkov &format_attr_filter_nid2.attr, 1446ed367e6cSBorislav Petkov &format_attr_filter_opc2.attr, 1447ed367e6cSBorislav Petkov &format_attr_filter_nc.attr, 1448ed367e6cSBorislav Petkov &format_attr_filter_c6.attr, 1449ed367e6cSBorislav Petkov &format_attr_filter_isoc.attr, 1450ed367e6cSBorislav Petkov NULL, 1451ed367e6cSBorislav Petkov }; 1452ed367e6cSBorislav Petkov 1453ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_pcu_formats_attr[] = { 1454cb225252SKan Liang &format_attr_event.attr, 1455ed367e6cSBorislav Petkov &format_attr_occ_sel.attr, 1456ed367e6cSBorislav Petkov &format_attr_edge.attr, 1457ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 1458ed367e6cSBorislav Petkov &format_attr_occ_invert.attr, 1459ed367e6cSBorislav Petkov &format_attr_occ_edge.attr, 1460ed367e6cSBorislav Petkov &format_attr_filter_band0.attr, 1461ed367e6cSBorislav Petkov &format_attr_filter_band1.attr, 1462ed367e6cSBorislav Petkov &format_attr_filter_band2.attr, 1463ed367e6cSBorislav Petkov &format_attr_filter_band3.attr, 1464ed367e6cSBorislav Petkov NULL, 1465ed367e6cSBorislav Petkov }; 1466ed367e6cSBorislav Petkov 1467ed367e6cSBorislav Petkov static struct attribute *ivbep_uncore_qpi_formats_attr[] = { 1468ed367e6cSBorislav Petkov &format_attr_event_ext.attr, 1469ed367e6cSBorislav Petkov &format_attr_umask.attr, 1470ed367e6cSBorislav Petkov &format_attr_edge.attr, 1471ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1472ed367e6cSBorislav Petkov &format_attr_match_rds.attr, 1473ed367e6cSBorislav Petkov &format_attr_match_rnid30.attr, 1474ed367e6cSBorislav Petkov &format_attr_match_rnid4.attr, 1475ed367e6cSBorislav Petkov &format_attr_match_dnid.attr, 1476ed367e6cSBorislav Petkov &format_attr_match_mc.attr, 1477ed367e6cSBorislav Petkov &format_attr_match_opc.attr, 1478ed367e6cSBorislav Petkov &format_attr_match_vnw.attr, 1479ed367e6cSBorislav Petkov &format_attr_match0.attr, 1480ed367e6cSBorislav Petkov &format_attr_match1.attr, 1481ed367e6cSBorislav Petkov &format_attr_mask_rds.attr, 1482ed367e6cSBorislav Petkov &format_attr_mask_rnid30.attr, 1483ed367e6cSBorislav Petkov &format_attr_mask_rnid4.attr, 1484ed367e6cSBorislav Petkov &format_attr_mask_dnid.attr, 1485ed367e6cSBorislav Petkov &format_attr_mask_mc.attr, 1486ed367e6cSBorislav Petkov &format_attr_mask_opc.attr, 1487ed367e6cSBorislav Petkov &format_attr_mask_vnw.attr, 1488ed367e6cSBorislav Petkov &format_attr_mask0.attr, 1489ed367e6cSBorislav Petkov &format_attr_mask1.attr, 1490ed367e6cSBorislav Petkov NULL, 1491ed367e6cSBorislav Petkov }; 1492ed367e6cSBorislav Petkov 149345bd07adSArvind Yadav static const struct attribute_group ivbep_uncore_format_group = { 1494ed367e6cSBorislav Petkov .name = "format", 1495ed367e6cSBorislav Petkov .attrs = ivbep_uncore_formats_attr, 1496ed367e6cSBorislav Petkov }; 1497ed367e6cSBorislav Petkov 149845bd07adSArvind Yadav static const struct attribute_group ivbep_uncore_ubox_format_group = { 1499ed367e6cSBorislav Petkov .name = "format", 1500ed367e6cSBorislav Petkov .attrs = ivbep_uncore_ubox_formats_attr, 1501ed367e6cSBorislav Petkov }; 1502ed367e6cSBorislav Petkov 150345bd07adSArvind Yadav static const struct attribute_group ivbep_uncore_cbox_format_group = { 1504ed367e6cSBorislav Petkov .name = "format", 1505ed367e6cSBorislav Petkov .attrs = ivbep_uncore_cbox_formats_attr, 1506ed367e6cSBorislav Petkov }; 1507ed367e6cSBorislav Petkov 150845bd07adSArvind Yadav static const struct attribute_group ivbep_uncore_pcu_format_group = { 1509ed367e6cSBorislav Petkov .name = "format", 1510ed367e6cSBorislav Petkov .attrs = ivbep_uncore_pcu_formats_attr, 1511ed367e6cSBorislav Petkov }; 1512ed367e6cSBorislav Petkov 151345bd07adSArvind Yadav static const struct attribute_group ivbep_uncore_qpi_format_group = { 1514ed367e6cSBorislav Petkov .name = "format", 1515ed367e6cSBorislav Petkov .attrs = ivbep_uncore_qpi_formats_attr, 1516ed367e6cSBorislav Petkov }; 1517ed367e6cSBorislav Petkov 1518ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_ubox = { 1519ed367e6cSBorislav Petkov .name = "ubox", 1520ed367e6cSBorislav Petkov .num_counters = 2, 1521ed367e6cSBorislav Petkov .num_boxes = 1, 1522ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1523ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1524ed367e6cSBorislav Petkov .perf_ctr = SNBEP_U_MSR_PMON_CTR0, 1525ed367e6cSBorislav Petkov .event_ctl = SNBEP_U_MSR_PMON_CTL0, 1526ed367e6cSBorislav Petkov .event_mask = IVBEP_U_MSR_PMON_RAW_EVENT_MASK, 1527ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, 1528ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, 1529ed367e6cSBorislav Petkov .ops = &ivbep_uncore_msr_ops, 1530ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_ubox_format_group, 1531ed367e6cSBorislav Petkov }; 1532ed367e6cSBorislav Petkov 1533ed367e6cSBorislav Petkov static struct extra_reg ivbep_uncore_cbox_extra_regs[] = { 1534ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 1535ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 1536ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2), 1537ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 1538ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc), 1539ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc), 1540ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 1541ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc), 1542ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 1543ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc), 1544ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 1545ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc), 1546ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10), 1547ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10), 1548ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10), 1549ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10), 1550ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18), 1551ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18), 1552ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8), 1553ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8), 1554ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8), 1555ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8), 1556ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10), 1557ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10), 1558ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10), 1559ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10), 1560ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10), 1561ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10), 1562ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18), 1563ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18), 1564ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8), 1565ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8), 1566ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8), 1567ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8), 1568ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10), 1569ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10), 1570ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8), 1571ed367e6cSBorislav Petkov EVENT_EXTRA_END 1572ed367e6cSBorislav Petkov }; 1573ed367e6cSBorislav Petkov 1574ed367e6cSBorislav Petkov static u64 ivbep_cbox_filter_mask(int fields) 1575ed367e6cSBorislav Petkov { 1576ed367e6cSBorislav Petkov u64 mask = 0; 1577ed367e6cSBorislav Petkov 1578ed367e6cSBorislav Petkov if (fields & 0x1) 1579ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_TID; 1580ed367e6cSBorislav Petkov if (fields & 0x2) 1581ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK; 1582ed367e6cSBorislav Petkov if (fields & 0x4) 1583ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE; 1584ed367e6cSBorislav Petkov if (fields & 0x8) 1585ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NID; 1586ed367e6cSBorislav Petkov if (fields & 0x10) { 1587ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC; 1588ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NC; 1589ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_C6; 1590ed367e6cSBorislav Petkov mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC; 1591ed367e6cSBorislav Petkov } 1592ed367e6cSBorislav Petkov 1593ed367e6cSBorislav Petkov return mask; 1594ed367e6cSBorislav Petkov } 1595ed367e6cSBorislav Petkov 1596ed367e6cSBorislav Petkov static struct event_constraint * 1597ed367e6cSBorislav Petkov ivbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 1598ed367e6cSBorislav Petkov { 1599ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, ivbep_cbox_filter_mask); 1600ed367e6cSBorislav Petkov } 1601ed367e6cSBorislav Petkov 1602ed367e6cSBorislav Petkov static int ivbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1603ed367e6cSBorislav Petkov { 1604ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1605ed367e6cSBorislav Petkov struct extra_reg *er; 1606ed367e6cSBorislav Petkov int idx = 0; 1607ed367e6cSBorislav Petkov 1608ed367e6cSBorislav Petkov for (er = ivbep_uncore_cbox_extra_regs; er->msr; er++) { 1609ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 1610ed367e6cSBorislav Petkov continue; 1611ed367e6cSBorislav Petkov idx |= er->idx; 1612ed367e6cSBorislav Petkov } 1613ed367e6cSBorislav Petkov 1614ed367e6cSBorislav Petkov if (idx) { 1615ed367e6cSBorislav Petkov reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + 1616ed367e6cSBorislav Petkov SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 1617ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx); 1618ed367e6cSBorislav Petkov reg1->idx = idx; 1619ed367e6cSBorislav Petkov } 1620ed367e6cSBorislav Petkov return 0; 1621ed367e6cSBorislav Petkov } 1622ed367e6cSBorislav Petkov 1623ed367e6cSBorislav Petkov static void ivbep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1624ed367e6cSBorislav Petkov { 1625ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1626ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1627ed367e6cSBorislav Petkov 1628ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) { 1629ed367e6cSBorislav Petkov u64 filter = uncore_shared_reg_config(box, 0); 1630ed367e6cSBorislav Petkov wrmsrl(reg1->reg, filter & 0xffffffff); 1631ed367e6cSBorislav Petkov wrmsrl(reg1->reg + 6, filter >> 32); 1632ed367e6cSBorislav Petkov } 1633ed367e6cSBorislav Petkov 1634ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1635ed367e6cSBorislav Petkov } 1636ed367e6cSBorislav Petkov 1637ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_cbox_ops = { 1638ed367e6cSBorislav Petkov .init_box = ivbep_uncore_msr_init_box, 1639ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, 1640ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, 1641ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, 1642ed367e6cSBorislav Petkov .enable_event = ivbep_cbox_enable_event, 1643ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter, 1644ed367e6cSBorislav Petkov .hw_config = ivbep_cbox_hw_config, 1645ed367e6cSBorislav Petkov .get_constraint = ivbep_cbox_get_constraint, 1646ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 1647ed367e6cSBorislav Petkov }; 1648ed367e6cSBorislav Petkov 1649ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_cbox = { 1650ed367e6cSBorislav Petkov .name = "cbox", 1651ed367e6cSBorislav Petkov .num_counters = 4, 1652ed367e6cSBorislav Petkov .num_boxes = 15, 1653ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1654ed367e6cSBorislav Petkov .event_ctl = SNBEP_C0_MSR_PMON_CTL0, 1655ed367e6cSBorislav Petkov .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, 1656ed367e6cSBorislav Petkov .event_mask = IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 1657ed367e6cSBorislav Petkov .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, 1658ed367e6cSBorislav Petkov .msr_offset = SNBEP_CBO_MSR_OFFSET, 1659ed367e6cSBorislav Petkov .num_shared_regs = 1, 1660ed367e6cSBorislav Petkov .constraints = snbep_uncore_cbox_constraints, 1661ed367e6cSBorislav Petkov .ops = &ivbep_uncore_cbox_ops, 1662ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_cbox_format_group, 1663ed367e6cSBorislav Petkov }; 1664ed367e6cSBorislav Petkov 1665ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_pcu_ops = { 1666ed367e6cSBorislav Petkov IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1667ed367e6cSBorislav Petkov .hw_config = snbep_pcu_hw_config, 1668ed367e6cSBorislav Petkov .get_constraint = snbep_pcu_get_constraint, 1669ed367e6cSBorislav Petkov .put_constraint = snbep_pcu_put_constraint, 1670ed367e6cSBorislav Petkov }; 1671ed367e6cSBorislav Petkov 1672ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_pcu = { 1673ed367e6cSBorislav Petkov .name = "pcu", 1674ed367e6cSBorislav Petkov .num_counters = 4, 1675ed367e6cSBorislav Petkov .num_boxes = 1, 1676ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1677ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, 1678ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, 1679ed367e6cSBorislav Petkov .event_mask = IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 1680ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, 1681ed367e6cSBorislav Petkov .num_shared_regs = 1, 1682ed367e6cSBorislav Petkov .ops = &ivbep_uncore_pcu_ops, 1683ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_pcu_format_group, 1684ed367e6cSBorislav Petkov }; 1685ed367e6cSBorislav Petkov 1686ed367e6cSBorislav Petkov static struct intel_uncore_type *ivbep_msr_uncores[] = { 1687ed367e6cSBorislav Petkov &ivbep_uncore_ubox, 1688ed367e6cSBorislav Petkov &ivbep_uncore_cbox, 1689ed367e6cSBorislav Petkov &ivbep_uncore_pcu, 1690ed367e6cSBorislav Petkov NULL, 1691ed367e6cSBorislav Petkov }; 1692ed367e6cSBorislav Petkov 1693ed367e6cSBorislav Petkov void ivbep_uncore_cpu_init(void) 1694ed367e6cSBorislav Petkov { 1695ed367e6cSBorislav Petkov if (ivbep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 1696ed367e6cSBorislav Petkov ivbep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 1697ed367e6cSBorislav Petkov uncore_msr_uncores = ivbep_msr_uncores; 1698ed367e6cSBorislav Petkov } 1699ed367e6cSBorislav Petkov 1700ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_ha = { 1701ed367e6cSBorislav Petkov .name = "ha", 1702ed367e6cSBorislav Petkov .num_counters = 4, 1703ed367e6cSBorislav Petkov .num_boxes = 2, 1704ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1705ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1706ed367e6cSBorislav Petkov }; 1707ed367e6cSBorislav Petkov 1708ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_imc = { 1709ed367e6cSBorislav Petkov .name = "imc", 1710ed367e6cSBorislav Petkov .num_counters = 4, 1711ed367e6cSBorislav Petkov .num_boxes = 8, 1712ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1713ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1714ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 1715ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 1716ed367e6cSBorislav Petkov .event_descs = snbep_uncore_imc_events, 1717ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1718ed367e6cSBorislav Petkov }; 1719ed367e6cSBorislav Petkov 1720ed367e6cSBorislav Petkov /* registers in IRP boxes are not properly aligned */ 1721ed367e6cSBorislav Petkov static unsigned ivbep_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4}; 1722ed367e6cSBorislav Petkov static unsigned ivbep_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0}; 1723ed367e6cSBorislav Petkov 1724ed367e6cSBorislav Petkov static void ivbep_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1725ed367e6cSBorislav Petkov { 1726ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1727ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1728ed367e6cSBorislav Petkov 1729ed367e6cSBorislav Petkov pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], 1730ed367e6cSBorislav Petkov hwc->config | SNBEP_PMON_CTL_EN); 1731ed367e6cSBorislav Petkov } 1732ed367e6cSBorislav Petkov 1733ed367e6cSBorislav Petkov static void ivbep_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event) 1734ed367e6cSBorislav Petkov { 1735ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1736ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1737ed367e6cSBorislav Petkov 1738ed367e6cSBorislav Petkov pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], hwc->config); 1739ed367e6cSBorislav Petkov } 1740ed367e6cSBorislav Petkov 1741ed367e6cSBorislav Petkov static u64 ivbep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) 1742ed367e6cSBorislav Petkov { 1743ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 1744ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1745ed367e6cSBorislav Petkov u64 count = 0; 1746ed367e6cSBorislav Petkov 1747ed367e6cSBorislav Petkov pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx], (u32 *)&count); 1748ed367e6cSBorislav Petkov pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1); 1749ed367e6cSBorislav Petkov 1750ed367e6cSBorislav Petkov return count; 1751ed367e6cSBorislav Petkov } 1752ed367e6cSBorislav Petkov 1753ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_irp_ops = { 1754ed367e6cSBorislav Petkov .init_box = ivbep_uncore_pci_init_box, 1755ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 1756ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 1757ed367e6cSBorislav Petkov .disable_event = ivbep_uncore_irp_disable_event, 1758ed367e6cSBorislav Petkov .enable_event = ivbep_uncore_irp_enable_event, 1759ed367e6cSBorislav Petkov .read_counter = ivbep_uncore_irp_read_counter, 1760ed367e6cSBorislav Petkov }; 1761ed367e6cSBorislav Petkov 1762ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_irp = { 1763ed367e6cSBorislav Petkov .name = "irp", 1764ed367e6cSBorislav Petkov .num_counters = 4, 1765ed367e6cSBorislav Petkov .num_boxes = 1, 1766ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1767ed367e6cSBorislav Petkov .event_mask = IVBEP_PMON_RAW_EVENT_MASK, 1768ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1769ed367e6cSBorislav Petkov .ops = &ivbep_uncore_irp_ops, 1770ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_format_group, 1771ed367e6cSBorislav Petkov }; 1772ed367e6cSBorislav Petkov 1773ed367e6cSBorislav Petkov static struct intel_uncore_ops ivbep_uncore_qpi_ops = { 1774ed367e6cSBorislav Petkov .init_box = ivbep_uncore_pci_init_box, 1775ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 1776ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 1777ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, 1778ed367e6cSBorislav Petkov .enable_event = snbep_qpi_enable_event, 1779ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter, 1780ed367e6cSBorislav Petkov .hw_config = snbep_qpi_hw_config, 1781ed367e6cSBorislav Petkov .get_constraint = uncore_get_constraint, 1782ed367e6cSBorislav Petkov .put_constraint = uncore_put_constraint, 1783ed367e6cSBorislav Petkov }; 1784ed367e6cSBorislav Petkov 1785ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_qpi = { 1786ed367e6cSBorislav Petkov .name = "qpi", 1787ed367e6cSBorislav Petkov .num_counters = 4, 1788ed367e6cSBorislav Petkov .num_boxes = 3, 1789ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1790ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 1791ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 1792ed367e6cSBorislav Petkov .event_mask = IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 1793ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1794ed367e6cSBorislav Petkov .num_shared_regs = 1, 1795ed367e6cSBorislav Petkov .ops = &ivbep_uncore_qpi_ops, 1796ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_qpi_format_group, 1797ed367e6cSBorislav Petkov }; 1798ed367e6cSBorislav Petkov 1799ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_r2pcie = { 1800ed367e6cSBorislav Petkov .name = "r2pcie", 1801ed367e6cSBorislav Petkov .num_counters = 4, 1802ed367e6cSBorislav Petkov .num_boxes = 1, 1803ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1804ed367e6cSBorislav Petkov .constraints = snbep_uncore_r2pcie_constraints, 1805ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1806ed367e6cSBorislav Petkov }; 1807ed367e6cSBorislav Petkov 1808ed367e6cSBorislav Petkov static struct intel_uncore_type ivbep_uncore_r3qpi = { 1809ed367e6cSBorislav Petkov .name = "r3qpi", 1810ed367e6cSBorislav Petkov .num_counters = 3, 1811ed367e6cSBorislav Petkov .num_boxes = 2, 1812ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 1813ed367e6cSBorislav Petkov .constraints = snbep_uncore_r3qpi_constraints, 1814ed367e6cSBorislav Petkov IVBEP_UNCORE_PCI_COMMON_INIT(), 1815ed367e6cSBorislav Petkov }; 1816ed367e6cSBorislav Petkov 1817ed367e6cSBorislav Petkov enum { 1818ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_HA, 1819ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_IMC, 1820ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_IRP, 1821ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_QPI, 1822ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_R2PCIE, 1823ed367e6cSBorislav Petkov IVBEP_PCI_UNCORE_R3QPI, 1824ed367e6cSBorislav Petkov }; 1825ed367e6cSBorislav Petkov 1826ed367e6cSBorislav Petkov static struct intel_uncore_type *ivbep_pci_uncores[] = { 1827ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_HA] = &ivbep_uncore_ha, 1828ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_IMC] = &ivbep_uncore_imc, 1829ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_IRP] = &ivbep_uncore_irp, 1830ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_QPI] = &ivbep_uncore_qpi, 1831ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_R2PCIE] = &ivbep_uncore_r2pcie, 1832ed367e6cSBorislav Petkov [IVBEP_PCI_UNCORE_R3QPI] = &ivbep_uncore_r3qpi, 1833ed367e6cSBorislav Petkov NULL, 1834ed367e6cSBorislav Petkov }; 1835ed367e6cSBorislav Petkov 1836ed367e6cSBorislav Petkov static const struct pci_device_id ivbep_uncore_pci_ids[] = { 1837ed367e6cSBorislav Petkov { /* Home Agent 0 */ 1838ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30), 1839ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 0), 1840ed367e6cSBorislav Petkov }, 1841ed367e6cSBorislav Petkov { /* Home Agent 1 */ 1842ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38), 1843ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 1), 1844ed367e6cSBorislav Petkov }, 1845ed367e6cSBorislav Petkov { /* MC0 Channel 0 */ 1846ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4), 1847ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 0), 1848ed367e6cSBorislav Petkov }, 1849ed367e6cSBorislav Petkov { /* MC0 Channel 1 */ 1850ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5), 1851ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 1), 1852ed367e6cSBorislav Petkov }, 1853ed367e6cSBorislav Petkov { /* MC0 Channel 3 */ 1854ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0), 1855ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 2), 1856ed367e6cSBorislav Petkov }, 1857ed367e6cSBorislav Petkov { /* MC0 Channel 4 */ 1858ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1), 1859ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 3), 1860ed367e6cSBorislav Petkov }, 1861ed367e6cSBorislav Petkov { /* MC1 Channel 0 */ 1862ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4), 1863ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 4), 1864ed367e6cSBorislav Petkov }, 1865ed367e6cSBorislav Petkov { /* MC1 Channel 1 */ 1866ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5), 1867ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 5), 1868ed367e6cSBorislav Petkov }, 1869ed367e6cSBorislav Petkov { /* MC1 Channel 3 */ 1870ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0), 1871ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 6), 1872ed367e6cSBorislav Petkov }, 1873ed367e6cSBorislav Petkov { /* MC1 Channel 4 */ 1874ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1), 1875ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 7), 1876ed367e6cSBorislav Petkov }, 1877ed367e6cSBorislav Petkov { /* IRP */ 1878ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39), 1879ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IRP, 0), 1880ed367e6cSBorislav Petkov }, 1881ed367e6cSBorislav Petkov { /* QPI0 Port 0 */ 1882ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32), 1883ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 0), 1884ed367e6cSBorislav Petkov }, 1885ed367e6cSBorislav Petkov { /* QPI0 Port 1 */ 1886ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33), 1887ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 1), 1888ed367e6cSBorislav Petkov }, 1889ed367e6cSBorislav Petkov { /* QPI1 Port 2 */ 1890ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a), 1891ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 2), 1892ed367e6cSBorislav Petkov }, 1893ed367e6cSBorislav Petkov { /* R2PCIe */ 1894ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34), 1895ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R2PCIE, 0), 1896ed367e6cSBorislav Petkov }, 1897ed367e6cSBorislav Petkov { /* R3QPI0 Link 0 */ 1898ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36), 1899ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 0), 1900ed367e6cSBorislav Petkov }, 1901ed367e6cSBorislav Petkov { /* R3QPI0 Link 1 */ 1902ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37), 1903ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 1), 1904ed367e6cSBorislav Petkov }, 1905ed367e6cSBorislav Petkov { /* R3QPI1 Link 2 */ 1906ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e), 1907ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 2), 1908ed367e6cSBorislav Petkov }, 1909ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1910ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86), 1911ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1912ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER), 1913ed367e6cSBorislav Petkov }, 1914ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 1915ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96), 1916ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1917ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER), 1918ed367e6cSBorislav Petkov }, 1919ed367e6cSBorislav Petkov { /* end: all zeroes */ } 1920ed367e6cSBorislav Petkov }; 1921ed367e6cSBorislav Petkov 1922ed367e6cSBorislav Petkov static struct pci_driver ivbep_uncore_pci_driver = { 1923ed367e6cSBorislav Petkov .name = "ivbep_uncore", 1924ed367e6cSBorislav Petkov .id_table = ivbep_uncore_pci_ids, 1925ed367e6cSBorislav Petkov }; 1926ed367e6cSBorislav Petkov 1927ed367e6cSBorislav Petkov int ivbep_uncore_pci_init(void) 1928ed367e6cSBorislav Petkov { 192968ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x0e1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 1930ed367e6cSBorislav Petkov if (ret) 1931ed367e6cSBorislav Petkov return ret; 1932ed367e6cSBorislav Petkov uncore_pci_uncores = ivbep_pci_uncores; 1933ed367e6cSBorislav Petkov uncore_pci_driver = &ivbep_uncore_pci_driver; 1934ed367e6cSBorislav Petkov return 0; 1935ed367e6cSBorislav Petkov } 1936ed367e6cSBorislav Petkov /* end of IvyTown uncore support */ 1937ed367e6cSBorislav Petkov 1938ed367e6cSBorislav Petkov /* KNL uncore support */ 1939ed367e6cSBorislav Petkov static struct attribute *knl_uncore_ubox_formats_attr[] = { 1940ed367e6cSBorislav Petkov &format_attr_event.attr, 1941ed367e6cSBorislav Petkov &format_attr_umask.attr, 1942ed367e6cSBorislav Petkov &format_attr_edge.attr, 1943ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 1944ed367e6cSBorislav Petkov &format_attr_inv.attr, 1945ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 1946ed367e6cSBorislav Petkov NULL, 1947ed367e6cSBorislav Petkov }; 1948ed367e6cSBorislav Petkov 194945bd07adSArvind Yadav static const struct attribute_group knl_uncore_ubox_format_group = { 1950ed367e6cSBorislav Petkov .name = "format", 1951ed367e6cSBorislav Petkov .attrs = knl_uncore_ubox_formats_attr, 1952ed367e6cSBorislav Petkov }; 1953ed367e6cSBorislav Petkov 1954ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_ubox = { 1955ed367e6cSBorislav Petkov .name = "ubox", 1956ed367e6cSBorislav Petkov .num_counters = 2, 1957ed367e6cSBorislav Petkov .num_boxes = 1, 1958ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 1959ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 1960ed367e6cSBorislav Petkov .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 1961ed367e6cSBorislav Petkov .event_ctl = HSWEP_U_MSR_PMON_CTL0, 1962ed367e6cSBorislav Petkov .event_mask = KNL_U_MSR_PMON_RAW_EVENT_MASK, 1963ed367e6cSBorislav Petkov .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 1964ed367e6cSBorislav Petkov .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 1965ed367e6cSBorislav Petkov .ops = &snbep_uncore_msr_ops, 1966ed367e6cSBorislav Petkov .format_group = &knl_uncore_ubox_format_group, 1967ed367e6cSBorislav Petkov }; 1968ed367e6cSBorislav Petkov 1969ed367e6cSBorislav Petkov static struct attribute *knl_uncore_cha_formats_attr[] = { 1970ed367e6cSBorislav Petkov &format_attr_event.attr, 1971ed367e6cSBorislav Petkov &format_attr_umask.attr, 1972ed367e6cSBorislav Petkov &format_attr_qor.attr, 1973ed367e6cSBorislav Petkov &format_attr_edge.attr, 1974ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 1975ed367e6cSBorislav Petkov &format_attr_inv.attr, 1976ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 1977ed367e6cSBorislav Petkov &format_attr_filter_tid4.attr, 1978ed367e6cSBorislav Petkov &format_attr_filter_link3.attr, 1979ed367e6cSBorislav Petkov &format_attr_filter_state4.attr, 1980ed367e6cSBorislav Petkov &format_attr_filter_local.attr, 1981ed367e6cSBorislav Petkov &format_attr_filter_all_op.attr, 1982ed367e6cSBorislav Petkov &format_attr_filter_nnm.attr, 1983ed367e6cSBorislav Petkov &format_attr_filter_opc3.attr, 1984ed367e6cSBorislav Petkov &format_attr_filter_nc.attr, 1985ed367e6cSBorislav Petkov &format_attr_filter_isoc.attr, 1986ed367e6cSBorislav Petkov NULL, 1987ed367e6cSBorislav Petkov }; 1988ed367e6cSBorislav Petkov 198945bd07adSArvind Yadav static const struct attribute_group knl_uncore_cha_format_group = { 1990ed367e6cSBorislav Petkov .name = "format", 1991ed367e6cSBorislav Petkov .attrs = knl_uncore_cha_formats_attr, 1992ed367e6cSBorislav Petkov }; 1993ed367e6cSBorislav Petkov 1994ed367e6cSBorislav Petkov static struct event_constraint knl_uncore_cha_constraints[] = { 1995ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 1996ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), 1997ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 1998ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 1999ed367e6cSBorislav Petkov }; 2000ed367e6cSBorislav Petkov 2001ed367e6cSBorislav Petkov static struct extra_reg knl_uncore_cha_extra_regs[] = { 2002ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 2003ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 2004ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2), 2005ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4), 2006ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4), 2007ed367e6cSBorislav Petkov EVENT_EXTRA_END 2008ed367e6cSBorislav Petkov }; 2009ed367e6cSBorislav Petkov 2010ed367e6cSBorislav Petkov static u64 knl_cha_filter_mask(int fields) 2011ed367e6cSBorislav Petkov { 2012ed367e6cSBorislav Petkov u64 mask = 0; 2013ed367e6cSBorislav Petkov 2014ed367e6cSBorislav Petkov if (fields & 0x1) 2015ed367e6cSBorislav Petkov mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID; 2016ed367e6cSBorislav Petkov if (fields & 0x2) 2017ed367e6cSBorislav Petkov mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE; 2018ed367e6cSBorislav Petkov if (fields & 0x4) 2019ed367e6cSBorislav Petkov mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP; 2020ed367e6cSBorislav Petkov return mask; 2021ed367e6cSBorislav Petkov } 2022ed367e6cSBorislav Petkov 2023ed367e6cSBorislav Petkov static struct event_constraint * 2024ed367e6cSBorislav Petkov knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 2025ed367e6cSBorislav Petkov { 2026ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, knl_cha_filter_mask); 2027ed367e6cSBorislav Petkov } 2028ed367e6cSBorislav Petkov 2029ed367e6cSBorislav Petkov static int knl_cha_hw_config(struct intel_uncore_box *box, 2030ed367e6cSBorislav Petkov struct perf_event *event) 2031ed367e6cSBorislav Petkov { 2032ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2033ed367e6cSBorislav Petkov struct extra_reg *er; 2034ed367e6cSBorislav Petkov int idx = 0; 2035ed367e6cSBorislav Petkov 2036ed367e6cSBorislav Petkov for (er = knl_uncore_cha_extra_regs; er->msr; er++) { 2037ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 2038ed367e6cSBorislav Petkov continue; 2039ed367e6cSBorislav Petkov idx |= er->idx; 2040ed367e6cSBorislav Petkov } 2041ed367e6cSBorislav Petkov 2042ed367e6cSBorislav Petkov if (idx) { 2043ed367e6cSBorislav Petkov reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 2044ed367e6cSBorislav Petkov KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx; 2045ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & knl_cha_filter_mask(idx); 2046ec336c87Shchrzani 2047ec336c87Shchrzani reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE; 2048ec336c87Shchrzani reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE; 2049ec336c87Shchrzani reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC; 2050ed367e6cSBorislav Petkov reg1->idx = idx; 2051ed367e6cSBorislav Petkov } 2052ed367e6cSBorislav Petkov return 0; 2053ed367e6cSBorislav Petkov } 2054ed367e6cSBorislav Petkov 2055ed367e6cSBorislav Petkov static void hswep_cbox_enable_event(struct intel_uncore_box *box, 2056ed367e6cSBorislav Petkov struct perf_event *event); 2057ed367e6cSBorislav Petkov 2058ed367e6cSBorislav Petkov static struct intel_uncore_ops knl_uncore_cha_ops = { 2059ed367e6cSBorislav Petkov .init_box = snbep_uncore_msr_init_box, 2060ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, 2061ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, 2062ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, 2063ed367e6cSBorislav Petkov .enable_event = hswep_cbox_enable_event, 2064ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter, 2065ed367e6cSBorislav Petkov .hw_config = knl_cha_hw_config, 2066ed367e6cSBorislav Petkov .get_constraint = knl_cha_get_constraint, 2067ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 2068ed367e6cSBorislav Petkov }; 2069ed367e6cSBorislav Petkov 2070ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_cha = { 2071ed367e6cSBorislav Petkov .name = "cha", 2072ed367e6cSBorislav Petkov .num_counters = 4, 2073ed367e6cSBorislav Petkov .num_boxes = 38, 2074ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2075ed367e6cSBorislav Petkov .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 2076ed367e6cSBorislav Petkov .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 2077ed367e6cSBorislav Petkov .event_mask = KNL_CHA_MSR_PMON_RAW_EVENT_MASK, 2078ed367e6cSBorislav Petkov .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 2079ed367e6cSBorislav Petkov .msr_offset = KNL_CHA_MSR_OFFSET, 2080ed367e6cSBorislav Petkov .num_shared_regs = 1, 2081ed367e6cSBorislav Petkov .constraints = knl_uncore_cha_constraints, 2082ed367e6cSBorislav Petkov .ops = &knl_uncore_cha_ops, 2083ed367e6cSBorislav Petkov .format_group = &knl_uncore_cha_format_group, 2084ed367e6cSBorislav Petkov }; 2085ed367e6cSBorislav Petkov 2086ed367e6cSBorislav Petkov static struct attribute *knl_uncore_pcu_formats_attr[] = { 2087ed367e6cSBorislav Petkov &format_attr_event2.attr, 2088ed367e6cSBorislav Petkov &format_attr_use_occ_ctr.attr, 2089ed367e6cSBorislav Petkov &format_attr_occ_sel.attr, 2090ed367e6cSBorislav Petkov &format_attr_edge.attr, 2091ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 2092ed367e6cSBorislav Petkov &format_attr_inv.attr, 2093ed367e6cSBorislav Petkov &format_attr_thresh6.attr, 2094ed367e6cSBorislav Petkov &format_attr_occ_invert.attr, 2095ed367e6cSBorislav Petkov &format_attr_occ_edge_det.attr, 2096ed367e6cSBorislav Petkov NULL, 2097ed367e6cSBorislav Petkov }; 2098ed367e6cSBorislav Petkov 209945bd07adSArvind Yadav static const struct attribute_group knl_uncore_pcu_format_group = { 2100ed367e6cSBorislav Petkov .name = "format", 2101ed367e6cSBorislav Petkov .attrs = knl_uncore_pcu_formats_attr, 2102ed367e6cSBorislav Petkov }; 2103ed367e6cSBorislav Petkov 2104ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_pcu = { 2105ed367e6cSBorislav Petkov .name = "pcu", 2106ed367e6cSBorislav Petkov .num_counters = 4, 2107ed367e6cSBorislav Petkov .num_boxes = 1, 2108ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2109ed367e6cSBorislav Petkov .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 2110ed367e6cSBorislav Petkov .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 2111ed367e6cSBorislav Petkov .event_mask = KNL_PCU_MSR_PMON_RAW_EVENT_MASK, 2112ed367e6cSBorislav Petkov .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 2113ed367e6cSBorislav Petkov .ops = &snbep_uncore_msr_ops, 2114ed367e6cSBorislav Petkov .format_group = &knl_uncore_pcu_format_group, 2115ed367e6cSBorislav Petkov }; 2116ed367e6cSBorislav Petkov 2117ed367e6cSBorislav Petkov static struct intel_uncore_type *knl_msr_uncores[] = { 2118ed367e6cSBorislav Petkov &knl_uncore_ubox, 2119ed367e6cSBorislav Petkov &knl_uncore_cha, 2120ed367e6cSBorislav Petkov &knl_uncore_pcu, 2121ed367e6cSBorislav Petkov NULL, 2122ed367e6cSBorislav Petkov }; 2123ed367e6cSBorislav Petkov 2124ed367e6cSBorislav Petkov void knl_uncore_cpu_init(void) 2125ed367e6cSBorislav Petkov { 2126ed367e6cSBorislav Petkov uncore_msr_uncores = knl_msr_uncores; 2127ed367e6cSBorislav Petkov } 2128ed367e6cSBorislav Petkov 2129ed367e6cSBorislav Petkov static void knl_uncore_imc_enable_box(struct intel_uncore_box *box) 2130ed367e6cSBorislav Petkov { 2131ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 2132ed367e6cSBorislav Petkov int box_ctl = uncore_pci_box_ctl(box); 2133ed367e6cSBorislav Petkov 2134ed367e6cSBorislav Petkov pci_write_config_dword(pdev, box_ctl, 0); 2135ed367e6cSBorislav Petkov } 2136ed367e6cSBorislav Petkov 2137ed367e6cSBorislav Petkov static void knl_uncore_imc_enable_event(struct intel_uncore_box *box, 2138ed367e6cSBorislav Petkov struct perf_event *event) 2139ed367e6cSBorislav Petkov { 2140ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 2141ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2142ed367e6cSBorislav Petkov 2143ed367e6cSBorislav Petkov if ((event->attr.config & SNBEP_PMON_CTL_EV_SEL_MASK) 2144ed367e6cSBorislav Petkov == UNCORE_FIXED_EVENT) 2145ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, 2146ed367e6cSBorislav Petkov hwc->config | KNL_PMON_FIXED_CTL_EN); 2147ed367e6cSBorislav Petkov else 2148ed367e6cSBorislav Petkov pci_write_config_dword(pdev, hwc->config_base, 2149ed367e6cSBorislav Petkov hwc->config | SNBEP_PMON_CTL_EN); 2150ed367e6cSBorislav Petkov } 2151ed367e6cSBorislav Petkov 2152ed367e6cSBorislav Petkov static struct intel_uncore_ops knl_uncore_imc_ops = { 2153ed367e6cSBorislav Petkov .init_box = snbep_uncore_pci_init_box, 2154ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 2155ed367e6cSBorislav Petkov .enable_box = knl_uncore_imc_enable_box, 2156ed367e6cSBorislav Petkov .read_counter = snbep_uncore_pci_read_counter, 2157ed367e6cSBorislav Petkov .enable_event = knl_uncore_imc_enable_event, 2158ed367e6cSBorislav Petkov .disable_event = snbep_uncore_pci_disable_event, 2159ed367e6cSBorislav Petkov }; 2160ed367e6cSBorislav Petkov 2161ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_imc_uclk = { 2162ed367e6cSBorislav Petkov .name = "imc_uclk", 2163ed367e6cSBorislav Petkov .num_counters = 4, 2164ed367e6cSBorislav Petkov .num_boxes = 2, 2165ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2166ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2167ed367e6cSBorislav Petkov .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW, 2168ed367e6cSBorislav Petkov .event_ctl = KNL_UCLK_MSR_PMON_CTL0, 2169ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2170ed367e6cSBorislav Petkov .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW, 2171ed367e6cSBorislav Petkov .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL, 2172ed367e6cSBorislav Petkov .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL, 2173ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2174ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2175ed367e6cSBorislav Petkov }; 2176ed367e6cSBorislav Petkov 2177ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_imc_dclk = { 2178ed367e6cSBorislav Petkov .name = "imc", 2179ed367e6cSBorislav Petkov .num_counters = 4, 2180ed367e6cSBorislav Petkov .num_boxes = 6, 2181ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2182ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2183ed367e6cSBorislav Petkov .perf_ctr = KNL_MC0_CH0_MSR_PMON_CTR0_LOW, 2184ed367e6cSBorislav Petkov .event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0, 2185ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2186ed367e6cSBorislav Petkov .fixed_ctr = KNL_MC0_CH0_MSR_PMON_FIXED_LOW, 2187ed367e6cSBorislav Petkov .fixed_ctl = KNL_MC0_CH0_MSR_PMON_FIXED_CTL, 2188ed367e6cSBorislav Petkov .box_ctl = KNL_MC0_CH0_MSR_PMON_BOX_CTL, 2189ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2190ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2191ed367e6cSBorislav Petkov }; 2192ed367e6cSBorislav Petkov 2193ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_edc_uclk = { 2194ed367e6cSBorislav Petkov .name = "edc_uclk", 2195ed367e6cSBorislav Petkov .num_counters = 4, 2196ed367e6cSBorislav Petkov .num_boxes = 8, 2197ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2198ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2199ed367e6cSBorislav Petkov .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW, 2200ed367e6cSBorislav Petkov .event_ctl = KNL_UCLK_MSR_PMON_CTL0, 2201ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2202ed367e6cSBorislav Petkov .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW, 2203ed367e6cSBorislav Petkov .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL, 2204ed367e6cSBorislav Petkov .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL, 2205ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2206ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2207ed367e6cSBorislav Petkov }; 2208ed367e6cSBorislav Petkov 2209ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_edc_eclk = { 2210ed367e6cSBorislav Petkov .name = "edc_eclk", 2211ed367e6cSBorislav Petkov .num_counters = 4, 2212ed367e6cSBorislav Petkov .num_boxes = 8, 2213ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2214ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2215ed367e6cSBorislav Petkov .perf_ctr = KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW, 2216ed367e6cSBorislav Petkov .event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0, 2217ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2218ed367e6cSBorislav Petkov .fixed_ctr = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW, 2219ed367e6cSBorislav Petkov .fixed_ctl = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL, 2220ed367e6cSBorislav Petkov .box_ctl = KNL_EDC0_ECLK_MSR_PMON_BOX_CTL, 2221ed367e6cSBorislav Petkov .ops = &knl_uncore_imc_ops, 2222ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2223ed367e6cSBorislav Petkov }; 2224ed367e6cSBorislav Petkov 2225ed367e6cSBorislav Petkov static struct event_constraint knl_uncore_m2pcie_constraints[] = { 2226ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 2227ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2228ed367e6cSBorislav Petkov }; 2229ed367e6cSBorislav Petkov 2230ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_m2pcie = { 2231ed367e6cSBorislav Petkov .name = "m2pcie", 2232ed367e6cSBorislav Petkov .num_counters = 4, 2233ed367e6cSBorislav Petkov .num_boxes = 1, 2234ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2235ed367e6cSBorislav Petkov .constraints = knl_uncore_m2pcie_constraints, 2236ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2237ed367e6cSBorislav Petkov }; 2238ed367e6cSBorislav Petkov 2239ed367e6cSBorislav Petkov static struct attribute *knl_uncore_irp_formats_attr[] = { 2240ed367e6cSBorislav Petkov &format_attr_event.attr, 2241ed367e6cSBorislav Petkov &format_attr_umask.attr, 2242ed367e6cSBorislav Petkov &format_attr_qor.attr, 2243ed367e6cSBorislav Petkov &format_attr_edge.attr, 2244ed367e6cSBorislav Petkov &format_attr_inv.attr, 2245ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 2246ed367e6cSBorislav Petkov NULL, 2247ed367e6cSBorislav Petkov }; 2248ed367e6cSBorislav Petkov 224945bd07adSArvind Yadav static const struct attribute_group knl_uncore_irp_format_group = { 2250ed367e6cSBorislav Petkov .name = "format", 2251ed367e6cSBorislav Petkov .attrs = knl_uncore_irp_formats_attr, 2252ed367e6cSBorislav Petkov }; 2253ed367e6cSBorislav Petkov 2254ed367e6cSBorislav Petkov static struct intel_uncore_type knl_uncore_irp = { 2255ed367e6cSBorislav Petkov .name = "irp", 2256ed367e6cSBorislav Petkov .num_counters = 2, 2257ed367e6cSBorislav Petkov .num_boxes = 1, 2258ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2259ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 2260ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 2261ed367e6cSBorislav Petkov .event_mask = KNL_IRP_PCI_PMON_RAW_EVENT_MASK, 2262ed367e6cSBorislav Petkov .box_ctl = KNL_IRP_PCI_PMON_BOX_CTL, 2263ed367e6cSBorislav Petkov .ops = &snbep_uncore_pci_ops, 2264ed367e6cSBorislav Petkov .format_group = &knl_uncore_irp_format_group, 2265ed367e6cSBorislav Petkov }; 2266ed367e6cSBorislav Petkov 2267ed367e6cSBorislav Petkov enum { 2268ed367e6cSBorislav Petkov KNL_PCI_UNCORE_MC_UCLK, 2269ed367e6cSBorislav Petkov KNL_PCI_UNCORE_MC_DCLK, 2270ed367e6cSBorislav Petkov KNL_PCI_UNCORE_EDC_UCLK, 2271ed367e6cSBorislav Petkov KNL_PCI_UNCORE_EDC_ECLK, 2272ed367e6cSBorislav Petkov KNL_PCI_UNCORE_M2PCIE, 2273ed367e6cSBorislav Petkov KNL_PCI_UNCORE_IRP, 2274ed367e6cSBorislav Petkov }; 2275ed367e6cSBorislav Petkov 2276ed367e6cSBorislav Petkov static struct intel_uncore_type *knl_pci_uncores[] = { 2277ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_MC_UCLK] = &knl_uncore_imc_uclk, 2278ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_MC_DCLK] = &knl_uncore_imc_dclk, 2279ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_EDC_UCLK] = &knl_uncore_edc_uclk, 2280ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_EDC_ECLK] = &knl_uncore_edc_eclk, 2281ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_M2PCIE] = &knl_uncore_m2pcie, 2282ed367e6cSBorislav Petkov [KNL_PCI_UNCORE_IRP] = &knl_uncore_irp, 2283ed367e6cSBorislav Petkov NULL, 2284ed367e6cSBorislav Petkov }; 2285ed367e6cSBorislav Petkov 2286ed367e6cSBorislav Petkov /* 2287ed367e6cSBorislav Petkov * KNL uses a common PCI device ID for multiple instances of an Uncore PMU 2288ed367e6cSBorislav Petkov * device type. prior to KNL, each instance of a PMU device type had a unique 2289ed367e6cSBorislav Petkov * device ID. 2290ed367e6cSBorislav Petkov * 2291ed367e6cSBorislav Petkov * PCI Device ID Uncore PMU Devices 2292ed367e6cSBorislav Petkov * ---------------------------------- 2293ed367e6cSBorislav Petkov * 0x7841 MC0 UClk, MC1 UClk 2294ed367e6cSBorislav Petkov * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2, 2295ed367e6cSBorislav Petkov * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2 2296ed367e6cSBorislav Petkov * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk, 2297ed367e6cSBorislav Petkov * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk 2298ed367e6cSBorislav Petkov * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk, 2299ed367e6cSBorislav Petkov * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk 2300ed367e6cSBorislav Petkov * 0x7817 M2PCIe 2301ed367e6cSBorislav Petkov * 0x7814 IRP 2302ed367e6cSBorislav Petkov */ 2303ed367e6cSBorislav Petkov 2304ed367e6cSBorislav Petkov static const struct pci_device_id knl_uncore_pci_ids[] = { 2305a54fa079SKan Liang { /* MC0 UClk */ 2306ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841), 2307a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 0, KNL_PCI_UNCORE_MC_UCLK, 0), 2308ed367e6cSBorislav Petkov }, 2309a54fa079SKan Liang { /* MC1 UClk */ 2310a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841), 2311a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 0, KNL_PCI_UNCORE_MC_UCLK, 1), 2312a54fa079SKan Liang }, 2313a54fa079SKan Liang { /* MC0 DClk CH 0 */ 2314ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2315a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 2, KNL_PCI_UNCORE_MC_DCLK, 0), 2316ed367e6cSBorislav Petkov }, 2317a54fa079SKan Liang { /* MC0 DClk CH 1 */ 2318a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2319a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 3, KNL_PCI_UNCORE_MC_DCLK, 1), 2320a54fa079SKan Liang }, 2321a54fa079SKan Liang { /* MC0 DClk CH 2 */ 2322a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2323a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 4, KNL_PCI_UNCORE_MC_DCLK, 2), 2324a54fa079SKan Liang }, 2325a54fa079SKan Liang { /* MC1 DClk CH 0 */ 2326a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2327a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 2, KNL_PCI_UNCORE_MC_DCLK, 3), 2328a54fa079SKan Liang }, 2329a54fa079SKan Liang { /* MC1 DClk CH 1 */ 2330a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2331a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 3, KNL_PCI_UNCORE_MC_DCLK, 4), 2332a54fa079SKan Liang }, 2333a54fa079SKan Liang { /* MC1 DClk CH 2 */ 2334a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2335a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 4, KNL_PCI_UNCORE_MC_DCLK, 5), 2336a54fa079SKan Liang }, 2337a54fa079SKan Liang { /* EDC0 UClk */ 2338ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2339a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, KNL_PCI_UNCORE_EDC_UCLK, 0), 2340ed367e6cSBorislav Petkov }, 2341a54fa079SKan Liang { /* EDC1 UClk */ 2342a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2343a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, KNL_PCI_UNCORE_EDC_UCLK, 1), 2344a54fa079SKan Liang }, 2345a54fa079SKan Liang { /* EDC2 UClk */ 2346a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2347a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(17, 0, KNL_PCI_UNCORE_EDC_UCLK, 2), 2348a54fa079SKan Liang }, 2349a54fa079SKan Liang { /* EDC3 UClk */ 2350a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2351a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 0, KNL_PCI_UNCORE_EDC_UCLK, 3), 2352a54fa079SKan Liang }, 2353a54fa079SKan Liang { /* EDC4 UClk */ 2354a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2355a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(19, 0, KNL_PCI_UNCORE_EDC_UCLK, 4), 2356a54fa079SKan Liang }, 2357a54fa079SKan Liang { /* EDC5 UClk */ 2358a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2359a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(20, 0, KNL_PCI_UNCORE_EDC_UCLK, 5), 2360a54fa079SKan Liang }, 2361a54fa079SKan Liang { /* EDC6 UClk */ 2362a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2363a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 0, KNL_PCI_UNCORE_EDC_UCLK, 6), 2364a54fa079SKan Liang }, 2365a54fa079SKan Liang { /* EDC7 UClk */ 2366a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2367a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 0, KNL_PCI_UNCORE_EDC_UCLK, 7), 2368a54fa079SKan Liang }, 2369a54fa079SKan Liang { /* EDC0 EClk */ 2370ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2371a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(24, 2, KNL_PCI_UNCORE_EDC_ECLK, 0), 2372a54fa079SKan Liang }, 2373a54fa079SKan Liang { /* EDC1 EClk */ 2374a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2375a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(25, 2, KNL_PCI_UNCORE_EDC_ECLK, 1), 2376a54fa079SKan Liang }, 2377a54fa079SKan Liang { /* EDC2 EClk */ 2378a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2379a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(26, 2, KNL_PCI_UNCORE_EDC_ECLK, 2), 2380a54fa079SKan Liang }, 2381a54fa079SKan Liang { /* EDC3 EClk */ 2382a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2383a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(27, 2, KNL_PCI_UNCORE_EDC_ECLK, 3), 2384a54fa079SKan Liang }, 2385a54fa079SKan Liang { /* EDC4 EClk */ 2386a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2387a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(28, 2, KNL_PCI_UNCORE_EDC_ECLK, 4), 2388a54fa079SKan Liang }, 2389a54fa079SKan Liang { /* EDC5 EClk */ 2390a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2391a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(29, 2, KNL_PCI_UNCORE_EDC_ECLK, 5), 2392a54fa079SKan Liang }, 2393a54fa079SKan Liang { /* EDC6 EClk */ 2394a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2395a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(30, 2, KNL_PCI_UNCORE_EDC_ECLK, 6), 2396a54fa079SKan Liang }, 2397a54fa079SKan Liang { /* EDC7 EClk */ 2398a54fa079SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2399a54fa079SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(31, 2, KNL_PCI_UNCORE_EDC_ECLK, 7), 2400ed367e6cSBorislav Petkov }, 2401ed367e6cSBorislav Petkov { /* M2PCIe */ 2402ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817), 2403ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0), 2404ed367e6cSBorislav Petkov }, 2405ed367e6cSBorislav Petkov { /* IRP */ 2406ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814), 2407ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0), 2408ed367e6cSBorislav Petkov }, 2409ed367e6cSBorislav Petkov { /* end: all zeroes */ } 2410ed367e6cSBorislav Petkov }; 2411ed367e6cSBorislav Petkov 2412ed367e6cSBorislav Petkov static struct pci_driver knl_uncore_pci_driver = { 2413ed367e6cSBorislav Petkov .name = "knl_uncore", 2414ed367e6cSBorislav Petkov .id_table = knl_uncore_pci_ids, 2415ed367e6cSBorislav Petkov }; 2416ed367e6cSBorislav Petkov 2417ed367e6cSBorislav Petkov int knl_uncore_pci_init(void) 2418ed367e6cSBorislav Petkov { 2419ed367e6cSBorislav Petkov int ret; 2420ed367e6cSBorislav Petkov 2421ed367e6cSBorislav Petkov /* All KNL PCI based PMON units are on the same PCI bus except IRP */ 2422ed367e6cSBorislav Petkov ret = snb_pci2phy_map_init(0x7814); /* IRP */ 2423ed367e6cSBorislav Petkov if (ret) 2424ed367e6cSBorislav Petkov return ret; 2425ed367e6cSBorislav Petkov ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */ 2426ed367e6cSBorislav Petkov if (ret) 2427ed367e6cSBorislav Petkov return ret; 2428ed367e6cSBorislav Petkov uncore_pci_uncores = knl_pci_uncores; 2429ed367e6cSBorislav Petkov uncore_pci_driver = &knl_uncore_pci_driver; 2430ed367e6cSBorislav Petkov return 0; 2431ed367e6cSBorislav Petkov } 2432ed367e6cSBorislav Petkov 2433ed367e6cSBorislav Petkov /* end of KNL uncore support */ 2434ed367e6cSBorislav Petkov 2435ed367e6cSBorislav Petkov /* Haswell-EP uncore support */ 2436ed367e6cSBorislav Petkov static struct attribute *hswep_uncore_ubox_formats_attr[] = { 2437ed367e6cSBorislav Petkov &format_attr_event.attr, 2438ed367e6cSBorislav Petkov &format_attr_umask.attr, 2439ed367e6cSBorislav Petkov &format_attr_edge.attr, 2440ed367e6cSBorislav Petkov &format_attr_inv.attr, 2441ed367e6cSBorislav Petkov &format_attr_thresh5.attr, 2442ed367e6cSBorislav Petkov &format_attr_filter_tid2.attr, 2443ed367e6cSBorislav Petkov &format_attr_filter_cid.attr, 2444ed367e6cSBorislav Petkov NULL, 2445ed367e6cSBorislav Petkov }; 2446ed367e6cSBorislav Petkov 244745bd07adSArvind Yadav static const struct attribute_group hswep_uncore_ubox_format_group = { 2448ed367e6cSBorislav Petkov .name = "format", 2449ed367e6cSBorislav Petkov .attrs = hswep_uncore_ubox_formats_attr, 2450ed367e6cSBorislav Petkov }; 2451ed367e6cSBorislav Petkov 2452ed367e6cSBorislav Petkov static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2453ed367e6cSBorislav Petkov { 2454ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2455ed367e6cSBorislav Petkov reg1->reg = HSWEP_U_MSR_PMON_FILTER; 2456ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK; 2457ed367e6cSBorislav Petkov reg1->idx = 0; 2458ed367e6cSBorislav Petkov return 0; 2459ed367e6cSBorislav Petkov } 2460ed367e6cSBorislav Petkov 2461ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_ubox_ops = { 2462ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2463ed367e6cSBorislav Petkov .hw_config = hswep_ubox_hw_config, 2464ed367e6cSBorislav Petkov .get_constraint = uncore_get_constraint, 2465ed367e6cSBorislav Petkov .put_constraint = uncore_put_constraint, 2466ed367e6cSBorislav Petkov }; 2467ed367e6cSBorislav Petkov 2468ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_ubox = { 2469ed367e6cSBorislav Petkov .name = "ubox", 2470ed367e6cSBorislav Petkov .num_counters = 2, 2471ed367e6cSBorislav Petkov .num_boxes = 1, 2472ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 2473ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2474ed367e6cSBorislav Petkov .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 2475ed367e6cSBorislav Petkov .event_ctl = HSWEP_U_MSR_PMON_CTL0, 2476ed367e6cSBorislav Petkov .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 2477ed367e6cSBorislav Petkov .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 2478ed367e6cSBorislav Petkov .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 2479ed367e6cSBorislav Petkov .num_shared_regs = 1, 2480ed367e6cSBorislav Petkov .ops = &hswep_uncore_ubox_ops, 2481ed367e6cSBorislav Petkov .format_group = &hswep_uncore_ubox_format_group, 2482ed367e6cSBorislav Petkov }; 2483ed367e6cSBorislav Petkov 2484ed367e6cSBorislav Petkov static struct attribute *hswep_uncore_cbox_formats_attr[] = { 2485ed367e6cSBorislav Petkov &format_attr_event.attr, 2486ed367e6cSBorislav Petkov &format_attr_umask.attr, 2487ed367e6cSBorislav Petkov &format_attr_edge.attr, 2488ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 2489ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 2490ed367e6cSBorislav Petkov &format_attr_filter_tid3.attr, 2491ed367e6cSBorislav Petkov &format_attr_filter_link2.attr, 2492ed367e6cSBorislav Petkov &format_attr_filter_state3.attr, 2493ed367e6cSBorislav Petkov &format_attr_filter_nid2.attr, 2494ed367e6cSBorislav Petkov &format_attr_filter_opc2.attr, 2495ed367e6cSBorislav Petkov &format_attr_filter_nc.attr, 2496ed367e6cSBorislav Petkov &format_attr_filter_c6.attr, 2497ed367e6cSBorislav Petkov &format_attr_filter_isoc.attr, 2498ed367e6cSBorislav Petkov NULL, 2499ed367e6cSBorislav Petkov }; 2500ed367e6cSBorislav Petkov 250145bd07adSArvind Yadav static const struct attribute_group hswep_uncore_cbox_format_group = { 2502ed367e6cSBorislav Petkov .name = "format", 2503ed367e6cSBorislav Petkov .attrs = hswep_uncore_cbox_formats_attr, 2504ed367e6cSBorislav Petkov }; 2505ed367e6cSBorislav Petkov 2506ed367e6cSBorislav Petkov static struct event_constraint hswep_uncore_cbox_constraints[] = { 2507ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x1), 2508ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x1), 2509ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 2510ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 2511ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 2512ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), 2513ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3e, 0x1), 2514ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2515ed367e6cSBorislav Petkov }; 2516ed367e6cSBorislav Petkov 2517ed367e6cSBorislav Petkov static struct extra_reg hswep_uncore_cbox_extra_regs[] = { 2518ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 2519ed367e6cSBorislav Petkov SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 2520ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 2521ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 2522ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 2523ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 2524ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4), 2525ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4), 2526ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8), 2527ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8), 2528ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8), 2529ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8), 2530ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8), 2531ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8), 2532ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12), 2533ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10), 2534ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18), 2535ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8), 2536ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8), 2537ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8), 2538ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18), 2539ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8), 2540ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10), 2541ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10), 2542ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10), 2543ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10), 2544ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10), 2545ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10), 2546ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18), 2547ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8), 2548ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8), 2549ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18), 2550ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8), 2551ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10), 2552ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10), 2553ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10), 2554ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10), 2555ed367e6cSBorislav Petkov SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8), 2556ed367e6cSBorislav Petkov EVENT_EXTRA_END 2557ed367e6cSBorislav Petkov }; 2558ed367e6cSBorislav Petkov 2559ed367e6cSBorislav Petkov static u64 hswep_cbox_filter_mask(int fields) 2560ed367e6cSBorislav Petkov { 2561ed367e6cSBorislav Petkov u64 mask = 0; 2562ed367e6cSBorislav Petkov if (fields & 0x1) 2563ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID; 2564ed367e6cSBorislav Petkov if (fields & 0x2) 2565ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK; 2566ed367e6cSBorislav Petkov if (fields & 0x4) 2567ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE; 2568ed367e6cSBorislav Petkov if (fields & 0x8) 2569ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID; 2570ed367e6cSBorislav Petkov if (fields & 0x10) { 2571ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC; 2572ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC; 2573ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6; 2574ed367e6cSBorislav Petkov mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC; 2575ed367e6cSBorislav Petkov } 2576ed367e6cSBorislav Petkov return mask; 2577ed367e6cSBorislav Petkov } 2578ed367e6cSBorislav Petkov 2579ed367e6cSBorislav Petkov static struct event_constraint * 2580ed367e6cSBorislav Petkov hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 2581ed367e6cSBorislav Petkov { 2582ed367e6cSBorislav Petkov return __snbep_cbox_get_constraint(box, event, hswep_cbox_filter_mask); 2583ed367e6cSBorislav Petkov } 2584ed367e6cSBorislav Petkov 2585ed367e6cSBorislav Petkov static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2586ed367e6cSBorislav Petkov { 2587ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2588ed367e6cSBorislav Petkov struct extra_reg *er; 2589ed367e6cSBorislav Petkov int idx = 0; 2590ed367e6cSBorislav Petkov 2591ed367e6cSBorislav Petkov for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) { 2592ed367e6cSBorislav Petkov if (er->event != (event->hw.config & er->config_mask)) 2593ed367e6cSBorislav Petkov continue; 2594ed367e6cSBorislav Petkov idx |= er->idx; 2595ed367e6cSBorislav Petkov } 2596ed367e6cSBorislav Petkov 2597ed367e6cSBorislav Petkov if (idx) { 2598ed367e6cSBorislav Petkov reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 2599ed367e6cSBorislav Petkov HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 2600ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx); 2601ed367e6cSBorislav Petkov reg1->idx = idx; 2602ed367e6cSBorislav Petkov } 2603ed367e6cSBorislav Petkov return 0; 2604ed367e6cSBorislav Petkov } 2605ed367e6cSBorislav Petkov 2606ed367e6cSBorislav Petkov static void hswep_cbox_enable_event(struct intel_uncore_box *box, 2607ed367e6cSBorislav Petkov struct perf_event *event) 2608ed367e6cSBorislav Petkov { 2609ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2610ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 2611ed367e6cSBorislav Petkov 2612ed367e6cSBorislav Petkov if (reg1->idx != EXTRA_REG_NONE) { 2613ed367e6cSBorislav Petkov u64 filter = uncore_shared_reg_config(box, 0); 2614ed367e6cSBorislav Petkov wrmsrl(reg1->reg, filter & 0xffffffff); 2615ed367e6cSBorislav Petkov wrmsrl(reg1->reg + 1, filter >> 32); 2616ed367e6cSBorislav Petkov } 2617ed367e6cSBorislav Petkov 2618ed367e6cSBorislav Petkov wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 2619ed367e6cSBorislav Petkov } 2620ed367e6cSBorislav Petkov 2621ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_cbox_ops = { 2622ed367e6cSBorislav Petkov .init_box = snbep_uncore_msr_init_box, 2623ed367e6cSBorislav Petkov .disable_box = snbep_uncore_msr_disable_box, 2624ed367e6cSBorislav Petkov .enable_box = snbep_uncore_msr_enable_box, 2625ed367e6cSBorislav Petkov .disable_event = snbep_uncore_msr_disable_event, 2626ed367e6cSBorislav Petkov .enable_event = hswep_cbox_enable_event, 2627ed367e6cSBorislav Petkov .read_counter = uncore_msr_read_counter, 2628ed367e6cSBorislav Petkov .hw_config = hswep_cbox_hw_config, 2629ed367e6cSBorislav Petkov .get_constraint = hswep_cbox_get_constraint, 2630ed367e6cSBorislav Petkov .put_constraint = snbep_cbox_put_constraint, 2631ed367e6cSBorislav Petkov }; 2632ed367e6cSBorislav Petkov 2633ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_cbox = { 2634ed367e6cSBorislav Petkov .name = "cbox", 2635ed367e6cSBorislav Petkov .num_counters = 4, 2636ed367e6cSBorislav Petkov .num_boxes = 18, 2637ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2638ed367e6cSBorislav Petkov .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 2639ed367e6cSBorislav Petkov .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 2640ed367e6cSBorislav Petkov .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 2641ed367e6cSBorislav Petkov .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 2642ed367e6cSBorislav Petkov .msr_offset = HSWEP_CBO_MSR_OFFSET, 2643ed367e6cSBorislav Petkov .num_shared_regs = 1, 2644ed367e6cSBorislav Petkov .constraints = hswep_uncore_cbox_constraints, 2645ed367e6cSBorislav Petkov .ops = &hswep_uncore_cbox_ops, 2646ed367e6cSBorislav Petkov .format_group = &hswep_uncore_cbox_format_group, 2647ed367e6cSBorislav Petkov }; 2648ed367e6cSBorislav Petkov 2649ed367e6cSBorislav Petkov /* 2650ed367e6cSBorislav Petkov * Write SBOX Initialization register bit by bit to avoid spurious #GPs 2651ed367e6cSBorislav Petkov */ 2652ed367e6cSBorislav Petkov static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box) 2653ed367e6cSBorislav Petkov { 2654ed367e6cSBorislav Petkov unsigned msr = uncore_msr_box_ctl(box); 2655ed367e6cSBorislav Petkov 2656ed367e6cSBorislav Petkov if (msr) { 2657ed367e6cSBorislav Petkov u64 init = SNBEP_PMON_BOX_CTL_INT; 2658ed367e6cSBorislav Petkov u64 flags = 0; 2659ed367e6cSBorislav Petkov int i; 2660ed367e6cSBorislav Petkov 2661ed367e6cSBorislav Petkov for_each_set_bit(i, (unsigned long *)&init, 64) { 2662ed367e6cSBorislav Petkov flags |= (1ULL << i); 2663ed367e6cSBorislav Petkov wrmsrl(msr, flags); 2664ed367e6cSBorislav Petkov } 2665ed367e6cSBorislav Petkov } 2666ed367e6cSBorislav Petkov } 2667ed367e6cSBorislav Petkov 2668ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = { 2669ed367e6cSBorislav Petkov __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2670ed367e6cSBorislav Petkov .init_box = hswep_uncore_sbox_msr_init_box 2671ed367e6cSBorislav Petkov }; 2672ed367e6cSBorislav Petkov 2673ed367e6cSBorislav Petkov static struct attribute *hswep_uncore_sbox_formats_attr[] = { 2674ed367e6cSBorislav Petkov &format_attr_event.attr, 2675ed367e6cSBorislav Petkov &format_attr_umask.attr, 2676ed367e6cSBorislav Petkov &format_attr_edge.attr, 2677ed367e6cSBorislav Petkov &format_attr_tid_en.attr, 2678ed367e6cSBorislav Petkov &format_attr_inv.attr, 2679ed367e6cSBorislav Petkov &format_attr_thresh8.attr, 2680ed367e6cSBorislav Petkov NULL, 2681ed367e6cSBorislav Petkov }; 2682ed367e6cSBorislav Petkov 268345bd07adSArvind Yadav static const struct attribute_group hswep_uncore_sbox_format_group = { 2684ed367e6cSBorislav Petkov .name = "format", 2685ed367e6cSBorislav Petkov .attrs = hswep_uncore_sbox_formats_attr, 2686ed367e6cSBorislav Petkov }; 2687ed367e6cSBorislav Petkov 2688ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_sbox = { 2689ed367e6cSBorislav Petkov .name = "sbox", 2690ed367e6cSBorislav Petkov .num_counters = 4, 2691ed367e6cSBorislav Petkov .num_boxes = 4, 2692ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 2693ed367e6cSBorislav Petkov .event_ctl = HSWEP_S0_MSR_PMON_CTL0, 2694ed367e6cSBorislav Petkov .perf_ctr = HSWEP_S0_MSR_PMON_CTR0, 2695ed367e6cSBorislav Petkov .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 2696ed367e6cSBorislav Petkov .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL, 2697ed367e6cSBorislav Petkov .msr_offset = HSWEP_SBOX_MSR_OFFSET, 2698ed367e6cSBorislav Petkov .ops = &hswep_uncore_sbox_msr_ops, 2699ed367e6cSBorislav Petkov .format_group = &hswep_uncore_sbox_format_group, 2700ed367e6cSBorislav Petkov }; 2701ed367e6cSBorislav Petkov 2702ed367e6cSBorislav Petkov static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2703ed367e6cSBorislav Petkov { 2704ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2705ed367e6cSBorislav Petkov struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 2706ed367e6cSBorislav Petkov int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 2707ed367e6cSBorislav Petkov 2708ed367e6cSBorislav Petkov if (ev_sel >= 0xb && ev_sel <= 0xe) { 2709ed367e6cSBorislav Petkov reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER; 2710ed367e6cSBorislav Petkov reg1->idx = ev_sel - 0xb; 2711ed367e6cSBorislav Petkov reg1->config = event->attr.config1 & (0xff << reg1->idx); 2712ed367e6cSBorislav Petkov } 2713ed367e6cSBorislav Petkov return 0; 2714ed367e6cSBorislav Petkov } 2715ed367e6cSBorislav Petkov 2716ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_pcu_ops = { 2717ed367e6cSBorislav Petkov SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2718ed367e6cSBorislav Petkov .hw_config = hswep_pcu_hw_config, 2719ed367e6cSBorislav Petkov .get_constraint = snbep_pcu_get_constraint, 2720ed367e6cSBorislav Petkov .put_constraint = snbep_pcu_put_constraint, 2721ed367e6cSBorislav Petkov }; 2722ed367e6cSBorislav Petkov 2723ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_pcu = { 2724ed367e6cSBorislav Petkov .name = "pcu", 2725ed367e6cSBorislav Petkov .num_counters = 4, 2726ed367e6cSBorislav Petkov .num_boxes = 1, 2727ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2728ed367e6cSBorislav Petkov .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 2729ed367e6cSBorislav Petkov .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 2730ed367e6cSBorislav Petkov .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 2731ed367e6cSBorislav Petkov .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 2732ed367e6cSBorislav Petkov .num_shared_regs = 1, 2733ed367e6cSBorislav Petkov .ops = &hswep_uncore_pcu_ops, 2734ed367e6cSBorislav Petkov .format_group = &snbep_uncore_pcu_format_group, 2735ed367e6cSBorislav Petkov }; 2736ed367e6cSBorislav Petkov 2737ed367e6cSBorislav Petkov static struct intel_uncore_type *hswep_msr_uncores[] = { 2738ed367e6cSBorislav Petkov &hswep_uncore_ubox, 2739ed367e6cSBorislav Petkov &hswep_uncore_cbox, 2740ed367e6cSBorislav Petkov &hswep_uncore_sbox, 2741ed367e6cSBorislav Petkov &hswep_uncore_pcu, 2742ed367e6cSBorislav Petkov NULL, 2743ed367e6cSBorislav Petkov }; 2744ed367e6cSBorislav Petkov 2745ed367e6cSBorislav Petkov void hswep_uncore_cpu_init(void) 2746ed367e6cSBorislav Petkov { 27476d6daa20SPrarit Bhargava int pkg = boot_cpu_data.logical_proc_id; 2748cf6d445fSThomas Gleixner 2749ed367e6cSBorislav Petkov if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 2750ed367e6cSBorislav Petkov hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 2751ed367e6cSBorislav Petkov 2752ed367e6cSBorislav Petkov /* Detect 6-8 core systems with only two SBOXes */ 2753cf6d445fSThomas Gleixner if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) { 2754ed367e6cSBorislav Petkov u32 capid4; 2755ed367e6cSBorislav Petkov 2756cf6d445fSThomas Gleixner pci_read_config_dword(uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3], 2757ed367e6cSBorislav Petkov 0x94, &capid4); 2758ed367e6cSBorislav Petkov if (((capid4 >> 6) & 0x3) == 0) 2759ed367e6cSBorislav Petkov hswep_uncore_sbox.num_boxes = 2; 2760ed367e6cSBorislav Petkov } 2761ed367e6cSBorislav Petkov 2762ed367e6cSBorislav Petkov uncore_msr_uncores = hswep_msr_uncores; 2763ed367e6cSBorislav Petkov } 2764ed367e6cSBorislav Petkov 2765ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_ha = { 2766ed367e6cSBorislav Petkov .name = "ha", 276710e9e7bdSKan Liang .num_counters = 4, 2768ed367e6cSBorislav Petkov .num_boxes = 2, 2769ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2770ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2771ed367e6cSBorislav Petkov }; 2772ed367e6cSBorislav Petkov 2773ed367e6cSBorislav Petkov static struct uncore_event_desc hswep_uncore_imc_events[] = { 2774ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"), 2775ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), 2776ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 2777ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 2778ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), 2779ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 2780ed367e6cSBorislav Petkov INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 2781ed367e6cSBorislav Petkov { /* end: all zeroes */ }, 2782ed367e6cSBorislav Petkov }; 2783ed367e6cSBorislav Petkov 2784ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_imc = { 2785ed367e6cSBorislav Petkov .name = "imc", 278610e9e7bdSKan Liang .num_counters = 4, 2787ed367e6cSBorislav Petkov .num_boxes = 8, 2788ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2789ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 2790ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 2791ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 2792ed367e6cSBorislav Petkov .event_descs = hswep_uncore_imc_events, 2793ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2794ed367e6cSBorislav Petkov }; 2795ed367e6cSBorislav Petkov 2796ed367e6cSBorislav Petkov static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8}; 2797ed367e6cSBorislav Petkov 2798ed367e6cSBorislav Petkov static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) 2799ed367e6cSBorislav Petkov { 2800ed367e6cSBorislav Petkov struct pci_dev *pdev = box->pci_dev; 2801ed367e6cSBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2802ed367e6cSBorislav Petkov u64 count = 0; 2803ed367e6cSBorislav Petkov 2804ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count); 2805ed367e6cSBorislav Petkov pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1); 2806ed367e6cSBorislav Petkov 2807ed367e6cSBorislav Petkov return count; 2808ed367e6cSBorislav Petkov } 2809ed367e6cSBorislav Petkov 2810ed367e6cSBorislav Petkov static struct intel_uncore_ops hswep_uncore_irp_ops = { 2811ed367e6cSBorislav Petkov .init_box = snbep_uncore_pci_init_box, 2812ed367e6cSBorislav Petkov .disable_box = snbep_uncore_pci_disable_box, 2813ed367e6cSBorislav Petkov .enable_box = snbep_uncore_pci_enable_box, 2814ed367e6cSBorislav Petkov .disable_event = ivbep_uncore_irp_disable_event, 2815ed367e6cSBorislav Petkov .enable_event = ivbep_uncore_irp_enable_event, 2816ed367e6cSBorislav Petkov .read_counter = hswep_uncore_irp_read_counter, 2817ed367e6cSBorislav Petkov }; 2818ed367e6cSBorislav Petkov 2819ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_irp = { 2820ed367e6cSBorislav Petkov .name = "irp", 2821ed367e6cSBorislav Petkov .num_counters = 4, 2822ed367e6cSBorislav Petkov .num_boxes = 1, 2823ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2824ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2825ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 2826ed367e6cSBorislav Petkov .ops = &hswep_uncore_irp_ops, 2827ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 2828ed367e6cSBorislav Petkov }; 2829ed367e6cSBorislav Petkov 2830ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_qpi = { 2831ed367e6cSBorislav Petkov .name = "qpi", 283210e9e7bdSKan Liang .num_counters = 4, 2833ed367e6cSBorislav Petkov .num_boxes = 3, 2834ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2835ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 2836ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 2837ed367e6cSBorislav Petkov .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 2838ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 2839ed367e6cSBorislav Petkov .num_shared_regs = 1, 2840ed367e6cSBorislav Petkov .ops = &snbep_uncore_qpi_ops, 2841ed367e6cSBorislav Petkov .format_group = &snbep_uncore_qpi_format_group, 2842ed367e6cSBorislav Petkov }; 2843ed367e6cSBorislav Petkov 2844ed367e6cSBorislav Petkov static struct event_constraint hswep_uncore_r2pcie_constraints[] = { 2845ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 2846ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 2847ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 2848ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x1), 2849ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x24, 0x1), 2850ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x1), 2851ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 2852ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x27, 0x1), 2853ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 2854ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 2855ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2a, 0x1), 2856ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), 2857ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 2858ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 2859ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 2860ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 2861ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 2862ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x35, 0x3), 2863ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2864ed367e6cSBorislav Petkov }; 2865ed367e6cSBorislav Petkov 2866ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_r2pcie = { 2867ed367e6cSBorislav Petkov .name = "r2pcie", 2868ed367e6cSBorislav Petkov .num_counters = 4, 2869ed367e6cSBorislav Petkov .num_boxes = 1, 2870ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 2871ed367e6cSBorislav Petkov .constraints = hswep_uncore_r2pcie_constraints, 2872ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2873ed367e6cSBorislav Petkov }; 2874ed367e6cSBorislav Petkov 2875ed367e6cSBorislav Petkov static struct event_constraint hswep_uncore_r3qpi_constraints[] = { 2876ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x3), 2877ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x07, 0x7), 2878ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x08, 0x7), 2879ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x7), 2880ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), 2881ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), 2882ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 2883ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 2884ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 2885ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 2886ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 2887ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x15, 0x3), 2888ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), 2889ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 2890ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 2891ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 2892ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 2893ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 2894ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 2895ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 2896ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 2897ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 2898ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 2899ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 2900ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 2901ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 2902ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 2903ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 2904ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 2905ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 2906ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 2907ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 2908ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 2909ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 2910ed367e6cSBorislav Petkov }; 2911ed367e6cSBorislav Petkov 2912ed367e6cSBorislav Petkov static struct intel_uncore_type hswep_uncore_r3qpi = { 2913ed367e6cSBorislav Petkov .name = "r3qpi", 291410e9e7bdSKan Liang .num_counters = 3, 2915ed367e6cSBorislav Petkov .num_boxes = 3, 2916ed367e6cSBorislav Petkov .perf_ctr_bits = 44, 2917ed367e6cSBorislav Petkov .constraints = hswep_uncore_r3qpi_constraints, 2918ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 2919ed367e6cSBorislav Petkov }; 2920ed367e6cSBorislav Petkov 2921ed367e6cSBorislav Petkov enum { 2922ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_HA, 2923ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_IMC, 2924ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_IRP, 2925ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_QPI, 2926ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_R2PCIE, 2927ed367e6cSBorislav Petkov HSWEP_PCI_UNCORE_R3QPI, 2928ed367e6cSBorislav Petkov }; 2929ed367e6cSBorislav Petkov 2930ed367e6cSBorislav Petkov static struct intel_uncore_type *hswep_pci_uncores[] = { 2931ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_HA] = &hswep_uncore_ha, 2932ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_IMC] = &hswep_uncore_imc, 2933ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_IRP] = &hswep_uncore_irp, 2934ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_QPI] = &hswep_uncore_qpi, 2935ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_R2PCIE] = &hswep_uncore_r2pcie, 2936ed367e6cSBorislav Petkov [HSWEP_PCI_UNCORE_R3QPI] = &hswep_uncore_r3qpi, 2937ed367e6cSBorislav Petkov NULL, 2938ed367e6cSBorislav Petkov }; 2939ed367e6cSBorislav Petkov 2940ed367e6cSBorislav Petkov static const struct pci_device_id hswep_uncore_pci_ids[] = { 2941ed367e6cSBorislav Petkov { /* Home Agent 0 */ 2942ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30), 2943ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0), 2944ed367e6cSBorislav Petkov }, 2945ed367e6cSBorislav Petkov { /* Home Agent 1 */ 2946ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38), 2947ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 1), 2948ed367e6cSBorislav Petkov }, 2949ed367e6cSBorislav Petkov { /* MC0 Channel 0 */ 2950ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0), 2951ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0), 2952ed367e6cSBorislav Petkov }, 2953ed367e6cSBorislav Petkov { /* MC0 Channel 1 */ 2954ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1), 2955ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1), 2956ed367e6cSBorislav Petkov }, 2957ed367e6cSBorislav Petkov { /* MC0 Channel 2 */ 2958ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4), 2959ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2), 2960ed367e6cSBorislav Petkov }, 2961ed367e6cSBorislav Petkov { /* MC0 Channel 3 */ 2962ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5), 2963ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3), 2964ed367e6cSBorislav Petkov }, 2965ed367e6cSBorislav Petkov { /* MC1 Channel 0 */ 2966ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0), 2967ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4), 2968ed367e6cSBorislav Petkov }, 2969ed367e6cSBorislav Petkov { /* MC1 Channel 1 */ 2970ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1), 2971ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5), 2972ed367e6cSBorislav Petkov }, 2973ed367e6cSBorislav Petkov { /* MC1 Channel 2 */ 2974ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4), 2975ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6), 2976ed367e6cSBorislav Petkov }, 2977ed367e6cSBorislav Petkov { /* MC1 Channel 3 */ 2978ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5), 2979ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7), 2980ed367e6cSBorislav Petkov }, 2981ed367e6cSBorislav Petkov { /* IRP */ 2982ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39), 2983ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0), 2984ed367e6cSBorislav Petkov }, 2985ed367e6cSBorislav Petkov { /* QPI0 Port 0 */ 2986ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32), 2987ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0), 2988ed367e6cSBorislav Petkov }, 2989ed367e6cSBorislav Petkov { /* QPI0 Port 1 */ 2990ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33), 2991ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 1), 2992ed367e6cSBorislav Petkov }, 2993ed367e6cSBorislav Petkov { /* QPI1 Port 2 */ 2994ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a), 2995ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 2), 2996ed367e6cSBorislav Petkov }, 2997ed367e6cSBorislav Petkov { /* R2PCIe */ 2998ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34), 2999ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0), 3000ed367e6cSBorislav Petkov }, 3001ed367e6cSBorislav Petkov { /* R3QPI0 Link 0 */ 3002ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36), 3003ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0), 3004ed367e6cSBorislav Petkov }, 3005ed367e6cSBorislav Petkov { /* R3QPI0 Link 1 */ 3006ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37), 3007ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 1), 3008ed367e6cSBorislav Petkov }, 3009ed367e6cSBorislav Petkov { /* R3QPI1 Link 2 */ 3010ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e), 3011ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 2), 3012ed367e6cSBorislav Petkov }, 3013ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 3014ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86), 3015ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3016ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT0_FILTER), 3017ed367e6cSBorislav Petkov }, 3018ed367e6cSBorislav Petkov { /* QPI Port 1 filter */ 3019ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96), 3020ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3021ed367e6cSBorislav Petkov SNBEP_PCI_QPI_PORT1_FILTER), 3022ed367e6cSBorislav Petkov }, 3023ed367e6cSBorislav Petkov { /* PCU.3 (for Capability registers) */ 3024ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fc0), 3025ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3026ed367e6cSBorislav Petkov HSWEP_PCI_PCU_3), 3027ed367e6cSBorislav Petkov }, 3028ed367e6cSBorislav Petkov { /* end: all zeroes */ } 3029ed367e6cSBorislav Petkov }; 3030ed367e6cSBorislav Petkov 3031ed367e6cSBorislav Petkov static struct pci_driver hswep_uncore_pci_driver = { 3032ed367e6cSBorislav Petkov .name = "hswep_uncore", 3033ed367e6cSBorislav Petkov .id_table = hswep_uncore_pci_ids, 3034ed367e6cSBorislav Petkov }; 3035ed367e6cSBorislav Petkov 3036ed367e6cSBorislav Petkov int hswep_uncore_pci_init(void) 3037ed367e6cSBorislav Petkov { 303868ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x2f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 3039ed367e6cSBorislav Petkov if (ret) 3040ed367e6cSBorislav Petkov return ret; 3041ed367e6cSBorislav Petkov uncore_pci_uncores = hswep_pci_uncores; 3042ed367e6cSBorislav Petkov uncore_pci_driver = &hswep_uncore_pci_driver; 3043ed367e6cSBorislav Petkov return 0; 3044ed367e6cSBorislav Petkov } 3045ed367e6cSBorislav Petkov /* end of Haswell-EP uncore support */ 3046ed367e6cSBorislav Petkov 3047ed367e6cSBorislav Petkov /* BDX uncore support */ 3048ed367e6cSBorislav Petkov 3049ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_ubox = { 3050ed367e6cSBorislav Petkov .name = "ubox", 3051ed367e6cSBorislav Petkov .num_counters = 2, 3052ed367e6cSBorislav Petkov .num_boxes = 1, 3053ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3054ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 3055ed367e6cSBorislav Petkov .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 3056ed367e6cSBorislav Petkov .event_ctl = HSWEP_U_MSR_PMON_CTL0, 3057ed367e6cSBorislav Petkov .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 3058ed367e6cSBorislav Petkov .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 3059ed367e6cSBorislav Petkov .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 3060ed367e6cSBorislav Petkov .num_shared_regs = 1, 3061ed367e6cSBorislav Petkov .ops = &ivbep_uncore_msr_ops, 3062ed367e6cSBorislav Petkov .format_group = &ivbep_uncore_ubox_format_group, 3063ed367e6cSBorislav Petkov }; 3064ed367e6cSBorislav Petkov 3065ed367e6cSBorislav Petkov static struct event_constraint bdx_uncore_cbox_constraints[] = { 3066ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x3), 3067ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 3068ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 3069ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x3e, 0x1), 3070ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 3071ed367e6cSBorislav Petkov }; 3072ed367e6cSBorislav Petkov 3073ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_cbox = { 3074ed367e6cSBorislav Petkov .name = "cbox", 3075ed367e6cSBorislav Petkov .num_counters = 4, 3076ed367e6cSBorislav Petkov .num_boxes = 24, 3077ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3078ed367e6cSBorislav Petkov .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 3079ed367e6cSBorislav Petkov .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 3080ed367e6cSBorislav Petkov .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 3081ed367e6cSBorislav Petkov .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 3082ed367e6cSBorislav Petkov .msr_offset = HSWEP_CBO_MSR_OFFSET, 3083ed367e6cSBorislav Petkov .num_shared_regs = 1, 3084ed367e6cSBorislav Petkov .constraints = bdx_uncore_cbox_constraints, 3085ed367e6cSBorislav Petkov .ops = &hswep_uncore_cbox_ops, 3086ed367e6cSBorislav Petkov .format_group = &hswep_uncore_cbox_format_group, 3087ed367e6cSBorislav Petkov }; 3088ed367e6cSBorislav Petkov 3089d7717587SStephane Eranian static struct intel_uncore_type bdx_uncore_sbox = { 3090d7717587SStephane Eranian .name = "sbox", 3091d7717587SStephane Eranian .num_counters = 4, 3092d7717587SStephane Eranian .num_boxes = 4, 3093d7717587SStephane Eranian .perf_ctr_bits = 48, 3094d7717587SStephane Eranian .event_ctl = HSWEP_S0_MSR_PMON_CTL0, 3095d7717587SStephane Eranian .perf_ctr = HSWEP_S0_MSR_PMON_CTR0, 3096d7717587SStephane Eranian .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 3097d7717587SStephane Eranian .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL, 3098d7717587SStephane Eranian .msr_offset = HSWEP_SBOX_MSR_OFFSET, 3099d7717587SStephane Eranian .ops = &hswep_uncore_sbox_msr_ops, 3100d7717587SStephane Eranian .format_group = &hswep_uncore_sbox_format_group, 3101d7717587SStephane Eranian }; 3102d7717587SStephane Eranian 3103d7717587SStephane Eranian #define BDX_MSR_UNCORE_SBOX 3 3104d7717587SStephane Eranian 3105ed367e6cSBorislav Petkov static struct intel_uncore_type *bdx_msr_uncores[] = { 3106ed367e6cSBorislav Petkov &bdx_uncore_ubox, 3107ed367e6cSBorislav Petkov &bdx_uncore_cbox, 3108ed367e6cSBorislav Petkov &hswep_uncore_pcu, 3109d7717587SStephane Eranian &bdx_uncore_sbox, 3110ed367e6cSBorislav Petkov NULL, 3111ed367e6cSBorislav Petkov }; 3112ed367e6cSBorislav Petkov 3113bb9fbe1bSKan Liang /* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */ 3114bb9fbe1bSKan Liang static struct event_constraint bdx_uncore_pcu_constraints[] = { 3115bb9fbe1bSKan Liang EVENT_CONSTRAINT(0x80, 0xe, 0x80), 3116bb9fbe1bSKan Liang EVENT_CONSTRAINT_END 3117bb9fbe1bSKan Liang }; 3118bb9fbe1bSKan Liang 3119ed367e6cSBorislav Petkov void bdx_uncore_cpu_init(void) 3120ed367e6cSBorislav Petkov { 31216265adb9SMasayoshi Mizuma int pkg = topology_phys_to_logical_pkg(boot_cpu_data.phys_proc_id); 312215a3e845SOskar Senft 3123ed367e6cSBorislav Petkov if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 3124ed367e6cSBorislav Petkov bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 3125ed367e6cSBorislav Petkov uncore_msr_uncores = bdx_msr_uncores; 3126bb9fbe1bSKan Liang 3127d7717587SStephane Eranian /* BDX-DE doesn't have SBOX */ 312815a3e845SOskar Senft if (boot_cpu_data.x86_model == 86) { 3129d7717587SStephane Eranian uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL; 313015a3e845SOskar Senft /* Detect systems with no SBOXes */ 313115a3e845SOskar Senft } else if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) { 313215a3e845SOskar Senft struct pci_dev *pdev; 313315a3e845SOskar Senft u32 capid4; 3134d7717587SStephane Eranian 313515a3e845SOskar Senft pdev = uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]; 313615a3e845SOskar Senft pci_read_config_dword(pdev, 0x94, &capid4); 313715a3e845SOskar Senft if (((capid4 >> 6) & 0x3) == 0) 313815a3e845SOskar Senft bdx_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL; 313915a3e845SOskar Senft } 3140bb9fbe1bSKan Liang hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints; 3141ed367e6cSBorislav Petkov } 3142ed367e6cSBorislav Petkov 3143ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_ha = { 3144ed367e6cSBorislav Petkov .name = "ha", 3145ed367e6cSBorislav Petkov .num_counters = 4, 3146ed367e6cSBorislav Petkov .num_boxes = 2, 3147ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3148ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3149ed367e6cSBorislav Petkov }; 3150ed367e6cSBorislav Petkov 3151ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_imc = { 3152ed367e6cSBorislav Petkov .name = "imc", 315310e9e7bdSKan Liang .num_counters = 4, 3154ed367e6cSBorislav Petkov .num_boxes = 8, 3155ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3156ed367e6cSBorislav Petkov .fixed_ctr_bits = 48, 3157ed367e6cSBorislav Petkov .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 3158ed367e6cSBorislav Petkov .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 3159ed367e6cSBorislav Petkov .event_descs = hswep_uncore_imc_events, 3160ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3161ed367e6cSBorislav Petkov }; 3162ed367e6cSBorislav Petkov 3163ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_irp = { 3164ed367e6cSBorislav Petkov .name = "irp", 3165ed367e6cSBorislav Petkov .num_counters = 4, 3166ed367e6cSBorislav Petkov .num_boxes = 1, 3167ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3168ed367e6cSBorislav Petkov .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3169ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3170ed367e6cSBorislav Petkov .ops = &hswep_uncore_irp_ops, 3171ed367e6cSBorislav Petkov .format_group = &snbep_uncore_format_group, 3172ed367e6cSBorislav Petkov }; 3173ed367e6cSBorislav Petkov 3174ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_qpi = { 3175ed367e6cSBorislav Petkov .name = "qpi", 3176ed367e6cSBorislav Petkov .num_counters = 4, 3177ed367e6cSBorislav Petkov .num_boxes = 3, 3178ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3179ed367e6cSBorislav Petkov .perf_ctr = SNBEP_PCI_PMON_CTR0, 3180ed367e6cSBorislav Petkov .event_ctl = SNBEP_PCI_PMON_CTL0, 3181ed367e6cSBorislav Petkov .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 3182ed367e6cSBorislav Petkov .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3183ed367e6cSBorislav Petkov .num_shared_regs = 1, 3184ed367e6cSBorislav Petkov .ops = &snbep_uncore_qpi_ops, 3185ed367e6cSBorislav Petkov .format_group = &snbep_uncore_qpi_format_group, 3186ed367e6cSBorislav Petkov }; 3187ed367e6cSBorislav Petkov 3188ed367e6cSBorislav Petkov static struct event_constraint bdx_uncore_r2pcie_constraints[] = { 3189ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3190ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3191ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3192ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x1), 3193ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x1), 3194ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3195ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3196ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3197ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3198ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 3199ed367e6cSBorislav Petkov }; 3200ed367e6cSBorislav Petkov 3201ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_r2pcie = { 3202ed367e6cSBorislav Petkov .name = "r2pcie", 3203ed367e6cSBorislav Petkov .num_counters = 4, 3204ed367e6cSBorislav Petkov .num_boxes = 1, 3205ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3206ed367e6cSBorislav Petkov .constraints = bdx_uncore_r2pcie_constraints, 3207ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3208ed367e6cSBorislav Petkov }; 3209ed367e6cSBorislav Petkov 3210ed367e6cSBorislav Petkov static struct event_constraint bdx_uncore_r3qpi_constraints[] = { 3211ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x01, 0x7), 3212ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x07, 0x7), 3213ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x08, 0x7), 3214ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x09, 0x7), 3215ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), 3216ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), 3217ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3218ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3219ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3220ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 3221ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x15, 0x3), 3222ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), 3223ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 3224ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 3225ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 3226ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 3227ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 3228ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3229ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3230ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 3231ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3232ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3233ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 3234ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 3235ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 3236ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 3237ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 3238ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 3239ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 3240ed367e6cSBorislav Petkov UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 3241ed367e6cSBorislav Petkov EVENT_CONSTRAINT_END 3242ed367e6cSBorislav Petkov }; 3243ed367e6cSBorislav Petkov 3244ed367e6cSBorislav Petkov static struct intel_uncore_type bdx_uncore_r3qpi = { 3245ed367e6cSBorislav Petkov .name = "r3qpi", 3246ed367e6cSBorislav Petkov .num_counters = 3, 3247ed367e6cSBorislav Petkov .num_boxes = 3, 3248ed367e6cSBorislav Petkov .perf_ctr_bits = 48, 3249ed367e6cSBorislav Petkov .constraints = bdx_uncore_r3qpi_constraints, 3250ed367e6cSBorislav Petkov SNBEP_UNCORE_PCI_COMMON_INIT(), 3251ed367e6cSBorislav Petkov }; 3252ed367e6cSBorislav Petkov 3253ed367e6cSBorislav Petkov enum { 3254ed367e6cSBorislav Petkov BDX_PCI_UNCORE_HA, 3255ed367e6cSBorislav Petkov BDX_PCI_UNCORE_IMC, 3256ed367e6cSBorislav Petkov BDX_PCI_UNCORE_IRP, 3257ed367e6cSBorislav Petkov BDX_PCI_UNCORE_QPI, 3258ed367e6cSBorislav Petkov BDX_PCI_UNCORE_R2PCIE, 3259ed367e6cSBorislav Petkov BDX_PCI_UNCORE_R3QPI, 3260ed367e6cSBorislav Petkov }; 3261ed367e6cSBorislav Petkov 3262ed367e6cSBorislav Petkov static struct intel_uncore_type *bdx_pci_uncores[] = { 3263ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha, 3264ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc, 3265ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp, 3266ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_QPI] = &bdx_uncore_qpi, 3267ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie, 3268ed367e6cSBorislav Petkov [BDX_PCI_UNCORE_R3QPI] = &bdx_uncore_r3qpi, 3269ed367e6cSBorislav Petkov NULL, 3270ed367e6cSBorislav Petkov }; 3271ed367e6cSBorislav Petkov 3272ed367e6cSBorislav Petkov static const struct pci_device_id bdx_uncore_pci_ids[] = { 3273ed367e6cSBorislav Petkov { /* Home Agent 0 */ 3274ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30), 3275ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0), 3276ed367e6cSBorislav Petkov }, 3277ed367e6cSBorislav Petkov { /* Home Agent 1 */ 3278ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38), 3279ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 1), 3280ed367e6cSBorislav Petkov }, 3281ed367e6cSBorislav Petkov { /* MC0 Channel 0 */ 3282ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0), 3283ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0), 3284ed367e6cSBorislav Petkov }, 3285ed367e6cSBorislav Petkov { /* MC0 Channel 1 */ 3286ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1), 3287ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1), 3288ed367e6cSBorislav Petkov }, 3289ed367e6cSBorislav Petkov { /* MC0 Channel 2 */ 3290ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4), 3291ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 2), 3292ed367e6cSBorislav Petkov }, 3293ed367e6cSBorislav Petkov { /* MC0 Channel 3 */ 3294ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5), 3295ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 3), 3296ed367e6cSBorislav Petkov }, 3297ed367e6cSBorislav Petkov { /* MC1 Channel 0 */ 3298ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0), 3299ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 4), 3300ed367e6cSBorislav Petkov }, 3301ed367e6cSBorislav Petkov { /* MC1 Channel 1 */ 3302ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1), 3303ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 5), 3304ed367e6cSBorislav Petkov }, 3305ed367e6cSBorislav Petkov { /* MC1 Channel 2 */ 3306ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4), 3307ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 6), 3308ed367e6cSBorislav Petkov }, 3309ed367e6cSBorislav Petkov { /* MC1 Channel 3 */ 3310ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5), 3311ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 7), 3312ed367e6cSBorislav Petkov }, 3313ed367e6cSBorislav Petkov { /* IRP */ 3314ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39), 3315ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0), 3316ed367e6cSBorislav Petkov }, 3317ed367e6cSBorislav Petkov { /* QPI0 Port 0 */ 3318ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32), 3319ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0), 3320ed367e6cSBorislav Petkov }, 3321ed367e6cSBorislav Petkov { /* QPI0 Port 1 */ 3322ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33), 3323ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 1), 3324ed367e6cSBorislav Petkov }, 3325ed367e6cSBorislav Petkov { /* QPI1 Port 2 */ 3326ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a), 3327ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 2), 3328ed367e6cSBorislav Petkov }, 3329ed367e6cSBorislav Petkov { /* R2PCIe */ 3330ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34), 3331ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0), 3332ed367e6cSBorislav Petkov }, 3333ed367e6cSBorislav Petkov { /* R3QPI0 Link 0 */ 3334ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36), 3335ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0), 3336ed367e6cSBorislav Petkov }, 3337ed367e6cSBorislav Petkov { /* R3QPI0 Link 1 */ 3338ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37), 3339ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 1), 3340ed367e6cSBorislav Petkov }, 3341ed367e6cSBorislav Petkov { /* R3QPI1 Link 2 */ 3342ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e), 3343ed367e6cSBorislav Petkov .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 2), 3344ed367e6cSBorislav Petkov }, 3345ed367e6cSBorislav Petkov { /* QPI Port 0 filter */ 3346ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86), 3347156c8b58SKan Liang .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3348156c8b58SKan Liang SNBEP_PCI_QPI_PORT0_FILTER), 3349ed367e6cSBorislav Petkov }, 3350ed367e6cSBorislav Petkov { /* QPI Port 1 filter */ 3351ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96), 3352156c8b58SKan Liang .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3353156c8b58SKan Liang SNBEP_PCI_QPI_PORT1_FILTER), 3354ed367e6cSBorislav Petkov }, 3355ed367e6cSBorislav Petkov { /* QPI Port 2 filter */ 3356ed367e6cSBorislav Petkov PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46), 3357156c8b58SKan Liang .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3358156c8b58SKan Liang BDX_PCI_QPI_PORT2_FILTER), 3359ed367e6cSBorislav Petkov }, 336015a3e845SOskar Senft { /* PCU.3 (for Capability registers) */ 336115a3e845SOskar Senft PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fc0), 336215a3e845SOskar Senft .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 336315a3e845SOskar Senft HSWEP_PCI_PCU_3), 336415a3e845SOskar Senft }, 3365ed367e6cSBorislav Petkov { /* end: all zeroes */ } 3366ed367e6cSBorislav Petkov }; 3367ed367e6cSBorislav Petkov 3368ed367e6cSBorislav Petkov static struct pci_driver bdx_uncore_pci_driver = { 3369ed367e6cSBorislav Petkov .name = "bdx_uncore", 3370ed367e6cSBorislav Petkov .id_table = bdx_uncore_pci_ids, 3371ed367e6cSBorislav Petkov }; 3372ed367e6cSBorislav Petkov 3373ed367e6cSBorislav Petkov int bdx_uncore_pci_init(void) 3374ed367e6cSBorislav Petkov { 337568ce4a0dSKan Liang int ret = snbep_pci2phy_map_init(0x6f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 3376ed367e6cSBorislav Petkov 3377ed367e6cSBorislav Petkov if (ret) 3378ed367e6cSBorislav Petkov return ret; 3379ed367e6cSBorislav Petkov uncore_pci_uncores = bdx_pci_uncores; 3380ed367e6cSBorislav Petkov uncore_pci_driver = &bdx_uncore_pci_driver; 3381ed367e6cSBorislav Petkov return 0; 3382ed367e6cSBorislav Petkov } 3383ed367e6cSBorislav Petkov 3384ed367e6cSBorislav Petkov /* end of BDX uncore support */ 3385cd34cd97SKan Liang 3386cd34cd97SKan Liang /* SKX uncore support */ 3387cd34cd97SKan Liang 3388cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_ubox = { 3389cd34cd97SKan Liang .name = "ubox", 3390cd34cd97SKan Liang .num_counters = 2, 3391cd34cd97SKan Liang .num_boxes = 1, 3392cd34cd97SKan Liang .perf_ctr_bits = 48, 3393cd34cd97SKan Liang .fixed_ctr_bits = 48, 3394cd34cd97SKan Liang .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 3395cd34cd97SKan Liang .event_ctl = HSWEP_U_MSR_PMON_CTL0, 3396cd34cd97SKan Liang .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 3397cd34cd97SKan Liang .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 3398cd34cd97SKan Liang .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 3399cd34cd97SKan Liang .ops = &ivbep_uncore_msr_ops, 3400cd34cd97SKan Liang .format_group = &ivbep_uncore_ubox_format_group, 3401cd34cd97SKan Liang }; 3402cd34cd97SKan Liang 3403cd34cd97SKan Liang static struct attribute *skx_uncore_cha_formats_attr[] = { 3404cd34cd97SKan Liang &format_attr_event.attr, 3405cd34cd97SKan Liang &format_attr_umask.attr, 3406cd34cd97SKan Liang &format_attr_edge.attr, 3407cd34cd97SKan Liang &format_attr_tid_en.attr, 3408cd34cd97SKan Liang &format_attr_inv.attr, 3409cd34cd97SKan Liang &format_attr_thresh8.attr, 3410cd34cd97SKan Liang &format_attr_filter_tid4.attr, 3411cd34cd97SKan Liang &format_attr_filter_state5.attr, 3412cd34cd97SKan Liang &format_attr_filter_rem.attr, 3413cd34cd97SKan Liang &format_attr_filter_loc.attr, 3414cd34cd97SKan Liang &format_attr_filter_nm.attr, 3415cd34cd97SKan Liang &format_attr_filter_all_op.attr, 3416cd34cd97SKan Liang &format_attr_filter_not_nm.attr, 3417cd34cd97SKan Liang &format_attr_filter_opc_0.attr, 3418cd34cd97SKan Liang &format_attr_filter_opc_1.attr, 3419cd34cd97SKan Liang &format_attr_filter_nc.attr, 3420cd34cd97SKan Liang &format_attr_filter_isoc.attr, 3421cd34cd97SKan Liang NULL, 3422cd34cd97SKan Liang }; 3423cd34cd97SKan Liang 342445bd07adSArvind Yadav static const struct attribute_group skx_uncore_chabox_format_group = { 3425cd34cd97SKan Liang .name = "format", 3426cd34cd97SKan Liang .attrs = skx_uncore_cha_formats_attr, 3427cd34cd97SKan Liang }; 3428cd34cd97SKan Liang 3429cd34cd97SKan Liang static struct event_constraint skx_uncore_chabox_constraints[] = { 3430cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 3431cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 3432cd34cd97SKan Liang EVENT_CONSTRAINT_END 3433cd34cd97SKan Liang }; 3434cd34cd97SKan Liang 3435cd34cd97SKan Liang static struct extra_reg skx_uncore_cha_extra_regs[] = { 3436cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 3437cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 3438cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 3439cd34cd97SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 3440c3f02682SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x3134, 0xffff, 0x4), 3441c3f02682SKan Liang SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4), 34428aa7b7b4SStephane Eranian SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8), 34438aa7b7b4SStephane Eranian SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8), 3444e340895cSStephane Eranian SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3), 3445ba883b4aSStephane Eranian EVENT_EXTRA_END 3446cd34cd97SKan Liang }; 3447cd34cd97SKan Liang 3448cd34cd97SKan Liang static u64 skx_cha_filter_mask(int fields) 3449cd34cd97SKan Liang { 3450cd34cd97SKan Liang u64 mask = 0; 3451cd34cd97SKan Liang 3452cd34cd97SKan Liang if (fields & 0x1) 3453cd34cd97SKan Liang mask |= SKX_CHA_MSR_PMON_BOX_FILTER_TID; 3454cd34cd97SKan Liang if (fields & 0x2) 3455cd34cd97SKan Liang mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LINK; 3456cd34cd97SKan Liang if (fields & 0x4) 3457cd34cd97SKan Liang mask |= SKX_CHA_MSR_PMON_BOX_FILTER_STATE; 34588aa7b7b4SStephane Eranian if (fields & 0x8) { 34598aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_REM; 34608aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LOC; 34618aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC; 34628aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NM; 34638aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM; 34648aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC0; 34658aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC1; 34668aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NC; 34678aa7b7b4SStephane Eranian mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ISOC; 34688aa7b7b4SStephane Eranian } 3469cd34cd97SKan Liang return mask; 3470cd34cd97SKan Liang } 3471cd34cd97SKan Liang 3472cd34cd97SKan Liang static struct event_constraint * 3473cd34cd97SKan Liang skx_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 3474cd34cd97SKan Liang { 3475cd34cd97SKan Liang return __snbep_cbox_get_constraint(box, event, skx_cha_filter_mask); 3476cd34cd97SKan Liang } 3477cd34cd97SKan Liang 3478cd34cd97SKan Liang static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 3479cd34cd97SKan Liang { 3480cd34cd97SKan Liang struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 3481cd34cd97SKan Liang struct extra_reg *er; 3482cd34cd97SKan Liang int idx = 0; 3483cd34cd97SKan Liang 3484cd34cd97SKan Liang for (er = skx_uncore_cha_extra_regs; er->msr; er++) { 3485cd34cd97SKan Liang if (er->event != (event->hw.config & er->config_mask)) 3486cd34cd97SKan Liang continue; 3487cd34cd97SKan Liang idx |= er->idx; 3488cd34cd97SKan Liang } 3489cd34cd97SKan Liang 3490cd34cd97SKan Liang if (idx) { 3491cd34cd97SKan Liang reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 3492cd34cd97SKan Liang HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 3493cd34cd97SKan Liang reg1->config = event->attr.config1 & skx_cha_filter_mask(idx); 3494cd34cd97SKan Liang reg1->idx = idx; 3495cd34cd97SKan Liang } 3496cd34cd97SKan Liang return 0; 3497cd34cd97SKan Liang } 3498cd34cd97SKan Liang 3499cd34cd97SKan Liang static struct intel_uncore_ops skx_uncore_chabox_ops = { 3500cd34cd97SKan Liang /* There is no frz_en for chabox ctl */ 3501cd34cd97SKan Liang .init_box = ivbep_uncore_msr_init_box, 3502cd34cd97SKan Liang .disable_box = snbep_uncore_msr_disable_box, 3503cd34cd97SKan Liang .enable_box = snbep_uncore_msr_enable_box, 3504cd34cd97SKan Liang .disable_event = snbep_uncore_msr_disable_event, 3505cd34cd97SKan Liang .enable_event = hswep_cbox_enable_event, 3506cd34cd97SKan Liang .read_counter = uncore_msr_read_counter, 3507cd34cd97SKan Liang .hw_config = skx_cha_hw_config, 3508cd34cd97SKan Liang .get_constraint = skx_cha_get_constraint, 3509cd34cd97SKan Liang .put_constraint = snbep_cbox_put_constraint, 3510cd34cd97SKan Liang }; 3511cd34cd97SKan Liang 3512cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_chabox = { 3513cd34cd97SKan Liang .name = "cha", 3514cd34cd97SKan Liang .num_counters = 4, 3515cd34cd97SKan Liang .perf_ctr_bits = 48, 3516cd34cd97SKan Liang .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 3517cd34cd97SKan Liang .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 3518cd34cd97SKan Liang .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 3519cd34cd97SKan Liang .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 3520cd34cd97SKan Liang .msr_offset = HSWEP_CBO_MSR_OFFSET, 3521cd34cd97SKan Liang .num_shared_regs = 1, 3522cd34cd97SKan Liang .constraints = skx_uncore_chabox_constraints, 3523cd34cd97SKan Liang .ops = &skx_uncore_chabox_ops, 3524cd34cd97SKan Liang .format_group = &skx_uncore_chabox_format_group, 3525cd34cd97SKan Liang }; 3526cd34cd97SKan Liang 3527cd34cd97SKan Liang static struct attribute *skx_uncore_iio_formats_attr[] = { 3528cd34cd97SKan Liang &format_attr_event.attr, 3529cd34cd97SKan Liang &format_attr_umask.attr, 3530cd34cd97SKan Liang &format_attr_edge.attr, 3531cd34cd97SKan Liang &format_attr_inv.attr, 3532cd34cd97SKan Liang &format_attr_thresh9.attr, 3533cd34cd97SKan Liang &format_attr_ch_mask.attr, 3534cd34cd97SKan Liang &format_attr_fc_mask.attr, 3535cd34cd97SKan Liang NULL, 3536cd34cd97SKan Liang }; 3537cd34cd97SKan Liang 353845bd07adSArvind Yadav static const struct attribute_group skx_uncore_iio_format_group = { 3539cd34cd97SKan Liang .name = "format", 3540cd34cd97SKan Liang .attrs = skx_uncore_iio_formats_attr, 3541cd34cd97SKan Liang }; 3542cd34cd97SKan Liang 3543cd34cd97SKan Liang static struct event_constraint skx_uncore_iio_constraints[] = { 3544cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x83, 0x3), 3545cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x88, 0xc), 3546cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x95, 0xc), 3547cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0xc0, 0xc), 3548cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0xc5, 0xc), 3549cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0xd4, 0xc), 3550cd34cd97SKan Liang EVENT_CONSTRAINT_END 3551cd34cd97SKan Liang }; 3552cd34cd97SKan Liang 3553cd34cd97SKan Liang static void skx_iio_enable_event(struct intel_uncore_box *box, 3554cd34cd97SKan Liang struct perf_event *event) 3555cd34cd97SKan Liang { 3556cd34cd97SKan Liang struct hw_perf_event *hwc = &event->hw; 3557cd34cd97SKan Liang 3558cd34cd97SKan Liang wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 3559cd34cd97SKan Liang } 3560cd34cd97SKan Liang 3561cd34cd97SKan Liang static struct intel_uncore_ops skx_uncore_iio_ops = { 3562cd34cd97SKan Liang .init_box = ivbep_uncore_msr_init_box, 3563cd34cd97SKan Liang .disable_box = snbep_uncore_msr_disable_box, 3564cd34cd97SKan Liang .enable_box = snbep_uncore_msr_enable_box, 3565cd34cd97SKan Liang .disable_event = snbep_uncore_msr_disable_event, 3566cd34cd97SKan Liang .enable_event = skx_iio_enable_event, 3567cd34cd97SKan Liang .read_counter = uncore_msr_read_counter, 3568cd34cd97SKan Liang }; 3569cd34cd97SKan Liang 3570cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_iio = { 3571cd34cd97SKan Liang .name = "iio", 3572cd34cd97SKan Liang .num_counters = 4, 357329b46dfbSKan Liang .num_boxes = 6, 3574cd34cd97SKan Liang .perf_ctr_bits = 48, 3575cd34cd97SKan Liang .event_ctl = SKX_IIO0_MSR_PMON_CTL0, 3576cd34cd97SKan Liang .perf_ctr = SKX_IIO0_MSR_PMON_CTR0, 3577cd34cd97SKan Liang .event_mask = SKX_IIO_PMON_RAW_EVENT_MASK, 3578cd34cd97SKan Liang .event_mask_ext = SKX_IIO_PMON_RAW_EVENT_MASK_EXT, 3579cd34cd97SKan Liang .box_ctl = SKX_IIO0_MSR_PMON_BOX_CTL, 3580cd34cd97SKan Liang .msr_offset = SKX_IIO_MSR_OFFSET, 3581cd34cd97SKan Liang .constraints = skx_uncore_iio_constraints, 3582cd34cd97SKan Liang .ops = &skx_uncore_iio_ops, 3583cd34cd97SKan Liang .format_group = &skx_uncore_iio_format_group, 3584cd34cd97SKan Liang }; 3585cd34cd97SKan Liang 35860f519f03SKan Liang enum perf_uncore_iio_freerunning_type_id { 35870f519f03SKan Liang SKX_IIO_MSR_IOCLK = 0, 35880f519f03SKan Liang SKX_IIO_MSR_BW = 1, 35890f519f03SKan Liang SKX_IIO_MSR_UTIL = 2, 35900f519f03SKan Liang 35910f519f03SKan Liang SKX_IIO_FREERUNNING_TYPE_MAX, 35920f519f03SKan Liang }; 35930f519f03SKan Liang 35940f519f03SKan Liang 35950f519f03SKan Liang static struct freerunning_counters skx_iio_freerunning[] = { 35960f519f03SKan Liang [SKX_IIO_MSR_IOCLK] = { 0xa45, 0x1, 0x20, 1, 36 }, 35970f519f03SKan Liang [SKX_IIO_MSR_BW] = { 0xb00, 0x1, 0x10, 8, 36 }, 35980f519f03SKan Liang [SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 }, 35990f519f03SKan Liang }; 36000f519f03SKan Liang 36010f519f03SKan Liang static struct uncore_event_desc skx_uncore_iio_freerunning_events[] = { 36020f519f03SKan Liang /* Free-Running IO CLOCKS Counter */ 36030f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"), 36040f519f03SKan Liang /* Free-Running IIO BANDWIDTH Counters */ 36050f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"), 36060f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.814697266e-6"), 36070f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"), 36080f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"), 36090f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.814697266e-6"), 36100f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"), 36110f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"), 36120f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.814697266e-6"), 36130f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"), 36140f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"), 36150f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.814697266e-6"), 36160f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"), 36170f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port0, "event=0xff,umask=0x24"), 36180f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port0.scale, "3.814697266e-6"), 36190f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port0.unit, "MiB"), 36200f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port1, "event=0xff,umask=0x25"), 36210f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port1.scale, "3.814697266e-6"), 36220f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port1.unit, "MiB"), 36230f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port2, "event=0xff,umask=0x26"), 36240f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port2.scale, "3.814697266e-6"), 36250f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port2.unit, "MiB"), 36260f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port3, "event=0xff,umask=0x27"), 36270f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port3.scale, "3.814697266e-6"), 36280f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(bw_out_port3.unit, "MiB"), 36290f519f03SKan Liang /* Free-running IIO UTILIZATION Counters */ 36300f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=0xff,umask=0x30"), 36310f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=0xff,umask=0x31"), 36320f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_in_port1, "event=0xff,umask=0x32"), 36330f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_out_port1, "event=0xff,umask=0x33"), 36340f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_in_port2, "event=0xff,umask=0x34"), 36350f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_out_port2, "event=0xff,umask=0x35"), 36360f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_in_port3, "event=0xff,umask=0x36"), 36370f519f03SKan Liang INTEL_UNCORE_EVENT_DESC(util_out_port3, "event=0xff,umask=0x37"), 36380f519f03SKan Liang { /* end: all zeroes */ }, 36390f519f03SKan Liang }; 36400f519f03SKan Liang 36410f519f03SKan Liang static struct intel_uncore_ops skx_uncore_iio_freerunning_ops = { 36420f519f03SKan Liang .read_counter = uncore_msr_read_counter, 3643543ac280SKan Liang .hw_config = uncore_freerunning_hw_config, 36440f519f03SKan Liang }; 36450f519f03SKan Liang 36460f519f03SKan Liang static struct attribute *skx_uncore_iio_freerunning_formats_attr[] = { 36470f519f03SKan Liang &format_attr_event.attr, 36480f519f03SKan Liang &format_attr_umask.attr, 36490f519f03SKan Liang NULL, 36500f519f03SKan Liang }; 36510f519f03SKan Liang 36520f519f03SKan Liang static const struct attribute_group skx_uncore_iio_freerunning_format_group = { 36530f519f03SKan Liang .name = "format", 36540f519f03SKan Liang .attrs = skx_uncore_iio_freerunning_formats_attr, 36550f519f03SKan Liang }; 36560f519f03SKan Liang 36570f519f03SKan Liang static struct intel_uncore_type skx_uncore_iio_free_running = { 36580f519f03SKan Liang .name = "iio_free_running", 36590f519f03SKan Liang .num_counters = 17, 36600f519f03SKan Liang .num_boxes = 6, 36610f519f03SKan Liang .num_freerunning_types = SKX_IIO_FREERUNNING_TYPE_MAX, 36620f519f03SKan Liang .freerunning = skx_iio_freerunning, 36630f519f03SKan Liang .ops = &skx_uncore_iio_freerunning_ops, 36640f519f03SKan Liang .event_descs = skx_uncore_iio_freerunning_events, 36650f519f03SKan Liang .format_group = &skx_uncore_iio_freerunning_format_group, 36660f519f03SKan Liang }; 36670f519f03SKan Liang 3668cd34cd97SKan Liang static struct attribute *skx_uncore_formats_attr[] = { 3669cd34cd97SKan Liang &format_attr_event.attr, 3670cd34cd97SKan Liang &format_attr_umask.attr, 3671cd34cd97SKan Liang &format_attr_edge.attr, 3672cd34cd97SKan Liang &format_attr_inv.attr, 3673cd34cd97SKan Liang &format_attr_thresh8.attr, 3674cd34cd97SKan Liang NULL, 3675cd34cd97SKan Liang }; 3676cd34cd97SKan Liang 367745bd07adSArvind Yadav static const struct attribute_group skx_uncore_format_group = { 3678cd34cd97SKan Liang .name = "format", 3679cd34cd97SKan Liang .attrs = skx_uncore_formats_attr, 3680cd34cd97SKan Liang }; 3681cd34cd97SKan Liang 3682cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_irp = { 3683cd34cd97SKan Liang .name = "irp", 3684cd34cd97SKan Liang .num_counters = 2, 368529b46dfbSKan Liang .num_boxes = 6, 3686cd34cd97SKan Liang .perf_ctr_bits = 48, 3687cd34cd97SKan Liang .event_ctl = SKX_IRP0_MSR_PMON_CTL0, 3688cd34cd97SKan Liang .perf_ctr = SKX_IRP0_MSR_PMON_CTR0, 3689cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3690cd34cd97SKan Liang .box_ctl = SKX_IRP0_MSR_PMON_BOX_CTL, 3691cd34cd97SKan Liang .msr_offset = SKX_IRP_MSR_OFFSET, 3692cd34cd97SKan Liang .ops = &skx_uncore_iio_ops, 3693cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3694cd34cd97SKan Liang }; 3695cd34cd97SKan Liang 3696bab4e569SKan Liang static struct attribute *skx_uncore_pcu_formats_attr[] = { 3697bab4e569SKan Liang &format_attr_event.attr, 3698bab4e569SKan Liang &format_attr_umask.attr, 3699bab4e569SKan Liang &format_attr_edge.attr, 3700bab4e569SKan Liang &format_attr_inv.attr, 3701bab4e569SKan Liang &format_attr_thresh8.attr, 3702bab4e569SKan Liang &format_attr_occ_invert.attr, 3703bab4e569SKan Liang &format_attr_occ_edge_det.attr, 3704bab4e569SKan Liang &format_attr_filter_band0.attr, 3705bab4e569SKan Liang &format_attr_filter_band1.attr, 3706bab4e569SKan Liang &format_attr_filter_band2.attr, 3707bab4e569SKan Liang &format_attr_filter_band3.attr, 3708bab4e569SKan Liang NULL, 3709bab4e569SKan Liang }; 3710bab4e569SKan Liang 3711bab4e569SKan Liang static struct attribute_group skx_uncore_pcu_format_group = { 3712bab4e569SKan Liang .name = "format", 3713bab4e569SKan Liang .attrs = skx_uncore_pcu_formats_attr, 3714bab4e569SKan Liang }; 3715bab4e569SKan Liang 3716cd34cd97SKan Liang static struct intel_uncore_ops skx_uncore_pcu_ops = { 3717cd34cd97SKan Liang IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 3718cd34cd97SKan Liang .hw_config = hswep_pcu_hw_config, 3719cd34cd97SKan Liang .get_constraint = snbep_pcu_get_constraint, 3720cd34cd97SKan Liang .put_constraint = snbep_pcu_put_constraint, 3721cd34cd97SKan Liang }; 3722cd34cd97SKan Liang 3723cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_pcu = { 3724cd34cd97SKan Liang .name = "pcu", 3725cd34cd97SKan Liang .num_counters = 4, 3726cd34cd97SKan Liang .num_boxes = 1, 3727cd34cd97SKan Liang .perf_ctr_bits = 48, 3728cd34cd97SKan Liang .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 3729cd34cd97SKan Liang .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 3730cd34cd97SKan Liang .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 3731cd34cd97SKan Liang .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 3732cd34cd97SKan Liang .num_shared_regs = 1, 3733cd34cd97SKan Liang .ops = &skx_uncore_pcu_ops, 3734bab4e569SKan Liang .format_group = &skx_uncore_pcu_format_group, 3735cd34cd97SKan Liang }; 3736cd34cd97SKan Liang 3737cd34cd97SKan Liang static struct intel_uncore_type *skx_msr_uncores[] = { 3738cd34cd97SKan Liang &skx_uncore_ubox, 3739cd34cd97SKan Liang &skx_uncore_chabox, 3740cd34cd97SKan Liang &skx_uncore_iio, 37410f519f03SKan Liang &skx_uncore_iio_free_running, 3742cd34cd97SKan Liang &skx_uncore_irp, 3743cd34cd97SKan Liang &skx_uncore_pcu, 3744cd34cd97SKan Liang NULL, 3745cd34cd97SKan Liang }; 3746cd34cd97SKan Liang 3747320b0651SKan Liang /* 3748320b0651SKan Liang * To determine the number of CHAs, it should read bits 27:0 in the CAPID6 3749320b0651SKan Liang * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083. 3750320b0651SKan Liang */ 3751320b0651SKan Liang #define SKX_CAPID6 0x9c 3752320b0651SKan Liang #define SKX_CHA_BIT_MASK GENMASK(27, 0) 3753320b0651SKan Liang 3754cd34cd97SKan Liang static int skx_count_chabox(void) 3755cd34cd97SKan Liang { 3756320b0651SKan Liang struct pci_dev *dev = NULL; 3757320b0651SKan Liang u32 val = 0; 3758cd34cd97SKan Liang 3759320b0651SKan Liang dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev); 3760320b0651SKan Liang if (!dev) 3761320b0651SKan Liang goto out; 3762cd34cd97SKan Liang 3763320b0651SKan Liang pci_read_config_dword(dev, SKX_CAPID6, &val); 3764320b0651SKan Liang val &= SKX_CHA_BIT_MASK; 3765320b0651SKan Liang out: 3766320b0651SKan Liang pci_dev_put(dev); 3767320b0651SKan Liang return hweight32(val); 3768cd34cd97SKan Liang } 3769cd34cd97SKan Liang 3770cd34cd97SKan Liang void skx_uncore_cpu_init(void) 3771cd34cd97SKan Liang { 3772cd34cd97SKan Liang skx_uncore_chabox.num_boxes = skx_count_chabox(); 3773cd34cd97SKan Liang uncore_msr_uncores = skx_msr_uncores; 3774cd34cd97SKan Liang } 3775cd34cd97SKan Liang 3776cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_imc = { 3777cd34cd97SKan Liang .name = "imc", 3778cd34cd97SKan Liang .num_counters = 4, 3779cd34cd97SKan Liang .num_boxes = 6, 3780cd34cd97SKan Liang .perf_ctr_bits = 48, 3781cd34cd97SKan Liang .fixed_ctr_bits = 48, 3782cd34cd97SKan Liang .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 3783cd34cd97SKan Liang .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 3784cd34cd97SKan Liang .event_descs = hswep_uncore_imc_events, 3785cd34cd97SKan Liang .perf_ctr = SNBEP_PCI_PMON_CTR0, 3786cd34cd97SKan Liang .event_ctl = SNBEP_PCI_PMON_CTL0, 3787cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3788cd34cd97SKan Liang .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3789cd34cd97SKan Liang .ops = &ivbep_uncore_pci_ops, 3790cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3791cd34cd97SKan Liang }; 3792cd34cd97SKan Liang 3793cd34cd97SKan Liang static struct attribute *skx_upi_uncore_formats_attr[] = { 379431766094SKan Liang &format_attr_event.attr, 3795cd34cd97SKan Liang &format_attr_umask_ext.attr, 3796cd34cd97SKan Liang &format_attr_edge.attr, 3797cd34cd97SKan Liang &format_attr_inv.attr, 3798cd34cd97SKan Liang &format_attr_thresh8.attr, 3799cd34cd97SKan Liang NULL, 3800cd34cd97SKan Liang }; 3801cd34cd97SKan Liang 380245bd07adSArvind Yadav static const struct attribute_group skx_upi_uncore_format_group = { 3803cd34cd97SKan Liang .name = "format", 3804cd34cd97SKan Liang .attrs = skx_upi_uncore_formats_attr, 3805cd34cd97SKan Liang }; 3806cd34cd97SKan Liang 3807cd34cd97SKan Liang static void skx_upi_uncore_pci_init_box(struct intel_uncore_box *box) 3808cd34cd97SKan Liang { 3809cd34cd97SKan Liang struct pci_dev *pdev = box->pci_dev; 3810cd34cd97SKan Liang 3811cd34cd97SKan Liang __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 3812cd34cd97SKan Liang pci_write_config_dword(pdev, SKX_UPI_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 3813cd34cd97SKan Liang } 3814cd34cd97SKan Liang 3815cd34cd97SKan Liang static struct intel_uncore_ops skx_upi_uncore_pci_ops = { 3816cd34cd97SKan Liang .init_box = skx_upi_uncore_pci_init_box, 3817cd34cd97SKan Liang .disable_box = snbep_uncore_pci_disable_box, 3818cd34cd97SKan Liang .enable_box = snbep_uncore_pci_enable_box, 3819cd34cd97SKan Liang .disable_event = snbep_uncore_pci_disable_event, 3820cd34cd97SKan Liang .enable_event = snbep_uncore_pci_enable_event, 3821cd34cd97SKan Liang .read_counter = snbep_uncore_pci_read_counter, 3822cd34cd97SKan Liang }; 3823cd34cd97SKan Liang 3824cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_upi = { 3825cd34cd97SKan Liang .name = "upi", 3826cd34cd97SKan Liang .num_counters = 4, 3827cd34cd97SKan Liang .num_boxes = 3, 3828cd34cd97SKan Liang .perf_ctr_bits = 48, 3829cd34cd97SKan Liang .perf_ctr = SKX_UPI_PCI_PMON_CTR0, 3830cd34cd97SKan Liang .event_ctl = SKX_UPI_PCI_PMON_CTL0, 3831b3625980SStephane Eranian .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3832b3625980SStephane Eranian .event_mask_ext = SKX_UPI_CTL_UMASK_EXT, 3833cd34cd97SKan Liang .box_ctl = SKX_UPI_PCI_PMON_BOX_CTL, 3834cd34cd97SKan Liang .ops = &skx_upi_uncore_pci_ops, 3835cd34cd97SKan Liang .format_group = &skx_upi_uncore_format_group, 3836cd34cd97SKan Liang }; 3837cd34cd97SKan Liang 3838cd34cd97SKan Liang static void skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box) 3839cd34cd97SKan Liang { 3840cd34cd97SKan Liang struct pci_dev *pdev = box->pci_dev; 3841cd34cd97SKan Liang 3842cd34cd97SKan Liang __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 3843cd34cd97SKan Liang pci_write_config_dword(pdev, SKX_M2M_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 3844cd34cd97SKan Liang } 3845cd34cd97SKan Liang 3846cd34cd97SKan Liang static struct intel_uncore_ops skx_m2m_uncore_pci_ops = { 3847cd34cd97SKan Liang .init_box = skx_m2m_uncore_pci_init_box, 3848cd34cd97SKan Liang .disable_box = snbep_uncore_pci_disable_box, 3849cd34cd97SKan Liang .enable_box = snbep_uncore_pci_enable_box, 3850cd34cd97SKan Liang .disable_event = snbep_uncore_pci_disable_event, 3851cd34cd97SKan Liang .enable_event = snbep_uncore_pci_enable_event, 3852cd34cd97SKan Liang .read_counter = snbep_uncore_pci_read_counter, 3853cd34cd97SKan Liang }; 3854cd34cd97SKan Liang 3855cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_m2m = { 3856cd34cd97SKan Liang .name = "m2m", 3857cd34cd97SKan Liang .num_counters = 4, 3858cd34cd97SKan Liang .num_boxes = 2, 3859cd34cd97SKan Liang .perf_ctr_bits = 48, 3860cd34cd97SKan Liang .perf_ctr = SKX_M2M_PCI_PMON_CTR0, 3861cd34cd97SKan Liang .event_ctl = SKX_M2M_PCI_PMON_CTL0, 3862cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3863cd34cd97SKan Liang .box_ctl = SKX_M2M_PCI_PMON_BOX_CTL, 3864cd34cd97SKan Liang .ops = &skx_m2m_uncore_pci_ops, 3865cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3866cd34cd97SKan Liang }; 3867cd34cd97SKan Liang 3868cd34cd97SKan Liang static struct event_constraint skx_uncore_m2pcie_constraints[] = { 3869cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 3870cd34cd97SKan Liang EVENT_CONSTRAINT_END 3871cd34cd97SKan Liang }; 3872cd34cd97SKan Liang 3873cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_m2pcie = { 3874cd34cd97SKan Liang .name = "m2pcie", 3875cd34cd97SKan Liang .num_counters = 4, 3876cd34cd97SKan Liang .num_boxes = 4, 3877cd34cd97SKan Liang .perf_ctr_bits = 48, 3878cd34cd97SKan Liang .constraints = skx_uncore_m2pcie_constraints, 3879cd34cd97SKan Liang .perf_ctr = SNBEP_PCI_PMON_CTR0, 3880cd34cd97SKan Liang .event_ctl = SNBEP_PCI_PMON_CTL0, 3881cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3882cd34cd97SKan Liang .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3883cd34cd97SKan Liang .ops = &ivbep_uncore_pci_ops, 3884cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3885cd34cd97SKan Liang }; 3886cd34cd97SKan Liang 3887cd34cd97SKan Liang static struct event_constraint skx_uncore_m3upi_constraints[] = { 3888cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x1d, 0x1), 3889cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x1e, 0x1), 3890cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x40, 0x7), 3891cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x4e, 0x7), 3892cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x4f, 0x7), 3893cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x50, 0x7), 3894cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x51, 0x7), 3895cd34cd97SKan Liang UNCORE_EVENT_CONSTRAINT(0x52, 0x7), 3896cd34cd97SKan Liang EVENT_CONSTRAINT_END 3897cd34cd97SKan Liang }; 3898cd34cd97SKan Liang 3899cd34cd97SKan Liang static struct intel_uncore_type skx_uncore_m3upi = { 3900cd34cd97SKan Liang .name = "m3upi", 3901cd34cd97SKan Liang .num_counters = 3, 3902cd34cd97SKan Liang .num_boxes = 3, 3903cd34cd97SKan Liang .perf_ctr_bits = 48, 3904cd34cd97SKan Liang .constraints = skx_uncore_m3upi_constraints, 3905cd34cd97SKan Liang .perf_ctr = SNBEP_PCI_PMON_CTR0, 3906cd34cd97SKan Liang .event_ctl = SNBEP_PCI_PMON_CTL0, 3907cd34cd97SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3908cd34cd97SKan Liang .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3909cd34cd97SKan Liang .ops = &ivbep_uncore_pci_ops, 3910cd34cd97SKan Liang .format_group = &skx_uncore_format_group, 3911cd34cd97SKan Liang }; 3912cd34cd97SKan Liang 3913cd34cd97SKan Liang enum { 3914cd34cd97SKan Liang SKX_PCI_UNCORE_IMC, 3915cd34cd97SKan Liang SKX_PCI_UNCORE_M2M, 3916cd34cd97SKan Liang SKX_PCI_UNCORE_UPI, 3917cd34cd97SKan Liang SKX_PCI_UNCORE_M2PCIE, 3918cd34cd97SKan Liang SKX_PCI_UNCORE_M3UPI, 3919cd34cd97SKan Liang }; 3920cd34cd97SKan Liang 3921cd34cd97SKan Liang static struct intel_uncore_type *skx_pci_uncores[] = { 3922cd34cd97SKan Liang [SKX_PCI_UNCORE_IMC] = &skx_uncore_imc, 3923cd34cd97SKan Liang [SKX_PCI_UNCORE_M2M] = &skx_uncore_m2m, 3924cd34cd97SKan Liang [SKX_PCI_UNCORE_UPI] = &skx_uncore_upi, 3925cd34cd97SKan Liang [SKX_PCI_UNCORE_M2PCIE] = &skx_uncore_m2pcie, 3926cd34cd97SKan Liang [SKX_PCI_UNCORE_M3UPI] = &skx_uncore_m3upi, 3927cd34cd97SKan Liang NULL, 3928cd34cd97SKan Liang }; 3929cd34cd97SKan Liang 3930cd34cd97SKan Liang static const struct pci_device_id skx_uncore_pci_ids[] = { 3931cd34cd97SKan Liang { /* MC0 Channel 0 */ 3932cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042), 3933cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 2, SKX_PCI_UNCORE_IMC, 0), 3934cd34cd97SKan Liang }, 3935cd34cd97SKan Liang { /* MC0 Channel 1 */ 3936cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046), 3937cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 6, SKX_PCI_UNCORE_IMC, 1), 3938cd34cd97SKan Liang }, 3939cd34cd97SKan Liang { /* MC0 Channel 2 */ 3940cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a), 3941cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 2, SKX_PCI_UNCORE_IMC, 2), 3942cd34cd97SKan Liang }, 3943cd34cd97SKan Liang { /* MC1 Channel 0 */ 3944cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042), 3945cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 2, SKX_PCI_UNCORE_IMC, 3), 3946cd34cd97SKan Liang }, 3947cd34cd97SKan Liang { /* MC1 Channel 1 */ 3948cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046), 3949cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 6, SKX_PCI_UNCORE_IMC, 4), 3950cd34cd97SKan Liang }, 3951cd34cd97SKan Liang { /* MC1 Channel 2 */ 3952cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a), 3953cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 2, SKX_PCI_UNCORE_IMC, 5), 3954cd34cd97SKan Liang }, 3955cd34cd97SKan Liang { /* M2M0 */ 3956cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066), 3957cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 0, SKX_PCI_UNCORE_M2M, 0), 3958cd34cd97SKan Liang }, 3959cd34cd97SKan Liang { /* M2M1 */ 3960cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066), 3961cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 0, SKX_PCI_UNCORE_M2M, 1), 3962cd34cd97SKan Liang }, 3963cd34cd97SKan Liang { /* UPI0 Link 0 */ 3964cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 3965cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, SKX_PCI_UNCORE_UPI, 0), 3966cd34cd97SKan Liang }, 3967cd34cd97SKan Liang { /* UPI0 Link 1 */ 3968cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 3969cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, SKX_PCI_UNCORE_UPI, 1), 3970cd34cd97SKan Liang }, 3971cd34cd97SKan Liang { /* UPI1 Link 2 */ 3972cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 3973cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, SKX_PCI_UNCORE_UPI, 2), 3974cd34cd97SKan Liang }, 3975cd34cd97SKan Liang { /* M2PCIe 0 */ 3976cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3977cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 1, SKX_PCI_UNCORE_M2PCIE, 0), 3978cd34cd97SKan Liang }, 3979cd34cd97SKan Liang { /* M2PCIe 1 */ 3980cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3981cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 1, SKX_PCI_UNCORE_M2PCIE, 1), 3982cd34cd97SKan Liang }, 3983cd34cd97SKan Liang { /* M2PCIe 2 */ 3984cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3985cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(23, 1, SKX_PCI_UNCORE_M2PCIE, 2), 3986cd34cd97SKan Liang }, 3987cd34cd97SKan Liang { /* M2PCIe 3 */ 3988cd34cd97SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 3989cd34cd97SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 5, SKX_PCI_UNCORE_M2PCIE, 3), 3990cd34cd97SKan Liang }, 3991cd34cd97SKan Liang { /* M3UPI0 Link 0 */ 39929d92cfeaSKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D), 39939d92cfeaSKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 1, SKX_PCI_UNCORE_M3UPI, 0), 3994cd34cd97SKan Liang }, 3995cd34cd97SKan Liang { /* M3UPI0 Link 1 */ 39969d92cfeaSKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204E), 39979d92cfeaSKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 2, SKX_PCI_UNCORE_M3UPI, 1), 3998cd34cd97SKan Liang }, 3999cd34cd97SKan Liang { /* M3UPI1 Link 2 */ 40009d92cfeaSKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D), 40019d92cfeaSKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 5, SKX_PCI_UNCORE_M3UPI, 2), 4002cd34cd97SKan Liang }, 4003cd34cd97SKan Liang { /* end: all zeroes */ } 4004cd34cd97SKan Liang }; 4005cd34cd97SKan Liang 4006cd34cd97SKan Liang 4007cd34cd97SKan Liang static struct pci_driver skx_uncore_pci_driver = { 4008cd34cd97SKan Liang .name = "skx_uncore", 4009cd34cd97SKan Liang .id_table = skx_uncore_pci_ids, 4010cd34cd97SKan Liang }; 4011cd34cd97SKan Liang 4012cd34cd97SKan Liang int skx_uncore_pci_init(void) 4013cd34cd97SKan Liang { 4014cd34cd97SKan Liang /* need to double check pci address */ 4015cd34cd97SKan Liang int ret = snbep_pci2phy_map_init(0x2014, SKX_CPUNODEID, SKX_GIDNIDMAP, false); 4016cd34cd97SKan Liang 4017cd34cd97SKan Liang if (ret) 4018cd34cd97SKan Liang return ret; 4019cd34cd97SKan Liang 4020cd34cd97SKan Liang uncore_pci_uncores = skx_pci_uncores; 4021cd34cd97SKan Liang uncore_pci_driver = &skx_uncore_pci_driver; 4022cd34cd97SKan Liang return 0; 4023cd34cd97SKan Liang } 4024cd34cd97SKan Liang 4025cd34cd97SKan Liang /* end of SKX uncore support */ 4026210cc5f9SKan Liang 4027210cc5f9SKan Liang /* SNR uncore support */ 4028210cc5f9SKan Liang 4029210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_ubox = { 4030210cc5f9SKan Liang .name = "ubox", 4031210cc5f9SKan Liang .num_counters = 2, 4032210cc5f9SKan Liang .num_boxes = 1, 4033210cc5f9SKan Liang .perf_ctr_bits = 48, 4034210cc5f9SKan Liang .fixed_ctr_bits = 48, 4035210cc5f9SKan Liang .perf_ctr = SNR_U_MSR_PMON_CTR0, 4036210cc5f9SKan Liang .event_ctl = SNR_U_MSR_PMON_CTL0, 4037210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4038210cc5f9SKan Liang .fixed_ctr = SNR_U_MSR_PMON_UCLK_FIXED_CTR, 4039210cc5f9SKan Liang .fixed_ctl = SNR_U_MSR_PMON_UCLK_FIXED_CTL, 4040210cc5f9SKan Liang .ops = &ivbep_uncore_msr_ops, 4041210cc5f9SKan Liang .format_group = &ivbep_uncore_format_group, 4042210cc5f9SKan Liang }; 4043210cc5f9SKan Liang 4044210cc5f9SKan Liang static struct attribute *snr_uncore_cha_formats_attr[] = { 4045210cc5f9SKan Liang &format_attr_event.attr, 4046210cc5f9SKan Liang &format_attr_umask_ext2.attr, 4047210cc5f9SKan Liang &format_attr_edge.attr, 4048210cc5f9SKan Liang &format_attr_tid_en.attr, 4049210cc5f9SKan Liang &format_attr_inv.attr, 4050210cc5f9SKan Liang &format_attr_thresh8.attr, 4051210cc5f9SKan Liang &format_attr_filter_tid5.attr, 4052210cc5f9SKan Liang NULL, 4053210cc5f9SKan Liang }; 4054210cc5f9SKan Liang static const struct attribute_group snr_uncore_chabox_format_group = { 4055210cc5f9SKan Liang .name = "format", 4056210cc5f9SKan Liang .attrs = snr_uncore_cha_formats_attr, 4057210cc5f9SKan Liang }; 4058210cc5f9SKan Liang 4059210cc5f9SKan Liang static int snr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 4060210cc5f9SKan Liang { 4061210cc5f9SKan Liang struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 4062210cc5f9SKan Liang 4063210cc5f9SKan Liang reg1->reg = SNR_C0_MSR_PMON_BOX_FILTER0 + 4064210cc5f9SKan Liang box->pmu->type->msr_offset * box->pmu->pmu_idx; 4065210cc5f9SKan Liang reg1->config = event->attr.config1 & SKX_CHA_MSR_PMON_BOX_FILTER_TID; 4066210cc5f9SKan Liang reg1->idx = 0; 4067210cc5f9SKan Liang 4068210cc5f9SKan Liang return 0; 4069210cc5f9SKan Liang } 4070210cc5f9SKan Liang 4071210cc5f9SKan Liang static void snr_cha_enable_event(struct intel_uncore_box *box, 4072210cc5f9SKan Liang struct perf_event *event) 4073210cc5f9SKan Liang { 4074210cc5f9SKan Liang struct hw_perf_event *hwc = &event->hw; 4075210cc5f9SKan Liang struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 4076210cc5f9SKan Liang 4077210cc5f9SKan Liang if (reg1->idx != EXTRA_REG_NONE) 4078210cc5f9SKan Liang wrmsrl(reg1->reg, reg1->config); 4079210cc5f9SKan Liang 4080210cc5f9SKan Liang wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 4081210cc5f9SKan Liang } 4082210cc5f9SKan Liang 4083210cc5f9SKan Liang static struct intel_uncore_ops snr_uncore_chabox_ops = { 4084210cc5f9SKan Liang .init_box = ivbep_uncore_msr_init_box, 4085210cc5f9SKan Liang .disable_box = snbep_uncore_msr_disable_box, 4086210cc5f9SKan Liang .enable_box = snbep_uncore_msr_enable_box, 4087210cc5f9SKan Liang .disable_event = snbep_uncore_msr_disable_event, 4088210cc5f9SKan Liang .enable_event = snr_cha_enable_event, 4089210cc5f9SKan Liang .read_counter = uncore_msr_read_counter, 4090210cc5f9SKan Liang .hw_config = snr_cha_hw_config, 4091210cc5f9SKan Liang }; 4092210cc5f9SKan Liang 4093210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_chabox = { 4094210cc5f9SKan Liang .name = "cha", 4095210cc5f9SKan Liang .num_counters = 4, 4096210cc5f9SKan Liang .num_boxes = 6, 4097210cc5f9SKan Liang .perf_ctr_bits = 48, 4098210cc5f9SKan Liang .event_ctl = SNR_CHA_MSR_PMON_CTL0, 4099210cc5f9SKan Liang .perf_ctr = SNR_CHA_MSR_PMON_CTR0, 4100210cc5f9SKan Liang .box_ctl = SNR_CHA_MSR_PMON_BOX_CTL, 4101210cc5f9SKan Liang .msr_offset = HSWEP_CBO_MSR_OFFSET, 4102210cc5f9SKan Liang .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 4103210cc5f9SKan Liang .event_mask_ext = SNR_CHA_RAW_EVENT_MASK_EXT, 4104210cc5f9SKan Liang .ops = &snr_uncore_chabox_ops, 4105210cc5f9SKan Liang .format_group = &snr_uncore_chabox_format_group, 4106210cc5f9SKan Liang }; 4107210cc5f9SKan Liang 4108210cc5f9SKan Liang static struct attribute *snr_uncore_iio_formats_attr[] = { 4109210cc5f9SKan Liang &format_attr_event.attr, 4110210cc5f9SKan Liang &format_attr_umask.attr, 4111210cc5f9SKan Liang &format_attr_edge.attr, 4112210cc5f9SKan Liang &format_attr_inv.attr, 4113210cc5f9SKan Liang &format_attr_thresh9.attr, 4114210cc5f9SKan Liang &format_attr_ch_mask2.attr, 4115210cc5f9SKan Liang &format_attr_fc_mask2.attr, 4116210cc5f9SKan Liang NULL, 4117210cc5f9SKan Liang }; 4118210cc5f9SKan Liang 4119210cc5f9SKan Liang static const struct attribute_group snr_uncore_iio_format_group = { 4120210cc5f9SKan Liang .name = "format", 4121210cc5f9SKan Liang .attrs = snr_uncore_iio_formats_attr, 4122210cc5f9SKan Liang }; 4123210cc5f9SKan Liang 4124210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_iio = { 4125210cc5f9SKan Liang .name = "iio", 4126210cc5f9SKan Liang .num_counters = 4, 4127210cc5f9SKan Liang .num_boxes = 5, 4128210cc5f9SKan Liang .perf_ctr_bits = 48, 4129210cc5f9SKan Liang .event_ctl = SNR_IIO_MSR_PMON_CTL0, 4130210cc5f9SKan Liang .perf_ctr = SNR_IIO_MSR_PMON_CTR0, 4131210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4132210cc5f9SKan Liang .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT, 4133210cc5f9SKan Liang .box_ctl = SNR_IIO_MSR_PMON_BOX_CTL, 4134210cc5f9SKan Liang .msr_offset = SNR_IIO_MSR_OFFSET, 4135210cc5f9SKan Liang .ops = &ivbep_uncore_msr_ops, 4136210cc5f9SKan Liang .format_group = &snr_uncore_iio_format_group, 4137210cc5f9SKan Liang }; 4138210cc5f9SKan Liang 4139210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_irp = { 4140210cc5f9SKan Liang .name = "irp", 4141210cc5f9SKan Liang .num_counters = 2, 4142210cc5f9SKan Liang .num_boxes = 5, 4143210cc5f9SKan Liang .perf_ctr_bits = 48, 4144210cc5f9SKan Liang .event_ctl = SNR_IRP0_MSR_PMON_CTL0, 4145210cc5f9SKan Liang .perf_ctr = SNR_IRP0_MSR_PMON_CTR0, 4146210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4147210cc5f9SKan Liang .box_ctl = SNR_IRP0_MSR_PMON_BOX_CTL, 4148210cc5f9SKan Liang .msr_offset = SNR_IRP_MSR_OFFSET, 4149210cc5f9SKan Liang .ops = &ivbep_uncore_msr_ops, 4150210cc5f9SKan Liang .format_group = &ivbep_uncore_format_group, 4151210cc5f9SKan Liang }; 4152210cc5f9SKan Liang 4153210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_m2pcie = { 4154210cc5f9SKan Liang .name = "m2pcie", 4155210cc5f9SKan Liang .num_counters = 4, 4156210cc5f9SKan Liang .num_boxes = 5, 4157210cc5f9SKan Liang .perf_ctr_bits = 48, 4158210cc5f9SKan Liang .event_ctl = SNR_M2PCIE_MSR_PMON_CTL0, 4159210cc5f9SKan Liang .perf_ctr = SNR_M2PCIE_MSR_PMON_CTR0, 4160210cc5f9SKan Liang .box_ctl = SNR_M2PCIE_MSR_PMON_BOX_CTL, 4161210cc5f9SKan Liang .msr_offset = SNR_M2PCIE_MSR_OFFSET, 4162210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4163210cc5f9SKan Liang .ops = &ivbep_uncore_msr_ops, 4164210cc5f9SKan Liang .format_group = &ivbep_uncore_format_group, 4165210cc5f9SKan Liang }; 4166210cc5f9SKan Liang 4167210cc5f9SKan Liang static int snr_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 4168210cc5f9SKan Liang { 4169210cc5f9SKan Liang struct hw_perf_event *hwc = &event->hw; 4170210cc5f9SKan Liang struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 4171210cc5f9SKan Liang int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 4172210cc5f9SKan Liang 4173210cc5f9SKan Liang if (ev_sel >= 0xb && ev_sel <= 0xe) { 4174210cc5f9SKan Liang reg1->reg = SNR_PCU_MSR_PMON_BOX_FILTER; 4175210cc5f9SKan Liang reg1->idx = ev_sel - 0xb; 4176210cc5f9SKan Liang reg1->config = event->attr.config1 & (0xff << reg1->idx); 4177210cc5f9SKan Liang } 4178210cc5f9SKan Liang return 0; 4179210cc5f9SKan Liang } 4180210cc5f9SKan Liang 4181210cc5f9SKan Liang static struct intel_uncore_ops snr_uncore_pcu_ops = { 4182210cc5f9SKan Liang IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 4183210cc5f9SKan Liang .hw_config = snr_pcu_hw_config, 4184210cc5f9SKan Liang .get_constraint = snbep_pcu_get_constraint, 4185210cc5f9SKan Liang .put_constraint = snbep_pcu_put_constraint, 4186210cc5f9SKan Liang }; 4187210cc5f9SKan Liang 4188210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_pcu = { 4189210cc5f9SKan Liang .name = "pcu", 4190210cc5f9SKan Liang .num_counters = 4, 4191210cc5f9SKan Liang .num_boxes = 1, 4192210cc5f9SKan Liang .perf_ctr_bits = 48, 4193210cc5f9SKan Liang .perf_ctr = SNR_PCU_MSR_PMON_CTR0, 4194210cc5f9SKan Liang .event_ctl = SNR_PCU_MSR_PMON_CTL0, 4195210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4196210cc5f9SKan Liang .box_ctl = SNR_PCU_MSR_PMON_BOX_CTL, 4197210cc5f9SKan Liang .num_shared_regs = 1, 4198210cc5f9SKan Liang .ops = &snr_uncore_pcu_ops, 4199210cc5f9SKan Liang .format_group = &skx_uncore_pcu_format_group, 4200210cc5f9SKan Liang }; 4201210cc5f9SKan Liang 4202210cc5f9SKan Liang enum perf_uncore_snr_iio_freerunning_type_id { 4203210cc5f9SKan Liang SNR_IIO_MSR_IOCLK, 4204210cc5f9SKan Liang SNR_IIO_MSR_BW_IN, 4205210cc5f9SKan Liang 4206210cc5f9SKan Liang SNR_IIO_FREERUNNING_TYPE_MAX, 4207210cc5f9SKan Liang }; 4208210cc5f9SKan Liang 4209210cc5f9SKan Liang static struct freerunning_counters snr_iio_freerunning[] = { 4210210cc5f9SKan Liang [SNR_IIO_MSR_IOCLK] = { 0x1eac, 0x1, 0x10, 1, 48 }, 4211210cc5f9SKan Liang [SNR_IIO_MSR_BW_IN] = { 0x1f00, 0x1, 0x10, 8, 48 }, 4212210cc5f9SKan Liang }; 4213210cc5f9SKan Liang 4214210cc5f9SKan Liang static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = { 4215210cc5f9SKan Liang /* Free-Running IIO CLOCKS Counter */ 4216210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"), 4217210cc5f9SKan Liang /* Free-Running IIO BANDWIDTH IN Counters */ 4218210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"), 4219210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.814697266e-6"), 4220210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"), 4221210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"), 4222210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.814697266e-6"), 4223210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"), 4224210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"), 4225210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.814697266e-6"), 4226210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"), 4227210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"), 4228210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.814697266e-6"), 4229210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"), 4230210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port4, "event=0xff,umask=0x24"), 4231210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale, "3.814697266e-6"), 4232210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit, "MiB"), 4233210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port5, "event=0xff,umask=0x25"), 4234210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale, "3.814697266e-6"), 4235210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit, "MiB"), 4236210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port6, "event=0xff,umask=0x26"), 4237210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale, "3.814697266e-6"), 4238210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit, "MiB"), 4239210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port7, "event=0xff,umask=0x27"), 4240210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale, "3.814697266e-6"), 4241210cc5f9SKan Liang INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit, "MiB"), 4242210cc5f9SKan Liang { /* end: all zeroes */ }, 4243210cc5f9SKan Liang }; 4244210cc5f9SKan Liang 4245210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_iio_free_running = { 4246210cc5f9SKan Liang .name = "iio_free_running", 4247210cc5f9SKan Liang .num_counters = 9, 4248210cc5f9SKan Liang .num_boxes = 5, 4249210cc5f9SKan Liang .num_freerunning_types = SNR_IIO_FREERUNNING_TYPE_MAX, 4250210cc5f9SKan Liang .freerunning = snr_iio_freerunning, 4251210cc5f9SKan Liang .ops = &skx_uncore_iio_freerunning_ops, 4252210cc5f9SKan Liang .event_descs = snr_uncore_iio_freerunning_events, 4253210cc5f9SKan Liang .format_group = &skx_uncore_iio_freerunning_format_group, 4254210cc5f9SKan Liang }; 4255210cc5f9SKan Liang 4256210cc5f9SKan Liang static struct intel_uncore_type *snr_msr_uncores[] = { 4257210cc5f9SKan Liang &snr_uncore_ubox, 4258210cc5f9SKan Liang &snr_uncore_chabox, 4259210cc5f9SKan Liang &snr_uncore_iio, 4260210cc5f9SKan Liang &snr_uncore_irp, 4261210cc5f9SKan Liang &snr_uncore_m2pcie, 4262210cc5f9SKan Liang &snr_uncore_pcu, 4263210cc5f9SKan Liang &snr_uncore_iio_free_running, 4264210cc5f9SKan Liang NULL, 4265210cc5f9SKan Liang }; 4266210cc5f9SKan Liang 4267210cc5f9SKan Liang void snr_uncore_cpu_init(void) 4268210cc5f9SKan Liang { 4269210cc5f9SKan Liang uncore_msr_uncores = snr_msr_uncores; 4270210cc5f9SKan Liang } 4271210cc5f9SKan Liang 4272210cc5f9SKan Liang static void snr_m2m_uncore_pci_init_box(struct intel_uncore_box *box) 4273210cc5f9SKan Liang { 4274210cc5f9SKan Liang struct pci_dev *pdev = box->pci_dev; 4275210cc5f9SKan Liang int box_ctl = uncore_pci_box_ctl(box); 4276210cc5f9SKan Liang 4277210cc5f9SKan Liang __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 4278210cc5f9SKan Liang pci_write_config_dword(pdev, box_ctl, IVBEP_PMON_BOX_CTL_INT); 4279210cc5f9SKan Liang } 4280210cc5f9SKan Liang 4281210cc5f9SKan Liang static struct intel_uncore_ops snr_m2m_uncore_pci_ops = { 4282210cc5f9SKan Liang .init_box = snr_m2m_uncore_pci_init_box, 4283210cc5f9SKan Liang .disable_box = snbep_uncore_pci_disable_box, 4284210cc5f9SKan Liang .enable_box = snbep_uncore_pci_enable_box, 4285210cc5f9SKan Liang .disable_event = snbep_uncore_pci_disable_event, 4286210cc5f9SKan Liang .enable_event = snbep_uncore_pci_enable_event, 4287210cc5f9SKan Liang .read_counter = snbep_uncore_pci_read_counter, 4288210cc5f9SKan Liang }; 4289210cc5f9SKan Liang 4290210cc5f9SKan Liang static struct attribute *snr_m2m_uncore_formats_attr[] = { 4291210cc5f9SKan Liang &format_attr_event.attr, 4292210cc5f9SKan Liang &format_attr_umask_ext3.attr, 4293210cc5f9SKan Liang &format_attr_edge.attr, 4294210cc5f9SKan Liang &format_attr_inv.attr, 4295210cc5f9SKan Liang &format_attr_thresh8.attr, 4296210cc5f9SKan Liang NULL, 4297210cc5f9SKan Liang }; 4298210cc5f9SKan Liang 4299210cc5f9SKan Liang static const struct attribute_group snr_m2m_uncore_format_group = { 4300210cc5f9SKan Liang .name = "format", 4301210cc5f9SKan Liang .attrs = snr_m2m_uncore_formats_attr, 4302210cc5f9SKan Liang }; 4303210cc5f9SKan Liang 4304210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_m2m = { 4305210cc5f9SKan Liang .name = "m2m", 4306210cc5f9SKan Liang .num_counters = 4, 4307210cc5f9SKan Liang .num_boxes = 1, 4308210cc5f9SKan Liang .perf_ctr_bits = 48, 4309210cc5f9SKan Liang .perf_ctr = SNR_M2M_PCI_PMON_CTR0, 4310210cc5f9SKan Liang .event_ctl = SNR_M2M_PCI_PMON_CTL0, 4311210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4312210cc5f9SKan Liang .event_mask_ext = SNR_M2M_PCI_PMON_UMASK_EXT, 4313210cc5f9SKan Liang .box_ctl = SNR_M2M_PCI_PMON_BOX_CTL, 4314210cc5f9SKan Liang .ops = &snr_m2m_uncore_pci_ops, 4315210cc5f9SKan Liang .format_group = &snr_m2m_uncore_format_group, 4316210cc5f9SKan Liang }; 4317210cc5f9SKan Liang 4318210cc5f9SKan Liang static struct intel_uncore_type snr_uncore_pcie3 = { 4319210cc5f9SKan Liang .name = "pcie3", 4320210cc5f9SKan Liang .num_counters = 4, 4321210cc5f9SKan Liang .num_boxes = 1, 4322210cc5f9SKan Liang .perf_ctr_bits = 48, 4323210cc5f9SKan Liang .perf_ctr = SNR_PCIE3_PCI_PMON_CTR0, 4324210cc5f9SKan Liang .event_ctl = SNR_PCIE3_PCI_PMON_CTL0, 4325210cc5f9SKan Liang .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4326210cc5f9SKan Liang .box_ctl = SNR_PCIE3_PCI_PMON_BOX_CTL, 4327210cc5f9SKan Liang .ops = &ivbep_uncore_pci_ops, 4328210cc5f9SKan Liang .format_group = &ivbep_uncore_format_group, 4329210cc5f9SKan Liang }; 4330210cc5f9SKan Liang 4331210cc5f9SKan Liang enum { 4332210cc5f9SKan Liang SNR_PCI_UNCORE_M2M, 4333210cc5f9SKan Liang SNR_PCI_UNCORE_PCIE3, 4334210cc5f9SKan Liang }; 4335210cc5f9SKan Liang 4336210cc5f9SKan Liang static struct intel_uncore_type *snr_pci_uncores[] = { 4337210cc5f9SKan Liang [SNR_PCI_UNCORE_M2M] = &snr_uncore_m2m, 4338210cc5f9SKan Liang [SNR_PCI_UNCORE_PCIE3] = &snr_uncore_pcie3, 4339210cc5f9SKan Liang NULL, 4340210cc5f9SKan Liang }; 4341210cc5f9SKan Liang 4342210cc5f9SKan Liang static const struct pci_device_id snr_uncore_pci_ids[] = { 4343210cc5f9SKan Liang { /* M2M */ 4344210cc5f9SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a), 4345210cc5f9SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, SNR_PCI_UNCORE_M2M, 0), 4346210cc5f9SKan Liang }, 4347210cc5f9SKan Liang { /* PCIe3 */ 4348210cc5f9SKan Liang PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x334a), 4349210cc5f9SKan Liang .driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 0, SNR_PCI_UNCORE_PCIE3, 0), 4350210cc5f9SKan Liang }, 4351210cc5f9SKan Liang { /* end: all zeroes */ } 4352210cc5f9SKan Liang }; 4353210cc5f9SKan Liang 4354210cc5f9SKan Liang static struct pci_driver snr_uncore_pci_driver = { 4355210cc5f9SKan Liang .name = "snr_uncore", 4356210cc5f9SKan Liang .id_table = snr_uncore_pci_ids, 4357210cc5f9SKan Liang }; 4358210cc5f9SKan Liang 4359210cc5f9SKan Liang int snr_uncore_pci_init(void) 4360210cc5f9SKan Liang { 4361210cc5f9SKan Liang /* SNR UBOX DID */ 4362210cc5f9SKan Liang int ret = snbep_pci2phy_map_init(0x3460, SKX_CPUNODEID, 4363210cc5f9SKan Liang SKX_GIDNIDMAP, true); 4364210cc5f9SKan Liang 4365210cc5f9SKan Liang if (ret) 4366210cc5f9SKan Liang return ret; 4367210cc5f9SKan Liang 4368210cc5f9SKan Liang uncore_pci_uncores = snr_pci_uncores; 4369210cc5f9SKan Liang uncore_pci_driver = &snr_uncore_pci_driver; 4370210cc5f9SKan Liang return 0; 4371210cc5f9SKan Liang } 4372210cc5f9SKan Liang 4373210cc5f9SKan Liang /* end of SNR uncore support */ 4374