1 // SPDX-License-Identifier: GPL-2.0 2 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */ 3 #include "uncore.h" 4 5 /* Uncore IMC PCI IDs */ 6 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 7 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 8 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150 9 #define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00 10 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04 11 #define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604 12 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904 13 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c 14 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900 15 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910 16 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f 17 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f 18 #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c 19 #define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904 20 #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914 21 #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f 22 #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f 23 #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc 24 #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0 25 #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10 26 #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4 27 #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f 28 #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f 29 #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2 30 #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30 31 #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18 32 #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6 33 #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31 34 #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33 35 #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca 36 #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32 37 38 /* SNB event control */ 39 #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff 40 #define SNB_UNC_CTL_UMASK_MASK 0x0000ff00 41 #define SNB_UNC_CTL_EDGE_DET (1 << 18) 42 #define SNB_UNC_CTL_EN (1 << 22) 43 #define SNB_UNC_CTL_INVERT (1 << 23) 44 #define SNB_UNC_CTL_CMASK_MASK 0x1f000000 45 #define NHM_UNC_CTL_CMASK_MASK 0xff000000 46 #define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0) 47 48 #define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ 49 SNB_UNC_CTL_UMASK_MASK | \ 50 SNB_UNC_CTL_EDGE_DET | \ 51 SNB_UNC_CTL_INVERT | \ 52 SNB_UNC_CTL_CMASK_MASK) 53 54 #define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ 55 SNB_UNC_CTL_UMASK_MASK | \ 56 SNB_UNC_CTL_EDGE_DET | \ 57 SNB_UNC_CTL_INVERT | \ 58 NHM_UNC_CTL_CMASK_MASK) 59 60 /* SNB global control register */ 61 #define SNB_UNC_PERF_GLOBAL_CTL 0x391 62 #define SNB_UNC_FIXED_CTR_CTRL 0x394 63 #define SNB_UNC_FIXED_CTR 0x395 64 65 /* SNB uncore global control */ 66 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1) 67 #define SNB_UNC_GLOBAL_CTL_EN (1 << 29) 68 69 /* SNB Cbo register */ 70 #define SNB_UNC_CBO_0_PERFEVTSEL0 0x700 71 #define SNB_UNC_CBO_0_PER_CTR0 0x706 72 #define SNB_UNC_CBO_MSR_OFFSET 0x10 73 74 /* SNB ARB register */ 75 #define SNB_UNC_ARB_PER_CTR0 0x3b0 76 #define SNB_UNC_ARB_PERFEVTSEL0 0x3b2 77 #define SNB_UNC_ARB_MSR_OFFSET 0x10 78 79 /* NHM global control register */ 80 #define NHM_UNC_PERF_GLOBAL_CTL 0x391 81 #define NHM_UNC_FIXED_CTR 0x394 82 #define NHM_UNC_FIXED_CTR_CTRL 0x395 83 84 /* NHM uncore global control */ 85 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1) 86 #define NHM_UNC_GLOBAL_CTL_EN_FC (1ULL << 32) 87 88 /* NHM uncore register */ 89 #define NHM_UNC_PERFEVTSEL0 0x3c0 90 #define NHM_UNC_UNCORE_PMC0 0x3b0 91 92 /* SKL uncore global control */ 93 #define SKL_UNC_PERF_GLOBAL_CTL 0xe01 94 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1) 95 96 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 97 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 98 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 99 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 100 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28"); 101 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31"); 102 103 /* Sandy Bridge uncore support */ 104 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 105 { 106 struct hw_perf_event *hwc = &event->hw; 107 108 if (hwc->idx < UNCORE_PMC_IDX_FIXED) 109 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 110 else 111 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); 112 } 113 114 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) 115 { 116 wrmsrl(event->hw.config_base, 0); 117 } 118 119 static void snb_uncore_msr_init_box(struct intel_uncore_box *box) 120 { 121 if (box->pmu->pmu_idx == 0) { 122 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 123 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); 124 } 125 } 126 127 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box) 128 { 129 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 130 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); 131 } 132 133 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box) 134 { 135 if (box->pmu->pmu_idx == 0) 136 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); 137 } 138 139 static struct uncore_event_desc snb_uncore_events[] = { 140 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 141 { /* end: all zeroes */ }, 142 }; 143 144 static struct attribute *snb_uncore_formats_attr[] = { 145 &format_attr_event.attr, 146 &format_attr_umask.attr, 147 &format_attr_edge.attr, 148 &format_attr_inv.attr, 149 &format_attr_cmask5.attr, 150 NULL, 151 }; 152 153 static const struct attribute_group snb_uncore_format_group = { 154 .name = "format", 155 .attrs = snb_uncore_formats_attr, 156 }; 157 158 static struct intel_uncore_ops snb_uncore_msr_ops = { 159 .init_box = snb_uncore_msr_init_box, 160 .enable_box = snb_uncore_msr_enable_box, 161 .exit_box = snb_uncore_msr_exit_box, 162 .disable_event = snb_uncore_msr_disable_event, 163 .enable_event = snb_uncore_msr_enable_event, 164 .read_counter = uncore_msr_read_counter, 165 }; 166 167 static struct event_constraint snb_uncore_arb_constraints[] = { 168 UNCORE_EVENT_CONSTRAINT(0x80, 0x1), 169 UNCORE_EVENT_CONSTRAINT(0x83, 0x1), 170 EVENT_CONSTRAINT_END 171 }; 172 173 static struct intel_uncore_type snb_uncore_cbox = { 174 .name = "cbox", 175 .num_counters = 2, 176 .num_boxes = 4, 177 .perf_ctr_bits = 44, 178 .fixed_ctr_bits = 48, 179 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0, 180 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0, 181 .fixed_ctr = SNB_UNC_FIXED_CTR, 182 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL, 183 .single_fixed = 1, 184 .event_mask = SNB_UNC_RAW_EVENT_MASK, 185 .msr_offset = SNB_UNC_CBO_MSR_OFFSET, 186 .ops = &snb_uncore_msr_ops, 187 .format_group = &snb_uncore_format_group, 188 .event_descs = snb_uncore_events, 189 }; 190 191 static struct intel_uncore_type snb_uncore_arb = { 192 .name = "arb", 193 .num_counters = 2, 194 .num_boxes = 1, 195 .perf_ctr_bits = 44, 196 .perf_ctr = SNB_UNC_ARB_PER_CTR0, 197 .event_ctl = SNB_UNC_ARB_PERFEVTSEL0, 198 .event_mask = SNB_UNC_RAW_EVENT_MASK, 199 .msr_offset = SNB_UNC_ARB_MSR_OFFSET, 200 .constraints = snb_uncore_arb_constraints, 201 .ops = &snb_uncore_msr_ops, 202 .format_group = &snb_uncore_format_group, 203 }; 204 205 static struct intel_uncore_type *snb_msr_uncores[] = { 206 &snb_uncore_cbox, 207 &snb_uncore_arb, 208 NULL, 209 }; 210 211 void snb_uncore_cpu_init(void) 212 { 213 uncore_msr_uncores = snb_msr_uncores; 214 if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 215 snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 216 } 217 218 static void skl_uncore_msr_init_box(struct intel_uncore_box *box) 219 { 220 if (box->pmu->pmu_idx == 0) { 221 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 222 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 223 } 224 225 /* The 8th CBOX has different MSR space */ 226 if (box->pmu->pmu_idx == 7) 227 __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags); 228 } 229 230 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) 231 { 232 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 233 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 234 } 235 236 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) 237 { 238 if (box->pmu->pmu_idx == 0) 239 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); 240 } 241 242 static struct intel_uncore_ops skl_uncore_msr_ops = { 243 .init_box = skl_uncore_msr_init_box, 244 .enable_box = skl_uncore_msr_enable_box, 245 .exit_box = skl_uncore_msr_exit_box, 246 .disable_event = snb_uncore_msr_disable_event, 247 .enable_event = snb_uncore_msr_enable_event, 248 .read_counter = uncore_msr_read_counter, 249 }; 250 251 static struct intel_uncore_type skl_uncore_cbox = { 252 .name = "cbox", 253 .num_counters = 4, 254 .num_boxes = 8, 255 .perf_ctr_bits = 44, 256 .fixed_ctr_bits = 48, 257 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0, 258 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0, 259 .fixed_ctr = SNB_UNC_FIXED_CTR, 260 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL, 261 .single_fixed = 1, 262 .event_mask = SNB_UNC_RAW_EVENT_MASK, 263 .msr_offset = SNB_UNC_CBO_MSR_OFFSET, 264 .ops = &skl_uncore_msr_ops, 265 .format_group = &snb_uncore_format_group, 266 .event_descs = snb_uncore_events, 267 }; 268 269 static struct intel_uncore_type *skl_msr_uncores[] = { 270 &skl_uncore_cbox, 271 &snb_uncore_arb, 272 NULL, 273 }; 274 275 void skl_uncore_cpu_init(void) 276 { 277 uncore_msr_uncores = skl_msr_uncores; 278 if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 279 skl_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 280 snb_uncore_arb.ops = &skl_uncore_msr_ops; 281 } 282 283 enum { 284 SNB_PCI_UNCORE_IMC, 285 }; 286 287 static struct uncore_event_desc snb_uncore_imc_events[] = { 288 INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"), 289 INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"), 290 INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"), 291 292 INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"), 293 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"), 294 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"), 295 296 { /* end: all zeroes */ }, 297 }; 298 299 #define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff 300 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48 301 302 /* page size multiple covering all config regs */ 303 #define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000 304 305 #define SNB_UNCORE_PCI_IMC_DATA_READS 0x1 306 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050 307 #define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2 308 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054 309 #define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE 310 311 enum perf_snb_uncore_imc_freerunning_types { 312 SNB_PCI_UNCORE_IMC_DATA = 0, 313 SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, 314 }; 315 316 static struct freerunning_counters snb_uncore_imc_freerunning[] = { 317 [SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 }, 318 }; 319 320 static struct attribute *snb_uncore_imc_formats_attr[] = { 321 &format_attr_event.attr, 322 NULL, 323 }; 324 325 static const struct attribute_group snb_uncore_imc_format_group = { 326 .name = "format", 327 .attrs = snb_uncore_imc_formats_attr, 328 }; 329 330 static void snb_uncore_imc_init_box(struct intel_uncore_box *box) 331 { 332 struct pci_dev *pdev = box->pci_dev; 333 int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET; 334 resource_size_t addr; 335 u32 pci_dword; 336 337 pci_read_config_dword(pdev, where, &pci_dword); 338 addr = pci_dword; 339 340 #ifdef CONFIG_PHYS_ADDR_T_64BIT 341 pci_read_config_dword(pdev, where + 4, &pci_dword); 342 addr |= ((resource_size_t)pci_dword << 32); 343 #endif 344 345 addr &= ~(PAGE_SIZE - 1); 346 347 box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE); 348 box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL; 349 } 350 351 static void snb_uncore_imc_exit_box(struct intel_uncore_box *box) 352 { 353 iounmap(box->io_addr); 354 } 355 356 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box) 357 {} 358 359 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box) 360 {} 361 362 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event) 363 {} 364 365 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event) 366 {} 367 368 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event) 369 { 370 struct hw_perf_event *hwc = &event->hw; 371 372 return (u64)*(unsigned int *)(box->io_addr + hwc->event_base); 373 } 374 375 /* 376 * Keep the custom event_init() function compatible with old event 377 * encoding for free running counters. 378 */ 379 static int snb_uncore_imc_event_init(struct perf_event *event) 380 { 381 struct intel_uncore_pmu *pmu; 382 struct intel_uncore_box *box; 383 struct hw_perf_event *hwc = &event->hw; 384 u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK; 385 int idx, base; 386 387 if (event->attr.type != event->pmu->type) 388 return -ENOENT; 389 390 pmu = uncore_event_to_pmu(event); 391 /* no device found for this pmu */ 392 if (pmu->func_id < 0) 393 return -ENOENT; 394 395 /* Sampling not supported yet */ 396 if (hwc->sample_period) 397 return -EINVAL; 398 399 /* unsupported modes and filters */ 400 if (event->attr.sample_period) /* no sampling */ 401 return -EINVAL; 402 403 /* 404 * Place all uncore events for a particular physical package 405 * onto a single cpu 406 */ 407 if (event->cpu < 0) 408 return -EINVAL; 409 410 /* check only supported bits are set */ 411 if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK) 412 return -EINVAL; 413 414 box = uncore_pmu_to_box(pmu, event->cpu); 415 if (!box || box->cpu < 0) 416 return -EINVAL; 417 418 event->cpu = box->cpu; 419 event->pmu_private = box; 420 421 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; 422 423 event->hw.idx = -1; 424 event->hw.last_tag = ~0ULL; 425 event->hw.extra_reg.idx = EXTRA_REG_NONE; 426 event->hw.branch_reg.idx = EXTRA_REG_NONE; 427 /* 428 * check event is known (whitelist, determines counter) 429 */ 430 switch (cfg) { 431 case SNB_UNCORE_PCI_IMC_DATA_READS: 432 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE; 433 idx = UNCORE_PMC_IDX_FREERUNNING; 434 break; 435 case SNB_UNCORE_PCI_IMC_DATA_WRITES: 436 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE; 437 idx = UNCORE_PMC_IDX_FREERUNNING; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 /* must be done before validate_group */ 444 event->hw.event_base = base; 445 event->hw.idx = idx; 446 447 /* Convert to standard encoding format for freerunning counters */ 448 event->hw.config = ((cfg - 1) << 8) | 0x10ff; 449 450 /* no group validation needed, we have free running counters */ 451 452 return 0; 453 } 454 455 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event) 456 { 457 return 0; 458 } 459 460 int snb_pci2phy_map_init(int devid) 461 { 462 struct pci_dev *dev = NULL; 463 struct pci2phy_map *map; 464 int bus, segment; 465 466 dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev); 467 if (!dev) 468 return -ENOTTY; 469 470 bus = dev->bus->number; 471 segment = pci_domain_nr(dev->bus); 472 473 raw_spin_lock(&pci2phy_map_lock); 474 map = __find_pci2phy_map(segment); 475 if (!map) { 476 raw_spin_unlock(&pci2phy_map_lock); 477 pci_dev_put(dev); 478 return -ENOMEM; 479 } 480 map->pbus_to_physid[bus] = 0; 481 raw_spin_unlock(&pci2phy_map_lock); 482 483 pci_dev_put(dev); 484 485 return 0; 486 } 487 488 static struct pmu snb_uncore_imc_pmu = { 489 .task_ctx_nr = perf_invalid_context, 490 .event_init = snb_uncore_imc_event_init, 491 .add = uncore_pmu_event_add, 492 .del = uncore_pmu_event_del, 493 .start = uncore_pmu_event_start, 494 .stop = uncore_pmu_event_stop, 495 .read = uncore_pmu_event_read, 496 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 497 }; 498 499 static struct intel_uncore_ops snb_uncore_imc_ops = { 500 .init_box = snb_uncore_imc_init_box, 501 .exit_box = snb_uncore_imc_exit_box, 502 .enable_box = snb_uncore_imc_enable_box, 503 .disable_box = snb_uncore_imc_disable_box, 504 .disable_event = snb_uncore_imc_disable_event, 505 .enable_event = snb_uncore_imc_enable_event, 506 .hw_config = snb_uncore_imc_hw_config, 507 .read_counter = snb_uncore_imc_read_counter, 508 }; 509 510 static struct intel_uncore_type snb_uncore_imc = { 511 .name = "imc", 512 .num_counters = 2, 513 .num_boxes = 1, 514 .num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, 515 .freerunning = snb_uncore_imc_freerunning, 516 .event_descs = snb_uncore_imc_events, 517 .format_group = &snb_uncore_imc_format_group, 518 .ops = &snb_uncore_imc_ops, 519 .pmu = &snb_uncore_imc_pmu, 520 }; 521 522 static struct intel_uncore_type *snb_pci_uncores[] = { 523 [SNB_PCI_UNCORE_IMC] = &snb_uncore_imc, 524 NULL, 525 }; 526 527 static const struct pci_device_id snb_uncore_pci_ids[] = { 528 { /* IMC */ 529 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC), 530 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 531 }, 532 { /* end: all zeroes */ }, 533 }; 534 535 static const struct pci_device_id ivb_uncore_pci_ids[] = { 536 { /* IMC */ 537 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC), 538 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 539 }, 540 { /* IMC */ 541 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC), 542 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 543 }, 544 { /* end: all zeroes */ }, 545 }; 546 547 static const struct pci_device_id hsw_uncore_pci_ids[] = { 548 { /* IMC */ 549 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC), 550 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 551 }, 552 { /* IMC */ 553 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC), 554 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 555 }, 556 { /* end: all zeroes */ }, 557 }; 558 559 static const struct pci_device_id bdw_uncore_pci_ids[] = { 560 { /* IMC */ 561 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC), 562 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 563 }, 564 { /* end: all zeroes */ }, 565 }; 566 567 static const struct pci_device_id skl_uncore_pci_ids[] = { 568 { /* IMC */ 569 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_Y_IMC), 570 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 571 }, 572 { /* IMC */ 573 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_U_IMC), 574 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 575 }, 576 { /* IMC */ 577 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HD_IMC), 578 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 579 }, 580 { /* IMC */ 581 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HQ_IMC), 582 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 583 }, 584 { /* IMC */ 585 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SD_IMC), 586 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 587 }, 588 { /* IMC */ 589 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC), 590 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 591 }, 592 { /* IMC */ 593 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC), 594 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 595 }, 596 { /* IMC */ 597 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC), 598 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 599 }, 600 { /* IMC */ 601 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC), 602 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 603 }, 604 { /* IMC */ 605 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC), 606 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 607 }, 608 { /* IMC */ 609 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC), 610 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 611 }, 612 { /* IMC */ 613 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC), 614 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 615 }, 616 { /* IMC */ 617 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC), 618 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 619 }, 620 { /* IMC */ 621 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC), 622 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 623 }, 624 { /* IMC */ 625 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC), 626 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 627 }, 628 { /* IMC */ 629 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC), 630 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 631 }, 632 { /* IMC */ 633 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC), 634 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 635 }, 636 { /* IMC */ 637 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC), 638 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 639 }, 640 { /* IMC */ 641 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC), 642 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 643 }, 644 { /* IMC */ 645 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC), 646 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 647 }, 648 { /* IMC */ 649 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC), 650 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 651 }, 652 { /* IMC */ 653 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC), 654 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 655 }, 656 { /* IMC */ 657 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC), 658 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 659 }, 660 { /* IMC */ 661 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC), 662 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 663 }, 664 { /* IMC */ 665 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC), 666 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 667 }, 668 { /* end: all zeroes */ }, 669 }; 670 671 static struct pci_driver snb_uncore_pci_driver = { 672 .name = "snb_uncore", 673 .id_table = snb_uncore_pci_ids, 674 }; 675 676 static struct pci_driver ivb_uncore_pci_driver = { 677 .name = "ivb_uncore", 678 .id_table = ivb_uncore_pci_ids, 679 }; 680 681 static struct pci_driver hsw_uncore_pci_driver = { 682 .name = "hsw_uncore", 683 .id_table = hsw_uncore_pci_ids, 684 }; 685 686 static struct pci_driver bdw_uncore_pci_driver = { 687 .name = "bdw_uncore", 688 .id_table = bdw_uncore_pci_ids, 689 }; 690 691 static struct pci_driver skl_uncore_pci_driver = { 692 .name = "skl_uncore", 693 .id_table = skl_uncore_pci_ids, 694 }; 695 696 struct imc_uncore_pci_dev { 697 __u32 pci_id; 698 struct pci_driver *driver; 699 }; 700 #define IMC_DEV(a, d) \ 701 { .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) } 702 703 static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = { 704 IMC_DEV(SNB_IMC, &snb_uncore_pci_driver), 705 IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver), /* 3rd Gen Core processor */ 706 IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */ 707 IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core Processor */ 708 IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core ULT Mobile Processor */ 709 IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver), /* 5th Gen Core U */ 710 IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver), /* 6th Gen Core Y */ 711 IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver), /* 6th Gen Core U */ 712 IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Dual Core */ 713 IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */ 714 IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */ 715 IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */ 716 IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */ 717 IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */ 718 IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */ 719 IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */ 720 IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */ 721 IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */ 722 IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */ 723 IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */ 724 IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 6 Cores */ 725 IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 2 Cores Desktop */ 726 IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Desktop */ 727 IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Desktop */ 728 IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Desktop */ 729 IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Work Station */ 730 IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Work Station */ 731 IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Work Station */ 732 IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */ 733 IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */ 734 IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */ 735 { /* end marker */ } 736 }; 737 738 739 #define for_each_imc_pci_id(x, t) \ 740 for (x = (t); (x)->pci_id; x++) 741 742 static struct pci_driver *imc_uncore_find_dev(void) 743 { 744 const struct imc_uncore_pci_dev *p; 745 int ret; 746 747 for_each_imc_pci_id(p, desktop_imc_pci_ids) { 748 ret = snb_pci2phy_map_init(p->pci_id); 749 if (ret == 0) 750 return p->driver; 751 } 752 return NULL; 753 } 754 755 static int imc_uncore_pci_init(void) 756 { 757 struct pci_driver *imc_drv = imc_uncore_find_dev(); 758 759 if (!imc_drv) 760 return -ENODEV; 761 762 uncore_pci_uncores = snb_pci_uncores; 763 uncore_pci_driver = imc_drv; 764 765 return 0; 766 } 767 768 int snb_uncore_pci_init(void) 769 { 770 return imc_uncore_pci_init(); 771 } 772 773 int ivb_uncore_pci_init(void) 774 { 775 return imc_uncore_pci_init(); 776 } 777 int hsw_uncore_pci_init(void) 778 { 779 return imc_uncore_pci_init(); 780 } 781 782 int bdw_uncore_pci_init(void) 783 { 784 return imc_uncore_pci_init(); 785 } 786 787 int skl_uncore_pci_init(void) 788 { 789 return imc_uncore_pci_init(); 790 } 791 792 /* end of Sandy Bridge uncore support */ 793 794 /* Nehalem uncore support */ 795 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box) 796 { 797 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); 798 } 799 800 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box) 801 { 802 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); 803 } 804 805 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 806 { 807 struct hw_perf_event *hwc = &event->hw; 808 809 if (hwc->idx < UNCORE_PMC_IDX_FIXED) 810 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 811 else 812 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); 813 } 814 815 static struct attribute *nhm_uncore_formats_attr[] = { 816 &format_attr_event.attr, 817 &format_attr_umask.attr, 818 &format_attr_edge.attr, 819 &format_attr_inv.attr, 820 &format_attr_cmask8.attr, 821 NULL, 822 }; 823 824 static const struct attribute_group nhm_uncore_format_group = { 825 .name = "format", 826 .attrs = nhm_uncore_formats_attr, 827 }; 828 829 static struct uncore_event_desc nhm_uncore_events[] = { 830 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 831 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"), 832 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"), 833 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"), 834 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"), 835 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"), 836 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"), 837 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"), 838 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"), 839 { /* end: all zeroes */ }, 840 }; 841 842 static struct intel_uncore_ops nhm_uncore_msr_ops = { 843 .disable_box = nhm_uncore_msr_disable_box, 844 .enable_box = nhm_uncore_msr_enable_box, 845 .disable_event = snb_uncore_msr_disable_event, 846 .enable_event = nhm_uncore_msr_enable_event, 847 .read_counter = uncore_msr_read_counter, 848 }; 849 850 static struct intel_uncore_type nhm_uncore = { 851 .name = "", 852 .num_counters = 8, 853 .num_boxes = 1, 854 .perf_ctr_bits = 48, 855 .fixed_ctr_bits = 48, 856 .event_ctl = NHM_UNC_PERFEVTSEL0, 857 .perf_ctr = NHM_UNC_UNCORE_PMC0, 858 .fixed_ctr = NHM_UNC_FIXED_CTR, 859 .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL, 860 .event_mask = NHM_UNC_RAW_EVENT_MASK, 861 .event_descs = nhm_uncore_events, 862 .ops = &nhm_uncore_msr_ops, 863 .format_group = &nhm_uncore_format_group, 864 }; 865 866 static struct intel_uncore_type *nhm_msr_uncores[] = { 867 &nhm_uncore, 868 NULL, 869 }; 870 871 void nhm_uncore_cpu_init(void) 872 { 873 uncore_msr_uncores = nhm_msr_uncores; 874 } 875 876 /* end of Nehalem uncore support */ 877