1 // SPDX-License-Identifier: GPL-2.0 2 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */ 3 #include "uncore.h" 4 5 /* Uncore IMC PCI IDs */ 6 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 7 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 8 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150 9 #define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00 10 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04 11 #define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604 12 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904 13 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c 14 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900 15 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910 16 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f 17 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f 18 #define PCI_DEVICE_ID_INTEL_SKL_E3_IMC 0x1918 19 #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c 20 #define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904 21 #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914 22 #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f 23 #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f 24 #define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC 0x5910 25 #define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC 0x5918 26 #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc 27 #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0 28 #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10 29 #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4 30 #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f 31 #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f 32 #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2 33 #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30 34 #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18 35 #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6 36 #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31 37 #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33 38 #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca 39 #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32 40 #define PCI_DEVICE_ID_INTEL_AML_YD_IMC 0x590c 41 #define PCI_DEVICE_ID_INTEL_AML_YQ_IMC 0x590d 42 #define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC 0x3ed0 43 #define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC 0x3e34 44 #define PCI_DEVICE_ID_INTEL_WHL_UD_IMC 0x3e35 45 #define PCI_DEVICE_ID_INTEL_CML_H1_IMC 0x9b44 46 #define PCI_DEVICE_ID_INTEL_CML_H2_IMC 0x9b54 47 #define PCI_DEVICE_ID_INTEL_CML_H3_IMC 0x9b64 48 #define PCI_DEVICE_ID_INTEL_CML_U1_IMC 0x9b51 49 #define PCI_DEVICE_ID_INTEL_CML_U2_IMC 0x9b61 50 #define PCI_DEVICE_ID_INTEL_CML_U3_IMC 0x9b71 51 #define PCI_DEVICE_ID_INTEL_CML_S1_IMC 0x9b33 52 #define PCI_DEVICE_ID_INTEL_CML_S2_IMC 0x9b43 53 #define PCI_DEVICE_ID_INTEL_CML_S3_IMC 0x9b53 54 #define PCI_DEVICE_ID_INTEL_CML_S4_IMC 0x9b63 55 #define PCI_DEVICE_ID_INTEL_CML_S5_IMC 0x9b73 56 #define PCI_DEVICE_ID_INTEL_ICL_U_IMC 0x8a02 57 #define PCI_DEVICE_ID_INTEL_ICL_U2_IMC 0x8a12 58 #define PCI_DEVICE_ID_INTEL_TGL_U1_IMC 0x9a02 59 #define PCI_DEVICE_ID_INTEL_TGL_U2_IMC 0x9a04 60 #define PCI_DEVICE_ID_INTEL_TGL_U3_IMC 0x9a12 61 #define PCI_DEVICE_ID_INTEL_TGL_U4_IMC 0x9a14 62 #define PCI_DEVICE_ID_INTEL_TGL_H_IMC 0x9a36 63 64 65 /* SNB event control */ 66 #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff 67 #define SNB_UNC_CTL_UMASK_MASK 0x0000ff00 68 #define SNB_UNC_CTL_EDGE_DET (1 << 18) 69 #define SNB_UNC_CTL_EN (1 << 22) 70 #define SNB_UNC_CTL_INVERT (1 << 23) 71 #define SNB_UNC_CTL_CMASK_MASK 0x1f000000 72 #define NHM_UNC_CTL_CMASK_MASK 0xff000000 73 #define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0) 74 75 #define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ 76 SNB_UNC_CTL_UMASK_MASK | \ 77 SNB_UNC_CTL_EDGE_DET | \ 78 SNB_UNC_CTL_INVERT | \ 79 SNB_UNC_CTL_CMASK_MASK) 80 81 #define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ 82 SNB_UNC_CTL_UMASK_MASK | \ 83 SNB_UNC_CTL_EDGE_DET | \ 84 SNB_UNC_CTL_INVERT | \ 85 NHM_UNC_CTL_CMASK_MASK) 86 87 /* SNB global control register */ 88 #define SNB_UNC_PERF_GLOBAL_CTL 0x391 89 #define SNB_UNC_FIXED_CTR_CTRL 0x394 90 #define SNB_UNC_FIXED_CTR 0x395 91 92 /* SNB uncore global control */ 93 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1) 94 #define SNB_UNC_GLOBAL_CTL_EN (1 << 29) 95 96 /* SNB Cbo register */ 97 #define SNB_UNC_CBO_0_PERFEVTSEL0 0x700 98 #define SNB_UNC_CBO_0_PER_CTR0 0x706 99 #define SNB_UNC_CBO_MSR_OFFSET 0x10 100 101 /* SNB ARB register */ 102 #define SNB_UNC_ARB_PER_CTR0 0x3b0 103 #define SNB_UNC_ARB_PERFEVTSEL0 0x3b2 104 #define SNB_UNC_ARB_MSR_OFFSET 0x10 105 106 /* NHM global control register */ 107 #define NHM_UNC_PERF_GLOBAL_CTL 0x391 108 #define NHM_UNC_FIXED_CTR 0x394 109 #define NHM_UNC_FIXED_CTR_CTRL 0x395 110 111 /* NHM uncore global control */ 112 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1) 113 #define NHM_UNC_GLOBAL_CTL_EN_FC (1ULL << 32) 114 115 /* NHM uncore register */ 116 #define NHM_UNC_PERFEVTSEL0 0x3c0 117 #define NHM_UNC_UNCORE_PMC0 0x3b0 118 119 /* SKL uncore global control */ 120 #define SKL_UNC_PERF_GLOBAL_CTL 0xe01 121 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1) 122 123 /* ICL Cbo register */ 124 #define ICL_UNC_CBO_CONFIG 0x396 125 #define ICL_UNC_NUM_CBO_MASK 0xf 126 #define ICL_UNC_CBO_0_PER_CTR0 0x702 127 #define ICL_UNC_CBO_MSR_OFFSET 0x8 128 129 /* ICL ARB register */ 130 #define ICL_UNC_ARB_PER_CTR 0x3b1 131 #define ICL_UNC_ARB_PERFEVTSEL 0x3b3 132 133 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 134 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 135 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 136 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 137 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28"); 138 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31"); 139 140 /* Sandy Bridge uncore support */ 141 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 142 { 143 struct hw_perf_event *hwc = &event->hw; 144 145 if (hwc->idx < UNCORE_PMC_IDX_FIXED) 146 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 147 else 148 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); 149 } 150 151 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) 152 { 153 wrmsrl(event->hw.config_base, 0); 154 } 155 156 static void snb_uncore_msr_init_box(struct intel_uncore_box *box) 157 { 158 if (box->pmu->pmu_idx == 0) { 159 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 160 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); 161 } 162 } 163 164 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box) 165 { 166 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 167 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); 168 } 169 170 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box) 171 { 172 if (box->pmu->pmu_idx == 0) 173 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); 174 } 175 176 static struct uncore_event_desc snb_uncore_events[] = { 177 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 178 { /* end: all zeroes */ }, 179 }; 180 181 static struct attribute *snb_uncore_formats_attr[] = { 182 &format_attr_event.attr, 183 &format_attr_umask.attr, 184 &format_attr_edge.attr, 185 &format_attr_inv.attr, 186 &format_attr_cmask5.attr, 187 NULL, 188 }; 189 190 static const struct attribute_group snb_uncore_format_group = { 191 .name = "format", 192 .attrs = snb_uncore_formats_attr, 193 }; 194 195 static struct intel_uncore_ops snb_uncore_msr_ops = { 196 .init_box = snb_uncore_msr_init_box, 197 .enable_box = snb_uncore_msr_enable_box, 198 .exit_box = snb_uncore_msr_exit_box, 199 .disable_event = snb_uncore_msr_disable_event, 200 .enable_event = snb_uncore_msr_enable_event, 201 .read_counter = uncore_msr_read_counter, 202 }; 203 204 static struct event_constraint snb_uncore_arb_constraints[] = { 205 UNCORE_EVENT_CONSTRAINT(0x80, 0x1), 206 UNCORE_EVENT_CONSTRAINT(0x83, 0x1), 207 EVENT_CONSTRAINT_END 208 }; 209 210 static struct intel_uncore_type snb_uncore_cbox = { 211 .name = "cbox", 212 .num_counters = 2, 213 .num_boxes = 4, 214 .perf_ctr_bits = 44, 215 .fixed_ctr_bits = 48, 216 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0, 217 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0, 218 .fixed_ctr = SNB_UNC_FIXED_CTR, 219 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL, 220 .single_fixed = 1, 221 .event_mask = SNB_UNC_RAW_EVENT_MASK, 222 .msr_offset = SNB_UNC_CBO_MSR_OFFSET, 223 .ops = &snb_uncore_msr_ops, 224 .format_group = &snb_uncore_format_group, 225 .event_descs = snb_uncore_events, 226 }; 227 228 static struct intel_uncore_type snb_uncore_arb = { 229 .name = "arb", 230 .num_counters = 2, 231 .num_boxes = 1, 232 .perf_ctr_bits = 44, 233 .perf_ctr = SNB_UNC_ARB_PER_CTR0, 234 .event_ctl = SNB_UNC_ARB_PERFEVTSEL0, 235 .event_mask = SNB_UNC_RAW_EVENT_MASK, 236 .msr_offset = SNB_UNC_ARB_MSR_OFFSET, 237 .constraints = snb_uncore_arb_constraints, 238 .ops = &snb_uncore_msr_ops, 239 .format_group = &snb_uncore_format_group, 240 }; 241 242 static struct intel_uncore_type *snb_msr_uncores[] = { 243 &snb_uncore_cbox, 244 &snb_uncore_arb, 245 NULL, 246 }; 247 248 void snb_uncore_cpu_init(void) 249 { 250 uncore_msr_uncores = snb_msr_uncores; 251 if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 252 snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 253 } 254 255 static void skl_uncore_msr_init_box(struct intel_uncore_box *box) 256 { 257 if (box->pmu->pmu_idx == 0) { 258 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 259 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 260 } 261 262 /* The 8th CBOX has different MSR space */ 263 if (box->pmu->pmu_idx == 7) 264 __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags); 265 } 266 267 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) 268 { 269 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 270 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 271 } 272 273 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) 274 { 275 if (box->pmu->pmu_idx == 0) 276 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); 277 } 278 279 static struct intel_uncore_ops skl_uncore_msr_ops = { 280 .init_box = skl_uncore_msr_init_box, 281 .enable_box = skl_uncore_msr_enable_box, 282 .exit_box = skl_uncore_msr_exit_box, 283 .disable_event = snb_uncore_msr_disable_event, 284 .enable_event = snb_uncore_msr_enable_event, 285 .read_counter = uncore_msr_read_counter, 286 }; 287 288 static struct intel_uncore_type skl_uncore_cbox = { 289 .name = "cbox", 290 .num_counters = 4, 291 .num_boxes = 8, 292 .perf_ctr_bits = 44, 293 .fixed_ctr_bits = 48, 294 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0, 295 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0, 296 .fixed_ctr = SNB_UNC_FIXED_CTR, 297 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL, 298 .single_fixed = 1, 299 .event_mask = SNB_UNC_RAW_EVENT_MASK, 300 .msr_offset = SNB_UNC_CBO_MSR_OFFSET, 301 .ops = &skl_uncore_msr_ops, 302 .format_group = &snb_uncore_format_group, 303 .event_descs = snb_uncore_events, 304 }; 305 306 static struct intel_uncore_type *skl_msr_uncores[] = { 307 &skl_uncore_cbox, 308 &snb_uncore_arb, 309 NULL, 310 }; 311 312 void skl_uncore_cpu_init(void) 313 { 314 uncore_msr_uncores = skl_msr_uncores; 315 if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) 316 skl_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; 317 snb_uncore_arb.ops = &skl_uncore_msr_ops; 318 } 319 320 static struct intel_uncore_ops icl_uncore_msr_ops = { 321 .disable_event = snb_uncore_msr_disable_event, 322 .enable_event = snb_uncore_msr_enable_event, 323 .read_counter = uncore_msr_read_counter, 324 }; 325 326 static struct intel_uncore_type icl_uncore_cbox = { 327 .name = "cbox", 328 .num_counters = 2, 329 .perf_ctr_bits = 44, 330 .perf_ctr = ICL_UNC_CBO_0_PER_CTR0, 331 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0, 332 .event_mask = SNB_UNC_RAW_EVENT_MASK, 333 .msr_offset = ICL_UNC_CBO_MSR_OFFSET, 334 .ops = &icl_uncore_msr_ops, 335 .format_group = &snb_uncore_format_group, 336 }; 337 338 static struct uncore_event_desc icl_uncore_events[] = { 339 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff"), 340 { /* end: all zeroes */ }, 341 }; 342 343 static struct attribute *icl_uncore_clock_formats_attr[] = { 344 &format_attr_event.attr, 345 NULL, 346 }; 347 348 static struct attribute_group icl_uncore_clock_format_group = { 349 .name = "format", 350 .attrs = icl_uncore_clock_formats_attr, 351 }; 352 353 static struct intel_uncore_type icl_uncore_clockbox = { 354 .name = "clock", 355 .num_counters = 1, 356 .num_boxes = 1, 357 .fixed_ctr_bits = 48, 358 .fixed_ctr = SNB_UNC_FIXED_CTR, 359 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL, 360 .single_fixed = 1, 361 .event_mask = SNB_UNC_CTL_EV_SEL_MASK, 362 .format_group = &icl_uncore_clock_format_group, 363 .ops = &icl_uncore_msr_ops, 364 .event_descs = icl_uncore_events, 365 }; 366 367 static struct intel_uncore_type icl_uncore_arb = { 368 .name = "arb", 369 .num_counters = 1, 370 .num_boxes = 1, 371 .perf_ctr_bits = 44, 372 .perf_ctr = ICL_UNC_ARB_PER_CTR, 373 .event_ctl = ICL_UNC_ARB_PERFEVTSEL, 374 .event_mask = SNB_UNC_RAW_EVENT_MASK, 375 .ops = &icl_uncore_msr_ops, 376 .format_group = &snb_uncore_format_group, 377 }; 378 379 static struct intel_uncore_type *icl_msr_uncores[] = { 380 &icl_uncore_cbox, 381 &icl_uncore_arb, 382 &icl_uncore_clockbox, 383 NULL, 384 }; 385 386 static int icl_get_cbox_num(void) 387 { 388 u64 num_boxes; 389 390 rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes); 391 392 return num_boxes & ICL_UNC_NUM_CBO_MASK; 393 } 394 395 void icl_uncore_cpu_init(void) 396 { 397 uncore_msr_uncores = icl_msr_uncores; 398 icl_uncore_cbox.num_boxes = icl_get_cbox_num(); 399 } 400 401 static struct intel_uncore_type *tgl_msr_uncores[] = { 402 &icl_uncore_cbox, 403 &snb_uncore_arb, 404 &icl_uncore_clockbox, 405 NULL, 406 }; 407 408 void tgl_uncore_cpu_init(void) 409 { 410 uncore_msr_uncores = tgl_msr_uncores; 411 icl_uncore_cbox.num_boxes = icl_get_cbox_num(); 412 icl_uncore_cbox.ops = &skl_uncore_msr_ops; 413 icl_uncore_clockbox.ops = &skl_uncore_msr_ops; 414 snb_uncore_arb.ops = &skl_uncore_msr_ops; 415 } 416 417 enum { 418 SNB_PCI_UNCORE_IMC, 419 }; 420 421 static struct uncore_event_desc snb_uncore_imc_events[] = { 422 INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"), 423 INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"), 424 INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"), 425 426 INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"), 427 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"), 428 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"), 429 430 INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"), 431 INTEL_UNCORE_EVENT_DESC(gt_requests.scale, "6.103515625e-5"), 432 INTEL_UNCORE_EVENT_DESC(gt_requests.unit, "MiB"), 433 434 INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"), 435 INTEL_UNCORE_EVENT_DESC(ia_requests.scale, "6.103515625e-5"), 436 INTEL_UNCORE_EVENT_DESC(ia_requests.unit, "MiB"), 437 438 INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"), 439 INTEL_UNCORE_EVENT_DESC(io_requests.scale, "6.103515625e-5"), 440 INTEL_UNCORE_EVENT_DESC(io_requests.unit, "MiB"), 441 442 { /* end: all zeroes */ }, 443 }; 444 445 #define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff 446 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48 447 448 /* page size multiple covering all config regs */ 449 #define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000 450 451 #define SNB_UNCORE_PCI_IMC_DATA_READS 0x1 452 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050 453 #define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2 454 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054 455 #define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE 456 457 /* BW break down- legacy counters */ 458 #define SNB_UNCORE_PCI_IMC_GT_REQUESTS 0x3 459 #define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040 460 #define SNB_UNCORE_PCI_IMC_IA_REQUESTS 0x4 461 #define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044 462 #define SNB_UNCORE_PCI_IMC_IO_REQUESTS 0x5 463 #define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048 464 465 enum perf_snb_uncore_imc_freerunning_types { 466 SNB_PCI_UNCORE_IMC_DATA_READS = 0, 467 SNB_PCI_UNCORE_IMC_DATA_WRITES, 468 SNB_PCI_UNCORE_IMC_GT_REQUESTS, 469 SNB_PCI_UNCORE_IMC_IA_REQUESTS, 470 SNB_PCI_UNCORE_IMC_IO_REQUESTS, 471 472 SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, 473 }; 474 475 static struct freerunning_counters snb_uncore_imc_freerunning[] = { 476 [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 477 0x0, 0x0, 1, 32 }, 478 [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE, 479 0x0, 0x0, 1, 32 }, 480 [SNB_PCI_UNCORE_IMC_GT_REQUESTS] = { SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE, 481 0x0, 0x0, 1, 32 }, 482 [SNB_PCI_UNCORE_IMC_IA_REQUESTS] = { SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE, 483 0x0, 0x0, 1, 32 }, 484 [SNB_PCI_UNCORE_IMC_IO_REQUESTS] = { SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE, 485 0x0, 0x0, 1, 32 }, 486 }; 487 488 static struct attribute *snb_uncore_imc_formats_attr[] = { 489 &format_attr_event.attr, 490 NULL, 491 }; 492 493 static const struct attribute_group snb_uncore_imc_format_group = { 494 .name = "format", 495 .attrs = snb_uncore_imc_formats_attr, 496 }; 497 498 static void snb_uncore_imc_init_box(struct intel_uncore_box *box) 499 { 500 struct intel_uncore_type *type = box->pmu->type; 501 struct pci_dev *pdev = box->pci_dev; 502 int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET; 503 resource_size_t addr; 504 u32 pci_dword; 505 506 pci_read_config_dword(pdev, where, &pci_dword); 507 addr = pci_dword; 508 509 #ifdef CONFIG_PHYS_ADDR_T_64BIT 510 pci_read_config_dword(pdev, where + 4, &pci_dword); 511 addr |= ((resource_size_t)pci_dword << 32); 512 #endif 513 514 addr &= ~(PAGE_SIZE - 1); 515 516 box->io_addr = ioremap(addr, type->mmio_map_size); 517 if (!box->io_addr) 518 pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); 519 520 box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL; 521 } 522 523 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box) 524 {} 525 526 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box) 527 {} 528 529 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event) 530 {} 531 532 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event) 533 {} 534 535 /* 536 * Keep the custom event_init() function compatible with old event 537 * encoding for free running counters. 538 */ 539 static int snb_uncore_imc_event_init(struct perf_event *event) 540 { 541 struct intel_uncore_pmu *pmu; 542 struct intel_uncore_box *box; 543 struct hw_perf_event *hwc = &event->hw; 544 u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK; 545 int idx, base; 546 547 if (event->attr.type != event->pmu->type) 548 return -ENOENT; 549 550 pmu = uncore_event_to_pmu(event); 551 /* no device found for this pmu */ 552 if (pmu->func_id < 0) 553 return -ENOENT; 554 555 /* Sampling not supported yet */ 556 if (hwc->sample_period) 557 return -EINVAL; 558 559 /* unsupported modes and filters */ 560 if (event->attr.sample_period) /* no sampling */ 561 return -EINVAL; 562 563 /* 564 * Place all uncore events for a particular physical package 565 * onto a single cpu 566 */ 567 if (event->cpu < 0) 568 return -EINVAL; 569 570 /* check only supported bits are set */ 571 if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK) 572 return -EINVAL; 573 574 box = uncore_pmu_to_box(pmu, event->cpu); 575 if (!box || box->cpu < 0) 576 return -EINVAL; 577 578 event->cpu = box->cpu; 579 event->pmu_private = box; 580 581 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; 582 583 event->hw.idx = -1; 584 event->hw.last_tag = ~0ULL; 585 event->hw.extra_reg.idx = EXTRA_REG_NONE; 586 event->hw.branch_reg.idx = EXTRA_REG_NONE; 587 /* 588 * check event is known (whitelist, determines counter) 589 */ 590 switch (cfg) { 591 case SNB_UNCORE_PCI_IMC_DATA_READS: 592 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE; 593 idx = UNCORE_PMC_IDX_FREERUNNING; 594 break; 595 case SNB_UNCORE_PCI_IMC_DATA_WRITES: 596 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE; 597 idx = UNCORE_PMC_IDX_FREERUNNING; 598 break; 599 case SNB_UNCORE_PCI_IMC_GT_REQUESTS: 600 base = SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE; 601 idx = UNCORE_PMC_IDX_FREERUNNING; 602 break; 603 case SNB_UNCORE_PCI_IMC_IA_REQUESTS: 604 base = SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE; 605 idx = UNCORE_PMC_IDX_FREERUNNING; 606 break; 607 case SNB_UNCORE_PCI_IMC_IO_REQUESTS: 608 base = SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE; 609 idx = UNCORE_PMC_IDX_FREERUNNING; 610 break; 611 default: 612 return -EINVAL; 613 } 614 615 /* must be done before validate_group */ 616 event->hw.event_base = base; 617 event->hw.idx = idx; 618 619 /* Convert to standard encoding format for freerunning counters */ 620 event->hw.config = ((cfg - 1) << 8) | 0x10ff; 621 622 /* no group validation needed, we have free running counters */ 623 624 return 0; 625 } 626 627 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event) 628 { 629 return 0; 630 } 631 632 int snb_pci2phy_map_init(int devid) 633 { 634 struct pci_dev *dev = NULL; 635 struct pci2phy_map *map; 636 int bus, segment; 637 638 dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev); 639 if (!dev) 640 return -ENOTTY; 641 642 bus = dev->bus->number; 643 segment = pci_domain_nr(dev->bus); 644 645 raw_spin_lock(&pci2phy_map_lock); 646 map = __find_pci2phy_map(segment); 647 if (!map) { 648 raw_spin_unlock(&pci2phy_map_lock); 649 pci_dev_put(dev); 650 return -ENOMEM; 651 } 652 map->pbus_to_physid[bus] = 0; 653 raw_spin_unlock(&pci2phy_map_lock); 654 655 pci_dev_put(dev); 656 657 return 0; 658 } 659 660 static struct pmu snb_uncore_imc_pmu = { 661 .task_ctx_nr = perf_invalid_context, 662 .event_init = snb_uncore_imc_event_init, 663 .add = uncore_pmu_event_add, 664 .del = uncore_pmu_event_del, 665 .start = uncore_pmu_event_start, 666 .stop = uncore_pmu_event_stop, 667 .read = uncore_pmu_event_read, 668 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 669 }; 670 671 static struct intel_uncore_ops snb_uncore_imc_ops = { 672 .init_box = snb_uncore_imc_init_box, 673 .exit_box = uncore_mmio_exit_box, 674 .enable_box = snb_uncore_imc_enable_box, 675 .disable_box = snb_uncore_imc_disable_box, 676 .disable_event = snb_uncore_imc_disable_event, 677 .enable_event = snb_uncore_imc_enable_event, 678 .hw_config = snb_uncore_imc_hw_config, 679 .read_counter = uncore_mmio_read_counter, 680 }; 681 682 static struct intel_uncore_type snb_uncore_imc = { 683 .name = "imc", 684 .num_counters = 5, 685 .num_boxes = 1, 686 .num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, 687 .mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE, 688 .freerunning = snb_uncore_imc_freerunning, 689 .event_descs = snb_uncore_imc_events, 690 .format_group = &snb_uncore_imc_format_group, 691 .ops = &snb_uncore_imc_ops, 692 .pmu = &snb_uncore_imc_pmu, 693 }; 694 695 static struct intel_uncore_type *snb_pci_uncores[] = { 696 [SNB_PCI_UNCORE_IMC] = &snb_uncore_imc, 697 NULL, 698 }; 699 700 static const struct pci_device_id snb_uncore_pci_ids[] = { 701 { /* IMC */ 702 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC), 703 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 704 }, 705 { /* end: all zeroes */ }, 706 }; 707 708 static const struct pci_device_id ivb_uncore_pci_ids[] = { 709 { /* IMC */ 710 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC), 711 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 712 }, 713 { /* IMC */ 714 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC), 715 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 716 }, 717 { /* end: all zeroes */ }, 718 }; 719 720 static const struct pci_device_id hsw_uncore_pci_ids[] = { 721 { /* IMC */ 722 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC), 723 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 724 }, 725 { /* IMC */ 726 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC), 727 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 728 }, 729 { /* end: all zeroes */ }, 730 }; 731 732 static const struct pci_device_id bdw_uncore_pci_ids[] = { 733 { /* IMC */ 734 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC), 735 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 736 }, 737 { /* end: all zeroes */ }, 738 }; 739 740 static const struct pci_device_id skl_uncore_pci_ids[] = { 741 { /* IMC */ 742 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_Y_IMC), 743 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 744 }, 745 { /* IMC */ 746 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_U_IMC), 747 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 748 }, 749 { /* IMC */ 750 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HD_IMC), 751 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 752 }, 753 { /* IMC */ 754 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HQ_IMC), 755 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 756 }, 757 { /* IMC */ 758 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SD_IMC), 759 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 760 }, 761 { /* IMC */ 762 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC), 763 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 764 }, 765 { /* IMC */ 766 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_E3_IMC), 767 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 768 }, 769 { /* IMC */ 770 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC), 771 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 772 }, 773 { /* IMC */ 774 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC), 775 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 776 }, 777 { /* IMC */ 778 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC), 779 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 780 }, 781 { /* IMC */ 782 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC), 783 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 784 }, 785 { /* IMC */ 786 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC), 787 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 788 }, 789 { /* IMC */ 790 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_HQ_IMC), 791 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 792 }, 793 { /* IMC */ 794 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_WQ_IMC), 795 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 796 }, 797 { /* IMC */ 798 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC), 799 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 800 }, 801 { /* IMC */ 802 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC), 803 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 804 }, 805 { /* IMC */ 806 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC), 807 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 808 }, 809 { /* IMC */ 810 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC), 811 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 812 }, 813 { /* IMC */ 814 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC), 815 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 816 }, 817 { /* IMC */ 818 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC), 819 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 820 }, 821 { /* IMC */ 822 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC), 823 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 824 }, 825 { /* IMC */ 826 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC), 827 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 828 }, 829 { /* IMC */ 830 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC), 831 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 832 }, 833 { /* IMC */ 834 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC), 835 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 836 }, 837 { /* IMC */ 838 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC), 839 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 840 }, 841 { /* IMC */ 842 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC), 843 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 844 }, 845 { /* IMC */ 846 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC), 847 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 848 }, 849 { /* IMC */ 850 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC), 851 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 852 }, 853 { /* IMC */ 854 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YD_IMC), 855 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 856 }, 857 { /* IMC */ 858 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YQ_IMC), 859 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 860 }, 861 { /* IMC */ 862 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UQ_IMC), 863 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 864 }, 865 { /* IMC */ 866 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC), 867 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 868 }, 869 { /* IMC */ 870 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UD_IMC), 871 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 872 }, 873 { /* IMC */ 874 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H1_IMC), 875 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 876 }, 877 { /* IMC */ 878 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H2_IMC), 879 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 880 }, 881 { /* IMC */ 882 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H3_IMC), 883 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 884 }, 885 { /* IMC */ 886 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U1_IMC), 887 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 888 }, 889 { /* IMC */ 890 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U2_IMC), 891 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 892 }, 893 { /* IMC */ 894 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U3_IMC), 895 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 896 }, 897 { /* IMC */ 898 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S1_IMC), 899 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 900 }, 901 { /* IMC */ 902 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S2_IMC), 903 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 904 }, 905 { /* IMC */ 906 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S3_IMC), 907 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 908 }, 909 { /* IMC */ 910 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S4_IMC), 911 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 912 }, 913 { /* IMC */ 914 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S5_IMC), 915 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 916 }, 917 { /* end: all zeroes */ }, 918 }; 919 920 static const struct pci_device_id icl_uncore_pci_ids[] = { 921 { /* IMC */ 922 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U_IMC), 923 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 924 }, 925 { /* IMC */ 926 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U2_IMC), 927 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 928 }, 929 { /* end: all zeroes */ }, 930 }; 931 932 static struct pci_driver snb_uncore_pci_driver = { 933 .name = "snb_uncore", 934 .id_table = snb_uncore_pci_ids, 935 }; 936 937 static struct pci_driver ivb_uncore_pci_driver = { 938 .name = "ivb_uncore", 939 .id_table = ivb_uncore_pci_ids, 940 }; 941 942 static struct pci_driver hsw_uncore_pci_driver = { 943 .name = "hsw_uncore", 944 .id_table = hsw_uncore_pci_ids, 945 }; 946 947 static struct pci_driver bdw_uncore_pci_driver = { 948 .name = "bdw_uncore", 949 .id_table = bdw_uncore_pci_ids, 950 }; 951 952 static struct pci_driver skl_uncore_pci_driver = { 953 .name = "skl_uncore", 954 .id_table = skl_uncore_pci_ids, 955 }; 956 957 static struct pci_driver icl_uncore_pci_driver = { 958 .name = "icl_uncore", 959 .id_table = icl_uncore_pci_ids, 960 }; 961 962 struct imc_uncore_pci_dev { 963 __u32 pci_id; 964 struct pci_driver *driver; 965 }; 966 #define IMC_DEV(a, d) \ 967 { .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) } 968 969 static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = { 970 IMC_DEV(SNB_IMC, &snb_uncore_pci_driver), 971 IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver), /* 3rd Gen Core processor */ 972 IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */ 973 IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core Processor */ 974 IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core ULT Mobile Processor */ 975 IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver), /* 5th Gen Core U */ 976 IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver), /* 6th Gen Core Y */ 977 IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver), /* 6th Gen Core U */ 978 IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Dual Core */ 979 IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */ 980 IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */ 981 IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */ 982 IMC_DEV(SKL_E3_IMC, &skl_uncore_pci_driver), /* Xeon E3 V5 Gen Core processor */ 983 IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */ 984 IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */ 985 IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */ 986 IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */ 987 IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */ 988 IMC_DEV(KBL_HQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core H Quad Core */ 989 IMC_DEV(KBL_WQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S 4 cores Work Station */ 990 IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */ 991 IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */ 992 IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */ 993 IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 6 Cores */ 994 IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 2 Cores Desktop */ 995 IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Desktop */ 996 IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Desktop */ 997 IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Desktop */ 998 IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Work Station */ 999 IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Work Station */ 1000 IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Work Station */ 1001 IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */ 1002 IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */ 1003 IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */ 1004 IMC_DEV(AML_YD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Dual Core */ 1005 IMC_DEV(AML_YQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Quad Core */ 1006 IMC_DEV(WHL_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */ 1007 IMC_DEV(WHL_4_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */ 1008 IMC_DEV(WHL_UD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Dual Core */ 1009 IMC_DEV(CML_H1_IMC, &skl_uncore_pci_driver), 1010 IMC_DEV(CML_H2_IMC, &skl_uncore_pci_driver), 1011 IMC_DEV(CML_H3_IMC, &skl_uncore_pci_driver), 1012 IMC_DEV(CML_U1_IMC, &skl_uncore_pci_driver), 1013 IMC_DEV(CML_U2_IMC, &skl_uncore_pci_driver), 1014 IMC_DEV(CML_U3_IMC, &skl_uncore_pci_driver), 1015 IMC_DEV(CML_S1_IMC, &skl_uncore_pci_driver), 1016 IMC_DEV(CML_S2_IMC, &skl_uncore_pci_driver), 1017 IMC_DEV(CML_S3_IMC, &skl_uncore_pci_driver), 1018 IMC_DEV(CML_S4_IMC, &skl_uncore_pci_driver), 1019 IMC_DEV(CML_S5_IMC, &skl_uncore_pci_driver), 1020 IMC_DEV(ICL_U_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */ 1021 IMC_DEV(ICL_U2_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */ 1022 { /* end marker */ } 1023 }; 1024 1025 1026 #define for_each_imc_pci_id(x, t) \ 1027 for (x = (t); (x)->pci_id; x++) 1028 1029 static struct pci_driver *imc_uncore_find_dev(void) 1030 { 1031 const struct imc_uncore_pci_dev *p; 1032 int ret; 1033 1034 for_each_imc_pci_id(p, desktop_imc_pci_ids) { 1035 ret = snb_pci2phy_map_init(p->pci_id); 1036 if (ret == 0) 1037 return p->driver; 1038 } 1039 return NULL; 1040 } 1041 1042 static int imc_uncore_pci_init(void) 1043 { 1044 struct pci_driver *imc_drv = imc_uncore_find_dev(); 1045 1046 if (!imc_drv) 1047 return -ENODEV; 1048 1049 uncore_pci_uncores = snb_pci_uncores; 1050 uncore_pci_driver = imc_drv; 1051 1052 return 0; 1053 } 1054 1055 int snb_uncore_pci_init(void) 1056 { 1057 return imc_uncore_pci_init(); 1058 } 1059 1060 int ivb_uncore_pci_init(void) 1061 { 1062 return imc_uncore_pci_init(); 1063 } 1064 int hsw_uncore_pci_init(void) 1065 { 1066 return imc_uncore_pci_init(); 1067 } 1068 1069 int bdw_uncore_pci_init(void) 1070 { 1071 return imc_uncore_pci_init(); 1072 } 1073 1074 int skl_uncore_pci_init(void) 1075 { 1076 return imc_uncore_pci_init(); 1077 } 1078 1079 /* end of Sandy Bridge uncore support */ 1080 1081 /* Nehalem uncore support */ 1082 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box) 1083 { 1084 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); 1085 } 1086 1087 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box) 1088 { 1089 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); 1090 } 1091 1092 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1093 { 1094 struct hw_perf_event *hwc = &event->hw; 1095 1096 if (hwc->idx < UNCORE_PMC_IDX_FIXED) 1097 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 1098 else 1099 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); 1100 } 1101 1102 static struct attribute *nhm_uncore_formats_attr[] = { 1103 &format_attr_event.attr, 1104 &format_attr_umask.attr, 1105 &format_attr_edge.attr, 1106 &format_attr_inv.attr, 1107 &format_attr_cmask8.attr, 1108 NULL, 1109 }; 1110 1111 static const struct attribute_group nhm_uncore_format_group = { 1112 .name = "format", 1113 .attrs = nhm_uncore_formats_attr, 1114 }; 1115 1116 static struct uncore_event_desc nhm_uncore_events[] = { 1117 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 1118 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"), 1119 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"), 1120 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"), 1121 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"), 1122 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"), 1123 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"), 1124 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"), 1125 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"), 1126 { /* end: all zeroes */ }, 1127 }; 1128 1129 static struct intel_uncore_ops nhm_uncore_msr_ops = { 1130 .disable_box = nhm_uncore_msr_disable_box, 1131 .enable_box = nhm_uncore_msr_enable_box, 1132 .disable_event = snb_uncore_msr_disable_event, 1133 .enable_event = nhm_uncore_msr_enable_event, 1134 .read_counter = uncore_msr_read_counter, 1135 }; 1136 1137 static struct intel_uncore_type nhm_uncore = { 1138 .name = "", 1139 .num_counters = 8, 1140 .num_boxes = 1, 1141 .perf_ctr_bits = 48, 1142 .fixed_ctr_bits = 48, 1143 .event_ctl = NHM_UNC_PERFEVTSEL0, 1144 .perf_ctr = NHM_UNC_UNCORE_PMC0, 1145 .fixed_ctr = NHM_UNC_FIXED_CTR, 1146 .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL, 1147 .event_mask = NHM_UNC_RAW_EVENT_MASK, 1148 .event_descs = nhm_uncore_events, 1149 .ops = &nhm_uncore_msr_ops, 1150 .format_group = &nhm_uncore_format_group, 1151 }; 1152 1153 static struct intel_uncore_type *nhm_msr_uncores[] = { 1154 &nhm_uncore, 1155 NULL, 1156 }; 1157 1158 void nhm_uncore_cpu_init(void) 1159 { 1160 uncore_msr_uncores = nhm_msr_uncores; 1161 } 1162 1163 /* end of Nehalem uncore support */ 1164 1165 /* Tiger Lake MMIO uncore support */ 1166 1167 static const struct pci_device_id tgl_uncore_pci_ids[] = { 1168 { /* IMC */ 1169 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U1_IMC), 1170 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 1171 }, 1172 { /* IMC */ 1173 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U2_IMC), 1174 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 1175 }, 1176 { /* IMC */ 1177 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U3_IMC), 1178 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 1179 }, 1180 { /* IMC */ 1181 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_U4_IMC), 1182 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 1183 }, 1184 { /* IMC */ 1185 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_H_IMC), 1186 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 1187 }, 1188 { /* end: all zeroes */ } 1189 }; 1190 1191 enum perf_tgl_uncore_imc_freerunning_types { 1192 TGL_MMIO_UNCORE_IMC_DATA_TOTAL, 1193 TGL_MMIO_UNCORE_IMC_DATA_READ, 1194 TGL_MMIO_UNCORE_IMC_DATA_WRITE, 1195 TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX 1196 }; 1197 1198 static struct freerunning_counters tgl_l_uncore_imc_freerunning[] = { 1199 [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0x5040, 0x0, 0x0, 1, 64 }, 1200 [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0x5058, 0x0, 0x0, 1, 64 }, 1201 [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0x50A0, 0x0, 0x0, 1, 64 }, 1202 }; 1203 1204 static struct freerunning_counters tgl_uncore_imc_freerunning[] = { 1205 [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0xd840, 0x0, 0x0, 1, 64 }, 1206 [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0xd858, 0x0, 0x0, 1, 64 }, 1207 [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0xd8A0, 0x0, 0x0, 1, 64 }, 1208 }; 1209 1210 static struct uncore_event_desc tgl_uncore_imc_events[] = { 1211 INTEL_UNCORE_EVENT_DESC(data_total, "event=0xff,umask=0x10"), 1212 INTEL_UNCORE_EVENT_DESC(data_total.scale, "6.103515625e-5"), 1213 INTEL_UNCORE_EVENT_DESC(data_total.unit, "MiB"), 1214 1215 INTEL_UNCORE_EVENT_DESC(data_read, "event=0xff,umask=0x20"), 1216 INTEL_UNCORE_EVENT_DESC(data_read.scale, "6.103515625e-5"), 1217 INTEL_UNCORE_EVENT_DESC(data_read.unit, "MiB"), 1218 1219 INTEL_UNCORE_EVENT_DESC(data_write, "event=0xff,umask=0x30"), 1220 INTEL_UNCORE_EVENT_DESC(data_write.scale, "6.103515625e-5"), 1221 INTEL_UNCORE_EVENT_DESC(data_write.unit, "MiB"), 1222 1223 { /* end: all zeroes */ } 1224 }; 1225 1226 static struct pci_dev *tgl_uncore_get_mc_dev(void) 1227 { 1228 const struct pci_device_id *ids = tgl_uncore_pci_ids; 1229 struct pci_dev *mc_dev = NULL; 1230 1231 while (ids && ids->vendor) { 1232 mc_dev = pci_get_device(PCI_VENDOR_ID_INTEL, ids->device, NULL); 1233 if (mc_dev) 1234 return mc_dev; 1235 ids++; 1236 } 1237 1238 return mc_dev; 1239 } 1240 1241 #define TGL_UNCORE_MMIO_IMC_MEM_OFFSET 0x10000 1242 #define TGL_UNCORE_PCI_IMC_MAP_SIZE 0xe000 1243 1244 static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) 1245 { 1246 struct pci_dev *pdev = tgl_uncore_get_mc_dev(); 1247 struct intel_uncore_pmu *pmu = box->pmu; 1248 struct intel_uncore_type *type = pmu->type; 1249 resource_size_t addr; 1250 u32 mch_bar; 1251 1252 if (!pdev) { 1253 pr_warn("perf uncore: Cannot find matched IMC device.\n"); 1254 return; 1255 } 1256 1257 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar); 1258 /* MCHBAR is disabled */ 1259 if (!(mch_bar & BIT(0))) { 1260 pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running counters.\n"); 1261 return; 1262 } 1263 mch_bar &= ~BIT(0); 1264 addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu->pmu_idx); 1265 1266 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1267 pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar); 1268 addr |= ((resource_size_t)mch_bar << 32); 1269 #endif 1270 1271 box->io_addr = ioremap(addr, type->mmio_map_size); 1272 if (!box->io_addr) 1273 pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); 1274 } 1275 1276 static struct intel_uncore_ops tgl_uncore_imc_freerunning_ops = { 1277 .init_box = tgl_uncore_imc_freerunning_init_box, 1278 .exit_box = uncore_mmio_exit_box, 1279 .read_counter = uncore_mmio_read_counter, 1280 .hw_config = uncore_freerunning_hw_config, 1281 }; 1282 1283 static struct attribute *tgl_uncore_imc_formats_attr[] = { 1284 &format_attr_event.attr, 1285 &format_attr_umask.attr, 1286 NULL 1287 }; 1288 1289 static const struct attribute_group tgl_uncore_imc_format_group = { 1290 .name = "format", 1291 .attrs = tgl_uncore_imc_formats_attr, 1292 }; 1293 1294 static struct intel_uncore_type tgl_uncore_imc_free_running = { 1295 .name = "imc_free_running", 1296 .num_counters = 3, 1297 .num_boxes = 2, 1298 .num_freerunning_types = TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX, 1299 .mmio_map_size = TGL_UNCORE_PCI_IMC_MAP_SIZE, 1300 .freerunning = tgl_uncore_imc_freerunning, 1301 .ops = &tgl_uncore_imc_freerunning_ops, 1302 .event_descs = tgl_uncore_imc_events, 1303 .format_group = &tgl_uncore_imc_format_group, 1304 }; 1305 1306 static struct intel_uncore_type *tgl_mmio_uncores[] = { 1307 &tgl_uncore_imc_free_running, 1308 NULL 1309 }; 1310 1311 void tgl_l_uncore_mmio_init(void) 1312 { 1313 tgl_uncore_imc_free_running.freerunning = tgl_l_uncore_imc_freerunning; 1314 uncore_mmio_uncores = tgl_mmio_uncores; 1315 } 1316 1317 void tgl_uncore_mmio_init(void) 1318 { 1319 uncore_mmio_uncores = tgl_mmio_uncores; 1320 } 1321 1322 /* end of Tiger Lake MMIO uncore support */ 1323