1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /* Generic device ID of a discovery table device */
4 #define UNCORE_DISCOVERY_TABLE_DEVICE		0x09a7
5 /* Capability ID for a discovery table device */
6 #define UNCORE_EXT_CAP_ID_DISCOVERY		0x23
7 /* First DVSEC offset */
8 #define UNCORE_DISCOVERY_DVSEC_OFFSET		0x8
9 /* Mask of the supported discovery entry type */
10 #define UNCORE_DISCOVERY_DVSEC_ID_MASK		0xffff
11 /* PMON discovery entry type ID */
12 #define UNCORE_DISCOVERY_DVSEC_ID_PMON		0x1
13 /* Second DVSEC offset */
14 #define UNCORE_DISCOVERY_DVSEC2_OFFSET		0xc
15 /* Mask of the discovery table BAR offset */
16 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK	0x7
17 /* Discovery table BAR base offset */
18 #define UNCORE_DISCOVERY_BIR_BASE		0x10
19 /* Discovery table BAR step */
20 #define UNCORE_DISCOVERY_BIR_STEP		0x4
21 /* Mask of the discovery table offset */
22 #define UNCORE_DISCOVERY_MASK			0xf
23 /* Global discovery table size */
24 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE	0x20
25 
26 #define UNCORE_DISCOVERY_PCI_DOMAIN(data)	((data >> 28) & 0x7)
27 #define UNCORE_DISCOVERY_PCI_BUS(data)		((data >> 20) & 0xff)
28 #define UNCORE_DISCOVERY_PCI_DEVFN(data)	((data >> 12) & 0xff)
29 #define UNCORE_DISCOVERY_PCI_BOX_CTRL(data)	(data & 0xfff)
30 
31 
32 #define uncore_discovery_invalid_unit(unit)			\
33 	(!unit.table1 || !unit.ctl || \
34 	 unit.table1 == -1ULL || unit.ctl == -1ULL ||	\
35 	 unit.table3 == -1ULL)
36 
37 #define GENERIC_PMON_CTL_EV_SEL_MASK	0x000000ff
38 #define GENERIC_PMON_CTL_UMASK_MASK	0x0000ff00
39 #define GENERIC_PMON_CTL_EDGE_DET	(1 << 18)
40 #define GENERIC_PMON_CTL_INVERT		(1 << 23)
41 #define GENERIC_PMON_CTL_TRESH_MASK	0xff000000
42 #define GENERIC_PMON_RAW_EVENT_MASK	(GENERIC_PMON_CTL_EV_SEL_MASK | \
43 					 GENERIC_PMON_CTL_UMASK_MASK | \
44 					 GENERIC_PMON_CTL_EDGE_DET | \
45 					 GENERIC_PMON_CTL_INVERT | \
46 					 GENERIC_PMON_CTL_TRESH_MASK)
47 
48 #define GENERIC_PMON_BOX_CTL_FRZ	(1 << 0)
49 #define GENERIC_PMON_BOX_CTL_RST_CTRL	(1 << 8)
50 #define GENERIC_PMON_BOX_CTL_RST_CTRS	(1 << 9)
51 #define GENERIC_PMON_BOX_CTL_INT	(GENERIC_PMON_BOX_CTL_RST_CTRL | \
52 					 GENERIC_PMON_BOX_CTL_RST_CTRS)
53 
54 enum uncore_access_type {
55 	UNCORE_ACCESS_MSR	= 0,
56 	UNCORE_ACCESS_MMIO,
57 	UNCORE_ACCESS_PCI,
58 
59 	UNCORE_ACCESS_MAX,
60 };
61 
62 struct uncore_global_discovery {
63 	union {
64 		u64	table1;
65 		struct {
66 			u64	type : 8,
67 				stride : 8,
68 				max_units : 10,
69 				__reserved_1 : 36,
70 				access_type : 2;
71 		};
72 	};
73 
74 	u64	ctl;		/* Global Control Address */
75 
76 	union {
77 		u64	table3;
78 		struct {
79 			u64	status_offset : 8,
80 				num_status : 16,
81 				__reserved_2 : 40;
82 		};
83 	};
84 };
85 
86 struct uncore_unit_discovery {
87 	union {
88 		u64	table1;
89 		struct {
90 			u64	num_regs : 8,
91 				ctl_offset : 8,
92 				bit_width : 8,
93 				ctr_offset : 8,
94 				status_offset : 8,
95 				__reserved_1 : 22,
96 				access_type : 2;
97 			};
98 		};
99 
100 	u64	ctl;		/* Unit Control Address */
101 
102 	union {
103 		u64	table3;
104 		struct {
105 			u64	box_type : 16,
106 				box_id : 16,
107 				__reserved_2 : 32;
108 		};
109 	};
110 };
111 
112 struct intel_uncore_discovery_type {
113 	struct rb_node	node;
114 	enum uncore_access_type	access_type;
115 	u64		box_ctrl;	/* Unit ctrl addr of the first box */
116 	u64		*box_ctrl_die;	/* Unit ctrl addr of the first box of each die */
117 	u16		type;		/* Type ID of the uncore block */
118 	u8		num_counters;
119 	u8		counter_width;
120 	u8		ctl_offset;	/* Counter Control 0 offset */
121 	u8		ctr_offset;	/* Counter 0 offset */
122 	u16		num_boxes;	/* number of boxes for the uncore block */
123 	unsigned int	*ids;		/* Box IDs */
124 	unsigned int	*box_offset;	/* Box offset */
125 };
126 
127 bool intel_uncore_has_discovery_tables(void);
128 void intel_uncore_clear_discovery_tables(void);
129 void intel_uncore_generic_uncore_cpu_init(void);
130 int intel_uncore_generic_uncore_pci_init(void);
131 void intel_uncore_generic_uncore_mmio_init(void);
132 
133 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);
134 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);
135 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);
136 
137 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box);
138 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box);
139 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
140 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
141 					     struct perf_event *event);
142 
143 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
144 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
145 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
146 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
147 					    struct perf_event *event);
148 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
149 					  struct perf_event *event);
150 
151 struct intel_uncore_type **
152 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra);
153