1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Generic device ID of a discovery table device */ 4 #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7 5 /* Capability ID for a discovery table device */ 6 #define UNCORE_EXT_CAP_ID_DISCOVERY 0x23 7 /* First DVSEC offset */ 8 #define UNCORE_DISCOVERY_DVSEC_OFFSET 0x8 9 /* Mask of the supported discovery entry type */ 10 #define UNCORE_DISCOVERY_DVSEC_ID_MASK 0xffff 11 /* PMON discovery entry type ID */ 12 #define UNCORE_DISCOVERY_DVSEC_ID_PMON 0x1 13 /* Second DVSEC offset */ 14 #define UNCORE_DISCOVERY_DVSEC2_OFFSET 0xc 15 /* Mask of the discovery table BAR offset */ 16 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK 0x7 17 /* Discovery table BAR base offset */ 18 #define UNCORE_DISCOVERY_BIR_BASE 0x10 19 /* Discovery table BAR step */ 20 #define UNCORE_DISCOVERY_BIR_STEP 0x4 21 /* Global discovery table size */ 22 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20 23 24 #define UNCORE_DISCOVERY_PCI_DOMAIN(data) ((data >> 28) & 0x7) 25 #define UNCORE_DISCOVERY_PCI_BUS(data) ((data >> 20) & 0xff) 26 #define UNCORE_DISCOVERY_PCI_DEVFN(data) ((data >> 12) & 0xff) 27 #define UNCORE_DISCOVERY_PCI_BOX_CTRL(data) (data & 0xfff) 28 29 30 #define uncore_discovery_invalid_unit(unit) \ 31 (!unit.table1 || !unit.ctl || \ 32 unit.table1 == -1ULL || unit.ctl == -1ULL || \ 33 unit.table3 == -1ULL) 34 35 #define GENERIC_PMON_CTL_EV_SEL_MASK 0x000000ff 36 #define GENERIC_PMON_CTL_UMASK_MASK 0x0000ff00 37 #define GENERIC_PMON_CTL_EDGE_DET (1 << 18) 38 #define GENERIC_PMON_CTL_INVERT (1 << 23) 39 #define GENERIC_PMON_CTL_TRESH_MASK 0xff000000 40 #define GENERIC_PMON_RAW_EVENT_MASK (GENERIC_PMON_CTL_EV_SEL_MASK | \ 41 GENERIC_PMON_CTL_UMASK_MASK | \ 42 GENERIC_PMON_CTL_EDGE_DET | \ 43 GENERIC_PMON_CTL_INVERT | \ 44 GENERIC_PMON_CTL_TRESH_MASK) 45 46 #define GENERIC_PMON_BOX_CTL_FRZ (1 << 0) 47 #define GENERIC_PMON_BOX_CTL_RST_CTRL (1 << 8) 48 #define GENERIC_PMON_BOX_CTL_RST_CTRS (1 << 9) 49 #define GENERIC_PMON_BOX_CTL_INT (GENERIC_PMON_BOX_CTL_RST_CTRL | \ 50 GENERIC_PMON_BOX_CTL_RST_CTRS) 51 52 enum uncore_access_type { 53 UNCORE_ACCESS_MSR = 0, 54 UNCORE_ACCESS_MMIO, 55 UNCORE_ACCESS_PCI, 56 57 UNCORE_ACCESS_MAX, 58 }; 59 60 struct uncore_global_discovery { 61 union { 62 u64 table1; 63 struct { 64 u64 type : 8, 65 stride : 8, 66 max_units : 10, 67 __reserved_1 : 36, 68 access_type : 2; 69 }; 70 }; 71 72 u64 ctl; /* Global Control Address */ 73 74 union { 75 u64 table3; 76 struct { 77 u64 status_offset : 8, 78 num_status : 16, 79 __reserved_2 : 40; 80 }; 81 }; 82 }; 83 84 struct uncore_unit_discovery { 85 union { 86 u64 table1; 87 struct { 88 u64 num_regs : 8, 89 ctl_offset : 8, 90 bit_width : 8, 91 ctr_offset : 8, 92 status_offset : 8, 93 __reserved_1 : 22, 94 access_type : 2; 95 }; 96 }; 97 98 u64 ctl; /* Unit Control Address */ 99 100 union { 101 u64 table3; 102 struct { 103 u64 box_type : 16, 104 box_id : 16, 105 __reserved_2 : 32; 106 }; 107 }; 108 }; 109 110 struct intel_uncore_discovery_type { 111 struct rb_node node; 112 enum uncore_access_type access_type; 113 u64 box_ctrl; /* Unit ctrl addr of the first box */ 114 u64 *box_ctrl_die; /* Unit ctrl addr of the first box of each die */ 115 u16 type; /* Type ID of the uncore block */ 116 u8 num_counters; 117 u8 counter_width; 118 u8 ctl_offset; /* Counter Control 0 offset */ 119 u8 ctr_offset; /* Counter 0 offset */ 120 u16 num_boxes; /* number of boxes for the uncore block */ 121 unsigned int *ids; /* Box IDs */ 122 unsigned int *box_offset; /* Box offset */ 123 }; 124 125 bool intel_uncore_has_discovery_tables(void); 126 void intel_uncore_clear_discovery_tables(void); 127 void intel_uncore_generic_uncore_cpu_init(void); 128 int intel_uncore_generic_uncore_pci_init(void); 129 void intel_uncore_generic_uncore_mmio_init(void); 130 131 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box); 132 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box); 133 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box); 134 135 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box); 136 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box); 137 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box); 138 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box, 139 struct perf_event *event); 140 void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box, 141 struct perf_event *event); 142 143 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box); 144 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box); 145 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box); 146 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box, 147 struct perf_event *event); 148 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box, 149 struct perf_event *event); 150 151 struct intel_uncore_type ** 152 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra); 153