1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #include <linux/slab.h> 3 #include <linux/pci.h> 4 #include <asm/apicdef.h> 5 #include <linux/io-64-nonatomic-lo-hi.h> 6 7 #include <linux/perf_event.h> 8 #include "../perf_event.h" 9 10 #define UNCORE_PMU_NAME_LEN 32 11 #define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC) 12 #define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC) 13 14 #define UNCORE_FIXED_EVENT 0xff 15 #define UNCORE_PMC_IDX_MAX_GENERIC 8 16 #define UNCORE_PMC_IDX_MAX_FIXED 1 17 #define UNCORE_PMC_IDX_MAX_FREERUNNING 1 18 #define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC 19 #define UNCORE_PMC_IDX_FREERUNNING (UNCORE_PMC_IDX_FIXED + \ 20 UNCORE_PMC_IDX_MAX_FIXED) 21 #define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FREERUNNING + \ 22 UNCORE_PMC_IDX_MAX_FREERUNNING) 23 24 #define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \ 25 ((dev << 24) | (func << 16) | (type << 8) | idx) 26 #define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) | idx) 27 #define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff) 28 #define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff) 29 #define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff) 30 #define UNCORE_PCI_DEV_IDX(data) (data & 0xff) 31 #define UNCORE_EXTRA_PCI_DEV 0xff 32 #define UNCORE_EXTRA_PCI_DEV_MAX 4 33 34 #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff) 35 36 struct pci_extra_dev { 37 struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX]; 38 }; 39 40 struct intel_uncore_ops; 41 struct intel_uncore_pmu; 42 struct intel_uncore_box; 43 struct uncore_event_desc; 44 struct freerunning_counters; 45 46 struct intel_uncore_type { 47 const char *name; 48 int num_counters; 49 int num_boxes; 50 int perf_ctr_bits; 51 int fixed_ctr_bits; 52 int num_freerunning_types; 53 unsigned perf_ctr; 54 unsigned event_ctl; 55 unsigned event_mask; 56 unsigned event_mask_ext; 57 unsigned fixed_ctr; 58 unsigned fixed_ctl; 59 unsigned box_ctl; 60 union { 61 unsigned msr_offset; 62 unsigned mmio_offset; 63 }; 64 unsigned mmio_map_size; 65 unsigned num_shared_regs:8; 66 unsigned single_fixed:1; 67 unsigned pair_ctr_ctl:1; 68 unsigned *msr_offsets; 69 struct event_constraint unconstrainted; 70 struct event_constraint *constraints; 71 struct intel_uncore_pmu *pmus; 72 struct intel_uncore_ops *ops; 73 struct uncore_event_desc *event_descs; 74 struct freerunning_counters *freerunning; 75 const struct attribute_group *attr_groups[4]; 76 const struct attribute_group **attr_update; 77 struct pmu *pmu; /* for custom pmu ops */ 78 /* 79 * Uncore PMU would store relevant platform topology configuration here 80 * to identify which platform component each PMON block of that type is 81 * supposed to monitor. 82 */ 83 u64 *topology; 84 /* 85 * Optional callbacks for managing mapping of Uncore units to PMONs 86 */ 87 int (*set_mapping)(struct intel_uncore_type *type); 88 void (*cleanup_mapping)(struct intel_uncore_type *type); 89 }; 90 91 #define pmu_group attr_groups[0] 92 #define format_group attr_groups[1] 93 #define events_group attr_groups[2] 94 95 struct intel_uncore_ops { 96 void (*init_box)(struct intel_uncore_box *); 97 void (*exit_box)(struct intel_uncore_box *); 98 void (*disable_box)(struct intel_uncore_box *); 99 void (*enable_box)(struct intel_uncore_box *); 100 void (*disable_event)(struct intel_uncore_box *, struct perf_event *); 101 void (*enable_event)(struct intel_uncore_box *, struct perf_event *); 102 u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *); 103 int (*hw_config)(struct intel_uncore_box *, struct perf_event *); 104 struct event_constraint *(*get_constraint)(struct intel_uncore_box *, 105 struct perf_event *); 106 void (*put_constraint)(struct intel_uncore_box *, struct perf_event *); 107 }; 108 109 struct intel_uncore_pmu { 110 struct pmu pmu; 111 char name[UNCORE_PMU_NAME_LEN]; 112 int pmu_idx; 113 int func_id; 114 bool registered; 115 atomic_t activeboxes; 116 struct intel_uncore_type *type; 117 struct intel_uncore_box **boxes; 118 }; 119 120 struct intel_uncore_extra_reg { 121 raw_spinlock_t lock; 122 u64 config, config1, config2; 123 atomic_t ref; 124 }; 125 126 struct intel_uncore_box { 127 int dieid; /* Logical die ID */ 128 int n_active; /* number of active events */ 129 int n_events; 130 int cpu; /* cpu to collect events */ 131 unsigned long flags; 132 atomic_t refcnt; 133 struct perf_event *events[UNCORE_PMC_IDX_MAX]; 134 struct perf_event *event_list[UNCORE_PMC_IDX_MAX]; 135 struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX]; 136 unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; 137 u64 tags[UNCORE_PMC_IDX_MAX]; 138 struct pci_dev *pci_dev; 139 struct intel_uncore_pmu *pmu; 140 u64 hrtimer_duration; /* hrtimer timeout for this box */ 141 struct hrtimer hrtimer; 142 struct list_head list; 143 struct list_head active_list; 144 void __iomem *io_addr; 145 struct intel_uncore_extra_reg shared_regs[]; 146 }; 147 148 /* CFL uncore 8th cbox MSRs */ 149 #define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70 150 #define CFL_UNC_CBO_7_PER_CTR0 0xf76 151 152 #define UNCORE_BOX_FLAG_INITIATED 0 153 /* event config registers are 8-byte apart */ 154 #define UNCORE_BOX_FLAG_CTL_OFFS8 1 155 /* CFL 8th CBOX has different MSR space */ 156 #define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS 2 157 158 struct uncore_event_desc { 159 struct device_attribute attr; 160 const char *config; 161 }; 162 163 struct freerunning_counters { 164 unsigned int counter_base; 165 unsigned int counter_offset; 166 unsigned int box_offset; 167 unsigned int num_counters; 168 unsigned int bits; 169 unsigned *box_offsets; 170 }; 171 172 struct pci2phy_map { 173 struct list_head list; 174 int segment; 175 int pbus_to_dieid[256]; 176 }; 177 178 struct pci2phy_map *__find_pci2phy_map(int segment); 179 int uncore_pcibus_to_dieid(struct pci_bus *bus); 180 181 ssize_t uncore_event_show(struct device *dev, 182 struct device_attribute *attr, char *buf); 183 184 static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev) 185 { 186 return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu); 187 } 188 189 #define to_device_attribute(n) container_of(n, struct device_attribute, attr) 190 #define to_dev_ext_attribute(n) container_of(n, struct dev_ext_attribute, attr) 191 #define attr_to_ext_attr(n) to_dev_ext_attribute(to_device_attribute(n)) 192 193 extern int __uncore_max_dies; 194 #define uncore_max_dies() (__uncore_max_dies) 195 196 #define INTEL_UNCORE_EVENT_DESC(_name, _config) \ 197 { \ 198 .attr = __ATTR(_name, 0444, uncore_event_show, NULL), \ 199 .config = _config, \ 200 } 201 202 #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \ 203 static ssize_t __uncore_##_var##_show(struct device *dev, \ 204 struct device_attribute *attr, \ 205 char *page) \ 206 { \ 207 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ 208 return sprintf(page, _format "\n"); \ 209 } \ 210 static struct device_attribute format_attr_##_var = \ 211 __ATTR(_name, 0444, __uncore_##_var##_show, NULL) 212 213 static inline bool uncore_pmc_fixed(int idx) 214 { 215 return idx == UNCORE_PMC_IDX_FIXED; 216 } 217 218 static inline bool uncore_pmc_freerunning(int idx) 219 { 220 return idx == UNCORE_PMC_IDX_FREERUNNING; 221 } 222 223 static inline bool uncore_mmio_is_valid_offset(struct intel_uncore_box *box, 224 unsigned long offset) 225 { 226 if (offset < box->pmu->type->mmio_map_size) 227 return true; 228 229 pr_warn_once("perf uncore: Invalid offset 0x%lx exceeds mapped area of %s.\n", 230 offset, box->pmu->type->name); 231 232 return false; 233 } 234 235 static inline 236 unsigned int uncore_mmio_box_ctl(struct intel_uncore_box *box) 237 { 238 return box->pmu->type->box_ctl + 239 box->pmu->type->mmio_offset * box->pmu->pmu_idx; 240 } 241 242 static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box) 243 { 244 return box->pmu->type->box_ctl; 245 } 246 247 static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box) 248 { 249 return box->pmu->type->fixed_ctl; 250 } 251 252 static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box) 253 { 254 return box->pmu->type->fixed_ctr; 255 } 256 257 static inline 258 unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx) 259 { 260 if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags)) 261 return idx * 8 + box->pmu->type->event_ctl; 262 263 return idx * 4 + box->pmu->type->event_ctl; 264 } 265 266 static inline 267 unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx) 268 { 269 return idx * 8 + box->pmu->type->perf_ctr; 270 } 271 272 static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box) 273 { 274 struct intel_uncore_pmu *pmu = box->pmu; 275 return pmu->type->msr_offsets ? 276 pmu->type->msr_offsets[pmu->pmu_idx] : 277 pmu->type->msr_offset * pmu->pmu_idx; 278 } 279 280 static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box) 281 { 282 if (!box->pmu->type->box_ctl) 283 return 0; 284 return box->pmu->type->box_ctl + uncore_msr_box_offset(box); 285 } 286 287 static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box) 288 { 289 if (!box->pmu->type->fixed_ctl) 290 return 0; 291 return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box); 292 } 293 294 static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box) 295 { 296 return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box); 297 } 298 299 300 /* 301 * In the uncore document, there is no event-code assigned to free running 302 * counters. Some events need to be defined to indicate the free running 303 * counters. The events are encoded as event-code + umask-code. 304 * 305 * The event-code for all free running counters is 0xff, which is the same as 306 * the fixed counters. 307 * 308 * The umask-code is used to distinguish a fixed counter and a free running 309 * counter, and different types of free running counters. 310 * - For fixed counters, the umask-code is 0x0X. 311 * X indicates the index of the fixed counter, which starts from 0. 312 * - For free running counters, the umask-code uses the rest of the space. 313 * It would bare the format of 0xXY. 314 * X stands for the type of free running counters, which starts from 1. 315 * Y stands for the index of free running counters of same type, which 316 * starts from 0. 317 * 318 * For example, there are three types of IIO free running counters on Skylake 319 * server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters. 320 * The event-code for all the free running counters is 0xff. 321 * 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type, 322 * which umask-code starts from 0x10. 323 * So 'ioclk' is encoded as event=0xff,umask=0x10 324 * 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is 325 * the second type, which umask-code starts from 0x20. 326 * So 'bw_in_port2' is encoded as event=0xff,umask=0x22 327 */ 328 static inline unsigned int uncore_freerunning_idx(u64 config) 329 { 330 return ((config >> 8) & 0xf); 331 } 332 333 #define UNCORE_FREERUNNING_UMASK_START 0x10 334 335 static inline unsigned int uncore_freerunning_type(u64 config) 336 { 337 return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf); 338 } 339 340 static inline 341 unsigned int uncore_freerunning_counter(struct intel_uncore_box *box, 342 struct perf_event *event) 343 { 344 unsigned int type = uncore_freerunning_type(event->hw.config); 345 unsigned int idx = uncore_freerunning_idx(event->hw.config); 346 struct intel_uncore_pmu *pmu = box->pmu; 347 348 return pmu->type->freerunning[type].counter_base + 349 pmu->type->freerunning[type].counter_offset * idx + 350 (pmu->type->freerunning[type].box_offsets ? 351 pmu->type->freerunning[type].box_offsets[pmu->pmu_idx] : 352 pmu->type->freerunning[type].box_offset * pmu->pmu_idx); 353 } 354 355 static inline 356 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx) 357 { 358 if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) { 359 return CFL_UNC_CBO_7_PERFEVTSEL0 + 360 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx); 361 } else { 362 return box->pmu->type->event_ctl + 363 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 364 uncore_msr_box_offset(box); 365 } 366 } 367 368 static inline 369 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx) 370 { 371 if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) { 372 return CFL_UNC_CBO_7_PER_CTR0 + 373 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx); 374 } else { 375 return box->pmu->type->perf_ctr + 376 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 377 uncore_msr_box_offset(box); 378 } 379 } 380 381 static inline 382 unsigned uncore_fixed_ctl(struct intel_uncore_box *box) 383 { 384 if (box->pci_dev || box->io_addr) 385 return uncore_pci_fixed_ctl(box); 386 else 387 return uncore_msr_fixed_ctl(box); 388 } 389 390 static inline 391 unsigned uncore_fixed_ctr(struct intel_uncore_box *box) 392 { 393 if (box->pci_dev || box->io_addr) 394 return uncore_pci_fixed_ctr(box); 395 else 396 return uncore_msr_fixed_ctr(box); 397 } 398 399 static inline 400 unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx) 401 { 402 if (box->pci_dev || box->io_addr) 403 return uncore_pci_event_ctl(box, idx); 404 else 405 return uncore_msr_event_ctl(box, idx); 406 } 407 408 static inline 409 unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx) 410 { 411 if (box->pci_dev || box->io_addr) 412 return uncore_pci_perf_ctr(box, idx); 413 else 414 return uncore_msr_perf_ctr(box, idx); 415 } 416 417 static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box) 418 { 419 return box->pmu->type->perf_ctr_bits; 420 } 421 422 static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box) 423 { 424 return box->pmu->type->fixed_ctr_bits; 425 } 426 427 static inline 428 unsigned int uncore_freerunning_bits(struct intel_uncore_box *box, 429 struct perf_event *event) 430 { 431 unsigned int type = uncore_freerunning_type(event->hw.config); 432 433 return box->pmu->type->freerunning[type].bits; 434 } 435 436 static inline int uncore_num_freerunning(struct intel_uncore_box *box, 437 struct perf_event *event) 438 { 439 unsigned int type = uncore_freerunning_type(event->hw.config); 440 441 return box->pmu->type->freerunning[type].num_counters; 442 } 443 444 static inline int uncore_num_freerunning_types(struct intel_uncore_box *box, 445 struct perf_event *event) 446 { 447 return box->pmu->type->num_freerunning_types; 448 } 449 450 static inline bool check_valid_freerunning_event(struct intel_uncore_box *box, 451 struct perf_event *event) 452 { 453 unsigned int type = uncore_freerunning_type(event->hw.config); 454 unsigned int idx = uncore_freerunning_idx(event->hw.config); 455 456 return (type < uncore_num_freerunning_types(box, event)) && 457 (idx < uncore_num_freerunning(box, event)); 458 } 459 460 static inline int uncore_num_counters(struct intel_uncore_box *box) 461 { 462 return box->pmu->type->num_counters; 463 } 464 465 static inline bool is_freerunning_event(struct perf_event *event) 466 { 467 u64 cfg = event->attr.config; 468 469 return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) && 470 (((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START); 471 } 472 473 /* Check and reject invalid config */ 474 static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box, 475 struct perf_event *event) 476 { 477 if (is_freerunning_event(event)) 478 return 0; 479 480 return -EINVAL; 481 } 482 483 static inline void uncore_disable_event(struct intel_uncore_box *box, 484 struct perf_event *event) 485 { 486 box->pmu->type->ops->disable_event(box, event); 487 } 488 489 static inline void uncore_enable_event(struct intel_uncore_box *box, 490 struct perf_event *event) 491 { 492 box->pmu->type->ops->enable_event(box, event); 493 } 494 495 static inline u64 uncore_read_counter(struct intel_uncore_box *box, 496 struct perf_event *event) 497 { 498 return box->pmu->type->ops->read_counter(box, event); 499 } 500 501 static inline void uncore_box_init(struct intel_uncore_box *box) 502 { 503 if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) { 504 if (box->pmu->type->ops->init_box) 505 box->pmu->type->ops->init_box(box); 506 } 507 } 508 509 static inline void uncore_box_exit(struct intel_uncore_box *box) 510 { 511 if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) { 512 if (box->pmu->type->ops->exit_box) 513 box->pmu->type->ops->exit_box(box); 514 } 515 } 516 517 static inline bool uncore_box_is_fake(struct intel_uncore_box *box) 518 { 519 return (box->dieid < 0); 520 } 521 522 static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event) 523 { 524 return container_of(event->pmu, struct intel_uncore_pmu, pmu); 525 } 526 527 static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event) 528 { 529 return event->pmu_private; 530 } 531 532 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu); 533 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event); 534 void uncore_mmio_exit_box(struct intel_uncore_box *box); 535 u64 uncore_mmio_read_counter(struct intel_uncore_box *box, 536 struct perf_event *event); 537 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box); 538 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box); 539 void uncore_pmu_event_start(struct perf_event *event, int flags); 540 void uncore_pmu_event_stop(struct perf_event *event, int flags); 541 int uncore_pmu_event_add(struct perf_event *event, int flags); 542 void uncore_pmu_event_del(struct perf_event *event, int flags); 543 void uncore_pmu_event_read(struct perf_event *event); 544 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event); 545 struct event_constraint * 546 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event); 547 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event); 548 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx); 549 550 extern struct intel_uncore_type **uncore_msr_uncores; 551 extern struct intel_uncore_type **uncore_pci_uncores; 552 extern struct intel_uncore_type **uncore_mmio_uncores; 553 extern struct pci_driver *uncore_pci_driver; 554 extern struct pci_driver *uncore_pci_sub_driver; 555 extern raw_spinlock_t pci2phy_map_lock; 556 extern struct list_head pci2phy_map_head; 557 extern struct pci_extra_dev *uncore_extra_pci_dev; 558 extern struct event_constraint uncore_constraint_empty; 559 560 /* uncore_snb.c */ 561 int snb_uncore_pci_init(void); 562 int ivb_uncore_pci_init(void); 563 int hsw_uncore_pci_init(void); 564 int bdw_uncore_pci_init(void); 565 int skl_uncore_pci_init(void); 566 void snb_uncore_cpu_init(void); 567 void nhm_uncore_cpu_init(void); 568 void skl_uncore_cpu_init(void); 569 void icl_uncore_cpu_init(void); 570 void tgl_uncore_cpu_init(void); 571 void tgl_uncore_mmio_init(void); 572 void tgl_l_uncore_mmio_init(void); 573 int snb_pci2phy_map_init(int devid); 574 575 /* uncore_snbep.c */ 576 int snbep_uncore_pci_init(void); 577 void snbep_uncore_cpu_init(void); 578 int ivbep_uncore_pci_init(void); 579 void ivbep_uncore_cpu_init(void); 580 int hswep_uncore_pci_init(void); 581 void hswep_uncore_cpu_init(void); 582 int bdx_uncore_pci_init(void); 583 void bdx_uncore_cpu_init(void); 584 int knl_uncore_pci_init(void); 585 void knl_uncore_cpu_init(void); 586 int skx_uncore_pci_init(void); 587 void skx_uncore_cpu_init(void); 588 int snr_uncore_pci_init(void); 589 void snr_uncore_cpu_init(void); 590 void snr_uncore_mmio_init(void); 591 int icx_uncore_pci_init(void); 592 void icx_uncore_cpu_init(void); 593 void icx_uncore_mmio_init(void); 594 595 /* uncore_nhmex.c */ 596 void nhmex_uncore_cpu_init(void); 597