1 /* 2 * Intel(R) Processor Trace PMU driver for perf 3 * Copyright (c) 2013-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 15 * Programming Reference: 16 * http://software.intel.com/en-us/intel-isa-extensions 17 */ 18 19 #ifndef __INTEL_PT_H__ 20 #define __INTEL_PT_H__ 21 22 /* 23 * PT MSR bit definitions 24 */ 25 #define RTIT_CTL_TRACEEN BIT(0) 26 #define RTIT_CTL_CYCLEACC BIT(1) 27 #define RTIT_CTL_OS BIT(2) 28 #define RTIT_CTL_USR BIT(3) 29 #define RTIT_CTL_CR3EN BIT(7) 30 #define RTIT_CTL_TOPA BIT(8) 31 #define RTIT_CTL_MTC_EN BIT(9) 32 #define RTIT_CTL_TSC_EN BIT(10) 33 #define RTIT_CTL_DISRETC BIT(11) 34 #define RTIT_CTL_BRANCH_EN BIT(13) 35 #define RTIT_CTL_MTC_RANGE_OFFSET 14 36 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 37 #define RTIT_CTL_CYC_THRESH_OFFSET 19 38 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 39 #define RTIT_CTL_PSB_FREQ_OFFSET 24 40 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 41 #define RTIT_CTL_ADDR0_OFFSET 32 42 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 43 #define RTIT_CTL_ADDR1_OFFSET 36 44 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 45 #define RTIT_CTL_ADDR2_OFFSET 40 46 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 47 #define RTIT_CTL_ADDR3_OFFSET 44 48 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 49 #define RTIT_STATUS_FILTEREN BIT(0) 50 #define RTIT_STATUS_CONTEXTEN BIT(1) 51 #define RTIT_STATUS_TRIGGEREN BIT(2) 52 #define RTIT_STATUS_BUFFOVF BIT(3) 53 #define RTIT_STATUS_ERROR BIT(4) 54 #define RTIT_STATUS_STOPPED BIT(5) 55 56 /* 57 * Single-entry ToPA: when this close to region boundary, switch 58 * buffers to avoid losing data. 59 */ 60 #define TOPA_PMI_MARGIN 512 61 62 #define TOPA_SHIFT 12 63 64 static inline unsigned int sizes(unsigned int tsz) 65 { 66 return 1 << (tsz + TOPA_SHIFT); 67 }; 68 69 struct topa_entry { 70 u64 end : 1; 71 u64 rsvd0 : 1; 72 u64 intr : 1; 73 u64 rsvd1 : 1; 74 u64 stop : 1; 75 u64 rsvd2 : 1; 76 u64 size : 4; 77 u64 rsvd3 : 2; 78 u64 base : 36; 79 u64 rsvd4 : 16; 80 }; 81 82 #define PT_CPUID_LEAVES 2 83 #define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ 84 85 /* TSC to Core Crystal Clock Ratio */ 86 #define CPUID_TSC_LEAF 0x15 87 88 enum pt_capabilities { 89 PT_CAP_max_subleaf = 0, 90 PT_CAP_cr3_filtering, 91 PT_CAP_psb_cyc, 92 PT_CAP_ip_filtering, 93 PT_CAP_mtc, 94 PT_CAP_topa_output, 95 PT_CAP_topa_multiple_entries, 96 PT_CAP_single_range_output, 97 PT_CAP_payloads_lip, 98 PT_CAP_num_address_ranges, 99 PT_CAP_mtc_periods, 100 PT_CAP_cycle_thresholds, 101 PT_CAP_psb_periods, 102 }; 103 104 struct pt_pmu { 105 struct pmu pmu; 106 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 107 bool vmx; 108 unsigned long max_nonturbo_ratio; 109 unsigned int tsc_art_num; 110 unsigned int tsc_art_den; 111 }; 112 113 /** 114 * struct pt_buffer - buffer configuration; one buffer per task_struct or 115 * cpu, depending on perf event configuration 116 * @cpu: cpu for per-cpu allocation 117 * @tables: list of ToPA tables in this buffer 118 * @first: shorthand for first topa table 119 * @last: shorthand for last topa table 120 * @cur: current topa table 121 * @nr_pages: buffer size in pages 122 * @cur_idx: current output region's index within @cur table 123 * @output_off: offset within the current output region 124 * @data_size: running total of the amount of data in this buffer 125 * @lost: if data was lost/truncated 126 * @head: logical write offset inside the buffer 127 * @snapshot: if this is for a snapshot/overwrite counter 128 * @stop_pos: STOP topa entry in the buffer 129 * @intr_pos: INT topa entry in the buffer 130 * @data_pages: array of pages from perf 131 * @topa_index: table of topa entries indexed by page offset 132 */ 133 struct pt_buffer { 134 int cpu; 135 struct list_head tables; 136 struct topa *first, *last, *cur; 137 unsigned int cur_idx; 138 size_t output_off; 139 unsigned long nr_pages; 140 local_t data_size; 141 local_t lost; 142 local64_t head; 143 bool snapshot; 144 unsigned long stop_pos, intr_pos; 145 void **data_pages; 146 struct topa_entry *topa_index[0]; 147 }; 148 149 #define PT_FILTERS_NUM 4 150 151 /** 152 * struct pt_filter - IP range filter configuration 153 * @msr_a: range start, goes to RTIT_ADDRn_A 154 * @msr_b: range end, goes to RTIT_ADDRn_B 155 * @config: 4-bit field in RTIT_CTL 156 */ 157 struct pt_filter { 158 unsigned long msr_a; 159 unsigned long msr_b; 160 unsigned long config; 161 }; 162 163 /** 164 * struct pt_filters - IP range filtering context 165 * @filter: filters defined for this context 166 * @nr_filters: number of defined filters in the @filter array 167 */ 168 struct pt_filters { 169 struct pt_filter filter[PT_FILTERS_NUM]; 170 unsigned int nr_filters; 171 }; 172 173 /** 174 * struct pt - per-cpu pt context 175 * @handle: perf output handle 176 * @filters: last configured filters 177 * @handle_nmi: do handle PT PMI on this cpu, there's an active event 178 * @vmx_on: 1 if VMX is ON on this cpu 179 */ 180 struct pt { 181 struct perf_output_handle handle; 182 struct pt_filters filters; 183 int handle_nmi; 184 int vmx_on; 185 }; 186 187 #endif /* __INTEL_PT_H__ */ 188