1 /* 2 * Intel(R) Processor Trace PMU driver for perf 3 * Copyright (c) 2013-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 15 * Programming Reference: 16 * http://software.intel.com/en-us/intel-isa-extensions 17 */ 18 19 #ifndef __INTEL_PT_H__ 20 #define __INTEL_PT_H__ 21 22 /* 23 * PT MSR bit definitions 24 */ 25 #define RTIT_CTL_TRACEEN BIT(0) 26 #define RTIT_CTL_CYCLEACC BIT(1) 27 #define RTIT_CTL_OS BIT(2) 28 #define RTIT_CTL_USR BIT(3) 29 #define RTIT_CTL_PWR_EVT_EN BIT(4) 30 #define RTIT_CTL_FUP_ON_PTW BIT(5) 31 #define RTIT_CTL_CR3EN BIT(7) 32 #define RTIT_CTL_TOPA BIT(8) 33 #define RTIT_CTL_MTC_EN BIT(9) 34 #define RTIT_CTL_TSC_EN BIT(10) 35 #define RTIT_CTL_DISRETC BIT(11) 36 #define RTIT_CTL_PTW_EN BIT(12) 37 #define RTIT_CTL_BRANCH_EN BIT(13) 38 #define RTIT_CTL_MTC_RANGE_OFFSET 14 39 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 40 #define RTIT_CTL_CYC_THRESH_OFFSET 19 41 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 42 #define RTIT_CTL_PSB_FREQ_OFFSET 24 43 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 44 #define RTIT_CTL_ADDR0_OFFSET 32 45 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 46 #define RTIT_CTL_ADDR1_OFFSET 36 47 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 48 #define RTIT_CTL_ADDR2_OFFSET 40 49 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 50 #define RTIT_CTL_ADDR3_OFFSET 44 51 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 52 #define RTIT_STATUS_FILTEREN BIT(0) 53 #define RTIT_STATUS_CONTEXTEN BIT(1) 54 #define RTIT_STATUS_TRIGGEREN BIT(2) 55 #define RTIT_STATUS_BUFFOVF BIT(3) 56 #define RTIT_STATUS_ERROR BIT(4) 57 #define RTIT_STATUS_STOPPED BIT(5) 58 59 /* 60 * Single-entry ToPA: when this close to region boundary, switch 61 * buffers to avoid losing data. 62 */ 63 #define TOPA_PMI_MARGIN 512 64 65 #define TOPA_SHIFT 12 66 67 static inline unsigned int sizes(unsigned int tsz) 68 { 69 return 1 << (tsz + TOPA_SHIFT); 70 }; 71 72 struct topa_entry { 73 u64 end : 1; 74 u64 rsvd0 : 1; 75 u64 intr : 1; 76 u64 rsvd1 : 1; 77 u64 stop : 1; 78 u64 rsvd2 : 1; 79 u64 size : 4; 80 u64 rsvd3 : 2; 81 u64 base : 36; 82 u64 rsvd4 : 16; 83 }; 84 85 #define PT_CPUID_LEAVES 2 86 #define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ 87 88 /* TSC to Core Crystal Clock Ratio */ 89 #define CPUID_TSC_LEAF 0x15 90 91 enum pt_capabilities { 92 PT_CAP_max_subleaf = 0, 93 PT_CAP_cr3_filtering, 94 PT_CAP_psb_cyc, 95 PT_CAP_ip_filtering, 96 PT_CAP_mtc, 97 PT_CAP_ptwrite, 98 PT_CAP_power_event_trace, 99 PT_CAP_topa_output, 100 PT_CAP_topa_multiple_entries, 101 PT_CAP_single_range_output, 102 PT_CAP_payloads_lip, 103 PT_CAP_num_address_ranges, 104 PT_CAP_mtc_periods, 105 PT_CAP_cycle_thresholds, 106 PT_CAP_psb_periods, 107 }; 108 109 struct pt_pmu { 110 struct pmu pmu; 111 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 112 bool vmx; 113 bool branch_en_always_on; 114 unsigned long max_nonturbo_ratio; 115 unsigned int tsc_art_num; 116 unsigned int tsc_art_den; 117 }; 118 119 /** 120 * struct pt_buffer - buffer configuration; one buffer per task_struct or 121 * cpu, depending on perf event configuration 122 * @cpu: cpu for per-cpu allocation 123 * @tables: list of ToPA tables in this buffer 124 * @first: shorthand for first topa table 125 * @last: shorthand for last topa table 126 * @cur: current topa table 127 * @nr_pages: buffer size in pages 128 * @cur_idx: current output region's index within @cur table 129 * @output_off: offset within the current output region 130 * @data_size: running total of the amount of data in this buffer 131 * @lost: if data was lost/truncated 132 * @head: logical write offset inside the buffer 133 * @snapshot: if this is for a snapshot/overwrite counter 134 * @stop_pos: STOP topa entry in the buffer 135 * @intr_pos: INT topa entry in the buffer 136 * @data_pages: array of pages from perf 137 * @topa_index: table of topa entries indexed by page offset 138 */ 139 struct pt_buffer { 140 int cpu; 141 struct list_head tables; 142 struct topa *first, *last, *cur; 143 unsigned int cur_idx; 144 size_t output_off; 145 unsigned long nr_pages; 146 local_t data_size; 147 local64_t head; 148 bool snapshot; 149 unsigned long stop_pos, intr_pos; 150 void **data_pages; 151 struct topa_entry *topa_index[0]; 152 }; 153 154 #define PT_FILTERS_NUM 4 155 156 /** 157 * struct pt_filter - IP range filter configuration 158 * @msr_a: range start, goes to RTIT_ADDRn_A 159 * @msr_b: range end, goes to RTIT_ADDRn_B 160 * @config: 4-bit field in RTIT_CTL 161 */ 162 struct pt_filter { 163 unsigned long msr_a; 164 unsigned long msr_b; 165 unsigned long config; 166 }; 167 168 /** 169 * struct pt_filters - IP range filtering context 170 * @filter: filters defined for this context 171 * @nr_filters: number of defined filters in the @filter array 172 */ 173 struct pt_filters { 174 struct pt_filter filter[PT_FILTERS_NUM]; 175 unsigned int nr_filters; 176 }; 177 178 /** 179 * struct pt - per-cpu pt context 180 * @handle: perf output handle 181 * @filters: last configured filters 182 * @handle_nmi: do handle PT PMI on this cpu, there's an active event 183 * @vmx_on: 1 if VMX is ON on this cpu 184 */ 185 struct pt { 186 struct perf_output_handle handle; 187 struct pt_filters filters; 188 int handle_nmi; 189 int vmx_on; 190 }; 191 192 #endif /* __INTEL_PT_H__ */ 193