1 /* 2 * Intel(R) Processor Trace PMU driver for perf 3 * Copyright (c) 2013-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions 15 * Programming Reference: 16 * http://software.intel.com/en-us/intel-isa-extensions 17 */ 18 19 #undef DEBUG 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/types.h> 24 #include <linux/slab.h> 25 #include <linux/device.h> 26 27 #include <asm/perf_event.h> 28 #include <asm/insn.h> 29 #include <asm/io.h> 30 #include <asm/intel_pt.h> 31 32 #include "../perf_event.h" 33 #include "pt.h" 34 35 static DEFINE_PER_CPU(struct pt, pt_ctx); 36 37 static struct pt_pmu pt_pmu; 38 39 /* 40 * Capabilities of Intel PT hardware, such as number of address bits or 41 * supported output schemes, are cached and exported to userspace as "caps" 42 * attribute group of pt pmu device 43 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store 44 * relevant bits together with intel_pt traces. 45 * 46 * These are necessary for both trace decoding (payloads_lip, contains address 47 * width encoded in IP-related packets), and event configuration (bitmasks with 48 * permitted values for certain bit fields). 49 */ 50 #define PT_CAP(_n, _l, _r, _m) \ 51 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \ 52 .reg = _r, .mask = _m } 53 54 static struct pt_cap_desc { 55 const char *name; 56 u32 leaf; 57 u8 reg; 58 u32 mask; 59 } pt_caps[] = { 60 PT_CAP(max_subleaf, 0, CPUID_EAX, 0xffffffff), 61 PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)), 62 PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)), 63 PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)), 64 PT_CAP(mtc, 0, CPUID_EBX, BIT(3)), 65 PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)), 66 PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)), 67 PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)), 68 PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)), 69 PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)), 70 PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)), 71 PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x3), 72 PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000), 73 PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff), 74 PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000), 75 }; 76 77 static u32 pt_cap_get(enum pt_capabilities cap) 78 { 79 struct pt_cap_desc *cd = &pt_caps[cap]; 80 u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; 81 unsigned int shift = __ffs(cd->mask); 82 83 return (c & cd->mask) >> shift; 84 } 85 86 static ssize_t pt_cap_show(struct device *cdev, 87 struct device_attribute *attr, 88 char *buf) 89 { 90 struct dev_ext_attribute *ea = 91 container_of(attr, struct dev_ext_attribute, attr); 92 enum pt_capabilities cap = (long)ea->var; 93 94 return snprintf(buf, PAGE_SIZE, "%x\n", pt_cap_get(cap)); 95 } 96 97 static struct attribute_group pt_cap_group = { 98 .name = "caps", 99 }; 100 101 PMU_FORMAT_ATTR(cyc, "config:1" ); 102 PMU_FORMAT_ATTR(mtc, "config:9" ); 103 PMU_FORMAT_ATTR(tsc, "config:10" ); 104 PMU_FORMAT_ATTR(noretcomp, "config:11" ); 105 PMU_FORMAT_ATTR(mtc_period, "config:14-17" ); 106 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" ); 107 PMU_FORMAT_ATTR(psb_period, "config:24-27" ); 108 109 static struct attribute *pt_formats_attr[] = { 110 &format_attr_cyc.attr, 111 &format_attr_mtc.attr, 112 &format_attr_tsc.attr, 113 &format_attr_noretcomp.attr, 114 &format_attr_mtc_period.attr, 115 &format_attr_cyc_thresh.attr, 116 &format_attr_psb_period.attr, 117 NULL, 118 }; 119 120 static struct attribute_group pt_format_group = { 121 .name = "format", 122 .attrs = pt_formats_attr, 123 }; 124 125 static ssize_t 126 pt_timing_attr_show(struct device *dev, struct device_attribute *attr, 127 char *page) 128 { 129 struct perf_pmu_events_attr *pmu_attr = 130 container_of(attr, struct perf_pmu_events_attr, attr); 131 132 switch (pmu_attr->id) { 133 case 0: 134 return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio); 135 case 1: 136 return sprintf(page, "%u:%u\n", 137 pt_pmu.tsc_art_num, 138 pt_pmu.tsc_art_den); 139 default: 140 break; 141 } 142 143 return -EINVAL; 144 } 145 146 PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0, 147 pt_timing_attr_show); 148 PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1, 149 pt_timing_attr_show); 150 151 static struct attribute *pt_timing_attr[] = { 152 &timing_attr_max_nonturbo_ratio.attr.attr, 153 &timing_attr_tsc_art_ratio.attr.attr, 154 NULL, 155 }; 156 157 static struct attribute_group pt_timing_group = { 158 .attrs = pt_timing_attr, 159 }; 160 161 static const struct attribute_group *pt_attr_groups[] = { 162 &pt_cap_group, 163 &pt_format_group, 164 &pt_timing_group, 165 NULL, 166 }; 167 168 static int __init pt_pmu_hw_init(void) 169 { 170 struct dev_ext_attribute *de_attrs; 171 struct attribute **attrs; 172 size_t size; 173 u64 reg; 174 int ret; 175 long i; 176 177 rdmsrl(MSR_PLATFORM_INFO, reg); 178 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8; 179 180 /* 181 * if available, read in TSC to core crystal clock ratio, 182 * otherwise, zero for numerator stands for "not enumerated" 183 * as per SDM 184 */ 185 if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) { 186 u32 eax, ebx, ecx, edx; 187 188 cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx); 189 190 pt_pmu.tsc_art_num = ebx; 191 pt_pmu.tsc_art_den = eax; 192 } 193 194 if (boot_cpu_has(X86_FEATURE_VMX)) { 195 /* 196 * Intel SDM, 36.5 "Tracing post-VMXON" says that 197 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace 198 * post-VMXON. 199 */ 200 rdmsrl(MSR_IA32_VMX_MISC, reg); 201 if (reg & BIT(14)) 202 pt_pmu.vmx = true; 203 } 204 205 attrs = NULL; 206 207 for (i = 0; i < PT_CPUID_LEAVES; i++) { 208 cpuid_count(20, i, 209 &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM], 210 &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM], 211 &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM], 212 &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]); 213 } 214 215 ret = -ENOMEM; 216 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1); 217 attrs = kzalloc(size, GFP_KERNEL); 218 if (!attrs) 219 goto fail; 220 221 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1); 222 de_attrs = kzalloc(size, GFP_KERNEL); 223 if (!de_attrs) 224 goto fail; 225 226 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) { 227 struct dev_ext_attribute *de_attr = de_attrs + i; 228 229 de_attr->attr.attr.name = pt_caps[i].name; 230 231 sysfs_attr_init(&de_attr->attr.attr); 232 233 de_attr->attr.attr.mode = S_IRUGO; 234 de_attr->attr.show = pt_cap_show; 235 de_attr->var = (void *)i; 236 237 attrs[i] = &de_attr->attr.attr; 238 } 239 240 pt_cap_group.attrs = attrs; 241 242 return 0; 243 244 fail: 245 kfree(attrs); 246 247 return ret; 248 } 249 250 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \ 251 RTIT_CTL_CYC_THRESH | \ 252 RTIT_CTL_PSB_FREQ) 253 254 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \ 255 RTIT_CTL_MTC_RANGE) 256 257 #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \ 258 RTIT_CTL_FUP_ON_PTW) 259 260 #define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ 261 RTIT_CTL_DISRETC | \ 262 RTIT_CTL_CYC_PSB | \ 263 RTIT_CTL_MTC | \ 264 RTIT_CTL_PWR_EVT_EN | \ 265 RTIT_CTL_FUP_ON_PTW | \ 266 RTIT_CTL_PTW_EN) 267 268 static bool pt_event_valid(struct perf_event *event) 269 { 270 u64 config = event->attr.config; 271 u64 allowed, requested; 272 273 if ((config & PT_CONFIG_MASK) != config) 274 return false; 275 276 if (config & RTIT_CTL_CYC_PSB) { 277 if (!pt_cap_get(PT_CAP_psb_cyc)) 278 return false; 279 280 allowed = pt_cap_get(PT_CAP_psb_periods); 281 requested = (config & RTIT_CTL_PSB_FREQ) >> 282 RTIT_CTL_PSB_FREQ_OFFSET; 283 if (requested && (!(allowed & BIT(requested)))) 284 return false; 285 286 allowed = pt_cap_get(PT_CAP_cycle_thresholds); 287 requested = (config & RTIT_CTL_CYC_THRESH) >> 288 RTIT_CTL_CYC_THRESH_OFFSET; 289 if (requested && (!(allowed & BIT(requested)))) 290 return false; 291 } 292 293 if (config & RTIT_CTL_MTC) { 294 /* 295 * In the unlikely case that CPUID lists valid mtc periods, 296 * but not the mtc capability, drop out here. 297 * 298 * Spec says that setting mtc period bits while mtc bit in 299 * CPUID is 0 will #GP, so better safe than sorry. 300 */ 301 if (!pt_cap_get(PT_CAP_mtc)) 302 return false; 303 304 allowed = pt_cap_get(PT_CAP_mtc_periods); 305 if (!allowed) 306 return false; 307 308 requested = (config & RTIT_CTL_MTC_RANGE) >> 309 RTIT_CTL_MTC_RANGE_OFFSET; 310 311 if (!(allowed & BIT(requested))) 312 return false; 313 } 314 315 if (config & RTIT_CTL_PWR_EVT_EN && 316 !pt_cap_get(PT_CAP_power_event_trace)) 317 return false; 318 319 if (config & RTIT_CTL_PTW) { 320 if (!pt_cap_get(PT_CAP_ptwrite)) 321 return false; 322 323 /* FUPonPTW without PTW doesn't make sense */ 324 if ((config & RTIT_CTL_FUP_ON_PTW) && 325 !(config & RTIT_CTL_PTW_EN)) 326 return false; 327 } 328 329 return true; 330 } 331 332 /* 333 * PT configuration helpers 334 * These all are cpu affine and operate on a local PT 335 */ 336 337 /* Address ranges and their corresponding msr configuration registers */ 338 static const struct pt_address_range { 339 unsigned long msr_a; 340 unsigned long msr_b; 341 unsigned int reg_off; 342 } pt_address_ranges[] = { 343 { 344 .msr_a = MSR_IA32_RTIT_ADDR0_A, 345 .msr_b = MSR_IA32_RTIT_ADDR0_B, 346 .reg_off = RTIT_CTL_ADDR0_OFFSET, 347 }, 348 { 349 .msr_a = MSR_IA32_RTIT_ADDR1_A, 350 .msr_b = MSR_IA32_RTIT_ADDR1_B, 351 .reg_off = RTIT_CTL_ADDR1_OFFSET, 352 }, 353 { 354 .msr_a = MSR_IA32_RTIT_ADDR2_A, 355 .msr_b = MSR_IA32_RTIT_ADDR2_B, 356 .reg_off = RTIT_CTL_ADDR2_OFFSET, 357 }, 358 { 359 .msr_a = MSR_IA32_RTIT_ADDR3_A, 360 .msr_b = MSR_IA32_RTIT_ADDR3_B, 361 .reg_off = RTIT_CTL_ADDR3_OFFSET, 362 } 363 }; 364 365 static u64 pt_config_filters(struct perf_event *event) 366 { 367 struct pt_filters *filters = event->hw.addr_filters; 368 struct pt *pt = this_cpu_ptr(&pt_ctx); 369 unsigned int range = 0; 370 u64 rtit_ctl = 0; 371 372 if (!filters) 373 return 0; 374 375 perf_event_addr_filters_sync(event); 376 377 for (range = 0; range < filters->nr_filters; range++) { 378 struct pt_filter *filter = &filters->filter[range]; 379 380 /* 381 * Note, if the range has zero start/end addresses due 382 * to its dynamic object not being loaded yet, we just 383 * go ahead and program zeroed range, which will simply 384 * produce no data. Note^2: if executable code at 0x0 385 * is a concern, we can set up an "invalid" configuration 386 * such as msr_b < msr_a. 387 */ 388 389 /* avoid redundant msr writes */ 390 if (pt->filters.filter[range].msr_a != filter->msr_a) { 391 wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a); 392 pt->filters.filter[range].msr_a = filter->msr_a; 393 } 394 395 if (pt->filters.filter[range].msr_b != filter->msr_b) { 396 wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b); 397 pt->filters.filter[range].msr_b = filter->msr_b; 398 } 399 400 rtit_ctl |= filter->config << pt_address_ranges[range].reg_off; 401 } 402 403 return rtit_ctl; 404 } 405 406 static void pt_config(struct perf_event *event) 407 { 408 u64 reg; 409 410 if (!event->hw.itrace_started) { 411 event->hw.itrace_started = 1; 412 wrmsrl(MSR_IA32_RTIT_STATUS, 0); 413 } 414 415 reg = pt_config_filters(event); 416 reg |= RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN | RTIT_CTL_TRACEEN; 417 418 if (!event->attr.exclude_kernel) 419 reg |= RTIT_CTL_OS; 420 if (!event->attr.exclude_user) 421 reg |= RTIT_CTL_USR; 422 423 reg |= (event->attr.config & PT_CONFIG_MASK); 424 425 event->hw.config = reg; 426 wrmsrl(MSR_IA32_RTIT_CTL, reg); 427 } 428 429 static void pt_config_stop(struct perf_event *event) 430 { 431 u64 ctl = READ_ONCE(event->hw.config); 432 433 /* may be already stopped by a PMI */ 434 if (!(ctl & RTIT_CTL_TRACEEN)) 435 return; 436 437 ctl &= ~RTIT_CTL_TRACEEN; 438 wrmsrl(MSR_IA32_RTIT_CTL, ctl); 439 440 WRITE_ONCE(event->hw.config, ctl); 441 442 /* 443 * A wrmsr that disables trace generation serializes other PT 444 * registers and causes all data packets to be written to memory, 445 * but a fence is required for the data to become globally visible. 446 * 447 * The below WMB, separating data store and aux_head store matches 448 * the consumer's RMB that separates aux_head load and data load. 449 */ 450 wmb(); 451 } 452 453 static void pt_config_buffer(void *buf, unsigned int topa_idx, 454 unsigned int output_off) 455 { 456 u64 reg; 457 458 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf)); 459 460 reg = 0x7f | ((u64)topa_idx << 7) | ((u64)output_off << 32); 461 462 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); 463 } 464 465 /* 466 * Keep ToPA table-related metadata on the same page as the actual table, 467 * taking up a few words from the top 468 */ 469 470 #define TENTS_PER_PAGE (((PAGE_SIZE - 40) / sizeof(struct topa_entry)) - 1) 471 472 /** 473 * struct topa - page-sized ToPA table with metadata at the top 474 * @table: actual ToPA table entries, as understood by PT hardware 475 * @list: linkage to struct pt_buffer's list of tables 476 * @phys: physical address of this page 477 * @offset: offset of the first entry in this table in the buffer 478 * @size: total size of all entries in this table 479 * @last: index of the last initialized entry in this table 480 */ 481 struct topa { 482 struct topa_entry table[TENTS_PER_PAGE]; 483 struct list_head list; 484 u64 phys; 485 u64 offset; 486 size_t size; 487 int last; 488 }; 489 490 /* make -1 stand for the last table entry */ 491 #define TOPA_ENTRY(t, i) ((i) == -1 ? &(t)->table[(t)->last] : &(t)->table[(i)]) 492 493 /** 494 * topa_alloc() - allocate page-sized ToPA table 495 * @cpu: CPU on which to allocate. 496 * @gfp: Allocation flags. 497 * 498 * Return: On success, return the pointer to ToPA table page. 499 */ 500 static struct topa *topa_alloc(int cpu, gfp_t gfp) 501 { 502 int node = cpu_to_node(cpu); 503 struct topa *topa; 504 struct page *p; 505 506 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0); 507 if (!p) 508 return NULL; 509 510 topa = page_address(p); 511 topa->last = 0; 512 topa->phys = page_to_phys(p); 513 514 /* 515 * In case of singe-entry ToPA, always put the self-referencing END 516 * link as the 2nd entry in the table 517 */ 518 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) { 519 TOPA_ENTRY(topa, 1)->base = topa->phys >> TOPA_SHIFT; 520 TOPA_ENTRY(topa, 1)->end = 1; 521 } 522 523 return topa; 524 } 525 526 /** 527 * topa_free() - free a page-sized ToPA table 528 * @topa: Table to deallocate. 529 */ 530 static void topa_free(struct topa *topa) 531 { 532 free_page((unsigned long)topa); 533 } 534 535 /** 536 * topa_insert_table() - insert a ToPA table into a buffer 537 * @buf: PT buffer that's being extended. 538 * @topa: New topa table to be inserted. 539 * 540 * If it's the first table in this buffer, set up buffer's pointers 541 * accordingly; otherwise, add a END=1 link entry to @topa to the current 542 * "last" table and adjust the last table pointer to @topa. 543 */ 544 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa) 545 { 546 struct topa *last = buf->last; 547 548 list_add_tail(&topa->list, &buf->tables); 549 550 if (!buf->first) { 551 buf->first = buf->last = buf->cur = topa; 552 return; 553 } 554 555 topa->offset = last->offset + last->size; 556 buf->last = topa; 557 558 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 559 return; 560 561 BUG_ON(last->last != TENTS_PER_PAGE - 1); 562 563 TOPA_ENTRY(last, -1)->base = topa->phys >> TOPA_SHIFT; 564 TOPA_ENTRY(last, -1)->end = 1; 565 } 566 567 /** 568 * topa_table_full() - check if a ToPA table is filled up 569 * @topa: ToPA table. 570 */ 571 static bool topa_table_full(struct topa *topa) 572 { 573 /* single-entry ToPA is a special case */ 574 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 575 return !!topa->last; 576 577 return topa->last == TENTS_PER_PAGE - 1; 578 } 579 580 /** 581 * topa_insert_pages() - create a list of ToPA tables 582 * @buf: PT buffer being initialized. 583 * @gfp: Allocation flags. 584 * 585 * This initializes a list of ToPA tables with entries from 586 * the data_pages provided by rb_alloc_aux(). 587 * 588 * Return: 0 on success or error code. 589 */ 590 static int topa_insert_pages(struct pt_buffer *buf, gfp_t gfp) 591 { 592 struct topa *topa = buf->last; 593 int order = 0; 594 struct page *p; 595 596 p = virt_to_page(buf->data_pages[buf->nr_pages]); 597 if (PagePrivate(p)) 598 order = page_private(p); 599 600 if (topa_table_full(topa)) { 601 topa = topa_alloc(buf->cpu, gfp); 602 if (!topa) 603 return -ENOMEM; 604 605 topa_insert_table(buf, topa); 606 } 607 608 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT; 609 TOPA_ENTRY(topa, -1)->size = order; 610 if (!buf->snapshot && !pt_cap_get(PT_CAP_topa_multiple_entries)) { 611 TOPA_ENTRY(topa, -1)->intr = 1; 612 TOPA_ENTRY(topa, -1)->stop = 1; 613 } 614 615 topa->last++; 616 topa->size += sizes(order); 617 618 buf->nr_pages += 1ul << order; 619 620 return 0; 621 } 622 623 /** 624 * pt_topa_dump() - print ToPA tables and their entries 625 * @buf: PT buffer. 626 */ 627 static void pt_topa_dump(struct pt_buffer *buf) 628 { 629 struct topa *topa; 630 631 list_for_each_entry(topa, &buf->tables, list) { 632 int i; 633 634 pr_debug("# table @%p (%016Lx), off %llx size %zx\n", topa->table, 635 topa->phys, topa->offset, topa->size); 636 for (i = 0; i < TENTS_PER_PAGE; i++) { 637 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n", 638 &topa->table[i], 639 (unsigned long)topa->table[i].base << TOPA_SHIFT, 640 sizes(topa->table[i].size), 641 topa->table[i].end ? 'E' : ' ', 642 topa->table[i].intr ? 'I' : ' ', 643 topa->table[i].stop ? 'S' : ' ', 644 *(u64 *)&topa->table[i]); 645 if ((pt_cap_get(PT_CAP_topa_multiple_entries) && 646 topa->table[i].stop) || 647 topa->table[i].end) 648 break; 649 } 650 } 651 } 652 653 /** 654 * pt_buffer_advance() - advance to the next output region 655 * @buf: PT buffer. 656 * 657 * Advance the current pointers in the buffer to the next ToPA entry. 658 */ 659 static void pt_buffer_advance(struct pt_buffer *buf) 660 { 661 buf->output_off = 0; 662 buf->cur_idx++; 663 664 if (buf->cur_idx == buf->cur->last) { 665 if (buf->cur == buf->last) 666 buf->cur = buf->first; 667 else 668 buf->cur = list_entry(buf->cur->list.next, struct topa, 669 list); 670 buf->cur_idx = 0; 671 } 672 } 673 674 /** 675 * pt_update_head() - calculate current offsets and sizes 676 * @pt: Per-cpu pt context. 677 * 678 * Update buffer's current write pointer position and data size. 679 */ 680 static void pt_update_head(struct pt *pt) 681 { 682 struct pt_buffer *buf = perf_get_aux(&pt->handle); 683 u64 topa_idx, base, old; 684 685 /* offset of the first region in this table from the beginning of buf */ 686 base = buf->cur->offset + buf->output_off; 687 688 /* offset of the current output region within this table */ 689 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++) 690 base += sizes(buf->cur->table[topa_idx].size); 691 692 if (buf->snapshot) { 693 local_set(&buf->data_size, base); 694 } else { 695 old = (local64_xchg(&buf->head, base) & 696 ((buf->nr_pages << PAGE_SHIFT) - 1)); 697 if (base < old) 698 base += buf->nr_pages << PAGE_SHIFT; 699 700 local_add(base - old, &buf->data_size); 701 } 702 } 703 704 /** 705 * pt_buffer_region() - obtain current output region's address 706 * @buf: PT buffer. 707 */ 708 static void *pt_buffer_region(struct pt_buffer *buf) 709 { 710 return phys_to_virt(buf->cur->table[buf->cur_idx].base << TOPA_SHIFT); 711 } 712 713 /** 714 * pt_buffer_region_size() - obtain current output region's size 715 * @buf: PT buffer. 716 */ 717 static size_t pt_buffer_region_size(struct pt_buffer *buf) 718 { 719 return sizes(buf->cur->table[buf->cur_idx].size); 720 } 721 722 /** 723 * pt_handle_status() - take care of possible status conditions 724 * @pt: Per-cpu pt context. 725 */ 726 static void pt_handle_status(struct pt *pt) 727 { 728 struct pt_buffer *buf = perf_get_aux(&pt->handle); 729 int advance = 0; 730 u64 status; 731 732 rdmsrl(MSR_IA32_RTIT_STATUS, status); 733 734 if (status & RTIT_STATUS_ERROR) { 735 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n"); 736 pt_topa_dump(buf); 737 status &= ~RTIT_STATUS_ERROR; 738 } 739 740 if (status & RTIT_STATUS_STOPPED) { 741 status &= ~RTIT_STATUS_STOPPED; 742 743 /* 744 * On systems that only do single-entry ToPA, hitting STOP 745 * means we are already losing data; need to let the decoder 746 * know. 747 */ 748 if (!pt_cap_get(PT_CAP_topa_multiple_entries) || 749 buf->output_off == sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size)) { 750 local_inc(&buf->lost); 751 advance++; 752 } 753 } 754 755 /* 756 * Also on single-entry ToPA implementations, interrupt will come 757 * before the output reaches its output region's boundary. 758 */ 759 if (!pt_cap_get(PT_CAP_topa_multiple_entries) && !buf->snapshot && 760 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) { 761 void *head = pt_buffer_region(buf); 762 763 /* everything within this margin needs to be zeroed out */ 764 memset(head + buf->output_off, 0, 765 pt_buffer_region_size(buf) - 766 buf->output_off); 767 advance++; 768 } 769 770 if (advance) 771 pt_buffer_advance(buf); 772 773 wrmsrl(MSR_IA32_RTIT_STATUS, status); 774 } 775 776 /** 777 * pt_read_offset() - translate registers into buffer pointers 778 * @buf: PT buffer. 779 * 780 * Set buffer's output pointers from MSR values. 781 */ 782 static void pt_read_offset(struct pt_buffer *buf) 783 { 784 u64 offset, base_topa; 785 786 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, base_topa); 787 buf->cur = phys_to_virt(base_topa); 788 789 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, offset); 790 /* offset within current output region */ 791 buf->output_off = offset >> 32; 792 /* index of current output region within this table */ 793 buf->cur_idx = (offset & 0xffffff80) >> 7; 794 } 795 796 /** 797 * pt_topa_next_entry() - obtain index of the first page in the next ToPA entry 798 * @buf: PT buffer. 799 * @pg: Page offset in the buffer. 800 * 801 * When advancing to the next output region (ToPA entry), given a page offset 802 * into the buffer, we need to find the offset of the first page in the next 803 * region. 804 */ 805 static unsigned int pt_topa_next_entry(struct pt_buffer *buf, unsigned int pg) 806 { 807 struct topa_entry *te = buf->topa_index[pg]; 808 809 /* one region */ 810 if (buf->first == buf->last && buf->first->last == 1) 811 return pg; 812 813 do { 814 pg++; 815 pg &= buf->nr_pages - 1; 816 } while (buf->topa_index[pg] == te); 817 818 return pg; 819 } 820 821 /** 822 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer 823 * @buf: PT buffer. 824 * @handle: Current output handle. 825 * 826 * Place INT and STOP marks to prevent overwriting old data that the consumer 827 * hasn't yet collected and waking up the consumer after a certain fraction of 828 * the buffer has filled up. Only needed and sensible for non-snapshot counters. 829 * 830 * This obviously relies on buf::head to figure out buffer markers, so it has 831 * to be called after pt_buffer_reset_offsets() and before the hardware tracing 832 * is enabled. 833 */ 834 static int pt_buffer_reset_markers(struct pt_buffer *buf, 835 struct perf_output_handle *handle) 836 837 { 838 unsigned long head = local64_read(&buf->head); 839 unsigned long idx, npages, wakeup; 840 841 /* can't stop in the middle of an output region */ 842 if (buf->output_off + handle->size + 1 < 843 sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size)) 844 return -EINVAL; 845 846 847 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */ 848 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 849 return 0; 850 851 /* clear STOP and INT from current entry */ 852 buf->topa_index[buf->stop_pos]->stop = 0; 853 buf->topa_index[buf->stop_pos]->intr = 0; 854 buf->topa_index[buf->intr_pos]->intr = 0; 855 856 /* how many pages till the STOP marker */ 857 npages = handle->size >> PAGE_SHIFT; 858 859 /* if it's on a page boundary, fill up one more page */ 860 if (!offset_in_page(head + handle->size + 1)) 861 npages++; 862 863 idx = (head >> PAGE_SHIFT) + npages; 864 idx &= buf->nr_pages - 1; 865 buf->stop_pos = idx; 866 867 wakeup = handle->wakeup >> PAGE_SHIFT; 868 869 /* in the worst case, wake up the consumer one page before hard stop */ 870 idx = (head >> PAGE_SHIFT) + npages - 1; 871 if (idx > wakeup) 872 idx = wakeup; 873 874 idx &= buf->nr_pages - 1; 875 buf->intr_pos = idx; 876 877 buf->topa_index[buf->stop_pos]->stop = 1; 878 buf->topa_index[buf->stop_pos]->intr = 1; 879 buf->topa_index[buf->intr_pos]->intr = 1; 880 881 return 0; 882 } 883 884 /** 885 * pt_buffer_setup_topa_index() - build topa_index[] table of regions 886 * @buf: PT buffer. 887 * 888 * topa_index[] references output regions indexed by offset into the 889 * buffer for purposes of quick reverse lookup. 890 */ 891 static void pt_buffer_setup_topa_index(struct pt_buffer *buf) 892 { 893 struct topa *cur = buf->first, *prev = buf->last; 894 struct topa_entry *te_cur = TOPA_ENTRY(cur, 0), 895 *te_prev = TOPA_ENTRY(prev, prev->last - 1); 896 int pg = 0, idx = 0; 897 898 while (pg < buf->nr_pages) { 899 int tidx; 900 901 /* pages within one topa entry */ 902 for (tidx = 0; tidx < 1 << te_cur->size; tidx++, pg++) 903 buf->topa_index[pg] = te_prev; 904 905 te_prev = te_cur; 906 907 if (idx == cur->last - 1) { 908 /* advance to next topa table */ 909 idx = 0; 910 cur = list_entry(cur->list.next, struct topa, list); 911 } else { 912 idx++; 913 } 914 te_cur = TOPA_ENTRY(cur, idx); 915 } 916 917 } 918 919 /** 920 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head 921 * @buf: PT buffer. 922 * @head: Write pointer (aux_head) from AUX buffer. 923 * 924 * Find the ToPA table and entry corresponding to given @head and set buffer's 925 * "current" pointers accordingly. This is done after we have obtained the 926 * current aux_head position from a successful call to perf_aux_output_begin() 927 * to make sure the hardware is writing to the right place. 928 * 929 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed 930 * into PT msrs when the tracing is enabled and buf::head and buf::data_size, 931 * which are used to determine INT and STOP markers' locations by a subsequent 932 * call to pt_buffer_reset_markers(). 933 */ 934 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head) 935 { 936 int pg; 937 938 if (buf->snapshot) 939 head &= (buf->nr_pages << PAGE_SHIFT) - 1; 940 941 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1); 942 pg = pt_topa_next_entry(buf, pg); 943 944 buf->cur = (struct topa *)((unsigned long)buf->topa_index[pg] & PAGE_MASK); 945 buf->cur_idx = ((unsigned long)buf->topa_index[pg] - 946 (unsigned long)buf->cur) / sizeof(struct topa_entry); 947 buf->output_off = head & (sizes(buf->cur->table[buf->cur_idx].size) - 1); 948 949 local64_set(&buf->head, head); 950 local_set(&buf->data_size, 0); 951 } 952 953 /** 954 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer 955 * @buf: PT buffer. 956 */ 957 static void pt_buffer_fini_topa(struct pt_buffer *buf) 958 { 959 struct topa *topa, *iter; 960 961 list_for_each_entry_safe(topa, iter, &buf->tables, list) { 962 /* 963 * right now, this is in free_aux() path only, so 964 * no need to unlink this table from the list 965 */ 966 topa_free(topa); 967 } 968 } 969 970 /** 971 * pt_buffer_init_topa() - initialize ToPA table for pt buffer 972 * @buf: PT buffer. 973 * @size: Total size of all regions within this ToPA. 974 * @gfp: Allocation flags. 975 */ 976 static int pt_buffer_init_topa(struct pt_buffer *buf, unsigned long nr_pages, 977 gfp_t gfp) 978 { 979 struct topa *topa; 980 int err; 981 982 topa = topa_alloc(buf->cpu, gfp); 983 if (!topa) 984 return -ENOMEM; 985 986 topa_insert_table(buf, topa); 987 988 while (buf->nr_pages < nr_pages) { 989 err = topa_insert_pages(buf, gfp); 990 if (err) { 991 pt_buffer_fini_topa(buf); 992 return -ENOMEM; 993 } 994 } 995 996 pt_buffer_setup_topa_index(buf); 997 998 /* link last table to the first one, unless we're double buffering */ 999 if (pt_cap_get(PT_CAP_topa_multiple_entries)) { 1000 TOPA_ENTRY(buf->last, -1)->base = buf->first->phys >> TOPA_SHIFT; 1001 TOPA_ENTRY(buf->last, -1)->end = 1; 1002 } 1003 1004 pt_topa_dump(buf); 1005 return 0; 1006 } 1007 1008 /** 1009 * pt_buffer_setup_aux() - set up topa tables for a PT buffer 1010 * @cpu: Cpu on which to allocate, -1 means current. 1011 * @pages: Array of pointers to buffer pages passed from perf core. 1012 * @nr_pages: Number of pages in the buffer. 1013 * @snapshot: If this is a snapshot/overwrite counter. 1014 * 1015 * This is a pmu::setup_aux callback that sets up ToPA tables and all the 1016 * bookkeeping for an AUX buffer. 1017 * 1018 * Return: Our private PT buffer structure. 1019 */ 1020 static void * 1021 pt_buffer_setup_aux(int cpu, void **pages, int nr_pages, bool snapshot) 1022 { 1023 struct pt_buffer *buf; 1024 int node, ret; 1025 1026 if (!nr_pages) 1027 return NULL; 1028 1029 if (cpu == -1) 1030 cpu = raw_smp_processor_id(); 1031 node = cpu_to_node(cpu); 1032 1033 buf = kzalloc_node(offsetof(struct pt_buffer, topa_index[nr_pages]), 1034 GFP_KERNEL, node); 1035 if (!buf) 1036 return NULL; 1037 1038 buf->cpu = cpu; 1039 buf->snapshot = snapshot; 1040 buf->data_pages = pages; 1041 1042 INIT_LIST_HEAD(&buf->tables); 1043 1044 ret = pt_buffer_init_topa(buf, nr_pages, GFP_KERNEL); 1045 if (ret) { 1046 kfree(buf); 1047 return NULL; 1048 } 1049 1050 return buf; 1051 } 1052 1053 /** 1054 * pt_buffer_free_aux() - perf AUX deallocation path callback 1055 * @data: PT buffer. 1056 */ 1057 static void pt_buffer_free_aux(void *data) 1058 { 1059 struct pt_buffer *buf = data; 1060 1061 pt_buffer_fini_topa(buf); 1062 kfree(buf); 1063 } 1064 1065 static int pt_addr_filters_init(struct perf_event *event) 1066 { 1067 struct pt_filters *filters; 1068 int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu); 1069 1070 if (!pt_cap_get(PT_CAP_num_address_ranges)) 1071 return 0; 1072 1073 filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node); 1074 if (!filters) 1075 return -ENOMEM; 1076 1077 if (event->parent) 1078 memcpy(filters, event->parent->hw.addr_filters, 1079 sizeof(*filters)); 1080 1081 event->hw.addr_filters = filters; 1082 1083 return 0; 1084 } 1085 1086 static void pt_addr_filters_fini(struct perf_event *event) 1087 { 1088 kfree(event->hw.addr_filters); 1089 event->hw.addr_filters = NULL; 1090 } 1091 1092 static inline bool valid_kernel_ip(unsigned long ip) 1093 { 1094 return virt_addr_valid(ip) && kernel_ip(ip); 1095 } 1096 1097 static int pt_event_addr_filters_validate(struct list_head *filters) 1098 { 1099 struct perf_addr_filter *filter; 1100 int range = 0; 1101 1102 list_for_each_entry(filter, filters, entry) { 1103 /* PT doesn't support single address triggers */ 1104 if (!filter->range || !filter->size) 1105 return -EOPNOTSUPP; 1106 1107 if (!filter->inode) { 1108 if (!valid_kernel_ip(filter->offset)) 1109 return -EINVAL; 1110 1111 if (!valid_kernel_ip(filter->offset + filter->size)) 1112 return -EINVAL; 1113 } 1114 1115 if (++range > pt_cap_get(PT_CAP_num_address_ranges)) 1116 return -EOPNOTSUPP; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static void pt_event_addr_filters_sync(struct perf_event *event) 1123 { 1124 struct perf_addr_filters_head *head = perf_event_addr_filters(event); 1125 unsigned long msr_a, msr_b, *offs = event->addr_filters_offs; 1126 struct pt_filters *filters = event->hw.addr_filters; 1127 struct perf_addr_filter *filter; 1128 int range = 0; 1129 1130 if (!filters) 1131 return; 1132 1133 list_for_each_entry(filter, &head->list, entry) { 1134 if (filter->inode && !offs[range]) { 1135 msr_a = msr_b = 0; 1136 } else { 1137 /* apply the offset */ 1138 msr_a = filter->offset + offs[range]; 1139 msr_b = filter->size + msr_a - 1; 1140 } 1141 1142 filters->filter[range].msr_a = msr_a; 1143 filters->filter[range].msr_b = msr_b; 1144 filters->filter[range].config = filter->filter ? 1 : 2; 1145 range++; 1146 } 1147 1148 filters->nr_filters = range; 1149 } 1150 1151 /** 1152 * intel_pt_interrupt() - PT PMI handler 1153 */ 1154 void intel_pt_interrupt(void) 1155 { 1156 struct pt *pt = this_cpu_ptr(&pt_ctx); 1157 struct pt_buffer *buf; 1158 struct perf_event *event = pt->handle.event; 1159 1160 /* 1161 * There may be a dangling PT bit in the interrupt status register 1162 * after PT has been disabled by pt_event_stop(). Make sure we don't 1163 * do anything (particularly, re-enable) for this event here. 1164 */ 1165 if (!READ_ONCE(pt->handle_nmi)) 1166 return; 1167 1168 /* 1169 * If VMX is on and PT does not support it, don't touch anything. 1170 */ 1171 if (READ_ONCE(pt->vmx_on)) 1172 return; 1173 1174 if (!event) 1175 return; 1176 1177 pt_config_stop(event); 1178 1179 buf = perf_get_aux(&pt->handle); 1180 if (!buf) 1181 return; 1182 1183 pt_read_offset(buf); 1184 1185 pt_handle_status(pt); 1186 1187 pt_update_head(pt); 1188 1189 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0), 1190 local_xchg(&buf->lost, 0)); 1191 1192 if (!event->hw.state) { 1193 int ret; 1194 1195 buf = perf_aux_output_begin(&pt->handle, event); 1196 if (!buf) { 1197 event->hw.state = PERF_HES_STOPPED; 1198 return; 1199 } 1200 1201 pt_buffer_reset_offsets(buf, pt->handle.head); 1202 /* snapshot counters don't use PMI, so it's safe */ 1203 ret = pt_buffer_reset_markers(buf, &pt->handle); 1204 if (ret) { 1205 perf_aux_output_end(&pt->handle, 0, true); 1206 return; 1207 } 1208 1209 pt_config_buffer(buf->cur->table, buf->cur_idx, 1210 buf->output_off); 1211 pt_config(event); 1212 } 1213 } 1214 1215 void intel_pt_handle_vmx(int on) 1216 { 1217 struct pt *pt = this_cpu_ptr(&pt_ctx); 1218 struct perf_event *event; 1219 unsigned long flags; 1220 1221 /* PT plays nice with VMX, do nothing */ 1222 if (pt_pmu.vmx) 1223 return; 1224 1225 /* 1226 * VMXON will clear RTIT_CTL.TraceEn; we need to make 1227 * sure to not try to set it while VMX is on. Disable 1228 * interrupts to avoid racing with pmu callbacks; 1229 * concurrent PMI should be handled fine. 1230 */ 1231 local_irq_save(flags); 1232 WRITE_ONCE(pt->vmx_on, on); 1233 1234 if (on) { 1235 /* prevent pt_config_stop() from writing RTIT_CTL */ 1236 event = pt->handle.event; 1237 if (event) 1238 event->hw.config = 0; 1239 } 1240 local_irq_restore(flags); 1241 } 1242 EXPORT_SYMBOL_GPL(intel_pt_handle_vmx); 1243 1244 /* 1245 * PMU callbacks 1246 */ 1247 1248 static void pt_event_start(struct perf_event *event, int mode) 1249 { 1250 struct hw_perf_event *hwc = &event->hw; 1251 struct pt *pt = this_cpu_ptr(&pt_ctx); 1252 struct pt_buffer *buf; 1253 1254 if (READ_ONCE(pt->vmx_on)) 1255 return; 1256 1257 buf = perf_aux_output_begin(&pt->handle, event); 1258 if (!buf) 1259 goto fail_stop; 1260 1261 pt_buffer_reset_offsets(buf, pt->handle.head); 1262 if (!buf->snapshot) { 1263 if (pt_buffer_reset_markers(buf, &pt->handle)) 1264 goto fail_end_stop; 1265 } 1266 1267 WRITE_ONCE(pt->handle_nmi, 1); 1268 hwc->state = 0; 1269 1270 pt_config_buffer(buf->cur->table, buf->cur_idx, 1271 buf->output_off); 1272 pt_config(event); 1273 1274 return; 1275 1276 fail_end_stop: 1277 perf_aux_output_end(&pt->handle, 0, true); 1278 fail_stop: 1279 hwc->state = PERF_HES_STOPPED; 1280 } 1281 1282 static void pt_event_stop(struct perf_event *event, int mode) 1283 { 1284 struct pt *pt = this_cpu_ptr(&pt_ctx); 1285 1286 /* 1287 * Protect against the PMI racing with disabling wrmsr, 1288 * see comment in intel_pt_interrupt(). 1289 */ 1290 WRITE_ONCE(pt->handle_nmi, 0); 1291 1292 pt_config_stop(event); 1293 1294 if (event->hw.state == PERF_HES_STOPPED) 1295 return; 1296 1297 event->hw.state = PERF_HES_STOPPED; 1298 1299 if (mode & PERF_EF_UPDATE) { 1300 struct pt_buffer *buf = perf_get_aux(&pt->handle); 1301 1302 if (!buf) 1303 return; 1304 1305 if (WARN_ON_ONCE(pt->handle.event != event)) 1306 return; 1307 1308 pt_read_offset(buf); 1309 1310 pt_handle_status(pt); 1311 1312 pt_update_head(pt); 1313 1314 if (buf->snapshot) 1315 pt->handle.head = 1316 local_xchg(&buf->data_size, 1317 buf->nr_pages << PAGE_SHIFT); 1318 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0), 1319 local_xchg(&buf->lost, 0)); 1320 } 1321 } 1322 1323 static void pt_event_del(struct perf_event *event, int mode) 1324 { 1325 pt_event_stop(event, PERF_EF_UPDATE); 1326 } 1327 1328 static int pt_event_add(struct perf_event *event, int mode) 1329 { 1330 struct pt *pt = this_cpu_ptr(&pt_ctx); 1331 struct hw_perf_event *hwc = &event->hw; 1332 int ret = -EBUSY; 1333 1334 if (pt->handle.event) 1335 goto fail; 1336 1337 if (mode & PERF_EF_START) { 1338 pt_event_start(event, 0); 1339 ret = -EINVAL; 1340 if (hwc->state == PERF_HES_STOPPED) 1341 goto fail; 1342 } else { 1343 hwc->state = PERF_HES_STOPPED; 1344 } 1345 1346 ret = 0; 1347 fail: 1348 1349 return ret; 1350 } 1351 1352 static void pt_event_read(struct perf_event *event) 1353 { 1354 } 1355 1356 static void pt_event_destroy(struct perf_event *event) 1357 { 1358 pt_addr_filters_fini(event); 1359 x86_del_exclusive(x86_lbr_exclusive_pt); 1360 } 1361 1362 static int pt_event_init(struct perf_event *event) 1363 { 1364 if (event->attr.type != pt_pmu.pmu.type) 1365 return -ENOENT; 1366 1367 if (!pt_event_valid(event)) 1368 return -EINVAL; 1369 1370 if (x86_add_exclusive(x86_lbr_exclusive_pt)) 1371 return -EBUSY; 1372 1373 if (pt_addr_filters_init(event)) { 1374 x86_del_exclusive(x86_lbr_exclusive_pt); 1375 return -ENOMEM; 1376 } 1377 1378 event->destroy = pt_event_destroy; 1379 1380 return 0; 1381 } 1382 1383 void cpu_emergency_stop_pt(void) 1384 { 1385 struct pt *pt = this_cpu_ptr(&pt_ctx); 1386 1387 if (pt->handle.event) 1388 pt_event_stop(pt->handle.event, PERF_EF_UPDATE); 1389 } 1390 1391 static __init int pt_init(void) 1392 { 1393 int ret, cpu, prior_warn = 0; 1394 1395 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE); 1396 1397 if (!boot_cpu_has(X86_FEATURE_INTEL_PT)) 1398 return -ENODEV; 1399 1400 get_online_cpus(); 1401 for_each_online_cpu(cpu) { 1402 u64 ctl; 1403 1404 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); 1405 if (!ret && (ctl & RTIT_CTL_TRACEEN)) 1406 prior_warn++; 1407 } 1408 put_online_cpus(); 1409 1410 if (prior_warn) { 1411 x86_add_exclusive(x86_lbr_exclusive_pt); 1412 pr_warn("PT is enabled at boot time, doing nothing\n"); 1413 1414 return -EBUSY; 1415 } 1416 1417 ret = pt_pmu_hw_init(); 1418 if (ret) 1419 return ret; 1420 1421 if (!pt_cap_get(PT_CAP_topa_output)) { 1422 pr_warn("ToPA output is not supported on this CPU\n"); 1423 return -ENODEV; 1424 } 1425 1426 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) 1427 pt_pmu.pmu.capabilities = 1428 PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF; 1429 1430 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; 1431 pt_pmu.pmu.attr_groups = pt_attr_groups; 1432 pt_pmu.pmu.task_ctx_nr = perf_sw_context; 1433 pt_pmu.pmu.event_init = pt_event_init; 1434 pt_pmu.pmu.add = pt_event_add; 1435 pt_pmu.pmu.del = pt_event_del; 1436 pt_pmu.pmu.start = pt_event_start; 1437 pt_pmu.pmu.stop = pt_event_stop; 1438 pt_pmu.pmu.read = pt_event_read; 1439 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux; 1440 pt_pmu.pmu.free_aux = pt_buffer_free_aux; 1441 pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync; 1442 pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate; 1443 pt_pmu.pmu.nr_addr_filters = 1444 pt_cap_get(PT_CAP_num_address_ranges); 1445 1446 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1); 1447 1448 return ret; 1449 } 1450 arch_initcall(pt_init); 1451