1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 25e865ed4SBorislav Petkov #include <linux/perf_event.h> 35e865ed4SBorislav Petkov #include <linux/types.h> 45e865ed4SBorislav Petkov 527f6d22bSBorislav Petkov #include "../perf_event.h" 65e865ed4SBorislav Petkov 75e865ed4SBorislav Petkov /* 85e865ed4SBorislav Petkov * Not sure about some of these 95e865ed4SBorislav Petkov */ 105e865ed4SBorislav Petkov static const u64 p6_perfmon_event_map[] = 115e865ed4SBorislav Petkov { 125e865ed4SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */ 135e865ed4SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */ 145e865ed4SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */ 155e865ed4SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */ 165e865ed4SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */ 175e865ed4SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */ 185e865ed4SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */ 195e865ed4SBorislav Petkov [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */ 205e865ed4SBorislav Petkov 215e865ed4SBorislav Petkov }; 225e865ed4SBorislav Petkov 235e865ed4SBorislav Petkov static const u64 __initconst p6_hw_cache_event_ids 245e865ed4SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 255e865ed4SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 265e865ed4SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 275e865ed4SBorislav Petkov { 285e865ed4SBorislav Petkov [ C(L1D) ] = { 295e865ed4SBorislav Petkov [ C(OP_READ) ] = { 305e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ 315e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */ 325e865ed4SBorislav Petkov }, 335e865ed4SBorislav Petkov [ C(OP_WRITE) ] = { 345e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 355e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */ 365e865ed4SBorislav Petkov }, 375e865ed4SBorislav Petkov [ C(OP_PREFETCH) ] = { 385e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 395e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 405e865ed4SBorislav Petkov }, 415e865ed4SBorislav Petkov }, 425e865ed4SBorislav Petkov [ C(L1I ) ] = { 435e865ed4SBorislav Petkov [ C(OP_READ) ] = { 445e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ 455e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */ 465e865ed4SBorislav Petkov }, 475e865ed4SBorislav Petkov [ C(OP_WRITE) ] = { 485e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 495e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = -1, 505e865ed4SBorislav Petkov }, 515e865ed4SBorislav Petkov [ C(OP_PREFETCH) ] = { 525e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 535e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 545e865ed4SBorislav Petkov }, 555e865ed4SBorislav Petkov }, 565e865ed4SBorislav Petkov [ C(LL ) ] = { 575e865ed4SBorislav Petkov [ C(OP_READ) ] = { 585e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 595e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 605e865ed4SBorislav Petkov }, 615e865ed4SBorislav Petkov [ C(OP_WRITE) ] = { 625e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 635e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */ 645e865ed4SBorislav Petkov }, 655e865ed4SBorislav Petkov [ C(OP_PREFETCH) ] = { 665e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 675e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 685e865ed4SBorislav Petkov }, 695e865ed4SBorislav Petkov }, 705e865ed4SBorislav Petkov [ C(DTLB) ] = { 715e865ed4SBorislav Petkov [ C(OP_READ) ] = { 725e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ 735e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 745e865ed4SBorislav Petkov }, 755e865ed4SBorislav Petkov [ C(OP_WRITE) ] = { 765e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 775e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 785e865ed4SBorislav Petkov }, 795e865ed4SBorislav Petkov [ C(OP_PREFETCH) ] = { 805e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 815e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0, 825e865ed4SBorislav Petkov }, 835e865ed4SBorislav Petkov }, 845e865ed4SBorislav Petkov [ C(ITLB) ] = { 855e865ed4SBorislav Petkov [ C(OP_READ) ] = { 865e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ 875e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */ 885e865ed4SBorislav Petkov }, 895e865ed4SBorislav Petkov [ C(OP_WRITE) ] = { 905e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 915e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = -1, 925e865ed4SBorislav Petkov }, 935e865ed4SBorislav Petkov [ C(OP_PREFETCH) ] = { 945e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 955e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = -1, 965e865ed4SBorislav Petkov }, 975e865ed4SBorislav Petkov }, 985e865ed4SBorislav Petkov [ C(BPU ) ] = { 995e865ed4SBorislav Petkov [ C(OP_READ) ] = { 1005e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */ 1015e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */ 1025e865ed4SBorislav Petkov }, 1035e865ed4SBorislav Petkov [ C(OP_WRITE) ] = { 1045e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1055e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1065e865ed4SBorislav Petkov }, 1075e865ed4SBorislav Petkov [ C(OP_PREFETCH) ] = { 1085e865ed4SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1095e865ed4SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1105e865ed4SBorislav Petkov }, 1115e865ed4SBorislav Petkov }, 1125e865ed4SBorislav Petkov }; 1135e865ed4SBorislav Petkov 1145e865ed4SBorislav Petkov static u64 p6_pmu_event_map(int hw_event) 1155e865ed4SBorislav Petkov { 1165e865ed4SBorislav Petkov return p6_perfmon_event_map[hw_event]; 1175e865ed4SBorislav Petkov } 1185e865ed4SBorislav Petkov 1195e865ed4SBorislav Petkov /* 1205e865ed4SBorislav Petkov * Event setting that is specified not to count anything. 1215e865ed4SBorislav Petkov * We use this to effectively disable a counter. 1225e865ed4SBorislav Petkov * 1235e865ed4SBorislav Petkov * L2_RQSTS with 0 MESI unit mask. 1245e865ed4SBorislav Petkov */ 1255e865ed4SBorislav Petkov #define P6_NOP_EVENT 0x0000002EULL 1265e865ed4SBorislav Petkov 1275e865ed4SBorislav Petkov static struct event_constraint p6_event_constraints[] = 1285e865ed4SBorislav Petkov { 1295e865ed4SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ 1305e865ed4SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 1315e865ed4SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 1325e865ed4SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 1335e865ed4SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 1345e865ed4SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 1355e865ed4SBorislav Petkov EVENT_CONSTRAINT_END 1365e865ed4SBorislav Petkov }; 1375e865ed4SBorislav Petkov 1385e865ed4SBorislav Petkov static void p6_pmu_disable_all(void) 1395e865ed4SBorislav Petkov { 1405e865ed4SBorislav Petkov u64 val; 1415e865ed4SBorislav Petkov 1425e865ed4SBorislav Petkov /* p6 only has one enable register */ 1435e865ed4SBorislav Petkov rdmsrl(MSR_P6_EVNTSEL0, val); 1445e865ed4SBorislav Petkov val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 1455e865ed4SBorislav Petkov wrmsrl(MSR_P6_EVNTSEL0, val); 1465e865ed4SBorislav Petkov } 1475e865ed4SBorislav Petkov 1485e865ed4SBorislav Petkov static void p6_pmu_enable_all(int added) 1495e865ed4SBorislav Petkov { 1505e865ed4SBorislav Petkov unsigned long val; 1515e865ed4SBorislav Petkov 1525e865ed4SBorislav Petkov /* p6 only has one enable register */ 1535e865ed4SBorislav Petkov rdmsrl(MSR_P6_EVNTSEL0, val); 1545e865ed4SBorislav Petkov val |= ARCH_PERFMON_EVENTSEL_ENABLE; 1555e865ed4SBorislav Petkov wrmsrl(MSR_P6_EVNTSEL0, val); 1565e865ed4SBorislav Petkov } 1575e865ed4SBorislav Petkov 1585e865ed4SBorislav Petkov static inline void 1595e865ed4SBorislav Petkov p6_pmu_disable_event(struct perf_event *event) 1605e865ed4SBorislav Petkov { 1615e865ed4SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1625e865ed4SBorislav Petkov u64 val = P6_NOP_EVENT; 1635e865ed4SBorislav Petkov 1645e865ed4SBorislav Petkov (void)wrmsrl_safe(hwc->config_base, val); 1655e865ed4SBorislav Petkov } 1665e865ed4SBorislav Petkov 1675e865ed4SBorislav Petkov static void p6_pmu_enable_event(struct perf_event *event) 1685e865ed4SBorislav Petkov { 1695e865ed4SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 1705e865ed4SBorislav Petkov u64 val; 1715e865ed4SBorislav Petkov 1725e865ed4SBorislav Petkov val = hwc->config; 1735e865ed4SBorislav Petkov 1745e865ed4SBorislav Petkov /* 1755e865ed4SBorislav Petkov * p6 only has a global event enable, set on PerfEvtSel0 1765e865ed4SBorislav Petkov * We "disable" events by programming P6_NOP_EVENT 1775e865ed4SBorislav Petkov * and we rely on p6_pmu_enable_all() being called 1785e865ed4SBorislav Petkov * to actually enable the events. 1795e865ed4SBorislav Petkov */ 1805e865ed4SBorislav Petkov 1815e865ed4SBorislav Petkov (void)wrmsrl_safe(hwc->config_base, val); 1825e865ed4SBorislav Petkov } 1835e865ed4SBorislav Petkov 1845e865ed4SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 1855e865ed4SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 1865e865ed4SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 1875e865ed4SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 1885e865ed4SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 1895e865ed4SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 1905e865ed4SBorislav Petkov 1915e865ed4SBorislav Petkov static struct attribute *intel_p6_formats_attr[] = { 1925e865ed4SBorislav Petkov &format_attr_event.attr, 1935e865ed4SBorislav Petkov &format_attr_umask.attr, 1945e865ed4SBorislav Petkov &format_attr_edge.attr, 1955e865ed4SBorislav Petkov &format_attr_pc.attr, 1965e865ed4SBorislav Petkov &format_attr_inv.attr, 1975e865ed4SBorislav Petkov &format_attr_cmask.attr, 1985e865ed4SBorislav Petkov NULL, 1995e865ed4SBorislav Petkov }; 2005e865ed4SBorislav Petkov 2015e865ed4SBorislav Petkov static __initconst const struct x86_pmu p6_pmu = { 2025e865ed4SBorislav Petkov .name = "p6", 2035e865ed4SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 2045e865ed4SBorislav Petkov .disable_all = p6_pmu_disable_all, 2055e865ed4SBorislav Petkov .enable_all = p6_pmu_enable_all, 2065e865ed4SBorislav Petkov .enable = p6_pmu_enable_event, 2075e865ed4SBorislav Petkov .disable = p6_pmu_disable_event, 2085e865ed4SBorislav Petkov .hw_config = x86_pmu_hw_config, 2095e865ed4SBorislav Petkov .schedule_events = x86_schedule_events, 2105e865ed4SBorislav Petkov .eventsel = MSR_P6_EVNTSEL0, 2115e865ed4SBorislav Petkov .perfctr = MSR_P6_PERFCTR0, 2125e865ed4SBorislav Petkov .event_map = p6_pmu_event_map, 2135e865ed4SBorislav Petkov .max_events = ARRAY_SIZE(p6_perfmon_event_map), 2145e865ed4SBorislav Petkov .apic = 1, 2155e865ed4SBorislav Petkov .max_period = (1ULL << 31) - 1, 2165e865ed4SBorislav Petkov .version = 0, 2175e865ed4SBorislav Petkov .num_counters = 2, 2185e865ed4SBorislav Petkov /* 2195e865ed4SBorislav Petkov * Events have 40 bits implemented. However they are designed such 2205e865ed4SBorislav Petkov * that bits [32-39] are sign extensions of bit 31. As such the 2215e865ed4SBorislav Petkov * effective width of a event for P6-like PMU is 32 bits only. 2225e865ed4SBorislav Petkov * 2235e865ed4SBorislav Petkov * See IA-32 Intel Architecture Software developer manual Vol 3B 2245e865ed4SBorislav Petkov */ 2255e865ed4SBorislav Petkov .cntval_bits = 32, 2265e865ed4SBorislav Petkov .cntval_mask = (1ULL << 32) - 1, 2275e865ed4SBorislav Petkov .get_event_constraints = x86_get_event_constraints, 2285e865ed4SBorislav Petkov .event_constraints = p6_event_constraints, 2295e865ed4SBorislav Petkov 2305e865ed4SBorislav Petkov .format_attrs = intel_p6_formats_attr, 2315e865ed4SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 2325e865ed4SBorislav Petkov 2335e865ed4SBorislav Petkov }; 2345e865ed4SBorislav Petkov 2355e865ed4SBorislav Petkov static __init void p6_pmu_rdpmc_quirk(void) 2365e865ed4SBorislav Petkov { 2375e865ed4SBorislav Petkov if (boot_cpu_data.x86_mask < 9) { 2385e865ed4SBorislav Petkov /* 2395e865ed4SBorislav Petkov * PPro erratum 26; fixed in stepping 9 and above. 2405e865ed4SBorislav Petkov */ 2415e865ed4SBorislav Petkov pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n"); 2425e865ed4SBorislav Petkov x86_pmu.attr_rdpmc_broken = 1; 2435e865ed4SBorislav Petkov x86_pmu.attr_rdpmc = 0; 2445e865ed4SBorislav Petkov } 2455e865ed4SBorislav Petkov } 2465e865ed4SBorislav Petkov 2475e865ed4SBorislav Petkov __init int p6_pmu_init(void) 2485e865ed4SBorislav Petkov { 2495e865ed4SBorislav Petkov x86_pmu = p6_pmu; 2505e865ed4SBorislav Petkov 2515e865ed4SBorislav Petkov switch (boot_cpu_data.x86_model) { 2525e865ed4SBorislav Petkov case 1: /* Pentium Pro */ 2535e865ed4SBorislav Petkov x86_add_quirk(p6_pmu_rdpmc_quirk); 2545e865ed4SBorislav Petkov break; 2555e865ed4SBorislav Petkov 2565e865ed4SBorislav Petkov case 3: /* Pentium II - Klamath */ 2575e865ed4SBorislav Petkov case 5: /* Pentium II - Deschutes */ 2585e865ed4SBorislav Petkov case 6: /* Pentium II - Mendocino */ 2595e865ed4SBorislav Petkov break; 2605e865ed4SBorislav Petkov 2615e865ed4SBorislav Petkov case 7: /* Pentium III - Katmai */ 2625e865ed4SBorislav Petkov case 8: /* Pentium III - Coppermine */ 2635e865ed4SBorislav Petkov case 10: /* Pentium III Xeon */ 2645e865ed4SBorislav Petkov case 11: /* Pentium III - Tualatin */ 2655e865ed4SBorislav Petkov break; 2665e865ed4SBorislav Petkov 2675e865ed4SBorislav Petkov case 9: /* Pentium M - Banias */ 2685e865ed4SBorislav Petkov case 13: /* Pentium M - Dothan */ 2695e865ed4SBorislav Petkov break; 2705e865ed4SBorislav Petkov 2715e865ed4SBorislav Petkov default: 2725e865ed4SBorislav Petkov pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model); 2735e865ed4SBorislav Petkov return -ENODEV; 2745e865ed4SBorislav Petkov } 2755e865ed4SBorislav Petkov 2765e865ed4SBorislav Petkov memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, 2775e865ed4SBorislav Petkov sizeof(hw_cache_event_ids)); 2785e865ed4SBorislav Petkov 2795e865ed4SBorislav Petkov return 0; 2805e865ed4SBorislav Petkov } 281