1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/types.h> 4 5 #include <asm/perf_event.h> 6 #include <asm/msr.h> 7 #include <asm/insn.h> 8 9 #include "../perf_event.h" 10 11 static const enum { 12 LBR_EIP_FLAGS = 1, 13 LBR_TSX = 2, 14 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = { 15 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS, 16 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX, 17 }; 18 19 /* 20 * Intel LBR_SELECT bits 21 * Intel Vol3a, April 2011, Section 16.7 Table 16-10 22 * 23 * Hardware branch filter (not available on all CPUs) 24 */ 25 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */ 26 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */ 27 #define LBR_JCC_BIT 2 /* do not capture conditional branches */ 28 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */ 29 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */ 30 #define LBR_RETURN_BIT 5 /* do not capture near returns */ 31 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */ 32 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */ 33 #define LBR_FAR_BIT 8 /* do not capture far branches */ 34 #define LBR_CALL_STACK_BIT 9 /* enable call stack */ 35 36 /* 37 * Following bit only exists in Linux; we mask it out before writing it to 38 * the actual MSR. But it helps the constraint perf code to understand 39 * that this is a separate configuration. 40 */ 41 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */ 42 43 #define LBR_KERNEL (1 << LBR_KERNEL_BIT) 44 #define LBR_USER (1 << LBR_USER_BIT) 45 #define LBR_JCC (1 << LBR_JCC_BIT) 46 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT) 47 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT) 48 #define LBR_RETURN (1 << LBR_RETURN_BIT) 49 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT) 50 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT) 51 #define LBR_FAR (1 << LBR_FAR_BIT) 52 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT) 53 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT) 54 55 #define LBR_PLM (LBR_KERNEL | LBR_USER) 56 57 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */ 58 #define LBR_NOT_SUPP -1 /* LBR filter not supported */ 59 #define LBR_IGN 0 /* ignored */ 60 61 #define LBR_ANY \ 62 (LBR_JCC |\ 63 LBR_REL_CALL |\ 64 LBR_IND_CALL |\ 65 LBR_RETURN |\ 66 LBR_REL_JMP |\ 67 LBR_IND_JMP |\ 68 LBR_FAR) 69 70 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63) 71 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62) 72 #define LBR_FROM_FLAG_ABORT BIT_ULL(61) 73 74 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59)) 75 76 /* 77 * x86control flow change classification 78 * x86control flow changes include branches, interrupts, traps, faults 79 */ 80 enum { 81 X86_BR_NONE = 0, /* unknown */ 82 83 X86_BR_USER = 1 << 0, /* branch target is user */ 84 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ 85 86 X86_BR_CALL = 1 << 2, /* call */ 87 X86_BR_RET = 1 << 3, /* return */ 88 X86_BR_SYSCALL = 1 << 4, /* syscall */ 89 X86_BR_SYSRET = 1 << 5, /* syscall return */ 90 X86_BR_INT = 1 << 6, /* sw interrupt */ 91 X86_BR_IRET = 1 << 7, /* return from interrupt */ 92 X86_BR_JCC = 1 << 8, /* conditional */ 93 X86_BR_JMP = 1 << 9, /* jump */ 94 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ 95 X86_BR_IND_CALL = 1 << 11,/* indirect calls */ 96 X86_BR_ABORT = 1 << 12,/* transaction abort */ 97 X86_BR_IN_TX = 1 << 13,/* in transaction */ 98 X86_BR_NO_TX = 1 << 14,/* not in transaction */ 99 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ 100 X86_BR_CALL_STACK = 1 << 16,/* call stack */ 101 X86_BR_IND_JMP = 1 << 17,/* indirect jump */ 102 103 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */ 104 105 }; 106 107 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) 108 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) 109 110 #define X86_BR_ANY \ 111 (X86_BR_CALL |\ 112 X86_BR_RET |\ 113 X86_BR_SYSCALL |\ 114 X86_BR_SYSRET |\ 115 X86_BR_INT |\ 116 X86_BR_IRET |\ 117 X86_BR_JCC |\ 118 X86_BR_JMP |\ 119 X86_BR_IRQ |\ 120 X86_BR_ABORT |\ 121 X86_BR_IND_CALL |\ 122 X86_BR_IND_JMP |\ 123 X86_BR_ZERO_CALL) 124 125 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) 126 127 #define X86_BR_ANY_CALL \ 128 (X86_BR_CALL |\ 129 X86_BR_IND_CALL |\ 130 X86_BR_ZERO_CALL |\ 131 X86_BR_SYSCALL |\ 132 X86_BR_IRQ |\ 133 X86_BR_INT) 134 135 /* 136 * Intel LBR_CTL bits 137 * 138 * Hardware branch filter for Arch LBR 139 */ 140 #define ARCH_LBR_KERNEL_BIT 1 /* capture at ring0 */ 141 #define ARCH_LBR_USER_BIT 2 /* capture at ring > 0 */ 142 #define ARCH_LBR_CALL_STACK_BIT 3 /* enable call stack */ 143 #define ARCH_LBR_JCC_BIT 16 /* capture conditional branches */ 144 #define ARCH_LBR_REL_JMP_BIT 17 /* capture relative jumps */ 145 #define ARCH_LBR_IND_JMP_BIT 18 /* capture indirect jumps */ 146 #define ARCH_LBR_REL_CALL_BIT 19 /* capture relative calls */ 147 #define ARCH_LBR_IND_CALL_BIT 20 /* capture indirect calls */ 148 #define ARCH_LBR_RETURN_BIT 21 /* capture near returns */ 149 #define ARCH_LBR_OTHER_BRANCH_BIT 22 /* capture other branches */ 150 151 #define ARCH_LBR_KERNEL (1ULL << ARCH_LBR_KERNEL_BIT) 152 #define ARCH_LBR_USER (1ULL << ARCH_LBR_USER_BIT) 153 #define ARCH_LBR_CALL_STACK (1ULL << ARCH_LBR_CALL_STACK_BIT) 154 #define ARCH_LBR_JCC (1ULL << ARCH_LBR_JCC_BIT) 155 #define ARCH_LBR_REL_JMP (1ULL << ARCH_LBR_REL_JMP_BIT) 156 #define ARCH_LBR_IND_JMP (1ULL << ARCH_LBR_IND_JMP_BIT) 157 #define ARCH_LBR_REL_CALL (1ULL << ARCH_LBR_REL_CALL_BIT) 158 #define ARCH_LBR_IND_CALL (1ULL << ARCH_LBR_IND_CALL_BIT) 159 #define ARCH_LBR_RETURN (1ULL << ARCH_LBR_RETURN_BIT) 160 #define ARCH_LBR_OTHER_BRANCH (1ULL << ARCH_LBR_OTHER_BRANCH_BIT) 161 162 #define ARCH_LBR_ANY \ 163 (ARCH_LBR_JCC |\ 164 ARCH_LBR_REL_JMP |\ 165 ARCH_LBR_IND_JMP |\ 166 ARCH_LBR_REL_CALL |\ 167 ARCH_LBR_IND_CALL |\ 168 ARCH_LBR_RETURN |\ 169 ARCH_LBR_OTHER_BRANCH) 170 171 #define ARCH_LBR_CTL_MASK 0x7f000e 172 173 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); 174 175 static __always_inline bool is_lbr_call_stack_bit_set(u64 config) 176 { 177 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 178 return !!(config & ARCH_LBR_CALL_STACK); 179 180 return !!(config & LBR_CALL_STACK); 181 } 182 183 /* 184 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI 185 * otherwise it becomes near impossible to get a reliable stack. 186 */ 187 188 static void __intel_pmu_lbr_enable(bool pmi) 189 { 190 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 191 u64 debugctl, lbr_select = 0, orig_debugctl; 192 193 /* 194 * No need to unfreeze manually, as v4 can do that as part 195 * of the GLOBAL_STATUS ack. 196 */ 197 if (pmi && x86_pmu.version >= 4) 198 return; 199 200 /* 201 * No need to reprogram LBR_SELECT in a PMI, as it 202 * did not change. 203 */ 204 if (cpuc->lbr_sel) 205 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; 206 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel) 207 wrmsrl(MSR_LBR_SELECT, lbr_select); 208 209 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 210 orig_debugctl = debugctl; 211 212 if (!static_cpu_has(X86_FEATURE_ARCH_LBR)) 213 debugctl |= DEBUGCTLMSR_LBR; 214 /* 215 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI. 216 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions 217 * may cause superfluous increase/decrease of LBR_TOS. 218 */ 219 if (is_lbr_call_stack_bit_set(lbr_select)) 220 debugctl &= ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; 221 else 222 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; 223 224 if (orig_debugctl != debugctl) 225 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 226 227 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 228 wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); 229 } 230 231 void intel_pmu_lbr_reset_32(void) 232 { 233 int i; 234 235 for (i = 0; i < x86_pmu.lbr_nr; i++) 236 wrmsrl(x86_pmu.lbr_from + i, 0); 237 } 238 239 void intel_pmu_lbr_reset_64(void) 240 { 241 int i; 242 243 for (i = 0; i < x86_pmu.lbr_nr; i++) { 244 wrmsrl(x86_pmu.lbr_from + i, 0); 245 wrmsrl(x86_pmu.lbr_to + i, 0); 246 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) 247 wrmsrl(x86_pmu.lbr_info + i, 0); 248 } 249 } 250 251 static void intel_pmu_arch_lbr_reset(void) 252 { 253 /* Write to ARCH_LBR_DEPTH MSR, all LBR entries are reset to 0 */ 254 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); 255 } 256 257 void intel_pmu_lbr_reset(void) 258 { 259 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 260 261 if (!x86_pmu.lbr_nr) 262 return; 263 264 x86_pmu.lbr_reset(); 265 266 cpuc->last_task_ctx = NULL; 267 cpuc->last_log_id = 0; 268 } 269 270 /* 271 * TOS = most recently recorded branch 272 */ 273 static inline u64 intel_pmu_lbr_tos(void) 274 { 275 u64 tos; 276 277 rdmsrl(x86_pmu.lbr_tos, tos); 278 return tos; 279 } 280 281 enum { 282 LBR_NONE, 283 LBR_VALID, 284 }; 285 286 /* 287 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in 288 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when 289 * TSX is not supported they have no consistent behavior: 290 * 291 * - For wrmsr(), bits 61:62 are considered part of the sign extension. 292 * - For HW updates (branch captures) bits 61:62 are always OFF and are not 293 * part of the sign extension. 294 * 295 * Therefore, if: 296 * 297 * 1) LBR has TSX format 298 * 2) CPU has no TSX support enabled 299 * 300 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any 301 * value from rdmsr() must be converted to have a 61 bits sign extension, 302 * ignoring the TSX flags. 303 */ 304 static inline bool lbr_from_signext_quirk_needed(void) 305 { 306 int lbr_format = x86_pmu.intel_cap.lbr_format; 307 bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) || 308 boot_cpu_has(X86_FEATURE_RTM); 309 310 return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX); 311 } 312 313 static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key); 314 315 /* If quirk is enabled, ensure sign extension is 63 bits: */ 316 inline u64 lbr_from_signext_quirk_wr(u64 val) 317 { 318 if (static_branch_unlikely(&lbr_from_quirk_key)) { 319 /* 320 * Sign extend into bits 61:62 while preserving bit 63. 321 * 322 * Quirk is enabled when TSX is disabled. Therefore TSX bits 323 * in val are always OFF and must be changed to be sign 324 * extension bits. Since bits 59:60 are guaranteed to be 325 * part of the sign extension bits, we can just copy them 326 * to 61:62. 327 */ 328 val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2; 329 } 330 return val; 331 } 332 333 /* 334 * If quirk is needed, ensure sign extension is 61 bits: 335 */ 336 static u64 lbr_from_signext_quirk_rd(u64 val) 337 { 338 if (static_branch_unlikely(&lbr_from_quirk_key)) { 339 /* 340 * Quirk is on when TSX is not enabled. Therefore TSX 341 * flags must be read as OFF. 342 */ 343 val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT); 344 } 345 return val; 346 } 347 348 static __always_inline void wrlbr_from(unsigned int idx, u64 val) 349 { 350 val = lbr_from_signext_quirk_wr(val); 351 wrmsrl(x86_pmu.lbr_from + idx, val); 352 } 353 354 static __always_inline void wrlbr_to(unsigned int idx, u64 val) 355 { 356 wrmsrl(x86_pmu.lbr_to + idx, val); 357 } 358 359 static __always_inline void wrlbr_info(unsigned int idx, u64 val) 360 { 361 wrmsrl(x86_pmu.lbr_info + idx, val); 362 } 363 364 static __always_inline u64 rdlbr_from(unsigned int idx, struct lbr_entry *lbr) 365 { 366 u64 val; 367 368 if (lbr) 369 return lbr->from; 370 371 rdmsrl(x86_pmu.lbr_from + idx, val); 372 373 return lbr_from_signext_quirk_rd(val); 374 } 375 376 static __always_inline u64 rdlbr_to(unsigned int idx, struct lbr_entry *lbr) 377 { 378 u64 val; 379 380 if (lbr) 381 return lbr->to; 382 383 rdmsrl(x86_pmu.lbr_to + idx, val); 384 385 return val; 386 } 387 388 static __always_inline u64 rdlbr_info(unsigned int idx, struct lbr_entry *lbr) 389 { 390 u64 val; 391 392 if (lbr) 393 return lbr->info; 394 395 rdmsrl(x86_pmu.lbr_info + idx, val); 396 397 return val; 398 } 399 400 static inline void 401 wrlbr_all(struct lbr_entry *lbr, unsigned int idx, bool need_info) 402 { 403 wrlbr_from(idx, lbr->from); 404 wrlbr_to(idx, lbr->to); 405 if (need_info) 406 wrlbr_info(idx, lbr->info); 407 } 408 409 static inline bool 410 rdlbr_all(struct lbr_entry *lbr, unsigned int idx, bool need_info) 411 { 412 u64 from = rdlbr_from(idx, NULL); 413 414 /* Don't read invalid entry */ 415 if (!from) 416 return false; 417 418 lbr->from = from; 419 lbr->to = rdlbr_to(idx, NULL); 420 if (need_info) 421 lbr->info = rdlbr_info(idx, NULL); 422 423 return true; 424 } 425 426 void intel_pmu_lbr_restore(void *ctx) 427 { 428 bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO; 429 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 430 struct x86_perf_task_context *task_ctx = ctx; 431 int i; 432 unsigned lbr_idx, mask; 433 u64 tos = task_ctx->tos; 434 435 mask = x86_pmu.lbr_nr - 1; 436 for (i = 0; i < task_ctx->valid_lbrs; i++) { 437 lbr_idx = (tos - i) & mask; 438 wrlbr_all(&task_ctx->lbr[i], lbr_idx, need_info); 439 } 440 441 for (; i < x86_pmu.lbr_nr; i++) { 442 lbr_idx = (tos - i) & mask; 443 wrlbr_from(lbr_idx, 0); 444 wrlbr_to(lbr_idx, 0); 445 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) 446 wrlbr_info(lbr_idx, 0); 447 } 448 449 wrmsrl(x86_pmu.lbr_tos, tos); 450 451 if (cpuc->lbr_select) 452 wrmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel); 453 } 454 455 static void intel_pmu_arch_lbr_restore(void *ctx) 456 { 457 struct x86_perf_task_context_arch_lbr *task_ctx = ctx; 458 struct lbr_entry *entries = task_ctx->entries; 459 int i; 460 461 /* Fast reset the LBRs before restore if the call stack is not full. */ 462 if (!entries[x86_pmu.lbr_nr - 1].from) 463 intel_pmu_arch_lbr_reset(); 464 465 for (i = 0; i < x86_pmu.lbr_nr; i++) { 466 if (!entries[i].from) 467 break; 468 wrlbr_all(&entries[i], i, true); 469 } 470 } 471 472 /* 473 * Restore the Architecture LBR state from the xsave area in the perf 474 * context data for the task via the XRSTORS instruction. 475 */ 476 static void intel_pmu_arch_lbr_xrstors(void *ctx) 477 { 478 struct x86_perf_task_context_arch_lbr_xsave *task_ctx = ctx; 479 480 xrstors(&task_ctx->xsave, XFEATURE_MASK_LBR); 481 } 482 483 static __always_inline bool lbr_is_reset_in_cstate(void *ctx) 484 { 485 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 486 return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL); 487 488 return !rdlbr_from(((struct x86_perf_task_context *)ctx)->tos, NULL); 489 } 490 491 static void __intel_pmu_lbr_restore(void *ctx) 492 { 493 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 494 495 if (task_context_opt(ctx)->lbr_callstack_users == 0 || 496 task_context_opt(ctx)->lbr_stack_state == LBR_NONE) { 497 intel_pmu_lbr_reset(); 498 return; 499 } 500 501 /* 502 * Does not restore the LBR registers, if 503 * - No one else touched them, and 504 * - Was not cleared in Cstate 505 */ 506 if ((ctx == cpuc->last_task_ctx) && 507 (task_context_opt(ctx)->log_id == cpuc->last_log_id) && 508 !lbr_is_reset_in_cstate(ctx)) { 509 task_context_opt(ctx)->lbr_stack_state = LBR_NONE; 510 return; 511 } 512 513 x86_pmu.lbr_restore(ctx); 514 515 task_context_opt(ctx)->lbr_stack_state = LBR_NONE; 516 } 517 518 void intel_pmu_lbr_save(void *ctx) 519 { 520 bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO; 521 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 522 struct x86_perf_task_context *task_ctx = ctx; 523 unsigned lbr_idx, mask; 524 u64 tos; 525 int i; 526 527 mask = x86_pmu.lbr_nr - 1; 528 tos = intel_pmu_lbr_tos(); 529 for (i = 0; i < x86_pmu.lbr_nr; i++) { 530 lbr_idx = (tos - i) & mask; 531 if (!rdlbr_all(&task_ctx->lbr[i], lbr_idx, need_info)) 532 break; 533 } 534 task_ctx->valid_lbrs = i; 535 task_ctx->tos = tos; 536 537 if (cpuc->lbr_select) 538 rdmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel); 539 } 540 541 static void intel_pmu_arch_lbr_save(void *ctx) 542 { 543 struct x86_perf_task_context_arch_lbr *task_ctx = ctx; 544 struct lbr_entry *entries = task_ctx->entries; 545 int i; 546 547 for (i = 0; i < x86_pmu.lbr_nr; i++) { 548 if (!rdlbr_all(&entries[i], i, true)) 549 break; 550 } 551 552 /* LBR call stack is not full. Reset is required in restore. */ 553 if (i < x86_pmu.lbr_nr) 554 entries[x86_pmu.lbr_nr - 1].from = 0; 555 } 556 557 /* 558 * Save the Architecture LBR state to the xsave area in the perf 559 * context data for the task via the XSAVES instruction. 560 */ 561 static void intel_pmu_arch_lbr_xsaves(void *ctx) 562 { 563 struct x86_perf_task_context_arch_lbr_xsave *task_ctx = ctx; 564 565 xsaves(&task_ctx->xsave, XFEATURE_MASK_LBR); 566 } 567 568 static void __intel_pmu_lbr_save(void *ctx) 569 { 570 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 571 572 if (task_context_opt(ctx)->lbr_callstack_users == 0) { 573 task_context_opt(ctx)->lbr_stack_state = LBR_NONE; 574 return; 575 } 576 577 x86_pmu.lbr_save(ctx); 578 579 task_context_opt(ctx)->lbr_stack_state = LBR_VALID; 580 581 cpuc->last_task_ctx = ctx; 582 cpuc->last_log_id = ++task_context_opt(ctx)->log_id; 583 } 584 585 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 586 struct perf_event_context *next) 587 { 588 void *prev_ctx_data, *next_ctx_data; 589 590 swap(prev->task_ctx_data, next->task_ctx_data); 591 592 /* 593 * Architecture specific synchronization makes sense in 594 * case both prev->task_ctx_data and next->task_ctx_data 595 * pointers are allocated. 596 */ 597 598 prev_ctx_data = next->task_ctx_data; 599 next_ctx_data = prev->task_ctx_data; 600 601 if (!prev_ctx_data || !next_ctx_data) 602 return; 603 604 swap(task_context_opt(prev_ctx_data)->lbr_callstack_users, 605 task_context_opt(next_ctx_data)->lbr_callstack_users); 606 } 607 608 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in) 609 { 610 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 611 void *task_ctx; 612 613 if (!cpuc->lbr_users) 614 return; 615 616 /* 617 * If LBR callstack feature is enabled and the stack was saved when 618 * the task was scheduled out, restore the stack. Otherwise flush 619 * the LBR stack. 620 */ 621 task_ctx = ctx ? ctx->task_ctx_data : NULL; 622 if (task_ctx) { 623 if (sched_in) 624 __intel_pmu_lbr_restore(task_ctx); 625 else 626 __intel_pmu_lbr_save(task_ctx); 627 return; 628 } 629 630 /* 631 * Since a context switch can flip the address space and LBR entries 632 * are not tagged with an identifier, we need to wipe the LBR, even for 633 * per-cpu events. You simply cannot resolve the branches from the old 634 * address space. 635 */ 636 if (sched_in) 637 intel_pmu_lbr_reset(); 638 } 639 640 static inline bool branch_user_callstack(unsigned br_sel) 641 { 642 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK); 643 } 644 645 void intel_pmu_lbr_add(struct perf_event *event) 646 { 647 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 648 649 if (!x86_pmu.lbr_nr) 650 return; 651 652 if (event->hw.flags & PERF_X86_EVENT_LBR_SELECT) 653 cpuc->lbr_select = 1; 654 655 cpuc->br_sel = event->hw.branch_reg.reg; 656 657 if (branch_user_callstack(cpuc->br_sel) && event->ctx->task_ctx_data) 658 task_context_opt(event->ctx->task_ctx_data)->lbr_callstack_users++; 659 660 /* 661 * Request pmu::sched_task() callback, which will fire inside the 662 * regular perf event scheduling, so that call will: 663 * 664 * - restore or wipe; when LBR-callstack, 665 * - wipe; otherwise, 666 * 667 * when this is from __perf_event_task_sched_in(). 668 * 669 * However, if this is from perf_install_in_context(), no such callback 670 * will follow and we'll need to reset the LBR here if this is the 671 * first LBR event. 672 * 673 * The problem is, we cannot tell these cases apart... but we can 674 * exclude the biggest chunk of cases by looking at 675 * event->total_time_running. An event that has accrued runtime cannot 676 * be 'new'. Conversely, a new event can get installed through the 677 * context switch path for the first time. 678 */ 679 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) 680 cpuc->lbr_pebs_users++; 681 perf_sched_cb_inc(event->ctx->pmu); 682 if (!cpuc->lbr_users++ && !event->total_time_running) 683 intel_pmu_lbr_reset(); 684 } 685 686 void release_lbr_buffers(void) 687 { 688 struct kmem_cache *kmem_cache; 689 struct cpu_hw_events *cpuc; 690 int cpu; 691 692 if (!static_cpu_has(X86_FEATURE_ARCH_LBR)) 693 return; 694 695 for_each_possible_cpu(cpu) { 696 cpuc = per_cpu_ptr(&cpu_hw_events, cpu); 697 kmem_cache = x86_get_pmu(cpu)->task_ctx_cache; 698 if (kmem_cache && cpuc->lbr_xsave) { 699 kmem_cache_free(kmem_cache, cpuc->lbr_xsave); 700 cpuc->lbr_xsave = NULL; 701 } 702 } 703 } 704 705 void reserve_lbr_buffers(void) 706 { 707 struct kmem_cache *kmem_cache; 708 struct cpu_hw_events *cpuc; 709 int cpu; 710 711 if (!static_cpu_has(X86_FEATURE_ARCH_LBR)) 712 return; 713 714 for_each_possible_cpu(cpu) { 715 cpuc = per_cpu_ptr(&cpu_hw_events, cpu); 716 kmem_cache = x86_get_pmu(cpu)->task_ctx_cache; 717 if (!kmem_cache || cpuc->lbr_xsave) 718 continue; 719 720 cpuc->lbr_xsave = kmem_cache_alloc_node(kmem_cache, 721 GFP_KERNEL | __GFP_ZERO, 722 cpu_to_node(cpu)); 723 } 724 } 725 726 void intel_pmu_lbr_del(struct perf_event *event) 727 { 728 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 729 730 if (!x86_pmu.lbr_nr) 731 return; 732 733 if (branch_user_callstack(cpuc->br_sel) && 734 event->ctx->task_ctx_data) 735 task_context_opt(event->ctx->task_ctx_data)->lbr_callstack_users--; 736 737 if (event->hw.flags & PERF_X86_EVENT_LBR_SELECT) 738 cpuc->lbr_select = 0; 739 740 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) 741 cpuc->lbr_pebs_users--; 742 cpuc->lbr_users--; 743 WARN_ON_ONCE(cpuc->lbr_users < 0); 744 WARN_ON_ONCE(cpuc->lbr_pebs_users < 0); 745 perf_sched_cb_dec(event->ctx->pmu); 746 } 747 748 static inline bool vlbr_exclude_host(void) 749 { 750 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 751 752 return test_bit(INTEL_PMC_IDX_FIXED_VLBR, 753 (unsigned long *)&cpuc->intel_ctrl_guest_mask); 754 } 755 756 void intel_pmu_lbr_enable_all(bool pmi) 757 { 758 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 759 760 if (cpuc->lbr_users && !vlbr_exclude_host()) 761 __intel_pmu_lbr_enable(pmi); 762 } 763 764 void intel_pmu_lbr_disable_all(void) 765 { 766 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 767 768 if (cpuc->lbr_users && !vlbr_exclude_host()) { 769 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 770 return __intel_pmu_arch_lbr_disable(); 771 772 __intel_pmu_lbr_disable(); 773 } 774 } 775 776 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) 777 { 778 unsigned long mask = x86_pmu.lbr_nr - 1; 779 u64 tos = intel_pmu_lbr_tos(); 780 int i; 781 782 for (i = 0; i < x86_pmu.lbr_nr; i++) { 783 unsigned long lbr_idx = (tos - i) & mask; 784 union { 785 struct { 786 u32 from; 787 u32 to; 788 }; 789 u64 lbr; 790 } msr_lastbranch; 791 792 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); 793 794 cpuc->lbr_entries[i].from = msr_lastbranch.from; 795 cpuc->lbr_entries[i].to = msr_lastbranch.to; 796 cpuc->lbr_entries[i].mispred = 0; 797 cpuc->lbr_entries[i].predicted = 0; 798 cpuc->lbr_entries[i].in_tx = 0; 799 cpuc->lbr_entries[i].abort = 0; 800 cpuc->lbr_entries[i].cycles = 0; 801 cpuc->lbr_entries[i].type = 0; 802 cpuc->lbr_entries[i].reserved = 0; 803 } 804 cpuc->lbr_stack.nr = i; 805 cpuc->lbr_stack.hw_idx = tos; 806 } 807 808 /* 809 * Due to lack of segmentation in Linux the effective address (offset) 810 * is the same as the linear address, allowing us to merge the LIP and EIP 811 * LBR formats. 812 */ 813 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) 814 { 815 bool need_info = false, call_stack = false; 816 unsigned long mask = x86_pmu.lbr_nr - 1; 817 int lbr_format = x86_pmu.intel_cap.lbr_format; 818 u64 tos = intel_pmu_lbr_tos(); 819 int i; 820 int out = 0; 821 int num = x86_pmu.lbr_nr; 822 823 if (cpuc->lbr_sel) { 824 need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO); 825 if (cpuc->lbr_sel->config & LBR_CALL_STACK) 826 call_stack = true; 827 } 828 829 for (i = 0; i < num; i++) { 830 unsigned long lbr_idx = (tos - i) & mask; 831 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; 832 int skip = 0; 833 u16 cycles = 0; 834 int lbr_flags = lbr_desc[lbr_format]; 835 836 from = rdlbr_from(lbr_idx, NULL); 837 to = rdlbr_to(lbr_idx, NULL); 838 839 /* 840 * Read LBR call stack entries 841 * until invalid entry (0s) is detected. 842 */ 843 if (call_stack && !from) 844 break; 845 846 if (lbr_format == LBR_FORMAT_INFO && need_info) { 847 u64 info; 848 849 info = rdlbr_info(lbr_idx, NULL); 850 mis = !!(info & LBR_INFO_MISPRED); 851 pred = !mis; 852 in_tx = !!(info & LBR_INFO_IN_TX); 853 abort = !!(info & LBR_INFO_ABORT); 854 cycles = (info & LBR_INFO_CYCLES); 855 } 856 857 if (lbr_format == LBR_FORMAT_TIME) { 858 mis = !!(from & LBR_FROM_FLAG_MISPRED); 859 pred = !mis; 860 skip = 1; 861 cycles = ((to >> 48) & LBR_INFO_CYCLES); 862 863 to = (u64)((((s64)to) << 16) >> 16); 864 } 865 866 if (lbr_flags & LBR_EIP_FLAGS) { 867 mis = !!(from & LBR_FROM_FLAG_MISPRED); 868 pred = !mis; 869 skip = 1; 870 } 871 if (lbr_flags & LBR_TSX) { 872 in_tx = !!(from & LBR_FROM_FLAG_IN_TX); 873 abort = !!(from & LBR_FROM_FLAG_ABORT); 874 skip = 3; 875 } 876 from = (u64)((((s64)from) << skip) >> skip); 877 878 /* 879 * Some CPUs report duplicated abort records, 880 * with the second entry not having an abort bit set. 881 * Skip them here. This loop runs backwards, 882 * so we need to undo the previous record. 883 * If the abort just happened outside the window 884 * the extra entry cannot be removed. 885 */ 886 if (abort && x86_pmu.lbr_double_abort && out > 0) 887 out--; 888 889 cpuc->lbr_entries[out].from = from; 890 cpuc->lbr_entries[out].to = to; 891 cpuc->lbr_entries[out].mispred = mis; 892 cpuc->lbr_entries[out].predicted = pred; 893 cpuc->lbr_entries[out].in_tx = in_tx; 894 cpuc->lbr_entries[out].abort = abort; 895 cpuc->lbr_entries[out].cycles = cycles; 896 cpuc->lbr_entries[out].type = 0; 897 cpuc->lbr_entries[out].reserved = 0; 898 out++; 899 } 900 cpuc->lbr_stack.nr = out; 901 cpuc->lbr_stack.hw_idx = tos; 902 } 903 904 static __always_inline int get_lbr_br_type(u64 info) 905 { 906 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) || !x86_pmu.lbr_br_type) 907 return 0; 908 909 return (info & LBR_INFO_BR_TYPE) >> LBR_INFO_BR_TYPE_OFFSET; 910 } 911 912 static __always_inline bool get_lbr_mispred(u64 info) 913 { 914 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred) 915 return 0; 916 917 return !!(info & LBR_INFO_MISPRED); 918 } 919 920 static __always_inline bool get_lbr_predicted(u64 info) 921 { 922 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred) 923 return 0; 924 925 return !(info & LBR_INFO_MISPRED); 926 } 927 928 static __always_inline u16 get_lbr_cycles(u64 info) 929 { 930 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && 931 !(x86_pmu.lbr_timed_lbr && info & LBR_INFO_CYC_CNT_VALID)) 932 return 0; 933 934 return info & LBR_INFO_CYCLES; 935 } 936 937 static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc, 938 struct lbr_entry *entries) 939 { 940 struct perf_branch_entry *e; 941 struct lbr_entry *lbr; 942 u64 from, to, info; 943 int i; 944 945 for (i = 0; i < x86_pmu.lbr_nr; i++) { 946 lbr = entries ? &entries[i] : NULL; 947 e = &cpuc->lbr_entries[i]; 948 949 from = rdlbr_from(i, lbr); 950 /* 951 * Read LBR entries until invalid entry (0s) is detected. 952 */ 953 if (!from) 954 break; 955 956 to = rdlbr_to(i, lbr); 957 info = rdlbr_info(i, lbr); 958 959 e->from = from; 960 e->to = to; 961 e->mispred = get_lbr_mispred(info); 962 e->predicted = get_lbr_predicted(info); 963 e->in_tx = !!(info & LBR_INFO_IN_TX); 964 e->abort = !!(info & LBR_INFO_ABORT); 965 e->cycles = get_lbr_cycles(info); 966 e->type = get_lbr_br_type(info); 967 e->reserved = 0; 968 } 969 970 cpuc->lbr_stack.nr = i; 971 } 972 973 static void intel_pmu_arch_lbr_read(struct cpu_hw_events *cpuc) 974 { 975 intel_pmu_store_lbr(cpuc, NULL); 976 } 977 978 static void intel_pmu_arch_lbr_read_xsave(struct cpu_hw_events *cpuc) 979 { 980 struct x86_perf_task_context_arch_lbr_xsave *xsave = cpuc->lbr_xsave; 981 982 if (!xsave) { 983 intel_pmu_store_lbr(cpuc, NULL); 984 return; 985 } 986 xsaves(&xsave->xsave, XFEATURE_MASK_LBR); 987 988 intel_pmu_store_lbr(cpuc, xsave->lbr.entries); 989 } 990 991 void intel_pmu_lbr_read(void) 992 { 993 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 994 995 /* 996 * Don't read when all LBRs users are using adaptive PEBS. 997 * 998 * This could be smarter and actually check the event, 999 * but this simple approach seems to work for now. 1000 */ 1001 if (!cpuc->lbr_users || vlbr_exclude_host() || 1002 cpuc->lbr_users == cpuc->lbr_pebs_users) 1003 return; 1004 1005 x86_pmu.lbr_read(cpuc); 1006 1007 intel_pmu_lbr_filter(cpuc); 1008 } 1009 1010 /* 1011 * SW filter is used: 1012 * - in case there is no HW filter 1013 * - in case the HW filter has errata or limitations 1014 */ 1015 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event) 1016 { 1017 u64 br_type = event->attr.branch_sample_type; 1018 int mask = 0; 1019 1020 if (br_type & PERF_SAMPLE_BRANCH_USER) 1021 mask |= X86_BR_USER; 1022 1023 if (br_type & PERF_SAMPLE_BRANCH_KERNEL) 1024 mask |= X86_BR_KERNEL; 1025 1026 /* we ignore BRANCH_HV here */ 1027 1028 if (br_type & PERF_SAMPLE_BRANCH_ANY) 1029 mask |= X86_BR_ANY; 1030 1031 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL) 1032 mask |= X86_BR_ANY_CALL; 1033 1034 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 1035 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET; 1036 1037 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL) 1038 mask |= X86_BR_IND_CALL; 1039 1040 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX) 1041 mask |= X86_BR_ABORT; 1042 1043 if (br_type & PERF_SAMPLE_BRANCH_IN_TX) 1044 mask |= X86_BR_IN_TX; 1045 1046 if (br_type & PERF_SAMPLE_BRANCH_NO_TX) 1047 mask |= X86_BR_NO_TX; 1048 1049 if (br_type & PERF_SAMPLE_BRANCH_COND) 1050 mask |= X86_BR_JCC; 1051 1052 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) { 1053 if (!x86_pmu_has_lbr_callstack()) 1054 return -EOPNOTSUPP; 1055 if (mask & ~(X86_BR_USER | X86_BR_KERNEL)) 1056 return -EINVAL; 1057 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET | 1058 X86_BR_CALL_STACK; 1059 } 1060 1061 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP) 1062 mask |= X86_BR_IND_JMP; 1063 1064 if (br_type & PERF_SAMPLE_BRANCH_CALL) 1065 mask |= X86_BR_CALL | X86_BR_ZERO_CALL; 1066 1067 if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE) 1068 mask |= X86_BR_TYPE_SAVE; 1069 1070 /* 1071 * stash actual user request into reg, it may 1072 * be used by fixup code for some CPU 1073 */ 1074 event->hw.branch_reg.reg = mask; 1075 return 0; 1076 } 1077 1078 /* 1079 * setup the HW LBR filter 1080 * Used only when available, may not be enough to disambiguate 1081 * all branches, may need the help of the SW filter 1082 */ 1083 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) 1084 { 1085 struct hw_perf_event_extra *reg; 1086 u64 br_type = event->attr.branch_sample_type; 1087 u64 mask = 0, v; 1088 int i; 1089 1090 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) { 1091 if (!(br_type & (1ULL << i))) 1092 continue; 1093 1094 v = x86_pmu.lbr_sel_map[i]; 1095 if (v == LBR_NOT_SUPP) 1096 return -EOPNOTSUPP; 1097 1098 if (v != LBR_IGN) 1099 mask |= v; 1100 } 1101 1102 reg = &event->hw.branch_reg; 1103 reg->idx = EXTRA_REG_LBR; 1104 1105 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) { 1106 reg->config = mask; 1107 return 0; 1108 } 1109 1110 /* 1111 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate 1112 * in suppress mode. So LBR_SELECT should be set to 1113 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) 1114 * But the 10th bit LBR_CALL_STACK does not operate 1115 * in suppress mode. 1116 */ 1117 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); 1118 1119 if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) && 1120 (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) && 1121 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)) 1122 reg->config |= LBR_NO_INFO; 1123 1124 return 0; 1125 } 1126 1127 int intel_pmu_setup_lbr_filter(struct perf_event *event) 1128 { 1129 int ret = 0; 1130 1131 /* 1132 * no LBR on this PMU 1133 */ 1134 if (!x86_pmu.lbr_nr) 1135 return -EOPNOTSUPP; 1136 1137 /* 1138 * setup SW LBR filter 1139 */ 1140 ret = intel_pmu_setup_sw_lbr_filter(event); 1141 if (ret) 1142 return ret; 1143 1144 /* 1145 * setup HW LBR filter, if any 1146 */ 1147 if (x86_pmu.lbr_sel_map) 1148 ret = intel_pmu_setup_hw_lbr_filter(event); 1149 1150 return ret; 1151 } 1152 1153 /* 1154 * return the type of control flow change at address "from" 1155 * instruction is not necessarily a branch (in case of interrupt). 1156 * 1157 * The branch type returned also includes the priv level of the 1158 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL). 1159 * 1160 * If a branch type is unknown OR the instruction cannot be 1161 * decoded (e.g., text page not present), then X86_BR_NONE is 1162 * returned. 1163 */ 1164 static int branch_type(unsigned long from, unsigned long to, int abort) 1165 { 1166 struct insn insn; 1167 void *addr; 1168 int bytes_read, bytes_left; 1169 int ret = X86_BR_NONE; 1170 int ext, to_plm, from_plm; 1171 u8 buf[MAX_INSN_SIZE]; 1172 int is64 = 0; 1173 1174 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER; 1175 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER; 1176 1177 /* 1178 * maybe zero if lbr did not fill up after a reset by the time 1179 * we get a PMU interrupt 1180 */ 1181 if (from == 0 || to == 0) 1182 return X86_BR_NONE; 1183 1184 if (abort) 1185 return X86_BR_ABORT | to_plm; 1186 1187 if (from_plm == X86_BR_USER) { 1188 /* 1189 * can happen if measuring at the user level only 1190 * and we interrupt in a kernel thread, e.g., idle. 1191 */ 1192 if (!current->mm) 1193 return X86_BR_NONE; 1194 1195 /* may fail if text not present */ 1196 bytes_left = copy_from_user_nmi(buf, (void __user *)from, 1197 MAX_INSN_SIZE); 1198 bytes_read = MAX_INSN_SIZE - bytes_left; 1199 if (!bytes_read) 1200 return X86_BR_NONE; 1201 1202 addr = buf; 1203 } else { 1204 /* 1205 * The LBR logs any address in the IP, even if the IP just 1206 * faulted. This means userspace can control the from address. 1207 * Ensure we don't blindly read any address by validating it is 1208 * a known text address. 1209 */ 1210 if (kernel_text_address(from)) { 1211 addr = (void *)from; 1212 /* 1213 * Assume we can get the maximum possible size 1214 * when grabbing kernel data. This is not 1215 * _strictly_ true since we could possibly be 1216 * executing up next to a memory hole, but 1217 * it is very unlikely to be a problem. 1218 */ 1219 bytes_read = MAX_INSN_SIZE; 1220 } else { 1221 return X86_BR_NONE; 1222 } 1223 } 1224 1225 /* 1226 * decoder needs to know the ABI especially 1227 * on 64-bit systems running 32-bit apps 1228 */ 1229 #ifdef CONFIG_X86_64 1230 is64 = kernel_ip((unsigned long)addr) || any_64bit_mode(current_pt_regs()); 1231 #endif 1232 insn_init(&insn, addr, bytes_read, is64); 1233 if (insn_get_opcode(&insn)) 1234 return X86_BR_ABORT; 1235 1236 switch (insn.opcode.bytes[0]) { 1237 case 0xf: 1238 switch (insn.opcode.bytes[1]) { 1239 case 0x05: /* syscall */ 1240 case 0x34: /* sysenter */ 1241 ret = X86_BR_SYSCALL; 1242 break; 1243 case 0x07: /* sysret */ 1244 case 0x35: /* sysexit */ 1245 ret = X86_BR_SYSRET; 1246 break; 1247 case 0x80 ... 0x8f: /* conditional */ 1248 ret = X86_BR_JCC; 1249 break; 1250 default: 1251 ret = X86_BR_NONE; 1252 } 1253 break; 1254 case 0x70 ... 0x7f: /* conditional */ 1255 ret = X86_BR_JCC; 1256 break; 1257 case 0xc2: /* near ret */ 1258 case 0xc3: /* near ret */ 1259 case 0xca: /* far ret */ 1260 case 0xcb: /* far ret */ 1261 ret = X86_BR_RET; 1262 break; 1263 case 0xcf: /* iret */ 1264 ret = X86_BR_IRET; 1265 break; 1266 case 0xcc ... 0xce: /* int */ 1267 ret = X86_BR_INT; 1268 break; 1269 case 0xe8: /* call near rel */ 1270 if (insn_get_immediate(&insn) || insn.immediate1.value == 0) { 1271 /* zero length call */ 1272 ret = X86_BR_ZERO_CALL; 1273 break; 1274 } 1275 fallthrough; 1276 case 0x9a: /* call far absolute */ 1277 ret = X86_BR_CALL; 1278 break; 1279 case 0xe0 ... 0xe3: /* loop jmp */ 1280 ret = X86_BR_JCC; 1281 break; 1282 case 0xe9 ... 0xeb: /* jmp */ 1283 ret = X86_BR_JMP; 1284 break; 1285 case 0xff: /* call near absolute, call far absolute ind */ 1286 if (insn_get_modrm(&insn)) 1287 return X86_BR_ABORT; 1288 1289 ext = (insn.modrm.bytes[0] >> 3) & 0x7; 1290 switch (ext) { 1291 case 2: /* near ind call */ 1292 case 3: /* far ind call */ 1293 ret = X86_BR_IND_CALL; 1294 break; 1295 case 4: 1296 case 5: 1297 ret = X86_BR_IND_JMP; 1298 break; 1299 } 1300 break; 1301 default: 1302 ret = X86_BR_NONE; 1303 } 1304 /* 1305 * interrupts, traps, faults (and thus ring transition) may 1306 * occur on any instructions. Thus, to classify them correctly, 1307 * we need to first look at the from and to priv levels. If they 1308 * are different and to is in the kernel, then it indicates 1309 * a ring transition. If the from instruction is not a ring 1310 * transition instr (syscall, systenter, int), then it means 1311 * it was a irq, trap or fault. 1312 * 1313 * we have no way of detecting kernel to kernel faults. 1314 */ 1315 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL 1316 && ret != X86_BR_SYSCALL && ret != X86_BR_INT) 1317 ret = X86_BR_IRQ; 1318 1319 /* 1320 * branch priv level determined by target as 1321 * is done by HW when LBR_SELECT is implemented 1322 */ 1323 if (ret != X86_BR_NONE) 1324 ret |= to_plm; 1325 1326 return ret; 1327 } 1328 1329 #define X86_BR_TYPE_MAP_MAX 16 1330 1331 static int branch_map[X86_BR_TYPE_MAP_MAX] = { 1332 PERF_BR_CALL, /* X86_BR_CALL */ 1333 PERF_BR_RET, /* X86_BR_RET */ 1334 PERF_BR_SYSCALL, /* X86_BR_SYSCALL */ 1335 PERF_BR_SYSRET, /* X86_BR_SYSRET */ 1336 PERF_BR_UNKNOWN, /* X86_BR_INT */ 1337 PERF_BR_UNKNOWN, /* X86_BR_IRET */ 1338 PERF_BR_COND, /* X86_BR_JCC */ 1339 PERF_BR_UNCOND, /* X86_BR_JMP */ 1340 PERF_BR_UNKNOWN, /* X86_BR_IRQ */ 1341 PERF_BR_IND_CALL, /* X86_BR_IND_CALL */ 1342 PERF_BR_UNKNOWN, /* X86_BR_ABORT */ 1343 PERF_BR_UNKNOWN, /* X86_BR_IN_TX */ 1344 PERF_BR_UNKNOWN, /* X86_BR_NO_TX */ 1345 PERF_BR_CALL, /* X86_BR_ZERO_CALL */ 1346 PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */ 1347 PERF_BR_IND, /* X86_BR_IND_JMP */ 1348 }; 1349 1350 static int 1351 common_branch_type(int type) 1352 { 1353 int i; 1354 1355 type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */ 1356 1357 if (type) { 1358 i = __ffs(type); 1359 if (i < X86_BR_TYPE_MAP_MAX) 1360 return branch_map[i]; 1361 } 1362 1363 return PERF_BR_UNKNOWN; 1364 } 1365 1366 enum { 1367 ARCH_LBR_BR_TYPE_JCC = 0, 1368 ARCH_LBR_BR_TYPE_NEAR_IND_JMP = 1, 1369 ARCH_LBR_BR_TYPE_NEAR_REL_JMP = 2, 1370 ARCH_LBR_BR_TYPE_NEAR_IND_CALL = 3, 1371 ARCH_LBR_BR_TYPE_NEAR_REL_CALL = 4, 1372 ARCH_LBR_BR_TYPE_NEAR_RET = 5, 1373 ARCH_LBR_BR_TYPE_KNOWN_MAX = ARCH_LBR_BR_TYPE_NEAR_RET, 1374 1375 ARCH_LBR_BR_TYPE_MAP_MAX = 16, 1376 }; 1377 1378 static const int arch_lbr_br_type_map[ARCH_LBR_BR_TYPE_MAP_MAX] = { 1379 [ARCH_LBR_BR_TYPE_JCC] = X86_BR_JCC, 1380 [ARCH_LBR_BR_TYPE_NEAR_IND_JMP] = X86_BR_IND_JMP, 1381 [ARCH_LBR_BR_TYPE_NEAR_REL_JMP] = X86_BR_JMP, 1382 [ARCH_LBR_BR_TYPE_NEAR_IND_CALL] = X86_BR_IND_CALL, 1383 [ARCH_LBR_BR_TYPE_NEAR_REL_CALL] = X86_BR_CALL, 1384 [ARCH_LBR_BR_TYPE_NEAR_RET] = X86_BR_RET, 1385 }; 1386 1387 /* 1388 * implement actual branch filter based on user demand. 1389 * Hardware may not exactly satisfy that request, thus 1390 * we need to inspect opcodes. Mismatched branches are 1391 * discarded. Therefore, the number of branches returned 1392 * in PERF_SAMPLE_BRANCH_STACK sample may vary. 1393 */ 1394 static void 1395 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) 1396 { 1397 u64 from, to; 1398 int br_sel = cpuc->br_sel; 1399 int i, j, type, to_plm; 1400 bool compress = false; 1401 1402 /* if sampling all branches, then nothing to filter */ 1403 if (((br_sel & X86_BR_ALL) == X86_BR_ALL) && 1404 ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE)) 1405 return; 1406 1407 for (i = 0; i < cpuc->lbr_stack.nr; i++) { 1408 1409 from = cpuc->lbr_entries[i].from; 1410 to = cpuc->lbr_entries[i].to; 1411 type = cpuc->lbr_entries[i].type; 1412 1413 /* 1414 * Parse the branch type recorded in LBR_x_INFO MSR. 1415 * Doesn't support OTHER_BRANCH decoding for now. 1416 * OTHER_BRANCH branch type still rely on software decoding. 1417 */ 1418 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && 1419 type <= ARCH_LBR_BR_TYPE_KNOWN_MAX) { 1420 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER; 1421 type = arch_lbr_br_type_map[type] | to_plm; 1422 } else 1423 type = branch_type(from, to, cpuc->lbr_entries[i].abort); 1424 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) { 1425 if (cpuc->lbr_entries[i].in_tx) 1426 type |= X86_BR_IN_TX; 1427 else 1428 type |= X86_BR_NO_TX; 1429 } 1430 1431 /* if type does not correspond, then discard */ 1432 if (type == X86_BR_NONE || (br_sel & type) != type) { 1433 cpuc->lbr_entries[i].from = 0; 1434 compress = true; 1435 } 1436 1437 if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE) 1438 cpuc->lbr_entries[i].type = common_branch_type(type); 1439 } 1440 1441 if (!compress) 1442 return; 1443 1444 /* remove all entries with from=0 */ 1445 for (i = 0; i < cpuc->lbr_stack.nr; ) { 1446 if (!cpuc->lbr_entries[i].from) { 1447 j = i; 1448 while (++j < cpuc->lbr_stack.nr) 1449 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; 1450 cpuc->lbr_stack.nr--; 1451 if (!cpuc->lbr_entries[i].from) 1452 continue; 1453 } 1454 i++; 1455 } 1456 } 1457 1458 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr) 1459 { 1460 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1461 1462 /* Cannot get TOS for large PEBS and Arch LBR */ 1463 if (static_cpu_has(X86_FEATURE_ARCH_LBR) || 1464 (cpuc->n_pebs == cpuc->n_large_pebs)) 1465 cpuc->lbr_stack.hw_idx = -1ULL; 1466 else 1467 cpuc->lbr_stack.hw_idx = intel_pmu_lbr_tos(); 1468 1469 intel_pmu_store_lbr(cpuc, lbr); 1470 intel_pmu_lbr_filter(cpuc); 1471 } 1472 1473 /* 1474 * Map interface branch filters onto LBR filters 1475 */ 1476 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1477 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, 1478 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, 1479 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, 1480 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1481 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP 1482 | LBR_IND_JMP | LBR_FAR, 1483 /* 1484 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches 1485 */ 1486 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = 1487 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR, 1488 /* 1489 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL 1490 */ 1491 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP, 1492 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, 1493 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, 1494 }; 1495 1496 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1497 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, 1498 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, 1499 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, 1500 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1501 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, 1502 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL 1503 | LBR_FAR, 1504 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, 1505 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, 1506 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, 1507 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL, 1508 }; 1509 1510 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1511 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, 1512 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, 1513 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, 1514 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1515 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, 1516 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL 1517 | LBR_FAR, 1518 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, 1519 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, 1520 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL 1521 | LBR_RETURN | LBR_CALL_STACK, 1522 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, 1523 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL, 1524 }; 1525 1526 static int arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1527 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = ARCH_LBR_ANY, 1528 [PERF_SAMPLE_BRANCH_USER_SHIFT] = ARCH_LBR_USER, 1529 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = ARCH_LBR_KERNEL, 1530 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1531 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = ARCH_LBR_RETURN | 1532 ARCH_LBR_OTHER_BRANCH, 1533 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = ARCH_LBR_REL_CALL | 1534 ARCH_LBR_IND_CALL | 1535 ARCH_LBR_OTHER_BRANCH, 1536 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = ARCH_LBR_IND_CALL, 1537 [PERF_SAMPLE_BRANCH_COND_SHIFT] = ARCH_LBR_JCC, 1538 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = ARCH_LBR_REL_CALL | 1539 ARCH_LBR_IND_CALL | 1540 ARCH_LBR_RETURN | 1541 ARCH_LBR_CALL_STACK, 1542 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = ARCH_LBR_IND_JMP, 1543 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = ARCH_LBR_REL_CALL, 1544 }; 1545 1546 /* core */ 1547 void __init intel_pmu_lbr_init_core(void) 1548 { 1549 x86_pmu.lbr_nr = 4; 1550 x86_pmu.lbr_tos = MSR_LBR_TOS; 1551 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 1552 x86_pmu.lbr_to = MSR_LBR_CORE_TO; 1553 1554 /* 1555 * SW branch filter usage: 1556 * - compensate for lack of HW filter 1557 */ 1558 } 1559 1560 /* nehalem/westmere */ 1561 void __init intel_pmu_lbr_init_nhm(void) 1562 { 1563 x86_pmu.lbr_nr = 16; 1564 x86_pmu.lbr_tos = MSR_LBR_TOS; 1565 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1566 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1567 1568 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1569 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; 1570 1571 /* 1572 * SW branch filter usage: 1573 * - workaround LBR_SEL errata (see above) 1574 * - support syscall, sysret capture. 1575 * That requires LBR_FAR but that means far 1576 * jmp need to be filtered out 1577 */ 1578 } 1579 1580 /* sandy bridge */ 1581 void __init intel_pmu_lbr_init_snb(void) 1582 { 1583 x86_pmu.lbr_nr = 16; 1584 x86_pmu.lbr_tos = MSR_LBR_TOS; 1585 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1586 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1587 1588 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1589 x86_pmu.lbr_sel_map = snb_lbr_sel_map; 1590 1591 /* 1592 * SW branch filter usage: 1593 * - support syscall, sysret capture. 1594 * That requires LBR_FAR but that means far 1595 * jmp need to be filtered out 1596 */ 1597 } 1598 1599 static inline struct kmem_cache * 1600 create_lbr_kmem_cache(size_t size, size_t align) 1601 { 1602 return kmem_cache_create("x86_lbr", size, align, 0, NULL); 1603 } 1604 1605 /* haswell */ 1606 void intel_pmu_lbr_init_hsw(void) 1607 { 1608 size_t size = sizeof(struct x86_perf_task_context); 1609 1610 x86_pmu.lbr_nr = 16; 1611 x86_pmu.lbr_tos = MSR_LBR_TOS; 1612 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1613 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1614 1615 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1616 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; 1617 1618 x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0); 1619 1620 if (lbr_from_signext_quirk_needed()) 1621 static_branch_enable(&lbr_from_quirk_key); 1622 } 1623 1624 /* skylake */ 1625 __init void intel_pmu_lbr_init_skl(void) 1626 { 1627 size_t size = sizeof(struct x86_perf_task_context); 1628 1629 x86_pmu.lbr_nr = 32; 1630 x86_pmu.lbr_tos = MSR_LBR_TOS; 1631 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1632 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1633 x86_pmu.lbr_info = MSR_LBR_INFO_0; 1634 1635 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1636 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; 1637 1638 x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0); 1639 1640 /* 1641 * SW branch filter usage: 1642 * - support syscall, sysret capture. 1643 * That requires LBR_FAR but that means far 1644 * jmp need to be filtered out 1645 */ 1646 } 1647 1648 /* atom */ 1649 void __init intel_pmu_lbr_init_atom(void) 1650 { 1651 /* 1652 * only models starting at stepping 10 seems 1653 * to have an operational LBR which can freeze 1654 * on PMU interrupt 1655 */ 1656 if (boot_cpu_data.x86_model == 28 1657 && boot_cpu_data.x86_stepping < 10) { 1658 pr_cont("LBR disabled due to erratum"); 1659 return; 1660 } 1661 1662 x86_pmu.lbr_nr = 8; 1663 x86_pmu.lbr_tos = MSR_LBR_TOS; 1664 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 1665 x86_pmu.lbr_to = MSR_LBR_CORE_TO; 1666 1667 /* 1668 * SW branch filter usage: 1669 * - compensate for lack of HW filter 1670 */ 1671 } 1672 1673 /* slm */ 1674 void __init intel_pmu_lbr_init_slm(void) 1675 { 1676 x86_pmu.lbr_nr = 8; 1677 x86_pmu.lbr_tos = MSR_LBR_TOS; 1678 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 1679 x86_pmu.lbr_to = MSR_LBR_CORE_TO; 1680 1681 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1682 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; 1683 1684 /* 1685 * SW branch filter usage: 1686 * - compensate for lack of HW filter 1687 */ 1688 pr_cont("8-deep LBR, "); 1689 } 1690 1691 /* Knights Landing */ 1692 void intel_pmu_lbr_init_knl(void) 1693 { 1694 x86_pmu.lbr_nr = 8; 1695 x86_pmu.lbr_tos = MSR_LBR_TOS; 1696 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1697 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1698 1699 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1700 x86_pmu.lbr_sel_map = snb_lbr_sel_map; 1701 1702 /* Knights Landing does have MISPREDICT bit */ 1703 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP) 1704 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS; 1705 } 1706 1707 /* 1708 * LBR state size is variable based on the max number of registers. 1709 * This calculates the expected state size, which should match 1710 * what the hardware enumerates for the size of XFEATURE_LBR. 1711 */ 1712 static inline unsigned int get_lbr_state_size(void) 1713 { 1714 return sizeof(struct arch_lbr_state) + 1715 x86_pmu.lbr_nr * sizeof(struct lbr_entry); 1716 } 1717 1718 static bool is_arch_lbr_xsave_available(void) 1719 { 1720 if (!boot_cpu_has(X86_FEATURE_XSAVES)) 1721 return false; 1722 1723 /* 1724 * Check the LBR state with the corresponding software structure. 1725 * Disable LBR XSAVES support if the size doesn't match. 1726 */ 1727 if (WARN_ON(xfeature_size(XFEATURE_LBR) != get_lbr_state_size())) 1728 return false; 1729 1730 return true; 1731 } 1732 1733 void __init intel_pmu_arch_lbr_init(void) 1734 { 1735 struct pmu *pmu = x86_get_pmu(smp_processor_id()); 1736 union cpuid28_eax eax; 1737 union cpuid28_ebx ebx; 1738 union cpuid28_ecx ecx; 1739 unsigned int unused_edx; 1740 bool arch_lbr_xsave; 1741 size_t size; 1742 u64 lbr_nr; 1743 1744 /* Arch LBR Capabilities */ 1745 cpuid(28, &eax.full, &ebx.full, &ecx.full, &unused_edx); 1746 1747 lbr_nr = fls(eax.split.lbr_depth_mask) * 8; 1748 if (!lbr_nr) 1749 goto clear_arch_lbr; 1750 1751 /* Apply the max depth of Arch LBR */ 1752 if (wrmsrl_safe(MSR_ARCH_LBR_DEPTH, lbr_nr)) 1753 goto clear_arch_lbr; 1754 1755 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask; 1756 x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset; 1757 x86_pmu.lbr_lip = eax.split.lbr_lip; 1758 x86_pmu.lbr_cpl = ebx.split.lbr_cpl; 1759 x86_pmu.lbr_filter = ebx.split.lbr_filter; 1760 x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack; 1761 x86_pmu.lbr_mispred = ecx.split.lbr_mispred; 1762 x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr; 1763 x86_pmu.lbr_br_type = ecx.split.lbr_br_type; 1764 x86_pmu.lbr_nr = lbr_nr; 1765 1766 1767 arch_lbr_xsave = is_arch_lbr_xsave_available(); 1768 if (arch_lbr_xsave) { 1769 size = sizeof(struct x86_perf_task_context_arch_lbr_xsave) + 1770 get_lbr_state_size(); 1771 pmu->task_ctx_cache = create_lbr_kmem_cache(size, 1772 XSAVE_ALIGNMENT); 1773 } 1774 1775 if (!pmu->task_ctx_cache) { 1776 arch_lbr_xsave = false; 1777 1778 size = sizeof(struct x86_perf_task_context_arch_lbr) + 1779 lbr_nr * sizeof(struct lbr_entry); 1780 pmu->task_ctx_cache = create_lbr_kmem_cache(size, 0); 1781 } 1782 1783 x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0; 1784 x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0; 1785 x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0; 1786 1787 /* LBR callstack requires both CPL and Branch Filtering support */ 1788 if (!x86_pmu.lbr_cpl || 1789 !x86_pmu.lbr_filter || 1790 !x86_pmu.lbr_call_stack) 1791 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_NOT_SUPP; 1792 1793 if (!x86_pmu.lbr_cpl) { 1794 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_NOT_SUPP; 1795 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_NOT_SUPP; 1796 } else if (!x86_pmu.lbr_filter) { 1797 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_NOT_SUPP; 1798 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_NOT_SUPP; 1799 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_NOT_SUPP; 1800 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_NOT_SUPP; 1801 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_NOT_SUPP; 1802 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_NOT_SUPP; 1803 arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_NOT_SUPP; 1804 } 1805 1806 x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK; 1807 x86_pmu.lbr_ctl_map = arch_lbr_ctl_map; 1808 1809 if (!x86_pmu.lbr_cpl && !x86_pmu.lbr_filter) 1810 x86_pmu.lbr_ctl_map = NULL; 1811 1812 x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset; 1813 if (arch_lbr_xsave) { 1814 x86_pmu.lbr_save = intel_pmu_arch_lbr_xsaves; 1815 x86_pmu.lbr_restore = intel_pmu_arch_lbr_xrstors; 1816 x86_pmu.lbr_read = intel_pmu_arch_lbr_read_xsave; 1817 pr_cont("XSAVE "); 1818 } else { 1819 x86_pmu.lbr_save = intel_pmu_arch_lbr_save; 1820 x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore; 1821 x86_pmu.lbr_read = intel_pmu_arch_lbr_read; 1822 } 1823 1824 pr_cont("Architectural LBR, "); 1825 1826 return; 1827 1828 clear_arch_lbr: 1829 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_ARCH_LBR); 1830 } 1831 1832 /** 1833 * x86_perf_get_lbr - get the LBR records information 1834 * 1835 * @lbr: the caller's memory to store the LBR records information 1836 * 1837 * Returns: 0 indicates the LBR info has been successfully obtained 1838 */ 1839 int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) 1840 { 1841 int lbr_fmt = x86_pmu.intel_cap.lbr_format; 1842 1843 lbr->nr = x86_pmu.lbr_nr; 1844 lbr->from = x86_pmu.lbr_from; 1845 lbr->to = x86_pmu.lbr_to; 1846 lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; 1847 1848 return 0; 1849 } 1850 EXPORT_SYMBOL_GPL(x86_perf_get_lbr); 1851 1852 struct event_constraint vlbr_constraint = 1853 __EVENT_CONSTRAINT(INTEL_FIXED_VLBR_EVENT, (1ULL << INTEL_PMC_IDX_FIXED_VLBR), 1854 FIXED_EVENT_FLAGS, 1, 0, PERF_X86_EVENT_LBR_SELECT); 1855