1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/perf_event.h> 3 #include <linux/types.h> 4 5 #include <asm/perf_event.h> 6 #include <asm/msr.h> 7 #include <asm/insn.h> 8 9 #include "../perf_event.h" 10 11 enum { 12 LBR_FORMAT_32 = 0x00, 13 LBR_FORMAT_LIP = 0x01, 14 LBR_FORMAT_EIP = 0x02, 15 LBR_FORMAT_EIP_FLAGS = 0x03, 16 LBR_FORMAT_EIP_FLAGS2 = 0x04, 17 LBR_FORMAT_INFO = 0x05, 18 LBR_FORMAT_TIME = 0x06, 19 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME, 20 }; 21 22 static const enum { 23 LBR_EIP_FLAGS = 1, 24 LBR_TSX = 2, 25 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = { 26 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS, 27 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX, 28 }; 29 30 /* 31 * Intel LBR_SELECT bits 32 * Intel Vol3a, April 2011, Section 16.7 Table 16-10 33 * 34 * Hardware branch filter (not available on all CPUs) 35 */ 36 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */ 37 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */ 38 #define LBR_JCC_BIT 2 /* do not capture conditional branches */ 39 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */ 40 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */ 41 #define LBR_RETURN_BIT 5 /* do not capture near returns */ 42 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */ 43 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */ 44 #define LBR_FAR_BIT 8 /* do not capture far branches */ 45 #define LBR_CALL_STACK_BIT 9 /* enable call stack */ 46 47 /* 48 * Following bit only exists in Linux; we mask it out before writing it to 49 * the actual MSR. But it helps the constraint perf code to understand 50 * that this is a separate configuration. 51 */ 52 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */ 53 54 #define LBR_KERNEL (1 << LBR_KERNEL_BIT) 55 #define LBR_USER (1 << LBR_USER_BIT) 56 #define LBR_JCC (1 << LBR_JCC_BIT) 57 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT) 58 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT) 59 #define LBR_RETURN (1 << LBR_RETURN_BIT) 60 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT) 61 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT) 62 #define LBR_FAR (1 << LBR_FAR_BIT) 63 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT) 64 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT) 65 66 #define LBR_PLM (LBR_KERNEL | LBR_USER) 67 68 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */ 69 #define LBR_NOT_SUPP -1 /* LBR filter not supported */ 70 #define LBR_IGN 0 /* ignored */ 71 72 #define LBR_ANY \ 73 (LBR_JCC |\ 74 LBR_REL_CALL |\ 75 LBR_IND_CALL |\ 76 LBR_RETURN |\ 77 LBR_REL_JMP |\ 78 LBR_IND_JMP |\ 79 LBR_FAR) 80 81 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63) 82 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62) 83 #define LBR_FROM_FLAG_ABORT BIT_ULL(61) 84 85 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59)) 86 87 /* 88 * x86control flow change classification 89 * x86control flow changes include branches, interrupts, traps, faults 90 */ 91 enum { 92 X86_BR_NONE = 0, /* unknown */ 93 94 X86_BR_USER = 1 << 0, /* branch target is user */ 95 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ 96 97 X86_BR_CALL = 1 << 2, /* call */ 98 X86_BR_RET = 1 << 3, /* return */ 99 X86_BR_SYSCALL = 1 << 4, /* syscall */ 100 X86_BR_SYSRET = 1 << 5, /* syscall return */ 101 X86_BR_INT = 1 << 6, /* sw interrupt */ 102 X86_BR_IRET = 1 << 7, /* return from interrupt */ 103 X86_BR_JCC = 1 << 8, /* conditional */ 104 X86_BR_JMP = 1 << 9, /* jump */ 105 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ 106 X86_BR_IND_CALL = 1 << 11,/* indirect calls */ 107 X86_BR_ABORT = 1 << 12,/* transaction abort */ 108 X86_BR_IN_TX = 1 << 13,/* in transaction */ 109 X86_BR_NO_TX = 1 << 14,/* not in transaction */ 110 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ 111 X86_BR_CALL_STACK = 1 << 16,/* call stack */ 112 X86_BR_IND_JMP = 1 << 17,/* indirect jump */ 113 114 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */ 115 116 }; 117 118 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) 119 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) 120 121 #define X86_BR_ANY \ 122 (X86_BR_CALL |\ 123 X86_BR_RET |\ 124 X86_BR_SYSCALL |\ 125 X86_BR_SYSRET |\ 126 X86_BR_INT |\ 127 X86_BR_IRET |\ 128 X86_BR_JCC |\ 129 X86_BR_JMP |\ 130 X86_BR_IRQ |\ 131 X86_BR_ABORT |\ 132 X86_BR_IND_CALL |\ 133 X86_BR_IND_JMP |\ 134 X86_BR_ZERO_CALL) 135 136 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) 137 138 #define X86_BR_ANY_CALL \ 139 (X86_BR_CALL |\ 140 X86_BR_IND_CALL |\ 141 X86_BR_ZERO_CALL |\ 142 X86_BR_SYSCALL |\ 143 X86_BR_IRQ |\ 144 X86_BR_INT) 145 146 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); 147 148 /* 149 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI 150 * otherwise it becomes near impossible to get a reliable stack. 151 */ 152 153 static void __intel_pmu_lbr_enable(bool pmi) 154 { 155 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 156 u64 debugctl, lbr_select = 0, orig_debugctl; 157 158 /* 159 * No need to unfreeze manually, as v4 can do that as part 160 * of the GLOBAL_STATUS ack. 161 */ 162 if (pmi && x86_pmu.version >= 4) 163 return; 164 165 /* 166 * No need to reprogram LBR_SELECT in a PMI, as it 167 * did not change. 168 */ 169 if (cpuc->lbr_sel) 170 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; 171 if (!pmi && cpuc->lbr_sel) 172 wrmsrl(MSR_LBR_SELECT, lbr_select); 173 174 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 175 orig_debugctl = debugctl; 176 debugctl |= DEBUGCTLMSR_LBR; 177 /* 178 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI. 179 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions 180 * may cause superfluous increase/decrease of LBR_TOS. 181 */ 182 if (!(lbr_select & LBR_CALL_STACK)) 183 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; 184 if (orig_debugctl != debugctl) 185 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 186 } 187 188 static void __intel_pmu_lbr_disable(void) 189 { 190 u64 debugctl; 191 192 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 193 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 194 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 195 } 196 197 static void intel_pmu_lbr_reset_32(void) 198 { 199 int i; 200 201 for (i = 0; i < x86_pmu.lbr_nr; i++) 202 wrmsrl(x86_pmu.lbr_from + i, 0); 203 } 204 205 static void intel_pmu_lbr_reset_64(void) 206 { 207 int i; 208 209 for (i = 0; i < x86_pmu.lbr_nr; i++) { 210 wrmsrl(x86_pmu.lbr_from + i, 0); 211 wrmsrl(x86_pmu.lbr_to + i, 0); 212 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) 213 wrmsrl(MSR_LBR_INFO_0 + i, 0); 214 } 215 } 216 217 void intel_pmu_lbr_reset(void) 218 { 219 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 220 221 if (!x86_pmu.lbr_nr) 222 return; 223 224 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) 225 intel_pmu_lbr_reset_32(); 226 else 227 intel_pmu_lbr_reset_64(); 228 229 cpuc->last_task_ctx = NULL; 230 cpuc->last_log_id = 0; 231 } 232 233 /* 234 * TOS = most recently recorded branch 235 */ 236 static inline u64 intel_pmu_lbr_tos(void) 237 { 238 u64 tos; 239 240 rdmsrl(x86_pmu.lbr_tos, tos); 241 return tos; 242 } 243 244 enum { 245 LBR_NONE, 246 LBR_VALID, 247 }; 248 249 /* 250 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in 251 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when 252 * TSX is not supported they have no consistent behavior: 253 * 254 * - For wrmsr(), bits 61:62 are considered part of the sign extension. 255 * - For HW updates (branch captures) bits 61:62 are always OFF and are not 256 * part of the sign extension. 257 * 258 * Therefore, if: 259 * 260 * 1) LBR has TSX format 261 * 2) CPU has no TSX support enabled 262 * 263 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any 264 * value from rdmsr() must be converted to have a 61 bits sign extension, 265 * ignoring the TSX flags. 266 */ 267 static inline bool lbr_from_signext_quirk_needed(void) 268 { 269 int lbr_format = x86_pmu.intel_cap.lbr_format; 270 bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) || 271 boot_cpu_has(X86_FEATURE_RTM); 272 273 return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX); 274 } 275 276 static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key); 277 278 /* If quirk is enabled, ensure sign extension is 63 bits: */ 279 inline u64 lbr_from_signext_quirk_wr(u64 val) 280 { 281 if (static_branch_unlikely(&lbr_from_quirk_key)) { 282 /* 283 * Sign extend into bits 61:62 while preserving bit 63. 284 * 285 * Quirk is enabled when TSX is disabled. Therefore TSX bits 286 * in val are always OFF and must be changed to be sign 287 * extension bits. Since bits 59:60 are guaranteed to be 288 * part of the sign extension bits, we can just copy them 289 * to 61:62. 290 */ 291 val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2; 292 } 293 return val; 294 } 295 296 /* 297 * If quirk is needed, ensure sign extension is 61 bits: 298 */ 299 static u64 lbr_from_signext_quirk_rd(u64 val) 300 { 301 if (static_branch_unlikely(&lbr_from_quirk_key)) { 302 /* 303 * Quirk is on when TSX is not enabled. Therefore TSX 304 * flags must be read as OFF. 305 */ 306 val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT); 307 } 308 return val; 309 } 310 311 static inline void wrlbr_from(unsigned int idx, u64 val) 312 { 313 val = lbr_from_signext_quirk_wr(val); 314 wrmsrl(x86_pmu.lbr_from + idx, val); 315 } 316 317 static inline void wrlbr_to(unsigned int idx, u64 val) 318 { 319 wrmsrl(x86_pmu.lbr_to + idx, val); 320 } 321 322 static inline u64 rdlbr_from(unsigned int idx) 323 { 324 u64 val; 325 326 rdmsrl(x86_pmu.lbr_from + idx, val); 327 328 return lbr_from_signext_quirk_rd(val); 329 } 330 331 static inline u64 rdlbr_to(unsigned int idx) 332 { 333 u64 val; 334 335 rdmsrl(x86_pmu.lbr_to + idx, val); 336 337 return val; 338 } 339 340 static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) 341 { 342 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 343 int i; 344 unsigned lbr_idx, mask; 345 u64 tos; 346 347 if (task_ctx->lbr_callstack_users == 0 || 348 task_ctx->lbr_stack_state == LBR_NONE) { 349 intel_pmu_lbr_reset(); 350 return; 351 } 352 353 tos = task_ctx->tos; 354 /* 355 * Does not restore the LBR registers, if 356 * - No one else touched them, and 357 * - Did not enter C6 358 */ 359 if ((task_ctx == cpuc->last_task_ctx) && 360 (task_ctx->log_id == cpuc->last_log_id) && 361 rdlbr_from(tos)) { 362 task_ctx->lbr_stack_state = LBR_NONE; 363 return; 364 } 365 366 mask = x86_pmu.lbr_nr - 1; 367 for (i = 0; i < task_ctx->valid_lbrs; i++) { 368 lbr_idx = (tos - i) & mask; 369 wrlbr_from(lbr_idx, task_ctx->lbr_from[i]); 370 wrlbr_to (lbr_idx, task_ctx->lbr_to[i]); 371 372 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) 373 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); 374 } 375 376 for (; i < x86_pmu.lbr_nr; i++) { 377 lbr_idx = (tos - i) & mask; 378 wrlbr_from(lbr_idx, 0); 379 wrlbr_to(lbr_idx, 0); 380 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) 381 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, 0); 382 } 383 384 wrmsrl(x86_pmu.lbr_tos, tos); 385 task_ctx->lbr_stack_state = LBR_NONE; 386 } 387 388 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx) 389 { 390 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 391 unsigned lbr_idx, mask; 392 u64 tos, from; 393 int i; 394 395 if (task_ctx->lbr_callstack_users == 0) { 396 task_ctx->lbr_stack_state = LBR_NONE; 397 return; 398 } 399 400 mask = x86_pmu.lbr_nr - 1; 401 tos = intel_pmu_lbr_tos(); 402 for (i = 0; i < x86_pmu.lbr_nr; i++) { 403 lbr_idx = (tos - i) & mask; 404 from = rdlbr_from(lbr_idx); 405 if (!from) 406 break; 407 task_ctx->lbr_from[i] = from; 408 task_ctx->lbr_to[i] = rdlbr_to(lbr_idx); 409 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) 410 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); 411 } 412 task_ctx->valid_lbrs = i; 413 task_ctx->tos = tos; 414 task_ctx->lbr_stack_state = LBR_VALID; 415 416 cpuc->last_task_ctx = task_ctx; 417 cpuc->last_log_id = ++task_ctx->log_id; 418 } 419 420 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev, 421 struct perf_event_context *next) 422 { 423 struct x86_perf_task_context *prev_ctx_data, *next_ctx_data; 424 425 swap(prev->task_ctx_data, next->task_ctx_data); 426 427 /* 428 * Architecture specific synchronization makes sense in 429 * case both prev->task_ctx_data and next->task_ctx_data 430 * pointers are allocated. 431 */ 432 433 prev_ctx_data = next->task_ctx_data; 434 next_ctx_data = prev->task_ctx_data; 435 436 if (!prev_ctx_data || !next_ctx_data) 437 return; 438 439 swap(prev_ctx_data->lbr_callstack_users, 440 next_ctx_data->lbr_callstack_users); 441 } 442 443 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in) 444 { 445 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 446 struct x86_perf_task_context *task_ctx; 447 448 if (!cpuc->lbr_users) 449 return; 450 451 /* 452 * If LBR callstack feature is enabled and the stack was saved when 453 * the task was scheduled out, restore the stack. Otherwise flush 454 * the LBR stack. 455 */ 456 task_ctx = ctx ? ctx->task_ctx_data : NULL; 457 if (task_ctx) { 458 if (sched_in) 459 __intel_pmu_lbr_restore(task_ctx); 460 else 461 __intel_pmu_lbr_save(task_ctx); 462 return; 463 } 464 465 /* 466 * Since a context switch can flip the address space and LBR entries 467 * are not tagged with an identifier, we need to wipe the LBR, even for 468 * per-cpu events. You simply cannot resolve the branches from the old 469 * address space. 470 */ 471 if (sched_in) 472 intel_pmu_lbr_reset(); 473 } 474 475 static inline bool branch_user_callstack(unsigned br_sel) 476 { 477 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK); 478 } 479 480 void intel_pmu_lbr_add(struct perf_event *event) 481 { 482 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 483 struct x86_perf_task_context *task_ctx; 484 485 if (!x86_pmu.lbr_nr) 486 return; 487 488 cpuc->br_sel = event->hw.branch_reg.reg; 489 490 if (branch_user_callstack(cpuc->br_sel) && event->ctx->task_ctx_data) { 491 task_ctx = event->ctx->task_ctx_data; 492 task_ctx->lbr_callstack_users++; 493 } 494 495 /* 496 * Request pmu::sched_task() callback, which will fire inside the 497 * regular perf event scheduling, so that call will: 498 * 499 * - restore or wipe; when LBR-callstack, 500 * - wipe; otherwise, 501 * 502 * when this is from __perf_event_task_sched_in(). 503 * 504 * However, if this is from perf_install_in_context(), no such callback 505 * will follow and we'll need to reset the LBR here if this is the 506 * first LBR event. 507 * 508 * The problem is, we cannot tell these cases apart... but we can 509 * exclude the biggest chunk of cases by looking at 510 * event->total_time_running. An event that has accrued runtime cannot 511 * be 'new'. Conversely, a new event can get installed through the 512 * context switch path for the first time. 513 */ 514 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) 515 cpuc->lbr_pebs_users++; 516 perf_sched_cb_inc(event->ctx->pmu); 517 if (!cpuc->lbr_users++ && !event->total_time_running) 518 intel_pmu_lbr_reset(); 519 } 520 521 void intel_pmu_lbr_del(struct perf_event *event) 522 { 523 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 524 struct x86_perf_task_context *task_ctx; 525 526 if (!x86_pmu.lbr_nr) 527 return; 528 529 if (branch_user_callstack(cpuc->br_sel) && 530 event->ctx->task_ctx_data) { 531 task_ctx = event->ctx->task_ctx_data; 532 task_ctx->lbr_callstack_users--; 533 } 534 535 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) 536 cpuc->lbr_pebs_users--; 537 cpuc->lbr_users--; 538 WARN_ON_ONCE(cpuc->lbr_users < 0); 539 WARN_ON_ONCE(cpuc->lbr_pebs_users < 0); 540 perf_sched_cb_dec(event->ctx->pmu); 541 } 542 543 void intel_pmu_lbr_enable_all(bool pmi) 544 { 545 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 546 547 if (cpuc->lbr_users) 548 __intel_pmu_lbr_enable(pmi); 549 } 550 551 void intel_pmu_lbr_disable_all(void) 552 { 553 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 554 555 if (cpuc->lbr_users) 556 __intel_pmu_lbr_disable(); 557 } 558 559 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) 560 { 561 unsigned long mask = x86_pmu.lbr_nr - 1; 562 u64 tos = intel_pmu_lbr_tos(); 563 int i; 564 565 for (i = 0; i < x86_pmu.lbr_nr; i++) { 566 unsigned long lbr_idx = (tos - i) & mask; 567 union { 568 struct { 569 u32 from; 570 u32 to; 571 }; 572 u64 lbr; 573 } msr_lastbranch; 574 575 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); 576 577 cpuc->lbr_entries[i].from = msr_lastbranch.from; 578 cpuc->lbr_entries[i].to = msr_lastbranch.to; 579 cpuc->lbr_entries[i].mispred = 0; 580 cpuc->lbr_entries[i].predicted = 0; 581 cpuc->lbr_entries[i].in_tx = 0; 582 cpuc->lbr_entries[i].abort = 0; 583 cpuc->lbr_entries[i].cycles = 0; 584 cpuc->lbr_entries[i].type = 0; 585 cpuc->lbr_entries[i].reserved = 0; 586 } 587 cpuc->lbr_stack.nr = i; 588 cpuc->lbr_stack.hw_idx = tos; 589 } 590 591 /* 592 * Due to lack of segmentation in Linux the effective address (offset) 593 * is the same as the linear address, allowing us to merge the LIP and EIP 594 * LBR formats. 595 */ 596 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) 597 { 598 bool need_info = false, call_stack = false; 599 unsigned long mask = x86_pmu.lbr_nr - 1; 600 int lbr_format = x86_pmu.intel_cap.lbr_format; 601 u64 tos = intel_pmu_lbr_tos(); 602 int i; 603 int out = 0; 604 int num = x86_pmu.lbr_nr; 605 606 if (cpuc->lbr_sel) { 607 need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO); 608 if (cpuc->lbr_sel->config & LBR_CALL_STACK) 609 call_stack = true; 610 } 611 612 for (i = 0; i < num; i++) { 613 unsigned long lbr_idx = (tos - i) & mask; 614 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; 615 int skip = 0; 616 u16 cycles = 0; 617 int lbr_flags = lbr_desc[lbr_format]; 618 619 from = rdlbr_from(lbr_idx); 620 to = rdlbr_to(lbr_idx); 621 622 /* 623 * Read LBR call stack entries 624 * until invalid entry (0s) is detected. 625 */ 626 if (call_stack && !from) 627 break; 628 629 if (lbr_format == LBR_FORMAT_INFO && need_info) { 630 u64 info; 631 632 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info); 633 mis = !!(info & LBR_INFO_MISPRED); 634 pred = !mis; 635 in_tx = !!(info & LBR_INFO_IN_TX); 636 abort = !!(info & LBR_INFO_ABORT); 637 cycles = (info & LBR_INFO_CYCLES); 638 } 639 640 if (lbr_format == LBR_FORMAT_TIME) { 641 mis = !!(from & LBR_FROM_FLAG_MISPRED); 642 pred = !mis; 643 skip = 1; 644 cycles = ((to >> 48) & LBR_INFO_CYCLES); 645 646 to = (u64)((((s64)to) << 16) >> 16); 647 } 648 649 if (lbr_flags & LBR_EIP_FLAGS) { 650 mis = !!(from & LBR_FROM_FLAG_MISPRED); 651 pred = !mis; 652 skip = 1; 653 } 654 if (lbr_flags & LBR_TSX) { 655 in_tx = !!(from & LBR_FROM_FLAG_IN_TX); 656 abort = !!(from & LBR_FROM_FLAG_ABORT); 657 skip = 3; 658 } 659 from = (u64)((((s64)from) << skip) >> skip); 660 661 /* 662 * Some CPUs report duplicated abort records, 663 * with the second entry not having an abort bit set. 664 * Skip them here. This loop runs backwards, 665 * so we need to undo the previous record. 666 * If the abort just happened outside the window 667 * the extra entry cannot be removed. 668 */ 669 if (abort && x86_pmu.lbr_double_abort && out > 0) 670 out--; 671 672 cpuc->lbr_entries[out].from = from; 673 cpuc->lbr_entries[out].to = to; 674 cpuc->lbr_entries[out].mispred = mis; 675 cpuc->lbr_entries[out].predicted = pred; 676 cpuc->lbr_entries[out].in_tx = in_tx; 677 cpuc->lbr_entries[out].abort = abort; 678 cpuc->lbr_entries[out].cycles = cycles; 679 cpuc->lbr_entries[out].type = 0; 680 cpuc->lbr_entries[out].reserved = 0; 681 out++; 682 } 683 cpuc->lbr_stack.nr = out; 684 cpuc->lbr_stack.hw_idx = tos; 685 } 686 687 void intel_pmu_lbr_read(void) 688 { 689 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 690 691 /* 692 * Don't read when all LBRs users are using adaptive PEBS. 693 * 694 * This could be smarter and actually check the event, 695 * but this simple approach seems to work for now. 696 */ 697 if (!cpuc->lbr_users || cpuc->lbr_users == cpuc->lbr_pebs_users) 698 return; 699 700 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) 701 intel_pmu_lbr_read_32(cpuc); 702 else 703 intel_pmu_lbr_read_64(cpuc); 704 705 intel_pmu_lbr_filter(cpuc); 706 } 707 708 /* 709 * SW filter is used: 710 * - in case there is no HW filter 711 * - in case the HW filter has errata or limitations 712 */ 713 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event) 714 { 715 u64 br_type = event->attr.branch_sample_type; 716 int mask = 0; 717 718 if (br_type & PERF_SAMPLE_BRANCH_USER) 719 mask |= X86_BR_USER; 720 721 if (br_type & PERF_SAMPLE_BRANCH_KERNEL) 722 mask |= X86_BR_KERNEL; 723 724 /* we ignore BRANCH_HV here */ 725 726 if (br_type & PERF_SAMPLE_BRANCH_ANY) 727 mask |= X86_BR_ANY; 728 729 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL) 730 mask |= X86_BR_ANY_CALL; 731 732 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 733 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET; 734 735 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL) 736 mask |= X86_BR_IND_CALL; 737 738 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX) 739 mask |= X86_BR_ABORT; 740 741 if (br_type & PERF_SAMPLE_BRANCH_IN_TX) 742 mask |= X86_BR_IN_TX; 743 744 if (br_type & PERF_SAMPLE_BRANCH_NO_TX) 745 mask |= X86_BR_NO_TX; 746 747 if (br_type & PERF_SAMPLE_BRANCH_COND) 748 mask |= X86_BR_JCC; 749 750 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) { 751 if (!x86_pmu_has_lbr_callstack()) 752 return -EOPNOTSUPP; 753 if (mask & ~(X86_BR_USER | X86_BR_KERNEL)) 754 return -EINVAL; 755 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET | 756 X86_BR_CALL_STACK; 757 } 758 759 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP) 760 mask |= X86_BR_IND_JMP; 761 762 if (br_type & PERF_SAMPLE_BRANCH_CALL) 763 mask |= X86_BR_CALL | X86_BR_ZERO_CALL; 764 765 if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE) 766 mask |= X86_BR_TYPE_SAVE; 767 768 /* 769 * stash actual user request into reg, it may 770 * be used by fixup code for some CPU 771 */ 772 event->hw.branch_reg.reg = mask; 773 return 0; 774 } 775 776 /* 777 * setup the HW LBR filter 778 * Used only when available, may not be enough to disambiguate 779 * all branches, may need the help of the SW filter 780 */ 781 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) 782 { 783 struct hw_perf_event_extra *reg; 784 u64 br_type = event->attr.branch_sample_type; 785 u64 mask = 0, v; 786 int i; 787 788 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) { 789 if (!(br_type & (1ULL << i))) 790 continue; 791 792 v = x86_pmu.lbr_sel_map[i]; 793 if (v == LBR_NOT_SUPP) 794 return -EOPNOTSUPP; 795 796 if (v != LBR_IGN) 797 mask |= v; 798 } 799 800 reg = &event->hw.branch_reg; 801 reg->idx = EXTRA_REG_LBR; 802 803 /* 804 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate 805 * in suppress mode. So LBR_SELECT should be set to 806 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) 807 * But the 10th bit LBR_CALL_STACK does not operate 808 * in suppress mode. 809 */ 810 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); 811 812 if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) && 813 (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) && 814 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)) 815 reg->config |= LBR_NO_INFO; 816 817 return 0; 818 } 819 820 int intel_pmu_setup_lbr_filter(struct perf_event *event) 821 { 822 int ret = 0; 823 824 /* 825 * no LBR on this PMU 826 */ 827 if (!x86_pmu.lbr_nr) 828 return -EOPNOTSUPP; 829 830 /* 831 * setup SW LBR filter 832 */ 833 ret = intel_pmu_setup_sw_lbr_filter(event); 834 if (ret) 835 return ret; 836 837 /* 838 * setup HW LBR filter, if any 839 */ 840 if (x86_pmu.lbr_sel_map) 841 ret = intel_pmu_setup_hw_lbr_filter(event); 842 843 return ret; 844 } 845 846 /* 847 * return the type of control flow change at address "from" 848 * instruction is not necessarily a branch (in case of interrupt). 849 * 850 * The branch type returned also includes the priv level of the 851 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL). 852 * 853 * If a branch type is unknown OR the instruction cannot be 854 * decoded (e.g., text page not present), then X86_BR_NONE is 855 * returned. 856 */ 857 static int branch_type(unsigned long from, unsigned long to, int abort) 858 { 859 struct insn insn; 860 void *addr; 861 int bytes_read, bytes_left; 862 int ret = X86_BR_NONE; 863 int ext, to_plm, from_plm; 864 u8 buf[MAX_INSN_SIZE]; 865 int is64 = 0; 866 867 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER; 868 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER; 869 870 /* 871 * maybe zero if lbr did not fill up after a reset by the time 872 * we get a PMU interrupt 873 */ 874 if (from == 0 || to == 0) 875 return X86_BR_NONE; 876 877 if (abort) 878 return X86_BR_ABORT | to_plm; 879 880 if (from_plm == X86_BR_USER) { 881 /* 882 * can happen if measuring at the user level only 883 * and we interrupt in a kernel thread, e.g., idle. 884 */ 885 if (!current->mm) 886 return X86_BR_NONE; 887 888 /* may fail if text not present */ 889 bytes_left = copy_from_user_nmi(buf, (void __user *)from, 890 MAX_INSN_SIZE); 891 bytes_read = MAX_INSN_SIZE - bytes_left; 892 if (!bytes_read) 893 return X86_BR_NONE; 894 895 addr = buf; 896 } else { 897 /* 898 * The LBR logs any address in the IP, even if the IP just 899 * faulted. This means userspace can control the from address. 900 * Ensure we don't blindy read any address by validating it is 901 * a known text address. 902 */ 903 if (kernel_text_address(from)) { 904 addr = (void *)from; 905 /* 906 * Assume we can get the maximum possible size 907 * when grabbing kernel data. This is not 908 * _strictly_ true since we could possibly be 909 * executing up next to a memory hole, but 910 * it is very unlikely to be a problem. 911 */ 912 bytes_read = MAX_INSN_SIZE; 913 } else { 914 return X86_BR_NONE; 915 } 916 } 917 918 /* 919 * decoder needs to know the ABI especially 920 * on 64-bit systems running 32-bit apps 921 */ 922 #ifdef CONFIG_X86_64 923 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32); 924 #endif 925 insn_init(&insn, addr, bytes_read, is64); 926 insn_get_opcode(&insn); 927 if (!insn.opcode.got) 928 return X86_BR_ABORT; 929 930 switch (insn.opcode.bytes[0]) { 931 case 0xf: 932 switch (insn.opcode.bytes[1]) { 933 case 0x05: /* syscall */ 934 case 0x34: /* sysenter */ 935 ret = X86_BR_SYSCALL; 936 break; 937 case 0x07: /* sysret */ 938 case 0x35: /* sysexit */ 939 ret = X86_BR_SYSRET; 940 break; 941 case 0x80 ... 0x8f: /* conditional */ 942 ret = X86_BR_JCC; 943 break; 944 default: 945 ret = X86_BR_NONE; 946 } 947 break; 948 case 0x70 ... 0x7f: /* conditional */ 949 ret = X86_BR_JCC; 950 break; 951 case 0xc2: /* near ret */ 952 case 0xc3: /* near ret */ 953 case 0xca: /* far ret */ 954 case 0xcb: /* far ret */ 955 ret = X86_BR_RET; 956 break; 957 case 0xcf: /* iret */ 958 ret = X86_BR_IRET; 959 break; 960 case 0xcc ... 0xce: /* int */ 961 ret = X86_BR_INT; 962 break; 963 case 0xe8: /* call near rel */ 964 insn_get_immediate(&insn); 965 if (insn.immediate1.value == 0) { 966 /* zero length call */ 967 ret = X86_BR_ZERO_CALL; 968 break; 969 } 970 /* fall through */ 971 case 0x9a: /* call far absolute */ 972 ret = X86_BR_CALL; 973 break; 974 case 0xe0 ... 0xe3: /* loop jmp */ 975 ret = X86_BR_JCC; 976 break; 977 case 0xe9 ... 0xeb: /* jmp */ 978 ret = X86_BR_JMP; 979 break; 980 case 0xff: /* call near absolute, call far absolute ind */ 981 insn_get_modrm(&insn); 982 ext = (insn.modrm.bytes[0] >> 3) & 0x7; 983 switch (ext) { 984 case 2: /* near ind call */ 985 case 3: /* far ind call */ 986 ret = X86_BR_IND_CALL; 987 break; 988 case 4: 989 case 5: 990 ret = X86_BR_IND_JMP; 991 break; 992 } 993 break; 994 default: 995 ret = X86_BR_NONE; 996 } 997 /* 998 * interrupts, traps, faults (and thus ring transition) may 999 * occur on any instructions. Thus, to classify them correctly, 1000 * we need to first look at the from and to priv levels. If they 1001 * are different and to is in the kernel, then it indicates 1002 * a ring transition. If the from instruction is not a ring 1003 * transition instr (syscall, systenter, int), then it means 1004 * it was a irq, trap or fault. 1005 * 1006 * we have no way of detecting kernel to kernel faults. 1007 */ 1008 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL 1009 && ret != X86_BR_SYSCALL && ret != X86_BR_INT) 1010 ret = X86_BR_IRQ; 1011 1012 /* 1013 * branch priv level determined by target as 1014 * is done by HW when LBR_SELECT is implemented 1015 */ 1016 if (ret != X86_BR_NONE) 1017 ret |= to_plm; 1018 1019 return ret; 1020 } 1021 1022 #define X86_BR_TYPE_MAP_MAX 16 1023 1024 static int branch_map[X86_BR_TYPE_MAP_MAX] = { 1025 PERF_BR_CALL, /* X86_BR_CALL */ 1026 PERF_BR_RET, /* X86_BR_RET */ 1027 PERF_BR_SYSCALL, /* X86_BR_SYSCALL */ 1028 PERF_BR_SYSRET, /* X86_BR_SYSRET */ 1029 PERF_BR_UNKNOWN, /* X86_BR_INT */ 1030 PERF_BR_UNKNOWN, /* X86_BR_IRET */ 1031 PERF_BR_COND, /* X86_BR_JCC */ 1032 PERF_BR_UNCOND, /* X86_BR_JMP */ 1033 PERF_BR_UNKNOWN, /* X86_BR_IRQ */ 1034 PERF_BR_IND_CALL, /* X86_BR_IND_CALL */ 1035 PERF_BR_UNKNOWN, /* X86_BR_ABORT */ 1036 PERF_BR_UNKNOWN, /* X86_BR_IN_TX */ 1037 PERF_BR_UNKNOWN, /* X86_BR_NO_TX */ 1038 PERF_BR_CALL, /* X86_BR_ZERO_CALL */ 1039 PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */ 1040 PERF_BR_IND, /* X86_BR_IND_JMP */ 1041 }; 1042 1043 static int 1044 common_branch_type(int type) 1045 { 1046 int i; 1047 1048 type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */ 1049 1050 if (type) { 1051 i = __ffs(type); 1052 if (i < X86_BR_TYPE_MAP_MAX) 1053 return branch_map[i]; 1054 } 1055 1056 return PERF_BR_UNKNOWN; 1057 } 1058 1059 /* 1060 * implement actual branch filter based on user demand. 1061 * Hardware may not exactly satisfy that request, thus 1062 * we need to inspect opcodes. Mismatched branches are 1063 * discarded. Therefore, the number of branches returned 1064 * in PERF_SAMPLE_BRANCH_STACK sample may vary. 1065 */ 1066 static void 1067 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) 1068 { 1069 u64 from, to; 1070 int br_sel = cpuc->br_sel; 1071 int i, j, type; 1072 bool compress = false; 1073 1074 /* if sampling all branches, then nothing to filter */ 1075 if (((br_sel & X86_BR_ALL) == X86_BR_ALL) && 1076 ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE)) 1077 return; 1078 1079 for (i = 0; i < cpuc->lbr_stack.nr; i++) { 1080 1081 from = cpuc->lbr_entries[i].from; 1082 to = cpuc->lbr_entries[i].to; 1083 1084 type = branch_type(from, to, cpuc->lbr_entries[i].abort); 1085 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) { 1086 if (cpuc->lbr_entries[i].in_tx) 1087 type |= X86_BR_IN_TX; 1088 else 1089 type |= X86_BR_NO_TX; 1090 } 1091 1092 /* if type does not correspond, then discard */ 1093 if (type == X86_BR_NONE || (br_sel & type) != type) { 1094 cpuc->lbr_entries[i].from = 0; 1095 compress = true; 1096 } 1097 1098 if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE) 1099 cpuc->lbr_entries[i].type = common_branch_type(type); 1100 } 1101 1102 if (!compress) 1103 return; 1104 1105 /* remove all entries with from=0 */ 1106 for (i = 0; i < cpuc->lbr_stack.nr; ) { 1107 if (!cpuc->lbr_entries[i].from) { 1108 j = i; 1109 while (++j < cpuc->lbr_stack.nr) 1110 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; 1111 cpuc->lbr_stack.nr--; 1112 if (!cpuc->lbr_entries[i].from) 1113 continue; 1114 } 1115 i++; 1116 } 1117 } 1118 1119 void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr) 1120 { 1121 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1122 int i; 1123 1124 cpuc->lbr_stack.nr = x86_pmu.lbr_nr; 1125 1126 /* Cannot get TOS for large PEBS */ 1127 if (cpuc->n_pebs == cpuc->n_large_pebs) 1128 cpuc->lbr_stack.hw_idx = -1ULL; 1129 else 1130 cpuc->lbr_stack.hw_idx = intel_pmu_lbr_tos(); 1131 1132 for (i = 0; i < x86_pmu.lbr_nr; i++) { 1133 u64 info = lbr->lbr[i].info; 1134 struct perf_branch_entry *e = &cpuc->lbr_entries[i]; 1135 1136 e->from = lbr->lbr[i].from; 1137 e->to = lbr->lbr[i].to; 1138 e->mispred = !!(info & LBR_INFO_MISPRED); 1139 e->predicted = !(info & LBR_INFO_MISPRED); 1140 e->in_tx = !!(info & LBR_INFO_IN_TX); 1141 e->abort = !!(info & LBR_INFO_ABORT); 1142 e->cycles = info & LBR_INFO_CYCLES; 1143 e->reserved = 0; 1144 } 1145 intel_pmu_lbr_filter(cpuc); 1146 } 1147 1148 /* 1149 * Map interface branch filters onto LBR filters 1150 */ 1151 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1152 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, 1153 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, 1154 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, 1155 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1156 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP 1157 | LBR_IND_JMP | LBR_FAR, 1158 /* 1159 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches 1160 */ 1161 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = 1162 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR, 1163 /* 1164 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL 1165 */ 1166 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP, 1167 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, 1168 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, 1169 }; 1170 1171 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1172 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, 1173 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, 1174 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, 1175 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1176 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, 1177 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL 1178 | LBR_FAR, 1179 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, 1180 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, 1181 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, 1182 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL, 1183 }; 1184 1185 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { 1186 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, 1187 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, 1188 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, 1189 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, 1190 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, 1191 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL 1192 | LBR_FAR, 1193 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, 1194 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, 1195 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL 1196 | LBR_RETURN | LBR_CALL_STACK, 1197 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, 1198 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL, 1199 }; 1200 1201 /* core */ 1202 void __init intel_pmu_lbr_init_core(void) 1203 { 1204 x86_pmu.lbr_nr = 4; 1205 x86_pmu.lbr_tos = MSR_LBR_TOS; 1206 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 1207 x86_pmu.lbr_to = MSR_LBR_CORE_TO; 1208 1209 /* 1210 * SW branch filter usage: 1211 * - compensate for lack of HW filter 1212 */ 1213 } 1214 1215 /* nehalem/westmere */ 1216 void __init intel_pmu_lbr_init_nhm(void) 1217 { 1218 x86_pmu.lbr_nr = 16; 1219 x86_pmu.lbr_tos = MSR_LBR_TOS; 1220 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1221 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1222 1223 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1224 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; 1225 1226 /* 1227 * SW branch filter usage: 1228 * - workaround LBR_SEL errata (see above) 1229 * - support syscall, sysret capture. 1230 * That requires LBR_FAR but that means far 1231 * jmp need to be filtered out 1232 */ 1233 } 1234 1235 /* sandy bridge */ 1236 void __init intel_pmu_lbr_init_snb(void) 1237 { 1238 x86_pmu.lbr_nr = 16; 1239 x86_pmu.lbr_tos = MSR_LBR_TOS; 1240 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1241 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1242 1243 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1244 x86_pmu.lbr_sel_map = snb_lbr_sel_map; 1245 1246 /* 1247 * SW branch filter usage: 1248 * - support syscall, sysret capture. 1249 * That requires LBR_FAR but that means far 1250 * jmp need to be filtered out 1251 */ 1252 } 1253 1254 /* haswell */ 1255 void intel_pmu_lbr_init_hsw(void) 1256 { 1257 x86_pmu.lbr_nr = 16; 1258 x86_pmu.lbr_tos = MSR_LBR_TOS; 1259 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1260 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1261 1262 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1263 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; 1264 1265 if (lbr_from_signext_quirk_needed()) 1266 static_branch_enable(&lbr_from_quirk_key); 1267 } 1268 1269 /* skylake */ 1270 __init void intel_pmu_lbr_init_skl(void) 1271 { 1272 x86_pmu.lbr_nr = 32; 1273 x86_pmu.lbr_tos = MSR_LBR_TOS; 1274 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1275 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1276 1277 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1278 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; 1279 1280 /* 1281 * SW branch filter usage: 1282 * - support syscall, sysret capture. 1283 * That requires LBR_FAR but that means far 1284 * jmp need to be filtered out 1285 */ 1286 } 1287 1288 /* atom */ 1289 void __init intel_pmu_lbr_init_atom(void) 1290 { 1291 /* 1292 * only models starting at stepping 10 seems 1293 * to have an operational LBR which can freeze 1294 * on PMU interrupt 1295 */ 1296 if (boot_cpu_data.x86_model == 28 1297 && boot_cpu_data.x86_stepping < 10) { 1298 pr_cont("LBR disabled due to erratum"); 1299 return; 1300 } 1301 1302 x86_pmu.lbr_nr = 8; 1303 x86_pmu.lbr_tos = MSR_LBR_TOS; 1304 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 1305 x86_pmu.lbr_to = MSR_LBR_CORE_TO; 1306 1307 /* 1308 * SW branch filter usage: 1309 * - compensate for lack of HW filter 1310 */ 1311 } 1312 1313 /* slm */ 1314 void __init intel_pmu_lbr_init_slm(void) 1315 { 1316 x86_pmu.lbr_nr = 8; 1317 x86_pmu.lbr_tos = MSR_LBR_TOS; 1318 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 1319 x86_pmu.lbr_to = MSR_LBR_CORE_TO; 1320 1321 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1322 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; 1323 1324 /* 1325 * SW branch filter usage: 1326 * - compensate for lack of HW filter 1327 */ 1328 pr_cont("8-deep LBR, "); 1329 } 1330 1331 /* Knights Landing */ 1332 void intel_pmu_lbr_init_knl(void) 1333 { 1334 x86_pmu.lbr_nr = 8; 1335 x86_pmu.lbr_tos = MSR_LBR_TOS; 1336 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; 1337 x86_pmu.lbr_to = MSR_LBR_NHM_TO; 1338 1339 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; 1340 x86_pmu.lbr_sel_map = snb_lbr_sel_map; 1341 1342 /* Knights Landing does have MISPREDICT bit */ 1343 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP) 1344 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS; 1345 } 1346