1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/bitops.h> 3 #include <linux/types.h> 4 #include <linux/slab.h> 5 6 #include <asm/cpu_entry_area.h> 7 #include <asm/perf_event.h> 8 #include <asm/tlbflush.h> 9 #include <asm/insn.h> 10 11 #include "../perf_event.h" 12 13 /* Waste a full page so it can be mapped into the cpu_entry_area */ 14 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 15 16 /* The size of a BTS record in bytes: */ 17 #define BTS_RECORD_SIZE 24 18 19 #define PEBS_FIXUP_SIZE PAGE_SIZE 20 21 /* 22 * pebs_record_32 for p4 and core not supported 23 24 struct pebs_record_32 { 25 u32 flags, ip; 26 u32 ax, bc, cx, dx; 27 u32 si, di, bp, sp; 28 }; 29 30 */ 31 32 union intel_x86_pebs_dse { 33 u64 val; 34 struct { 35 unsigned int ld_dse:4; 36 unsigned int ld_stlb_miss:1; 37 unsigned int ld_locked:1; 38 unsigned int ld_reserved:26; 39 }; 40 struct { 41 unsigned int st_l1d_hit:1; 42 unsigned int st_reserved1:3; 43 unsigned int st_stlb_miss:1; 44 unsigned int st_locked:1; 45 unsigned int st_reserved2:26; 46 }; 47 }; 48 49 50 /* 51 * Map PEBS Load Latency Data Source encodings to generic 52 * memory data source information 53 */ 54 #define P(a, b) PERF_MEM_S(a, b) 55 #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) 56 #define LEVEL(x) P(LVLNUM, x) 57 #define REM P(REMOTE, REMOTE) 58 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) 59 60 /* Version for Sandy Bridge and later */ 61 static u64 pebs_data_source[] = { 62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 63 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 64 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ 65 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ 66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ 67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ 68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ 69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ 70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ 71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ 72 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ 73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ 74 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */ 75 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ 76 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */ 77 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */ 78 }; 79 80 /* Patch up minor differences in the bits */ 81 void __init intel_pmu_pebs_data_source_nhm(void) 82 { 83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 85 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 86 } 87 88 void __init intel_pmu_pebs_data_source_skl(bool pmem) 89 { 90 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); 91 92 pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); 93 pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); 94 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); 95 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); 96 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); 97 } 98 99 static u64 precise_store_data(u64 status) 100 { 101 union intel_x86_pebs_dse dse; 102 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); 103 104 dse.val = status; 105 106 /* 107 * bit 4: TLB access 108 * 1 = stored missed 2nd level TLB 109 * 110 * so it either hit the walker or the OS 111 * otherwise hit 2nd level TLB 112 */ 113 if (dse.st_stlb_miss) 114 val |= P(TLB, MISS); 115 else 116 val |= P(TLB, HIT); 117 118 /* 119 * bit 0: hit L1 data cache 120 * if not set, then all we know is that 121 * it missed L1D 122 */ 123 if (dse.st_l1d_hit) 124 val |= P(LVL, HIT); 125 else 126 val |= P(LVL, MISS); 127 128 /* 129 * bit 5: Locked prefix 130 */ 131 if (dse.st_locked) 132 val |= P(LOCK, LOCKED); 133 134 return val; 135 } 136 137 static u64 precise_datala_hsw(struct perf_event *event, u64 status) 138 { 139 union perf_mem_data_src dse; 140 141 dse.val = PERF_MEM_NA; 142 143 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 144 dse.mem_op = PERF_MEM_OP_STORE; 145 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) 146 dse.mem_op = PERF_MEM_OP_LOAD; 147 148 /* 149 * L1 info only valid for following events: 150 * 151 * MEM_UOPS_RETIRED.STLB_MISS_STORES 152 * MEM_UOPS_RETIRED.LOCK_STORES 153 * MEM_UOPS_RETIRED.SPLIT_STORES 154 * MEM_UOPS_RETIRED.ALL_STORES 155 */ 156 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { 157 if (status & 1) 158 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; 159 else 160 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; 161 } 162 return dse.val; 163 } 164 165 static u64 load_latency_data(u64 status) 166 { 167 union intel_x86_pebs_dse dse; 168 u64 val; 169 170 dse.val = status; 171 172 /* 173 * use the mapping table for bit 0-3 174 */ 175 val = pebs_data_source[dse.ld_dse]; 176 177 /* 178 * Nehalem models do not support TLB, Lock infos 179 */ 180 if (x86_pmu.pebs_no_tlb) { 181 val |= P(TLB, NA) | P(LOCK, NA); 182 return val; 183 } 184 /* 185 * bit 4: TLB access 186 * 0 = did not miss 2nd level TLB 187 * 1 = missed 2nd level TLB 188 */ 189 if (dse.ld_stlb_miss) 190 val |= P(TLB, MISS) | P(TLB, L2); 191 else 192 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 193 194 /* 195 * bit 5: locked prefix 196 */ 197 if (dse.ld_locked) 198 val |= P(LOCK, LOCKED); 199 200 return val; 201 } 202 203 struct pebs_record_core { 204 u64 flags, ip; 205 u64 ax, bx, cx, dx; 206 u64 si, di, bp, sp; 207 u64 r8, r9, r10, r11; 208 u64 r12, r13, r14, r15; 209 }; 210 211 struct pebs_record_nhm { 212 u64 flags, ip; 213 u64 ax, bx, cx, dx; 214 u64 si, di, bp, sp; 215 u64 r8, r9, r10, r11; 216 u64 r12, r13, r14, r15; 217 u64 status, dla, dse, lat; 218 }; 219 220 /* 221 * Same as pebs_record_nhm, with two additional fields. 222 */ 223 struct pebs_record_hsw { 224 u64 flags, ip; 225 u64 ax, bx, cx, dx; 226 u64 si, di, bp, sp; 227 u64 r8, r9, r10, r11; 228 u64 r12, r13, r14, r15; 229 u64 status, dla, dse, lat; 230 u64 real_ip, tsx_tuning; 231 }; 232 233 union hsw_tsx_tuning { 234 struct { 235 u32 cycles_last_block : 32, 236 hle_abort : 1, 237 rtm_abort : 1, 238 instruction_abort : 1, 239 non_instruction_abort : 1, 240 retry : 1, 241 data_conflict : 1, 242 capacity_writes : 1, 243 capacity_reads : 1; 244 }; 245 u64 value; 246 }; 247 248 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL 249 250 /* Same as HSW, plus TSC */ 251 252 struct pebs_record_skl { 253 u64 flags, ip; 254 u64 ax, bx, cx, dx; 255 u64 si, di, bp, sp; 256 u64 r8, r9, r10, r11; 257 u64 r12, r13, r14, r15; 258 u64 status, dla, dse, lat; 259 u64 real_ip, tsx_tuning; 260 u64 tsc; 261 }; 262 263 void init_debug_store_on_cpu(int cpu) 264 { 265 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 266 267 if (!ds) 268 return; 269 270 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 271 (u32)((u64)(unsigned long)ds), 272 (u32)((u64)(unsigned long)ds >> 32)); 273 } 274 275 void fini_debug_store_on_cpu(int cpu) 276 { 277 if (!per_cpu(cpu_hw_events, cpu).ds) 278 return; 279 280 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); 281 } 282 283 static DEFINE_PER_CPU(void *, insn_buffer); 284 285 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot) 286 { 287 unsigned long start = (unsigned long)cea; 288 phys_addr_t pa; 289 size_t msz = 0; 290 291 pa = virt_to_phys(addr); 292 293 preempt_disable(); 294 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE) 295 cea_set_pte(cea, pa, prot); 296 297 /* 298 * This is a cross-CPU update of the cpu_entry_area, we must shoot down 299 * all TLB entries for it. 300 */ 301 flush_tlb_kernel_range(start, start + size); 302 preempt_enable(); 303 } 304 305 static void ds_clear_cea(void *cea, size_t size) 306 { 307 unsigned long start = (unsigned long)cea; 308 size_t msz = 0; 309 310 preempt_disable(); 311 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE) 312 cea_set_pte(cea, 0, PAGE_NONE); 313 314 flush_tlb_kernel_range(start, start + size); 315 preempt_enable(); 316 } 317 318 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu) 319 { 320 unsigned int order = get_order(size); 321 int node = cpu_to_node(cpu); 322 struct page *page; 323 324 page = __alloc_pages_node(node, flags | __GFP_ZERO, order); 325 return page ? page_address(page) : NULL; 326 } 327 328 static void dsfree_pages(const void *buffer, size_t size) 329 { 330 if (buffer) 331 free_pages((unsigned long)buffer, get_order(size)); 332 } 333 334 static int alloc_pebs_buffer(int cpu) 335 { 336 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 337 struct debug_store *ds = hwev->ds; 338 size_t bsiz = x86_pmu.pebs_buffer_size; 339 int max, node = cpu_to_node(cpu); 340 void *buffer, *ibuffer, *cea; 341 342 if (!x86_pmu.pebs) 343 return 0; 344 345 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu); 346 if (unlikely(!buffer)) 347 return -ENOMEM; 348 349 /* 350 * HSW+ already provides us the eventing ip; no need to allocate this 351 * buffer then. 352 */ 353 if (x86_pmu.intel_cap.pebs_format < 2) { 354 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); 355 if (!ibuffer) { 356 dsfree_pages(buffer, bsiz); 357 return -ENOMEM; 358 } 359 per_cpu(insn_buffer, cpu) = ibuffer; 360 } 361 hwev->ds_pebs_vaddr = buffer; 362 /* Update the cpu entry area mapping */ 363 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 364 ds->pebs_buffer_base = (unsigned long) cea; 365 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL); 366 ds->pebs_index = ds->pebs_buffer_base; 367 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); 368 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; 369 return 0; 370 } 371 372 static void release_pebs_buffer(int cpu) 373 { 374 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 375 void *cea; 376 377 if (!x86_pmu.pebs) 378 return; 379 380 kfree(per_cpu(insn_buffer, cpu)); 381 per_cpu(insn_buffer, cpu) = NULL; 382 383 /* Clear the fixmap */ 384 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 385 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); 386 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); 387 hwev->ds_pebs_vaddr = NULL; 388 } 389 390 static int alloc_bts_buffer(int cpu) 391 { 392 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 393 struct debug_store *ds = hwev->ds; 394 void *buffer, *cea; 395 int max; 396 397 if (!x86_pmu.bts) 398 return 0; 399 400 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu); 401 if (unlikely(!buffer)) { 402 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); 403 return -ENOMEM; 404 } 405 hwev->ds_bts_vaddr = buffer; 406 /* Update the fixmap */ 407 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 408 ds->bts_buffer_base = (unsigned long) cea; 409 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL); 410 ds->bts_index = ds->bts_buffer_base; 411 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; 412 ds->bts_absolute_maximum = ds->bts_buffer_base + 413 max * BTS_RECORD_SIZE; 414 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - 415 (max / 16) * BTS_RECORD_SIZE; 416 return 0; 417 } 418 419 static void release_bts_buffer(int cpu) 420 { 421 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 422 void *cea; 423 424 if (!x86_pmu.bts) 425 return; 426 427 /* Clear the fixmap */ 428 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 429 ds_clear_cea(cea, BTS_BUFFER_SIZE); 430 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); 431 hwev->ds_bts_vaddr = NULL; 432 } 433 434 static int alloc_ds_buffer(int cpu) 435 { 436 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; 437 438 memset(ds, 0, sizeof(*ds)); 439 per_cpu(cpu_hw_events, cpu).ds = ds; 440 return 0; 441 } 442 443 static void release_ds_buffer(int cpu) 444 { 445 per_cpu(cpu_hw_events, cpu).ds = NULL; 446 } 447 448 void release_ds_buffers(void) 449 { 450 int cpu; 451 452 if (!x86_pmu.bts && !x86_pmu.pebs) 453 return; 454 455 for_each_possible_cpu(cpu) 456 release_ds_buffer(cpu); 457 458 for_each_possible_cpu(cpu) { 459 /* 460 * Again, ignore errors from offline CPUs, they will no longer 461 * observe cpu_hw_events.ds and not program the DS_AREA when 462 * they come up. 463 */ 464 fini_debug_store_on_cpu(cpu); 465 } 466 467 for_each_possible_cpu(cpu) { 468 release_pebs_buffer(cpu); 469 release_bts_buffer(cpu); 470 } 471 } 472 473 void reserve_ds_buffers(void) 474 { 475 int bts_err = 0, pebs_err = 0; 476 int cpu; 477 478 x86_pmu.bts_active = 0; 479 x86_pmu.pebs_active = 0; 480 481 if (!x86_pmu.bts && !x86_pmu.pebs) 482 return; 483 484 if (!x86_pmu.bts) 485 bts_err = 1; 486 487 if (!x86_pmu.pebs) 488 pebs_err = 1; 489 490 for_each_possible_cpu(cpu) { 491 if (alloc_ds_buffer(cpu)) { 492 bts_err = 1; 493 pebs_err = 1; 494 } 495 496 if (!bts_err && alloc_bts_buffer(cpu)) 497 bts_err = 1; 498 499 if (!pebs_err && alloc_pebs_buffer(cpu)) 500 pebs_err = 1; 501 502 if (bts_err && pebs_err) 503 break; 504 } 505 506 if (bts_err) { 507 for_each_possible_cpu(cpu) 508 release_bts_buffer(cpu); 509 } 510 511 if (pebs_err) { 512 for_each_possible_cpu(cpu) 513 release_pebs_buffer(cpu); 514 } 515 516 if (bts_err && pebs_err) { 517 for_each_possible_cpu(cpu) 518 release_ds_buffer(cpu); 519 } else { 520 if (x86_pmu.bts && !bts_err) 521 x86_pmu.bts_active = 1; 522 523 if (x86_pmu.pebs && !pebs_err) 524 x86_pmu.pebs_active = 1; 525 526 for_each_possible_cpu(cpu) { 527 /* 528 * Ignores wrmsr_on_cpu() errors for offline CPUs they 529 * will get this call through intel_pmu_cpu_starting(). 530 */ 531 init_debug_store_on_cpu(cpu); 532 } 533 } 534 } 535 536 /* 537 * BTS 538 */ 539 540 struct event_constraint bts_constraint = 541 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); 542 543 void intel_pmu_enable_bts(u64 config) 544 { 545 unsigned long debugctlmsr; 546 547 debugctlmsr = get_debugctlmsr(); 548 549 debugctlmsr |= DEBUGCTLMSR_TR; 550 debugctlmsr |= DEBUGCTLMSR_BTS; 551 if (config & ARCH_PERFMON_EVENTSEL_INT) 552 debugctlmsr |= DEBUGCTLMSR_BTINT; 553 554 if (!(config & ARCH_PERFMON_EVENTSEL_OS)) 555 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; 556 557 if (!(config & ARCH_PERFMON_EVENTSEL_USR)) 558 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; 559 560 update_debugctlmsr(debugctlmsr); 561 } 562 563 void intel_pmu_disable_bts(void) 564 { 565 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 566 unsigned long debugctlmsr; 567 568 if (!cpuc->ds) 569 return; 570 571 debugctlmsr = get_debugctlmsr(); 572 573 debugctlmsr &= 574 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | 575 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); 576 577 update_debugctlmsr(debugctlmsr); 578 } 579 580 int intel_pmu_drain_bts_buffer(void) 581 { 582 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 583 struct debug_store *ds = cpuc->ds; 584 struct bts_record { 585 u64 from; 586 u64 to; 587 u64 flags; 588 }; 589 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 590 struct bts_record *at, *base, *top; 591 struct perf_output_handle handle; 592 struct perf_event_header header; 593 struct perf_sample_data data; 594 unsigned long skip = 0; 595 struct pt_regs regs; 596 597 if (!event) 598 return 0; 599 600 if (!x86_pmu.bts_active) 601 return 0; 602 603 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; 604 top = (struct bts_record *)(unsigned long)ds->bts_index; 605 606 if (top <= base) 607 return 0; 608 609 memset(®s, 0, sizeof(regs)); 610 611 ds->bts_index = ds->bts_buffer_base; 612 613 perf_sample_data_init(&data, 0, event->hw.last_period); 614 615 /* 616 * BTS leaks kernel addresses in branches across the cpl boundary, 617 * such as traps or system calls, so unless the user is asking for 618 * kernel tracing (and right now it's not possible), we'd need to 619 * filter them out. But first we need to count how many of those we 620 * have in the current batch. This is an extra O(n) pass, however, 621 * it's much faster than the other one especially considering that 622 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the 623 * alloc_bts_buffer()). 624 */ 625 for (at = base; at < top; at++) { 626 /* 627 * Note that right now *this* BTS code only works if 628 * attr::exclude_kernel is set, but let's keep this extra 629 * check here in case that changes. 630 */ 631 if (event->attr.exclude_kernel && 632 (kernel_ip(at->from) || kernel_ip(at->to))) 633 skip++; 634 } 635 636 /* 637 * Prepare a generic sample, i.e. fill in the invariant fields. 638 * We will overwrite the from and to address before we output 639 * the sample. 640 */ 641 rcu_read_lock(); 642 perf_prepare_sample(&header, &data, event, ®s); 643 644 if (perf_output_begin(&handle, event, header.size * 645 (top - base - skip))) 646 goto unlock; 647 648 for (at = base; at < top; at++) { 649 /* Filter out any records that contain kernel addresses. */ 650 if (event->attr.exclude_kernel && 651 (kernel_ip(at->from) || kernel_ip(at->to))) 652 continue; 653 654 data.ip = at->from; 655 data.addr = at->to; 656 657 perf_output_sample(&handle, &header, &data, event); 658 } 659 660 perf_output_end(&handle); 661 662 /* There's new data available. */ 663 event->hw.interrupts++; 664 event->pending_kill = POLL_IN; 665 unlock: 666 rcu_read_unlock(); 667 return 1; 668 } 669 670 static inline void intel_pmu_drain_pebs_buffer(void) 671 { 672 struct pt_regs regs; 673 674 x86_pmu.drain_pebs(®s); 675 } 676 677 /* 678 * PEBS 679 */ 680 struct event_constraint intel_core2_pebs_event_constraints[] = { 681 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 682 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ 683 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ 684 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ 685 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 686 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 687 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), 688 EVENT_CONSTRAINT_END 689 }; 690 691 struct event_constraint intel_atom_pebs_event_constraints[] = { 692 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 693 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ 694 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 695 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 696 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), 697 /* Allow all events as PEBS with no flags */ 698 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 699 EVENT_CONSTRAINT_END 700 }; 701 702 struct event_constraint intel_slm_pebs_event_constraints[] = { 703 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 704 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), 705 /* Allow all events as PEBS with no flags */ 706 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 707 EVENT_CONSTRAINT_END 708 }; 709 710 struct event_constraint intel_glm_pebs_event_constraints[] = { 711 /* Allow all events as PEBS with no flags */ 712 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 713 EVENT_CONSTRAINT_END 714 }; 715 716 struct event_constraint intel_glp_pebs_event_constraints[] = { 717 /* Allow all events as PEBS with no flags */ 718 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 719 EVENT_CONSTRAINT_END 720 }; 721 722 struct event_constraint intel_nehalem_pebs_event_constraints[] = { 723 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 724 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 725 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 726 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ 727 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 728 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 729 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ 730 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 731 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 732 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 733 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 734 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 735 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 736 EVENT_CONSTRAINT_END 737 }; 738 739 struct event_constraint intel_westmere_pebs_event_constraints[] = { 740 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 741 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 742 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 743 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ 744 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 745 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 746 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ 747 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 748 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 749 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 750 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 751 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 752 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 753 EVENT_CONSTRAINT_END 754 }; 755 756 struct event_constraint intel_snb_pebs_event_constraints[] = { 757 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 758 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 759 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 760 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 761 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 762 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 763 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 764 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 765 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 766 /* Allow all events as PEBS with no flags */ 767 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 768 EVENT_CONSTRAINT_END 769 }; 770 771 struct event_constraint intel_ivb_pebs_event_constraints[] = { 772 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 773 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 774 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 775 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 776 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 777 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 778 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 779 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 780 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 781 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 782 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 783 /* Allow all events as PEBS with no flags */ 784 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 785 EVENT_CONSTRAINT_END 786 }; 787 788 struct event_constraint intel_hsw_pebs_event_constraints[] = { 789 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 790 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 791 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 792 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 793 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 794 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 795 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 796 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 797 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 798 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 799 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 800 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 801 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 802 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 803 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 804 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 805 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 806 /* Allow all events as PEBS with no flags */ 807 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 808 EVENT_CONSTRAINT_END 809 }; 810 811 struct event_constraint intel_bdw_pebs_event_constraints[] = { 812 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 813 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 814 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 815 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 816 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 817 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 818 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 819 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 820 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 821 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 822 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 823 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 824 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 825 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 826 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 827 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 828 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 829 /* Allow all events as PEBS with no flags */ 830 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 831 EVENT_CONSTRAINT_END 832 }; 833 834 835 struct event_constraint intel_skl_pebs_event_constraints[] = { 836 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 837 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 838 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 839 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ 840 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 841 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ 842 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 843 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 844 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 845 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ 846 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 847 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 848 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 849 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 850 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 851 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 852 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ 853 /* Allow all events as PEBS with no flags */ 854 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 855 EVENT_CONSTRAINT_END 856 }; 857 858 struct event_constraint *intel_pebs_constraints(struct perf_event *event) 859 { 860 struct event_constraint *c; 861 862 if (!event->attr.precise_ip) 863 return NULL; 864 865 if (x86_pmu.pebs_constraints) { 866 for_each_event_constraint(c, x86_pmu.pebs_constraints) { 867 if ((event->hw.config & c->cmask) == c->code) { 868 event->hw.flags |= c->flags; 869 return c; 870 } 871 } 872 } 873 874 return &emptyconstraint; 875 } 876 877 /* 878 * We need the sched_task callback even for per-cpu events when we use 879 * the large interrupt threshold, such that we can provide PID and TID 880 * to PEBS samples. 881 */ 882 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc) 883 { 884 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); 885 } 886 887 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) 888 { 889 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 890 891 if (!sched_in && pebs_needs_sched_cb(cpuc)) 892 intel_pmu_drain_pebs_buffer(); 893 } 894 895 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) 896 { 897 struct debug_store *ds = cpuc->ds; 898 u64 threshold; 899 900 if (cpuc->n_pebs == cpuc->n_large_pebs) { 901 threshold = ds->pebs_absolute_maximum - 902 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size; 903 } else { 904 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; 905 } 906 907 ds->pebs_interrupt_threshold = threshold; 908 } 909 910 static void 911 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu) 912 { 913 /* 914 * Make sure we get updated with the first PEBS 915 * event. It will trigger also during removal, but 916 * that does not hurt: 917 */ 918 bool update = cpuc->n_pebs == 1; 919 920 if (needed_cb != pebs_needs_sched_cb(cpuc)) { 921 if (!needed_cb) 922 perf_sched_cb_inc(pmu); 923 else 924 perf_sched_cb_dec(pmu); 925 926 update = true; 927 } 928 929 if (update) 930 pebs_update_threshold(cpuc); 931 } 932 933 void intel_pmu_pebs_add(struct perf_event *event) 934 { 935 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 936 struct hw_perf_event *hwc = &event->hw; 937 bool needed_cb = pebs_needs_sched_cb(cpuc); 938 939 cpuc->n_pebs++; 940 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 941 cpuc->n_large_pebs++; 942 943 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); 944 } 945 946 void intel_pmu_pebs_enable(struct perf_event *event) 947 { 948 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 949 struct hw_perf_event *hwc = &event->hw; 950 struct debug_store *ds = cpuc->ds; 951 952 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; 953 954 cpuc->pebs_enabled |= 1ULL << hwc->idx; 955 956 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) 957 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); 958 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 959 cpuc->pebs_enabled |= 1ULL << 63; 960 961 /* 962 * Use auto-reload if possible to save a MSR write in the PMI. 963 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD. 964 */ 965 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 966 ds->pebs_event_reset[hwc->idx] = 967 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; 968 } else { 969 ds->pebs_event_reset[hwc->idx] = 0; 970 } 971 } 972 973 void intel_pmu_pebs_del(struct perf_event *event) 974 { 975 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 976 struct hw_perf_event *hwc = &event->hw; 977 bool needed_cb = pebs_needs_sched_cb(cpuc); 978 979 cpuc->n_pebs--; 980 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 981 cpuc->n_large_pebs--; 982 983 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); 984 } 985 986 void intel_pmu_pebs_disable(struct perf_event *event) 987 { 988 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 989 struct hw_perf_event *hwc = &event->hw; 990 991 if (cpuc->n_pebs == cpuc->n_large_pebs) 992 intel_pmu_drain_pebs_buffer(); 993 994 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); 995 996 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) 997 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); 998 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 999 cpuc->pebs_enabled &= ~(1ULL << 63); 1000 1001 if (cpuc->enabled) 1002 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1003 1004 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 1005 } 1006 1007 void intel_pmu_pebs_enable_all(void) 1008 { 1009 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1010 1011 if (cpuc->pebs_enabled) 1012 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1013 } 1014 1015 void intel_pmu_pebs_disable_all(void) 1016 { 1017 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1018 1019 if (cpuc->pebs_enabled) 1020 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1021 } 1022 1023 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) 1024 { 1025 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1026 unsigned long from = cpuc->lbr_entries[0].from; 1027 unsigned long old_to, to = cpuc->lbr_entries[0].to; 1028 unsigned long ip = regs->ip; 1029 int is_64bit = 0; 1030 void *kaddr; 1031 int size; 1032 1033 /* 1034 * We don't need to fixup if the PEBS assist is fault like 1035 */ 1036 if (!x86_pmu.intel_cap.pebs_trap) 1037 return 1; 1038 1039 /* 1040 * No LBR entry, no basic block, no rewinding 1041 */ 1042 if (!cpuc->lbr_stack.nr || !from || !to) 1043 return 0; 1044 1045 /* 1046 * Basic blocks should never cross user/kernel boundaries 1047 */ 1048 if (kernel_ip(ip) != kernel_ip(to)) 1049 return 0; 1050 1051 /* 1052 * unsigned math, either ip is before the start (impossible) or 1053 * the basic block is larger than 1 page (sanity) 1054 */ 1055 if ((ip - to) > PEBS_FIXUP_SIZE) 1056 return 0; 1057 1058 /* 1059 * We sampled a branch insn, rewind using the LBR stack 1060 */ 1061 if (ip == to) { 1062 set_linear_ip(regs, from); 1063 return 1; 1064 } 1065 1066 size = ip - to; 1067 if (!kernel_ip(ip)) { 1068 int bytes; 1069 u8 *buf = this_cpu_read(insn_buffer); 1070 1071 /* 'size' must fit our buffer, see above */ 1072 bytes = copy_from_user_nmi(buf, (void __user *)to, size); 1073 if (bytes != 0) 1074 return 0; 1075 1076 kaddr = buf; 1077 } else { 1078 kaddr = (void *)to; 1079 } 1080 1081 do { 1082 struct insn insn; 1083 1084 old_to = to; 1085 1086 #ifdef CONFIG_X86_64 1087 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); 1088 #endif 1089 insn_init(&insn, kaddr, size, is_64bit); 1090 insn_get_length(&insn); 1091 /* 1092 * Make sure there was not a problem decoding the 1093 * instruction and getting the length. This is 1094 * doubly important because we have an infinite 1095 * loop if insn.length=0. 1096 */ 1097 if (!insn.length) 1098 break; 1099 1100 to += insn.length; 1101 kaddr += insn.length; 1102 size -= insn.length; 1103 } while (to < ip); 1104 1105 if (to == ip) { 1106 set_linear_ip(regs, old_to); 1107 return 1; 1108 } 1109 1110 /* 1111 * Even though we decoded the basic block, the instruction stream 1112 * never matched the given IP, either the TO or the IP got corrupted. 1113 */ 1114 return 0; 1115 } 1116 1117 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs) 1118 { 1119 if (pebs->tsx_tuning) { 1120 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; 1121 return tsx.cycles_last_block; 1122 } 1123 return 0; 1124 } 1125 1126 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs) 1127 { 1128 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; 1129 1130 /* For RTM XABORTs also log the abort code from AX */ 1131 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) 1132 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 1133 return txn; 1134 } 1135 1136 static void setup_pebs_sample_data(struct perf_event *event, 1137 struct pt_regs *iregs, void *__pebs, 1138 struct perf_sample_data *data, 1139 struct pt_regs *regs) 1140 { 1141 #define PERF_X86_EVENT_PEBS_HSW_PREC \ 1142 (PERF_X86_EVENT_PEBS_ST_HSW | \ 1143 PERF_X86_EVENT_PEBS_LD_HSW | \ 1144 PERF_X86_EVENT_PEBS_NA_HSW) 1145 /* 1146 * We cast to the biggest pebs_record but are careful not to 1147 * unconditionally access the 'extra' entries. 1148 */ 1149 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1150 struct pebs_record_skl *pebs = __pebs; 1151 u64 sample_type; 1152 int fll, fst, dsrc; 1153 int fl = event->hw.flags; 1154 1155 if (pebs == NULL) 1156 return; 1157 1158 sample_type = event->attr.sample_type; 1159 dsrc = sample_type & PERF_SAMPLE_DATA_SRC; 1160 1161 fll = fl & PERF_X86_EVENT_PEBS_LDLAT; 1162 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); 1163 1164 perf_sample_data_init(data, 0, event->hw.last_period); 1165 1166 data->period = event->hw.last_period; 1167 1168 /* 1169 * Use latency for weight (only avail with PEBS-LL) 1170 */ 1171 if (fll && (sample_type & PERF_SAMPLE_WEIGHT)) 1172 data->weight = pebs->lat; 1173 1174 /* 1175 * data.data_src encodes the data source 1176 */ 1177 if (dsrc) { 1178 u64 val = PERF_MEM_NA; 1179 if (fll) 1180 val = load_latency_data(pebs->dse); 1181 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) 1182 val = precise_datala_hsw(event, pebs->dse); 1183 else if (fst) 1184 val = precise_store_data(pebs->dse); 1185 data->data_src.val = val; 1186 } 1187 1188 /* 1189 * We use the interrupt regs as a base because the PEBS record does not 1190 * contain a full regs set, specifically it seems to lack segment 1191 * descriptors, which get used by things like user_mode(). 1192 * 1193 * In the simple case fix up only the IP for PERF_SAMPLE_IP. 1194 * 1195 * We must however always use BP,SP from iregs for the unwinder to stay 1196 * sane; the record BP,SP can point into thin air when the record is 1197 * from a previous PMI context or an (I)RET happend between the record 1198 * and PMI. 1199 */ 1200 *regs = *iregs; 1201 1202 /* 1203 * Initialize regs_>flags from PEBS, 1204 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3), 1205 * i.e., do not rely on it being zero: 1206 */ 1207 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; 1208 1209 if (sample_type & PERF_SAMPLE_REGS_INTR) { 1210 regs->ax = pebs->ax; 1211 regs->bx = pebs->bx; 1212 regs->cx = pebs->cx; 1213 regs->dx = pebs->dx; 1214 regs->si = pebs->si; 1215 regs->di = pebs->di; 1216 1217 /* 1218 * Per the above; only set BP,SP if we don't need callchains. 1219 * 1220 * XXX: does this make sense? 1221 */ 1222 if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) { 1223 regs->bp = pebs->bp; 1224 regs->sp = pebs->sp; 1225 } 1226 1227 #ifndef CONFIG_X86_32 1228 regs->r8 = pebs->r8; 1229 regs->r9 = pebs->r9; 1230 regs->r10 = pebs->r10; 1231 regs->r11 = pebs->r11; 1232 regs->r12 = pebs->r12; 1233 regs->r13 = pebs->r13; 1234 regs->r14 = pebs->r14; 1235 regs->r15 = pebs->r15; 1236 #endif 1237 } 1238 1239 if (event->attr.precise_ip > 1) { 1240 /* 1241 * Haswell and later processors have an 'eventing IP' 1242 * (real IP) which fixes the off-by-1 skid in hardware. 1243 * Use it when precise_ip >= 2 : 1244 */ 1245 if (x86_pmu.intel_cap.pebs_format >= 2) { 1246 set_linear_ip(regs, pebs->real_ip); 1247 regs->flags |= PERF_EFLAGS_EXACT; 1248 } else { 1249 /* Otherwise, use PEBS off-by-1 IP: */ 1250 set_linear_ip(regs, pebs->ip); 1251 1252 /* 1253 * With precise_ip >= 2, try to fix up the off-by-1 IP 1254 * using the LBR. If successful, the fixup function 1255 * corrects regs->ip and calls set_linear_ip() on regs: 1256 */ 1257 if (intel_pmu_pebs_fixup_ip(regs)) 1258 regs->flags |= PERF_EFLAGS_EXACT; 1259 } 1260 } else { 1261 /* 1262 * When precise_ip == 1, return the PEBS off-by-1 IP, 1263 * no fixup attempted: 1264 */ 1265 set_linear_ip(regs, pebs->ip); 1266 } 1267 1268 1269 if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) && 1270 x86_pmu.intel_cap.pebs_format >= 1) 1271 data->addr = pebs->dla; 1272 1273 if (x86_pmu.intel_cap.pebs_format >= 2) { 1274 /* Only set the TSX weight when no memory weight. */ 1275 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) 1276 data->weight = intel_hsw_weight(pebs); 1277 1278 if (sample_type & PERF_SAMPLE_TRANSACTION) 1279 data->txn = intel_hsw_transaction(pebs); 1280 } 1281 1282 /* 1283 * v3 supplies an accurate time stamp, so we use that 1284 * for the time stamp. 1285 * 1286 * We can only do this for the default trace clock. 1287 */ 1288 if (x86_pmu.intel_cap.pebs_format >= 3 && 1289 event->attr.use_clockid == 0) 1290 data->time = native_sched_clock_from_tsc(pebs->tsc); 1291 1292 if (has_branch_stack(event)) 1293 data->br_stack = &cpuc->lbr_stack; 1294 } 1295 1296 static inline void * 1297 get_next_pebs_record_by_bit(void *base, void *top, int bit) 1298 { 1299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1300 void *at; 1301 u64 pebs_status; 1302 1303 /* 1304 * fmt0 does not have a status bitfield (does not use 1305 * perf_record_nhm format) 1306 */ 1307 if (x86_pmu.intel_cap.pebs_format < 1) 1308 return base; 1309 1310 if (base == NULL) 1311 return NULL; 1312 1313 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 1314 struct pebs_record_nhm *p = at; 1315 1316 if (test_bit(bit, (unsigned long *)&p->status)) { 1317 /* PEBS v3 has accurate status bits */ 1318 if (x86_pmu.intel_cap.pebs_format >= 3) 1319 return at; 1320 1321 if (p->status == (1 << bit)) 1322 return at; 1323 1324 /* clear non-PEBS bit and re-check */ 1325 pebs_status = p->status & cpuc->pebs_enabled; 1326 pebs_status &= PEBS_COUNTER_MASK; 1327 if (pebs_status == (1 << bit)) 1328 return at; 1329 } 1330 } 1331 return NULL; 1332 } 1333 1334 void intel_pmu_auto_reload_read(struct perf_event *event) 1335 { 1336 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); 1337 1338 perf_pmu_disable(event->pmu); 1339 intel_pmu_drain_pebs_buffer(); 1340 perf_pmu_enable(event->pmu); 1341 } 1342 1343 /* 1344 * Special variant of intel_pmu_save_and_restart() for auto-reload. 1345 */ 1346 static int 1347 intel_pmu_save_and_restart_reload(struct perf_event *event, int count) 1348 { 1349 struct hw_perf_event *hwc = &event->hw; 1350 int shift = 64 - x86_pmu.cntval_bits; 1351 u64 period = hwc->sample_period; 1352 u64 prev_raw_count, new_raw_count; 1353 s64 new, old; 1354 1355 WARN_ON(!period); 1356 1357 /* 1358 * drain_pebs() only happens when the PMU is disabled. 1359 */ 1360 WARN_ON(this_cpu_read(cpu_hw_events.enabled)); 1361 1362 prev_raw_count = local64_read(&hwc->prev_count); 1363 rdpmcl(hwc->event_base_rdpmc, new_raw_count); 1364 local64_set(&hwc->prev_count, new_raw_count); 1365 1366 /* 1367 * Since the counter increments a negative counter value and 1368 * overflows on the sign switch, giving the interval: 1369 * 1370 * [-period, 0] 1371 * 1372 * the difference between two consequtive reads is: 1373 * 1374 * A) value2 - value1; 1375 * when no overflows have happened in between, 1376 * 1377 * B) (0 - value1) + (value2 - (-period)); 1378 * when one overflow happened in between, 1379 * 1380 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); 1381 * when @n overflows happened in between. 1382 * 1383 * Here A) is the obvious difference, B) is the extension to the 1384 * discrete interval, where the first term is to the top of the 1385 * interval and the second term is from the bottom of the next 1386 * interval and C) the extension to multiple intervals, where the 1387 * middle term is the whole intervals covered. 1388 * 1389 * An equivalent of C, by reduction, is: 1390 * 1391 * value2 - value1 + n * period 1392 */ 1393 new = ((s64)(new_raw_count << shift) >> shift); 1394 old = ((s64)(prev_raw_count << shift) >> shift); 1395 local64_add(new - old + count * period, &event->count); 1396 1397 perf_event_update_userpage(event); 1398 1399 return 0; 1400 } 1401 1402 static void __intel_pmu_pebs_event(struct perf_event *event, 1403 struct pt_regs *iregs, 1404 void *base, void *top, 1405 int bit, int count) 1406 { 1407 struct hw_perf_event *hwc = &event->hw; 1408 struct perf_sample_data data; 1409 struct pt_regs regs; 1410 void *at = get_next_pebs_record_by_bit(base, top, bit); 1411 1412 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 1413 /* 1414 * Now, auto-reload is only enabled in fixed period mode. 1415 * The reload value is always hwc->sample_period. 1416 * May need to change it, if auto-reload is enabled in 1417 * freq mode later. 1418 */ 1419 intel_pmu_save_and_restart_reload(event, count); 1420 } else if (!intel_pmu_save_and_restart(event)) 1421 return; 1422 1423 while (count > 1) { 1424 setup_pebs_sample_data(event, iregs, at, &data, ®s); 1425 perf_event_output(event, &data, ®s); 1426 at += x86_pmu.pebs_record_size; 1427 at = get_next_pebs_record_by_bit(at, top, bit); 1428 count--; 1429 } 1430 1431 setup_pebs_sample_data(event, iregs, at, &data, ®s); 1432 1433 /* 1434 * All but the last records are processed. 1435 * The last one is left to be able to call the overflow handler. 1436 */ 1437 if (perf_event_overflow(event, &data, ®s)) { 1438 x86_pmu_stop(event, 0); 1439 return; 1440 } 1441 1442 } 1443 1444 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) 1445 { 1446 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1447 struct debug_store *ds = cpuc->ds; 1448 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ 1449 struct pebs_record_core *at, *top; 1450 int n; 1451 1452 if (!x86_pmu.pebs_active) 1453 return; 1454 1455 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; 1456 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; 1457 1458 /* 1459 * Whatever else happens, drain the thing 1460 */ 1461 ds->pebs_index = ds->pebs_buffer_base; 1462 1463 if (!test_bit(0, cpuc->active_mask)) 1464 return; 1465 1466 WARN_ON_ONCE(!event); 1467 1468 if (!event->attr.precise_ip) 1469 return; 1470 1471 n = top - at; 1472 if (n <= 0) { 1473 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 1474 intel_pmu_save_and_restart_reload(event, 0); 1475 return; 1476 } 1477 1478 __intel_pmu_pebs_event(event, iregs, at, top, 0, n); 1479 } 1480 1481 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 1482 { 1483 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1484 struct debug_store *ds = cpuc->ds; 1485 struct perf_event *event; 1486 void *base, *at, *top; 1487 short counts[MAX_PEBS_EVENTS] = {}; 1488 short error[MAX_PEBS_EVENTS] = {}; 1489 int bit, i; 1490 1491 if (!x86_pmu.pebs_active) 1492 return; 1493 1494 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; 1495 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; 1496 1497 ds->pebs_index = ds->pebs_buffer_base; 1498 1499 if (unlikely(base >= top)) { 1500 /* 1501 * The drain_pebs() could be called twice in a short period 1502 * for auto-reload event in pmu::read(). There are no 1503 * overflows have happened in between. 1504 * It needs to call intel_pmu_save_and_restart_reload() to 1505 * update the event->count for this case. 1506 */ 1507 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, 1508 x86_pmu.max_pebs_events) { 1509 event = cpuc->events[bit]; 1510 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 1511 intel_pmu_save_and_restart_reload(event, 0); 1512 } 1513 return; 1514 } 1515 1516 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 1517 struct pebs_record_nhm *p = at; 1518 u64 pebs_status; 1519 1520 pebs_status = p->status & cpuc->pebs_enabled; 1521 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1; 1522 1523 /* PEBS v3 has more accurate status bits */ 1524 if (x86_pmu.intel_cap.pebs_format >= 3) { 1525 for_each_set_bit(bit, (unsigned long *)&pebs_status, 1526 x86_pmu.max_pebs_events) 1527 counts[bit]++; 1528 1529 continue; 1530 } 1531 1532 /* 1533 * On some CPUs the PEBS status can be zero when PEBS is 1534 * racing with clearing of GLOBAL_STATUS. 1535 * 1536 * Normally we would drop that record, but in the 1537 * case when there is only a single active PEBS event 1538 * we can assume it's for that event. 1539 */ 1540 if (!pebs_status && cpuc->pebs_enabled && 1541 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) 1542 pebs_status = cpuc->pebs_enabled; 1543 1544 bit = find_first_bit((unsigned long *)&pebs_status, 1545 x86_pmu.max_pebs_events); 1546 if (bit >= x86_pmu.max_pebs_events) 1547 continue; 1548 1549 /* 1550 * The PEBS hardware does not deal well with the situation 1551 * when events happen near to each other and multiple bits 1552 * are set. But it should happen rarely. 1553 * 1554 * If these events include one PEBS and multiple non-PEBS 1555 * events, it doesn't impact PEBS record. The record will 1556 * be handled normally. (slow path) 1557 * 1558 * If these events include two or more PEBS events, the 1559 * records for the events can be collapsed into a single 1560 * one, and it's not possible to reconstruct all events 1561 * that caused the PEBS record. It's called collision. 1562 * If collision happened, the record will be dropped. 1563 */ 1564 if (p->status != (1ULL << bit)) { 1565 for_each_set_bit(i, (unsigned long *)&pebs_status, 1566 x86_pmu.max_pebs_events) 1567 error[i]++; 1568 continue; 1569 } 1570 1571 counts[bit]++; 1572 } 1573 1574 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) { 1575 if ((counts[bit] == 0) && (error[bit] == 0)) 1576 continue; 1577 1578 event = cpuc->events[bit]; 1579 if (WARN_ON_ONCE(!event)) 1580 continue; 1581 1582 if (WARN_ON_ONCE(!event->attr.precise_ip)) 1583 continue; 1584 1585 /* log dropped samples number */ 1586 if (error[bit]) { 1587 perf_log_lost_samples(event, error[bit]); 1588 1589 if (perf_event_account_interrupt(event)) 1590 x86_pmu_stop(event, 0); 1591 } 1592 1593 if (counts[bit]) { 1594 __intel_pmu_pebs_event(event, iregs, base, 1595 top, bit, counts[bit]); 1596 } 1597 } 1598 } 1599 1600 /* 1601 * BTS, PEBS probe and setup 1602 */ 1603 1604 void __init intel_ds_init(void) 1605 { 1606 /* 1607 * No support for 32bit formats 1608 */ 1609 if (!boot_cpu_has(X86_FEATURE_DTES64)) 1610 return; 1611 1612 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); 1613 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); 1614 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; 1615 if (x86_pmu.pebs) { 1616 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; 1617 int format = x86_pmu.intel_cap.pebs_format; 1618 1619 switch (format) { 1620 case 0: 1621 pr_cont("PEBS fmt0%c, ", pebs_type); 1622 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); 1623 /* 1624 * Using >PAGE_SIZE buffers makes the WRMSR to 1625 * PERF_GLOBAL_CTRL in intel_pmu_enable_all() 1626 * mysteriously hang on Core2. 1627 * 1628 * As a workaround, we don't do this. 1629 */ 1630 x86_pmu.pebs_buffer_size = PAGE_SIZE; 1631 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; 1632 break; 1633 1634 case 1: 1635 pr_cont("PEBS fmt1%c, ", pebs_type); 1636 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); 1637 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1638 break; 1639 1640 case 2: 1641 pr_cont("PEBS fmt2%c, ", pebs_type); 1642 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); 1643 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1644 break; 1645 1646 case 3: 1647 pr_cont("PEBS fmt3%c, ", pebs_type); 1648 x86_pmu.pebs_record_size = 1649 sizeof(struct pebs_record_skl); 1650 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1651 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 1652 break; 1653 1654 default: 1655 pr_cont("no PEBS fmt%d%c, ", format, pebs_type); 1656 x86_pmu.pebs = 0; 1657 } 1658 } 1659 } 1660 1661 void perf_restore_debug_store(void) 1662 { 1663 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 1664 1665 if (!x86_pmu.bts && !x86_pmu.pebs) 1666 return; 1667 1668 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); 1669 } 1670