xref: /openbmc/linux/arch/x86/events/intel/ds.c (revision 9221b289)
1  // SPDX-License-Identifier: GPL-2.0
2  #include <linux/bitops.h>
3  #include <linux/types.h>
4  #include <linux/slab.h>
5  
6  #include <asm/cpu_entry_area.h>
7  #include <asm/perf_event.h>
8  #include <asm/tlbflush.h>
9  #include <asm/insn.h>
10  #include <asm/io.h>
11  
12  #include "../perf_event.h"
13  
14  /* Waste a full page so it can be mapped into the cpu_entry_area */
15  DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
16  
17  /* The size of a BTS record in bytes: */
18  #define BTS_RECORD_SIZE		24
19  
20  #define PEBS_FIXUP_SIZE		PAGE_SIZE
21  
22  /*
23   * pebs_record_32 for p4 and core not supported
24  
25  struct pebs_record_32 {
26  	u32 flags, ip;
27  	u32 ax, bc, cx, dx;
28  	u32 si, di, bp, sp;
29  };
30  
31   */
32  
33  union intel_x86_pebs_dse {
34  	u64 val;
35  	struct {
36  		unsigned int ld_dse:4;
37  		unsigned int ld_stlb_miss:1;
38  		unsigned int ld_locked:1;
39  		unsigned int ld_data_blk:1;
40  		unsigned int ld_addr_blk:1;
41  		unsigned int ld_reserved:24;
42  	};
43  	struct {
44  		unsigned int st_l1d_hit:1;
45  		unsigned int st_reserved1:3;
46  		unsigned int st_stlb_miss:1;
47  		unsigned int st_locked:1;
48  		unsigned int st_reserved2:26;
49  	};
50  	struct {
51  		unsigned int st_lat_dse:4;
52  		unsigned int st_lat_stlb_miss:1;
53  		unsigned int st_lat_locked:1;
54  		unsigned int ld_reserved3:26;
55  	};
56  };
57  
58  
59  /*
60   * Map PEBS Load Latency Data Source encodings to generic
61   * memory data source information
62   */
63  #define P(a, b) PERF_MEM_S(a, b)
64  #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
65  #define LEVEL(x) P(LVLNUM, x)
66  #define REM P(REMOTE, REMOTE)
67  #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
68  
69  /* Version for Sandy Bridge and later */
70  static u64 pebs_data_source[] = {
71  	P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
72  	OP_LH | P(LVL, L1)  | LEVEL(L1) | P(SNOOP, NONE),  /* 0x01: L1 local */
73  	OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
74  	OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),  /* 0x03: L2 hit */
75  	OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, NONE),  /* 0x04: L3 hit */
76  	OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, MISS),  /* 0x05: L3 hit, snoop miss */
77  	OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HIT),   /* 0x06: L3 hit, snoop hit */
78  	OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HITM),  /* 0x07: L3 hit, snoop hitm */
79  	OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
80  	OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
81  	OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, HIT),       /* 0x0a: L3 miss, shared */
82  	OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
83  	OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | SNOOP_NONE_MISS,     /* 0x0c: L3 miss, excl */
84  	OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
85  	OP_LH | P(LVL, IO)  | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
86  	OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
87  };
88  
89  /* Patch up minor differences in the bits */
90  void __init intel_pmu_pebs_data_source_nhm(void)
91  {
92  	pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
93  	pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
94  	pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
95  }
96  
97  static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source)
98  {
99  	u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
100  
101  	data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
102  	data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
103  	data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
104  	data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
105  	data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
106  }
107  
108  void __init intel_pmu_pebs_data_source_skl(bool pmem)
109  {
110  	__intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
111  }
112  
113  static void __init intel_pmu_pebs_data_source_grt(u64 *data_source)
114  {
115  	data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
116  	data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
117  	data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
118  }
119  
120  void __init intel_pmu_pebs_data_source_adl(void)
121  {
122  	u64 *data_source;
123  
124  	data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
125  	memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
126  	__intel_pmu_pebs_data_source_skl(false, data_source);
127  
128  	data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
129  	memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
130  	intel_pmu_pebs_data_source_grt(data_source);
131  }
132  
133  static u64 precise_store_data(u64 status)
134  {
135  	union intel_x86_pebs_dse dse;
136  	u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
137  
138  	dse.val = status;
139  
140  	/*
141  	 * bit 4: TLB access
142  	 * 1 = stored missed 2nd level TLB
143  	 *
144  	 * so it either hit the walker or the OS
145  	 * otherwise hit 2nd level TLB
146  	 */
147  	if (dse.st_stlb_miss)
148  		val |= P(TLB, MISS);
149  	else
150  		val |= P(TLB, HIT);
151  
152  	/*
153  	 * bit 0: hit L1 data cache
154  	 * if not set, then all we know is that
155  	 * it missed L1D
156  	 */
157  	if (dse.st_l1d_hit)
158  		val |= P(LVL, HIT);
159  	else
160  		val |= P(LVL, MISS);
161  
162  	/*
163  	 * bit 5: Locked prefix
164  	 */
165  	if (dse.st_locked)
166  		val |= P(LOCK, LOCKED);
167  
168  	return val;
169  }
170  
171  static u64 precise_datala_hsw(struct perf_event *event, u64 status)
172  {
173  	union perf_mem_data_src dse;
174  
175  	dse.val = PERF_MEM_NA;
176  
177  	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
178  		dse.mem_op = PERF_MEM_OP_STORE;
179  	else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
180  		dse.mem_op = PERF_MEM_OP_LOAD;
181  
182  	/*
183  	 * L1 info only valid for following events:
184  	 *
185  	 * MEM_UOPS_RETIRED.STLB_MISS_STORES
186  	 * MEM_UOPS_RETIRED.LOCK_STORES
187  	 * MEM_UOPS_RETIRED.SPLIT_STORES
188  	 * MEM_UOPS_RETIRED.ALL_STORES
189  	 */
190  	if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
191  		if (status & 1)
192  			dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
193  		else
194  			dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
195  	}
196  	return dse.val;
197  }
198  
199  static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
200  {
201  	/*
202  	 * TLB access
203  	 * 0 = did not miss 2nd level TLB
204  	 * 1 = missed 2nd level TLB
205  	 */
206  	if (tlb)
207  		*val |= P(TLB, MISS) | P(TLB, L2);
208  	else
209  		*val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
210  
211  	/* locked prefix */
212  	if (lock)
213  		*val |= P(LOCK, LOCKED);
214  }
215  
216  /* Retrieve the latency data for e-core of ADL */
217  u64 adl_latency_data_small(struct perf_event *event, u64 status)
218  {
219  	union intel_x86_pebs_dse dse;
220  	u64 val;
221  
222  	WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big);
223  
224  	dse.val = status;
225  
226  	val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
227  
228  	/*
229  	 * For the atom core on ADL,
230  	 * bit 4: lock, bit 5: TLB access.
231  	 */
232  	pebs_set_tlb_lock(&val, dse.ld_locked, dse.ld_stlb_miss);
233  
234  	if (dse.ld_data_blk)
235  		val |= P(BLK, DATA);
236  	else
237  		val |= P(BLK, NA);
238  
239  	return val;
240  }
241  
242  static u64 load_latency_data(struct perf_event *event, u64 status)
243  {
244  	union intel_x86_pebs_dse dse;
245  	u64 val;
246  
247  	dse.val = status;
248  
249  	/*
250  	 * use the mapping table for bit 0-3
251  	 */
252  	val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
253  
254  	/*
255  	 * Nehalem models do not support TLB, Lock infos
256  	 */
257  	if (x86_pmu.pebs_no_tlb) {
258  		val |= P(TLB, NA) | P(LOCK, NA);
259  		return val;
260  	}
261  
262  	pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);
263  
264  	/*
265  	 * Ice Lake and earlier models do not support block infos.
266  	 */
267  	if (!x86_pmu.pebs_block) {
268  		val |= P(BLK, NA);
269  		return val;
270  	}
271  	/*
272  	 * bit 6: load was blocked since its data could not be forwarded
273  	 *        from a preceding store
274  	 */
275  	if (dse.ld_data_blk)
276  		val |= P(BLK, DATA);
277  
278  	/*
279  	 * bit 7: load was blocked due to potential address conflict with
280  	 *        a preceding store
281  	 */
282  	if (dse.ld_addr_blk)
283  		val |= P(BLK, ADDR);
284  
285  	if (!dse.ld_data_blk && !dse.ld_addr_blk)
286  		val |= P(BLK, NA);
287  
288  	return val;
289  }
290  
291  static u64 store_latency_data(struct perf_event *event, u64 status)
292  {
293  	union intel_x86_pebs_dse dse;
294  	u64 val;
295  
296  	dse.val = status;
297  
298  	/*
299  	 * use the mapping table for bit 0-3
300  	 */
301  	val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];
302  
303  	pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);
304  
305  	val |= P(BLK, NA);
306  
307  	return val;
308  }
309  
310  struct pebs_record_core {
311  	u64 flags, ip;
312  	u64 ax, bx, cx, dx;
313  	u64 si, di, bp, sp;
314  	u64 r8,  r9,  r10, r11;
315  	u64 r12, r13, r14, r15;
316  };
317  
318  struct pebs_record_nhm {
319  	u64 flags, ip;
320  	u64 ax, bx, cx, dx;
321  	u64 si, di, bp, sp;
322  	u64 r8,  r9,  r10, r11;
323  	u64 r12, r13, r14, r15;
324  	u64 status, dla, dse, lat;
325  };
326  
327  /*
328   * Same as pebs_record_nhm, with two additional fields.
329   */
330  struct pebs_record_hsw {
331  	u64 flags, ip;
332  	u64 ax, bx, cx, dx;
333  	u64 si, di, bp, sp;
334  	u64 r8,  r9,  r10, r11;
335  	u64 r12, r13, r14, r15;
336  	u64 status, dla, dse, lat;
337  	u64 real_ip, tsx_tuning;
338  };
339  
340  union hsw_tsx_tuning {
341  	struct {
342  		u32 cycles_last_block     : 32,
343  		    hle_abort		  : 1,
344  		    rtm_abort		  : 1,
345  		    instruction_abort     : 1,
346  		    non_instruction_abort : 1,
347  		    retry		  : 1,
348  		    data_conflict	  : 1,
349  		    capacity_writes	  : 1,
350  		    capacity_reads	  : 1;
351  	};
352  	u64	    value;
353  };
354  
355  #define PEBS_HSW_TSX_FLAGS	0xff00000000ULL
356  
357  /* Same as HSW, plus TSC */
358  
359  struct pebs_record_skl {
360  	u64 flags, ip;
361  	u64 ax, bx, cx, dx;
362  	u64 si, di, bp, sp;
363  	u64 r8,  r9,  r10, r11;
364  	u64 r12, r13, r14, r15;
365  	u64 status, dla, dse, lat;
366  	u64 real_ip, tsx_tuning;
367  	u64 tsc;
368  };
369  
370  void init_debug_store_on_cpu(int cpu)
371  {
372  	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
373  
374  	if (!ds)
375  		return;
376  
377  	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
378  		     (u32)((u64)(unsigned long)ds),
379  		     (u32)((u64)(unsigned long)ds >> 32));
380  }
381  
382  void fini_debug_store_on_cpu(int cpu)
383  {
384  	if (!per_cpu(cpu_hw_events, cpu).ds)
385  		return;
386  
387  	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
388  }
389  
390  static DEFINE_PER_CPU(void *, insn_buffer);
391  
392  static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
393  {
394  	unsigned long start = (unsigned long)cea;
395  	phys_addr_t pa;
396  	size_t msz = 0;
397  
398  	pa = virt_to_phys(addr);
399  
400  	preempt_disable();
401  	for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
402  		cea_set_pte(cea, pa, prot);
403  
404  	/*
405  	 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
406  	 * all TLB entries for it.
407  	 */
408  	flush_tlb_kernel_range(start, start + size);
409  	preempt_enable();
410  }
411  
412  static void ds_clear_cea(void *cea, size_t size)
413  {
414  	unsigned long start = (unsigned long)cea;
415  	size_t msz = 0;
416  
417  	preempt_disable();
418  	for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
419  		cea_set_pte(cea, 0, PAGE_NONE);
420  
421  	flush_tlb_kernel_range(start, start + size);
422  	preempt_enable();
423  }
424  
425  static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
426  {
427  	unsigned int order = get_order(size);
428  	int node = cpu_to_node(cpu);
429  	struct page *page;
430  
431  	page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
432  	return page ? page_address(page) : NULL;
433  }
434  
435  static void dsfree_pages(const void *buffer, size_t size)
436  {
437  	if (buffer)
438  		free_pages((unsigned long)buffer, get_order(size));
439  }
440  
441  static int alloc_pebs_buffer(int cpu)
442  {
443  	struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
444  	struct debug_store *ds = hwev->ds;
445  	size_t bsiz = x86_pmu.pebs_buffer_size;
446  	int max, node = cpu_to_node(cpu);
447  	void *buffer, *insn_buff, *cea;
448  
449  	if (!x86_pmu.pebs)
450  		return 0;
451  
452  	buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
453  	if (unlikely(!buffer))
454  		return -ENOMEM;
455  
456  	/*
457  	 * HSW+ already provides us the eventing ip; no need to allocate this
458  	 * buffer then.
459  	 */
460  	if (x86_pmu.intel_cap.pebs_format < 2) {
461  		insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
462  		if (!insn_buff) {
463  			dsfree_pages(buffer, bsiz);
464  			return -ENOMEM;
465  		}
466  		per_cpu(insn_buffer, cpu) = insn_buff;
467  	}
468  	hwev->ds_pebs_vaddr = buffer;
469  	/* Update the cpu entry area mapping */
470  	cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
471  	ds->pebs_buffer_base = (unsigned long) cea;
472  	ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
473  	ds->pebs_index = ds->pebs_buffer_base;
474  	max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
475  	ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
476  	return 0;
477  }
478  
479  static void release_pebs_buffer(int cpu)
480  {
481  	struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
482  	void *cea;
483  
484  	if (!x86_pmu.pebs)
485  		return;
486  
487  	kfree(per_cpu(insn_buffer, cpu));
488  	per_cpu(insn_buffer, cpu) = NULL;
489  
490  	/* Clear the fixmap */
491  	cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
492  	ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
493  	dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
494  	hwev->ds_pebs_vaddr = NULL;
495  }
496  
497  static int alloc_bts_buffer(int cpu)
498  {
499  	struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
500  	struct debug_store *ds = hwev->ds;
501  	void *buffer, *cea;
502  	int max;
503  
504  	if (!x86_pmu.bts)
505  		return 0;
506  
507  	buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
508  	if (unlikely(!buffer)) {
509  		WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
510  		return -ENOMEM;
511  	}
512  	hwev->ds_bts_vaddr = buffer;
513  	/* Update the fixmap */
514  	cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
515  	ds->bts_buffer_base = (unsigned long) cea;
516  	ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
517  	ds->bts_index = ds->bts_buffer_base;
518  	max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
519  	ds->bts_absolute_maximum = ds->bts_buffer_base +
520  					max * BTS_RECORD_SIZE;
521  	ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
522  					(max / 16) * BTS_RECORD_SIZE;
523  	return 0;
524  }
525  
526  static void release_bts_buffer(int cpu)
527  {
528  	struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
529  	void *cea;
530  
531  	if (!x86_pmu.bts)
532  		return;
533  
534  	/* Clear the fixmap */
535  	cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
536  	ds_clear_cea(cea, BTS_BUFFER_SIZE);
537  	dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
538  	hwev->ds_bts_vaddr = NULL;
539  }
540  
541  static int alloc_ds_buffer(int cpu)
542  {
543  	struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
544  
545  	memset(ds, 0, sizeof(*ds));
546  	per_cpu(cpu_hw_events, cpu).ds = ds;
547  	return 0;
548  }
549  
550  static void release_ds_buffer(int cpu)
551  {
552  	per_cpu(cpu_hw_events, cpu).ds = NULL;
553  }
554  
555  void release_ds_buffers(void)
556  {
557  	int cpu;
558  
559  	if (!x86_pmu.bts && !x86_pmu.pebs)
560  		return;
561  
562  	for_each_possible_cpu(cpu)
563  		release_ds_buffer(cpu);
564  
565  	for_each_possible_cpu(cpu) {
566  		/*
567  		 * Again, ignore errors from offline CPUs, they will no longer
568  		 * observe cpu_hw_events.ds and not program the DS_AREA when
569  		 * they come up.
570  		 */
571  		fini_debug_store_on_cpu(cpu);
572  	}
573  
574  	for_each_possible_cpu(cpu) {
575  		release_pebs_buffer(cpu);
576  		release_bts_buffer(cpu);
577  	}
578  }
579  
580  void reserve_ds_buffers(void)
581  {
582  	int bts_err = 0, pebs_err = 0;
583  	int cpu;
584  
585  	x86_pmu.bts_active = 0;
586  	x86_pmu.pebs_active = 0;
587  
588  	if (!x86_pmu.bts && !x86_pmu.pebs)
589  		return;
590  
591  	if (!x86_pmu.bts)
592  		bts_err = 1;
593  
594  	if (!x86_pmu.pebs)
595  		pebs_err = 1;
596  
597  	for_each_possible_cpu(cpu) {
598  		if (alloc_ds_buffer(cpu)) {
599  			bts_err = 1;
600  			pebs_err = 1;
601  		}
602  
603  		if (!bts_err && alloc_bts_buffer(cpu))
604  			bts_err = 1;
605  
606  		if (!pebs_err && alloc_pebs_buffer(cpu))
607  			pebs_err = 1;
608  
609  		if (bts_err && pebs_err)
610  			break;
611  	}
612  
613  	if (bts_err) {
614  		for_each_possible_cpu(cpu)
615  			release_bts_buffer(cpu);
616  	}
617  
618  	if (pebs_err) {
619  		for_each_possible_cpu(cpu)
620  			release_pebs_buffer(cpu);
621  	}
622  
623  	if (bts_err && pebs_err) {
624  		for_each_possible_cpu(cpu)
625  			release_ds_buffer(cpu);
626  	} else {
627  		if (x86_pmu.bts && !bts_err)
628  			x86_pmu.bts_active = 1;
629  
630  		if (x86_pmu.pebs && !pebs_err)
631  			x86_pmu.pebs_active = 1;
632  
633  		for_each_possible_cpu(cpu) {
634  			/*
635  			 * Ignores wrmsr_on_cpu() errors for offline CPUs they
636  			 * will get this call through intel_pmu_cpu_starting().
637  			 */
638  			init_debug_store_on_cpu(cpu);
639  		}
640  	}
641  }
642  
643  /*
644   * BTS
645   */
646  
647  struct event_constraint bts_constraint =
648  	EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
649  
650  void intel_pmu_enable_bts(u64 config)
651  {
652  	unsigned long debugctlmsr;
653  
654  	debugctlmsr = get_debugctlmsr();
655  
656  	debugctlmsr |= DEBUGCTLMSR_TR;
657  	debugctlmsr |= DEBUGCTLMSR_BTS;
658  	if (config & ARCH_PERFMON_EVENTSEL_INT)
659  		debugctlmsr |= DEBUGCTLMSR_BTINT;
660  
661  	if (!(config & ARCH_PERFMON_EVENTSEL_OS))
662  		debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
663  
664  	if (!(config & ARCH_PERFMON_EVENTSEL_USR))
665  		debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
666  
667  	update_debugctlmsr(debugctlmsr);
668  }
669  
670  void intel_pmu_disable_bts(void)
671  {
672  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
673  	unsigned long debugctlmsr;
674  
675  	if (!cpuc->ds)
676  		return;
677  
678  	debugctlmsr = get_debugctlmsr();
679  
680  	debugctlmsr &=
681  		~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
682  		  DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
683  
684  	update_debugctlmsr(debugctlmsr);
685  }
686  
687  int intel_pmu_drain_bts_buffer(void)
688  {
689  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
690  	struct debug_store *ds = cpuc->ds;
691  	struct bts_record {
692  		u64	from;
693  		u64	to;
694  		u64	flags;
695  	};
696  	struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
697  	struct bts_record *at, *base, *top;
698  	struct perf_output_handle handle;
699  	struct perf_event_header header;
700  	struct perf_sample_data data;
701  	unsigned long skip = 0;
702  	struct pt_regs regs;
703  
704  	if (!event)
705  		return 0;
706  
707  	if (!x86_pmu.bts_active)
708  		return 0;
709  
710  	base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
711  	top  = (struct bts_record *)(unsigned long)ds->bts_index;
712  
713  	if (top <= base)
714  		return 0;
715  
716  	memset(&regs, 0, sizeof(regs));
717  
718  	ds->bts_index = ds->bts_buffer_base;
719  
720  	perf_sample_data_init(&data, 0, event->hw.last_period);
721  
722  	/*
723  	 * BTS leaks kernel addresses in branches across the cpl boundary,
724  	 * such as traps or system calls, so unless the user is asking for
725  	 * kernel tracing (and right now it's not possible), we'd need to
726  	 * filter them out. But first we need to count how many of those we
727  	 * have in the current batch. This is an extra O(n) pass, however,
728  	 * it's much faster than the other one especially considering that
729  	 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
730  	 * alloc_bts_buffer()).
731  	 */
732  	for (at = base; at < top; at++) {
733  		/*
734  		 * Note that right now *this* BTS code only works if
735  		 * attr::exclude_kernel is set, but let's keep this extra
736  		 * check here in case that changes.
737  		 */
738  		if (event->attr.exclude_kernel &&
739  		    (kernel_ip(at->from) || kernel_ip(at->to)))
740  			skip++;
741  	}
742  
743  	/*
744  	 * Prepare a generic sample, i.e. fill in the invariant fields.
745  	 * We will overwrite the from and to address before we output
746  	 * the sample.
747  	 */
748  	rcu_read_lock();
749  	perf_prepare_sample(&header, &data, event, &regs);
750  
751  	if (perf_output_begin(&handle, &data, event,
752  			      header.size * (top - base - skip)))
753  		goto unlock;
754  
755  	for (at = base; at < top; at++) {
756  		/* Filter out any records that contain kernel addresses. */
757  		if (event->attr.exclude_kernel &&
758  		    (kernel_ip(at->from) || kernel_ip(at->to)))
759  			continue;
760  
761  		data.ip		= at->from;
762  		data.addr	= at->to;
763  
764  		perf_output_sample(&handle, &header, &data, event);
765  	}
766  
767  	perf_output_end(&handle);
768  
769  	/* There's new data available. */
770  	event->hw.interrupts++;
771  	event->pending_kill = POLL_IN;
772  unlock:
773  	rcu_read_unlock();
774  	return 1;
775  }
776  
777  static inline void intel_pmu_drain_pebs_buffer(void)
778  {
779  	struct perf_sample_data data;
780  
781  	x86_pmu.drain_pebs(NULL, &data);
782  }
783  
784  /*
785   * PEBS
786   */
787  struct event_constraint intel_core2_pebs_event_constraints[] = {
788  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
789  	INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
790  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
791  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
792  	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
793  	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
794  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
795  	EVENT_CONSTRAINT_END
796  };
797  
798  struct event_constraint intel_atom_pebs_event_constraints[] = {
799  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
800  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
801  	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
802  	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
803  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
804  	/* Allow all events as PEBS with no flags */
805  	INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
806  	EVENT_CONSTRAINT_END
807  };
808  
809  struct event_constraint intel_slm_pebs_event_constraints[] = {
810  	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
811  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
812  	/* Allow all events as PEBS with no flags */
813  	INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
814  	EVENT_CONSTRAINT_END
815  };
816  
817  struct event_constraint intel_glm_pebs_event_constraints[] = {
818  	/* Allow all events as PEBS with no flags */
819  	INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
820  	EVENT_CONSTRAINT_END
821  };
822  
823  struct event_constraint intel_grt_pebs_event_constraints[] = {
824  	/* Allow all events as PEBS with no flags */
825  	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xf),
826  	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
827  	EVENT_CONSTRAINT_END
828  };
829  
830  struct event_constraint intel_nehalem_pebs_event_constraints[] = {
831  	INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
832  	INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
833  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
834  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
835  	INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
836  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
837  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
838  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
839  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
840  	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
841  	INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
842  	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
843  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
844  	EVENT_CONSTRAINT_END
845  };
846  
847  struct event_constraint intel_westmere_pebs_event_constraints[] = {
848  	INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
849  	INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
850  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
851  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
852  	INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
853  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
854  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
855  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
856  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
857  	INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
858  	INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
859  	/* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
860  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
861  	EVENT_CONSTRAINT_END
862  };
863  
864  struct event_constraint intel_snb_pebs_event_constraints[] = {
865  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
866  	INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
867  	INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
868  	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
869  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
870          INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
871          INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
872          INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
873          INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
874  	/* Allow all events as PEBS with no flags */
875  	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
876  	EVENT_CONSTRAINT_END
877  };
878  
879  struct event_constraint intel_ivb_pebs_event_constraints[] = {
880          INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
881          INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
882  	INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
883  	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
884  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
885  	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
886  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
887  	INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
888  	INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
889  	INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
890  	INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
891  	/* Allow all events as PEBS with no flags */
892  	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
893          EVENT_CONSTRAINT_END
894  };
895  
896  struct event_constraint intel_hsw_pebs_event_constraints[] = {
897  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
898  	INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
899  	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
900  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
901  	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
902  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
903  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
904  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
905  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
906  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
907  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
908  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
909  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
910  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
911  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
912  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
913  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
914  	/* Allow all events as PEBS with no flags */
915  	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
916  	EVENT_CONSTRAINT_END
917  };
918  
919  struct event_constraint intel_bdw_pebs_event_constraints[] = {
920  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
921  	INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
922  	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
923  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
924  	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
925  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
926  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
927  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
928  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
929  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
930  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
931  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
932  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
933  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
934  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
935  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
936  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
937  	/* Allow all events as PEBS with no flags */
938  	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
939  	EVENT_CONSTRAINT_END
940  };
941  
942  
943  struct event_constraint intel_skl_pebs_event_constraints[] = {
944  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),	/* INST_RETIRED.PREC_DIST */
945  	/* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
946  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
947  	/* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
948  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
949  	INTEL_PLD_CONSTRAINT(0x1cd, 0xf),		      /* MEM_TRANS_RETIRED.* */
950  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
951  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
952  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
953  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
954  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
955  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
956  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
957  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
958  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
959  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
960  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
961  	/* Allow all events as PEBS with no flags */
962  	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
963  	EVENT_CONSTRAINT_END
964  };
965  
966  struct event_constraint intel_icl_pebs_event_constraints[] = {
967  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL),	/* old INST_RETIRED.PREC_DIST */
968  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
969  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),	/* SLOTS */
970  
971  	INTEL_PLD_CONSTRAINT(0x1cd, 0xff),			/* MEM_TRANS_RETIRED.LOAD_LATENCY */
972  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),	/* MEM_INST_RETIRED.LOAD */
973  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x2d0, 0xf),	/* MEM_INST_RETIRED.STORE */
974  
975  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
976  
977  	INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),		/* MEM_INST_RETIRED.* */
978  
979  	/*
980  	 * Everything else is handled by PMU_FL_PEBS_ALL, because we
981  	 * need the full constraints from the main table.
982  	 */
983  
984  	EVENT_CONSTRAINT_END
985  };
986  
987  struct event_constraint intel_spr_pebs_event_constraints[] = {
988  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
989  	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
990  
991  	INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
992  	INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
993  	INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
994  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),
995  	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x2d0, 0xf),
996  
997  	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
998  
999  	INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1000  
1001  	/*
1002  	 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1003  	 * need the full constraints from the main table.
1004  	 */
1005  
1006  	EVENT_CONSTRAINT_END
1007  };
1008  
1009  struct event_constraint *intel_pebs_constraints(struct perf_event *event)
1010  {
1011  	struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
1012  	struct event_constraint *c;
1013  
1014  	if (!event->attr.precise_ip)
1015  		return NULL;
1016  
1017  	if (pebs_constraints) {
1018  		for_each_event_constraint(c, pebs_constraints) {
1019  			if (constraint_match(c, event->hw.config)) {
1020  				event->hw.flags |= c->flags;
1021  				return c;
1022  			}
1023  		}
1024  	}
1025  
1026  	/*
1027  	 * Extended PEBS support
1028  	 * Makes the PEBS code search the normal constraints.
1029  	 */
1030  	if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1031  		return NULL;
1032  
1033  	return &emptyconstraint;
1034  }
1035  
1036  /*
1037   * We need the sched_task callback even for per-cpu events when we use
1038   * the large interrupt threshold, such that we can provide PID and TID
1039   * to PEBS samples.
1040   */
1041  static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
1042  {
1043  	if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
1044  		return false;
1045  
1046  	return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
1047  }
1048  
1049  void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
1050  {
1051  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1052  
1053  	if (!sched_in && pebs_needs_sched_cb(cpuc))
1054  		intel_pmu_drain_pebs_buffer();
1055  }
1056  
1057  static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
1058  {
1059  	struct debug_store *ds = cpuc->ds;
1060  	int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
1061  	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1062  	u64 threshold;
1063  	int reserved;
1064  
1065  	if (cpuc->n_pebs_via_pt)
1066  		return;
1067  
1068  	if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1069  		reserved = max_pebs_events + num_counters_fixed;
1070  	else
1071  		reserved = max_pebs_events;
1072  
1073  	if (cpuc->n_pebs == cpuc->n_large_pebs) {
1074  		threshold = ds->pebs_absolute_maximum -
1075  			reserved * cpuc->pebs_record_size;
1076  	} else {
1077  		threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
1078  	}
1079  
1080  	ds->pebs_interrupt_threshold = threshold;
1081  }
1082  
1083  static void adaptive_pebs_record_size_update(void)
1084  {
1085  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1086  	u64 pebs_data_cfg = cpuc->pebs_data_cfg;
1087  	int sz = sizeof(struct pebs_basic);
1088  
1089  	if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
1090  		sz += sizeof(struct pebs_meminfo);
1091  	if (pebs_data_cfg & PEBS_DATACFG_GP)
1092  		sz += sizeof(struct pebs_gprs);
1093  	if (pebs_data_cfg & PEBS_DATACFG_XMMS)
1094  		sz += sizeof(struct pebs_xmm);
1095  	if (pebs_data_cfg & PEBS_DATACFG_LBRS)
1096  		sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1097  
1098  	cpuc->pebs_record_size = sz;
1099  }
1100  
1101  #define PERF_PEBS_MEMINFO_TYPE	(PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC |   \
1102  				PERF_SAMPLE_PHYS_ADDR |			     \
1103  				PERF_SAMPLE_WEIGHT_TYPE |		     \
1104  				PERF_SAMPLE_TRANSACTION |		     \
1105  				PERF_SAMPLE_DATA_PAGE_SIZE)
1106  
1107  static u64 pebs_update_adaptive_cfg(struct perf_event *event)
1108  {
1109  	struct perf_event_attr *attr = &event->attr;
1110  	u64 sample_type = attr->sample_type;
1111  	u64 pebs_data_cfg = 0;
1112  	bool gprs, tsx_weight;
1113  
1114  	if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
1115  	    attr->precise_ip > 1)
1116  		return pebs_data_cfg;
1117  
1118  	if (sample_type & PERF_PEBS_MEMINFO_TYPE)
1119  		pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
1120  
1121  	/*
1122  	 * We need GPRs when:
1123  	 * + user requested them
1124  	 * + precise_ip < 2 for the non event IP
1125  	 * + For RTM TSX weight we need GPRs for the abort code.
1126  	 */
1127  	gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
1128  	       (attr->sample_regs_intr & PEBS_GP_REGS);
1129  
1130  	tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
1131  		     ((attr->config & INTEL_ARCH_EVENT_MASK) ==
1132  		      x86_pmu.rtm_abort_event);
1133  
1134  	if (gprs || (attr->precise_ip < 2) || tsx_weight)
1135  		pebs_data_cfg |= PEBS_DATACFG_GP;
1136  
1137  	if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
1138  	    (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1139  		pebs_data_cfg |= PEBS_DATACFG_XMMS;
1140  
1141  	if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1142  		/*
1143  		 * For now always log all LBRs. Could configure this
1144  		 * later.
1145  		 */
1146  		pebs_data_cfg |= PEBS_DATACFG_LBRS |
1147  			((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1148  	}
1149  
1150  	return pebs_data_cfg;
1151  }
1152  
1153  static void
1154  pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1155  		  struct perf_event *event, bool add)
1156  {
1157  	struct pmu *pmu = event->ctx->pmu;
1158  	/*
1159  	 * Make sure we get updated with the first PEBS
1160  	 * event. It will trigger also during removal, but
1161  	 * that does not hurt:
1162  	 */
1163  	bool update = cpuc->n_pebs == 1;
1164  
1165  	if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1166  		if (!needed_cb)
1167  			perf_sched_cb_inc(pmu);
1168  		else
1169  			perf_sched_cb_dec(pmu);
1170  
1171  		update = true;
1172  	}
1173  
1174  	/*
1175  	 * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1176  	 * iterating all remaining PEBS events to reconstruct the config.
1177  	 */
1178  	if (x86_pmu.intel_cap.pebs_baseline && add) {
1179  		u64 pebs_data_cfg;
1180  
1181  		/* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1182  		if (cpuc->n_pebs == 1) {
1183  			cpuc->pebs_data_cfg = 0;
1184  			cpuc->pebs_record_size = sizeof(struct pebs_basic);
1185  		}
1186  
1187  		pebs_data_cfg = pebs_update_adaptive_cfg(event);
1188  
1189  		/* Update pebs_record_size if new event requires more data. */
1190  		if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1191  			cpuc->pebs_data_cfg |= pebs_data_cfg;
1192  			adaptive_pebs_record_size_update();
1193  			update = true;
1194  		}
1195  	}
1196  
1197  	if (update)
1198  		pebs_update_threshold(cpuc);
1199  }
1200  
1201  void intel_pmu_pebs_add(struct perf_event *event)
1202  {
1203  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1204  	struct hw_perf_event *hwc = &event->hw;
1205  	bool needed_cb = pebs_needs_sched_cb(cpuc);
1206  
1207  	cpuc->n_pebs++;
1208  	if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1209  		cpuc->n_large_pebs++;
1210  	if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1211  		cpuc->n_pebs_via_pt++;
1212  
1213  	pebs_update_state(needed_cb, cpuc, event, true);
1214  }
1215  
1216  static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1217  {
1218  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1219  
1220  	if (!is_pebs_pt(event))
1221  		return;
1222  
1223  	if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1224  		cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1225  }
1226  
1227  static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1228  {
1229  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1230  	struct hw_perf_event *hwc = &event->hw;
1231  	struct debug_store *ds = cpuc->ds;
1232  	u64 value = ds->pebs_event_reset[hwc->idx];
1233  	u32 base = MSR_RELOAD_PMC0;
1234  	unsigned int idx = hwc->idx;
1235  
1236  	if (!is_pebs_pt(event))
1237  		return;
1238  
1239  	if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1240  		cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1241  
1242  	cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1243  
1244  	if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1245  		base = MSR_RELOAD_FIXED_CTR0;
1246  		idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1247  		if (x86_pmu.intel_cap.pebs_format < 5)
1248  			value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
1249  		else
1250  			value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
1251  	}
1252  	wrmsrl(base + idx, value);
1253  }
1254  
1255  void intel_pmu_pebs_enable(struct perf_event *event)
1256  {
1257  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1258  	struct hw_perf_event *hwc = &event->hw;
1259  	struct debug_store *ds = cpuc->ds;
1260  	unsigned int idx = hwc->idx;
1261  
1262  	hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1263  
1264  	cpuc->pebs_enabled |= 1ULL << hwc->idx;
1265  
1266  	if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1267  		cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1268  	else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1269  		cpuc->pebs_enabled |= 1ULL << 63;
1270  
1271  	if (x86_pmu.intel_cap.pebs_baseline) {
1272  		hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1273  		if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1274  			wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1275  			cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1276  		}
1277  	}
1278  
1279  	if (idx >= INTEL_PMC_IDX_FIXED) {
1280  		if (x86_pmu.intel_cap.pebs_format < 5)
1281  			idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
1282  		else
1283  			idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1284  	}
1285  
1286  	/*
1287  	 * Use auto-reload if possible to save a MSR write in the PMI.
1288  	 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1289  	 */
1290  	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1291  		ds->pebs_event_reset[idx] =
1292  			(u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1293  	} else {
1294  		ds->pebs_event_reset[idx] = 0;
1295  	}
1296  
1297  	intel_pmu_pebs_via_pt_enable(event);
1298  }
1299  
1300  void intel_pmu_pebs_del(struct perf_event *event)
1301  {
1302  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1303  	struct hw_perf_event *hwc = &event->hw;
1304  	bool needed_cb = pebs_needs_sched_cb(cpuc);
1305  
1306  	cpuc->n_pebs--;
1307  	if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1308  		cpuc->n_large_pebs--;
1309  	if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1310  		cpuc->n_pebs_via_pt--;
1311  
1312  	pebs_update_state(needed_cb, cpuc, event, false);
1313  }
1314  
1315  void intel_pmu_pebs_disable(struct perf_event *event)
1316  {
1317  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1318  	struct hw_perf_event *hwc = &event->hw;
1319  
1320  	if (cpuc->n_pebs == cpuc->n_large_pebs &&
1321  	    cpuc->n_pebs != cpuc->n_pebs_via_pt)
1322  		intel_pmu_drain_pebs_buffer();
1323  
1324  	cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1325  
1326  	if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1327  	    (x86_pmu.version < 5))
1328  		cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1329  	else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1330  		cpuc->pebs_enabled &= ~(1ULL << 63);
1331  
1332  	intel_pmu_pebs_via_pt_disable(event);
1333  
1334  	if (cpuc->enabled)
1335  		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1336  
1337  	hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1338  }
1339  
1340  void intel_pmu_pebs_enable_all(void)
1341  {
1342  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1343  
1344  	if (cpuc->pebs_enabled)
1345  		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1346  }
1347  
1348  void intel_pmu_pebs_disable_all(void)
1349  {
1350  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1351  
1352  	if (cpuc->pebs_enabled)
1353  		__intel_pmu_pebs_disable_all();
1354  }
1355  
1356  static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1357  {
1358  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1359  	unsigned long from = cpuc->lbr_entries[0].from;
1360  	unsigned long old_to, to = cpuc->lbr_entries[0].to;
1361  	unsigned long ip = regs->ip;
1362  	int is_64bit = 0;
1363  	void *kaddr;
1364  	int size;
1365  
1366  	/*
1367  	 * We don't need to fixup if the PEBS assist is fault like
1368  	 */
1369  	if (!x86_pmu.intel_cap.pebs_trap)
1370  		return 1;
1371  
1372  	/*
1373  	 * No LBR entry, no basic block, no rewinding
1374  	 */
1375  	if (!cpuc->lbr_stack.nr || !from || !to)
1376  		return 0;
1377  
1378  	/*
1379  	 * Basic blocks should never cross user/kernel boundaries
1380  	 */
1381  	if (kernel_ip(ip) != kernel_ip(to))
1382  		return 0;
1383  
1384  	/*
1385  	 * unsigned math, either ip is before the start (impossible) or
1386  	 * the basic block is larger than 1 page (sanity)
1387  	 */
1388  	if ((ip - to) > PEBS_FIXUP_SIZE)
1389  		return 0;
1390  
1391  	/*
1392  	 * We sampled a branch insn, rewind using the LBR stack
1393  	 */
1394  	if (ip == to) {
1395  		set_linear_ip(regs, from);
1396  		return 1;
1397  	}
1398  
1399  	size = ip - to;
1400  	if (!kernel_ip(ip)) {
1401  		int bytes;
1402  		u8 *buf = this_cpu_read(insn_buffer);
1403  
1404  		/* 'size' must fit our buffer, see above */
1405  		bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1406  		if (bytes != 0)
1407  			return 0;
1408  
1409  		kaddr = buf;
1410  	} else {
1411  		kaddr = (void *)to;
1412  	}
1413  
1414  	do {
1415  		struct insn insn;
1416  
1417  		old_to = to;
1418  
1419  #ifdef CONFIG_X86_64
1420  		is_64bit = kernel_ip(to) || any_64bit_mode(regs);
1421  #endif
1422  		insn_init(&insn, kaddr, size, is_64bit);
1423  
1424  		/*
1425  		 * Make sure there was not a problem decoding the instruction.
1426  		 * This is doubly important because we have an infinite loop if
1427  		 * insn.length=0.
1428  		 */
1429  		if (insn_get_length(&insn))
1430  			break;
1431  
1432  		to += insn.length;
1433  		kaddr += insn.length;
1434  		size -= insn.length;
1435  	} while (to < ip);
1436  
1437  	if (to == ip) {
1438  		set_linear_ip(regs, old_to);
1439  		return 1;
1440  	}
1441  
1442  	/*
1443  	 * Even though we decoded the basic block, the instruction stream
1444  	 * never matched the given IP, either the TO or the IP got corrupted.
1445  	 */
1446  	return 0;
1447  }
1448  
1449  static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1450  {
1451  	if (tsx_tuning) {
1452  		union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1453  		return tsx.cycles_last_block;
1454  	}
1455  	return 0;
1456  }
1457  
1458  static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1459  {
1460  	u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1461  
1462  	/* For RTM XABORTs also log the abort code from AX */
1463  	if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1464  		txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1465  	return txn;
1466  }
1467  
1468  static inline u64 get_pebs_status(void *n)
1469  {
1470  	if (x86_pmu.intel_cap.pebs_format < 4)
1471  		return ((struct pebs_record_nhm *)n)->status;
1472  	return ((struct pebs_basic *)n)->applicable_counters;
1473  }
1474  
1475  #define PERF_X86_EVENT_PEBS_HSW_PREC \
1476  		(PERF_X86_EVENT_PEBS_ST_HSW | \
1477  		 PERF_X86_EVENT_PEBS_LD_HSW | \
1478  		 PERF_X86_EVENT_PEBS_NA_HSW)
1479  
1480  static u64 get_data_src(struct perf_event *event, u64 aux)
1481  {
1482  	u64 val = PERF_MEM_NA;
1483  	int fl = event->hw.flags;
1484  	bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1485  
1486  	if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1487  		val = load_latency_data(event, aux);
1488  	else if (fl & PERF_X86_EVENT_PEBS_STLAT)
1489  		val = store_latency_data(event, aux);
1490  	else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID)
1491  		val = x86_pmu.pebs_latency_data(event, aux);
1492  	else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1493  		val = precise_datala_hsw(event, aux);
1494  	else if (fst)
1495  		val = precise_store_data(aux);
1496  	return val;
1497  }
1498  
1499  #define PERF_SAMPLE_ADDR_TYPE	(PERF_SAMPLE_ADDR |		\
1500  				 PERF_SAMPLE_PHYS_ADDR |	\
1501  				 PERF_SAMPLE_DATA_PAGE_SIZE)
1502  
1503  static void setup_pebs_fixed_sample_data(struct perf_event *event,
1504  				   struct pt_regs *iregs, void *__pebs,
1505  				   struct perf_sample_data *data,
1506  				   struct pt_regs *regs)
1507  {
1508  	/*
1509  	 * We cast to the biggest pebs_record but are careful not to
1510  	 * unconditionally access the 'extra' entries.
1511  	 */
1512  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1513  	struct pebs_record_skl *pebs = __pebs;
1514  	u64 sample_type;
1515  	int fll;
1516  
1517  	if (pebs == NULL)
1518  		return;
1519  
1520  	sample_type = event->attr.sample_type;
1521  	fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1522  
1523  	perf_sample_data_init(data, 0, event->hw.last_period);
1524  
1525  	data->period = event->hw.last_period;
1526  
1527  	/*
1528  	 * Use latency for weight (only avail with PEBS-LL)
1529  	 */
1530  	if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE))
1531  		data->weight.full = pebs->lat;
1532  
1533  	/*
1534  	 * data.data_src encodes the data source
1535  	 */
1536  	if (sample_type & PERF_SAMPLE_DATA_SRC)
1537  		data->data_src.val = get_data_src(event, pebs->dse);
1538  
1539  	/*
1540  	 * We must however always use iregs for the unwinder to stay sane; the
1541  	 * record BP,SP,IP can point into thin air when the record is from a
1542  	 * previous PMI context or an (I)RET happened between the record and
1543  	 * PMI.
1544  	 */
1545  	if (sample_type & PERF_SAMPLE_CALLCHAIN)
1546  		data->callchain = perf_callchain(event, iregs);
1547  
1548  	/*
1549  	 * We use the interrupt regs as a base because the PEBS record does not
1550  	 * contain a full regs set, specifically it seems to lack segment
1551  	 * descriptors, which get used by things like user_mode().
1552  	 *
1553  	 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1554  	 */
1555  	*regs = *iregs;
1556  
1557  	/*
1558  	 * Initialize regs_>flags from PEBS,
1559  	 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1560  	 * i.e., do not rely on it being zero:
1561  	 */
1562  	regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1563  
1564  	if (sample_type & PERF_SAMPLE_REGS_INTR) {
1565  		regs->ax = pebs->ax;
1566  		regs->bx = pebs->bx;
1567  		regs->cx = pebs->cx;
1568  		regs->dx = pebs->dx;
1569  		regs->si = pebs->si;
1570  		regs->di = pebs->di;
1571  
1572  		regs->bp = pebs->bp;
1573  		regs->sp = pebs->sp;
1574  
1575  #ifndef CONFIG_X86_32
1576  		regs->r8 = pebs->r8;
1577  		regs->r9 = pebs->r9;
1578  		regs->r10 = pebs->r10;
1579  		regs->r11 = pebs->r11;
1580  		regs->r12 = pebs->r12;
1581  		regs->r13 = pebs->r13;
1582  		regs->r14 = pebs->r14;
1583  		regs->r15 = pebs->r15;
1584  #endif
1585  	}
1586  
1587  	if (event->attr.precise_ip > 1) {
1588  		/*
1589  		 * Haswell and later processors have an 'eventing IP'
1590  		 * (real IP) which fixes the off-by-1 skid in hardware.
1591  		 * Use it when precise_ip >= 2 :
1592  		 */
1593  		if (x86_pmu.intel_cap.pebs_format >= 2) {
1594  			set_linear_ip(regs, pebs->real_ip);
1595  			regs->flags |= PERF_EFLAGS_EXACT;
1596  		} else {
1597  			/* Otherwise, use PEBS off-by-1 IP: */
1598  			set_linear_ip(regs, pebs->ip);
1599  
1600  			/*
1601  			 * With precise_ip >= 2, try to fix up the off-by-1 IP
1602  			 * using the LBR. If successful, the fixup function
1603  			 * corrects regs->ip and calls set_linear_ip() on regs:
1604  			 */
1605  			if (intel_pmu_pebs_fixup_ip(regs))
1606  				regs->flags |= PERF_EFLAGS_EXACT;
1607  		}
1608  	} else {
1609  		/*
1610  		 * When precise_ip == 1, return the PEBS off-by-1 IP,
1611  		 * no fixup attempted:
1612  		 */
1613  		set_linear_ip(regs, pebs->ip);
1614  	}
1615  
1616  
1617  	if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
1618  	    x86_pmu.intel_cap.pebs_format >= 1)
1619  		data->addr = pebs->dla;
1620  
1621  	if (x86_pmu.intel_cap.pebs_format >= 2) {
1622  		/* Only set the TSX weight when no memory weight. */
1623  		if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll)
1624  			data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
1625  
1626  		if (sample_type & PERF_SAMPLE_TRANSACTION)
1627  			data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1628  							      pebs->ax);
1629  	}
1630  
1631  	/*
1632  	 * v3 supplies an accurate time stamp, so we use that
1633  	 * for the time stamp.
1634  	 *
1635  	 * We can only do this for the default trace clock.
1636  	 */
1637  	if (x86_pmu.intel_cap.pebs_format >= 3 &&
1638  		event->attr.use_clockid == 0)
1639  		data->time = native_sched_clock_from_tsc(pebs->tsc);
1640  
1641  	if (has_branch_stack(event))
1642  		data->br_stack = &cpuc->lbr_stack;
1643  }
1644  
1645  static void adaptive_pebs_save_regs(struct pt_regs *regs,
1646  				    struct pebs_gprs *gprs)
1647  {
1648  	regs->ax = gprs->ax;
1649  	regs->bx = gprs->bx;
1650  	regs->cx = gprs->cx;
1651  	regs->dx = gprs->dx;
1652  	regs->si = gprs->si;
1653  	regs->di = gprs->di;
1654  	regs->bp = gprs->bp;
1655  	regs->sp = gprs->sp;
1656  #ifndef CONFIG_X86_32
1657  	regs->r8 = gprs->r8;
1658  	regs->r9 = gprs->r9;
1659  	regs->r10 = gprs->r10;
1660  	regs->r11 = gprs->r11;
1661  	regs->r12 = gprs->r12;
1662  	regs->r13 = gprs->r13;
1663  	regs->r14 = gprs->r14;
1664  	regs->r15 = gprs->r15;
1665  #endif
1666  }
1667  
1668  #define PEBS_LATENCY_MASK			0xffff
1669  #define PEBS_CACHE_LATENCY_OFFSET		32
1670  
1671  /*
1672   * With adaptive PEBS the layout depends on what fields are configured.
1673   */
1674  
1675  static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1676  					    struct pt_regs *iregs, void *__pebs,
1677  					    struct perf_sample_data *data,
1678  					    struct pt_regs *regs)
1679  {
1680  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1681  	struct pebs_basic *basic = __pebs;
1682  	void *next_record = basic + 1;
1683  	u64 sample_type;
1684  	u64 format_size;
1685  	struct pebs_meminfo *meminfo = NULL;
1686  	struct pebs_gprs *gprs = NULL;
1687  	struct x86_perf_regs *perf_regs;
1688  
1689  	if (basic == NULL)
1690  		return;
1691  
1692  	perf_regs = container_of(regs, struct x86_perf_regs, regs);
1693  	perf_regs->xmm_regs = NULL;
1694  
1695  	sample_type = event->attr.sample_type;
1696  	format_size = basic->format_size;
1697  	perf_sample_data_init(data, 0, event->hw.last_period);
1698  	data->period = event->hw.last_period;
1699  
1700  	if (event->attr.use_clockid == 0)
1701  		data->time = native_sched_clock_from_tsc(basic->tsc);
1702  
1703  	/*
1704  	 * We must however always use iregs for the unwinder to stay sane; the
1705  	 * record BP,SP,IP can point into thin air when the record is from a
1706  	 * previous PMI context or an (I)RET happened between the record and
1707  	 * PMI.
1708  	 */
1709  	if (sample_type & PERF_SAMPLE_CALLCHAIN)
1710  		data->callchain = perf_callchain(event, iregs);
1711  
1712  	*regs = *iregs;
1713  	/* The ip in basic is EventingIP */
1714  	set_linear_ip(regs, basic->ip);
1715  	regs->flags = PERF_EFLAGS_EXACT;
1716  
1717  	/*
1718  	 * The record for MEMINFO is in front of GP
1719  	 * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1720  	 * Save the pointer here but process later.
1721  	 */
1722  	if (format_size & PEBS_DATACFG_MEMINFO) {
1723  		meminfo = next_record;
1724  		next_record = meminfo + 1;
1725  	}
1726  
1727  	if (format_size & PEBS_DATACFG_GP) {
1728  		gprs = next_record;
1729  		next_record = gprs + 1;
1730  
1731  		if (event->attr.precise_ip < 2) {
1732  			set_linear_ip(regs, gprs->ip);
1733  			regs->flags &= ~PERF_EFLAGS_EXACT;
1734  		}
1735  
1736  		if (sample_type & PERF_SAMPLE_REGS_INTR)
1737  			adaptive_pebs_save_regs(regs, gprs);
1738  	}
1739  
1740  	if (format_size & PEBS_DATACFG_MEMINFO) {
1741  		if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1742  			u64 weight = meminfo->latency;
1743  
1744  			if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) {
1745  				data->weight.var2_w = weight & PEBS_LATENCY_MASK;
1746  				weight >>= PEBS_CACHE_LATENCY_OFFSET;
1747  			}
1748  
1749  			/*
1750  			 * Although meminfo::latency is defined as a u64,
1751  			 * only the lower 32 bits include the valid data
1752  			 * in practice on Ice Lake and earlier platforms.
1753  			 */
1754  			if (sample_type & PERF_SAMPLE_WEIGHT) {
1755  				data->weight.full = weight ?:
1756  					intel_get_tsx_weight(meminfo->tsx_tuning);
1757  			} else {
1758  				data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?:
1759  					intel_get_tsx_weight(meminfo->tsx_tuning);
1760  			}
1761  		}
1762  
1763  		if (sample_type & PERF_SAMPLE_DATA_SRC)
1764  			data->data_src.val = get_data_src(event, meminfo->aux);
1765  
1766  		if (sample_type & PERF_SAMPLE_ADDR_TYPE)
1767  			data->addr = meminfo->address;
1768  
1769  		if (sample_type & PERF_SAMPLE_TRANSACTION)
1770  			data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
1771  							  gprs ? gprs->ax : 0);
1772  	}
1773  
1774  	if (format_size & PEBS_DATACFG_XMMS) {
1775  		struct pebs_xmm *xmm = next_record;
1776  
1777  		next_record = xmm + 1;
1778  		perf_regs->xmm_regs = xmm->xmm;
1779  	}
1780  
1781  	if (format_size & PEBS_DATACFG_LBRS) {
1782  		struct lbr_entry *lbr = next_record;
1783  		int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
1784  					& 0xff) + 1;
1785  		next_record = next_record + num_lbr * sizeof(struct lbr_entry);
1786  
1787  		if (has_branch_stack(event)) {
1788  			intel_pmu_store_pebs_lbrs(lbr);
1789  			data->br_stack = &cpuc->lbr_stack;
1790  		}
1791  	}
1792  
1793  	WARN_ONCE(next_record != __pebs + (format_size >> 48),
1794  			"PEBS record size %llu, expected %llu, config %llx\n",
1795  			format_size >> 48,
1796  			(u64)(next_record - __pebs),
1797  			basic->format_size);
1798  }
1799  
1800  static inline void *
1801  get_next_pebs_record_by_bit(void *base, void *top, int bit)
1802  {
1803  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1804  	void *at;
1805  	u64 pebs_status;
1806  
1807  	/*
1808  	 * fmt0 does not have a status bitfield (does not use
1809  	 * perf_record_nhm format)
1810  	 */
1811  	if (x86_pmu.intel_cap.pebs_format < 1)
1812  		return base;
1813  
1814  	if (base == NULL)
1815  		return NULL;
1816  
1817  	for (at = base; at < top; at += cpuc->pebs_record_size) {
1818  		unsigned long status = get_pebs_status(at);
1819  
1820  		if (test_bit(bit, (unsigned long *)&status)) {
1821  			/* PEBS v3 has accurate status bits */
1822  			if (x86_pmu.intel_cap.pebs_format >= 3)
1823  				return at;
1824  
1825  			if (status == (1 << bit))
1826  				return at;
1827  
1828  			/* clear non-PEBS bit and re-check */
1829  			pebs_status = status & cpuc->pebs_enabled;
1830  			pebs_status &= PEBS_COUNTER_MASK;
1831  			if (pebs_status == (1 << bit))
1832  				return at;
1833  		}
1834  	}
1835  	return NULL;
1836  }
1837  
1838  void intel_pmu_auto_reload_read(struct perf_event *event)
1839  {
1840  	WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
1841  
1842  	perf_pmu_disable(event->pmu);
1843  	intel_pmu_drain_pebs_buffer();
1844  	perf_pmu_enable(event->pmu);
1845  }
1846  
1847  /*
1848   * Special variant of intel_pmu_save_and_restart() for auto-reload.
1849   */
1850  static int
1851  intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1852  {
1853  	struct hw_perf_event *hwc = &event->hw;
1854  	int shift = 64 - x86_pmu.cntval_bits;
1855  	u64 period = hwc->sample_period;
1856  	u64 prev_raw_count, new_raw_count;
1857  	s64 new, old;
1858  
1859  	WARN_ON(!period);
1860  
1861  	/*
1862  	 * drain_pebs() only happens when the PMU is disabled.
1863  	 */
1864  	WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1865  
1866  	prev_raw_count = local64_read(&hwc->prev_count);
1867  	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1868  	local64_set(&hwc->prev_count, new_raw_count);
1869  
1870  	/*
1871  	 * Since the counter increments a negative counter value and
1872  	 * overflows on the sign switch, giving the interval:
1873  	 *
1874  	 *   [-period, 0]
1875  	 *
1876  	 * the difference between two consecutive reads is:
1877  	 *
1878  	 *   A) value2 - value1;
1879  	 *      when no overflows have happened in between,
1880  	 *
1881  	 *   B) (0 - value1) + (value2 - (-period));
1882  	 *      when one overflow happened in between,
1883  	 *
1884  	 *   C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1885  	 *      when @n overflows happened in between.
1886  	 *
1887  	 * Here A) is the obvious difference, B) is the extension to the
1888  	 * discrete interval, where the first term is to the top of the
1889  	 * interval and the second term is from the bottom of the next
1890  	 * interval and C) the extension to multiple intervals, where the
1891  	 * middle term is the whole intervals covered.
1892  	 *
1893  	 * An equivalent of C, by reduction, is:
1894  	 *
1895  	 *   value2 - value1 + n * period
1896  	 */
1897  	new = ((s64)(new_raw_count << shift) >> shift);
1898  	old = ((s64)(prev_raw_count << shift) >> shift);
1899  	local64_add(new - old + count * period, &event->count);
1900  
1901  	local64_set(&hwc->period_left, -new);
1902  
1903  	perf_event_update_userpage(event);
1904  
1905  	return 0;
1906  }
1907  
1908  static __always_inline void
1909  __intel_pmu_pebs_event(struct perf_event *event,
1910  		       struct pt_regs *iregs,
1911  		       struct perf_sample_data *data,
1912  		       void *base, void *top,
1913  		       int bit, int count,
1914  		       void (*setup_sample)(struct perf_event *,
1915  					    struct pt_regs *,
1916  					    void *,
1917  					    struct perf_sample_data *,
1918  					    struct pt_regs *))
1919  {
1920  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1921  	struct hw_perf_event *hwc = &event->hw;
1922  	struct x86_perf_regs perf_regs;
1923  	struct pt_regs *regs = &perf_regs.regs;
1924  	void *at = get_next_pebs_record_by_bit(base, top, bit);
1925  	static struct pt_regs dummy_iregs;
1926  
1927  	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1928  		/*
1929  		 * Now, auto-reload is only enabled in fixed period mode.
1930  		 * The reload value is always hwc->sample_period.
1931  		 * May need to change it, if auto-reload is enabled in
1932  		 * freq mode later.
1933  		 */
1934  		intel_pmu_save_and_restart_reload(event, count);
1935  	} else if (!intel_pmu_save_and_restart(event))
1936  		return;
1937  
1938  	if (!iregs)
1939  		iregs = &dummy_iregs;
1940  
1941  	while (count > 1) {
1942  		setup_sample(event, iregs, at, data, regs);
1943  		perf_event_output(event, data, regs);
1944  		at += cpuc->pebs_record_size;
1945  		at = get_next_pebs_record_by_bit(at, top, bit);
1946  		count--;
1947  	}
1948  
1949  	setup_sample(event, iregs, at, data, regs);
1950  	if (iregs == &dummy_iregs) {
1951  		/*
1952  		 * The PEBS records may be drained in the non-overflow context,
1953  		 * e.g., large PEBS + context switch. Perf should treat the
1954  		 * last record the same as other PEBS records, and doesn't
1955  		 * invoke the generic overflow handler.
1956  		 */
1957  		perf_event_output(event, data, regs);
1958  	} else {
1959  		/*
1960  		 * All but the last records are processed.
1961  		 * The last one is left to be able to call the overflow handler.
1962  		 */
1963  		if (perf_event_overflow(event, data, regs))
1964  			x86_pmu_stop(event, 0);
1965  	}
1966  }
1967  
1968  static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
1969  {
1970  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1971  	struct debug_store *ds = cpuc->ds;
1972  	struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1973  	struct pebs_record_core *at, *top;
1974  	int n;
1975  
1976  	if (!x86_pmu.pebs_active)
1977  		return;
1978  
1979  	at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1980  	top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1981  
1982  	/*
1983  	 * Whatever else happens, drain the thing
1984  	 */
1985  	ds->pebs_index = ds->pebs_buffer_base;
1986  
1987  	if (!test_bit(0, cpuc->active_mask))
1988  		return;
1989  
1990  	WARN_ON_ONCE(!event);
1991  
1992  	if (!event->attr.precise_ip)
1993  		return;
1994  
1995  	n = top - at;
1996  	if (n <= 0) {
1997  		if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1998  			intel_pmu_save_and_restart_reload(event, 0);
1999  		return;
2000  	}
2001  
2002  	__intel_pmu_pebs_event(event, iregs, data, at, top, 0, n,
2003  			       setup_pebs_fixed_sample_data);
2004  }
2005  
2006  static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
2007  {
2008  	struct perf_event *event;
2009  	int bit;
2010  
2011  	/*
2012  	 * The drain_pebs() could be called twice in a short period
2013  	 * for auto-reload event in pmu::read(). There are no
2014  	 * overflows have happened in between.
2015  	 * It needs to call intel_pmu_save_and_restart_reload() to
2016  	 * update the event->count for this case.
2017  	 */
2018  	for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
2019  		event = cpuc->events[bit];
2020  		if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2021  			intel_pmu_save_and_restart_reload(event, 0);
2022  	}
2023  }
2024  
2025  static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
2026  {
2027  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2028  	struct debug_store *ds = cpuc->ds;
2029  	struct perf_event *event;
2030  	void *base, *at, *top;
2031  	short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2032  	short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2033  	int bit, i, size;
2034  	u64 mask;
2035  
2036  	if (!x86_pmu.pebs_active)
2037  		return;
2038  
2039  	base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
2040  	top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
2041  
2042  	ds->pebs_index = ds->pebs_buffer_base;
2043  
2044  	mask = (1ULL << x86_pmu.max_pebs_events) - 1;
2045  	size = x86_pmu.max_pebs_events;
2046  	if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
2047  		mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
2048  		size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
2049  	}
2050  
2051  	if (unlikely(base >= top)) {
2052  		intel_pmu_pebs_event_update_no_drain(cpuc, size);
2053  		return;
2054  	}
2055  
2056  	for (at = base; at < top; at += x86_pmu.pebs_record_size) {
2057  		struct pebs_record_nhm *p = at;
2058  		u64 pebs_status;
2059  
2060  		pebs_status = p->status & cpuc->pebs_enabled;
2061  		pebs_status &= mask;
2062  
2063  		/* PEBS v3 has more accurate status bits */
2064  		if (x86_pmu.intel_cap.pebs_format >= 3) {
2065  			for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2066  				counts[bit]++;
2067  
2068  			continue;
2069  		}
2070  
2071  		/*
2072  		 * On some CPUs the PEBS status can be zero when PEBS is
2073  		 * racing with clearing of GLOBAL_STATUS.
2074  		 *
2075  		 * Normally we would drop that record, but in the
2076  		 * case when there is only a single active PEBS event
2077  		 * we can assume it's for that event.
2078  		 */
2079  		if (!pebs_status && cpuc->pebs_enabled &&
2080  			!(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
2081  			pebs_status = p->status = cpuc->pebs_enabled;
2082  
2083  		bit = find_first_bit((unsigned long *)&pebs_status,
2084  					x86_pmu.max_pebs_events);
2085  		if (bit >= x86_pmu.max_pebs_events)
2086  			continue;
2087  
2088  		/*
2089  		 * The PEBS hardware does not deal well with the situation
2090  		 * when events happen near to each other and multiple bits
2091  		 * are set. But it should happen rarely.
2092  		 *
2093  		 * If these events include one PEBS and multiple non-PEBS
2094  		 * events, it doesn't impact PEBS record. The record will
2095  		 * be handled normally. (slow path)
2096  		 *
2097  		 * If these events include two or more PEBS events, the
2098  		 * records for the events can be collapsed into a single
2099  		 * one, and it's not possible to reconstruct all events
2100  		 * that caused the PEBS record. It's called collision.
2101  		 * If collision happened, the record will be dropped.
2102  		 */
2103  		if (pebs_status != (1ULL << bit)) {
2104  			for_each_set_bit(i, (unsigned long *)&pebs_status, size)
2105  				error[i]++;
2106  			continue;
2107  		}
2108  
2109  		counts[bit]++;
2110  	}
2111  
2112  	for_each_set_bit(bit, (unsigned long *)&mask, size) {
2113  		if ((counts[bit] == 0) && (error[bit] == 0))
2114  			continue;
2115  
2116  		event = cpuc->events[bit];
2117  		if (WARN_ON_ONCE(!event))
2118  			continue;
2119  
2120  		if (WARN_ON_ONCE(!event->attr.precise_ip))
2121  			continue;
2122  
2123  		/* log dropped samples number */
2124  		if (error[bit]) {
2125  			perf_log_lost_samples(event, error[bit]);
2126  
2127  			if (iregs && perf_event_account_interrupt(event))
2128  				x86_pmu_stop(event, 0);
2129  		}
2130  
2131  		if (counts[bit]) {
2132  			__intel_pmu_pebs_event(event, iregs, data, base,
2133  					       top, bit, counts[bit],
2134  					       setup_pebs_fixed_sample_data);
2135  		}
2136  	}
2137  }
2138  
2139  static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
2140  {
2141  	short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2142  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2143  	int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
2144  	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2145  	struct debug_store *ds = cpuc->ds;
2146  	struct perf_event *event;
2147  	void *base, *at, *top;
2148  	int bit, size;
2149  	u64 mask;
2150  
2151  	if (!x86_pmu.pebs_active)
2152  		return;
2153  
2154  	base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
2155  	top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
2156  
2157  	ds->pebs_index = ds->pebs_buffer_base;
2158  
2159  	mask = ((1ULL << max_pebs_events) - 1) |
2160  	       (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
2161  	size = INTEL_PMC_IDX_FIXED + num_counters_fixed;
2162  
2163  	if (unlikely(base >= top)) {
2164  		intel_pmu_pebs_event_update_no_drain(cpuc, size);
2165  		return;
2166  	}
2167  
2168  	for (at = base; at < top; at += cpuc->pebs_record_size) {
2169  		u64 pebs_status;
2170  
2171  		pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
2172  		pebs_status &= mask;
2173  
2174  		for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2175  			counts[bit]++;
2176  	}
2177  
2178  	for_each_set_bit(bit, (unsigned long *)&mask, size) {
2179  		if (counts[bit] == 0)
2180  			continue;
2181  
2182  		event = cpuc->events[bit];
2183  		if (WARN_ON_ONCE(!event))
2184  			continue;
2185  
2186  		if (WARN_ON_ONCE(!event->attr.precise_ip))
2187  			continue;
2188  
2189  		__intel_pmu_pebs_event(event, iregs, data, base,
2190  				       top, bit, counts[bit],
2191  				       setup_pebs_adaptive_sample_data);
2192  	}
2193  }
2194  
2195  /*
2196   * BTS, PEBS probe and setup
2197   */
2198  
2199  void __init intel_ds_init(void)
2200  {
2201  	/*
2202  	 * No support for 32bit formats
2203  	 */
2204  	if (!boot_cpu_has(X86_FEATURE_DTES64))
2205  		return;
2206  
2207  	x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
2208  	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2209  	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2210  	if (x86_pmu.version <= 4)
2211  		x86_pmu.pebs_no_isolation = 1;
2212  
2213  	if (x86_pmu.pebs) {
2214  		char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
2215  		char *pebs_qual = "";
2216  		int format = x86_pmu.intel_cap.pebs_format;
2217  
2218  		if (format < 4)
2219  			x86_pmu.intel_cap.pebs_baseline = 0;
2220  
2221  		switch (format) {
2222  		case 0:
2223  			pr_cont("PEBS fmt0%c, ", pebs_type);
2224  			x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2225  			/*
2226  			 * Using >PAGE_SIZE buffers makes the WRMSR to
2227  			 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2228  			 * mysteriously hang on Core2.
2229  			 *
2230  			 * As a workaround, we don't do this.
2231  			 */
2232  			x86_pmu.pebs_buffer_size = PAGE_SIZE;
2233  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2234  			break;
2235  
2236  		case 1:
2237  			pr_cont("PEBS fmt1%c, ", pebs_type);
2238  			x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2239  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2240  			break;
2241  
2242  		case 2:
2243  			pr_cont("PEBS fmt2%c, ", pebs_type);
2244  			x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2245  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2246  			break;
2247  
2248  		case 3:
2249  			pr_cont("PEBS fmt3%c, ", pebs_type);
2250  			x86_pmu.pebs_record_size =
2251  						sizeof(struct pebs_record_skl);
2252  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2253  			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2254  			break;
2255  
2256  		case 4:
2257  		case 5:
2258  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2259  			x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2260  			if (x86_pmu.intel_cap.pebs_baseline) {
2261  				x86_pmu.large_pebs_flags |=
2262  					PERF_SAMPLE_BRANCH_STACK |
2263  					PERF_SAMPLE_TIME;
2264  				x86_pmu.flags |= PMU_FL_PEBS_ALL;
2265  				pebs_qual = "-baseline";
2266  				x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2267  			} else {
2268  				/* Only basic record supported */
2269  				x86_pmu.large_pebs_flags &=
2270  					~(PERF_SAMPLE_ADDR |
2271  					  PERF_SAMPLE_TIME |
2272  					  PERF_SAMPLE_DATA_SRC |
2273  					  PERF_SAMPLE_TRANSACTION |
2274  					  PERF_SAMPLE_REGS_USER |
2275  					  PERF_SAMPLE_REGS_INTR);
2276  			}
2277  			pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2278  
2279  			if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) {
2280  				pr_cont("PEBS-via-PT, ");
2281  				x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2282  			}
2283  
2284  			break;
2285  
2286  		default:
2287  			pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2288  			x86_pmu.pebs = 0;
2289  		}
2290  	}
2291  }
2292  
2293  void perf_restore_debug_store(void)
2294  {
2295  	struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2296  
2297  	if (!x86_pmu.bts && !x86_pmu.pebs)
2298  		return;
2299  
2300  	wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2301  }
2302