1 /* 2 * Support cstate residency counters 3 * 4 * Copyright (C) 2015, Intel Corp. 5 * Author: Kan Liang (kan.liang@intel.com) 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Library General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Library General Public License for more details. 16 * 17 */ 18 19 /* 20 * This file export cstate related free running (read-only) counters 21 * for perf. These counters may be use simultaneously by other tools, 22 * such as turbostat. However, it still make sense to implement them 23 * in perf. Because we can conveniently collect them together with 24 * other events, and allow to use them from tools without special MSR 25 * access code. 26 * 27 * The events only support system-wide mode counting. There is no 28 * sampling support because it is not supported by the hardware. 29 * 30 * According to counters' scope and category, two PMUs are registered 31 * with the perf_event core subsystem. 32 * - 'cstate_core': The counter is available for each physical core. 33 * The counters include CORE_C*_RESIDENCY. 34 * - 'cstate_pkg': The counter is available for each physical package. 35 * The counters include PKG_C*_RESIDENCY. 36 * 37 * All of these counters are specified in the Intel® 64 and IA-32 38 * Architectures Software Developer.s Manual Vol3b. 39 * 40 * Model specific counters: 41 * MSR_CORE_C1_RES: CORE C1 Residency Counter 42 * perf code: 0x00 43 * Available model: SLM,AMT,GLM,CNL 44 * Scope: Core (each processor core has a MSR) 45 * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter 46 * perf code: 0x01 47 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, 48 CNL 49 * Scope: Core 50 * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter 51 * perf code: 0x02 52 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, 53 * SKL,KNL,GLM,CNL 54 * Scope: Core 55 * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter 56 * perf code: 0x03 57 * Available model: SNB,IVB,HSW,BDW,SKL,CNL 58 * Scope: Core 59 * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. 60 * perf code: 0x00 61 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL 62 * Scope: Package (physical package) 63 * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. 64 * perf code: 0x01 65 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, 66 * GLM,CNL 67 * Scope: Package (physical package) 68 * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. 69 * perf code: 0x02 70 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW 71 * SKL,KNL,GLM,CNL 72 * Scope: Package (physical package) 73 * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. 74 * perf code: 0x03 75 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL 76 * Scope: Package (physical package) 77 * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. 78 * perf code: 0x04 79 * Available model: HSW ULT,CNL 80 * Scope: Package (physical package) 81 * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. 82 * perf code: 0x05 83 * Available model: HSW ULT,CNL 84 * Scope: Package (physical package) 85 * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. 86 * perf code: 0x06 87 * Available model: HSW ULT,GLM,CNL 88 * Scope: Package (physical package) 89 * 90 */ 91 92 #include <linux/module.h> 93 #include <linux/slab.h> 94 #include <linux/perf_event.h> 95 #include <asm/cpu_device_id.h> 96 #include <asm/intel-family.h> 97 #include "../perf_event.h" 98 99 MODULE_LICENSE("GPL"); 100 101 #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format) \ 102 static ssize_t __cstate_##_var##_show(struct kobject *kobj, \ 103 struct kobj_attribute *attr, \ 104 char *page) \ 105 { \ 106 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ 107 return sprintf(page, _format "\n"); \ 108 } \ 109 static struct kobj_attribute format_attr_##_var = \ 110 __ATTR(_name, 0444, __cstate_##_var##_show, NULL) 111 112 static ssize_t cstate_get_attr_cpumask(struct device *dev, 113 struct device_attribute *attr, 114 char *buf); 115 116 /* Model -> events mapping */ 117 struct cstate_model { 118 unsigned long core_events; 119 unsigned long pkg_events; 120 unsigned long quirks; 121 }; 122 123 /* Quirk flags */ 124 #define SLM_PKG_C6_USE_C7_MSR (1UL << 0) 125 #define KNL_CORE_C6_MSR (1UL << 1) 126 127 struct perf_cstate_msr { 128 u64 msr; 129 struct perf_pmu_events_attr *attr; 130 }; 131 132 133 /* cstate_core PMU */ 134 static struct pmu cstate_core_pmu; 135 static bool has_cstate_core; 136 137 enum perf_cstate_core_events { 138 PERF_CSTATE_CORE_C1_RES = 0, 139 PERF_CSTATE_CORE_C3_RES, 140 PERF_CSTATE_CORE_C6_RES, 141 PERF_CSTATE_CORE_C7_RES, 142 143 PERF_CSTATE_CORE_EVENT_MAX, 144 }; 145 146 PMU_EVENT_ATTR_STRING(c1-residency, evattr_cstate_core_c1, "event=0x00"); 147 PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_core_c3, "event=0x01"); 148 PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_core_c6, "event=0x02"); 149 PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_core_c7, "event=0x03"); 150 151 static struct perf_cstate_msr core_msr[] = { 152 [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES, &evattr_cstate_core_c1 }, 153 [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY, &evattr_cstate_core_c3 }, 154 [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY, &evattr_cstate_core_c6 }, 155 [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY, &evattr_cstate_core_c7 }, 156 }; 157 158 static struct attribute *core_events_attrs[PERF_CSTATE_CORE_EVENT_MAX + 1] = { 159 NULL, 160 }; 161 162 static struct attribute_group core_events_attr_group = { 163 .name = "events", 164 .attrs = core_events_attrs, 165 }; 166 167 DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63"); 168 static struct attribute *core_format_attrs[] = { 169 &format_attr_core_event.attr, 170 NULL, 171 }; 172 173 static struct attribute_group core_format_attr_group = { 174 .name = "format", 175 .attrs = core_format_attrs, 176 }; 177 178 static cpumask_t cstate_core_cpu_mask; 179 static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL); 180 181 static struct attribute *cstate_cpumask_attrs[] = { 182 &dev_attr_cpumask.attr, 183 NULL, 184 }; 185 186 static struct attribute_group cpumask_attr_group = { 187 .attrs = cstate_cpumask_attrs, 188 }; 189 190 static const struct attribute_group *core_attr_groups[] = { 191 &core_events_attr_group, 192 &core_format_attr_group, 193 &cpumask_attr_group, 194 NULL, 195 }; 196 197 /* cstate_pkg PMU */ 198 static struct pmu cstate_pkg_pmu; 199 static bool has_cstate_pkg; 200 201 enum perf_cstate_pkg_events { 202 PERF_CSTATE_PKG_C2_RES = 0, 203 PERF_CSTATE_PKG_C3_RES, 204 PERF_CSTATE_PKG_C6_RES, 205 PERF_CSTATE_PKG_C7_RES, 206 PERF_CSTATE_PKG_C8_RES, 207 PERF_CSTATE_PKG_C9_RES, 208 PERF_CSTATE_PKG_C10_RES, 209 210 PERF_CSTATE_PKG_EVENT_MAX, 211 }; 212 213 PMU_EVENT_ATTR_STRING(c2-residency, evattr_cstate_pkg_c2, "event=0x00"); 214 PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_pkg_c3, "event=0x01"); 215 PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_pkg_c6, "event=0x02"); 216 PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_pkg_c7, "event=0x03"); 217 PMU_EVENT_ATTR_STRING(c8-residency, evattr_cstate_pkg_c8, "event=0x04"); 218 PMU_EVENT_ATTR_STRING(c9-residency, evattr_cstate_pkg_c9, "event=0x05"); 219 PMU_EVENT_ATTR_STRING(c10-residency, evattr_cstate_pkg_c10, "event=0x06"); 220 221 static struct perf_cstate_msr pkg_msr[] = { 222 [PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY, &evattr_cstate_pkg_c2 }, 223 [PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY, &evattr_cstate_pkg_c3 }, 224 [PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY, &evattr_cstate_pkg_c6 }, 225 [PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY, &evattr_cstate_pkg_c7 }, 226 [PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY, &evattr_cstate_pkg_c8 }, 227 [PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY, &evattr_cstate_pkg_c9 }, 228 [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY, &evattr_cstate_pkg_c10 }, 229 }; 230 231 static struct attribute *pkg_events_attrs[PERF_CSTATE_PKG_EVENT_MAX + 1] = { 232 NULL, 233 }; 234 235 static struct attribute_group pkg_events_attr_group = { 236 .name = "events", 237 .attrs = pkg_events_attrs, 238 }; 239 240 DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63"); 241 static struct attribute *pkg_format_attrs[] = { 242 &format_attr_pkg_event.attr, 243 NULL, 244 }; 245 static struct attribute_group pkg_format_attr_group = { 246 .name = "format", 247 .attrs = pkg_format_attrs, 248 }; 249 250 static cpumask_t cstate_pkg_cpu_mask; 251 252 static const struct attribute_group *pkg_attr_groups[] = { 253 &pkg_events_attr_group, 254 &pkg_format_attr_group, 255 &cpumask_attr_group, 256 NULL, 257 }; 258 259 static ssize_t cstate_get_attr_cpumask(struct device *dev, 260 struct device_attribute *attr, 261 char *buf) 262 { 263 struct pmu *pmu = dev_get_drvdata(dev); 264 265 if (pmu == &cstate_core_pmu) 266 return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask); 267 else if (pmu == &cstate_pkg_pmu) 268 return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask); 269 else 270 return 0; 271 } 272 273 static int cstate_pmu_event_init(struct perf_event *event) 274 { 275 u64 cfg = event->attr.config; 276 int cpu; 277 278 if (event->attr.type != event->pmu->type) 279 return -ENOENT; 280 281 /* unsupported modes and filters */ 282 if (event->attr.exclude_user || 283 event->attr.exclude_kernel || 284 event->attr.exclude_hv || 285 event->attr.exclude_idle || 286 event->attr.exclude_host || 287 event->attr.exclude_guest || 288 event->attr.sample_period) /* no sampling */ 289 return -EINVAL; 290 291 if (event->cpu < 0) 292 return -EINVAL; 293 294 if (event->pmu == &cstate_core_pmu) { 295 if (cfg >= PERF_CSTATE_CORE_EVENT_MAX) 296 return -EINVAL; 297 if (!core_msr[cfg].attr) 298 return -EINVAL; 299 event->hw.event_base = core_msr[cfg].msr; 300 cpu = cpumask_any_and(&cstate_core_cpu_mask, 301 topology_sibling_cpumask(event->cpu)); 302 } else if (event->pmu == &cstate_pkg_pmu) { 303 if (cfg >= PERF_CSTATE_PKG_EVENT_MAX) 304 return -EINVAL; 305 if (!pkg_msr[cfg].attr) 306 return -EINVAL; 307 event->hw.event_base = pkg_msr[cfg].msr; 308 cpu = cpumask_any_and(&cstate_pkg_cpu_mask, 309 topology_core_cpumask(event->cpu)); 310 } else { 311 return -ENOENT; 312 } 313 314 if (cpu >= nr_cpu_ids) 315 return -ENODEV; 316 317 event->cpu = cpu; 318 event->hw.config = cfg; 319 event->hw.idx = -1; 320 return 0; 321 } 322 323 static inline u64 cstate_pmu_read_counter(struct perf_event *event) 324 { 325 u64 val; 326 327 rdmsrl(event->hw.event_base, val); 328 return val; 329 } 330 331 static void cstate_pmu_event_update(struct perf_event *event) 332 { 333 struct hw_perf_event *hwc = &event->hw; 334 u64 prev_raw_count, new_raw_count; 335 336 again: 337 prev_raw_count = local64_read(&hwc->prev_count); 338 new_raw_count = cstate_pmu_read_counter(event); 339 340 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 341 new_raw_count) != prev_raw_count) 342 goto again; 343 344 local64_add(new_raw_count - prev_raw_count, &event->count); 345 } 346 347 static void cstate_pmu_event_start(struct perf_event *event, int mode) 348 { 349 local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event)); 350 } 351 352 static void cstate_pmu_event_stop(struct perf_event *event, int mode) 353 { 354 cstate_pmu_event_update(event); 355 } 356 357 static void cstate_pmu_event_del(struct perf_event *event, int mode) 358 { 359 cstate_pmu_event_stop(event, PERF_EF_UPDATE); 360 } 361 362 static int cstate_pmu_event_add(struct perf_event *event, int mode) 363 { 364 if (mode & PERF_EF_START) 365 cstate_pmu_event_start(event, mode); 366 367 return 0; 368 } 369 370 /* 371 * Check if exiting cpu is the designated reader. If so migrate the 372 * events when there is a valid target available 373 */ 374 static int cstate_cpu_exit(unsigned int cpu) 375 { 376 unsigned int target; 377 378 if (has_cstate_core && 379 cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) { 380 381 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu); 382 /* Migrate events if there is a valid target */ 383 if (target < nr_cpu_ids) { 384 cpumask_set_cpu(target, &cstate_core_cpu_mask); 385 perf_pmu_migrate_context(&cstate_core_pmu, cpu, target); 386 } 387 } 388 389 if (has_cstate_pkg && 390 cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) { 391 392 target = cpumask_any_but(topology_core_cpumask(cpu), cpu); 393 /* Migrate events if there is a valid target */ 394 if (target < nr_cpu_ids) { 395 cpumask_set_cpu(target, &cstate_pkg_cpu_mask); 396 perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target); 397 } 398 } 399 return 0; 400 } 401 402 static int cstate_cpu_init(unsigned int cpu) 403 { 404 unsigned int target; 405 406 /* 407 * If this is the first online thread of that core, set it in 408 * the core cpu mask as the designated reader. 409 */ 410 target = cpumask_any_and(&cstate_core_cpu_mask, 411 topology_sibling_cpumask(cpu)); 412 413 if (has_cstate_core && target >= nr_cpu_ids) 414 cpumask_set_cpu(cpu, &cstate_core_cpu_mask); 415 416 /* 417 * If this is the first online thread of that package, set it 418 * in the package cpu mask as the designated reader. 419 */ 420 target = cpumask_any_and(&cstate_pkg_cpu_mask, 421 topology_core_cpumask(cpu)); 422 if (has_cstate_pkg && target >= nr_cpu_ids) 423 cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask); 424 425 return 0; 426 } 427 428 static struct pmu cstate_core_pmu = { 429 .attr_groups = core_attr_groups, 430 .name = "cstate_core", 431 .task_ctx_nr = perf_invalid_context, 432 .event_init = cstate_pmu_event_init, 433 .add = cstate_pmu_event_add, 434 .del = cstate_pmu_event_del, 435 .start = cstate_pmu_event_start, 436 .stop = cstate_pmu_event_stop, 437 .read = cstate_pmu_event_update, 438 .capabilities = PERF_PMU_CAP_NO_INTERRUPT, 439 .module = THIS_MODULE, 440 }; 441 442 static struct pmu cstate_pkg_pmu = { 443 .attr_groups = pkg_attr_groups, 444 .name = "cstate_pkg", 445 .task_ctx_nr = perf_invalid_context, 446 .event_init = cstate_pmu_event_init, 447 .add = cstate_pmu_event_add, 448 .del = cstate_pmu_event_del, 449 .start = cstate_pmu_event_start, 450 .stop = cstate_pmu_event_stop, 451 .read = cstate_pmu_event_update, 452 .capabilities = PERF_PMU_CAP_NO_INTERRUPT, 453 .module = THIS_MODULE, 454 }; 455 456 static const struct cstate_model nhm_cstates __initconst = { 457 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 458 BIT(PERF_CSTATE_CORE_C6_RES), 459 460 .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) | 461 BIT(PERF_CSTATE_PKG_C6_RES) | 462 BIT(PERF_CSTATE_PKG_C7_RES), 463 }; 464 465 static const struct cstate_model snb_cstates __initconst = { 466 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 467 BIT(PERF_CSTATE_CORE_C6_RES) | 468 BIT(PERF_CSTATE_CORE_C7_RES), 469 470 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 471 BIT(PERF_CSTATE_PKG_C3_RES) | 472 BIT(PERF_CSTATE_PKG_C6_RES) | 473 BIT(PERF_CSTATE_PKG_C7_RES), 474 }; 475 476 static const struct cstate_model hswult_cstates __initconst = { 477 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 478 BIT(PERF_CSTATE_CORE_C6_RES) | 479 BIT(PERF_CSTATE_CORE_C7_RES), 480 481 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 482 BIT(PERF_CSTATE_PKG_C3_RES) | 483 BIT(PERF_CSTATE_PKG_C6_RES) | 484 BIT(PERF_CSTATE_PKG_C7_RES) | 485 BIT(PERF_CSTATE_PKG_C8_RES) | 486 BIT(PERF_CSTATE_PKG_C9_RES) | 487 BIT(PERF_CSTATE_PKG_C10_RES), 488 }; 489 490 static const struct cstate_model cnl_cstates __initconst = { 491 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 492 BIT(PERF_CSTATE_CORE_C3_RES) | 493 BIT(PERF_CSTATE_CORE_C6_RES) | 494 BIT(PERF_CSTATE_CORE_C7_RES), 495 496 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 497 BIT(PERF_CSTATE_PKG_C3_RES) | 498 BIT(PERF_CSTATE_PKG_C6_RES) | 499 BIT(PERF_CSTATE_PKG_C7_RES) | 500 BIT(PERF_CSTATE_PKG_C8_RES) | 501 BIT(PERF_CSTATE_PKG_C9_RES) | 502 BIT(PERF_CSTATE_PKG_C10_RES), 503 }; 504 505 static const struct cstate_model slm_cstates __initconst = { 506 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 507 BIT(PERF_CSTATE_CORE_C6_RES), 508 509 .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), 510 .quirks = SLM_PKG_C6_USE_C7_MSR, 511 }; 512 513 514 static const struct cstate_model knl_cstates __initconst = { 515 .core_events = BIT(PERF_CSTATE_CORE_C6_RES), 516 517 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 518 BIT(PERF_CSTATE_PKG_C3_RES) | 519 BIT(PERF_CSTATE_PKG_C6_RES), 520 .quirks = KNL_CORE_C6_MSR, 521 }; 522 523 524 static const struct cstate_model glm_cstates __initconst = { 525 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 526 BIT(PERF_CSTATE_CORE_C3_RES) | 527 BIT(PERF_CSTATE_CORE_C6_RES), 528 529 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 530 BIT(PERF_CSTATE_PKG_C3_RES) | 531 BIT(PERF_CSTATE_PKG_C6_RES) | 532 BIT(PERF_CSTATE_PKG_C10_RES), 533 }; 534 535 536 #define X86_CSTATES_MODEL(model, states) \ 537 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) } 538 539 static const struct x86_cpu_id intel_cstates_match[] __initconst = { 540 X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM, nhm_cstates), 541 X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EP, nhm_cstates), 542 X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EX, nhm_cstates), 543 544 X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE, nhm_cstates), 545 X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EP, nhm_cstates), 546 X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EX, nhm_cstates), 547 548 X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE, snb_cstates), 549 X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE_X, snb_cstates), 550 551 X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE, snb_cstates), 552 X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates), 553 554 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_CORE, snb_cstates), 555 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates), 556 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates), 557 558 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates), 559 560 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT1, slm_cstates), 561 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT2, slm_cstates), 562 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates), 563 564 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE, snb_cstates), 565 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates), 566 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E, snb_cstates), 567 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X, snb_cstates), 568 569 X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE, snb_cstates), 570 X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates), 571 X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates), 572 573 X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates), 574 X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates), 575 576 X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates), 577 578 X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), 579 X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), 580 581 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates), 582 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates), 583 584 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates), 585 { }, 586 }; 587 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); 588 589 /* 590 * Probe the cstate events and insert the available one into sysfs attrs 591 * Return false if there are no available events. 592 */ 593 static bool __init cstate_probe_msr(const unsigned long evmsk, int max, 594 struct perf_cstate_msr *msr, 595 struct attribute **attrs) 596 { 597 bool found = false; 598 unsigned int bit; 599 u64 val; 600 601 for (bit = 0; bit < max; bit++) { 602 if (test_bit(bit, &evmsk) && !rdmsrl_safe(msr[bit].msr, &val)) { 603 *attrs++ = &msr[bit].attr->attr.attr; 604 found = true; 605 } else { 606 msr[bit].attr = NULL; 607 } 608 } 609 *attrs = NULL; 610 611 return found; 612 } 613 614 static int __init cstate_probe(const struct cstate_model *cm) 615 { 616 /* SLM has different MSR for PKG C6 */ 617 if (cm->quirks & SLM_PKG_C6_USE_C7_MSR) 618 pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY; 619 620 /* KNL has different MSR for CORE C6 */ 621 if (cm->quirks & KNL_CORE_C6_MSR) 622 pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY; 623 624 625 has_cstate_core = cstate_probe_msr(cm->core_events, 626 PERF_CSTATE_CORE_EVENT_MAX, 627 core_msr, core_events_attrs); 628 629 has_cstate_pkg = cstate_probe_msr(cm->pkg_events, 630 PERF_CSTATE_PKG_EVENT_MAX, 631 pkg_msr, pkg_events_attrs); 632 633 return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV; 634 } 635 636 static inline void cstate_cleanup(void) 637 { 638 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE); 639 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING); 640 641 if (has_cstate_core) 642 perf_pmu_unregister(&cstate_core_pmu); 643 644 if (has_cstate_pkg) 645 perf_pmu_unregister(&cstate_pkg_pmu); 646 } 647 648 static int __init cstate_init(void) 649 { 650 int err; 651 652 cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING, 653 "perf/x86/cstate:starting", cstate_cpu_init, NULL); 654 cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE, 655 "perf/x86/cstate:online", NULL, cstate_cpu_exit); 656 657 if (has_cstate_core) { 658 err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1); 659 if (err) { 660 has_cstate_core = false; 661 pr_info("Failed to register cstate core pmu\n"); 662 cstate_cleanup(); 663 return err; 664 } 665 } 666 667 if (has_cstate_pkg) { 668 err = perf_pmu_register(&cstate_pkg_pmu, cstate_pkg_pmu.name, -1); 669 if (err) { 670 has_cstate_pkg = false; 671 pr_info("Failed to register cstate pkg pmu\n"); 672 cstate_cleanup(); 673 return err; 674 } 675 } 676 return 0; 677 } 678 679 static int __init cstate_pmu_init(void) 680 { 681 const struct x86_cpu_id *id; 682 int err; 683 684 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 685 return -ENODEV; 686 687 id = x86_match_cpu(intel_cstates_match); 688 if (!id) 689 return -ENODEV; 690 691 err = cstate_probe((const struct cstate_model *) id->driver_data); 692 if (err) 693 return err; 694 695 return cstate_init(); 696 } 697 module_init(cstate_pmu_init); 698 699 static void __exit cstate_pmu_exit(void) 700 { 701 cstate_cleanup(); 702 } 703 module_exit(cstate_pmu_exit); 704