16aec1ad7SBorislav Petkov /* 2940b2f2fSBorislav Petkov * Support cstate residency counters 36aec1ad7SBorislav Petkov * 46aec1ad7SBorislav Petkov * Copyright (C) 2015, Intel Corp. 56aec1ad7SBorislav Petkov * Author: Kan Liang (kan.liang@intel.com) 66aec1ad7SBorislav Petkov * 76aec1ad7SBorislav Petkov * This library is free software; you can redistribute it and/or 86aec1ad7SBorislav Petkov * modify it under the terms of the GNU Library General Public 96aec1ad7SBorislav Petkov * License as published by the Free Software Foundation; either 106aec1ad7SBorislav Petkov * version 2 of the License, or (at your option) any later version. 116aec1ad7SBorislav Petkov * 126aec1ad7SBorislav Petkov * This library is distributed in the hope that it will be useful, 136aec1ad7SBorislav Petkov * but WITHOUT ANY WARRANTY; without even the implied warranty of 146aec1ad7SBorislav Petkov * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 156aec1ad7SBorislav Petkov * Library General Public License for more details. 166aec1ad7SBorislav Petkov * 176aec1ad7SBorislav Petkov */ 186aec1ad7SBorislav Petkov 196aec1ad7SBorislav Petkov /* 206aec1ad7SBorislav Petkov * This file export cstate related free running (read-only) counters 216aec1ad7SBorislav Petkov * for perf. These counters may be use simultaneously by other tools, 226aec1ad7SBorislav Petkov * such as turbostat. However, it still make sense to implement them 236aec1ad7SBorislav Petkov * in perf. Because we can conveniently collect them together with 246aec1ad7SBorislav Petkov * other events, and allow to use them from tools without special MSR 256aec1ad7SBorislav Petkov * access code. 266aec1ad7SBorislav Petkov * 276aec1ad7SBorislav Petkov * The events only support system-wide mode counting. There is no 286aec1ad7SBorislav Petkov * sampling support because it is not supported by the hardware. 296aec1ad7SBorislav Petkov * 306aec1ad7SBorislav Petkov * According to counters' scope and category, two PMUs are registered 316aec1ad7SBorislav Petkov * with the perf_event core subsystem. 326aec1ad7SBorislav Petkov * - 'cstate_core': The counter is available for each physical core. 336aec1ad7SBorislav Petkov * The counters include CORE_C*_RESIDENCY. 346aec1ad7SBorislav Petkov * - 'cstate_pkg': The counter is available for each physical package. 356aec1ad7SBorislav Petkov * The counters include PKG_C*_RESIDENCY. 366aec1ad7SBorislav Petkov * 376aec1ad7SBorislav Petkov * All of these counters are specified in the Intel® 64 and IA-32 386aec1ad7SBorislav Petkov * Architectures Software Developer.s Manual Vol3b. 396aec1ad7SBorislav Petkov * 406aec1ad7SBorislav Petkov * Model specific counters: 416aec1ad7SBorislav Petkov * MSR_CORE_C1_RES: CORE C1 Residency Counter 426aec1ad7SBorislav Petkov * perf code: 0x00 43ecf71fbcSKan Liang * Available model: SLM,AMT,GLM,CNL,TNT 446aec1ad7SBorislav Petkov * Scope: Core (each processor core has a MSR) 456aec1ad7SBorislav Petkov * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter 466aec1ad7SBorislav Petkov * perf code: 0x01 471159e094SHarry Pan * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, 48ecf71fbcSKan Liang * CNL,KBL,CML,TNT 496aec1ad7SBorislav Petkov * Scope: Core 506aec1ad7SBorislav Petkov * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter 516aec1ad7SBorislav Petkov * perf code: 0x02 521159e094SHarry Pan * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, 53ecf71fbcSKan Liang * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, 54ecf71fbcSKan Liang * TNT 556aec1ad7SBorislav Petkov * Scope: Core 566aec1ad7SBorislav Petkov * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter 576aec1ad7SBorislav Petkov * perf code: 0x03 58f1857a24SKan Liang * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, 5952e92f40SKan Liang * ICL,TGL 606aec1ad7SBorislav Petkov * Scope: Core 616aec1ad7SBorislav Petkov * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. 626aec1ad7SBorislav Petkov * perf code: 0x00 631ffa6c04SKan Liang * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, 64ecf71fbcSKan Liang * KBL,CML,ICL,TGL,TNT 656aec1ad7SBorislav Petkov * Scope: Package (physical package) 666aec1ad7SBorislav Petkov * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. 676aec1ad7SBorislav Petkov * perf code: 0x01 681159e094SHarry Pan * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, 69ecf71fbcSKan Liang * GLM,CNL,KBL,CML,ICL,TGL,TNT 706aec1ad7SBorislav Petkov * Scope: Package (physical package) 716aec1ad7SBorislav Petkov * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. 726aec1ad7SBorislav Petkov * perf code: 0x02 73ecf71fbcSKan Liang * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, 74ecf71fbcSKan Liang * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, 75ecf71fbcSKan Liang * TNT 766aec1ad7SBorislav Petkov * Scope: Package (physical package) 776aec1ad7SBorislav Petkov * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. 786aec1ad7SBorislav Petkov * perf code: 0x03 791ffa6c04SKan Liang * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, 8052e92f40SKan Liang * KBL,CML,ICL,TGL 816aec1ad7SBorislav Petkov * Scope: Package (physical package) 826aec1ad7SBorislav Petkov * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. 836aec1ad7SBorislav Petkov * perf code: 0x04 8452e92f40SKan Liang * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL 856aec1ad7SBorislav Petkov * Scope: Package (physical package) 866aec1ad7SBorislav Petkov * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. 876aec1ad7SBorislav Petkov * perf code: 0x05 8852e92f40SKan Liang * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL 896aec1ad7SBorislav Petkov * Scope: Package (physical package) 906aec1ad7SBorislav Petkov * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. 916aec1ad7SBorislav Petkov * perf code: 0x06 92ecf71fbcSKan Liang * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, 93ecf71fbcSKan Liang * TNT 946aec1ad7SBorislav Petkov * Scope: Package (physical package) 956aec1ad7SBorislav Petkov * 966aec1ad7SBorislav Petkov */ 976aec1ad7SBorislav Petkov 986aec1ad7SBorislav Petkov #include <linux/module.h> 996aec1ad7SBorislav Petkov #include <linux/slab.h> 1006aec1ad7SBorislav Petkov #include <linux/perf_event.h> 101a5f81290SPeter Zijlstra #include <linux/nospec.h> 1026aec1ad7SBorislav Petkov #include <asm/cpu_device_id.h> 103bf4ad541SDave Hansen #include <asm/intel-family.h> 10427f6d22bSBorislav Petkov #include "../perf_event.h" 1058f2a28c5SJiri Olsa #include "../probe.h" 1066aec1ad7SBorislav Petkov 107c7afba32SThomas Gleixner MODULE_LICENSE("GPL"); 108c7afba32SThomas Gleixner 1096aec1ad7SBorislav Petkov #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format) \ 1106aec1ad7SBorislav Petkov static ssize_t __cstate_##_var##_show(struct kobject *kobj, \ 1116aec1ad7SBorislav Petkov struct kobj_attribute *attr, \ 1126aec1ad7SBorislav Petkov char *page) \ 1136aec1ad7SBorislav Petkov { \ 1146aec1ad7SBorislav Petkov BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ 1156aec1ad7SBorislav Petkov return sprintf(page, _format "\n"); \ 1166aec1ad7SBorislav Petkov } \ 1176aec1ad7SBorislav Petkov static struct kobj_attribute format_attr_##_var = \ 1186aec1ad7SBorislav Petkov __ATTR(_name, 0444, __cstate_##_var##_show, NULL) 1196aec1ad7SBorislav Petkov 1206aec1ad7SBorislav Petkov static ssize_t cstate_get_attr_cpumask(struct device *dev, 1216aec1ad7SBorislav Petkov struct device_attribute *attr, 1226aec1ad7SBorislav Petkov char *buf); 1236aec1ad7SBorislav Petkov 124424646eeSThomas Gleixner /* Model -> events mapping */ 125424646eeSThomas Gleixner struct cstate_model { 126424646eeSThomas Gleixner unsigned long core_events; 127424646eeSThomas Gleixner unsigned long pkg_events; 128424646eeSThomas Gleixner unsigned long quirks; 129424646eeSThomas Gleixner }; 130424646eeSThomas Gleixner 131424646eeSThomas Gleixner /* Quirk flags */ 132424646eeSThomas Gleixner #define SLM_PKG_C6_USE_C7_MSR (1UL << 0) 133889882bcSLukasz Odzioba #define KNL_CORE_C6_MSR (1UL << 1) 134424646eeSThomas Gleixner 1356aec1ad7SBorislav Petkov struct perf_cstate_msr { 1366aec1ad7SBorislav Petkov u64 msr; 1376aec1ad7SBorislav Petkov struct perf_pmu_events_attr *attr; 1386aec1ad7SBorislav Petkov }; 1396aec1ad7SBorislav Petkov 1406aec1ad7SBorislav Petkov 1416aec1ad7SBorislav Petkov /* cstate_core PMU */ 1426aec1ad7SBorislav Petkov static struct pmu cstate_core_pmu; 1436aec1ad7SBorislav Petkov static bool has_cstate_core; 1446aec1ad7SBorislav Petkov 145424646eeSThomas Gleixner enum perf_cstate_core_events { 1466aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C1_RES = 0, 1476aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C3_RES, 1486aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C6_RES, 1496aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C7_RES, 1506aec1ad7SBorislav Petkov 1516aec1ad7SBorislav Petkov PERF_CSTATE_CORE_EVENT_MAX, 1526aec1ad7SBorislav Petkov }; 1536aec1ad7SBorislav Petkov 1548f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00"); 1558f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01"); 1568f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02"); 1578f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_core_c7, "event=0x03"); 1586aec1ad7SBorislav Petkov 1598f2a28c5SJiri Olsa static unsigned long core_msr_mask; 1608f2a28c5SJiri Olsa 1618f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c1); 1628f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c3); 1638f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c6); 1648f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c7); 1658f2a28c5SJiri Olsa 1668f2a28c5SJiri Olsa static bool test_msr(int idx, void *data) 1678f2a28c5SJiri Olsa { 1688f2a28c5SJiri Olsa return test_bit(idx, (unsigned long *) data); 1698f2a28c5SJiri Olsa } 1708f2a28c5SJiri Olsa 1718f2a28c5SJiri Olsa static struct perf_msr core_msr[] = { 1728f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES, &group_cstate_core_c1, test_msr }, 1738f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY, &group_cstate_core_c3, test_msr }, 1748f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY, &group_cstate_core_c6, test_msr }, 1758f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY, &group_cstate_core_c7, test_msr }, 1766aec1ad7SBorislav Petkov }; 1776aec1ad7SBorislav Petkov 1788f2a28c5SJiri Olsa static struct attribute *attrs_empty[] = { 1796aec1ad7SBorislav Petkov NULL, 1806aec1ad7SBorislav Petkov }; 1816aec1ad7SBorislav Petkov 1828f2a28c5SJiri Olsa /* 1838f2a28c5SJiri Olsa * There are no default events, but we need to create 1848f2a28c5SJiri Olsa * "events" group (with empty attrs) before updating 1858f2a28c5SJiri Olsa * it with detected events. 1868f2a28c5SJiri Olsa */ 1876aec1ad7SBorislav Petkov static struct attribute_group core_events_attr_group = { 1886aec1ad7SBorislav Petkov .name = "events", 1898f2a28c5SJiri Olsa .attrs = attrs_empty, 1906aec1ad7SBorislav Petkov }; 1916aec1ad7SBorislav Petkov 1926aec1ad7SBorislav Petkov DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63"); 1936aec1ad7SBorislav Petkov static struct attribute *core_format_attrs[] = { 1946aec1ad7SBorislav Petkov &format_attr_core_event.attr, 1956aec1ad7SBorislav Petkov NULL, 1966aec1ad7SBorislav Petkov }; 1976aec1ad7SBorislav Petkov 1986aec1ad7SBorislav Petkov static struct attribute_group core_format_attr_group = { 1996aec1ad7SBorislav Petkov .name = "format", 2006aec1ad7SBorislav Petkov .attrs = core_format_attrs, 2016aec1ad7SBorislav Petkov }; 2026aec1ad7SBorislav Petkov 2036aec1ad7SBorislav Petkov static cpumask_t cstate_core_cpu_mask; 2046aec1ad7SBorislav Petkov static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL); 2056aec1ad7SBorislav Petkov 2066aec1ad7SBorislav Petkov static struct attribute *cstate_cpumask_attrs[] = { 2076aec1ad7SBorislav Petkov &dev_attr_cpumask.attr, 2086aec1ad7SBorislav Petkov NULL, 2096aec1ad7SBorislav Petkov }; 2106aec1ad7SBorislav Petkov 2116aec1ad7SBorislav Petkov static struct attribute_group cpumask_attr_group = { 2126aec1ad7SBorislav Petkov .attrs = cstate_cpumask_attrs, 2136aec1ad7SBorislav Petkov }; 2146aec1ad7SBorislav Petkov 2156aec1ad7SBorislav Petkov static const struct attribute_group *core_attr_groups[] = { 2166aec1ad7SBorislav Petkov &core_events_attr_group, 2176aec1ad7SBorislav Petkov &core_format_attr_group, 2186aec1ad7SBorislav Petkov &cpumask_attr_group, 2196aec1ad7SBorislav Petkov NULL, 2206aec1ad7SBorislav Petkov }; 2216aec1ad7SBorislav Petkov 2226aec1ad7SBorislav Petkov /* cstate_pkg PMU */ 2236aec1ad7SBorislav Petkov static struct pmu cstate_pkg_pmu; 2246aec1ad7SBorislav Petkov static bool has_cstate_pkg; 2256aec1ad7SBorislav Petkov 226424646eeSThomas Gleixner enum perf_cstate_pkg_events { 2276aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C2_RES = 0, 2286aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C3_RES, 2296aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C6_RES, 2306aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C7_RES, 2316aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C8_RES, 2326aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C9_RES, 2336aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C10_RES, 2346aec1ad7SBorislav Petkov 2356aec1ad7SBorislav Petkov PERF_CSTATE_PKG_EVENT_MAX, 2366aec1ad7SBorislav Petkov }; 2376aec1ad7SBorislav Petkov 2388f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c2-residency, attr_cstate_pkg_c2, "event=0x00"); 2398f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_pkg_c3, "event=0x01"); 2408f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_pkg_c6, "event=0x02"); 2418f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_pkg_c7, "event=0x03"); 2428f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c8-residency, attr_cstate_pkg_c8, "event=0x04"); 2438f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c9-residency, attr_cstate_pkg_c9, "event=0x05"); 2448f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06"); 2456aec1ad7SBorislav Petkov 2468f2a28c5SJiri Olsa static unsigned long pkg_msr_mask; 2476aec1ad7SBorislav Petkov 2488f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c2); 2498f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c3); 2508f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c6); 2518f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c7); 2528f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c8); 2538f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c9); 2548f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c10); 2558f2a28c5SJiri Olsa 2568f2a28c5SJiri Olsa static struct perf_msr pkg_msr[] = { 2578f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY, &group_cstate_pkg_c2, test_msr }, 2588f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY, &group_cstate_pkg_c3, test_msr }, 2598f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY, &group_cstate_pkg_c6, test_msr }, 2608f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY, &group_cstate_pkg_c7, test_msr }, 2618f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY, &group_cstate_pkg_c8, test_msr }, 2628f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY, &group_cstate_pkg_c9, test_msr }, 2638f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY, &group_cstate_pkg_c10, test_msr }, 2646aec1ad7SBorislav Petkov }; 2656aec1ad7SBorislav Petkov 2666aec1ad7SBorislav Petkov static struct attribute_group pkg_events_attr_group = { 2676aec1ad7SBorislav Petkov .name = "events", 2688f2a28c5SJiri Olsa .attrs = attrs_empty, 2696aec1ad7SBorislav Petkov }; 2706aec1ad7SBorislav Petkov 2716aec1ad7SBorislav Petkov DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63"); 2726aec1ad7SBorislav Petkov static struct attribute *pkg_format_attrs[] = { 2736aec1ad7SBorislav Petkov &format_attr_pkg_event.attr, 2746aec1ad7SBorislav Petkov NULL, 2756aec1ad7SBorislav Petkov }; 2766aec1ad7SBorislav Petkov static struct attribute_group pkg_format_attr_group = { 2776aec1ad7SBorislav Petkov .name = "format", 2786aec1ad7SBorislav Petkov .attrs = pkg_format_attrs, 2796aec1ad7SBorislav Petkov }; 2806aec1ad7SBorislav Petkov 2816aec1ad7SBorislav Petkov static cpumask_t cstate_pkg_cpu_mask; 2826aec1ad7SBorislav Petkov 2836aec1ad7SBorislav Petkov static const struct attribute_group *pkg_attr_groups[] = { 2846aec1ad7SBorislav Petkov &pkg_events_attr_group, 2856aec1ad7SBorislav Petkov &pkg_format_attr_group, 2866aec1ad7SBorislav Petkov &cpumask_attr_group, 2876aec1ad7SBorislav Petkov NULL, 2886aec1ad7SBorislav Petkov }; 2896aec1ad7SBorislav Petkov 2906aec1ad7SBorislav Petkov static ssize_t cstate_get_attr_cpumask(struct device *dev, 2916aec1ad7SBorislav Petkov struct device_attribute *attr, 2926aec1ad7SBorislav Petkov char *buf) 2936aec1ad7SBorislav Petkov { 2946aec1ad7SBorislav Petkov struct pmu *pmu = dev_get_drvdata(dev); 2956aec1ad7SBorislav Petkov 2966aec1ad7SBorislav Petkov if (pmu == &cstate_core_pmu) 2976aec1ad7SBorislav Petkov return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask); 2986aec1ad7SBorislav Petkov else if (pmu == &cstate_pkg_pmu) 2996aec1ad7SBorislav Petkov return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask); 3006aec1ad7SBorislav Petkov else 3016aec1ad7SBorislav Petkov return 0; 3026aec1ad7SBorislav Petkov } 3036aec1ad7SBorislav Petkov 3046aec1ad7SBorislav Petkov static int cstate_pmu_event_init(struct perf_event *event) 3056aec1ad7SBorislav Petkov { 3066aec1ad7SBorislav Petkov u64 cfg = event->attr.config; 30749de0493SThomas Gleixner int cpu; 3086aec1ad7SBorislav Petkov 3096aec1ad7SBorislav Petkov if (event->attr.type != event->pmu->type) 3106aec1ad7SBorislav Petkov return -ENOENT; 3116aec1ad7SBorislav Petkov 3126aec1ad7SBorislav Petkov /* unsupported modes and filters */ 3132ff40250SAndrew Murray if (event->attr.sample_period) /* no sampling */ 3146aec1ad7SBorislav Petkov return -EINVAL; 3156aec1ad7SBorislav Petkov 31649de0493SThomas Gleixner if (event->cpu < 0) 31749de0493SThomas Gleixner return -EINVAL; 31849de0493SThomas Gleixner 3196aec1ad7SBorislav Petkov if (event->pmu == &cstate_core_pmu) { 3206aec1ad7SBorislav Petkov if (cfg >= PERF_CSTATE_CORE_EVENT_MAX) 3216aec1ad7SBorislav Petkov return -EINVAL; 3228f2a28c5SJiri Olsa cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_CORE_EVENT_MAX); 3238f2a28c5SJiri Olsa if (!(core_msr_mask & (1 << cfg))) 3246aec1ad7SBorislav Petkov return -EINVAL; 3256aec1ad7SBorislav Petkov event->hw.event_base = core_msr[cfg].msr; 32649de0493SThomas Gleixner cpu = cpumask_any_and(&cstate_core_cpu_mask, 32749de0493SThomas Gleixner topology_sibling_cpumask(event->cpu)); 3286aec1ad7SBorislav Petkov } else if (event->pmu == &cstate_pkg_pmu) { 3296aec1ad7SBorislav Petkov if (cfg >= PERF_CSTATE_PKG_EVENT_MAX) 3306aec1ad7SBorislav Petkov return -EINVAL; 331a5f81290SPeter Zijlstra cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX); 3328f2a28c5SJiri Olsa if (!(pkg_msr_mask & (1 << cfg))) 3336aec1ad7SBorislav Petkov return -EINVAL; 3346aec1ad7SBorislav Petkov event->hw.event_base = pkg_msr[cfg].msr; 33549de0493SThomas Gleixner cpu = cpumask_any_and(&cstate_pkg_cpu_mask, 336cb63ba0fSKan Liang topology_die_cpumask(event->cpu)); 33749de0493SThomas Gleixner } else { 3386aec1ad7SBorislav Petkov return -ENOENT; 33949de0493SThomas Gleixner } 3406aec1ad7SBorislav Petkov 34149de0493SThomas Gleixner if (cpu >= nr_cpu_ids) 34249de0493SThomas Gleixner return -ENODEV; 34349de0493SThomas Gleixner 34449de0493SThomas Gleixner event->cpu = cpu; 3456aec1ad7SBorislav Petkov event->hw.config = cfg; 3466aec1ad7SBorislav Petkov event->hw.idx = -1; 34749de0493SThomas Gleixner return 0; 3486aec1ad7SBorislav Petkov } 3496aec1ad7SBorislav Petkov 3506aec1ad7SBorislav Petkov static inline u64 cstate_pmu_read_counter(struct perf_event *event) 3516aec1ad7SBorislav Petkov { 3526aec1ad7SBorislav Petkov u64 val; 3536aec1ad7SBorislav Petkov 3546aec1ad7SBorislav Petkov rdmsrl(event->hw.event_base, val); 3556aec1ad7SBorislav Petkov return val; 3566aec1ad7SBorislav Petkov } 3576aec1ad7SBorislav Petkov 3586aec1ad7SBorislav Petkov static void cstate_pmu_event_update(struct perf_event *event) 3596aec1ad7SBorislav Petkov { 3606aec1ad7SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 3616aec1ad7SBorislav Petkov u64 prev_raw_count, new_raw_count; 3626aec1ad7SBorislav Petkov 3636aec1ad7SBorislav Petkov again: 3646aec1ad7SBorislav Petkov prev_raw_count = local64_read(&hwc->prev_count); 3656aec1ad7SBorislav Petkov new_raw_count = cstate_pmu_read_counter(event); 3666aec1ad7SBorislav Petkov 3676aec1ad7SBorislav Petkov if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 3686aec1ad7SBorislav Petkov new_raw_count) != prev_raw_count) 3696aec1ad7SBorislav Petkov goto again; 3706aec1ad7SBorislav Petkov 3716aec1ad7SBorislav Petkov local64_add(new_raw_count - prev_raw_count, &event->count); 3726aec1ad7SBorislav Petkov } 3736aec1ad7SBorislav Petkov 3746aec1ad7SBorislav Petkov static void cstate_pmu_event_start(struct perf_event *event, int mode) 3756aec1ad7SBorislav Petkov { 3766aec1ad7SBorislav Petkov local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event)); 3776aec1ad7SBorislav Petkov } 3786aec1ad7SBorislav Petkov 3796aec1ad7SBorislav Petkov static void cstate_pmu_event_stop(struct perf_event *event, int mode) 3806aec1ad7SBorislav Petkov { 3816aec1ad7SBorislav Petkov cstate_pmu_event_update(event); 3826aec1ad7SBorislav Petkov } 3836aec1ad7SBorislav Petkov 3846aec1ad7SBorislav Petkov static void cstate_pmu_event_del(struct perf_event *event, int mode) 3856aec1ad7SBorislav Petkov { 3866aec1ad7SBorislav Petkov cstate_pmu_event_stop(event, PERF_EF_UPDATE); 3876aec1ad7SBorislav Petkov } 3886aec1ad7SBorislav Petkov 3896aec1ad7SBorislav Petkov static int cstate_pmu_event_add(struct perf_event *event, int mode) 3906aec1ad7SBorislav Petkov { 3916aec1ad7SBorislav Petkov if (mode & PERF_EF_START) 3926aec1ad7SBorislav Petkov cstate_pmu_event_start(event, mode); 3936aec1ad7SBorislav Petkov 3946aec1ad7SBorislav Petkov return 0; 3956aec1ad7SBorislav Petkov } 3966aec1ad7SBorislav Petkov 39749de0493SThomas Gleixner /* 39849de0493SThomas Gleixner * Check if exiting cpu is the designated reader. If so migrate the 39949de0493SThomas Gleixner * events when there is a valid target available 40049de0493SThomas Gleixner */ 40177c34ef1SSebastian Andrzej Siewior static int cstate_cpu_exit(unsigned int cpu) 4026aec1ad7SBorislav Petkov { 40349de0493SThomas Gleixner unsigned int target; 4046aec1ad7SBorislav Petkov 40549de0493SThomas Gleixner if (has_cstate_core && 40649de0493SThomas Gleixner cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) { 4076aec1ad7SBorislav Petkov 40849de0493SThomas Gleixner target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu); 40949de0493SThomas Gleixner /* Migrate events if there is a valid target */ 41049de0493SThomas Gleixner if (target < nr_cpu_ids) { 4116aec1ad7SBorislav Petkov cpumask_set_cpu(target, &cstate_core_cpu_mask); 4126aec1ad7SBorislav Petkov perf_pmu_migrate_context(&cstate_core_pmu, cpu, target); 4136aec1ad7SBorislav Petkov } 4146aec1ad7SBorislav Petkov } 41549de0493SThomas Gleixner 41649de0493SThomas Gleixner if (has_cstate_pkg && 41749de0493SThomas Gleixner cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) { 41849de0493SThomas Gleixner 419cb63ba0fSKan Liang target = cpumask_any_but(topology_die_cpumask(cpu), cpu); 42049de0493SThomas Gleixner /* Migrate events if there is a valid target */ 42149de0493SThomas Gleixner if (target < nr_cpu_ids) { 4226aec1ad7SBorislav Petkov cpumask_set_cpu(target, &cstate_pkg_cpu_mask); 4236aec1ad7SBorislav Petkov perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target); 4246aec1ad7SBorislav Petkov } 4256aec1ad7SBorislav Petkov } 42677c34ef1SSebastian Andrzej Siewior return 0; 42749de0493SThomas Gleixner } 4286aec1ad7SBorislav Petkov 42977c34ef1SSebastian Andrzej Siewior static int cstate_cpu_init(unsigned int cpu) 4306aec1ad7SBorislav Petkov { 43149de0493SThomas Gleixner unsigned int target; 4326aec1ad7SBorislav Petkov 43349de0493SThomas Gleixner /* 43449de0493SThomas Gleixner * If this is the first online thread of that core, set it in 43549de0493SThomas Gleixner * the core cpu mask as the designated reader. 43649de0493SThomas Gleixner */ 43749de0493SThomas Gleixner target = cpumask_any_and(&cstate_core_cpu_mask, 43849de0493SThomas Gleixner topology_sibling_cpumask(cpu)); 43949de0493SThomas Gleixner 44049de0493SThomas Gleixner if (has_cstate_core && target >= nr_cpu_ids) 4416aec1ad7SBorislav Petkov cpumask_set_cpu(cpu, &cstate_core_cpu_mask); 4426aec1ad7SBorislav Petkov 44349de0493SThomas Gleixner /* 44449de0493SThomas Gleixner * If this is the first online thread of that package, set it 44549de0493SThomas Gleixner * in the package cpu mask as the designated reader. 44649de0493SThomas Gleixner */ 44749de0493SThomas Gleixner target = cpumask_any_and(&cstate_pkg_cpu_mask, 448cb63ba0fSKan Liang topology_die_cpumask(cpu)); 44949de0493SThomas Gleixner if (has_cstate_pkg && target >= nr_cpu_ids) 4506aec1ad7SBorislav Petkov cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask); 4516aec1ad7SBorislav Petkov 45277c34ef1SSebastian Andrzej Siewior return 0; 4536aec1ad7SBorislav Petkov } 454c7afba32SThomas Gleixner 455d9f3b450SValdis Klētnieks static const struct attribute_group *core_attr_update[] = { 4568f2a28c5SJiri Olsa &group_cstate_core_c1, 4578f2a28c5SJiri Olsa &group_cstate_core_c3, 4588f2a28c5SJiri Olsa &group_cstate_core_c6, 4598f2a28c5SJiri Olsa &group_cstate_core_c7, 4608f2a28c5SJiri Olsa NULL, 4618f2a28c5SJiri Olsa }; 4628f2a28c5SJiri Olsa 463d9f3b450SValdis Klētnieks static const struct attribute_group *pkg_attr_update[] = { 4648f2a28c5SJiri Olsa &group_cstate_pkg_c2, 4658f2a28c5SJiri Olsa &group_cstate_pkg_c3, 4668f2a28c5SJiri Olsa &group_cstate_pkg_c6, 4678f2a28c5SJiri Olsa &group_cstate_pkg_c7, 4688f2a28c5SJiri Olsa &group_cstate_pkg_c8, 4698f2a28c5SJiri Olsa &group_cstate_pkg_c9, 4708f2a28c5SJiri Olsa &group_cstate_pkg_c10, 4718f2a28c5SJiri Olsa NULL, 4728f2a28c5SJiri Olsa }; 4738f2a28c5SJiri Olsa 474424646eeSThomas Gleixner static struct pmu cstate_core_pmu = { 475424646eeSThomas Gleixner .attr_groups = core_attr_groups, 4768f2a28c5SJiri Olsa .attr_update = core_attr_update, 477424646eeSThomas Gleixner .name = "cstate_core", 478424646eeSThomas Gleixner .task_ctx_nr = perf_invalid_context, 479424646eeSThomas Gleixner .event_init = cstate_pmu_event_init, 480424646eeSThomas Gleixner .add = cstate_pmu_event_add, 481424646eeSThomas Gleixner .del = cstate_pmu_event_del, 482424646eeSThomas Gleixner .start = cstate_pmu_event_start, 483424646eeSThomas Gleixner .stop = cstate_pmu_event_stop, 484424646eeSThomas Gleixner .read = cstate_pmu_event_update, 4852ff40250SAndrew Murray .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 48674545f63SDavid Carrillo-Cisneros .module = THIS_MODULE, 487424646eeSThomas Gleixner }; 488424646eeSThomas Gleixner 489424646eeSThomas Gleixner static struct pmu cstate_pkg_pmu = { 490424646eeSThomas Gleixner .attr_groups = pkg_attr_groups, 4918f2a28c5SJiri Olsa .attr_update = pkg_attr_update, 492424646eeSThomas Gleixner .name = "cstate_pkg", 493424646eeSThomas Gleixner .task_ctx_nr = perf_invalid_context, 494424646eeSThomas Gleixner .event_init = cstate_pmu_event_init, 495424646eeSThomas Gleixner .add = cstate_pmu_event_add, 496424646eeSThomas Gleixner .del = cstate_pmu_event_del, 497424646eeSThomas Gleixner .start = cstate_pmu_event_start, 498424646eeSThomas Gleixner .stop = cstate_pmu_event_stop, 499424646eeSThomas Gleixner .read = cstate_pmu_event_update, 5002ff40250SAndrew Murray .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 50174545f63SDavid Carrillo-Cisneros .module = THIS_MODULE, 502424646eeSThomas Gleixner }; 503424646eeSThomas Gleixner 504424646eeSThomas Gleixner static const struct cstate_model nhm_cstates __initconst = { 505424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 506424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES), 507424646eeSThomas Gleixner 508424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) | 509424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C6_RES) | 510424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C7_RES), 511424646eeSThomas Gleixner }; 512424646eeSThomas Gleixner 513424646eeSThomas Gleixner static const struct cstate_model snb_cstates __initconst = { 514424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 515424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES) | 516424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C7_RES), 517424646eeSThomas Gleixner 518424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 519424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C3_RES) | 520424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C6_RES) | 521424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C7_RES), 522424646eeSThomas Gleixner }; 523424646eeSThomas Gleixner 524424646eeSThomas Gleixner static const struct cstate_model hswult_cstates __initconst = { 525424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 526424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES) | 527424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C7_RES), 528424646eeSThomas Gleixner 529424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 530424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C3_RES) | 531424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C6_RES) | 532424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C7_RES) | 533424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C8_RES) | 534424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C9_RES) | 535424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C10_RES), 536424646eeSThomas Gleixner }; 537424646eeSThomas Gleixner 5381159e094SHarry Pan static const struct cstate_model cnl_cstates __initconst = { 5391159e094SHarry Pan .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 5401159e094SHarry Pan BIT(PERF_CSTATE_CORE_C3_RES) | 5411159e094SHarry Pan BIT(PERF_CSTATE_CORE_C6_RES) | 5421159e094SHarry Pan BIT(PERF_CSTATE_CORE_C7_RES), 5431159e094SHarry Pan 5441159e094SHarry Pan .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 5451159e094SHarry Pan BIT(PERF_CSTATE_PKG_C3_RES) | 5461159e094SHarry Pan BIT(PERF_CSTATE_PKG_C6_RES) | 5471159e094SHarry Pan BIT(PERF_CSTATE_PKG_C7_RES) | 5481159e094SHarry Pan BIT(PERF_CSTATE_PKG_C8_RES) | 5491159e094SHarry Pan BIT(PERF_CSTATE_PKG_C9_RES) | 5501159e094SHarry Pan BIT(PERF_CSTATE_PKG_C10_RES), 5511159e094SHarry Pan }; 5521159e094SHarry Pan 553f1857a24SKan Liang static const struct cstate_model icl_cstates __initconst = { 554f1857a24SKan Liang .core_events = BIT(PERF_CSTATE_CORE_C6_RES) | 555f1857a24SKan Liang BIT(PERF_CSTATE_CORE_C7_RES), 556f1857a24SKan Liang 557f1857a24SKan Liang .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 558f1857a24SKan Liang BIT(PERF_CSTATE_PKG_C3_RES) | 559f1857a24SKan Liang BIT(PERF_CSTATE_PKG_C6_RES) | 560f1857a24SKan Liang BIT(PERF_CSTATE_PKG_C7_RES) | 561f1857a24SKan Liang BIT(PERF_CSTATE_PKG_C8_RES) | 562f1857a24SKan Liang BIT(PERF_CSTATE_PKG_C9_RES) | 563f1857a24SKan Liang BIT(PERF_CSTATE_PKG_C10_RES), 564f1857a24SKan Liang }; 565f1857a24SKan Liang 566424646eeSThomas Gleixner static const struct cstate_model slm_cstates __initconst = { 567424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 568424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES), 569424646eeSThomas Gleixner 570424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), 571424646eeSThomas Gleixner .quirks = SLM_PKG_C6_USE_C7_MSR, 572424646eeSThomas Gleixner }; 573424646eeSThomas Gleixner 574889882bcSLukasz Odzioba 575889882bcSLukasz Odzioba static const struct cstate_model knl_cstates __initconst = { 576889882bcSLukasz Odzioba .core_events = BIT(PERF_CSTATE_CORE_C6_RES), 577889882bcSLukasz Odzioba 578889882bcSLukasz Odzioba .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 579889882bcSLukasz Odzioba BIT(PERF_CSTATE_PKG_C3_RES) | 580889882bcSLukasz Odzioba BIT(PERF_CSTATE_PKG_C6_RES), 581889882bcSLukasz Odzioba .quirks = KNL_CORE_C6_MSR, 582889882bcSLukasz Odzioba }; 583889882bcSLukasz Odzioba 584889882bcSLukasz Odzioba 5855c10b048SHarry Pan static const struct cstate_model glm_cstates __initconst = { 5865c10b048SHarry Pan .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 5875c10b048SHarry Pan BIT(PERF_CSTATE_CORE_C3_RES) | 5885c10b048SHarry Pan BIT(PERF_CSTATE_CORE_C6_RES), 5895c10b048SHarry Pan 5905c10b048SHarry Pan .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 5915c10b048SHarry Pan BIT(PERF_CSTATE_PKG_C3_RES) | 5925c10b048SHarry Pan BIT(PERF_CSTATE_PKG_C6_RES) | 5935c10b048SHarry Pan BIT(PERF_CSTATE_PKG_C10_RES), 5945c10b048SHarry Pan }; 5955c10b048SHarry Pan 596889882bcSLukasz Odzioba 597424646eeSThomas Gleixner static const struct x86_cpu_id intel_cstates_match[] __initconst = { 598ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &nhm_cstates), 599ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &nhm_cstates), 600ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &nhm_cstates), 601424646eeSThomas Gleixner 602ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &nhm_cstates), 603ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &nhm_cstates), 604ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &nhm_cstates), 605424646eeSThomas Gleixner 606ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &snb_cstates), 607ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &snb_cstates), 608424646eeSThomas Gleixner 609ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &snb_cstates), 610ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &snb_cstates), 611424646eeSThomas Gleixner 612ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &snb_cstates), 613ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &snb_cstates), 614ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &snb_cstates), 615424646eeSThomas Gleixner 616ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &hswult_cstates), 617424646eeSThomas Gleixner 618ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &slm_cstates), 619ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &slm_cstates), 620ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &slm_cstates), 621424646eeSThomas Gleixner 622ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &snb_cstates), 623ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &snb_cstates), 624ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &snb_cstates), 625ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &snb_cstates), 626424646eeSThomas Gleixner 627ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &snb_cstates), 628ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &snb_cstates), 629ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &snb_cstates), 630889882bcSLukasz Odzioba 631ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &hswult_cstates), 632ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &hswult_cstates), 633ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &hswult_cstates), 634ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &hswult_cstates), 635f2029b1eSSrinivas Pandruvada 636ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &cnl_cstates), 6371159e094SHarry Pan 638ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &knl_cstates), 639ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &knl_cstates), 6405c10b048SHarry Pan 641ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &glm_cstates), 642ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &glm_cstates), 643ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates), 644ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates), 645ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates), 6465b16ef2eSHarry Pan X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates), 647f08c47d1SKan Liang 648ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates), 649ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates), 650ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &icl_cstates), 651ef37219aSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates), 652424646eeSThomas Gleixner { }, 653424646eeSThomas Gleixner }; 654424646eeSThomas Gleixner MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); 655424646eeSThomas Gleixner 656424646eeSThomas Gleixner static int __init cstate_probe(const struct cstate_model *cm) 6576aec1ad7SBorislav Petkov { 6586aec1ad7SBorislav Petkov /* SLM has different MSR for PKG C6 */ 659424646eeSThomas Gleixner if (cm->quirks & SLM_PKG_C6_USE_C7_MSR) 6606aec1ad7SBorislav Petkov pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY; 6616aec1ad7SBorislav Petkov 662889882bcSLukasz Odzioba /* KNL has different MSR for CORE C6 */ 663889882bcSLukasz Odzioba if (cm->quirks & KNL_CORE_C6_MSR) 664889882bcSLukasz Odzioba pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY; 665889882bcSLukasz Odzioba 666889882bcSLukasz Odzioba 6678f2a28c5SJiri Olsa core_msr_mask = perf_msr_probe(core_msr, PERF_CSTATE_CORE_EVENT_MAX, 6688f2a28c5SJiri Olsa true, (void *) &cm->core_events); 6696aec1ad7SBorislav Petkov 6708f2a28c5SJiri Olsa pkg_msr_mask = perf_msr_probe(pkg_msr, PERF_CSTATE_PKG_EVENT_MAX, 6718f2a28c5SJiri Olsa true, (void *) &cm->pkg_events); 6728f2a28c5SJiri Olsa 6738f2a28c5SJiri Olsa has_cstate_core = !!core_msr_mask; 6748f2a28c5SJiri Olsa has_cstate_pkg = !!pkg_msr_mask; 6756aec1ad7SBorislav Petkov 6766aec1ad7SBorislav Petkov return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV; 6776aec1ad7SBorislav Petkov } 6786aec1ad7SBorislav Petkov 679c7afba32SThomas Gleixner static inline void cstate_cleanup(void) 6806aec1ad7SBorislav Petkov { 681834fcd29SThomas Gleixner cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE); 682834fcd29SThomas Gleixner cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING); 683834fcd29SThomas Gleixner 684d29859e7SThomas Gleixner if (has_cstate_core) 685d29859e7SThomas Gleixner perf_pmu_unregister(&cstate_core_pmu); 686d29859e7SThomas Gleixner 687d29859e7SThomas Gleixner if (has_cstate_pkg) 688d29859e7SThomas Gleixner perf_pmu_unregister(&cstate_pkg_pmu); 689d29859e7SThomas Gleixner } 690d29859e7SThomas Gleixner 691d29859e7SThomas Gleixner static int __init cstate_init(void) 692d29859e7SThomas Gleixner { 69377c34ef1SSebastian Andrzej Siewior int err; 6946aec1ad7SBorislav Petkov 69577c34ef1SSebastian Andrzej Siewior cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING, 696834fcd29SThomas Gleixner "perf/x86/cstate:starting", cstate_cpu_init, NULL); 69777c34ef1SSebastian Andrzej Siewior cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE, 698834fcd29SThomas Gleixner "perf/x86/cstate:online", NULL, cstate_cpu_exit); 6996aec1ad7SBorislav Petkov 7006aec1ad7SBorislav Petkov if (has_cstate_core) { 7016aec1ad7SBorislav Petkov err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1); 702d29859e7SThomas Gleixner if (err) { 703d29859e7SThomas Gleixner has_cstate_core = false; 704d29859e7SThomas Gleixner pr_info("Failed to register cstate core pmu\n"); 705834fcd29SThomas Gleixner cstate_cleanup(); 70677c34ef1SSebastian Andrzej Siewior return err; 707d29859e7SThomas Gleixner } 7086aec1ad7SBorislav Petkov } 7096aec1ad7SBorislav Petkov 7106aec1ad7SBorislav Petkov if (has_cstate_pkg) { 711cb63ba0fSKan Liang if (topology_max_die_per_package() > 1) { 712cb63ba0fSKan Liang err = perf_pmu_register(&cstate_pkg_pmu, 713cb63ba0fSKan Liang "cstate_die", -1); 714cb63ba0fSKan Liang } else { 715cb63ba0fSKan Liang err = perf_pmu_register(&cstate_pkg_pmu, 716cb63ba0fSKan Liang cstate_pkg_pmu.name, -1); 717cb63ba0fSKan Liang } 718d29859e7SThomas Gleixner if (err) { 719d29859e7SThomas Gleixner has_cstate_pkg = false; 720d29859e7SThomas Gleixner pr_info("Failed to register cstate pkg pmu\n"); 721d29859e7SThomas Gleixner cstate_cleanup(); 72277c34ef1SSebastian Andrzej Siewior return err; 7236aec1ad7SBorislav Petkov } 7246aec1ad7SBorislav Petkov } 725834fcd29SThomas Gleixner return 0; 726d29859e7SThomas Gleixner } 7276aec1ad7SBorislav Petkov 7286aec1ad7SBorislav Petkov static int __init cstate_pmu_init(void) 7296aec1ad7SBorislav Petkov { 730424646eeSThomas Gleixner const struct x86_cpu_id *id; 7316aec1ad7SBorislav Petkov int err; 7326aec1ad7SBorislav Petkov 733424646eeSThomas Gleixner if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 7346aec1ad7SBorislav Petkov return -ENODEV; 7356aec1ad7SBorislav Petkov 736424646eeSThomas Gleixner id = x86_match_cpu(intel_cstates_match); 737424646eeSThomas Gleixner if (!id) 738424646eeSThomas Gleixner return -ENODEV; 739424646eeSThomas Gleixner 740424646eeSThomas Gleixner err = cstate_probe((const struct cstate_model *) id->driver_data); 7416aec1ad7SBorislav Petkov if (err) 7426aec1ad7SBorislav Petkov return err; 7436aec1ad7SBorislav Petkov 744d29859e7SThomas Gleixner return cstate_init(); 7456aec1ad7SBorislav Petkov } 746c7afba32SThomas Gleixner module_init(cstate_pmu_init); 747c7afba32SThomas Gleixner 748c7afba32SThomas Gleixner static void __exit cstate_pmu_exit(void) 749c7afba32SThomas Gleixner { 750c7afba32SThomas Gleixner cstate_cleanup(); 751c7afba32SThomas Gleixner } 752c7afba32SThomas Gleixner module_exit(cstate_pmu_exit); 753