16aec1ad7SBorislav Petkov /* 2940b2f2fSBorislav Petkov * Support cstate residency counters 36aec1ad7SBorislav Petkov * 46aec1ad7SBorislav Petkov * Copyright (C) 2015, Intel Corp. 56aec1ad7SBorislav Petkov * Author: Kan Liang (kan.liang@intel.com) 66aec1ad7SBorislav Petkov * 76aec1ad7SBorislav Petkov * This library is free software; you can redistribute it and/or 86aec1ad7SBorislav Petkov * modify it under the terms of the GNU Library General Public 96aec1ad7SBorislav Petkov * License as published by the Free Software Foundation; either 106aec1ad7SBorislav Petkov * version 2 of the License, or (at your option) any later version. 116aec1ad7SBorislav Petkov * 126aec1ad7SBorislav Petkov * This library is distributed in the hope that it will be useful, 136aec1ad7SBorislav Petkov * but WITHOUT ANY WARRANTY; without even the implied warranty of 146aec1ad7SBorislav Petkov * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 156aec1ad7SBorislav Petkov * Library General Public License for more details. 166aec1ad7SBorislav Petkov * 176aec1ad7SBorislav Petkov */ 186aec1ad7SBorislav Petkov 196aec1ad7SBorislav Petkov /* 206aec1ad7SBorislav Petkov * This file export cstate related free running (read-only) counters 216aec1ad7SBorislav Petkov * for perf. These counters may be use simultaneously by other tools, 226aec1ad7SBorislav Petkov * such as turbostat. However, it still make sense to implement them 236aec1ad7SBorislav Petkov * in perf. Because we can conveniently collect them together with 246aec1ad7SBorislav Petkov * other events, and allow to use them from tools without special MSR 256aec1ad7SBorislav Petkov * access code. 266aec1ad7SBorislav Petkov * 276aec1ad7SBorislav Petkov * The events only support system-wide mode counting. There is no 286aec1ad7SBorislav Petkov * sampling support because it is not supported by the hardware. 296aec1ad7SBorislav Petkov * 306aec1ad7SBorislav Petkov * According to counters' scope and category, two PMUs are registered 316aec1ad7SBorislav Petkov * with the perf_event core subsystem. 326aec1ad7SBorislav Petkov * - 'cstate_core': The counter is available for each physical core. 336aec1ad7SBorislav Petkov * The counters include CORE_C*_RESIDENCY. 346aec1ad7SBorislav Petkov * - 'cstate_pkg': The counter is available for each physical package. 356aec1ad7SBorislav Petkov * The counters include PKG_C*_RESIDENCY. 366aec1ad7SBorislav Petkov * 376aec1ad7SBorislav Petkov * All of these counters are specified in the Intel® 64 and IA-32 386aec1ad7SBorislav Petkov * Architectures Software Developer.s Manual Vol3b. 396aec1ad7SBorislav Petkov * 406aec1ad7SBorislav Petkov * Model specific counters: 416aec1ad7SBorislav Petkov * MSR_CORE_C1_RES: CORE C1 Residency Counter 426aec1ad7SBorislav Petkov * perf code: 0x00 431159e094SHarry Pan * Available model: SLM,AMT,GLM,CNL 446aec1ad7SBorislav Petkov * Scope: Core (each processor core has a MSR) 456aec1ad7SBorislav Petkov * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter 466aec1ad7SBorislav Petkov * perf code: 0x01 471159e094SHarry Pan * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, 481ffa6c04SKan Liang * CNL,KBL,CML 496aec1ad7SBorislav Petkov * Scope: Core 506aec1ad7SBorislav Petkov * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter 516aec1ad7SBorislav Petkov * perf code: 0x02 521159e094SHarry Pan * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, 531ffa6c04SKan Liang * SKL,KNL,GLM,CNL,KBL,CML 546aec1ad7SBorislav Petkov * Scope: Core 556aec1ad7SBorislav Petkov * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter 566aec1ad7SBorislav Petkov * perf code: 0x03 571ffa6c04SKan Liang * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML 586aec1ad7SBorislav Petkov * Scope: Core 596aec1ad7SBorislav Petkov * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. 606aec1ad7SBorislav Petkov * perf code: 0x00 611ffa6c04SKan Liang * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, 621ffa6c04SKan Liang * KBL,CML 636aec1ad7SBorislav Petkov * Scope: Package (physical package) 646aec1ad7SBorislav Petkov * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. 656aec1ad7SBorislav Petkov * perf code: 0x01 661159e094SHarry Pan * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, 671ffa6c04SKan Liang * GLM,CNL,KBL,CML 686aec1ad7SBorislav Petkov * Scope: Package (physical package) 696aec1ad7SBorislav Petkov * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. 706aec1ad7SBorislav Petkov * perf code: 0x02 71889882bcSLukasz Odzioba * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW 721ffa6c04SKan Liang * SKL,KNL,GLM,CNL,KBL,CML 736aec1ad7SBorislav Petkov * Scope: Package (physical package) 746aec1ad7SBorislav Petkov * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. 756aec1ad7SBorislav Petkov * perf code: 0x03 761ffa6c04SKan Liang * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, 771ffa6c04SKan Liang * KBL,CML 786aec1ad7SBorislav Petkov * Scope: Package (physical package) 796aec1ad7SBorislav Petkov * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. 806aec1ad7SBorislav Petkov * perf code: 0x04 811ffa6c04SKan Liang * Available model: HSW ULT,KBL,CNL,CML 826aec1ad7SBorislav Petkov * Scope: Package (physical package) 836aec1ad7SBorislav Petkov * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. 846aec1ad7SBorislav Petkov * perf code: 0x05 851ffa6c04SKan Liang * Available model: HSW ULT,KBL,CNL,CML 866aec1ad7SBorislav Petkov * Scope: Package (physical package) 876aec1ad7SBorislav Petkov * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. 886aec1ad7SBorislav Petkov * perf code: 0x06 891ffa6c04SKan Liang * Available model: HSW ULT,KBL,GLM,CNL,CML 906aec1ad7SBorislav Petkov * Scope: Package (physical package) 916aec1ad7SBorislav Petkov * 926aec1ad7SBorislav Petkov */ 936aec1ad7SBorislav Petkov 946aec1ad7SBorislav Petkov #include <linux/module.h> 956aec1ad7SBorislav Petkov #include <linux/slab.h> 966aec1ad7SBorislav Petkov #include <linux/perf_event.h> 97a5f81290SPeter Zijlstra #include <linux/nospec.h> 986aec1ad7SBorislav Petkov #include <asm/cpu_device_id.h> 99bf4ad541SDave Hansen #include <asm/intel-family.h> 10027f6d22bSBorislav Petkov #include "../perf_event.h" 1018f2a28c5SJiri Olsa #include "../probe.h" 1026aec1ad7SBorislav Petkov 103c7afba32SThomas Gleixner MODULE_LICENSE("GPL"); 104c7afba32SThomas Gleixner 1056aec1ad7SBorislav Petkov #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format) \ 1066aec1ad7SBorislav Petkov static ssize_t __cstate_##_var##_show(struct kobject *kobj, \ 1076aec1ad7SBorislav Petkov struct kobj_attribute *attr, \ 1086aec1ad7SBorislav Petkov char *page) \ 1096aec1ad7SBorislav Petkov { \ 1106aec1ad7SBorislav Petkov BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ 1116aec1ad7SBorislav Petkov return sprintf(page, _format "\n"); \ 1126aec1ad7SBorislav Petkov } \ 1136aec1ad7SBorislav Petkov static struct kobj_attribute format_attr_##_var = \ 1146aec1ad7SBorislav Petkov __ATTR(_name, 0444, __cstate_##_var##_show, NULL) 1156aec1ad7SBorislav Petkov 1166aec1ad7SBorislav Petkov static ssize_t cstate_get_attr_cpumask(struct device *dev, 1176aec1ad7SBorislav Petkov struct device_attribute *attr, 1186aec1ad7SBorislav Petkov char *buf); 1196aec1ad7SBorislav Petkov 120424646eeSThomas Gleixner /* Model -> events mapping */ 121424646eeSThomas Gleixner struct cstate_model { 122424646eeSThomas Gleixner unsigned long core_events; 123424646eeSThomas Gleixner unsigned long pkg_events; 124424646eeSThomas Gleixner unsigned long quirks; 125424646eeSThomas Gleixner }; 126424646eeSThomas Gleixner 127424646eeSThomas Gleixner /* Quirk flags */ 128424646eeSThomas Gleixner #define SLM_PKG_C6_USE_C7_MSR (1UL << 0) 129889882bcSLukasz Odzioba #define KNL_CORE_C6_MSR (1UL << 1) 130424646eeSThomas Gleixner 1316aec1ad7SBorislav Petkov struct perf_cstate_msr { 1326aec1ad7SBorislav Petkov u64 msr; 1336aec1ad7SBorislav Petkov struct perf_pmu_events_attr *attr; 1346aec1ad7SBorislav Petkov }; 1356aec1ad7SBorislav Petkov 1366aec1ad7SBorislav Petkov 1376aec1ad7SBorislav Petkov /* cstate_core PMU */ 1386aec1ad7SBorislav Petkov static struct pmu cstate_core_pmu; 1396aec1ad7SBorislav Petkov static bool has_cstate_core; 1406aec1ad7SBorislav Petkov 141424646eeSThomas Gleixner enum perf_cstate_core_events { 1426aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C1_RES = 0, 1436aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C3_RES, 1446aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C6_RES, 1456aec1ad7SBorislav Petkov PERF_CSTATE_CORE_C7_RES, 1466aec1ad7SBorislav Petkov 1476aec1ad7SBorislav Petkov PERF_CSTATE_CORE_EVENT_MAX, 1486aec1ad7SBorislav Petkov }; 1496aec1ad7SBorislav Petkov 1508f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00"); 1518f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01"); 1528f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02"); 1538f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_core_c7, "event=0x03"); 1546aec1ad7SBorislav Petkov 1558f2a28c5SJiri Olsa static unsigned long core_msr_mask; 1568f2a28c5SJiri Olsa 1578f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c1); 1588f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c3); 1598f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c6); 1608f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_core_c7); 1618f2a28c5SJiri Olsa 1628f2a28c5SJiri Olsa static bool test_msr(int idx, void *data) 1638f2a28c5SJiri Olsa { 1648f2a28c5SJiri Olsa return test_bit(idx, (unsigned long *) data); 1658f2a28c5SJiri Olsa } 1668f2a28c5SJiri Olsa 1678f2a28c5SJiri Olsa static struct perf_msr core_msr[] = { 1688f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES, &group_cstate_core_c1, test_msr }, 1698f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY, &group_cstate_core_c3, test_msr }, 1708f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY, &group_cstate_core_c6, test_msr }, 1718f2a28c5SJiri Olsa [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY, &group_cstate_core_c7, test_msr }, 1726aec1ad7SBorislav Petkov }; 1736aec1ad7SBorislav Petkov 1748f2a28c5SJiri Olsa static struct attribute *attrs_empty[] = { 1756aec1ad7SBorislav Petkov NULL, 1766aec1ad7SBorislav Petkov }; 1776aec1ad7SBorislav Petkov 1788f2a28c5SJiri Olsa /* 1798f2a28c5SJiri Olsa * There are no default events, but we need to create 1808f2a28c5SJiri Olsa * "events" group (with empty attrs) before updating 1818f2a28c5SJiri Olsa * it with detected events. 1828f2a28c5SJiri Olsa */ 1836aec1ad7SBorislav Petkov static struct attribute_group core_events_attr_group = { 1846aec1ad7SBorislav Petkov .name = "events", 1858f2a28c5SJiri Olsa .attrs = attrs_empty, 1866aec1ad7SBorislav Petkov }; 1876aec1ad7SBorislav Petkov 1886aec1ad7SBorislav Petkov DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63"); 1896aec1ad7SBorislav Petkov static struct attribute *core_format_attrs[] = { 1906aec1ad7SBorislav Petkov &format_attr_core_event.attr, 1916aec1ad7SBorislav Petkov NULL, 1926aec1ad7SBorislav Petkov }; 1936aec1ad7SBorislav Petkov 1946aec1ad7SBorislav Petkov static struct attribute_group core_format_attr_group = { 1956aec1ad7SBorislav Petkov .name = "format", 1966aec1ad7SBorislav Petkov .attrs = core_format_attrs, 1976aec1ad7SBorislav Petkov }; 1986aec1ad7SBorislav Petkov 1996aec1ad7SBorislav Petkov static cpumask_t cstate_core_cpu_mask; 2006aec1ad7SBorislav Petkov static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL); 2016aec1ad7SBorislav Petkov 2026aec1ad7SBorislav Petkov static struct attribute *cstate_cpumask_attrs[] = { 2036aec1ad7SBorislav Petkov &dev_attr_cpumask.attr, 2046aec1ad7SBorislav Petkov NULL, 2056aec1ad7SBorislav Petkov }; 2066aec1ad7SBorislav Petkov 2076aec1ad7SBorislav Petkov static struct attribute_group cpumask_attr_group = { 2086aec1ad7SBorislav Petkov .attrs = cstate_cpumask_attrs, 2096aec1ad7SBorislav Petkov }; 2106aec1ad7SBorislav Petkov 2116aec1ad7SBorislav Petkov static const struct attribute_group *core_attr_groups[] = { 2126aec1ad7SBorislav Petkov &core_events_attr_group, 2136aec1ad7SBorislav Petkov &core_format_attr_group, 2146aec1ad7SBorislav Petkov &cpumask_attr_group, 2156aec1ad7SBorislav Petkov NULL, 2166aec1ad7SBorislav Petkov }; 2176aec1ad7SBorislav Petkov 2186aec1ad7SBorislav Petkov /* cstate_pkg PMU */ 2196aec1ad7SBorislav Petkov static struct pmu cstate_pkg_pmu; 2206aec1ad7SBorislav Petkov static bool has_cstate_pkg; 2216aec1ad7SBorislav Petkov 222424646eeSThomas Gleixner enum perf_cstate_pkg_events { 2236aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C2_RES = 0, 2246aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C3_RES, 2256aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C6_RES, 2266aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C7_RES, 2276aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C8_RES, 2286aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C9_RES, 2296aec1ad7SBorislav Petkov PERF_CSTATE_PKG_C10_RES, 2306aec1ad7SBorislav Petkov 2316aec1ad7SBorislav Petkov PERF_CSTATE_PKG_EVENT_MAX, 2326aec1ad7SBorislav Petkov }; 2336aec1ad7SBorislav Petkov 2348f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c2-residency, attr_cstate_pkg_c2, "event=0x00"); 2358f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_pkg_c3, "event=0x01"); 2368f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_pkg_c6, "event=0x02"); 2378f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_pkg_c7, "event=0x03"); 2388f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c8-residency, attr_cstate_pkg_c8, "event=0x04"); 2398f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c9-residency, attr_cstate_pkg_c9, "event=0x05"); 2408f2a28c5SJiri Olsa PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06"); 2416aec1ad7SBorislav Petkov 2428f2a28c5SJiri Olsa static unsigned long pkg_msr_mask; 2436aec1ad7SBorislav Petkov 2448f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c2); 2458f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c3); 2468f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c6); 2478f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c7); 2488f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c8); 2498f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c9); 2508f2a28c5SJiri Olsa PMU_EVENT_GROUP(events, cstate_pkg_c10); 2518f2a28c5SJiri Olsa 2528f2a28c5SJiri Olsa static struct perf_msr pkg_msr[] = { 2538f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY, &group_cstate_pkg_c2, test_msr }, 2548f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY, &group_cstate_pkg_c3, test_msr }, 2558f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY, &group_cstate_pkg_c6, test_msr }, 2568f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY, &group_cstate_pkg_c7, test_msr }, 2578f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY, &group_cstate_pkg_c8, test_msr }, 2588f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY, &group_cstate_pkg_c9, test_msr }, 2598f2a28c5SJiri Olsa [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY, &group_cstate_pkg_c10, test_msr }, 2606aec1ad7SBorislav Petkov }; 2616aec1ad7SBorislav Petkov 2626aec1ad7SBorislav Petkov static struct attribute_group pkg_events_attr_group = { 2636aec1ad7SBorislav Petkov .name = "events", 2648f2a28c5SJiri Olsa .attrs = attrs_empty, 2656aec1ad7SBorislav Petkov }; 2666aec1ad7SBorislav Petkov 2676aec1ad7SBorislav Petkov DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63"); 2686aec1ad7SBorislav Petkov static struct attribute *pkg_format_attrs[] = { 2696aec1ad7SBorislav Petkov &format_attr_pkg_event.attr, 2706aec1ad7SBorislav Petkov NULL, 2716aec1ad7SBorislav Petkov }; 2726aec1ad7SBorislav Petkov static struct attribute_group pkg_format_attr_group = { 2736aec1ad7SBorislav Petkov .name = "format", 2746aec1ad7SBorislav Petkov .attrs = pkg_format_attrs, 2756aec1ad7SBorislav Petkov }; 2766aec1ad7SBorislav Petkov 2776aec1ad7SBorislav Petkov static cpumask_t cstate_pkg_cpu_mask; 2786aec1ad7SBorislav Petkov 2796aec1ad7SBorislav Petkov static const struct attribute_group *pkg_attr_groups[] = { 2806aec1ad7SBorislav Petkov &pkg_events_attr_group, 2816aec1ad7SBorislav Petkov &pkg_format_attr_group, 2826aec1ad7SBorislav Petkov &cpumask_attr_group, 2836aec1ad7SBorislav Petkov NULL, 2846aec1ad7SBorislav Petkov }; 2856aec1ad7SBorislav Petkov 2866aec1ad7SBorislav Petkov static ssize_t cstate_get_attr_cpumask(struct device *dev, 2876aec1ad7SBorislav Petkov struct device_attribute *attr, 2886aec1ad7SBorislav Petkov char *buf) 2896aec1ad7SBorislav Petkov { 2906aec1ad7SBorislav Petkov struct pmu *pmu = dev_get_drvdata(dev); 2916aec1ad7SBorislav Petkov 2926aec1ad7SBorislav Petkov if (pmu == &cstate_core_pmu) 2936aec1ad7SBorislav Petkov return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask); 2946aec1ad7SBorislav Petkov else if (pmu == &cstate_pkg_pmu) 2956aec1ad7SBorislav Petkov return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask); 2966aec1ad7SBorislav Petkov else 2976aec1ad7SBorislav Petkov return 0; 2986aec1ad7SBorislav Petkov } 2996aec1ad7SBorislav Petkov 3006aec1ad7SBorislav Petkov static int cstate_pmu_event_init(struct perf_event *event) 3016aec1ad7SBorislav Petkov { 3026aec1ad7SBorislav Petkov u64 cfg = event->attr.config; 30349de0493SThomas Gleixner int cpu; 3046aec1ad7SBorislav Petkov 3056aec1ad7SBorislav Petkov if (event->attr.type != event->pmu->type) 3066aec1ad7SBorislav Petkov return -ENOENT; 3076aec1ad7SBorislav Petkov 3086aec1ad7SBorislav Petkov /* unsupported modes and filters */ 3092ff40250SAndrew Murray if (event->attr.sample_period) /* no sampling */ 3106aec1ad7SBorislav Petkov return -EINVAL; 3116aec1ad7SBorislav Petkov 31249de0493SThomas Gleixner if (event->cpu < 0) 31349de0493SThomas Gleixner return -EINVAL; 31449de0493SThomas Gleixner 3156aec1ad7SBorislav Petkov if (event->pmu == &cstate_core_pmu) { 3166aec1ad7SBorislav Petkov if (cfg >= PERF_CSTATE_CORE_EVENT_MAX) 3176aec1ad7SBorislav Petkov return -EINVAL; 3188f2a28c5SJiri Olsa cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_CORE_EVENT_MAX); 3198f2a28c5SJiri Olsa if (!(core_msr_mask & (1 << cfg))) 3206aec1ad7SBorislav Petkov return -EINVAL; 3216aec1ad7SBorislav Petkov event->hw.event_base = core_msr[cfg].msr; 32249de0493SThomas Gleixner cpu = cpumask_any_and(&cstate_core_cpu_mask, 32349de0493SThomas Gleixner topology_sibling_cpumask(event->cpu)); 3246aec1ad7SBorislav Petkov } else if (event->pmu == &cstate_pkg_pmu) { 3256aec1ad7SBorislav Petkov if (cfg >= PERF_CSTATE_PKG_EVENT_MAX) 3266aec1ad7SBorislav Petkov return -EINVAL; 327a5f81290SPeter Zijlstra cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX); 3288f2a28c5SJiri Olsa if (!(pkg_msr_mask & (1 << cfg))) 3296aec1ad7SBorislav Petkov return -EINVAL; 3306aec1ad7SBorislav Petkov event->hw.event_base = pkg_msr[cfg].msr; 33149de0493SThomas Gleixner cpu = cpumask_any_and(&cstate_pkg_cpu_mask, 332cb63ba0fSKan Liang topology_die_cpumask(event->cpu)); 33349de0493SThomas Gleixner } else { 3346aec1ad7SBorislav Petkov return -ENOENT; 33549de0493SThomas Gleixner } 3366aec1ad7SBorislav Petkov 33749de0493SThomas Gleixner if (cpu >= nr_cpu_ids) 33849de0493SThomas Gleixner return -ENODEV; 33949de0493SThomas Gleixner 34049de0493SThomas Gleixner event->cpu = cpu; 3416aec1ad7SBorislav Petkov event->hw.config = cfg; 3426aec1ad7SBorislav Petkov event->hw.idx = -1; 34349de0493SThomas Gleixner return 0; 3446aec1ad7SBorislav Petkov } 3456aec1ad7SBorislav Petkov 3466aec1ad7SBorislav Petkov static inline u64 cstate_pmu_read_counter(struct perf_event *event) 3476aec1ad7SBorislav Petkov { 3486aec1ad7SBorislav Petkov u64 val; 3496aec1ad7SBorislav Petkov 3506aec1ad7SBorislav Petkov rdmsrl(event->hw.event_base, val); 3516aec1ad7SBorislav Petkov return val; 3526aec1ad7SBorislav Petkov } 3536aec1ad7SBorislav Petkov 3546aec1ad7SBorislav Petkov static void cstate_pmu_event_update(struct perf_event *event) 3556aec1ad7SBorislav Petkov { 3566aec1ad7SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 3576aec1ad7SBorislav Petkov u64 prev_raw_count, new_raw_count; 3586aec1ad7SBorislav Petkov 3596aec1ad7SBorislav Petkov again: 3606aec1ad7SBorislav Petkov prev_raw_count = local64_read(&hwc->prev_count); 3616aec1ad7SBorislav Petkov new_raw_count = cstate_pmu_read_counter(event); 3626aec1ad7SBorislav Petkov 3636aec1ad7SBorislav Petkov if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 3646aec1ad7SBorislav Petkov new_raw_count) != prev_raw_count) 3656aec1ad7SBorislav Petkov goto again; 3666aec1ad7SBorislav Petkov 3676aec1ad7SBorislav Petkov local64_add(new_raw_count - prev_raw_count, &event->count); 3686aec1ad7SBorislav Petkov } 3696aec1ad7SBorislav Petkov 3706aec1ad7SBorislav Petkov static void cstate_pmu_event_start(struct perf_event *event, int mode) 3716aec1ad7SBorislav Petkov { 3726aec1ad7SBorislav Petkov local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event)); 3736aec1ad7SBorislav Petkov } 3746aec1ad7SBorislav Petkov 3756aec1ad7SBorislav Petkov static void cstate_pmu_event_stop(struct perf_event *event, int mode) 3766aec1ad7SBorislav Petkov { 3776aec1ad7SBorislav Petkov cstate_pmu_event_update(event); 3786aec1ad7SBorislav Petkov } 3796aec1ad7SBorislav Petkov 3806aec1ad7SBorislav Petkov static void cstate_pmu_event_del(struct perf_event *event, int mode) 3816aec1ad7SBorislav Petkov { 3826aec1ad7SBorislav Petkov cstate_pmu_event_stop(event, PERF_EF_UPDATE); 3836aec1ad7SBorislav Petkov } 3846aec1ad7SBorislav Petkov 3856aec1ad7SBorislav Petkov static int cstate_pmu_event_add(struct perf_event *event, int mode) 3866aec1ad7SBorislav Petkov { 3876aec1ad7SBorislav Petkov if (mode & PERF_EF_START) 3886aec1ad7SBorislav Petkov cstate_pmu_event_start(event, mode); 3896aec1ad7SBorislav Petkov 3906aec1ad7SBorislav Petkov return 0; 3916aec1ad7SBorislav Petkov } 3926aec1ad7SBorislav Petkov 39349de0493SThomas Gleixner /* 39449de0493SThomas Gleixner * Check if exiting cpu is the designated reader. If so migrate the 39549de0493SThomas Gleixner * events when there is a valid target available 39649de0493SThomas Gleixner */ 39777c34ef1SSebastian Andrzej Siewior static int cstate_cpu_exit(unsigned int cpu) 3986aec1ad7SBorislav Petkov { 39949de0493SThomas Gleixner unsigned int target; 4006aec1ad7SBorislav Petkov 40149de0493SThomas Gleixner if (has_cstate_core && 40249de0493SThomas Gleixner cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) { 4036aec1ad7SBorislav Petkov 40449de0493SThomas Gleixner target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu); 40549de0493SThomas Gleixner /* Migrate events if there is a valid target */ 40649de0493SThomas Gleixner if (target < nr_cpu_ids) { 4076aec1ad7SBorislav Petkov cpumask_set_cpu(target, &cstate_core_cpu_mask); 4086aec1ad7SBorislav Petkov perf_pmu_migrate_context(&cstate_core_pmu, cpu, target); 4096aec1ad7SBorislav Petkov } 4106aec1ad7SBorislav Petkov } 41149de0493SThomas Gleixner 41249de0493SThomas Gleixner if (has_cstate_pkg && 41349de0493SThomas Gleixner cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) { 41449de0493SThomas Gleixner 415cb63ba0fSKan Liang target = cpumask_any_but(topology_die_cpumask(cpu), cpu); 41649de0493SThomas Gleixner /* Migrate events if there is a valid target */ 41749de0493SThomas Gleixner if (target < nr_cpu_ids) { 4186aec1ad7SBorislav Petkov cpumask_set_cpu(target, &cstate_pkg_cpu_mask); 4196aec1ad7SBorislav Petkov perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target); 4206aec1ad7SBorislav Petkov } 4216aec1ad7SBorislav Petkov } 42277c34ef1SSebastian Andrzej Siewior return 0; 42349de0493SThomas Gleixner } 4246aec1ad7SBorislav Petkov 42577c34ef1SSebastian Andrzej Siewior static int cstate_cpu_init(unsigned int cpu) 4266aec1ad7SBorislav Petkov { 42749de0493SThomas Gleixner unsigned int target; 4286aec1ad7SBorislav Petkov 42949de0493SThomas Gleixner /* 43049de0493SThomas Gleixner * If this is the first online thread of that core, set it in 43149de0493SThomas Gleixner * the core cpu mask as the designated reader. 43249de0493SThomas Gleixner */ 43349de0493SThomas Gleixner target = cpumask_any_and(&cstate_core_cpu_mask, 43449de0493SThomas Gleixner topology_sibling_cpumask(cpu)); 43549de0493SThomas Gleixner 43649de0493SThomas Gleixner if (has_cstate_core && target >= nr_cpu_ids) 4376aec1ad7SBorislav Petkov cpumask_set_cpu(cpu, &cstate_core_cpu_mask); 4386aec1ad7SBorislav Petkov 43949de0493SThomas Gleixner /* 44049de0493SThomas Gleixner * If this is the first online thread of that package, set it 44149de0493SThomas Gleixner * in the package cpu mask as the designated reader. 44249de0493SThomas Gleixner */ 44349de0493SThomas Gleixner target = cpumask_any_and(&cstate_pkg_cpu_mask, 444cb63ba0fSKan Liang topology_die_cpumask(cpu)); 44549de0493SThomas Gleixner if (has_cstate_pkg && target >= nr_cpu_ids) 4466aec1ad7SBorislav Petkov cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask); 4476aec1ad7SBorislav Petkov 44877c34ef1SSebastian Andrzej Siewior return 0; 4496aec1ad7SBorislav Petkov } 450c7afba32SThomas Gleixner 451d9f3b450SValdis Klētnieks static const struct attribute_group *core_attr_update[] = { 4528f2a28c5SJiri Olsa &group_cstate_core_c1, 4538f2a28c5SJiri Olsa &group_cstate_core_c3, 4548f2a28c5SJiri Olsa &group_cstate_core_c6, 4558f2a28c5SJiri Olsa &group_cstate_core_c7, 4568f2a28c5SJiri Olsa NULL, 4578f2a28c5SJiri Olsa }; 4588f2a28c5SJiri Olsa 459d9f3b450SValdis Klētnieks static const struct attribute_group *pkg_attr_update[] = { 4608f2a28c5SJiri Olsa &group_cstate_pkg_c2, 4618f2a28c5SJiri Olsa &group_cstate_pkg_c3, 4628f2a28c5SJiri Olsa &group_cstate_pkg_c6, 4638f2a28c5SJiri Olsa &group_cstate_pkg_c7, 4648f2a28c5SJiri Olsa &group_cstate_pkg_c8, 4658f2a28c5SJiri Olsa &group_cstate_pkg_c9, 4668f2a28c5SJiri Olsa &group_cstate_pkg_c10, 4678f2a28c5SJiri Olsa NULL, 4688f2a28c5SJiri Olsa }; 4698f2a28c5SJiri Olsa 470424646eeSThomas Gleixner static struct pmu cstate_core_pmu = { 471424646eeSThomas Gleixner .attr_groups = core_attr_groups, 4728f2a28c5SJiri Olsa .attr_update = core_attr_update, 473424646eeSThomas Gleixner .name = "cstate_core", 474424646eeSThomas Gleixner .task_ctx_nr = perf_invalid_context, 475424646eeSThomas Gleixner .event_init = cstate_pmu_event_init, 476424646eeSThomas Gleixner .add = cstate_pmu_event_add, 477424646eeSThomas Gleixner .del = cstate_pmu_event_del, 478424646eeSThomas Gleixner .start = cstate_pmu_event_start, 479424646eeSThomas Gleixner .stop = cstate_pmu_event_stop, 480424646eeSThomas Gleixner .read = cstate_pmu_event_update, 4812ff40250SAndrew Murray .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 48274545f63SDavid Carrillo-Cisneros .module = THIS_MODULE, 483424646eeSThomas Gleixner }; 484424646eeSThomas Gleixner 485424646eeSThomas Gleixner static struct pmu cstate_pkg_pmu = { 486424646eeSThomas Gleixner .attr_groups = pkg_attr_groups, 4878f2a28c5SJiri Olsa .attr_update = pkg_attr_update, 488424646eeSThomas Gleixner .name = "cstate_pkg", 489424646eeSThomas Gleixner .task_ctx_nr = perf_invalid_context, 490424646eeSThomas Gleixner .event_init = cstate_pmu_event_init, 491424646eeSThomas Gleixner .add = cstate_pmu_event_add, 492424646eeSThomas Gleixner .del = cstate_pmu_event_del, 493424646eeSThomas Gleixner .start = cstate_pmu_event_start, 494424646eeSThomas Gleixner .stop = cstate_pmu_event_stop, 495424646eeSThomas Gleixner .read = cstate_pmu_event_update, 4962ff40250SAndrew Murray .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, 49774545f63SDavid Carrillo-Cisneros .module = THIS_MODULE, 498424646eeSThomas Gleixner }; 499424646eeSThomas Gleixner 500424646eeSThomas Gleixner static const struct cstate_model nhm_cstates __initconst = { 501424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 502424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES), 503424646eeSThomas Gleixner 504424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) | 505424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C6_RES) | 506424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C7_RES), 507424646eeSThomas Gleixner }; 508424646eeSThomas Gleixner 509424646eeSThomas Gleixner static const struct cstate_model snb_cstates __initconst = { 510424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 511424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES) | 512424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C7_RES), 513424646eeSThomas Gleixner 514424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 515424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C3_RES) | 516424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C6_RES) | 517424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C7_RES), 518424646eeSThomas Gleixner }; 519424646eeSThomas Gleixner 520424646eeSThomas Gleixner static const struct cstate_model hswult_cstates __initconst = { 521424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | 522424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES) | 523424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C7_RES), 524424646eeSThomas Gleixner 525424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 526424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C3_RES) | 527424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C6_RES) | 528424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C7_RES) | 529424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C8_RES) | 530424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C9_RES) | 531424646eeSThomas Gleixner BIT(PERF_CSTATE_PKG_C10_RES), 532424646eeSThomas Gleixner }; 533424646eeSThomas Gleixner 5341159e094SHarry Pan static const struct cstate_model cnl_cstates __initconst = { 5351159e094SHarry Pan .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 5361159e094SHarry Pan BIT(PERF_CSTATE_CORE_C3_RES) | 5371159e094SHarry Pan BIT(PERF_CSTATE_CORE_C6_RES) | 5381159e094SHarry Pan BIT(PERF_CSTATE_CORE_C7_RES), 5391159e094SHarry Pan 5401159e094SHarry Pan .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 5411159e094SHarry Pan BIT(PERF_CSTATE_PKG_C3_RES) | 5421159e094SHarry Pan BIT(PERF_CSTATE_PKG_C6_RES) | 5431159e094SHarry Pan BIT(PERF_CSTATE_PKG_C7_RES) | 5441159e094SHarry Pan BIT(PERF_CSTATE_PKG_C8_RES) | 5451159e094SHarry Pan BIT(PERF_CSTATE_PKG_C9_RES) | 5461159e094SHarry Pan BIT(PERF_CSTATE_PKG_C10_RES), 5471159e094SHarry Pan }; 5481159e094SHarry Pan 549424646eeSThomas Gleixner static const struct cstate_model slm_cstates __initconst = { 550424646eeSThomas Gleixner .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 551424646eeSThomas Gleixner BIT(PERF_CSTATE_CORE_C6_RES), 552424646eeSThomas Gleixner 553424646eeSThomas Gleixner .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), 554424646eeSThomas Gleixner .quirks = SLM_PKG_C6_USE_C7_MSR, 555424646eeSThomas Gleixner }; 556424646eeSThomas Gleixner 557889882bcSLukasz Odzioba 558889882bcSLukasz Odzioba static const struct cstate_model knl_cstates __initconst = { 559889882bcSLukasz Odzioba .core_events = BIT(PERF_CSTATE_CORE_C6_RES), 560889882bcSLukasz Odzioba 561889882bcSLukasz Odzioba .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 562889882bcSLukasz Odzioba BIT(PERF_CSTATE_PKG_C3_RES) | 563889882bcSLukasz Odzioba BIT(PERF_CSTATE_PKG_C6_RES), 564889882bcSLukasz Odzioba .quirks = KNL_CORE_C6_MSR, 565889882bcSLukasz Odzioba }; 566889882bcSLukasz Odzioba 567889882bcSLukasz Odzioba 5685c10b048SHarry Pan static const struct cstate_model glm_cstates __initconst = { 5695c10b048SHarry Pan .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 5705c10b048SHarry Pan BIT(PERF_CSTATE_CORE_C3_RES) | 5715c10b048SHarry Pan BIT(PERF_CSTATE_CORE_C6_RES), 5725c10b048SHarry Pan 5735c10b048SHarry Pan .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 5745c10b048SHarry Pan BIT(PERF_CSTATE_PKG_C3_RES) | 5755c10b048SHarry Pan BIT(PERF_CSTATE_PKG_C6_RES) | 5765c10b048SHarry Pan BIT(PERF_CSTATE_PKG_C10_RES), 5775c10b048SHarry Pan }; 5785c10b048SHarry Pan 579889882bcSLukasz Odzioba 580424646eeSThomas Gleixner #define X86_CSTATES_MODEL(model, states) \ 581424646eeSThomas Gleixner { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) } 582424646eeSThomas Gleixner 583424646eeSThomas Gleixner static const struct x86_cpu_id intel_cstates_match[] __initconst = { 584bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM, nhm_cstates), 585bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EP, nhm_cstates), 586bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EX, nhm_cstates), 587424646eeSThomas Gleixner 588bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE, nhm_cstates), 589bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EP, nhm_cstates), 590bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EX, nhm_cstates), 591424646eeSThomas Gleixner 592bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE, snb_cstates), 593bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE_X, snb_cstates), 594424646eeSThomas Gleixner 595bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE, snb_cstates), 596bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates), 597424646eeSThomas Gleixner 598c66f78a6SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_HASWELL, snb_cstates), 599bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates), 6005e741407SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_G, snb_cstates), 601424646eeSThomas Gleixner 602af239c44SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_L, hswult_cstates), 603424646eeSThomas Gleixner 604f2c4db1bSPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates), 6055ebb34edSPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_D, slm_cstates), 606bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates), 607424646eeSThomas Gleixner 608c66f78a6SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL, snb_cstates), 6095ebb34edSPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_D, snb_cstates), 6105e741407SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_G, snb_cstates), 611bf4ad541SDave Hansen X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X, snb_cstates), 612424646eeSThomas Gleixner 613af239c44SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_L, snb_cstates), 614c66f78a6SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE, snb_cstates), 615b09c146fSKan Liang X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates), 616889882bcSLukasz Odzioba 617af239c44SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates), 618c66f78a6SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE, hswult_cstates), 6191ffa6c04SKan Liang X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE_L, hswult_cstates), 6201ffa6c04SKan Liang X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE, hswult_cstates), 621f2029b1eSSrinivas Pandruvada 622af239c44SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates), 6231159e094SHarry Pan 624889882bcSLukasz Odzioba X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), 6251dba23b1SPiotr Luc X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), 6265c10b048SHarry Pan 6275c10b048SHarry Pan X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates), 6285ebb34edSPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates), 629b09c146fSKan Liang 630f2c4db1bSPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates), 631f08c47d1SKan Liang 632af239c44SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates), 633c66f78a6SPeter Zijlstra X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates), 634424646eeSThomas Gleixner { }, 635424646eeSThomas Gleixner }; 636424646eeSThomas Gleixner MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); 637424646eeSThomas Gleixner 638424646eeSThomas Gleixner static int __init cstate_probe(const struct cstate_model *cm) 6396aec1ad7SBorislav Petkov { 6406aec1ad7SBorislav Petkov /* SLM has different MSR for PKG C6 */ 641424646eeSThomas Gleixner if (cm->quirks & SLM_PKG_C6_USE_C7_MSR) 6426aec1ad7SBorislav Petkov pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY; 6436aec1ad7SBorislav Petkov 644889882bcSLukasz Odzioba /* KNL has different MSR for CORE C6 */ 645889882bcSLukasz Odzioba if (cm->quirks & KNL_CORE_C6_MSR) 646889882bcSLukasz Odzioba pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY; 647889882bcSLukasz Odzioba 648889882bcSLukasz Odzioba 6498f2a28c5SJiri Olsa core_msr_mask = perf_msr_probe(core_msr, PERF_CSTATE_CORE_EVENT_MAX, 6508f2a28c5SJiri Olsa true, (void *) &cm->core_events); 6516aec1ad7SBorislav Petkov 6528f2a28c5SJiri Olsa pkg_msr_mask = perf_msr_probe(pkg_msr, PERF_CSTATE_PKG_EVENT_MAX, 6538f2a28c5SJiri Olsa true, (void *) &cm->pkg_events); 6548f2a28c5SJiri Olsa 6558f2a28c5SJiri Olsa has_cstate_core = !!core_msr_mask; 6568f2a28c5SJiri Olsa has_cstate_pkg = !!pkg_msr_mask; 6576aec1ad7SBorislav Petkov 6586aec1ad7SBorislav Petkov return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV; 6596aec1ad7SBorislav Petkov } 6606aec1ad7SBorislav Petkov 661c7afba32SThomas Gleixner static inline void cstate_cleanup(void) 6626aec1ad7SBorislav Petkov { 663834fcd29SThomas Gleixner cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE); 664834fcd29SThomas Gleixner cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING); 665834fcd29SThomas Gleixner 666d29859e7SThomas Gleixner if (has_cstate_core) 667d29859e7SThomas Gleixner perf_pmu_unregister(&cstate_core_pmu); 668d29859e7SThomas Gleixner 669d29859e7SThomas Gleixner if (has_cstate_pkg) 670d29859e7SThomas Gleixner perf_pmu_unregister(&cstate_pkg_pmu); 671d29859e7SThomas Gleixner } 672d29859e7SThomas Gleixner 673d29859e7SThomas Gleixner static int __init cstate_init(void) 674d29859e7SThomas Gleixner { 67577c34ef1SSebastian Andrzej Siewior int err; 6766aec1ad7SBorislav Petkov 67777c34ef1SSebastian Andrzej Siewior cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING, 678834fcd29SThomas Gleixner "perf/x86/cstate:starting", cstate_cpu_init, NULL); 67977c34ef1SSebastian Andrzej Siewior cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE, 680834fcd29SThomas Gleixner "perf/x86/cstate:online", NULL, cstate_cpu_exit); 6816aec1ad7SBorislav Petkov 6826aec1ad7SBorislav Petkov if (has_cstate_core) { 6836aec1ad7SBorislav Petkov err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1); 684d29859e7SThomas Gleixner if (err) { 685d29859e7SThomas Gleixner has_cstate_core = false; 686d29859e7SThomas Gleixner pr_info("Failed to register cstate core pmu\n"); 687834fcd29SThomas Gleixner cstate_cleanup(); 68877c34ef1SSebastian Andrzej Siewior return err; 689d29859e7SThomas Gleixner } 6906aec1ad7SBorislav Petkov } 6916aec1ad7SBorislav Petkov 6926aec1ad7SBorislav Petkov if (has_cstate_pkg) { 693cb63ba0fSKan Liang if (topology_max_die_per_package() > 1) { 694cb63ba0fSKan Liang err = perf_pmu_register(&cstate_pkg_pmu, 695cb63ba0fSKan Liang "cstate_die", -1); 696cb63ba0fSKan Liang } else { 697cb63ba0fSKan Liang err = perf_pmu_register(&cstate_pkg_pmu, 698cb63ba0fSKan Liang cstate_pkg_pmu.name, -1); 699cb63ba0fSKan Liang } 700d29859e7SThomas Gleixner if (err) { 701d29859e7SThomas Gleixner has_cstate_pkg = false; 702d29859e7SThomas Gleixner pr_info("Failed to register cstate pkg pmu\n"); 703d29859e7SThomas Gleixner cstate_cleanup(); 70477c34ef1SSebastian Andrzej Siewior return err; 7056aec1ad7SBorislav Petkov } 7066aec1ad7SBorislav Petkov } 707834fcd29SThomas Gleixner return 0; 708d29859e7SThomas Gleixner } 7096aec1ad7SBorislav Petkov 7106aec1ad7SBorislav Petkov static int __init cstate_pmu_init(void) 7116aec1ad7SBorislav Petkov { 712424646eeSThomas Gleixner const struct x86_cpu_id *id; 7136aec1ad7SBorislav Petkov int err; 7146aec1ad7SBorislav Petkov 715424646eeSThomas Gleixner if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 7166aec1ad7SBorislav Petkov return -ENODEV; 7176aec1ad7SBorislav Petkov 718424646eeSThomas Gleixner id = x86_match_cpu(intel_cstates_match); 719424646eeSThomas Gleixner if (!id) 720424646eeSThomas Gleixner return -ENODEV; 721424646eeSThomas Gleixner 722424646eeSThomas Gleixner err = cstate_probe((const struct cstate_model *) id->driver_data); 7236aec1ad7SBorislav Petkov if (err) 7246aec1ad7SBorislav Petkov return err; 7256aec1ad7SBorislav Petkov 726d29859e7SThomas Gleixner return cstate_init(); 7276aec1ad7SBorislav Petkov } 728c7afba32SThomas Gleixner module_init(cstate_pmu_init); 729c7afba32SThomas Gleixner 730c7afba32SThomas Gleixner static void __exit cstate_pmu_exit(void) 731c7afba32SThomas Gleixner { 732c7afba32SThomas Gleixner cstate_cleanup(); 733c7afba32SThomas Gleixner } 734c7afba32SThomas Gleixner module_exit(cstate_pmu_exit); 735