1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/hardirq.h> 21 #include <asm/intel-family.h> 22 #include <asm/intel_pt.h> 23 #include <asm/apic.h> 24 #include <asm/cpu_device_id.h> 25 26 #include "../perf_event.h" 27 28 /* 29 * Intel PerfMon, used on Core and later. 30 */ 31 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 32 { 33 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 34 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 35 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 36 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 37 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 38 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 39 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 40 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 41 }; 42 43 static struct event_constraint intel_core_event_constraints[] __read_mostly = 44 { 45 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 46 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 47 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 48 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 49 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 50 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 51 EVENT_CONSTRAINT_END 52 }; 53 54 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 55 { 56 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 57 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 58 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 59 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 60 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 61 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 62 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 63 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 64 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 65 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 66 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 67 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 68 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 69 EVENT_CONSTRAINT_END 70 }; 71 72 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 73 { 74 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 75 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 76 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 77 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 78 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 79 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 80 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 81 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 82 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 83 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 84 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 85 EVENT_CONSTRAINT_END 86 }; 87 88 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 89 { 90 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 91 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 92 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 93 EVENT_EXTRA_END 94 }; 95 96 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 97 { 98 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 99 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 100 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 101 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 102 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 103 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 104 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 105 EVENT_CONSTRAINT_END 106 }; 107 108 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 109 { 110 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 111 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 112 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 114 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 116 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 117 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 119 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 120 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 121 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 122 123 /* 124 * When HT is off these events can only run on the bottom 4 counters 125 * When HT is on, they are impacted by the HT bug and require EXCL access 126 */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 131 132 EVENT_CONSTRAINT_END 133 }; 134 135 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 136 { 137 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 138 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 139 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 140 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 141 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 142 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 143 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 145 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 150 151 /* 152 * When HT is off these events can only run on the bottom 4 counters 153 * When HT is on, they are impacted by the HT bug and require EXCL access 154 */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 159 160 EVENT_CONSTRAINT_END 161 }; 162 163 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 164 { 165 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 166 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 167 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 169 EVENT_EXTRA_END 170 }; 171 172 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 173 { 174 EVENT_CONSTRAINT_END 175 }; 176 177 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 178 { 179 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 180 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 181 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 182 EVENT_CONSTRAINT_END 183 }; 184 185 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 186 { 187 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 188 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 189 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 190 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 191 FIXED_EVENT_CONSTRAINT(0x0500, 4), 192 FIXED_EVENT_CONSTRAINT(0x0600, 5), 193 FIXED_EVENT_CONSTRAINT(0x0700, 6), 194 FIXED_EVENT_CONSTRAINT(0x0800, 7), 195 FIXED_EVENT_CONSTRAINT(0x0900, 8), 196 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 197 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 198 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 199 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 200 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 201 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 202 FIXED_EVENT_CONSTRAINT(0x1000, 15), 203 EVENT_CONSTRAINT_END 204 }; 205 206 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 207 { 208 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 210 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 211 EVENT_CONSTRAINT_END 212 }; 213 214 static struct event_constraint intel_skl_event_constraints[] = { 215 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 216 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 217 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 218 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 219 220 /* 221 * when HT is off, these can only run on the bottom 4 counters 222 */ 223 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 224 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 225 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 226 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 227 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 228 229 EVENT_CONSTRAINT_END 230 }; 231 232 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 235 EVENT_EXTRA_END 236 }; 237 238 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 239 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 240 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 241 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 242 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 243 EVENT_EXTRA_END 244 }; 245 246 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 247 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 248 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 249 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 250 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 251 EVENT_EXTRA_END 252 }; 253 254 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 255 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 256 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 257 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 258 /* 259 * Note the low 8 bits eventsel code is not a continuous field, containing 260 * some #GPing bits. These are masked out. 261 */ 262 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 263 EVENT_EXTRA_END 264 }; 265 266 static struct event_constraint intel_icl_event_constraints[] = { 267 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 268 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 269 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 270 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 271 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 272 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 273 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 274 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 275 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 276 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 277 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 278 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 279 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 280 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 281 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 282 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 283 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 284 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 285 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 286 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 287 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 288 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 289 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 290 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 291 EVENT_CONSTRAINT_END 292 }; 293 294 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 295 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 296 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 297 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 298 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 299 EVENT_EXTRA_END 300 }; 301 302 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 303 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 304 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 305 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 306 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 307 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 308 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 309 EVENT_EXTRA_END 310 }; 311 312 static struct event_constraint intel_spr_event_constraints[] = { 313 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 314 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 315 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 316 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 317 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 318 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 319 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 320 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 321 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 322 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 323 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 324 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 325 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 326 327 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 328 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 329 /* 330 * Generally event codes < 0x90 are restricted to counters 0-3. 331 * The 0x2E and 0x3C are exception, which has no restriction. 332 */ 333 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 334 335 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 336 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 337 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 338 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 339 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 340 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 341 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 342 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 343 /* 344 * Generally event codes >= 0x90 are likely to have no restrictions. 345 * The exception are defined as above. 346 */ 347 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 348 349 EVENT_CONSTRAINT_END 350 }; 351 352 353 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 354 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 355 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 356 357 static struct attribute *nhm_mem_events_attrs[] = { 358 EVENT_PTR(mem_ld_nhm), 359 NULL, 360 }; 361 362 /* 363 * topdown events for Intel Core CPUs. 364 * 365 * The events are all in slots, which is a free slot in a 4 wide 366 * pipeline. Some events are already reported in slots, for cycle 367 * events we multiply by the pipeline width (4). 368 * 369 * With Hyper Threading on, topdown metrics are either summed or averaged 370 * between the threads of a core: (count_t0 + count_t1). 371 * 372 * For the average case the metric is always scaled to pipeline width, 373 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 374 */ 375 376 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 377 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 378 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 379 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 380 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 381 "event=0xe,umask=0x1"); /* uops_issued.any */ 382 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 383 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 384 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 385 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 386 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 387 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 388 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 389 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 390 "4", "2"); 391 392 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 393 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 394 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 395 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 396 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 397 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 398 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 399 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 400 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 401 402 static struct attribute *snb_events_attrs[] = { 403 EVENT_PTR(td_slots_issued), 404 EVENT_PTR(td_slots_retired), 405 EVENT_PTR(td_fetch_bubbles), 406 EVENT_PTR(td_total_slots), 407 EVENT_PTR(td_total_slots_scale), 408 EVENT_PTR(td_recovery_bubbles), 409 EVENT_PTR(td_recovery_bubbles_scale), 410 NULL, 411 }; 412 413 static struct attribute *snb_mem_events_attrs[] = { 414 EVENT_PTR(mem_ld_snb), 415 EVENT_PTR(mem_st_snb), 416 NULL, 417 }; 418 419 static struct event_constraint intel_hsw_event_constraints[] = { 420 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 421 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 422 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 423 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 424 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 425 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 426 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 427 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 428 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 429 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 430 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 431 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 432 433 /* 434 * When HT is off these events can only run on the bottom 4 counters 435 * When HT is on, they are impacted by the HT bug and require EXCL access 436 */ 437 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 438 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 439 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 440 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 441 442 EVENT_CONSTRAINT_END 443 }; 444 445 static struct event_constraint intel_bdw_event_constraints[] = { 446 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 447 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 448 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 449 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 450 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 451 /* 452 * when HT is off, these can only run on the bottom 4 counters 453 */ 454 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 455 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 456 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 457 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 458 EVENT_CONSTRAINT_END 459 }; 460 461 static u64 intel_pmu_event_map(int hw_event) 462 { 463 return intel_perfmon_event_map[hw_event]; 464 } 465 466 static __initconst const u64 spr_hw_cache_event_ids 467 [PERF_COUNT_HW_CACHE_MAX] 468 [PERF_COUNT_HW_CACHE_OP_MAX] 469 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 470 { 471 [ C(L1D ) ] = { 472 [ C(OP_READ) ] = { 473 [ C(RESULT_ACCESS) ] = 0x81d0, 474 [ C(RESULT_MISS) ] = 0xe124, 475 }, 476 [ C(OP_WRITE) ] = { 477 [ C(RESULT_ACCESS) ] = 0x82d0, 478 }, 479 }, 480 [ C(L1I ) ] = { 481 [ C(OP_READ) ] = { 482 [ C(RESULT_MISS) ] = 0xe424, 483 }, 484 [ C(OP_WRITE) ] = { 485 [ C(RESULT_ACCESS) ] = -1, 486 [ C(RESULT_MISS) ] = -1, 487 }, 488 }, 489 [ C(LL ) ] = { 490 [ C(OP_READ) ] = { 491 [ C(RESULT_ACCESS) ] = 0x12a, 492 [ C(RESULT_MISS) ] = 0x12a, 493 }, 494 [ C(OP_WRITE) ] = { 495 [ C(RESULT_ACCESS) ] = 0x12a, 496 [ C(RESULT_MISS) ] = 0x12a, 497 }, 498 }, 499 [ C(DTLB) ] = { 500 [ C(OP_READ) ] = { 501 [ C(RESULT_ACCESS) ] = 0x81d0, 502 [ C(RESULT_MISS) ] = 0xe12, 503 }, 504 [ C(OP_WRITE) ] = { 505 [ C(RESULT_ACCESS) ] = 0x82d0, 506 [ C(RESULT_MISS) ] = 0xe13, 507 }, 508 }, 509 [ C(ITLB) ] = { 510 [ C(OP_READ) ] = { 511 [ C(RESULT_ACCESS) ] = -1, 512 [ C(RESULT_MISS) ] = 0xe11, 513 }, 514 [ C(OP_WRITE) ] = { 515 [ C(RESULT_ACCESS) ] = -1, 516 [ C(RESULT_MISS) ] = -1, 517 }, 518 [ C(OP_PREFETCH) ] = { 519 [ C(RESULT_ACCESS) ] = -1, 520 [ C(RESULT_MISS) ] = -1, 521 }, 522 }, 523 [ C(BPU ) ] = { 524 [ C(OP_READ) ] = { 525 [ C(RESULT_ACCESS) ] = 0x4c4, 526 [ C(RESULT_MISS) ] = 0x4c5, 527 }, 528 [ C(OP_WRITE) ] = { 529 [ C(RESULT_ACCESS) ] = -1, 530 [ C(RESULT_MISS) ] = -1, 531 }, 532 [ C(OP_PREFETCH) ] = { 533 [ C(RESULT_ACCESS) ] = -1, 534 [ C(RESULT_MISS) ] = -1, 535 }, 536 }, 537 [ C(NODE) ] = { 538 [ C(OP_READ) ] = { 539 [ C(RESULT_ACCESS) ] = 0x12a, 540 [ C(RESULT_MISS) ] = 0x12a, 541 }, 542 }, 543 }; 544 545 static __initconst const u64 spr_hw_cache_extra_regs 546 [PERF_COUNT_HW_CACHE_MAX] 547 [PERF_COUNT_HW_CACHE_OP_MAX] 548 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 549 { 550 [ C(LL ) ] = { 551 [ C(OP_READ) ] = { 552 [ C(RESULT_ACCESS) ] = 0x10001, 553 [ C(RESULT_MISS) ] = 0x3fbfc00001, 554 }, 555 [ C(OP_WRITE) ] = { 556 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 557 [ C(RESULT_MISS) ] = 0x3f3fc00002, 558 }, 559 }, 560 [ C(NODE) ] = { 561 [ C(OP_READ) ] = { 562 [ C(RESULT_ACCESS) ] = 0x10c000001, 563 [ C(RESULT_MISS) ] = 0x3fb3000001, 564 }, 565 }, 566 }; 567 568 /* 569 * Notes on the events: 570 * - data reads do not include code reads (comparable to earlier tables) 571 * - data counts include speculative execution (except L1 write, dtlb, bpu) 572 * - remote node access includes remote memory, remote cache, remote mmio. 573 * - prefetches are not included in the counts. 574 * - icache miss does not include decoded icache 575 */ 576 577 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 578 #define SKL_DEMAND_RFO BIT_ULL(1) 579 #define SKL_ANY_RESPONSE BIT_ULL(16) 580 #define SKL_SUPPLIER_NONE BIT_ULL(17) 581 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 582 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 583 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 584 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 585 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 586 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 587 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 588 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 589 #define SKL_SPL_HIT BIT_ULL(30) 590 #define SKL_SNOOP_NONE BIT_ULL(31) 591 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 592 #define SKL_SNOOP_MISS BIT_ULL(33) 593 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 594 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 595 #define SKL_SNOOP_HITM BIT_ULL(36) 596 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 597 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 598 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 599 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 600 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 601 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 602 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 603 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 604 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 605 SKL_SNOOP_HITM|SKL_SPL_HIT) 606 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 607 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 608 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 609 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 610 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 611 612 static __initconst const u64 skl_hw_cache_event_ids 613 [PERF_COUNT_HW_CACHE_MAX] 614 [PERF_COUNT_HW_CACHE_OP_MAX] 615 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 616 { 617 [ C(L1D ) ] = { 618 [ C(OP_READ) ] = { 619 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 620 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 621 }, 622 [ C(OP_WRITE) ] = { 623 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 624 [ C(RESULT_MISS) ] = 0x0, 625 }, 626 [ C(OP_PREFETCH) ] = { 627 [ C(RESULT_ACCESS) ] = 0x0, 628 [ C(RESULT_MISS) ] = 0x0, 629 }, 630 }, 631 [ C(L1I ) ] = { 632 [ C(OP_READ) ] = { 633 [ C(RESULT_ACCESS) ] = 0x0, 634 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 635 }, 636 [ C(OP_WRITE) ] = { 637 [ C(RESULT_ACCESS) ] = -1, 638 [ C(RESULT_MISS) ] = -1, 639 }, 640 [ C(OP_PREFETCH) ] = { 641 [ C(RESULT_ACCESS) ] = 0x0, 642 [ C(RESULT_MISS) ] = 0x0, 643 }, 644 }, 645 [ C(LL ) ] = { 646 [ C(OP_READ) ] = { 647 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 648 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 649 }, 650 [ C(OP_WRITE) ] = { 651 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 652 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 653 }, 654 [ C(OP_PREFETCH) ] = { 655 [ C(RESULT_ACCESS) ] = 0x0, 656 [ C(RESULT_MISS) ] = 0x0, 657 }, 658 }, 659 [ C(DTLB) ] = { 660 [ C(OP_READ) ] = { 661 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 662 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 663 }, 664 [ C(OP_WRITE) ] = { 665 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 666 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 667 }, 668 [ C(OP_PREFETCH) ] = { 669 [ C(RESULT_ACCESS) ] = 0x0, 670 [ C(RESULT_MISS) ] = 0x0, 671 }, 672 }, 673 [ C(ITLB) ] = { 674 [ C(OP_READ) ] = { 675 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 676 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 677 }, 678 [ C(OP_WRITE) ] = { 679 [ C(RESULT_ACCESS) ] = -1, 680 [ C(RESULT_MISS) ] = -1, 681 }, 682 [ C(OP_PREFETCH) ] = { 683 [ C(RESULT_ACCESS) ] = -1, 684 [ C(RESULT_MISS) ] = -1, 685 }, 686 }, 687 [ C(BPU ) ] = { 688 [ C(OP_READ) ] = { 689 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 690 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 691 }, 692 [ C(OP_WRITE) ] = { 693 [ C(RESULT_ACCESS) ] = -1, 694 [ C(RESULT_MISS) ] = -1, 695 }, 696 [ C(OP_PREFETCH) ] = { 697 [ C(RESULT_ACCESS) ] = -1, 698 [ C(RESULT_MISS) ] = -1, 699 }, 700 }, 701 [ C(NODE) ] = { 702 [ C(OP_READ) ] = { 703 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 704 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 705 }, 706 [ C(OP_WRITE) ] = { 707 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 708 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 709 }, 710 [ C(OP_PREFETCH) ] = { 711 [ C(RESULT_ACCESS) ] = 0x0, 712 [ C(RESULT_MISS) ] = 0x0, 713 }, 714 }, 715 }; 716 717 static __initconst const u64 skl_hw_cache_extra_regs 718 [PERF_COUNT_HW_CACHE_MAX] 719 [PERF_COUNT_HW_CACHE_OP_MAX] 720 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 721 { 722 [ C(LL ) ] = { 723 [ C(OP_READ) ] = { 724 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 725 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 726 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 727 SKL_L3_MISS|SKL_ANY_SNOOP| 728 SKL_SUPPLIER_NONE, 729 }, 730 [ C(OP_WRITE) ] = { 731 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 732 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 733 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 734 SKL_L3_MISS|SKL_ANY_SNOOP| 735 SKL_SUPPLIER_NONE, 736 }, 737 [ C(OP_PREFETCH) ] = { 738 [ C(RESULT_ACCESS) ] = 0x0, 739 [ C(RESULT_MISS) ] = 0x0, 740 }, 741 }, 742 [ C(NODE) ] = { 743 [ C(OP_READ) ] = { 744 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 745 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 746 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 747 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 748 }, 749 [ C(OP_WRITE) ] = { 750 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 751 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 752 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 753 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 754 }, 755 [ C(OP_PREFETCH) ] = { 756 [ C(RESULT_ACCESS) ] = 0x0, 757 [ C(RESULT_MISS) ] = 0x0, 758 }, 759 }, 760 }; 761 762 #define SNB_DMND_DATA_RD (1ULL << 0) 763 #define SNB_DMND_RFO (1ULL << 1) 764 #define SNB_DMND_IFETCH (1ULL << 2) 765 #define SNB_DMND_WB (1ULL << 3) 766 #define SNB_PF_DATA_RD (1ULL << 4) 767 #define SNB_PF_RFO (1ULL << 5) 768 #define SNB_PF_IFETCH (1ULL << 6) 769 #define SNB_LLC_DATA_RD (1ULL << 7) 770 #define SNB_LLC_RFO (1ULL << 8) 771 #define SNB_LLC_IFETCH (1ULL << 9) 772 #define SNB_BUS_LOCKS (1ULL << 10) 773 #define SNB_STRM_ST (1ULL << 11) 774 #define SNB_OTHER (1ULL << 15) 775 #define SNB_RESP_ANY (1ULL << 16) 776 #define SNB_NO_SUPP (1ULL << 17) 777 #define SNB_LLC_HITM (1ULL << 18) 778 #define SNB_LLC_HITE (1ULL << 19) 779 #define SNB_LLC_HITS (1ULL << 20) 780 #define SNB_LLC_HITF (1ULL << 21) 781 #define SNB_LOCAL (1ULL << 22) 782 #define SNB_REMOTE (0xffULL << 23) 783 #define SNB_SNP_NONE (1ULL << 31) 784 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 785 #define SNB_SNP_MISS (1ULL << 33) 786 #define SNB_NO_FWD (1ULL << 34) 787 #define SNB_SNP_FWD (1ULL << 35) 788 #define SNB_HITM (1ULL << 36) 789 #define SNB_NON_DRAM (1ULL << 37) 790 791 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 792 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 793 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 794 795 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 796 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 797 SNB_HITM) 798 799 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 800 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 801 802 #define SNB_L3_ACCESS SNB_RESP_ANY 803 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 804 805 static __initconst const u64 snb_hw_cache_extra_regs 806 [PERF_COUNT_HW_CACHE_MAX] 807 [PERF_COUNT_HW_CACHE_OP_MAX] 808 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 809 { 810 [ C(LL ) ] = { 811 [ C(OP_READ) ] = { 812 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 813 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 814 }, 815 [ C(OP_WRITE) ] = { 816 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 817 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 818 }, 819 [ C(OP_PREFETCH) ] = { 820 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 821 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 822 }, 823 }, 824 [ C(NODE) ] = { 825 [ C(OP_READ) ] = { 826 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 827 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 828 }, 829 [ C(OP_WRITE) ] = { 830 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 831 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 832 }, 833 [ C(OP_PREFETCH) ] = { 834 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 835 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 836 }, 837 }, 838 }; 839 840 static __initconst const u64 snb_hw_cache_event_ids 841 [PERF_COUNT_HW_CACHE_MAX] 842 [PERF_COUNT_HW_CACHE_OP_MAX] 843 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 844 { 845 [ C(L1D) ] = { 846 [ C(OP_READ) ] = { 847 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 848 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 849 }, 850 [ C(OP_WRITE) ] = { 851 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 852 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 853 }, 854 [ C(OP_PREFETCH) ] = { 855 [ C(RESULT_ACCESS) ] = 0x0, 856 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 857 }, 858 }, 859 [ C(L1I ) ] = { 860 [ C(OP_READ) ] = { 861 [ C(RESULT_ACCESS) ] = 0x0, 862 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 863 }, 864 [ C(OP_WRITE) ] = { 865 [ C(RESULT_ACCESS) ] = -1, 866 [ C(RESULT_MISS) ] = -1, 867 }, 868 [ C(OP_PREFETCH) ] = { 869 [ C(RESULT_ACCESS) ] = 0x0, 870 [ C(RESULT_MISS) ] = 0x0, 871 }, 872 }, 873 [ C(LL ) ] = { 874 [ C(OP_READ) ] = { 875 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 876 [ C(RESULT_ACCESS) ] = 0x01b7, 877 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 878 [ C(RESULT_MISS) ] = 0x01b7, 879 }, 880 [ C(OP_WRITE) ] = { 881 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 882 [ C(RESULT_ACCESS) ] = 0x01b7, 883 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 884 [ C(RESULT_MISS) ] = 0x01b7, 885 }, 886 [ C(OP_PREFETCH) ] = { 887 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 888 [ C(RESULT_ACCESS) ] = 0x01b7, 889 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 890 [ C(RESULT_MISS) ] = 0x01b7, 891 }, 892 }, 893 [ C(DTLB) ] = { 894 [ C(OP_READ) ] = { 895 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 896 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 897 }, 898 [ C(OP_WRITE) ] = { 899 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 900 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 901 }, 902 [ C(OP_PREFETCH) ] = { 903 [ C(RESULT_ACCESS) ] = 0x0, 904 [ C(RESULT_MISS) ] = 0x0, 905 }, 906 }, 907 [ C(ITLB) ] = { 908 [ C(OP_READ) ] = { 909 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 910 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 911 }, 912 [ C(OP_WRITE) ] = { 913 [ C(RESULT_ACCESS) ] = -1, 914 [ C(RESULT_MISS) ] = -1, 915 }, 916 [ C(OP_PREFETCH) ] = { 917 [ C(RESULT_ACCESS) ] = -1, 918 [ C(RESULT_MISS) ] = -1, 919 }, 920 }, 921 [ C(BPU ) ] = { 922 [ C(OP_READ) ] = { 923 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 924 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 925 }, 926 [ C(OP_WRITE) ] = { 927 [ C(RESULT_ACCESS) ] = -1, 928 [ C(RESULT_MISS) ] = -1, 929 }, 930 [ C(OP_PREFETCH) ] = { 931 [ C(RESULT_ACCESS) ] = -1, 932 [ C(RESULT_MISS) ] = -1, 933 }, 934 }, 935 [ C(NODE) ] = { 936 [ C(OP_READ) ] = { 937 [ C(RESULT_ACCESS) ] = 0x01b7, 938 [ C(RESULT_MISS) ] = 0x01b7, 939 }, 940 [ C(OP_WRITE) ] = { 941 [ C(RESULT_ACCESS) ] = 0x01b7, 942 [ C(RESULT_MISS) ] = 0x01b7, 943 }, 944 [ C(OP_PREFETCH) ] = { 945 [ C(RESULT_ACCESS) ] = 0x01b7, 946 [ C(RESULT_MISS) ] = 0x01b7, 947 }, 948 }, 949 950 }; 951 952 /* 953 * Notes on the events: 954 * - data reads do not include code reads (comparable to earlier tables) 955 * - data counts include speculative execution (except L1 write, dtlb, bpu) 956 * - remote node access includes remote memory, remote cache, remote mmio. 957 * - prefetches are not included in the counts because they are not 958 * reliably counted. 959 */ 960 961 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 962 #define HSW_DEMAND_RFO BIT_ULL(1) 963 #define HSW_ANY_RESPONSE BIT_ULL(16) 964 #define HSW_SUPPLIER_NONE BIT_ULL(17) 965 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 966 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 967 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 968 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 969 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 970 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 971 HSW_L3_MISS_REMOTE_HOP2P) 972 #define HSW_SNOOP_NONE BIT_ULL(31) 973 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 974 #define HSW_SNOOP_MISS BIT_ULL(33) 975 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 976 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 977 #define HSW_SNOOP_HITM BIT_ULL(36) 978 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 979 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 980 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 981 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 982 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 983 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 984 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 985 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 986 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 987 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 988 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 989 990 #define BDW_L3_MISS_LOCAL BIT(26) 991 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 992 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 993 HSW_L3_MISS_REMOTE_HOP2P) 994 995 996 static __initconst const u64 hsw_hw_cache_event_ids 997 [PERF_COUNT_HW_CACHE_MAX] 998 [PERF_COUNT_HW_CACHE_OP_MAX] 999 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1000 { 1001 [ C(L1D ) ] = { 1002 [ C(OP_READ) ] = { 1003 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1004 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1005 }, 1006 [ C(OP_WRITE) ] = { 1007 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1008 [ C(RESULT_MISS) ] = 0x0, 1009 }, 1010 [ C(OP_PREFETCH) ] = { 1011 [ C(RESULT_ACCESS) ] = 0x0, 1012 [ C(RESULT_MISS) ] = 0x0, 1013 }, 1014 }, 1015 [ C(L1I ) ] = { 1016 [ C(OP_READ) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x0, 1018 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1019 }, 1020 [ C(OP_WRITE) ] = { 1021 [ C(RESULT_ACCESS) ] = -1, 1022 [ C(RESULT_MISS) ] = -1, 1023 }, 1024 [ C(OP_PREFETCH) ] = { 1025 [ C(RESULT_ACCESS) ] = 0x0, 1026 [ C(RESULT_MISS) ] = 0x0, 1027 }, 1028 }, 1029 [ C(LL ) ] = { 1030 [ C(OP_READ) ] = { 1031 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1032 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1033 }, 1034 [ C(OP_WRITE) ] = { 1035 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1036 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1037 }, 1038 [ C(OP_PREFETCH) ] = { 1039 [ C(RESULT_ACCESS) ] = 0x0, 1040 [ C(RESULT_MISS) ] = 0x0, 1041 }, 1042 }, 1043 [ C(DTLB) ] = { 1044 [ C(OP_READ) ] = { 1045 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1046 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1047 }, 1048 [ C(OP_WRITE) ] = { 1049 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1050 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1051 }, 1052 [ C(OP_PREFETCH) ] = { 1053 [ C(RESULT_ACCESS) ] = 0x0, 1054 [ C(RESULT_MISS) ] = 0x0, 1055 }, 1056 }, 1057 [ C(ITLB) ] = { 1058 [ C(OP_READ) ] = { 1059 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1060 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1061 }, 1062 [ C(OP_WRITE) ] = { 1063 [ C(RESULT_ACCESS) ] = -1, 1064 [ C(RESULT_MISS) ] = -1, 1065 }, 1066 [ C(OP_PREFETCH) ] = { 1067 [ C(RESULT_ACCESS) ] = -1, 1068 [ C(RESULT_MISS) ] = -1, 1069 }, 1070 }, 1071 [ C(BPU ) ] = { 1072 [ C(OP_READ) ] = { 1073 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1074 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1075 }, 1076 [ C(OP_WRITE) ] = { 1077 [ C(RESULT_ACCESS) ] = -1, 1078 [ C(RESULT_MISS) ] = -1, 1079 }, 1080 [ C(OP_PREFETCH) ] = { 1081 [ C(RESULT_ACCESS) ] = -1, 1082 [ C(RESULT_MISS) ] = -1, 1083 }, 1084 }, 1085 [ C(NODE) ] = { 1086 [ C(OP_READ) ] = { 1087 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1088 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1089 }, 1090 [ C(OP_WRITE) ] = { 1091 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1092 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1093 }, 1094 [ C(OP_PREFETCH) ] = { 1095 [ C(RESULT_ACCESS) ] = 0x0, 1096 [ C(RESULT_MISS) ] = 0x0, 1097 }, 1098 }, 1099 }; 1100 1101 static __initconst const u64 hsw_hw_cache_extra_regs 1102 [PERF_COUNT_HW_CACHE_MAX] 1103 [PERF_COUNT_HW_CACHE_OP_MAX] 1104 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1105 { 1106 [ C(LL ) ] = { 1107 [ C(OP_READ) ] = { 1108 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1109 HSW_LLC_ACCESS, 1110 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1111 HSW_L3_MISS|HSW_ANY_SNOOP, 1112 }, 1113 [ C(OP_WRITE) ] = { 1114 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1115 HSW_LLC_ACCESS, 1116 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1117 HSW_L3_MISS|HSW_ANY_SNOOP, 1118 }, 1119 [ C(OP_PREFETCH) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x0, 1121 [ C(RESULT_MISS) ] = 0x0, 1122 }, 1123 }, 1124 [ C(NODE) ] = { 1125 [ C(OP_READ) ] = { 1126 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1127 HSW_L3_MISS_LOCAL_DRAM| 1128 HSW_SNOOP_DRAM, 1129 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1130 HSW_L3_MISS_REMOTE| 1131 HSW_SNOOP_DRAM, 1132 }, 1133 [ C(OP_WRITE) ] = { 1134 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1135 HSW_L3_MISS_LOCAL_DRAM| 1136 HSW_SNOOP_DRAM, 1137 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1138 HSW_L3_MISS_REMOTE| 1139 HSW_SNOOP_DRAM, 1140 }, 1141 [ C(OP_PREFETCH) ] = { 1142 [ C(RESULT_ACCESS) ] = 0x0, 1143 [ C(RESULT_MISS) ] = 0x0, 1144 }, 1145 }, 1146 }; 1147 1148 static __initconst const u64 westmere_hw_cache_event_ids 1149 [PERF_COUNT_HW_CACHE_MAX] 1150 [PERF_COUNT_HW_CACHE_OP_MAX] 1151 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1152 { 1153 [ C(L1D) ] = { 1154 [ C(OP_READ) ] = { 1155 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1156 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1157 }, 1158 [ C(OP_WRITE) ] = { 1159 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1160 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1161 }, 1162 [ C(OP_PREFETCH) ] = { 1163 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1164 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1165 }, 1166 }, 1167 [ C(L1I ) ] = { 1168 [ C(OP_READ) ] = { 1169 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1170 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1171 }, 1172 [ C(OP_WRITE) ] = { 1173 [ C(RESULT_ACCESS) ] = -1, 1174 [ C(RESULT_MISS) ] = -1, 1175 }, 1176 [ C(OP_PREFETCH) ] = { 1177 [ C(RESULT_ACCESS) ] = 0x0, 1178 [ C(RESULT_MISS) ] = 0x0, 1179 }, 1180 }, 1181 [ C(LL ) ] = { 1182 [ C(OP_READ) ] = { 1183 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1184 [ C(RESULT_ACCESS) ] = 0x01b7, 1185 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1186 [ C(RESULT_MISS) ] = 0x01b7, 1187 }, 1188 /* 1189 * Use RFO, not WRITEBACK, because a write miss would typically occur 1190 * on RFO. 1191 */ 1192 [ C(OP_WRITE) ] = { 1193 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1194 [ C(RESULT_ACCESS) ] = 0x01b7, 1195 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1196 [ C(RESULT_MISS) ] = 0x01b7, 1197 }, 1198 [ C(OP_PREFETCH) ] = { 1199 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1200 [ C(RESULT_ACCESS) ] = 0x01b7, 1201 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1202 [ C(RESULT_MISS) ] = 0x01b7, 1203 }, 1204 }, 1205 [ C(DTLB) ] = { 1206 [ C(OP_READ) ] = { 1207 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1208 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1209 }, 1210 [ C(OP_WRITE) ] = { 1211 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1212 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1213 }, 1214 [ C(OP_PREFETCH) ] = { 1215 [ C(RESULT_ACCESS) ] = 0x0, 1216 [ C(RESULT_MISS) ] = 0x0, 1217 }, 1218 }, 1219 [ C(ITLB) ] = { 1220 [ C(OP_READ) ] = { 1221 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1222 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1223 }, 1224 [ C(OP_WRITE) ] = { 1225 [ C(RESULT_ACCESS) ] = -1, 1226 [ C(RESULT_MISS) ] = -1, 1227 }, 1228 [ C(OP_PREFETCH) ] = { 1229 [ C(RESULT_ACCESS) ] = -1, 1230 [ C(RESULT_MISS) ] = -1, 1231 }, 1232 }, 1233 [ C(BPU ) ] = { 1234 [ C(OP_READ) ] = { 1235 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1236 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1237 }, 1238 [ C(OP_WRITE) ] = { 1239 [ C(RESULT_ACCESS) ] = -1, 1240 [ C(RESULT_MISS) ] = -1, 1241 }, 1242 [ C(OP_PREFETCH) ] = { 1243 [ C(RESULT_ACCESS) ] = -1, 1244 [ C(RESULT_MISS) ] = -1, 1245 }, 1246 }, 1247 [ C(NODE) ] = { 1248 [ C(OP_READ) ] = { 1249 [ C(RESULT_ACCESS) ] = 0x01b7, 1250 [ C(RESULT_MISS) ] = 0x01b7, 1251 }, 1252 [ C(OP_WRITE) ] = { 1253 [ C(RESULT_ACCESS) ] = 0x01b7, 1254 [ C(RESULT_MISS) ] = 0x01b7, 1255 }, 1256 [ C(OP_PREFETCH) ] = { 1257 [ C(RESULT_ACCESS) ] = 0x01b7, 1258 [ C(RESULT_MISS) ] = 0x01b7, 1259 }, 1260 }, 1261 }; 1262 1263 /* 1264 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1265 * See IA32 SDM Vol 3B 30.6.1.3 1266 */ 1267 1268 #define NHM_DMND_DATA_RD (1 << 0) 1269 #define NHM_DMND_RFO (1 << 1) 1270 #define NHM_DMND_IFETCH (1 << 2) 1271 #define NHM_DMND_WB (1 << 3) 1272 #define NHM_PF_DATA_RD (1 << 4) 1273 #define NHM_PF_DATA_RFO (1 << 5) 1274 #define NHM_PF_IFETCH (1 << 6) 1275 #define NHM_OFFCORE_OTHER (1 << 7) 1276 #define NHM_UNCORE_HIT (1 << 8) 1277 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1278 #define NHM_OTHER_CORE_HITM (1 << 10) 1279 /* reserved */ 1280 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1281 #define NHM_REMOTE_DRAM (1 << 13) 1282 #define NHM_LOCAL_DRAM (1 << 14) 1283 #define NHM_NON_DRAM (1 << 15) 1284 1285 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1286 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1287 1288 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1289 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1290 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1291 1292 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1293 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1294 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1295 1296 static __initconst const u64 nehalem_hw_cache_extra_regs 1297 [PERF_COUNT_HW_CACHE_MAX] 1298 [PERF_COUNT_HW_CACHE_OP_MAX] 1299 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1300 { 1301 [ C(LL ) ] = { 1302 [ C(OP_READ) ] = { 1303 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1304 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1305 }, 1306 [ C(OP_WRITE) ] = { 1307 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1308 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1309 }, 1310 [ C(OP_PREFETCH) ] = { 1311 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1312 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1313 }, 1314 }, 1315 [ C(NODE) ] = { 1316 [ C(OP_READ) ] = { 1317 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1318 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1319 }, 1320 [ C(OP_WRITE) ] = { 1321 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1322 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1323 }, 1324 [ C(OP_PREFETCH) ] = { 1325 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1326 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1327 }, 1328 }, 1329 }; 1330 1331 static __initconst const u64 nehalem_hw_cache_event_ids 1332 [PERF_COUNT_HW_CACHE_MAX] 1333 [PERF_COUNT_HW_CACHE_OP_MAX] 1334 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1335 { 1336 [ C(L1D) ] = { 1337 [ C(OP_READ) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1339 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1340 }, 1341 [ C(OP_WRITE) ] = { 1342 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1343 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1344 }, 1345 [ C(OP_PREFETCH) ] = { 1346 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1347 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1348 }, 1349 }, 1350 [ C(L1I ) ] = { 1351 [ C(OP_READ) ] = { 1352 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1353 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1354 }, 1355 [ C(OP_WRITE) ] = { 1356 [ C(RESULT_ACCESS) ] = -1, 1357 [ C(RESULT_MISS) ] = -1, 1358 }, 1359 [ C(OP_PREFETCH) ] = { 1360 [ C(RESULT_ACCESS) ] = 0x0, 1361 [ C(RESULT_MISS) ] = 0x0, 1362 }, 1363 }, 1364 [ C(LL ) ] = { 1365 [ C(OP_READ) ] = { 1366 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1367 [ C(RESULT_ACCESS) ] = 0x01b7, 1368 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1369 [ C(RESULT_MISS) ] = 0x01b7, 1370 }, 1371 /* 1372 * Use RFO, not WRITEBACK, because a write miss would typically occur 1373 * on RFO. 1374 */ 1375 [ C(OP_WRITE) ] = { 1376 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1377 [ C(RESULT_ACCESS) ] = 0x01b7, 1378 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1379 [ C(RESULT_MISS) ] = 0x01b7, 1380 }, 1381 [ C(OP_PREFETCH) ] = { 1382 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1383 [ C(RESULT_ACCESS) ] = 0x01b7, 1384 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1385 [ C(RESULT_MISS) ] = 0x01b7, 1386 }, 1387 }, 1388 [ C(DTLB) ] = { 1389 [ C(OP_READ) ] = { 1390 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1391 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1392 }, 1393 [ C(OP_WRITE) ] = { 1394 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1395 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1396 }, 1397 [ C(OP_PREFETCH) ] = { 1398 [ C(RESULT_ACCESS) ] = 0x0, 1399 [ C(RESULT_MISS) ] = 0x0, 1400 }, 1401 }, 1402 [ C(ITLB) ] = { 1403 [ C(OP_READ) ] = { 1404 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1405 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1406 }, 1407 [ C(OP_WRITE) ] = { 1408 [ C(RESULT_ACCESS) ] = -1, 1409 [ C(RESULT_MISS) ] = -1, 1410 }, 1411 [ C(OP_PREFETCH) ] = { 1412 [ C(RESULT_ACCESS) ] = -1, 1413 [ C(RESULT_MISS) ] = -1, 1414 }, 1415 }, 1416 [ C(BPU ) ] = { 1417 [ C(OP_READ) ] = { 1418 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1419 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1420 }, 1421 [ C(OP_WRITE) ] = { 1422 [ C(RESULT_ACCESS) ] = -1, 1423 [ C(RESULT_MISS) ] = -1, 1424 }, 1425 [ C(OP_PREFETCH) ] = { 1426 [ C(RESULT_ACCESS) ] = -1, 1427 [ C(RESULT_MISS) ] = -1, 1428 }, 1429 }, 1430 [ C(NODE) ] = { 1431 [ C(OP_READ) ] = { 1432 [ C(RESULT_ACCESS) ] = 0x01b7, 1433 [ C(RESULT_MISS) ] = 0x01b7, 1434 }, 1435 [ C(OP_WRITE) ] = { 1436 [ C(RESULT_ACCESS) ] = 0x01b7, 1437 [ C(RESULT_MISS) ] = 0x01b7, 1438 }, 1439 [ C(OP_PREFETCH) ] = { 1440 [ C(RESULT_ACCESS) ] = 0x01b7, 1441 [ C(RESULT_MISS) ] = 0x01b7, 1442 }, 1443 }, 1444 }; 1445 1446 static __initconst const u64 core2_hw_cache_event_ids 1447 [PERF_COUNT_HW_CACHE_MAX] 1448 [PERF_COUNT_HW_CACHE_OP_MAX] 1449 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1450 { 1451 [ C(L1D) ] = { 1452 [ C(OP_READ) ] = { 1453 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1454 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1455 }, 1456 [ C(OP_WRITE) ] = { 1457 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1458 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1459 }, 1460 [ C(OP_PREFETCH) ] = { 1461 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1462 [ C(RESULT_MISS) ] = 0, 1463 }, 1464 }, 1465 [ C(L1I ) ] = { 1466 [ C(OP_READ) ] = { 1467 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1468 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1469 }, 1470 [ C(OP_WRITE) ] = { 1471 [ C(RESULT_ACCESS) ] = -1, 1472 [ C(RESULT_MISS) ] = -1, 1473 }, 1474 [ C(OP_PREFETCH) ] = { 1475 [ C(RESULT_ACCESS) ] = 0, 1476 [ C(RESULT_MISS) ] = 0, 1477 }, 1478 }, 1479 [ C(LL ) ] = { 1480 [ C(OP_READ) ] = { 1481 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1482 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1483 }, 1484 [ C(OP_WRITE) ] = { 1485 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1486 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1487 }, 1488 [ C(OP_PREFETCH) ] = { 1489 [ C(RESULT_ACCESS) ] = 0, 1490 [ C(RESULT_MISS) ] = 0, 1491 }, 1492 }, 1493 [ C(DTLB) ] = { 1494 [ C(OP_READ) ] = { 1495 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1496 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1497 }, 1498 [ C(OP_WRITE) ] = { 1499 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1500 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1501 }, 1502 [ C(OP_PREFETCH) ] = { 1503 [ C(RESULT_ACCESS) ] = 0, 1504 [ C(RESULT_MISS) ] = 0, 1505 }, 1506 }, 1507 [ C(ITLB) ] = { 1508 [ C(OP_READ) ] = { 1509 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1510 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1511 }, 1512 [ C(OP_WRITE) ] = { 1513 [ C(RESULT_ACCESS) ] = -1, 1514 [ C(RESULT_MISS) ] = -1, 1515 }, 1516 [ C(OP_PREFETCH) ] = { 1517 [ C(RESULT_ACCESS) ] = -1, 1518 [ C(RESULT_MISS) ] = -1, 1519 }, 1520 }, 1521 [ C(BPU ) ] = { 1522 [ C(OP_READ) ] = { 1523 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1524 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1525 }, 1526 [ C(OP_WRITE) ] = { 1527 [ C(RESULT_ACCESS) ] = -1, 1528 [ C(RESULT_MISS) ] = -1, 1529 }, 1530 [ C(OP_PREFETCH) ] = { 1531 [ C(RESULT_ACCESS) ] = -1, 1532 [ C(RESULT_MISS) ] = -1, 1533 }, 1534 }, 1535 }; 1536 1537 static __initconst const u64 atom_hw_cache_event_ids 1538 [PERF_COUNT_HW_CACHE_MAX] 1539 [PERF_COUNT_HW_CACHE_OP_MAX] 1540 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1541 { 1542 [ C(L1D) ] = { 1543 [ C(OP_READ) ] = { 1544 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1545 [ C(RESULT_MISS) ] = 0, 1546 }, 1547 [ C(OP_WRITE) ] = { 1548 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1549 [ C(RESULT_MISS) ] = 0, 1550 }, 1551 [ C(OP_PREFETCH) ] = { 1552 [ C(RESULT_ACCESS) ] = 0x0, 1553 [ C(RESULT_MISS) ] = 0, 1554 }, 1555 }, 1556 [ C(L1I ) ] = { 1557 [ C(OP_READ) ] = { 1558 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1559 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1560 }, 1561 [ C(OP_WRITE) ] = { 1562 [ C(RESULT_ACCESS) ] = -1, 1563 [ C(RESULT_MISS) ] = -1, 1564 }, 1565 [ C(OP_PREFETCH) ] = { 1566 [ C(RESULT_ACCESS) ] = 0, 1567 [ C(RESULT_MISS) ] = 0, 1568 }, 1569 }, 1570 [ C(LL ) ] = { 1571 [ C(OP_READ) ] = { 1572 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1573 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1574 }, 1575 [ C(OP_WRITE) ] = { 1576 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1577 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1578 }, 1579 [ C(OP_PREFETCH) ] = { 1580 [ C(RESULT_ACCESS) ] = 0, 1581 [ C(RESULT_MISS) ] = 0, 1582 }, 1583 }, 1584 [ C(DTLB) ] = { 1585 [ C(OP_READ) ] = { 1586 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1587 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1588 }, 1589 [ C(OP_WRITE) ] = { 1590 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1591 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1592 }, 1593 [ C(OP_PREFETCH) ] = { 1594 [ C(RESULT_ACCESS) ] = 0, 1595 [ C(RESULT_MISS) ] = 0, 1596 }, 1597 }, 1598 [ C(ITLB) ] = { 1599 [ C(OP_READ) ] = { 1600 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1601 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1602 }, 1603 [ C(OP_WRITE) ] = { 1604 [ C(RESULT_ACCESS) ] = -1, 1605 [ C(RESULT_MISS) ] = -1, 1606 }, 1607 [ C(OP_PREFETCH) ] = { 1608 [ C(RESULT_ACCESS) ] = -1, 1609 [ C(RESULT_MISS) ] = -1, 1610 }, 1611 }, 1612 [ C(BPU ) ] = { 1613 [ C(OP_READ) ] = { 1614 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1615 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1616 }, 1617 [ C(OP_WRITE) ] = { 1618 [ C(RESULT_ACCESS) ] = -1, 1619 [ C(RESULT_MISS) ] = -1, 1620 }, 1621 [ C(OP_PREFETCH) ] = { 1622 [ C(RESULT_ACCESS) ] = -1, 1623 [ C(RESULT_MISS) ] = -1, 1624 }, 1625 }, 1626 }; 1627 1628 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1629 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1630 /* no_alloc_cycles.not_delivered */ 1631 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1632 "event=0xca,umask=0x50"); 1633 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1634 /* uops_retired.all */ 1635 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1636 "event=0xc2,umask=0x10"); 1637 /* uops_retired.all */ 1638 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1639 "event=0xc2,umask=0x10"); 1640 1641 static struct attribute *slm_events_attrs[] = { 1642 EVENT_PTR(td_total_slots_slm), 1643 EVENT_PTR(td_total_slots_scale_slm), 1644 EVENT_PTR(td_fetch_bubbles_slm), 1645 EVENT_PTR(td_fetch_bubbles_scale_slm), 1646 EVENT_PTR(td_slots_issued_slm), 1647 EVENT_PTR(td_slots_retired_slm), 1648 NULL 1649 }; 1650 1651 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1652 { 1653 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1654 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1655 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1656 EVENT_EXTRA_END 1657 }; 1658 1659 #define SLM_DMND_READ SNB_DMND_DATA_RD 1660 #define SLM_DMND_WRITE SNB_DMND_RFO 1661 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1662 1663 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1664 #define SLM_LLC_ACCESS SNB_RESP_ANY 1665 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1666 1667 static __initconst const u64 slm_hw_cache_extra_regs 1668 [PERF_COUNT_HW_CACHE_MAX] 1669 [PERF_COUNT_HW_CACHE_OP_MAX] 1670 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1671 { 1672 [ C(LL ) ] = { 1673 [ C(OP_READ) ] = { 1674 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1675 [ C(RESULT_MISS) ] = 0, 1676 }, 1677 [ C(OP_WRITE) ] = { 1678 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1679 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1680 }, 1681 [ C(OP_PREFETCH) ] = { 1682 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1683 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1684 }, 1685 }, 1686 }; 1687 1688 static __initconst const u64 slm_hw_cache_event_ids 1689 [PERF_COUNT_HW_CACHE_MAX] 1690 [PERF_COUNT_HW_CACHE_OP_MAX] 1691 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1692 { 1693 [ C(L1D) ] = { 1694 [ C(OP_READ) ] = { 1695 [ C(RESULT_ACCESS) ] = 0, 1696 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1697 }, 1698 [ C(OP_WRITE) ] = { 1699 [ C(RESULT_ACCESS) ] = 0, 1700 [ C(RESULT_MISS) ] = 0, 1701 }, 1702 [ C(OP_PREFETCH) ] = { 1703 [ C(RESULT_ACCESS) ] = 0, 1704 [ C(RESULT_MISS) ] = 0, 1705 }, 1706 }, 1707 [ C(L1I ) ] = { 1708 [ C(OP_READ) ] = { 1709 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1710 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1711 }, 1712 [ C(OP_WRITE) ] = { 1713 [ C(RESULT_ACCESS) ] = -1, 1714 [ C(RESULT_MISS) ] = -1, 1715 }, 1716 [ C(OP_PREFETCH) ] = { 1717 [ C(RESULT_ACCESS) ] = 0, 1718 [ C(RESULT_MISS) ] = 0, 1719 }, 1720 }, 1721 [ C(LL ) ] = { 1722 [ C(OP_READ) ] = { 1723 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1724 [ C(RESULT_ACCESS) ] = 0x01b7, 1725 [ C(RESULT_MISS) ] = 0, 1726 }, 1727 [ C(OP_WRITE) ] = { 1728 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1729 [ C(RESULT_ACCESS) ] = 0x01b7, 1730 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1731 [ C(RESULT_MISS) ] = 0x01b7, 1732 }, 1733 [ C(OP_PREFETCH) ] = { 1734 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1735 [ C(RESULT_ACCESS) ] = 0x01b7, 1736 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1737 [ C(RESULT_MISS) ] = 0x01b7, 1738 }, 1739 }, 1740 [ C(DTLB) ] = { 1741 [ C(OP_READ) ] = { 1742 [ C(RESULT_ACCESS) ] = 0, 1743 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1744 }, 1745 [ C(OP_WRITE) ] = { 1746 [ C(RESULT_ACCESS) ] = 0, 1747 [ C(RESULT_MISS) ] = 0, 1748 }, 1749 [ C(OP_PREFETCH) ] = { 1750 [ C(RESULT_ACCESS) ] = 0, 1751 [ C(RESULT_MISS) ] = 0, 1752 }, 1753 }, 1754 [ C(ITLB) ] = { 1755 [ C(OP_READ) ] = { 1756 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1757 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1758 }, 1759 [ C(OP_WRITE) ] = { 1760 [ C(RESULT_ACCESS) ] = -1, 1761 [ C(RESULT_MISS) ] = -1, 1762 }, 1763 [ C(OP_PREFETCH) ] = { 1764 [ C(RESULT_ACCESS) ] = -1, 1765 [ C(RESULT_MISS) ] = -1, 1766 }, 1767 }, 1768 [ C(BPU ) ] = { 1769 [ C(OP_READ) ] = { 1770 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1771 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1772 }, 1773 [ C(OP_WRITE) ] = { 1774 [ C(RESULT_ACCESS) ] = -1, 1775 [ C(RESULT_MISS) ] = -1, 1776 }, 1777 [ C(OP_PREFETCH) ] = { 1778 [ C(RESULT_ACCESS) ] = -1, 1779 [ C(RESULT_MISS) ] = -1, 1780 }, 1781 }, 1782 }; 1783 1784 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1785 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1786 /* UOPS_NOT_DELIVERED.ANY */ 1787 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1788 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1789 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1790 /* UOPS_RETIRED.ANY */ 1791 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1792 /* UOPS_ISSUED.ANY */ 1793 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1794 1795 static struct attribute *glm_events_attrs[] = { 1796 EVENT_PTR(td_total_slots_glm), 1797 EVENT_PTR(td_total_slots_scale_glm), 1798 EVENT_PTR(td_fetch_bubbles_glm), 1799 EVENT_PTR(td_recovery_bubbles_glm), 1800 EVENT_PTR(td_slots_issued_glm), 1801 EVENT_PTR(td_slots_retired_glm), 1802 NULL 1803 }; 1804 1805 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1806 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1807 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1808 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1809 EVENT_EXTRA_END 1810 }; 1811 1812 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1813 #define GLM_DEMAND_RFO BIT_ULL(1) 1814 #define GLM_ANY_RESPONSE BIT_ULL(16) 1815 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1816 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1817 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1818 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1819 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1820 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1821 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1822 1823 static __initconst const u64 glm_hw_cache_event_ids 1824 [PERF_COUNT_HW_CACHE_MAX] 1825 [PERF_COUNT_HW_CACHE_OP_MAX] 1826 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1827 [C(L1D)] = { 1828 [C(OP_READ)] = { 1829 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1830 [C(RESULT_MISS)] = 0x0, 1831 }, 1832 [C(OP_WRITE)] = { 1833 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1834 [C(RESULT_MISS)] = 0x0, 1835 }, 1836 [C(OP_PREFETCH)] = { 1837 [C(RESULT_ACCESS)] = 0x0, 1838 [C(RESULT_MISS)] = 0x0, 1839 }, 1840 }, 1841 [C(L1I)] = { 1842 [C(OP_READ)] = { 1843 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1844 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1845 }, 1846 [C(OP_WRITE)] = { 1847 [C(RESULT_ACCESS)] = -1, 1848 [C(RESULT_MISS)] = -1, 1849 }, 1850 [C(OP_PREFETCH)] = { 1851 [C(RESULT_ACCESS)] = 0x0, 1852 [C(RESULT_MISS)] = 0x0, 1853 }, 1854 }, 1855 [C(LL)] = { 1856 [C(OP_READ)] = { 1857 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1858 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1859 }, 1860 [C(OP_WRITE)] = { 1861 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1862 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1863 }, 1864 [C(OP_PREFETCH)] = { 1865 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1866 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1867 }, 1868 }, 1869 [C(DTLB)] = { 1870 [C(OP_READ)] = { 1871 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1872 [C(RESULT_MISS)] = 0x0, 1873 }, 1874 [C(OP_WRITE)] = { 1875 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1876 [C(RESULT_MISS)] = 0x0, 1877 }, 1878 [C(OP_PREFETCH)] = { 1879 [C(RESULT_ACCESS)] = 0x0, 1880 [C(RESULT_MISS)] = 0x0, 1881 }, 1882 }, 1883 [C(ITLB)] = { 1884 [C(OP_READ)] = { 1885 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1886 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1887 }, 1888 [C(OP_WRITE)] = { 1889 [C(RESULT_ACCESS)] = -1, 1890 [C(RESULT_MISS)] = -1, 1891 }, 1892 [C(OP_PREFETCH)] = { 1893 [C(RESULT_ACCESS)] = -1, 1894 [C(RESULT_MISS)] = -1, 1895 }, 1896 }, 1897 [C(BPU)] = { 1898 [C(OP_READ)] = { 1899 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1900 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1901 }, 1902 [C(OP_WRITE)] = { 1903 [C(RESULT_ACCESS)] = -1, 1904 [C(RESULT_MISS)] = -1, 1905 }, 1906 [C(OP_PREFETCH)] = { 1907 [C(RESULT_ACCESS)] = -1, 1908 [C(RESULT_MISS)] = -1, 1909 }, 1910 }, 1911 }; 1912 1913 static __initconst const u64 glm_hw_cache_extra_regs 1914 [PERF_COUNT_HW_CACHE_MAX] 1915 [PERF_COUNT_HW_CACHE_OP_MAX] 1916 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1917 [C(LL)] = { 1918 [C(OP_READ)] = { 1919 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1920 GLM_LLC_ACCESS, 1921 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1922 GLM_LLC_MISS, 1923 }, 1924 [C(OP_WRITE)] = { 1925 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1926 GLM_LLC_ACCESS, 1927 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1928 GLM_LLC_MISS, 1929 }, 1930 [C(OP_PREFETCH)] = { 1931 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1932 GLM_LLC_ACCESS, 1933 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1934 GLM_LLC_MISS, 1935 }, 1936 }, 1937 }; 1938 1939 static __initconst const u64 glp_hw_cache_event_ids 1940 [PERF_COUNT_HW_CACHE_MAX] 1941 [PERF_COUNT_HW_CACHE_OP_MAX] 1942 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1943 [C(L1D)] = { 1944 [C(OP_READ)] = { 1945 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1946 [C(RESULT_MISS)] = 0x0, 1947 }, 1948 [C(OP_WRITE)] = { 1949 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1950 [C(RESULT_MISS)] = 0x0, 1951 }, 1952 [C(OP_PREFETCH)] = { 1953 [C(RESULT_ACCESS)] = 0x0, 1954 [C(RESULT_MISS)] = 0x0, 1955 }, 1956 }, 1957 [C(L1I)] = { 1958 [C(OP_READ)] = { 1959 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1960 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1961 }, 1962 [C(OP_WRITE)] = { 1963 [C(RESULT_ACCESS)] = -1, 1964 [C(RESULT_MISS)] = -1, 1965 }, 1966 [C(OP_PREFETCH)] = { 1967 [C(RESULT_ACCESS)] = 0x0, 1968 [C(RESULT_MISS)] = 0x0, 1969 }, 1970 }, 1971 [C(LL)] = { 1972 [C(OP_READ)] = { 1973 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1974 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1975 }, 1976 [C(OP_WRITE)] = { 1977 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1978 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1979 }, 1980 [C(OP_PREFETCH)] = { 1981 [C(RESULT_ACCESS)] = 0x0, 1982 [C(RESULT_MISS)] = 0x0, 1983 }, 1984 }, 1985 [C(DTLB)] = { 1986 [C(OP_READ)] = { 1987 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1988 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1989 }, 1990 [C(OP_WRITE)] = { 1991 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1992 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1993 }, 1994 [C(OP_PREFETCH)] = { 1995 [C(RESULT_ACCESS)] = 0x0, 1996 [C(RESULT_MISS)] = 0x0, 1997 }, 1998 }, 1999 [C(ITLB)] = { 2000 [C(OP_READ)] = { 2001 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2002 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2003 }, 2004 [C(OP_WRITE)] = { 2005 [C(RESULT_ACCESS)] = -1, 2006 [C(RESULT_MISS)] = -1, 2007 }, 2008 [C(OP_PREFETCH)] = { 2009 [C(RESULT_ACCESS)] = -1, 2010 [C(RESULT_MISS)] = -1, 2011 }, 2012 }, 2013 [C(BPU)] = { 2014 [C(OP_READ)] = { 2015 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2016 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2017 }, 2018 [C(OP_WRITE)] = { 2019 [C(RESULT_ACCESS)] = -1, 2020 [C(RESULT_MISS)] = -1, 2021 }, 2022 [C(OP_PREFETCH)] = { 2023 [C(RESULT_ACCESS)] = -1, 2024 [C(RESULT_MISS)] = -1, 2025 }, 2026 }, 2027 }; 2028 2029 static __initconst const u64 glp_hw_cache_extra_regs 2030 [PERF_COUNT_HW_CACHE_MAX] 2031 [PERF_COUNT_HW_CACHE_OP_MAX] 2032 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2033 [C(LL)] = { 2034 [C(OP_READ)] = { 2035 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2036 GLM_LLC_ACCESS, 2037 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2038 GLM_LLC_MISS, 2039 }, 2040 [C(OP_WRITE)] = { 2041 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2042 GLM_LLC_ACCESS, 2043 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2044 GLM_LLC_MISS, 2045 }, 2046 [C(OP_PREFETCH)] = { 2047 [C(RESULT_ACCESS)] = 0x0, 2048 [C(RESULT_MISS)] = 0x0, 2049 }, 2050 }, 2051 }; 2052 2053 #define TNT_LOCAL_DRAM BIT_ULL(26) 2054 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2055 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2056 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2057 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2058 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2059 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2060 2061 static __initconst const u64 tnt_hw_cache_extra_regs 2062 [PERF_COUNT_HW_CACHE_MAX] 2063 [PERF_COUNT_HW_CACHE_OP_MAX] 2064 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2065 [C(LL)] = { 2066 [C(OP_READ)] = { 2067 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2068 TNT_LLC_ACCESS, 2069 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2070 TNT_LLC_MISS, 2071 }, 2072 [C(OP_WRITE)] = { 2073 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2074 TNT_LLC_ACCESS, 2075 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2076 TNT_LLC_MISS, 2077 }, 2078 [C(OP_PREFETCH)] = { 2079 [C(RESULT_ACCESS)] = 0x0, 2080 [C(RESULT_MISS)] = 0x0, 2081 }, 2082 }, 2083 }; 2084 2085 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2086 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2087 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2088 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2089 2090 static struct attribute *tnt_events_attrs[] = { 2091 EVENT_PTR(td_fe_bound_tnt), 2092 EVENT_PTR(td_retiring_tnt), 2093 EVENT_PTR(td_bad_spec_tnt), 2094 EVENT_PTR(td_be_bound_tnt), 2095 NULL, 2096 }; 2097 2098 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2099 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2100 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2101 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2102 EVENT_EXTRA_END 2103 }; 2104 2105 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2106 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2107 2108 static struct attribute *grt_mem_attrs[] = { 2109 EVENT_PTR(mem_ld_grt), 2110 EVENT_PTR(mem_st_grt), 2111 NULL 2112 }; 2113 2114 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2115 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2116 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2117 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2118 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2119 EVENT_EXTRA_END 2120 }; 2121 2122 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2123 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2124 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2125 #define KNL_MCDRAM_FAR BIT_ULL(22) 2126 #define KNL_DDR_LOCAL BIT_ULL(23) 2127 #define KNL_DDR_FAR BIT_ULL(24) 2128 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2129 KNL_DDR_LOCAL | KNL_DDR_FAR) 2130 #define KNL_L2_READ SLM_DMND_READ 2131 #define KNL_L2_WRITE SLM_DMND_WRITE 2132 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2133 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2134 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2135 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2136 SNB_NON_DRAM) 2137 2138 static __initconst const u64 knl_hw_cache_extra_regs 2139 [PERF_COUNT_HW_CACHE_MAX] 2140 [PERF_COUNT_HW_CACHE_OP_MAX] 2141 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2142 [C(LL)] = { 2143 [C(OP_READ)] = { 2144 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2145 [C(RESULT_MISS)] = 0, 2146 }, 2147 [C(OP_WRITE)] = { 2148 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2149 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2150 }, 2151 [C(OP_PREFETCH)] = { 2152 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2153 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2154 }, 2155 }, 2156 }; 2157 2158 /* 2159 * Used from PMIs where the LBRs are already disabled. 2160 * 2161 * This function could be called consecutively. It is required to remain in 2162 * disabled state if called consecutively. 2163 * 2164 * During consecutive calls, the same disable value will be written to related 2165 * registers, so the PMU state remains unchanged. 2166 * 2167 * intel_bts events don't coexist with intel PMU's BTS events because of 2168 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2169 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2170 * 2171 * Avoid PEBS_ENABLE MSR access in PMIs. 2172 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2173 * It doesn't matter if the PEBS is enabled or not. 2174 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2175 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2176 * However, there are some cases which may change PEBS status, e.g. PMI 2177 * throttle. The PEBS_ENABLE should be updated where the status changes. 2178 */ 2179 static __always_inline void __intel_pmu_disable_all(bool bts) 2180 { 2181 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2182 2183 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2184 2185 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2186 intel_pmu_disable_bts(); 2187 } 2188 2189 static __always_inline void intel_pmu_disable_all(void) 2190 { 2191 __intel_pmu_disable_all(true); 2192 intel_pmu_pebs_disable_all(); 2193 intel_pmu_lbr_disable_all(); 2194 } 2195 2196 static void __intel_pmu_enable_all(int added, bool pmi) 2197 { 2198 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2199 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2200 2201 intel_pmu_lbr_enable_all(pmi); 2202 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2203 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2204 2205 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2206 struct perf_event *event = 2207 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2208 2209 if (WARN_ON_ONCE(!event)) 2210 return; 2211 2212 intel_pmu_enable_bts(event->hw.config); 2213 } 2214 } 2215 2216 static void intel_pmu_enable_all(int added) 2217 { 2218 intel_pmu_pebs_enable_all(); 2219 __intel_pmu_enable_all(added, false); 2220 } 2221 2222 static noinline int 2223 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2224 unsigned int cnt, unsigned long flags) 2225 { 2226 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2227 2228 intel_pmu_lbr_read(); 2229 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2230 2231 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2232 intel_pmu_enable_all(0); 2233 local_irq_restore(flags); 2234 return cnt; 2235 } 2236 2237 static int 2238 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2239 { 2240 unsigned long flags; 2241 2242 /* must not have branches... */ 2243 local_irq_save(flags); 2244 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2245 __intel_pmu_lbr_disable(); 2246 /* ... until here */ 2247 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2248 } 2249 2250 static int 2251 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2252 { 2253 unsigned long flags; 2254 2255 /* must not have branches... */ 2256 local_irq_save(flags); 2257 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2258 __intel_pmu_arch_lbr_disable(); 2259 /* ... until here */ 2260 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2261 } 2262 2263 /* 2264 * Workaround for: 2265 * Intel Errata AAK100 (model 26) 2266 * Intel Errata AAP53 (model 30) 2267 * Intel Errata BD53 (model 44) 2268 * 2269 * The official story: 2270 * These chips need to be 'reset' when adding counters by programming the 2271 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2272 * in sequence on the same PMC or on different PMCs. 2273 * 2274 * In practice it appears some of these events do in fact count, and 2275 * we need to program all 4 events. 2276 */ 2277 static void intel_pmu_nhm_workaround(void) 2278 { 2279 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2280 static const unsigned long nhm_magic[4] = { 2281 0x4300B5, 2282 0x4300D2, 2283 0x4300B1, 2284 0x4300B1 2285 }; 2286 struct perf_event *event; 2287 int i; 2288 2289 /* 2290 * The Errata requires below steps: 2291 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2292 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2293 * the corresponding PMCx; 2294 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2295 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2296 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2297 */ 2298 2299 /* 2300 * The real steps we choose are a little different from above. 2301 * A) To reduce MSR operations, we don't run step 1) as they 2302 * are already cleared before this function is called; 2303 * B) Call x86_perf_event_update to save PMCx before configuring 2304 * PERFEVTSELx with magic number; 2305 * C) With step 5), we do clear only when the PERFEVTSELx is 2306 * not used currently. 2307 * D) Call x86_perf_event_set_period to restore PMCx; 2308 */ 2309 2310 /* We always operate 4 pairs of PERF Counters */ 2311 for (i = 0; i < 4; i++) { 2312 event = cpuc->events[i]; 2313 if (event) 2314 x86_perf_event_update(event); 2315 } 2316 2317 for (i = 0; i < 4; i++) { 2318 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2319 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2320 } 2321 2322 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2323 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2324 2325 for (i = 0; i < 4; i++) { 2326 event = cpuc->events[i]; 2327 2328 if (event) { 2329 x86_perf_event_set_period(event); 2330 __x86_pmu_enable_event(&event->hw, 2331 ARCH_PERFMON_EVENTSEL_ENABLE); 2332 } else 2333 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2334 } 2335 } 2336 2337 static void intel_pmu_nhm_enable_all(int added) 2338 { 2339 if (added) 2340 intel_pmu_nhm_workaround(); 2341 intel_pmu_enable_all(added); 2342 } 2343 2344 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2345 { 2346 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2347 2348 if (cpuc->tfa_shadow != val) { 2349 cpuc->tfa_shadow = val; 2350 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2351 } 2352 } 2353 2354 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2355 { 2356 /* 2357 * We're going to use PMC3, make sure TFA is set before we touch it. 2358 */ 2359 if (cntr == 3) 2360 intel_set_tfa(cpuc, true); 2361 } 2362 2363 static void intel_tfa_pmu_enable_all(int added) 2364 { 2365 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2366 2367 /* 2368 * If we find PMC3 is no longer used when we enable the PMU, we can 2369 * clear TFA. 2370 */ 2371 if (!test_bit(3, cpuc->active_mask)) 2372 intel_set_tfa(cpuc, false); 2373 2374 intel_pmu_enable_all(added); 2375 } 2376 2377 static inline u64 intel_pmu_get_status(void) 2378 { 2379 u64 status; 2380 2381 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2382 2383 return status; 2384 } 2385 2386 static inline void intel_pmu_ack_status(u64 ack) 2387 { 2388 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2389 } 2390 2391 static inline bool event_is_checkpointed(struct perf_event *event) 2392 { 2393 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2394 } 2395 2396 static inline void intel_set_masks(struct perf_event *event, int idx) 2397 { 2398 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2399 2400 if (event->attr.exclude_host) 2401 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2402 if (event->attr.exclude_guest) 2403 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2404 if (event_is_checkpointed(event)) 2405 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2406 } 2407 2408 static inline void intel_clear_masks(struct perf_event *event, int idx) 2409 { 2410 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2411 2412 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2413 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2414 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2415 } 2416 2417 static void intel_pmu_disable_fixed(struct perf_event *event) 2418 { 2419 struct hw_perf_event *hwc = &event->hw; 2420 u64 ctrl_val, mask; 2421 int idx = hwc->idx; 2422 2423 if (is_topdown_idx(idx)) { 2424 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2425 2426 /* 2427 * When there are other active TopDown events, 2428 * don't disable the fixed counter 3. 2429 */ 2430 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2431 return; 2432 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2433 } 2434 2435 intel_clear_masks(event, idx); 2436 2437 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2438 rdmsrl(hwc->config_base, ctrl_val); 2439 ctrl_val &= ~mask; 2440 wrmsrl(hwc->config_base, ctrl_val); 2441 } 2442 2443 static void intel_pmu_disable_event(struct perf_event *event) 2444 { 2445 struct hw_perf_event *hwc = &event->hw; 2446 int idx = hwc->idx; 2447 2448 switch (idx) { 2449 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2450 intel_clear_masks(event, idx); 2451 x86_pmu_disable_event(event); 2452 break; 2453 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2454 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2455 intel_pmu_disable_fixed(event); 2456 break; 2457 case INTEL_PMC_IDX_FIXED_BTS: 2458 intel_pmu_disable_bts(); 2459 intel_pmu_drain_bts_buffer(); 2460 return; 2461 case INTEL_PMC_IDX_FIXED_VLBR: 2462 intel_clear_masks(event, idx); 2463 break; 2464 default: 2465 intel_clear_masks(event, idx); 2466 pr_warn("Failed to disable the event with invalid index %d\n", 2467 idx); 2468 return; 2469 } 2470 2471 /* 2472 * Needs to be called after x86_pmu_disable_event, 2473 * so we don't trigger the event without PEBS bit set. 2474 */ 2475 if (unlikely(event->attr.precise_ip)) 2476 intel_pmu_pebs_disable(event); 2477 } 2478 2479 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2480 { 2481 if (is_pebs_pt(event)) 2482 perf_report_aux_output_id(event, idx); 2483 } 2484 2485 static void intel_pmu_del_event(struct perf_event *event) 2486 { 2487 if (needs_branch_stack(event)) 2488 intel_pmu_lbr_del(event); 2489 if (event->attr.precise_ip) 2490 intel_pmu_pebs_del(event); 2491 } 2492 2493 static int icl_set_topdown_event_period(struct perf_event *event) 2494 { 2495 struct hw_perf_event *hwc = &event->hw; 2496 s64 left = local64_read(&hwc->period_left); 2497 2498 /* 2499 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2500 * Software should start both registers, PERF_METRICS and fixed 2501 * counter 3, from zero. 2502 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2503 * After that, both MSRs will be cleared for each read. 2504 * Don't need to clear them again. 2505 */ 2506 if (left == x86_pmu.max_period) { 2507 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2508 wrmsrl(MSR_PERF_METRICS, 0); 2509 hwc->saved_slots = 0; 2510 hwc->saved_metric = 0; 2511 } 2512 2513 if ((hwc->saved_slots) && is_slots_event(event)) { 2514 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2515 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2516 } 2517 2518 perf_event_update_userpage(event); 2519 2520 return 0; 2521 } 2522 2523 static int adl_set_topdown_event_period(struct perf_event *event) 2524 { 2525 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2526 2527 if (pmu->cpu_type != hybrid_big) 2528 return 0; 2529 2530 return icl_set_topdown_event_period(event); 2531 } 2532 2533 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2534 { 2535 u32 val; 2536 2537 /* 2538 * The metric is reported as an 8bit integer fraction 2539 * summing up to 0xff. 2540 * slots-in-metric = (Metric / 0xff) * slots 2541 */ 2542 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2543 return mul_u64_u32_div(slots, val, 0xff); 2544 } 2545 2546 static u64 icl_get_topdown_value(struct perf_event *event, 2547 u64 slots, u64 metrics) 2548 { 2549 int idx = event->hw.idx; 2550 u64 delta; 2551 2552 if (is_metric_idx(idx)) 2553 delta = icl_get_metrics_event_value(metrics, slots, idx); 2554 else 2555 delta = slots; 2556 2557 return delta; 2558 } 2559 2560 static void __icl_update_topdown_event(struct perf_event *event, 2561 u64 slots, u64 metrics, 2562 u64 last_slots, u64 last_metrics) 2563 { 2564 u64 delta, last = 0; 2565 2566 delta = icl_get_topdown_value(event, slots, metrics); 2567 if (last_slots) 2568 last = icl_get_topdown_value(event, last_slots, last_metrics); 2569 2570 /* 2571 * The 8bit integer fraction of metric may be not accurate, 2572 * especially when the changes is very small. 2573 * For example, if only a few bad_spec happens, the fraction 2574 * may be reduced from 1 to 0. If so, the bad_spec event value 2575 * will be 0 which is definitely less than the last value. 2576 * Avoid update event->count for this case. 2577 */ 2578 if (delta > last) { 2579 delta -= last; 2580 local64_add(delta, &event->count); 2581 } 2582 } 2583 2584 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2585 u64 metrics, int metric_end) 2586 { 2587 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2588 struct perf_event *other; 2589 int idx; 2590 2591 event->hw.saved_slots = slots; 2592 event->hw.saved_metric = metrics; 2593 2594 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2595 if (!is_topdown_idx(idx)) 2596 continue; 2597 other = cpuc->events[idx]; 2598 other->hw.saved_slots = slots; 2599 other->hw.saved_metric = metrics; 2600 } 2601 } 2602 2603 /* 2604 * Update all active Topdown events. 2605 * 2606 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2607 * modify by a NMI. PMU has to be disabled before calling this function. 2608 */ 2609 2610 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2611 { 2612 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2613 struct perf_event *other; 2614 u64 slots, metrics; 2615 bool reset = true; 2616 int idx; 2617 2618 /* read Fixed counter 3 */ 2619 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2620 if (!slots) 2621 return 0; 2622 2623 /* read PERF_METRICS */ 2624 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2625 2626 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2627 if (!is_topdown_idx(idx)) 2628 continue; 2629 other = cpuc->events[idx]; 2630 __icl_update_topdown_event(other, slots, metrics, 2631 event ? event->hw.saved_slots : 0, 2632 event ? event->hw.saved_metric : 0); 2633 } 2634 2635 /* 2636 * Check and update this event, which may have been cleared 2637 * in active_mask e.g. x86_pmu_stop() 2638 */ 2639 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2640 __icl_update_topdown_event(event, slots, metrics, 2641 event->hw.saved_slots, 2642 event->hw.saved_metric); 2643 2644 /* 2645 * In x86_pmu_stop(), the event is cleared in active_mask first, 2646 * then drain the delta, which indicates context switch for 2647 * counting. 2648 * Save metric and slots for context switch. 2649 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2650 * Because the values will be restored in next schedule in. 2651 */ 2652 update_saved_topdown_regs(event, slots, metrics, metric_end); 2653 reset = false; 2654 } 2655 2656 if (reset) { 2657 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2658 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2659 wrmsrl(MSR_PERF_METRICS, 0); 2660 if (event) 2661 update_saved_topdown_regs(event, 0, 0, metric_end); 2662 } 2663 2664 return slots; 2665 } 2666 2667 static u64 icl_update_topdown_event(struct perf_event *event) 2668 { 2669 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2670 x86_pmu.num_topdown_events - 1); 2671 } 2672 2673 static u64 adl_update_topdown_event(struct perf_event *event) 2674 { 2675 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2676 2677 if (pmu->cpu_type != hybrid_big) 2678 return 0; 2679 2680 return icl_update_topdown_event(event); 2681 } 2682 2683 2684 static void intel_pmu_read_topdown_event(struct perf_event *event) 2685 { 2686 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2687 2688 /* Only need to call update_topdown_event() once for group read. */ 2689 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2690 !is_slots_event(event)) 2691 return; 2692 2693 perf_pmu_disable(event->pmu); 2694 x86_pmu.update_topdown_event(event); 2695 perf_pmu_enable(event->pmu); 2696 } 2697 2698 static void intel_pmu_read_event(struct perf_event *event) 2699 { 2700 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2701 intel_pmu_auto_reload_read(event); 2702 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 2703 intel_pmu_read_topdown_event(event); 2704 else 2705 x86_perf_event_update(event); 2706 } 2707 2708 static void intel_pmu_enable_fixed(struct perf_event *event) 2709 { 2710 struct hw_perf_event *hwc = &event->hw; 2711 u64 ctrl_val, mask, bits = 0; 2712 int idx = hwc->idx; 2713 2714 if (is_topdown_idx(idx)) { 2715 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2716 /* 2717 * When there are other active TopDown events, 2718 * don't enable the fixed counter 3 again. 2719 */ 2720 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2721 return; 2722 2723 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2724 } 2725 2726 intel_set_masks(event, idx); 2727 2728 /* 2729 * Enable IRQ generation (0x8), if not PEBS, 2730 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2731 * if requested: 2732 */ 2733 if (!event->attr.precise_ip) 2734 bits |= 0x8; 2735 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2736 bits |= 0x2; 2737 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2738 bits |= 0x1; 2739 2740 /* 2741 * ANY bit is supported in v3 and up 2742 */ 2743 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2744 bits |= 0x4; 2745 2746 idx -= INTEL_PMC_IDX_FIXED; 2747 bits <<= (idx * 4); 2748 mask = 0xfULL << (idx * 4); 2749 2750 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2751 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2752 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2753 } 2754 2755 rdmsrl(hwc->config_base, ctrl_val); 2756 ctrl_val &= ~mask; 2757 ctrl_val |= bits; 2758 wrmsrl(hwc->config_base, ctrl_val); 2759 } 2760 2761 static void intel_pmu_enable_event(struct perf_event *event) 2762 { 2763 struct hw_perf_event *hwc = &event->hw; 2764 int idx = hwc->idx; 2765 2766 if (unlikely(event->attr.precise_ip)) 2767 intel_pmu_pebs_enable(event); 2768 2769 switch (idx) { 2770 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2771 intel_set_masks(event, idx); 2772 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2773 break; 2774 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2775 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2776 intel_pmu_enable_fixed(event); 2777 break; 2778 case INTEL_PMC_IDX_FIXED_BTS: 2779 if (!__this_cpu_read(cpu_hw_events.enabled)) 2780 return; 2781 intel_pmu_enable_bts(hwc->config); 2782 break; 2783 case INTEL_PMC_IDX_FIXED_VLBR: 2784 intel_set_masks(event, idx); 2785 break; 2786 default: 2787 pr_warn("Failed to enable the event with invalid index %d\n", 2788 idx); 2789 } 2790 } 2791 2792 static void intel_pmu_add_event(struct perf_event *event) 2793 { 2794 if (event->attr.precise_ip) 2795 intel_pmu_pebs_add(event); 2796 if (needs_branch_stack(event)) 2797 intel_pmu_lbr_add(event); 2798 } 2799 2800 /* 2801 * Save and restart an expired event. Called by NMI contexts, 2802 * so it has to be careful about preempting normal event ops: 2803 */ 2804 int intel_pmu_save_and_restart(struct perf_event *event) 2805 { 2806 x86_perf_event_update(event); 2807 /* 2808 * For a checkpointed counter always reset back to 0. This 2809 * avoids a situation where the counter overflows, aborts the 2810 * transaction and is then set back to shortly before the 2811 * overflow, and overflows and aborts again. 2812 */ 2813 if (unlikely(event_is_checkpointed(event))) { 2814 /* No race with NMIs because the counter should not be armed */ 2815 wrmsrl(event->hw.event_base, 0); 2816 local64_set(&event->hw.prev_count, 0); 2817 } 2818 return x86_perf_event_set_period(event); 2819 } 2820 2821 static void intel_pmu_reset(void) 2822 { 2823 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2824 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2825 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2826 int num_counters = hybrid(cpuc->pmu, num_counters); 2827 unsigned long flags; 2828 int idx; 2829 2830 if (!num_counters) 2831 return; 2832 2833 local_irq_save(flags); 2834 2835 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2836 2837 for (idx = 0; idx < num_counters; idx++) { 2838 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2839 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2840 } 2841 for (idx = 0; idx < num_counters_fixed; idx++) { 2842 if (fixed_counter_disabled(idx, cpuc->pmu)) 2843 continue; 2844 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2845 } 2846 2847 if (ds) 2848 ds->bts_index = ds->bts_buffer_base; 2849 2850 /* Ack all overflows and disable fixed counters */ 2851 if (x86_pmu.version >= 2) { 2852 intel_pmu_ack_status(intel_pmu_get_status()); 2853 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2854 } 2855 2856 /* Reset LBRs and LBR freezing */ 2857 if (x86_pmu.lbr_nr) { 2858 update_debugctlmsr(get_debugctlmsr() & 2859 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2860 } 2861 2862 local_irq_restore(flags); 2863 } 2864 2865 /* 2866 * We may be running with guest PEBS events created by KVM, and the 2867 * PEBS records are logged into the guest's DS and invisible to host. 2868 * 2869 * In the case of guest PEBS overflow, we only trigger a fake event 2870 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 2871 * The guest will then vm-entry and check the guest DS area to read 2872 * the guest PEBS records. 2873 * 2874 * The contents and other behavior of the guest event do not matter. 2875 */ 2876 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 2877 struct perf_sample_data *data) 2878 { 2879 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2880 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 2881 struct perf_event *event = NULL; 2882 int bit; 2883 2884 if (!unlikely(perf_guest_state())) 2885 return; 2886 2887 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 2888 !guest_pebs_idxs) 2889 return; 2890 2891 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, 2892 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) { 2893 event = cpuc->events[bit]; 2894 if (!event->attr.precise_ip) 2895 continue; 2896 2897 perf_sample_data_init(data, 0, event->hw.last_period); 2898 if (perf_event_overflow(event, data, regs)) 2899 x86_pmu_stop(event, 0); 2900 2901 /* Inject one fake event is enough. */ 2902 break; 2903 } 2904 } 2905 2906 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2907 { 2908 struct perf_sample_data data; 2909 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2910 int bit; 2911 int handled = 0; 2912 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2913 2914 inc_irq_stat(apic_perf_irqs); 2915 2916 /* 2917 * Ignore a range of extra bits in status that do not indicate 2918 * overflow by themselves. 2919 */ 2920 status &= ~(GLOBAL_STATUS_COND_CHG | 2921 GLOBAL_STATUS_ASIF | 2922 GLOBAL_STATUS_LBRS_FROZEN); 2923 if (!status) 2924 return 0; 2925 /* 2926 * In case multiple PEBS events are sampled at the same time, 2927 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2928 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2929 * having their bits set in the status register. This is a sign 2930 * that there was at least one PEBS record pending at the time 2931 * of the PMU interrupt. PEBS counters must only be processed 2932 * via the drain_pebs() calls and not via the regular sample 2933 * processing loop coming after that the function, otherwise 2934 * phony regular samples may be generated in the sampling buffer 2935 * not marked with the EXACT tag. Another possibility is to have 2936 * one PEBS event and at least one non-PEBS event which overflows 2937 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2938 * not be set, yet the overflow status bit for the PEBS counter will 2939 * be on Skylake. 2940 * 2941 * To avoid this problem, we systematically ignore the PEBS-enabled 2942 * counters from the GLOBAL_STATUS mask and we always process PEBS 2943 * events via drain_pebs(). 2944 */ 2945 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 2946 2947 /* 2948 * PEBS overflow sets bit 62 in the global status register 2949 */ 2950 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2951 u64 pebs_enabled = cpuc->pebs_enabled; 2952 2953 handled++; 2954 x86_pmu_handle_guest_pebs(regs, &data); 2955 x86_pmu.drain_pebs(regs, &data); 2956 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2957 2958 /* 2959 * PMI throttle may be triggered, which stops the PEBS event. 2960 * Although cpuc->pebs_enabled is updated accordingly, the 2961 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2962 * cpuc->enabled has been forced to 0 in PMI. 2963 * Update the MSR if pebs_enabled is changed. 2964 */ 2965 if (pebs_enabled != cpuc->pebs_enabled) 2966 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2967 } 2968 2969 /* 2970 * Intel PT 2971 */ 2972 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2973 handled++; 2974 if (!perf_guest_handle_intel_pt_intr()) 2975 intel_pt_interrupt(); 2976 } 2977 2978 /* 2979 * Intel Perf metrics 2980 */ 2981 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 2982 handled++; 2983 if (x86_pmu.update_topdown_event) 2984 x86_pmu.update_topdown_event(NULL); 2985 } 2986 2987 /* 2988 * Checkpointed counters can lead to 'spurious' PMIs because the 2989 * rollback caused by the PMI will have cleared the overflow status 2990 * bit. Therefore always force probe these counters. 2991 */ 2992 status |= cpuc->intel_cp_status; 2993 2994 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2995 struct perf_event *event = cpuc->events[bit]; 2996 2997 handled++; 2998 2999 if (!test_bit(bit, cpuc->active_mask)) 3000 continue; 3001 3002 if (!intel_pmu_save_and_restart(event)) 3003 continue; 3004 3005 perf_sample_data_init(&data, 0, event->hw.last_period); 3006 3007 if (has_branch_stack(event)) 3008 data.br_stack = &cpuc->lbr_stack; 3009 3010 if (perf_event_overflow(event, &data, regs)) 3011 x86_pmu_stop(event, 0); 3012 } 3013 3014 return handled; 3015 } 3016 3017 /* 3018 * This handler is triggered by the local APIC, so the APIC IRQ handling 3019 * rules apply: 3020 */ 3021 static int intel_pmu_handle_irq(struct pt_regs *regs) 3022 { 3023 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3024 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3025 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3026 int loops; 3027 u64 status; 3028 int handled; 3029 int pmu_enabled; 3030 3031 /* 3032 * Save the PMU state. 3033 * It needs to be restored when leaving the handler. 3034 */ 3035 pmu_enabled = cpuc->enabled; 3036 /* 3037 * In general, the early ACK is only applied for old platforms. 3038 * For the big core starts from Haswell, the late ACK should be 3039 * applied. 3040 * For the small core after Tremont, we have to do the ACK right 3041 * before re-enabling counters, which is in the middle of the 3042 * NMI handler. 3043 */ 3044 if (!late_ack && !mid_ack) 3045 apic_write(APIC_LVTPC, APIC_DM_NMI); 3046 intel_bts_disable_local(); 3047 cpuc->enabled = 0; 3048 __intel_pmu_disable_all(true); 3049 handled = intel_pmu_drain_bts_buffer(); 3050 handled += intel_bts_interrupt(); 3051 status = intel_pmu_get_status(); 3052 if (!status) 3053 goto done; 3054 3055 loops = 0; 3056 again: 3057 intel_pmu_lbr_read(); 3058 intel_pmu_ack_status(status); 3059 if (++loops > 100) { 3060 static bool warned; 3061 3062 if (!warned) { 3063 WARN(1, "perfevents: irq loop stuck!\n"); 3064 perf_event_print_debug(); 3065 warned = true; 3066 } 3067 intel_pmu_reset(); 3068 goto done; 3069 } 3070 3071 handled += handle_pmi_common(regs, status); 3072 3073 /* 3074 * Repeat if there is more work to be done: 3075 */ 3076 status = intel_pmu_get_status(); 3077 if (status) 3078 goto again; 3079 3080 done: 3081 if (mid_ack) 3082 apic_write(APIC_LVTPC, APIC_DM_NMI); 3083 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3084 cpuc->enabled = pmu_enabled; 3085 if (pmu_enabled) 3086 __intel_pmu_enable_all(0, true); 3087 intel_bts_enable_local(); 3088 3089 /* 3090 * Only unmask the NMI after the overflow counters 3091 * have been reset. This avoids spurious NMIs on 3092 * Haswell CPUs. 3093 */ 3094 if (late_ack) 3095 apic_write(APIC_LVTPC, APIC_DM_NMI); 3096 return handled; 3097 } 3098 3099 static struct event_constraint * 3100 intel_bts_constraints(struct perf_event *event) 3101 { 3102 if (unlikely(intel_pmu_has_bts(event))) 3103 return &bts_constraint; 3104 3105 return NULL; 3106 } 3107 3108 /* 3109 * Note: matches a fake event, like Fixed2. 3110 */ 3111 static struct event_constraint * 3112 intel_vlbr_constraints(struct perf_event *event) 3113 { 3114 struct event_constraint *c = &vlbr_constraint; 3115 3116 if (unlikely(constraint_match(c, event->hw.config))) { 3117 event->hw.flags |= c->flags; 3118 return c; 3119 } 3120 3121 return NULL; 3122 } 3123 3124 static int intel_alt_er(struct cpu_hw_events *cpuc, 3125 int idx, u64 config) 3126 { 3127 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3128 int alt_idx = idx; 3129 3130 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3131 return idx; 3132 3133 if (idx == EXTRA_REG_RSP_0) 3134 alt_idx = EXTRA_REG_RSP_1; 3135 3136 if (idx == EXTRA_REG_RSP_1) 3137 alt_idx = EXTRA_REG_RSP_0; 3138 3139 if (config & ~extra_regs[alt_idx].valid_mask) 3140 return idx; 3141 3142 return alt_idx; 3143 } 3144 3145 static void intel_fixup_er(struct perf_event *event, int idx) 3146 { 3147 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3148 event->hw.extra_reg.idx = idx; 3149 3150 if (idx == EXTRA_REG_RSP_0) { 3151 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3152 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3153 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3154 } else if (idx == EXTRA_REG_RSP_1) { 3155 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3156 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3157 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3158 } 3159 } 3160 3161 /* 3162 * manage allocation of shared extra msr for certain events 3163 * 3164 * sharing can be: 3165 * per-cpu: to be shared between the various events on a single PMU 3166 * per-core: per-cpu + shared by HT threads 3167 */ 3168 static struct event_constraint * 3169 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3170 struct perf_event *event, 3171 struct hw_perf_event_extra *reg) 3172 { 3173 struct event_constraint *c = &emptyconstraint; 3174 struct er_account *era; 3175 unsigned long flags; 3176 int idx = reg->idx; 3177 3178 /* 3179 * reg->alloc can be set due to existing state, so for fake cpuc we 3180 * need to ignore this, otherwise we might fail to allocate proper fake 3181 * state for this extra reg constraint. Also see the comment below. 3182 */ 3183 if (reg->alloc && !cpuc->is_fake) 3184 return NULL; /* call x86_get_event_constraint() */ 3185 3186 again: 3187 era = &cpuc->shared_regs->regs[idx]; 3188 /* 3189 * we use spin_lock_irqsave() to avoid lockdep issues when 3190 * passing a fake cpuc 3191 */ 3192 raw_spin_lock_irqsave(&era->lock, flags); 3193 3194 if (!atomic_read(&era->ref) || era->config == reg->config) { 3195 3196 /* 3197 * If its a fake cpuc -- as per validate_{group,event}() we 3198 * shouldn't touch event state and we can avoid doing so 3199 * since both will only call get_event_constraints() once 3200 * on each event, this avoids the need for reg->alloc. 3201 * 3202 * Not doing the ER fixup will only result in era->reg being 3203 * wrong, but since we won't actually try and program hardware 3204 * this isn't a problem either. 3205 */ 3206 if (!cpuc->is_fake) { 3207 if (idx != reg->idx) 3208 intel_fixup_er(event, idx); 3209 3210 /* 3211 * x86_schedule_events() can call get_event_constraints() 3212 * multiple times on events in the case of incremental 3213 * scheduling(). reg->alloc ensures we only do the ER 3214 * allocation once. 3215 */ 3216 reg->alloc = 1; 3217 } 3218 3219 /* lock in msr value */ 3220 era->config = reg->config; 3221 era->reg = reg->reg; 3222 3223 /* one more user */ 3224 atomic_inc(&era->ref); 3225 3226 /* 3227 * need to call x86_get_event_constraint() 3228 * to check if associated event has constraints 3229 */ 3230 c = NULL; 3231 } else { 3232 idx = intel_alt_er(cpuc, idx, reg->config); 3233 if (idx != reg->idx) { 3234 raw_spin_unlock_irqrestore(&era->lock, flags); 3235 goto again; 3236 } 3237 } 3238 raw_spin_unlock_irqrestore(&era->lock, flags); 3239 3240 return c; 3241 } 3242 3243 static void 3244 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3245 struct hw_perf_event_extra *reg) 3246 { 3247 struct er_account *era; 3248 3249 /* 3250 * Only put constraint if extra reg was actually allocated. Also takes 3251 * care of event which do not use an extra shared reg. 3252 * 3253 * Also, if this is a fake cpuc we shouldn't touch any event state 3254 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3255 * either since it'll be thrown out. 3256 */ 3257 if (!reg->alloc || cpuc->is_fake) 3258 return; 3259 3260 era = &cpuc->shared_regs->regs[reg->idx]; 3261 3262 /* one fewer user */ 3263 atomic_dec(&era->ref); 3264 3265 /* allocate again next time */ 3266 reg->alloc = 0; 3267 } 3268 3269 static struct event_constraint * 3270 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3271 struct perf_event *event) 3272 { 3273 struct event_constraint *c = NULL, *d; 3274 struct hw_perf_event_extra *xreg, *breg; 3275 3276 xreg = &event->hw.extra_reg; 3277 if (xreg->idx != EXTRA_REG_NONE) { 3278 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3279 if (c == &emptyconstraint) 3280 return c; 3281 } 3282 breg = &event->hw.branch_reg; 3283 if (breg->idx != EXTRA_REG_NONE) { 3284 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3285 if (d == &emptyconstraint) { 3286 __intel_shared_reg_put_constraints(cpuc, xreg); 3287 c = d; 3288 } 3289 } 3290 return c; 3291 } 3292 3293 struct event_constraint * 3294 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3295 struct perf_event *event) 3296 { 3297 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3298 struct event_constraint *c; 3299 3300 if (event_constraints) { 3301 for_each_event_constraint(c, event_constraints) { 3302 if (constraint_match(c, event->hw.config)) { 3303 event->hw.flags |= c->flags; 3304 return c; 3305 } 3306 } 3307 } 3308 3309 return &hybrid_var(cpuc->pmu, unconstrained); 3310 } 3311 3312 static struct event_constraint * 3313 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3314 struct perf_event *event) 3315 { 3316 struct event_constraint *c; 3317 3318 c = intel_vlbr_constraints(event); 3319 if (c) 3320 return c; 3321 3322 c = intel_bts_constraints(event); 3323 if (c) 3324 return c; 3325 3326 c = intel_shared_regs_constraints(cpuc, event); 3327 if (c) 3328 return c; 3329 3330 c = intel_pebs_constraints(event); 3331 if (c) 3332 return c; 3333 3334 return x86_get_event_constraints(cpuc, idx, event); 3335 } 3336 3337 static void 3338 intel_start_scheduling(struct cpu_hw_events *cpuc) 3339 { 3340 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3341 struct intel_excl_states *xl; 3342 int tid = cpuc->excl_thread_id; 3343 3344 /* 3345 * nothing needed if in group validation mode 3346 */ 3347 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3348 return; 3349 3350 /* 3351 * no exclusion needed 3352 */ 3353 if (WARN_ON_ONCE(!excl_cntrs)) 3354 return; 3355 3356 xl = &excl_cntrs->states[tid]; 3357 3358 xl->sched_started = true; 3359 /* 3360 * lock shared state until we are done scheduling 3361 * in stop_event_scheduling() 3362 * makes scheduling appear as a transaction 3363 */ 3364 raw_spin_lock(&excl_cntrs->lock); 3365 } 3366 3367 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3368 { 3369 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3370 struct event_constraint *c = cpuc->event_constraint[idx]; 3371 struct intel_excl_states *xl; 3372 int tid = cpuc->excl_thread_id; 3373 3374 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3375 return; 3376 3377 if (WARN_ON_ONCE(!excl_cntrs)) 3378 return; 3379 3380 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3381 return; 3382 3383 xl = &excl_cntrs->states[tid]; 3384 3385 lockdep_assert_held(&excl_cntrs->lock); 3386 3387 if (c->flags & PERF_X86_EVENT_EXCL) 3388 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3389 else 3390 xl->state[cntr] = INTEL_EXCL_SHARED; 3391 } 3392 3393 static void 3394 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3395 { 3396 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3397 struct intel_excl_states *xl; 3398 int tid = cpuc->excl_thread_id; 3399 3400 /* 3401 * nothing needed if in group validation mode 3402 */ 3403 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3404 return; 3405 /* 3406 * no exclusion needed 3407 */ 3408 if (WARN_ON_ONCE(!excl_cntrs)) 3409 return; 3410 3411 xl = &excl_cntrs->states[tid]; 3412 3413 xl->sched_started = false; 3414 /* 3415 * release shared state lock (acquired in intel_start_scheduling()) 3416 */ 3417 raw_spin_unlock(&excl_cntrs->lock); 3418 } 3419 3420 static struct event_constraint * 3421 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3422 { 3423 WARN_ON_ONCE(!cpuc->constraint_list); 3424 3425 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3426 struct event_constraint *cx; 3427 3428 /* 3429 * grab pre-allocated constraint entry 3430 */ 3431 cx = &cpuc->constraint_list[idx]; 3432 3433 /* 3434 * initialize dynamic constraint 3435 * with static constraint 3436 */ 3437 *cx = *c; 3438 3439 /* 3440 * mark constraint as dynamic 3441 */ 3442 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3443 c = cx; 3444 } 3445 3446 return c; 3447 } 3448 3449 static struct event_constraint * 3450 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3451 int idx, struct event_constraint *c) 3452 { 3453 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3454 struct intel_excl_states *xlo; 3455 int tid = cpuc->excl_thread_id; 3456 int is_excl, i, w; 3457 3458 /* 3459 * validating a group does not require 3460 * enforcing cross-thread exclusion 3461 */ 3462 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3463 return c; 3464 3465 /* 3466 * no exclusion needed 3467 */ 3468 if (WARN_ON_ONCE(!excl_cntrs)) 3469 return c; 3470 3471 /* 3472 * because we modify the constraint, we need 3473 * to make a copy. Static constraints come 3474 * from static const tables. 3475 * 3476 * only needed when constraint has not yet 3477 * been cloned (marked dynamic) 3478 */ 3479 c = dyn_constraint(cpuc, c, idx); 3480 3481 /* 3482 * From here on, the constraint is dynamic. 3483 * Either it was just allocated above, or it 3484 * was allocated during a earlier invocation 3485 * of this function 3486 */ 3487 3488 /* 3489 * state of sibling HT 3490 */ 3491 xlo = &excl_cntrs->states[tid ^ 1]; 3492 3493 /* 3494 * event requires exclusive counter access 3495 * across HT threads 3496 */ 3497 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3498 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3499 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3500 if (!cpuc->n_excl++) 3501 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3502 } 3503 3504 /* 3505 * Modify static constraint with current dynamic 3506 * state of thread 3507 * 3508 * EXCLUSIVE: sibling counter measuring exclusive event 3509 * SHARED : sibling counter measuring non-exclusive event 3510 * UNUSED : sibling counter unused 3511 */ 3512 w = c->weight; 3513 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3514 /* 3515 * exclusive event in sibling counter 3516 * our corresponding counter cannot be used 3517 * regardless of our event 3518 */ 3519 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3520 __clear_bit(i, c->idxmsk); 3521 w--; 3522 continue; 3523 } 3524 /* 3525 * if measuring an exclusive event, sibling 3526 * measuring non-exclusive, then counter cannot 3527 * be used 3528 */ 3529 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3530 __clear_bit(i, c->idxmsk); 3531 w--; 3532 continue; 3533 } 3534 } 3535 3536 /* 3537 * if we return an empty mask, then switch 3538 * back to static empty constraint to avoid 3539 * the cost of freeing later on 3540 */ 3541 if (!w) 3542 c = &emptyconstraint; 3543 3544 c->weight = w; 3545 3546 return c; 3547 } 3548 3549 static struct event_constraint * 3550 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3551 struct perf_event *event) 3552 { 3553 struct event_constraint *c1, *c2; 3554 3555 c1 = cpuc->event_constraint[idx]; 3556 3557 /* 3558 * first time only 3559 * - static constraint: no change across incremental scheduling calls 3560 * - dynamic constraint: handled by intel_get_excl_constraints() 3561 */ 3562 c2 = __intel_get_event_constraints(cpuc, idx, event); 3563 if (c1) { 3564 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3565 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3566 c1->weight = c2->weight; 3567 c2 = c1; 3568 } 3569 3570 if (cpuc->excl_cntrs) 3571 return intel_get_excl_constraints(cpuc, event, idx, c2); 3572 3573 return c2; 3574 } 3575 3576 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3577 struct perf_event *event) 3578 { 3579 struct hw_perf_event *hwc = &event->hw; 3580 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3581 int tid = cpuc->excl_thread_id; 3582 struct intel_excl_states *xl; 3583 3584 /* 3585 * nothing needed if in group validation mode 3586 */ 3587 if (cpuc->is_fake) 3588 return; 3589 3590 if (WARN_ON_ONCE(!excl_cntrs)) 3591 return; 3592 3593 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3594 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3595 if (!--cpuc->n_excl) 3596 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3597 } 3598 3599 /* 3600 * If event was actually assigned, then mark the counter state as 3601 * unused now. 3602 */ 3603 if (hwc->idx >= 0) { 3604 xl = &excl_cntrs->states[tid]; 3605 3606 /* 3607 * put_constraint may be called from x86_schedule_events() 3608 * which already has the lock held so here make locking 3609 * conditional. 3610 */ 3611 if (!xl->sched_started) 3612 raw_spin_lock(&excl_cntrs->lock); 3613 3614 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3615 3616 if (!xl->sched_started) 3617 raw_spin_unlock(&excl_cntrs->lock); 3618 } 3619 } 3620 3621 static void 3622 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3623 struct perf_event *event) 3624 { 3625 struct hw_perf_event_extra *reg; 3626 3627 reg = &event->hw.extra_reg; 3628 if (reg->idx != EXTRA_REG_NONE) 3629 __intel_shared_reg_put_constraints(cpuc, reg); 3630 3631 reg = &event->hw.branch_reg; 3632 if (reg->idx != EXTRA_REG_NONE) 3633 __intel_shared_reg_put_constraints(cpuc, reg); 3634 } 3635 3636 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3637 struct perf_event *event) 3638 { 3639 intel_put_shared_regs_event_constraints(cpuc, event); 3640 3641 /* 3642 * is PMU has exclusive counter restrictions, then 3643 * all events are subject to and must call the 3644 * put_excl_constraints() routine 3645 */ 3646 if (cpuc->excl_cntrs) 3647 intel_put_excl_constraints(cpuc, event); 3648 } 3649 3650 static void intel_pebs_aliases_core2(struct perf_event *event) 3651 { 3652 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3653 /* 3654 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3655 * (0x003c) so that we can use it with PEBS. 3656 * 3657 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3658 * PEBS capable. However we can use INST_RETIRED.ANY_P 3659 * (0x00c0), which is a PEBS capable event, to get the same 3660 * count. 3661 * 3662 * INST_RETIRED.ANY_P counts the number of cycles that retires 3663 * CNTMASK instructions. By setting CNTMASK to a value (16) 3664 * larger than the maximum number of instructions that can be 3665 * retired per cycle (4) and then inverting the condition, we 3666 * count all cycles that retire 16 or less instructions, which 3667 * is every cycle. 3668 * 3669 * Thereby we gain a PEBS capable cycle counter. 3670 */ 3671 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3672 3673 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3674 event->hw.config = alt_config; 3675 } 3676 } 3677 3678 static void intel_pebs_aliases_snb(struct perf_event *event) 3679 { 3680 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3681 /* 3682 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3683 * (0x003c) so that we can use it with PEBS. 3684 * 3685 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3686 * PEBS capable. However we can use UOPS_RETIRED.ALL 3687 * (0x01c2), which is a PEBS capable event, to get the same 3688 * count. 3689 * 3690 * UOPS_RETIRED.ALL counts the number of cycles that retires 3691 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3692 * larger than the maximum number of micro-ops that can be 3693 * retired per cycle (4) and then inverting the condition, we 3694 * count all cycles that retire 16 or less micro-ops, which 3695 * is every cycle. 3696 * 3697 * Thereby we gain a PEBS capable cycle counter. 3698 */ 3699 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3700 3701 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3702 event->hw.config = alt_config; 3703 } 3704 } 3705 3706 static void intel_pebs_aliases_precdist(struct perf_event *event) 3707 { 3708 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3709 /* 3710 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3711 * (0x003c) so that we can use it with PEBS. 3712 * 3713 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3714 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3715 * (0x01c0), which is a PEBS capable event, to get the same 3716 * count. 3717 * 3718 * The PREC_DIST event has special support to minimize sample 3719 * shadowing effects. One drawback is that it can be 3720 * only programmed on counter 1, but that seems like an 3721 * acceptable trade off. 3722 */ 3723 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3724 3725 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3726 event->hw.config = alt_config; 3727 } 3728 } 3729 3730 static void intel_pebs_aliases_ivb(struct perf_event *event) 3731 { 3732 if (event->attr.precise_ip < 3) 3733 return intel_pebs_aliases_snb(event); 3734 return intel_pebs_aliases_precdist(event); 3735 } 3736 3737 static void intel_pebs_aliases_skl(struct perf_event *event) 3738 { 3739 if (event->attr.precise_ip < 3) 3740 return intel_pebs_aliases_core2(event); 3741 return intel_pebs_aliases_precdist(event); 3742 } 3743 3744 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3745 { 3746 unsigned long flags = x86_pmu.large_pebs_flags; 3747 3748 if (event->attr.use_clockid) 3749 flags &= ~PERF_SAMPLE_TIME; 3750 if (!event->attr.exclude_kernel) 3751 flags &= ~PERF_SAMPLE_REGS_USER; 3752 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3753 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3754 return flags; 3755 } 3756 3757 static int intel_pmu_bts_config(struct perf_event *event) 3758 { 3759 struct perf_event_attr *attr = &event->attr; 3760 3761 if (unlikely(intel_pmu_has_bts(event))) { 3762 /* BTS is not supported by this architecture. */ 3763 if (!x86_pmu.bts_active) 3764 return -EOPNOTSUPP; 3765 3766 /* BTS is currently only allowed for user-mode. */ 3767 if (!attr->exclude_kernel) 3768 return -EOPNOTSUPP; 3769 3770 /* BTS is not allowed for precise events. */ 3771 if (attr->precise_ip) 3772 return -EOPNOTSUPP; 3773 3774 /* disallow bts if conflicting events are present */ 3775 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3776 return -EBUSY; 3777 3778 event->destroy = hw_perf_lbr_event_destroy; 3779 } 3780 3781 return 0; 3782 } 3783 3784 static int core_pmu_hw_config(struct perf_event *event) 3785 { 3786 int ret = x86_pmu_hw_config(event); 3787 3788 if (ret) 3789 return ret; 3790 3791 return intel_pmu_bts_config(event); 3792 } 3793 3794 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3795 ((x86_pmu.num_topdown_events - 1) << 8)) 3796 3797 static bool is_available_metric_event(struct perf_event *event) 3798 { 3799 return is_metric_event(event) && 3800 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3801 } 3802 3803 static inline bool is_mem_loads_event(struct perf_event *event) 3804 { 3805 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3806 } 3807 3808 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3809 { 3810 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3811 } 3812 3813 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3814 { 3815 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3816 return false; 3817 3818 if (is_hybrid()) 3819 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3820 3821 return true; 3822 } 3823 3824 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3825 { 3826 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3827 3828 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3829 } 3830 3831 static int intel_pmu_hw_config(struct perf_event *event) 3832 { 3833 int ret = x86_pmu_hw_config(event); 3834 3835 if (ret) 3836 return ret; 3837 3838 ret = intel_pmu_bts_config(event); 3839 if (ret) 3840 return ret; 3841 3842 if (event->attr.precise_ip) { 3843 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3844 return -EINVAL; 3845 3846 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3847 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3848 if (!(event->attr.sample_type & 3849 ~intel_pmu_large_pebs_flags(event))) { 3850 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3851 event->attach_state |= PERF_ATTACH_SCHED_CB; 3852 } 3853 } 3854 if (x86_pmu.pebs_aliases) 3855 x86_pmu.pebs_aliases(event); 3856 3857 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3858 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3859 } 3860 3861 if (needs_branch_stack(event)) { 3862 ret = intel_pmu_setup_lbr_filter(event); 3863 if (ret) 3864 return ret; 3865 event->attach_state |= PERF_ATTACH_SCHED_CB; 3866 3867 /* 3868 * BTS is set up earlier in this path, so don't account twice 3869 */ 3870 if (!unlikely(intel_pmu_has_bts(event))) { 3871 /* disallow lbr if conflicting events are present */ 3872 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3873 return -EBUSY; 3874 3875 event->destroy = hw_perf_lbr_event_destroy; 3876 } 3877 } 3878 3879 if (event->attr.aux_output) { 3880 if (!event->attr.precise_ip) 3881 return -EINVAL; 3882 3883 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3884 } 3885 3886 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3887 (event->attr.type == PERF_TYPE_HW_CACHE)) 3888 return 0; 3889 3890 /* 3891 * Config Topdown slots and metric events 3892 * 3893 * The slots event on Fixed Counter 3 can support sampling, 3894 * which will be handled normally in x86_perf_event_update(). 3895 * 3896 * Metric events don't support sampling and require being paired 3897 * with a slots event as group leader. When the slots event 3898 * is used in a metrics group, it too cannot support sampling. 3899 */ 3900 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3901 if (event->attr.config1 || event->attr.config2) 3902 return -EINVAL; 3903 3904 /* 3905 * The TopDown metrics events and slots event don't 3906 * support any filters. 3907 */ 3908 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3909 return -EINVAL; 3910 3911 if (is_available_metric_event(event)) { 3912 struct perf_event *leader = event->group_leader; 3913 3914 /* The metric events don't support sampling. */ 3915 if (is_sampling_event(event)) 3916 return -EINVAL; 3917 3918 /* The metric events require a slots group leader. */ 3919 if (!is_slots_event(leader)) 3920 return -EINVAL; 3921 3922 /* 3923 * The leader/SLOTS must not be a sampling event for 3924 * metric use; hardware requires it starts at 0 when used 3925 * in conjunction with MSR_PERF_METRICS. 3926 */ 3927 if (is_sampling_event(leader)) 3928 return -EINVAL; 3929 3930 event->event_caps |= PERF_EV_CAP_SIBLING; 3931 /* 3932 * Only once we have a METRICs sibling do we 3933 * need TopDown magic. 3934 */ 3935 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3936 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3937 } 3938 } 3939 3940 /* 3941 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3942 * doesn't function quite right. As a work-around it needs to always be 3943 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3944 * The actual count of this second event is irrelevant it just needs 3945 * to be active to make the first event function correctly. 3946 * 3947 * In a group, the auxiliary event must be in front of the load latency 3948 * event. The rule is to simplify the implementation of the check. 3949 * That's because perf cannot have a complete group at the moment. 3950 */ 3951 if (require_mem_loads_aux_event(event) && 3952 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3953 is_mem_loads_event(event)) { 3954 struct perf_event *leader = event->group_leader; 3955 struct perf_event *sibling = NULL; 3956 3957 if (!is_mem_loads_aux_event(leader)) { 3958 for_each_sibling_event(sibling, leader) { 3959 if (is_mem_loads_aux_event(sibling)) 3960 break; 3961 } 3962 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3963 return -ENODATA; 3964 } 3965 } 3966 3967 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3968 return 0; 3969 3970 if (x86_pmu.version < 3) 3971 return -EINVAL; 3972 3973 ret = perf_allow_cpu(&event->attr); 3974 if (ret) 3975 return ret; 3976 3977 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3978 3979 return 0; 3980 } 3981 3982 /* 3983 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 3984 * The host perf conext helps to prepare the values of the real hardware for 3985 * a set of msrs that need to be switched atomically in a vmx transaction. 3986 * 3987 * For example, the pseudocode needed to add a new msr should look like: 3988 * 3989 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 3990 * .msr = the hardware msr address, 3991 * .host = the value the hardware has when it doesn't run a guest, 3992 * .guest = the value the hardware has when it runs a guest, 3993 * }; 3994 * 3995 * These values have nothing to do with the emulated values the guest sees 3996 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 3997 * specifically in the intel_pmu_{get,set}_msr(). 3998 */ 3999 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4000 { 4001 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4002 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4003 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4004 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4005 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4006 int global_ctrl, pebs_enable; 4007 4008 *nr = 0; 4009 global_ctrl = (*nr)++; 4010 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4011 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4012 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4013 .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask), 4014 }; 4015 4016 if (!x86_pmu.pebs) 4017 return arr; 4018 4019 /* 4020 * If PMU counter has PEBS enabled it is not enough to 4021 * disable counter on a guest entry since PEBS memory 4022 * write can overshoot guest entry and corrupt guest 4023 * memory. Disabling PEBS solves the problem. 4024 * 4025 * Don't do this if the CPU already enforces it. 4026 */ 4027 if (x86_pmu.pebs_no_isolation) { 4028 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4029 .msr = MSR_IA32_PEBS_ENABLE, 4030 .host = cpuc->pebs_enabled, 4031 .guest = 0, 4032 }; 4033 return arr; 4034 } 4035 4036 if (!kvm_pmu || !x86_pmu.pebs_ept) 4037 return arr; 4038 4039 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4040 .msr = MSR_IA32_DS_AREA, 4041 .host = (unsigned long)cpuc->ds, 4042 .guest = kvm_pmu->ds_area, 4043 }; 4044 4045 if (x86_pmu.intel_cap.pebs_baseline) { 4046 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4047 .msr = MSR_PEBS_DATA_CFG, 4048 .host = cpuc->pebs_data_cfg, 4049 .guest = kvm_pmu->pebs_data_cfg, 4050 }; 4051 } 4052 4053 pebs_enable = (*nr)++; 4054 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4055 .msr = MSR_IA32_PEBS_ENABLE, 4056 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4057 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, 4058 }; 4059 4060 if (arr[pebs_enable].host) { 4061 /* Disable guest PEBS if host PEBS is enabled. */ 4062 arr[pebs_enable].guest = 0; 4063 } else { 4064 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4065 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4066 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4067 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4068 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4069 } 4070 4071 return arr; 4072 } 4073 4074 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4075 { 4076 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4077 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4078 int idx; 4079 4080 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4081 struct perf_event *event = cpuc->events[idx]; 4082 4083 arr[idx].msr = x86_pmu_config_addr(idx); 4084 arr[idx].host = arr[idx].guest = 0; 4085 4086 if (!test_bit(idx, cpuc->active_mask)) 4087 continue; 4088 4089 arr[idx].host = arr[idx].guest = 4090 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4091 4092 if (event->attr.exclude_host) 4093 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4094 else if (event->attr.exclude_guest) 4095 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4096 } 4097 4098 *nr = x86_pmu.num_counters; 4099 return arr; 4100 } 4101 4102 static void core_pmu_enable_event(struct perf_event *event) 4103 { 4104 if (!event->attr.exclude_host) 4105 x86_pmu_enable_event(event); 4106 } 4107 4108 static void core_pmu_enable_all(int added) 4109 { 4110 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4111 int idx; 4112 4113 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4114 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4115 4116 if (!test_bit(idx, cpuc->active_mask) || 4117 cpuc->events[idx]->attr.exclude_host) 4118 continue; 4119 4120 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4121 } 4122 } 4123 4124 static int hsw_hw_config(struct perf_event *event) 4125 { 4126 int ret = intel_pmu_hw_config(event); 4127 4128 if (ret) 4129 return ret; 4130 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4131 return 0; 4132 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4133 4134 /* 4135 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4136 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4137 * this combination. 4138 */ 4139 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4140 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4141 event->attr.precise_ip > 0)) 4142 return -EOPNOTSUPP; 4143 4144 if (event_is_checkpointed(event)) { 4145 /* 4146 * Sampling of checkpointed events can cause situations where 4147 * the CPU constantly aborts because of a overflow, which is 4148 * then checkpointed back and ignored. Forbid checkpointing 4149 * for sampling. 4150 * 4151 * But still allow a long sampling period, so that perf stat 4152 * from KVM works. 4153 */ 4154 if (event->attr.sample_period > 0 && 4155 event->attr.sample_period < 0x7fffffff) 4156 return -EOPNOTSUPP; 4157 } 4158 return 0; 4159 } 4160 4161 static struct event_constraint counter0_constraint = 4162 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4163 4164 static struct event_constraint counter2_constraint = 4165 EVENT_CONSTRAINT(0, 0x4, 0); 4166 4167 static struct event_constraint fixed0_constraint = 4168 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4169 4170 static struct event_constraint fixed0_counter0_constraint = 4171 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4172 4173 static struct event_constraint * 4174 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4175 struct perf_event *event) 4176 { 4177 struct event_constraint *c; 4178 4179 c = intel_get_event_constraints(cpuc, idx, event); 4180 4181 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4182 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4183 if (c->idxmsk64 & (1U << 2)) 4184 return &counter2_constraint; 4185 return &emptyconstraint; 4186 } 4187 4188 return c; 4189 } 4190 4191 static struct event_constraint * 4192 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4193 struct perf_event *event) 4194 { 4195 /* 4196 * Fixed counter 0 has less skid. 4197 * Force instruction:ppp in Fixed counter 0 4198 */ 4199 if ((event->attr.precise_ip == 3) && 4200 constraint_match(&fixed0_constraint, event->hw.config)) 4201 return &fixed0_constraint; 4202 4203 return hsw_get_event_constraints(cpuc, idx, event); 4204 } 4205 4206 static struct event_constraint * 4207 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4208 struct perf_event *event) 4209 { 4210 struct event_constraint *c; 4211 4212 c = icl_get_event_constraints(cpuc, idx, event); 4213 4214 /* 4215 * The :ppp indicates the Precise Distribution (PDist) facility, which 4216 * is only supported on the GP counter 0. If a :ppp event which is not 4217 * available on the GP counter 0, error out. 4218 * Exception: Instruction PDIR is only available on the fixed counter 0. 4219 */ 4220 if ((event->attr.precise_ip == 3) && 4221 !constraint_match(&fixed0_constraint, event->hw.config)) { 4222 if (c->idxmsk64 & BIT_ULL(0)) 4223 return &counter0_constraint; 4224 4225 return &emptyconstraint; 4226 } 4227 4228 return c; 4229 } 4230 4231 static struct event_constraint * 4232 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4233 struct perf_event *event) 4234 { 4235 struct event_constraint *c; 4236 4237 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4238 if (event->attr.precise_ip == 3) 4239 return &counter0_constraint; 4240 4241 c = intel_get_event_constraints(cpuc, idx, event); 4242 4243 return c; 4244 } 4245 4246 static struct event_constraint * 4247 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4248 struct perf_event *event) 4249 { 4250 struct event_constraint *c; 4251 4252 c = intel_get_event_constraints(cpuc, idx, event); 4253 4254 /* 4255 * :ppp means to do reduced skid PEBS, 4256 * which is available on PMC0 and fixed counter 0. 4257 */ 4258 if (event->attr.precise_ip == 3) { 4259 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4260 if (constraint_match(&fixed0_constraint, event->hw.config)) 4261 return &fixed0_counter0_constraint; 4262 4263 return &counter0_constraint; 4264 } 4265 4266 return c; 4267 } 4268 4269 static bool allow_tsx_force_abort = true; 4270 4271 static struct event_constraint * 4272 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4273 struct perf_event *event) 4274 { 4275 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4276 4277 /* 4278 * Without TFA we must not use PMC3. 4279 */ 4280 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4281 c = dyn_constraint(cpuc, c, idx); 4282 c->idxmsk64 &= ~(1ULL << 3); 4283 c->weight--; 4284 } 4285 4286 return c; 4287 } 4288 4289 static struct event_constraint * 4290 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4291 struct perf_event *event) 4292 { 4293 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4294 4295 if (pmu->cpu_type == hybrid_big) 4296 return spr_get_event_constraints(cpuc, idx, event); 4297 else if (pmu->cpu_type == hybrid_small) 4298 return tnt_get_event_constraints(cpuc, idx, event); 4299 4300 WARN_ON(1); 4301 return &emptyconstraint; 4302 } 4303 4304 static int adl_hw_config(struct perf_event *event) 4305 { 4306 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4307 4308 if (pmu->cpu_type == hybrid_big) 4309 return hsw_hw_config(event); 4310 else if (pmu->cpu_type == hybrid_small) 4311 return intel_pmu_hw_config(event); 4312 4313 WARN_ON(1); 4314 return -EOPNOTSUPP; 4315 } 4316 4317 static u8 adl_get_hybrid_cpu_type(void) 4318 { 4319 return hybrid_big; 4320 } 4321 4322 /* 4323 * Broadwell: 4324 * 4325 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4326 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4327 * the two to enforce a minimum period of 128 (the smallest value that has bits 4328 * 0-5 cleared and >= 100). 4329 * 4330 * Because of how the code in x86_perf_event_set_period() works, the truncation 4331 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4332 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4333 * 4334 * Therefore the effective (average) period matches the requested period, 4335 * despite coarser hardware granularity. 4336 */ 4337 static u64 bdw_limit_period(struct perf_event *event, u64 left) 4338 { 4339 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4340 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4341 if (left < 128) 4342 left = 128; 4343 left &= ~0x3fULL; 4344 } 4345 return left; 4346 } 4347 4348 static u64 nhm_limit_period(struct perf_event *event, u64 left) 4349 { 4350 return max(left, 32ULL); 4351 } 4352 4353 static u64 spr_limit_period(struct perf_event *event, u64 left) 4354 { 4355 if (event->attr.precise_ip == 3) 4356 return max(left, 128ULL); 4357 4358 return left; 4359 } 4360 4361 PMU_FORMAT_ATTR(event, "config:0-7" ); 4362 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4363 PMU_FORMAT_ATTR(edge, "config:18" ); 4364 PMU_FORMAT_ATTR(pc, "config:19" ); 4365 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4366 PMU_FORMAT_ATTR(inv, "config:23" ); 4367 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4368 PMU_FORMAT_ATTR(in_tx, "config:32"); 4369 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4370 4371 static struct attribute *intel_arch_formats_attr[] = { 4372 &format_attr_event.attr, 4373 &format_attr_umask.attr, 4374 &format_attr_edge.attr, 4375 &format_attr_pc.attr, 4376 &format_attr_inv.attr, 4377 &format_attr_cmask.attr, 4378 NULL, 4379 }; 4380 4381 ssize_t intel_event_sysfs_show(char *page, u64 config) 4382 { 4383 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4384 4385 return x86_event_sysfs_show(page, config, event); 4386 } 4387 4388 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4389 { 4390 struct intel_shared_regs *regs; 4391 int i; 4392 4393 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4394 GFP_KERNEL, cpu_to_node(cpu)); 4395 if (regs) { 4396 /* 4397 * initialize the locks to keep lockdep happy 4398 */ 4399 for (i = 0; i < EXTRA_REG_MAX; i++) 4400 raw_spin_lock_init(®s->regs[i].lock); 4401 4402 regs->core_id = -1; 4403 } 4404 return regs; 4405 } 4406 4407 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4408 { 4409 struct intel_excl_cntrs *c; 4410 4411 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4412 GFP_KERNEL, cpu_to_node(cpu)); 4413 if (c) { 4414 raw_spin_lock_init(&c->lock); 4415 c->core_id = -1; 4416 } 4417 return c; 4418 } 4419 4420 4421 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4422 { 4423 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4424 4425 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4426 cpuc->shared_regs = allocate_shared_regs(cpu); 4427 if (!cpuc->shared_regs) 4428 goto err; 4429 } 4430 4431 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4432 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4433 4434 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4435 if (!cpuc->constraint_list) 4436 goto err_shared_regs; 4437 } 4438 4439 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4440 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4441 if (!cpuc->excl_cntrs) 4442 goto err_constraint_list; 4443 4444 cpuc->excl_thread_id = 0; 4445 } 4446 4447 return 0; 4448 4449 err_constraint_list: 4450 kfree(cpuc->constraint_list); 4451 cpuc->constraint_list = NULL; 4452 4453 err_shared_regs: 4454 kfree(cpuc->shared_regs); 4455 cpuc->shared_regs = NULL; 4456 4457 err: 4458 return -ENOMEM; 4459 } 4460 4461 static int intel_pmu_cpu_prepare(int cpu) 4462 { 4463 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4464 } 4465 4466 static void flip_smm_bit(void *data) 4467 { 4468 unsigned long set = *(unsigned long *)data; 4469 4470 if (set > 0) { 4471 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4472 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4473 } else { 4474 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4475 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4476 } 4477 } 4478 4479 static bool init_hybrid_pmu(int cpu) 4480 { 4481 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4482 u8 cpu_type = get_this_hybrid_cpu_type(); 4483 struct x86_hybrid_pmu *pmu = NULL; 4484 int i; 4485 4486 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4487 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4488 4489 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4490 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4491 pmu = &x86_pmu.hybrid_pmu[i]; 4492 break; 4493 } 4494 } 4495 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4496 cpuc->pmu = NULL; 4497 return false; 4498 } 4499 4500 /* Only check and dump the PMU information for the first CPU */ 4501 if (!cpumask_empty(&pmu->supported_cpus)) 4502 goto end; 4503 4504 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4505 return false; 4506 4507 pr_info("%s PMU driver: ", pmu->name); 4508 4509 if (pmu->intel_cap.pebs_output_pt_available) 4510 pr_cont("PEBS-via-PT "); 4511 4512 pr_cont("\n"); 4513 4514 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4515 pmu->intel_ctrl); 4516 4517 end: 4518 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4519 cpuc->pmu = &pmu->pmu; 4520 4521 x86_pmu_update_cpu_context(&pmu->pmu, cpu); 4522 4523 return true; 4524 } 4525 4526 static void intel_pmu_cpu_starting(int cpu) 4527 { 4528 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4529 int core_id = topology_core_id(cpu); 4530 int i; 4531 4532 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4533 return; 4534 4535 init_debug_store_on_cpu(cpu); 4536 /* 4537 * Deal with CPUs that don't clear their LBRs on power-up. 4538 */ 4539 intel_pmu_lbr_reset(); 4540 4541 cpuc->lbr_sel = NULL; 4542 4543 if (x86_pmu.flags & PMU_FL_TFA) { 4544 WARN_ON_ONCE(cpuc->tfa_shadow); 4545 cpuc->tfa_shadow = ~0ULL; 4546 intel_set_tfa(cpuc, false); 4547 } 4548 4549 if (x86_pmu.version > 1) 4550 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4551 4552 /* 4553 * Disable perf metrics if any added CPU doesn't support it. 4554 * 4555 * Turn off the check for a hybrid architecture, because the 4556 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4557 * the architecture features. The perf metrics is a model-specific 4558 * feature for now. The corresponding bit should always be 0 on 4559 * a hybrid platform, e.g., Alder Lake. 4560 */ 4561 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4562 union perf_capabilities perf_cap; 4563 4564 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4565 if (!perf_cap.perf_metrics) { 4566 x86_pmu.intel_cap.perf_metrics = 0; 4567 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4568 } 4569 } 4570 4571 if (!cpuc->shared_regs) 4572 return; 4573 4574 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4575 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4576 struct intel_shared_regs *pc; 4577 4578 pc = per_cpu(cpu_hw_events, i).shared_regs; 4579 if (pc && pc->core_id == core_id) { 4580 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4581 cpuc->shared_regs = pc; 4582 break; 4583 } 4584 } 4585 cpuc->shared_regs->core_id = core_id; 4586 cpuc->shared_regs->refcnt++; 4587 } 4588 4589 if (x86_pmu.lbr_sel_map) 4590 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4591 4592 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4593 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4594 struct cpu_hw_events *sibling; 4595 struct intel_excl_cntrs *c; 4596 4597 sibling = &per_cpu(cpu_hw_events, i); 4598 c = sibling->excl_cntrs; 4599 if (c && c->core_id == core_id) { 4600 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4601 cpuc->excl_cntrs = c; 4602 if (!sibling->excl_thread_id) 4603 cpuc->excl_thread_id = 1; 4604 break; 4605 } 4606 } 4607 cpuc->excl_cntrs->core_id = core_id; 4608 cpuc->excl_cntrs->refcnt++; 4609 } 4610 } 4611 4612 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4613 { 4614 struct intel_excl_cntrs *c; 4615 4616 c = cpuc->excl_cntrs; 4617 if (c) { 4618 if (c->core_id == -1 || --c->refcnt == 0) 4619 kfree(c); 4620 cpuc->excl_cntrs = NULL; 4621 } 4622 4623 kfree(cpuc->constraint_list); 4624 cpuc->constraint_list = NULL; 4625 } 4626 4627 static void intel_pmu_cpu_dying(int cpu) 4628 { 4629 fini_debug_store_on_cpu(cpu); 4630 } 4631 4632 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4633 { 4634 struct intel_shared_regs *pc; 4635 4636 pc = cpuc->shared_regs; 4637 if (pc) { 4638 if (pc->core_id == -1 || --pc->refcnt == 0) 4639 kfree(pc); 4640 cpuc->shared_regs = NULL; 4641 } 4642 4643 free_excl_cntrs(cpuc); 4644 } 4645 4646 static void intel_pmu_cpu_dead(int cpu) 4647 { 4648 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4649 4650 intel_cpuc_finish(cpuc); 4651 4652 if (is_hybrid() && cpuc->pmu) 4653 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4654 } 4655 4656 static void intel_pmu_sched_task(struct perf_event_context *ctx, 4657 bool sched_in) 4658 { 4659 intel_pmu_pebs_sched_task(ctx, sched_in); 4660 intel_pmu_lbr_sched_task(ctx, sched_in); 4661 } 4662 4663 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4664 struct perf_event_context *next) 4665 { 4666 intel_pmu_lbr_swap_task_ctx(prev, next); 4667 } 4668 4669 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4670 { 4671 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4672 } 4673 4674 static void intel_aux_output_init(void) 4675 { 4676 /* Refer also intel_pmu_aux_output_match() */ 4677 if (x86_pmu.intel_cap.pebs_output_pt_available) 4678 x86_pmu.assign = intel_pmu_assign_event; 4679 } 4680 4681 static int intel_pmu_aux_output_match(struct perf_event *event) 4682 { 4683 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 4684 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4685 return 0; 4686 4687 return is_intel_pt_event(event); 4688 } 4689 4690 static int intel_pmu_filter_match(struct perf_event *event) 4691 { 4692 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4693 unsigned int cpu = smp_processor_id(); 4694 4695 return cpumask_test_cpu(cpu, &pmu->supported_cpus); 4696 } 4697 4698 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4699 4700 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4701 4702 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4703 4704 static struct attribute *intel_arch3_formats_attr[] = { 4705 &format_attr_event.attr, 4706 &format_attr_umask.attr, 4707 &format_attr_edge.attr, 4708 &format_attr_pc.attr, 4709 &format_attr_any.attr, 4710 &format_attr_inv.attr, 4711 &format_attr_cmask.attr, 4712 NULL, 4713 }; 4714 4715 static struct attribute *hsw_format_attr[] = { 4716 &format_attr_in_tx.attr, 4717 &format_attr_in_tx_cp.attr, 4718 &format_attr_offcore_rsp.attr, 4719 &format_attr_ldlat.attr, 4720 NULL 4721 }; 4722 4723 static struct attribute *nhm_format_attr[] = { 4724 &format_attr_offcore_rsp.attr, 4725 &format_attr_ldlat.attr, 4726 NULL 4727 }; 4728 4729 static struct attribute *slm_format_attr[] = { 4730 &format_attr_offcore_rsp.attr, 4731 NULL 4732 }; 4733 4734 static struct attribute *skl_format_attr[] = { 4735 &format_attr_frontend.attr, 4736 NULL, 4737 }; 4738 4739 static __initconst const struct x86_pmu core_pmu = { 4740 .name = "core", 4741 .handle_irq = x86_pmu_handle_irq, 4742 .disable_all = x86_pmu_disable_all, 4743 .enable_all = core_pmu_enable_all, 4744 .enable = core_pmu_enable_event, 4745 .disable = x86_pmu_disable_event, 4746 .hw_config = core_pmu_hw_config, 4747 .schedule_events = x86_schedule_events, 4748 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4749 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4750 .event_map = intel_pmu_event_map, 4751 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4752 .apic = 1, 4753 .large_pebs_flags = LARGE_PEBS_FLAGS, 4754 4755 /* 4756 * Intel PMCs cannot be accessed sanely above 32-bit width, 4757 * so we install an artificial 1<<31 period regardless of 4758 * the generic event period: 4759 */ 4760 .max_period = (1ULL<<31) - 1, 4761 .get_event_constraints = intel_get_event_constraints, 4762 .put_event_constraints = intel_put_event_constraints, 4763 .event_constraints = intel_core_event_constraints, 4764 .guest_get_msrs = core_guest_get_msrs, 4765 .format_attrs = intel_arch_formats_attr, 4766 .events_sysfs_show = intel_event_sysfs_show, 4767 4768 /* 4769 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4770 * together with PMU version 1 and thus be using core_pmu with 4771 * shared_regs. We need following callbacks here to allocate 4772 * it properly. 4773 */ 4774 .cpu_prepare = intel_pmu_cpu_prepare, 4775 .cpu_starting = intel_pmu_cpu_starting, 4776 .cpu_dying = intel_pmu_cpu_dying, 4777 .cpu_dead = intel_pmu_cpu_dead, 4778 4779 .check_period = intel_pmu_check_period, 4780 4781 .lbr_reset = intel_pmu_lbr_reset_64, 4782 .lbr_read = intel_pmu_lbr_read_64, 4783 .lbr_save = intel_pmu_lbr_save, 4784 .lbr_restore = intel_pmu_lbr_restore, 4785 }; 4786 4787 static __initconst const struct x86_pmu intel_pmu = { 4788 .name = "Intel", 4789 .handle_irq = intel_pmu_handle_irq, 4790 .disable_all = intel_pmu_disable_all, 4791 .enable_all = intel_pmu_enable_all, 4792 .enable = intel_pmu_enable_event, 4793 .disable = intel_pmu_disable_event, 4794 .add = intel_pmu_add_event, 4795 .del = intel_pmu_del_event, 4796 .read = intel_pmu_read_event, 4797 .hw_config = intel_pmu_hw_config, 4798 .schedule_events = x86_schedule_events, 4799 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4800 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4801 .event_map = intel_pmu_event_map, 4802 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4803 .apic = 1, 4804 .large_pebs_flags = LARGE_PEBS_FLAGS, 4805 /* 4806 * Intel PMCs cannot be accessed sanely above 32 bit width, 4807 * so we install an artificial 1<<31 period regardless of 4808 * the generic event period: 4809 */ 4810 .max_period = (1ULL << 31) - 1, 4811 .get_event_constraints = intel_get_event_constraints, 4812 .put_event_constraints = intel_put_event_constraints, 4813 .pebs_aliases = intel_pebs_aliases_core2, 4814 4815 .format_attrs = intel_arch3_formats_attr, 4816 .events_sysfs_show = intel_event_sysfs_show, 4817 4818 .cpu_prepare = intel_pmu_cpu_prepare, 4819 .cpu_starting = intel_pmu_cpu_starting, 4820 .cpu_dying = intel_pmu_cpu_dying, 4821 .cpu_dead = intel_pmu_cpu_dead, 4822 4823 .guest_get_msrs = intel_guest_get_msrs, 4824 .sched_task = intel_pmu_sched_task, 4825 .swap_task_ctx = intel_pmu_swap_task_ctx, 4826 4827 .check_period = intel_pmu_check_period, 4828 4829 .aux_output_match = intel_pmu_aux_output_match, 4830 4831 .lbr_reset = intel_pmu_lbr_reset_64, 4832 .lbr_read = intel_pmu_lbr_read_64, 4833 .lbr_save = intel_pmu_lbr_save, 4834 .lbr_restore = intel_pmu_lbr_restore, 4835 4836 /* 4837 * SMM has access to all 4 rings and while traditionally SMM code only 4838 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 4839 * 4840 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 4841 * between SMM or not, this results in what should be pure userspace 4842 * counters including SMM data. 4843 * 4844 * This is a clear privilege issue, therefore globally disable 4845 * counting SMM by default. 4846 */ 4847 .attr_freeze_on_smi = 1, 4848 }; 4849 4850 static __init void intel_clovertown_quirk(void) 4851 { 4852 /* 4853 * PEBS is unreliable due to: 4854 * 4855 * AJ67 - PEBS may experience CPL leaks 4856 * AJ68 - PEBS PMI may be delayed by one event 4857 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4858 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4859 * 4860 * AJ67 could be worked around by restricting the OS/USR flags. 4861 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4862 * 4863 * AJ106 could possibly be worked around by not allowing LBR 4864 * usage from PEBS, including the fixup. 4865 * AJ68 could possibly be worked around by always programming 4866 * a pebs_event_reset[0] value and coping with the lost events. 4867 * 4868 * But taken together it might just make sense to not enable PEBS on 4869 * these chips. 4870 */ 4871 pr_warn("PEBS disabled due to CPU errata\n"); 4872 x86_pmu.pebs = 0; 4873 x86_pmu.pebs_constraints = NULL; 4874 } 4875 4876 static const struct x86_cpu_desc isolation_ucodes[] = { 4877 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4878 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 4879 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 4880 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 4881 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4882 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 4883 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 4884 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 4885 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 4886 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 4887 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 4888 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 4889 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 4890 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4891 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 4892 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 4893 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 4894 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4895 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4896 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4897 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4898 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4899 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4900 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4901 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4902 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4903 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4904 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 4905 {} 4906 }; 4907 4908 static void intel_check_pebs_isolation(void) 4909 { 4910 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4911 } 4912 4913 static __init void intel_pebs_isolation_quirk(void) 4914 { 4915 WARN_ON_ONCE(x86_pmu.check_microcode); 4916 x86_pmu.check_microcode = intel_check_pebs_isolation; 4917 intel_check_pebs_isolation(); 4918 } 4919 4920 static const struct x86_cpu_desc pebs_ucodes[] = { 4921 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4922 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4923 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4924 {} 4925 }; 4926 4927 static bool intel_snb_pebs_broken(void) 4928 { 4929 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4930 } 4931 4932 static void intel_snb_check_microcode(void) 4933 { 4934 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4935 return; 4936 4937 /* 4938 * Serialized by the microcode lock.. 4939 */ 4940 if (x86_pmu.pebs_broken) { 4941 pr_info("PEBS enabled due to microcode update\n"); 4942 x86_pmu.pebs_broken = 0; 4943 } else { 4944 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4945 x86_pmu.pebs_broken = 1; 4946 } 4947 } 4948 4949 static bool is_lbr_from(unsigned long msr) 4950 { 4951 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4952 4953 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4954 } 4955 4956 /* 4957 * Under certain circumstances, access certain MSR may cause #GP. 4958 * The function tests if the input MSR can be safely accessed. 4959 */ 4960 static bool check_msr(unsigned long msr, u64 mask) 4961 { 4962 u64 val_old, val_new, val_tmp; 4963 4964 /* 4965 * Disable the check for real HW, so we don't 4966 * mess with potentially enabled registers: 4967 */ 4968 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4969 return true; 4970 4971 /* 4972 * Read the current value, change it and read it back to see if it 4973 * matches, this is needed to detect certain hardware emulators 4974 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4975 */ 4976 if (rdmsrl_safe(msr, &val_old)) 4977 return false; 4978 4979 /* 4980 * Only change the bits which can be updated by wrmsrl. 4981 */ 4982 val_tmp = val_old ^ mask; 4983 4984 if (is_lbr_from(msr)) 4985 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4986 4987 if (wrmsrl_safe(msr, val_tmp) || 4988 rdmsrl_safe(msr, &val_new)) 4989 return false; 4990 4991 /* 4992 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4993 * should equal rdmsrl()'s even with the quirk. 4994 */ 4995 if (val_new != val_tmp) 4996 return false; 4997 4998 if (is_lbr_from(msr)) 4999 val_old = lbr_from_signext_quirk_wr(val_old); 5000 5001 /* Here it's sure that the MSR can be safely accessed. 5002 * Restore the old value and return. 5003 */ 5004 wrmsrl(msr, val_old); 5005 5006 return true; 5007 } 5008 5009 static __init void intel_sandybridge_quirk(void) 5010 { 5011 x86_pmu.check_microcode = intel_snb_check_microcode; 5012 cpus_read_lock(); 5013 intel_snb_check_microcode(); 5014 cpus_read_unlock(); 5015 } 5016 5017 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5018 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5019 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5020 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5021 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5022 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5023 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5024 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5025 }; 5026 5027 static __init void intel_arch_events_quirk(void) 5028 { 5029 int bit; 5030 5031 /* disable event that reported as not present by cpuid */ 5032 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5033 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5034 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5035 intel_arch_events_map[bit].name); 5036 } 5037 } 5038 5039 static __init void intel_nehalem_quirk(void) 5040 { 5041 union cpuid10_ebx ebx; 5042 5043 ebx.full = x86_pmu.events_maskl; 5044 if (ebx.split.no_branch_misses_retired) { 5045 /* 5046 * Erratum AAJ80 detected, we work it around by using 5047 * the BR_MISP_EXEC.ANY event. This will over-count 5048 * branch-misses, but it's still much better than the 5049 * architectural event which is often completely bogus: 5050 */ 5051 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5052 ebx.split.no_branch_misses_retired = 0; 5053 x86_pmu.events_maskl = ebx.full; 5054 pr_info("CPU erratum AAJ80 worked around\n"); 5055 } 5056 } 5057 5058 /* 5059 * enable software workaround for errata: 5060 * SNB: BJ122 5061 * IVB: BV98 5062 * HSW: HSD29 5063 * 5064 * Only needed when HT is enabled. However detecting 5065 * if HT is enabled is difficult (model specific). So instead, 5066 * we enable the workaround in the early boot, and verify if 5067 * it is needed in a later initcall phase once we have valid 5068 * topology information to check if HT is actually enabled 5069 */ 5070 static __init void intel_ht_bug(void) 5071 { 5072 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5073 5074 x86_pmu.start_scheduling = intel_start_scheduling; 5075 x86_pmu.commit_scheduling = intel_commit_scheduling; 5076 x86_pmu.stop_scheduling = intel_stop_scheduling; 5077 } 5078 5079 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5080 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5081 5082 /* Haswell special events */ 5083 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5084 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5085 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5086 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5087 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5088 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5089 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5090 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5091 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5092 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5093 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5094 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5095 5096 static struct attribute *hsw_events_attrs[] = { 5097 EVENT_PTR(td_slots_issued), 5098 EVENT_PTR(td_slots_retired), 5099 EVENT_PTR(td_fetch_bubbles), 5100 EVENT_PTR(td_total_slots), 5101 EVENT_PTR(td_total_slots_scale), 5102 EVENT_PTR(td_recovery_bubbles), 5103 EVENT_PTR(td_recovery_bubbles_scale), 5104 NULL 5105 }; 5106 5107 static struct attribute *hsw_mem_events_attrs[] = { 5108 EVENT_PTR(mem_ld_hsw), 5109 EVENT_PTR(mem_st_hsw), 5110 NULL, 5111 }; 5112 5113 static struct attribute *hsw_tsx_events_attrs[] = { 5114 EVENT_PTR(tx_start), 5115 EVENT_PTR(tx_commit), 5116 EVENT_PTR(tx_abort), 5117 EVENT_PTR(tx_capacity), 5118 EVENT_PTR(tx_conflict), 5119 EVENT_PTR(el_start), 5120 EVENT_PTR(el_commit), 5121 EVENT_PTR(el_abort), 5122 EVENT_PTR(el_capacity), 5123 EVENT_PTR(el_conflict), 5124 EVENT_PTR(cycles_t), 5125 EVENT_PTR(cycles_ct), 5126 NULL 5127 }; 5128 5129 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 5130 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 5131 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 5132 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 5133 5134 static struct attribute *icl_events_attrs[] = { 5135 EVENT_PTR(mem_ld_hsw), 5136 EVENT_PTR(mem_st_hsw), 5137 NULL, 5138 }; 5139 5140 static struct attribute *icl_td_events_attrs[] = { 5141 EVENT_PTR(slots), 5142 EVENT_PTR(td_retiring), 5143 EVENT_PTR(td_bad_spec), 5144 EVENT_PTR(td_fe_bound), 5145 EVENT_PTR(td_be_bound), 5146 NULL, 5147 }; 5148 5149 static struct attribute *icl_tsx_events_attrs[] = { 5150 EVENT_PTR(tx_start), 5151 EVENT_PTR(tx_abort), 5152 EVENT_PTR(tx_commit), 5153 EVENT_PTR(tx_capacity_read), 5154 EVENT_PTR(tx_capacity_write), 5155 EVENT_PTR(tx_conflict), 5156 EVENT_PTR(el_start), 5157 EVENT_PTR(el_abort), 5158 EVENT_PTR(el_commit), 5159 EVENT_PTR(el_capacity_read), 5160 EVENT_PTR(el_capacity_write), 5161 EVENT_PTR(el_conflict), 5162 EVENT_PTR(cycles_t), 5163 EVENT_PTR(cycles_ct), 5164 NULL, 5165 }; 5166 5167 5168 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5169 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5170 5171 static struct attribute *spr_events_attrs[] = { 5172 EVENT_PTR(mem_ld_hsw), 5173 EVENT_PTR(mem_st_spr), 5174 EVENT_PTR(mem_ld_aux), 5175 NULL, 5176 }; 5177 5178 static struct attribute *spr_td_events_attrs[] = { 5179 EVENT_PTR(slots), 5180 EVENT_PTR(td_retiring), 5181 EVENT_PTR(td_bad_spec), 5182 EVENT_PTR(td_fe_bound), 5183 EVENT_PTR(td_be_bound), 5184 EVENT_PTR(td_heavy_ops), 5185 EVENT_PTR(td_br_mispredict), 5186 EVENT_PTR(td_fetch_lat), 5187 EVENT_PTR(td_mem_bound), 5188 NULL, 5189 }; 5190 5191 static struct attribute *spr_tsx_events_attrs[] = { 5192 EVENT_PTR(tx_start), 5193 EVENT_PTR(tx_abort), 5194 EVENT_PTR(tx_commit), 5195 EVENT_PTR(tx_capacity_read), 5196 EVENT_PTR(tx_capacity_write), 5197 EVENT_PTR(tx_conflict), 5198 EVENT_PTR(cycles_t), 5199 EVENT_PTR(cycles_ct), 5200 NULL, 5201 }; 5202 5203 static ssize_t freeze_on_smi_show(struct device *cdev, 5204 struct device_attribute *attr, 5205 char *buf) 5206 { 5207 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5208 } 5209 5210 static DEFINE_MUTEX(freeze_on_smi_mutex); 5211 5212 static ssize_t freeze_on_smi_store(struct device *cdev, 5213 struct device_attribute *attr, 5214 const char *buf, size_t count) 5215 { 5216 unsigned long val; 5217 ssize_t ret; 5218 5219 ret = kstrtoul(buf, 0, &val); 5220 if (ret) 5221 return ret; 5222 5223 if (val > 1) 5224 return -EINVAL; 5225 5226 mutex_lock(&freeze_on_smi_mutex); 5227 5228 if (x86_pmu.attr_freeze_on_smi == val) 5229 goto done; 5230 5231 x86_pmu.attr_freeze_on_smi = val; 5232 5233 cpus_read_lock(); 5234 on_each_cpu(flip_smm_bit, &val, 1); 5235 cpus_read_unlock(); 5236 done: 5237 mutex_unlock(&freeze_on_smi_mutex); 5238 5239 return count; 5240 } 5241 5242 static void update_tfa_sched(void *ignored) 5243 { 5244 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5245 5246 /* 5247 * check if PMC3 is used 5248 * and if so force schedule out for all event types all contexts 5249 */ 5250 if (test_bit(3, cpuc->active_mask)) 5251 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5252 } 5253 5254 static ssize_t show_sysctl_tfa(struct device *cdev, 5255 struct device_attribute *attr, 5256 char *buf) 5257 { 5258 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5259 } 5260 5261 static ssize_t set_sysctl_tfa(struct device *cdev, 5262 struct device_attribute *attr, 5263 const char *buf, size_t count) 5264 { 5265 bool val; 5266 ssize_t ret; 5267 5268 ret = kstrtobool(buf, &val); 5269 if (ret) 5270 return ret; 5271 5272 /* no change */ 5273 if (val == allow_tsx_force_abort) 5274 return count; 5275 5276 allow_tsx_force_abort = val; 5277 5278 cpus_read_lock(); 5279 on_each_cpu(update_tfa_sched, NULL, 1); 5280 cpus_read_unlock(); 5281 5282 return count; 5283 } 5284 5285 5286 static DEVICE_ATTR_RW(freeze_on_smi); 5287 5288 static ssize_t branches_show(struct device *cdev, 5289 struct device_attribute *attr, 5290 char *buf) 5291 { 5292 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5293 } 5294 5295 static DEVICE_ATTR_RO(branches); 5296 5297 static struct attribute *lbr_attrs[] = { 5298 &dev_attr_branches.attr, 5299 NULL 5300 }; 5301 5302 static char pmu_name_str[30]; 5303 5304 static ssize_t pmu_name_show(struct device *cdev, 5305 struct device_attribute *attr, 5306 char *buf) 5307 { 5308 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5309 } 5310 5311 static DEVICE_ATTR_RO(pmu_name); 5312 5313 static struct attribute *intel_pmu_caps_attrs[] = { 5314 &dev_attr_pmu_name.attr, 5315 NULL 5316 }; 5317 5318 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5319 show_sysctl_tfa, 5320 set_sysctl_tfa); 5321 5322 static struct attribute *intel_pmu_attrs[] = { 5323 &dev_attr_freeze_on_smi.attr, 5324 &dev_attr_allow_tsx_force_abort.attr, 5325 NULL, 5326 }; 5327 5328 static umode_t 5329 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5330 { 5331 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5332 } 5333 5334 static umode_t 5335 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5336 { 5337 return x86_pmu.pebs ? attr->mode : 0; 5338 } 5339 5340 static umode_t 5341 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5342 { 5343 return x86_pmu.lbr_nr ? attr->mode : 0; 5344 } 5345 5346 static umode_t 5347 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5348 { 5349 return x86_pmu.version >= 2 ? attr->mode : 0; 5350 } 5351 5352 static umode_t 5353 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5354 { 5355 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5356 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5357 5358 return attr->mode; 5359 } 5360 5361 static struct attribute_group group_events_td = { 5362 .name = "events", 5363 }; 5364 5365 static struct attribute_group group_events_mem = { 5366 .name = "events", 5367 .is_visible = pebs_is_visible, 5368 }; 5369 5370 static struct attribute_group group_events_tsx = { 5371 .name = "events", 5372 .is_visible = tsx_is_visible, 5373 }; 5374 5375 static struct attribute_group group_caps_gen = { 5376 .name = "caps", 5377 .attrs = intel_pmu_caps_attrs, 5378 }; 5379 5380 static struct attribute_group group_caps_lbr = { 5381 .name = "caps", 5382 .attrs = lbr_attrs, 5383 .is_visible = lbr_is_visible, 5384 }; 5385 5386 static struct attribute_group group_format_extra = { 5387 .name = "format", 5388 .is_visible = exra_is_visible, 5389 }; 5390 5391 static struct attribute_group group_format_extra_skl = { 5392 .name = "format", 5393 .is_visible = exra_is_visible, 5394 }; 5395 5396 static struct attribute_group group_default = { 5397 .attrs = intel_pmu_attrs, 5398 .is_visible = default_is_visible, 5399 }; 5400 5401 static const struct attribute_group *attr_update[] = { 5402 &group_events_td, 5403 &group_events_mem, 5404 &group_events_tsx, 5405 &group_caps_gen, 5406 &group_caps_lbr, 5407 &group_format_extra, 5408 &group_format_extra_skl, 5409 &group_default, 5410 NULL, 5411 }; 5412 5413 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5414 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5415 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5416 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5417 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5418 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5419 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5420 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5421 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5422 5423 static struct attribute *adl_hybrid_events_attrs[] = { 5424 EVENT_PTR(slots_adl), 5425 EVENT_PTR(td_retiring_adl), 5426 EVENT_PTR(td_bad_spec_adl), 5427 EVENT_PTR(td_fe_bound_adl), 5428 EVENT_PTR(td_be_bound_adl), 5429 EVENT_PTR(td_heavy_ops_adl), 5430 EVENT_PTR(td_br_mis_adl), 5431 EVENT_PTR(td_fetch_lat_adl), 5432 EVENT_PTR(td_mem_bound_adl), 5433 NULL, 5434 }; 5435 5436 /* Must be in IDX order */ 5437 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5438 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5439 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5440 5441 static struct attribute *adl_hybrid_mem_attrs[] = { 5442 EVENT_PTR(mem_ld_adl), 5443 EVENT_PTR(mem_st_adl), 5444 EVENT_PTR(mem_ld_aux_adl), 5445 NULL, 5446 }; 5447 5448 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5449 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5450 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5451 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5452 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5453 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5454 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5455 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5456 5457 static struct attribute *adl_hybrid_tsx_attrs[] = { 5458 EVENT_PTR(tx_start_adl), 5459 EVENT_PTR(tx_abort_adl), 5460 EVENT_PTR(tx_commit_adl), 5461 EVENT_PTR(tx_capacity_read_adl), 5462 EVENT_PTR(tx_capacity_write_adl), 5463 EVENT_PTR(tx_conflict_adl), 5464 EVENT_PTR(cycles_t_adl), 5465 EVENT_PTR(cycles_ct_adl), 5466 NULL, 5467 }; 5468 5469 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5470 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5471 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5472 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5473 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5474 5475 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5476 FORMAT_HYBRID_PTR(in_tx), 5477 FORMAT_HYBRID_PTR(in_tx_cp), 5478 FORMAT_HYBRID_PTR(offcore_rsp), 5479 FORMAT_HYBRID_PTR(ldlat), 5480 FORMAT_HYBRID_PTR(frontend), 5481 NULL, 5482 }; 5483 5484 static struct attribute *adl_hybrid_extra_attr[] = { 5485 FORMAT_HYBRID_PTR(offcore_rsp), 5486 FORMAT_HYBRID_PTR(ldlat), 5487 FORMAT_HYBRID_PTR(frontend), 5488 NULL, 5489 }; 5490 5491 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5492 { 5493 struct device *dev = kobj_to_dev(kobj); 5494 struct x86_hybrid_pmu *pmu = 5495 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5496 struct perf_pmu_events_hybrid_attr *pmu_attr = 5497 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5498 5499 return pmu->cpu_type & pmu_attr->pmu_type; 5500 } 5501 5502 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5503 struct attribute *attr, int i) 5504 { 5505 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5506 } 5507 5508 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5509 { 5510 int cpu = cpumask_first(&pmu->supported_cpus); 5511 5512 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5513 } 5514 5515 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5516 struct attribute *attr, int i) 5517 { 5518 struct device *dev = kobj_to_dev(kobj); 5519 struct x86_hybrid_pmu *pmu = 5520 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5521 int cpu = hybrid_find_supported_cpu(pmu); 5522 5523 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5524 } 5525 5526 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5527 struct attribute *attr, int i) 5528 { 5529 struct device *dev = kobj_to_dev(kobj); 5530 struct x86_hybrid_pmu *pmu = 5531 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5532 struct perf_pmu_format_hybrid_attr *pmu_attr = 5533 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5534 int cpu = hybrid_find_supported_cpu(pmu); 5535 5536 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5537 } 5538 5539 static struct attribute_group hybrid_group_events_td = { 5540 .name = "events", 5541 .is_visible = hybrid_events_is_visible, 5542 }; 5543 5544 static struct attribute_group hybrid_group_events_mem = { 5545 .name = "events", 5546 .is_visible = hybrid_events_is_visible, 5547 }; 5548 5549 static struct attribute_group hybrid_group_events_tsx = { 5550 .name = "events", 5551 .is_visible = hybrid_tsx_is_visible, 5552 }; 5553 5554 static struct attribute_group hybrid_group_format_extra = { 5555 .name = "format", 5556 .is_visible = hybrid_format_is_visible, 5557 }; 5558 5559 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5560 struct device_attribute *attr, 5561 char *buf) 5562 { 5563 struct x86_hybrid_pmu *pmu = 5564 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5565 5566 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5567 } 5568 5569 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5570 static struct attribute *intel_hybrid_cpus_attrs[] = { 5571 &dev_attr_cpus.attr, 5572 NULL, 5573 }; 5574 5575 static struct attribute_group hybrid_group_cpus = { 5576 .attrs = intel_hybrid_cpus_attrs, 5577 }; 5578 5579 static const struct attribute_group *hybrid_attr_update[] = { 5580 &hybrid_group_events_td, 5581 &hybrid_group_events_mem, 5582 &hybrid_group_events_tsx, 5583 &group_caps_gen, 5584 &group_caps_lbr, 5585 &hybrid_group_format_extra, 5586 &group_default, 5587 &hybrid_group_cpus, 5588 NULL, 5589 }; 5590 5591 static struct attribute *empty_attrs; 5592 5593 static void intel_pmu_check_num_counters(int *num_counters, 5594 int *num_counters_fixed, 5595 u64 *intel_ctrl, u64 fixed_mask) 5596 { 5597 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5598 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5599 *num_counters, INTEL_PMC_MAX_GENERIC); 5600 *num_counters = INTEL_PMC_MAX_GENERIC; 5601 } 5602 *intel_ctrl = (1ULL << *num_counters) - 1; 5603 5604 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5605 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5606 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5607 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5608 } 5609 5610 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5611 } 5612 5613 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5614 int num_counters, 5615 int num_counters_fixed, 5616 u64 intel_ctrl) 5617 { 5618 struct event_constraint *c; 5619 5620 if (!event_constraints) 5621 return; 5622 5623 /* 5624 * event on fixed counter2 (REF_CYCLES) only works on this 5625 * counter, so do not extend mask to generic counters 5626 */ 5627 for_each_event_constraint(c, event_constraints) { 5628 /* 5629 * Don't extend the topdown slots and metrics 5630 * events to the generic counters. 5631 */ 5632 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5633 /* 5634 * Disable topdown slots and metrics events, 5635 * if slots event is not in CPUID. 5636 */ 5637 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5638 c->idxmsk64 = 0; 5639 c->weight = hweight64(c->idxmsk64); 5640 continue; 5641 } 5642 5643 if (c->cmask == FIXED_EVENT_FLAGS) { 5644 /* Disabled fixed counters which are not in CPUID */ 5645 c->idxmsk64 &= intel_ctrl; 5646 5647 /* 5648 * Don't extend the pseudo-encoding to the 5649 * generic counters 5650 */ 5651 if (!use_fixed_pseudo_encoding(c->code)) 5652 c->idxmsk64 |= (1ULL << num_counters) - 1; 5653 } 5654 c->idxmsk64 &= 5655 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5656 c->weight = hweight64(c->idxmsk64); 5657 } 5658 } 5659 5660 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5661 { 5662 struct extra_reg *er; 5663 5664 /* 5665 * Access extra MSR may cause #GP under certain circumstances. 5666 * E.g. KVM doesn't support offcore event 5667 * Check all extra_regs here. 5668 */ 5669 if (!extra_regs) 5670 return; 5671 5672 for (er = extra_regs; er->msr; er++) { 5673 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5674 /* Disable LBR select mapping */ 5675 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5676 x86_pmu.lbr_sel_map = NULL; 5677 } 5678 } 5679 5680 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5681 { 5682 struct x86_hybrid_pmu *pmu; 5683 int i; 5684 5685 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5686 pmu = &x86_pmu.hybrid_pmu[i]; 5687 5688 intel_pmu_check_num_counters(&pmu->num_counters, 5689 &pmu->num_counters_fixed, 5690 &pmu->intel_ctrl, 5691 fixed_mask); 5692 5693 if (pmu->intel_cap.perf_metrics) { 5694 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5695 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5696 } 5697 5698 if (pmu->intel_cap.pebs_output_pt_available) 5699 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5700 5701 intel_pmu_check_event_constraints(pmu->event_constraints, 5702 pmu->num_counters, 5703 pmu->num_counters_fixed, 5704 pmu->intel_ctrl); 5705 5706 intel_pmu_check_extra_regs(pmu->extra_regs); 5707 } 5708 } 5709 5710 __init int intel_pmu_init(void) 5711 { 5712 struct attribute **extra_skl_attr = &empty_attrs; 5713 struct attribute **extra_attr = &empty_attrs; 5714 struct attribute **td_attr = &empty_attrs; 5715 struct attribute **mem_attr = &empty_attrs; 5716 struct attribute **tsx_attr = &empty_attrs; 5717 union cpuid10_edx edx; 5718 union cpuid10_eax eax; 5719 union cpuid10_ebx ebx; 5720 unsigned int fixed_mask; 5721 bool pmem = false; 5722 int version, i; 5723 char *name; 5724 struct x86_hybrid_pmu *pmu; 5725 5726 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5727 switch (boot_cpu_data.x86) { 5728 case 0x6: 5729 return p6_pmu_init(); 5730 case 0xb: 5731 return knc_pmu_init(); 5732 case 0xf: 5733 return p4_pmu_init(); 5734 } 5735 return -ENODEV; 5736 } 5737 5738 /* 5739 * Check whether the Architectural PerfMon supports 5740 * Branch Misses Retired hw_event or not. 5741 */ 5742 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5743 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5744 return -ENODEV; 5745 5746 version = eax.split.version_id; 5747 if (version < 2) 5748 x86_pmu = core_pmu; 5749 else 5750 x86_pmu = intel_pmu; 5751 5752 x86_pmu.version = version; 5753 x86_pmu.num_counters = eax.split.num_counters; 5754 x86_pmu.cntval_bits = eax.split.bit_width; 5755 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5756 5757 x86_pmu.events_maskl = ebx.full; 5758 x86_pmu.events_mask_len = eax.split.mask_length; 5759 5760 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5761 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 5762 5763 /* 5764 * Quirk: v2 perfmon does not report fixed-purpose events, so 5765 * assume at least 3 events, when not running in a hypervisor: 5766 */ 5767 if (version > 1 && version < 5) { 5768 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5769 5770 x86_pmu.num_counters_fixed = 5771 max((int)edx.split.num_counters_fixed, assume); 5772 5773 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5774 } else if (version >= 5) 5775 x86_pmu.num_counters_fixed = fls(fixed_mask); 5776 5777 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5778 u64 capabilities; 5779 5780 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5781 x86_pmu.intel_cap.capabilities = capabilities; 5782 } 5783 5784 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5785 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5786 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5787 } 5788 5789 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5790 intel_pmu_arch_lbr_init(); 5791 5792 intel_ds_init(); 5793 5794 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5795 5796 if (version >= 5) { 5797 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5798 if (x86_pmu.intel_cap.anythread_deprecated) 5799 pr_cont(" AnyThread deprecated, "); 5800 } 5801 5802 /* 5803 * Install the hw-cache-events table: 5804 */ 5805 switch (boot_cpu_data.x86_model) { 5806 case INTEL_FAM6_CORE_YONAH: 5807 pr_cont("Core events, "); 5808 name = "core"; 5809 break; 5810 5811 case INTEL_FAM6_CORE2_MEROM: 5812 x86_add_quirk(intel_clovertown_quirk); 5813 fallthrough; 5814 5815 case INTEL_FAM6_CORE2_MEROM_L: 5816 case INTEL_FAM6_CORE2_PENRYN: 5817 case INTEL_FAM6_CORE2_DUNNINGTON: 5818 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5819 sizeof(hw_cache_event_ids)); 5820 5821 intel_pmu_lbr_init_core(); 5822 5823 x86_pmu.event_constraints = intel_core2_event_constraints; 5824 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5825 pr_cont("Core2 events, "); 5826 name = "core2"; 5827 break; 5828 5829 case INTEL_FAM6_NEHALEM: 5830 case INTEL_FAM6_NEHALEM_EP: 5831 case INTEL_FAM6_NEHALEM_EX: 5832 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5833 sizeof(hw_cache_event_ids)); 5834 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5835 sizeof(hw_cache_extra_regs)); 5836 5837 intel_pmu_lbr_init_nhm(); 5838 5839 x86_pmu.event_constraints = intel_nehalem_event_constraints; 5840 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5841 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5842 x86_pmu.extra_regs = intel_nehalem_extra_regs; 5843 x86_pmu.limit_period = nhm_limit_period; 5844 5845 mem_attr = nhm_mem_events_attrs; 5846 5847 /* UOPS_ISSUED.STALLED_CYCLES */ 5848 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5849 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5850 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5851 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5852 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5853 5854 intel_pmu_pebs_data_source_nhm(); 5855 x86_add_quirk(intel_nehalem_quirk); 5856 x86_pmu.pebs_no_tlb = 1; 5857 extra_attr = nhm_format_attr; 5858 5859 pr_cont("Nehalem events, "); 5860 name = "nehalem"; 5861 break; 5862 5863 case INTEL_FAM6_ATOM_BONNELL: 5864 case INTEL_FAM6_ATOM_BONNELL_MID: 5865 case INTEL_FAM6_ATOM_SALTWELL: 5866 case INTEL_FAM6_ATOM_SALTWELL_MID: 5867 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5868 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5869 sizeof(hw_cache_event_ids)); 5870 5871 intel_pmu_lbr_init_atom(); 5872 5873 x86_pmu.event_constraints = intel_gen_event_constraints; 5874 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5875 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5876 pr_cont("Atom events, "); 5877 name = "bonnell"; 5878 break; 5879 5880 case INTEL_FAM6_ATOM_SILVERMONT: 5881 case INTEL_FAM6_ATOM_SILVERMONT_D: 5882 case INTEL_FAM6_ATOM_SILVERMONT_MID: 5883 case INTEL_FAM6_ATOM_AIRMONT: 5884 case INTEL_FAM6_ATOM_AIRMONT_MID: 5885 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5886 sizeof(hw_cache_event_ids)); 5887 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5888 sizeof(hw_cache_extra_regs)); 5889 5890 intel_pmu_lbr_init_slm(); 5891 5892 x86_pmu.event_constraints = intel_slm_event_constraints; 5893 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5894 x86_pmu.extra_regs = intel_slm_extra_regs; 5895 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5896 td_attr = slm_events_attrs; 5897 extra_attr = slm_format_attr; 5898 pr_cont("Silvermont events, "); 5899 name = "silvermont"; 5900 break; 5901 5902 case INTEL_FAM6_ATOM_GOLDMONT: 5903 case INTEL_FAM6_ATOM_GOLDMONT_D: 5904 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 5905 sizeof(hw_cache_event_ids)); 5906 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 5907 sizeof(hw_cache_extra_regs)); 5908 5909 intel_pmu_lbr_init_skl(); 5910 5911 x86_pmu.event_constraints = intel_slm_event_constraints; 5912 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 5913 x86_pmu.extra_regs = intel_glm_extra_regs; 5914 /* 5915 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5916 * for precise cycles. 5917 * :pp is identical to :ppp 5918 */ 5919 x86_pmu.pebs_aliases = NULL; 5920 x86_pmu.pebs_prec_dist = true; 5921 x86_pmu.lbr_pt_coexist = true; 5922 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5923 td_attr = glm_events_attrs; 5924 extra_attr = slm_format_attr; 5925 pr_cont("Goldmont events, "); 5926 name = "goldmont"; 5927 break; 5928 5929 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5930 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5931 sizeof(hw_cache_event_ids)); 5932 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5933 sizeof(hw_cache_extra_regs)); 5934 5935 intel_pmu_lbr_init_skl(); 5936 5937 x86_pmu.event_constraints = intel_slm_event_constraints; 5938 x86_pmu.extra_regs = intel_glm_extra_regs; 5939 /* 5940 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5941 * for precise cycles. 5942 */ 5943 x86_pmu.pebs_aliases = NULL; 5944 x86_pmu.pebs_prec_dist = true; 5945 x86_pmu.lbr_pt_coexist = true; 5946 x86_pmu.pebs_capable = ~0ULL; 5947 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5948 x86_pmu.flags |= PMU_FL_PEBS_ALL; 5949 x86_pmu.get_event_constraints = glp_get_event_constraints; 5950 td_attr = glm_events_attrs; 5951 /* Goldmont Plus has 4-wide pipeline */ 5952 event_attr_td_total_slots_scale_glm.event_str = "4"; 5953 extra_attr = slm_format_attr; 5954 pr_cont("Goldmont plus events, "); 5955 name = "goldmont_plus"; 5956 break; 5957 5958 case INTEL_FAM6_ATOM_TREMONT_D: 5959 case INTEL_FAM6_ATOM_TREMONT: 5960 case INTEL_FAM6_ATOM_TREMONT_L: 5961 x86_pmu.late_ack = true; 5962 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5963 sizeof(hw_cache_event_ids)); 5964 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5965 sizeof(hw_cache_extra_regs)); 5966 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5967 5968 intel_pmu_lbr_init_skl(); 5969 5970 x86_pmu.event_constraints = intel_slm_event_constraints; 5971 x86_pmu.extra_regs = intel_tnt_extra_regs; 5972 /* 5973 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5974 * for precise cycles. 5975 */ 5976 x86_pmu.pebs_aliases = NULL; 5977 x86_pmu.pebs_prec_dist = true; 5978 x86_pmu.lbr_pt_coexist = true; 5979 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5980 x86_pmu.get_event_constraints = tnt_get_event_constraints; 5981 td_attr = tnt_events_attrs; 5982 extra_attr = slm_format_attr; 5983 pr_cont("Tremont events, "); 5984 name = "Tremont"; 5985 break; 5986 5987 case INTEL_FAM6_ALDERLAKE_N: 5988 x86_pmu.mid_ack = true; 5989 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5990 sizeof(hw_cache_event_ids)); 5991 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5992 sizeof(hw_cache_extra_regs)); 5993 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5994 5995 x86_pmu.event_constraints = intel_slm_event_constraints; 5996 x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints; 5997 x86_pmu.extra_regs = intel_grt_extra_regs; 5998 5999 x86_pmu.pebs_aliases = NULL; 6000 x86_pmu.pebs_prec_dist = true; 6001 x86_pmu.pebs_block = true; 6002 x86_pmu.lbr_pt_coexist = true; 6003 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6004 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6005 6006 intel_pmu_pebs_data_source_grt(); 6007 x86_pmu.pebs_latency_data = adl_latency_data_small; 6008 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6009 x86_pmu.limit_period = spr_limit_period; 6010 td_attr = tnt_events_attrs; 6011 mem_attr = grt_mem_attrs; 6012 extra_attr = nhm_format_attr; 6013 pr_cont("Gracemont events, "); 6014 name = "gracemont"; 6015 break; 6016 6017 case INTEL_FAM6_WESTMERE: 6018 case INTEL_FAM6_WESTMERE_EP: 6019 case INTEL_FAM6_WESTMERE_EX: 6020 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 6021 sizeof(hw_cache_event_ids)); 6022 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6023 sizeof(hw_cache_extra_regs)); 6024 6025 intel_pmu_lbr_init_nhm(); 6026 6027 x86_pmu.event_constraints = intel_westmere_event_constraints; 6028 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6029 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 6030 x86_pmu.extra_regs = intel_westmere_extra_regs; 6031 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6032 6033 mem_attr = nhm_mem_events_attrs; 6034 6035 /* UOPS_ISSUED.STALLED_CYCLES */ 6036 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6037 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6038 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6039 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6040 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6041 6042 intel_pmu_pebs_data_source_nhm(); 6043 extra_attr = nhm_format_attr; 6044 pr_cont("Westmere events, "); 6045 name = "westmere"; 6046 break; 6047 6048 case INTEL_FAM6_SANDYBRIDGE: 6049 case INTEL_FAM6_SANDYBRIDGE_X: 6050 x86_add_quirk(intel_sandybridge_quirk); 6051 x86_add_quirk(intel_ht_bug); 6052 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6053 sizeof(hw_cache_event_ids)); 6054 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6055 sizeof(hw_cache_extra_regs)); 6056 6057 intel_pmu_lbr_init_snb(); 6058 6059 x86_pmu.event_constraints = intel_snb_event_constraints; 6060 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 6061 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 6062 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 6063 x86_pmu.extra_regs = intel_snbep_extra_regs; 6064 else 6065 x86_pmu.extra_regs = intel_snb_extra_regs; 6066 6067 6068 /* all extra regs are per-cpu when HT is on */ 6069 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6070 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6071 6072 td_attr = snb_events_attrs; 6073 mem_attr = snb_mem_events_attrs; 6074 6075 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6076 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6077 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6078 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 6079 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6080 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 6081 6082 extra_attr = nhm_format_attr; 6083 6084 pr_cont("SandyBridge events, "); 6085 name = "sandybridge"; 6086 break; 6087 6088 case INTEL_FAM6_IVYBRIDGE: 6089 case INTEL_FAM6_IVYBRIDGE_X: 6090 x86_add_quirk(intel_ht_bug); 6091 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6092 sizeof(hw_cache_event_ids)); 6093 /* dTLB-load-misses on IVB is different than SNB */ 6094 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 6095 6096 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6097 sizeof(hw_cache_extra_regs)); 6098 6099 intel_pmu_lbr_init_snb(); 6100 6101 x86_pmu.event_constraints = intel_ivb_event_constraints; 6102 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 6103 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6104 x86_pmu.pebs_prec_dist = true; 6105 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 6106 x86_pmu.extra_regs = intel_snbep_extra_regs; 6107 else 6108 x86_pmu.extra_regs = intel_snb_extra_regs; 6109 /* all extra regs are per-cpu when HT is on */ 6110 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6111 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6112 6113 td_attr = snb_events_attrs; 6114 mem_attr = snb_mem_events_attrs; 6115 6116 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6117 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6118 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6119 6120 extra_attr = nhm_format_attr; 6121 6122 pr_cont("IvyBridge events, "); 6123 name = "ivybridge"; 6124 break; 6125 6126 6127 case INTEL_FAM6_HASWELL: 6128 case INTEL_FAM6_HASWELL_X: 6129 case INTEL_FAM6_HASWELL_L: 6130 case INTEL_FAM6_HASWELL_G: 6131 x86_add_quirk(intel_ht_bug); 6132 x86_add_quirk(intel_pebs_isolation_quirk); 6133 x86_pmu.late_ack = true; 6134 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6135 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6136 6137 intel_pmu_lbr_init_hsw(); 6138 6139 x86_pmu.event_constraints = intel_hsw_event_constraints; 6140 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 6141 x86_pmu.extra_regs = intel_snbep_extra_regs; 6142 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6143 x86_pmu.pebs_prec_dist = true; 6144 /* all extra regs are per-cpu when HT is on */ 6145 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6146 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6147 6148 x86_pmu.hw_config = hsw_hw_config; 6149 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6150 x86_pmu.lbr_double_abort = true; 6151 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6152 hsw_format_attr : nhm_format_attr; 6153 td_attr = hsw_events_attrs; 6154 mem_attr = hsw_mem_events_attrs; 6155 tsx_attr = hsw_tsx_events_attrs; 6156 pr_cont("Haswell events, "); 6157 name = "haswell"; 6158 break; 6159 6160 case INTEL_FAM6_BROADWELL: 6161 case INTEL_FAM6_BROADWELL_D: 6162 case INTEL_FAM6_BROADWELL_G: 6163 case INTEL_FAM6_BROADWELL_X: 6164 x86_add_quirk(intel_pebs_isolation_quirk); 6165 x86_pmu.late_ack = true; 6166 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6167 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6168 6169 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 6170 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 6171 BDW_L3_MISS|HSW_SNOOP_DRAM; 6172 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6173 HSW_SNOOP_DRAM; 6174 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6175 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6176 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6177 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6178 6179 intel_pmu_lbr_init_hsw(); 6180 6181 x86_pmu.event_constraints = intel_bdw_event_constraints; 6182 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6183 x86_pmu.extra_regs = intel_snbep_extra_regs; 6184 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6185 x86_pmu.pebs_prec_dist = true; 6186 /* all extra regs are per-cpu when HT is on */ 6187 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6188 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6189 6190 x86_pmu.hw_config = hsw_hw_config; 6191 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6192 x86_pmu.limit_period = bdw_limit_period; 6193 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6194 hsw_format_attr : nhm_format_attr; 6195 td_attr = hsw_events_attrs; 6196 mem_attr = hsw_mem_events_attrs; 6197 tsx_attr = hsw_tsx_events_attrs; 6198 pr_cont("Broadwell events, "); 6199 name = "broadwell"; 6200 break; 6201 6202 case INTEL_FAM6_XEON_PHI_KNL: 6203 case INTEL_FAM6_XEON_PHI_KNM: 6204 memcpy(hw_cache_event_ids, 6205 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6206 memcpy(hw_cache_extra_regs, 6207 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6208 intel_pmu_lbr_init_knl(); 6209 6210 x86_pmu.event_constraints = intel_slm_event_constraints; 6211 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6212 x86_pmu.extra_regs = intel_knl_extra_regs; 6213 6214 /* all extra regs are per-cpu when HT is on */ 6215 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6216 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6217 extra_attr = slm_format_attr; 6218 pr_cont("Knights Landing/Mill events, "); 6219 name = "knights-landing"; 6220 break; 6221 6222 case INTEL_FAM6_SKYLAKE_X: 6223 pmem = true; 6224 fallthrough; 6225 case INTEL_FAM6_SKYLAKE_L: 6226 case INTEL_FAM6_SKYLAKE: 6227 case INTEL_FAM6_KABYLAKE_L: 6228 case INTEL_FAM6_KABYLAKE: 6229 case INTEL_FAM6_COMETLAKE_L: 6230 case INTEL_FAM6_COMETLAKE: 6231 x86_add_quirk(intel_pebs_isolation_quirk); 6232 x86_pmu.late_ack = true; 6233 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6234 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6235 intel_pmu_lbr_init_skl(); 6236 6237 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6238 event_attr_td_recovery_bubbles.event_str_noht = 6239 "event=0xd,umask=0x1,cmask=1"; 6240 event_attr_td_recovery_bubbles.event_str_ht = 6241 "event=0xd,umask=0x1,cmask=1,any=1"; 6242 6243 x86_pmu.event_constraints = intel_skl_event_constraints; 6244 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6245 x86_pmu.extra_regs = intel_skl_extra_regs; 6246 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6247 x86_pmu.pebs_prec_dist = true; 6248 /* all extra regs are per-cpu when HT is on */ 6249 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6250 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6251 6252 x86_pmu.hw_config = hsw_hw_config; 6253 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6254 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6255 hsw_format_attr : nhm_format_attr; 6256 extra_skl_attr = skl_format_attr; 6257 td_attr = hsw_events_attrs; 6258 mem_attr = hsw_mem_events_attrs; 6259 tsx_attr = hsw_tsx_events_attrs; 6260 intel_pmu_pebs_data_source_skl(pmem); 6261 6262 /* 6263 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6264 * TSX force abort hooks are not required on these systems. Only deploy 6265 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6266 */ 6267 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6268 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6269 x86_pmu.flags |= PMU_FL_TFA; 6270 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6271 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6272 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6273 } 6274 6275 pr_cont("Skylake events, "); 6276 name = "skylake"; 6277 break; 6278 6279 case INTEL_FAM6_ICELAKE_X: 6280 case INTEL_FAM6_ICELAKE_D: 6281 x86_pmu.pebs_ept = 1; 6282 pmem = true; 6283 fallthrough; 6284 case INTEL_FAM6_ICELAKE_L: 6285 case INTEL_FAM6_ICELAKE: 6286 case INTEL_FAM6_TIGERLAKE_L: 6287 case INTEL_FAM6_TIGERLAKE: 6288 case INTEL_FAM6_ROCKETLAKE: 6289 x86_pmu.late_ack = true; 6290 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6291 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6292 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6293 intel_pmu_lbr_init_skl(); 6294 6295 x86_pmu.event_constraints = intel_icl_event_constraints; 6296 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6297 x86_pmu.extra_regs = intel_icl_extra_regs; 6298 x86_pmu.pebs_aliases = NULL; 6299 x86_pmu.pebs_prec_dist = true; 6300 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6301 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6302 6303 x86_pmu.hw_config = hsw_hw_config; 6304 x86_pmu.get_event_constraints = icl_get_event_constraints; 6305 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6306 hsw_format_attr : nhm_format_attr; 6307 extra_skl_attr = skl_format_attr; 6308 mem_attr = icl_events_attrs; 6309 td_attr = icl_td_events_attrs; 6310 tsx_attr = icl_tsx_events_attrs; 6311 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6312 x86_pmu.lbr_pt_coexist = true; 6313 intel_pmu_pebs_data_source_skl(pmem); 6314 x86_pmu.num_topdown_events = 4; 6315 x86_pmu.update_topdown_event = icl_update_topdown_event; 6316 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6317 pr_cont("Icelake events, "); 6318 name = "icelake"; 6319 break; 6320 6321 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6322 pmem = true; 6323 x86_pmu.late_ack = true; 6324 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6325 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6326 6327 x86_pmu.event_constraints = intel_spr_event_constraints; 6328 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6329 x86_pmu.extra_regs = intel_spr_extra_regs; 6330 x86_pmu.limit_period = spr_limit_period; 6331 x86_pmu.pebs_aliases = NULL; 6332 x86_pmu.pebs_prec_dist = true; 6333 x86_pmu.pebs_block = true; 6334 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6335 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6336 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6337 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6338 6339 x86_pmu.hw_config = hsw_hw_config; 6340 x86_pmu.get_event_constraints = spr_get_event_constraints; 6341 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6342 hsw_format_attr : nhm_format_attr; 6343 extra_skl_attr = skl_format_attr; 6344 mem_attr = spr_events_attrs; 6345 td_attr = spr_td_events_attrs; 6346 tsx_attr = spr_tsx_events_attrs; 6347 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6348 x86_pmu.lbr_pt_coexist = true; 6349 intel_pmu_pebs_data_source_skl(pmem); 6350 x86_pmu.num_topdown_events = 8; 6351 x86_pmu.update_topdown_event = icl_update_topdown_event; 6352 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6353 pr_cont("Sapphire Rapids events, "); 6354 name = "sapphire_rapids"; 6355 break; 6356 6357 case INTEL_FAM6_ALDERLAKE: 6358 case INTEL_FAM6_ALDERLAKE_L: 6359 case INTEL_FAM6_RAPTORLAKE: 6360 case INTEL_FAM6_RAPTORLAKE_P: 6361 /* 6362 * Alder Lake has 2 types of CPU, core and atom. 6363 * 6364 * Initialize the common PerfMon capabilities here. 6365 */ 6366 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6367 sizeof(struct x86_hybrid_pmu), 6368 GFP_KERNEL); 6369 if (!x86_pmu.hybrid_pmu) 6370 return -ENOMEM; 6371 static_branch_enable(&perf_is_hybrid); 6372 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6373 6374 x86_pmu.pebs_aliases = NULL; 6375 x86_pmu.pebs_prec_dist = true; 6376 x86_pmu.pebs_block = true; 6377 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6378 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6379 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6380 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6381 x86_pmu.lbr_pt_coexist = true; 6382 intel_pmu_pebs_data_source_adl(); 6383 x86_pmu.pebs_latency_data = adl_latency_data_small; 6384 x86_pmu.num_topdown_events = 8; 6385 x86_pmu.update_topdown_event = adl_update_topdown_event; 6386 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; 6387 6388 x86_pmu.filter_match = intel_pmu_filter_match; 6389 x86_pmu.get_event_constraints = adl_get_event_constraints; 6390 x86_pmu.hw_config = adl_hw_config; 6391 x86_pmu.limit_period = spr_limit_period; 6392 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6393 /* 6394 * The rtm_abort_event is used to check whether to enable GPRs 6395 * for the RTM abort event. Atom doesn't have the RTM abort 6396 * event. There is no harmful to set it in the common 6397 * x86_pmu.rtm_abort_event. 6398 */ 6399 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6400 6401 td_attr = adl_hybrid_events_attrs; 6402 mem_attr = adl_hybrid_mem_attrs; 6403 tsx_attr = adl_hybrid_tsx_attrs; 6404 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6405 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6406 6407 /* Initialize big core specific PerfMon capabilities.*/ 6408 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6409 pmu->name = "cpu_core"; 6410 pmu->cpu_type = hybrid_big; 6411 pmu->late_ack = true; 6412 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6413 pmu->num_counters = x86_pmu.num_counters + 2; 6414 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6415 } else { 6416 pmu->num_counters = x86_pmu.num_counters; 6417 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6418 } 6419 6420 /* 6421 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 6422 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 6423 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 6424 * mistakenly add extra counters for P-cores. Correct the number of 6425 * counters here. 6426 */ 6427 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) { 6428 pmu->num_counters = x86_pmu.num_counters; 6429 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6430 } 6431 6432 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6433 pmu->unconstrained = (struct event_constraint) 6434 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6435 0, pmu->num_counters, 0, 0); 6436 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6437 pmu->intel_cap.perf_metrics = 1; 6438 pmu->intel_cap.pebs_output_pt_available = 0; 6439 6440 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6441 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6442 pmu->event_constraints = intel_spr_event_constraints; 6443 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6444 pmu->extra_regs = intel_spr_extra_regs; 6445 6446 /* Initialize Atom core specific PerfMon capabilities.*/ 6447 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6448 pmu->name = "cpu_atom"; 6449 pmu->cpu_type = hybrid_small; 6450 pmu->mid_ack = true; 6451 pmu->num_counters = x86_pmu.num_counters; 6452 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6453 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6454 pmu->unconstrained = (struct event_constraint) 6455 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6456 0, pmu->num_counters, 0, 0); 6457 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6458 pmu->intel_cap.perf_metrics = 0; 6459 pmu->intel_cap.pebs_output_pt_available = 1; 6460 6461 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6462 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6463 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6464 pmu->event_constraints = intel_slm_event_constraints; 6465 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6466 pmu->extra_regs = intel_grt_extra_regs; 6467 pr_cont("Alderlake Hybrid events, "); 6468 name = "alderlake_hybrid"; 6469 break; 6470 6471 default: 6472 switch (x86_pmu.version) { 6473 case 1: 6474 x86_pmu.event_constraints = intel_v1_event_constraints; 6475 pr_cont("generic architected perfmon v1, "); 6476 name = "generic_arch_v1"; 6477 break; 6478 case 2: 6479 case 3: 6480 case 4: 6481 /* 6482 * default constraints for v2 and up 6483 */ 6484 x86_pmu.event_constraints = intel_gen_event_constraints; 6485 pr_cont("generic architected perfmon, "); 6486 name = "generic_arch_v2+"; 6487 break; 6488 default: 6489 /* 6490 * The default constraints for v5 and up can support up to 6491 * 16 fixed counters. For the fixed counters 4 and later, 6492 * the pseudo-encoding is applied. 6493 * The constraints may be cut according to the CPUID enumeration 6494 * by inserting the EVENT_CONSTRAINT_END. 6495 */ 6496 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) 6497 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 6498 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1; 6499 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 6500 pr_cont("generic architected perfmon, "); 6501 name = "generic_arch_v5+"; 6502 break; 6503 } 6504 } 6505 6506 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6507 6508 if (!is_hybrid()) { 6509 group_events_td.attrs = td_attr; 6510 group_events_mem.attrs = mem_attr; 6511 group_events_tsx.attrs = tsx_attr; 6512 group_format_extra.attrs = extra_attr; 6513 group_format_extra_skl.attrs = extra_skl_attr; 6514 6515 x86_pmu.attr_update = attr_update; 6516 } else { 6517 hybrid_group_events_td.attrs = td_attr; 6518 hybrid_group_events_mem.attrs = mem_attr; 6519 hybrid_group_events_tsx.attrs = tsx_attr; 6520 hybrid_group_format_extra.attrs = extra_attr; 6521 6522 x86_pmu.attr_update = hybrid_attr_update; 6523 } 6524 6525 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6526 &x86_pmu.num_counters_fixed, 6527 &x86_pmu.intel_ctrl, 6528 (u64)fixed_mask); 6529 6530 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6531 if (x86_pmu.intel_cap.anythread_deprecated) 6532 x86_pmu.format_attrs = intel_arch_formats_attr; 6533 6534 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6535 x86_pmu.num_counters, 6536 x86_pmu.num_counters_fixed, 6537 x86_pmu.intel_ctrl); 6538 /* 6539 * Access LBR MSR may cause #GP under certain circumstances. 6540 * Check all LBR MSR here. 6541 * Disable LBR access if any LBR MSRs can not be accessed. 6542 */ 6543 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6544 x86_pmu.lbr_nr = 0; 6545 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6546 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6547 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6548 x86_pmu.lbr_nr = 0; 6549 } 6550 6551 if (x86_pmu.lbr_nr) { 6552 intel_pmu_lbr_init(); 6553 6554 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6555 6556 /* only support branch_stack snapshot for perfmon >= v2 */ 6557 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6558 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6559 static_call_update(perf_snapshot_branch_stack, 6560 intel_pmu_snapshot_arch_branch_stack); 6561 } else { 6562 static_call_update(perf_snapshot_branch_stack, 6563 intel_pmu_snapshot_branch_stack); 6564 } 6565 } 6566 } 6567 6568 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6569 6570 /* Support full width counters using alternative MSR range */ 6571 if (x86_pmu.intel_cap.full_width_write) { 6572 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6573 x86_pmu.perfctr = MSR_IA32_PMC0; 6574 pr_cont("full-width counters, "); 6575 } 6576 6577 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6578 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6579 6580 if (is_hybrid()) 6581 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6582 6583 intel_aux_output_init(); 6584 6585 return 0; 6586 } 6587 6588 /* 6589 * HT bug: phase 2 init 6590 * Called once we have valid topology information to check 6591 * whether or not HT is enabled 6592 * If HT is off, then we disable the workaround 6593 */ 6594 static __init int fixup_ht_bug(void) 6595 { 6596 int c; 6597 /* 6598 * problem not present on this CPU model, nothing to do 6599 */ 6600 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6601 return 0; 6602 6603 if (topology_max_smt_threads() > 1) { 6604 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6605 return 0; 6606 } 6607 6608 cpus_read_lock(); 6609 6610 hardlockup_detector_perf_stop(); 6611 6612 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6613 6614 x86_pmu.start_scheduling = NULL; 6615 x86_pmu.commit_scheduling = NULL; 6616 x86_pmu.stop_scheduling = NULL; 6617 6618 hardlockup_detector_perf_restart(); 6619 6620 for_each_online_cpu(c) 6621 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6622 6623 cpus_read_unlock(); 6624 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6625 return 0; 6626 } 6627 subsys_initcall(fixup_ht_bug) 6628