1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 18 #include <asm/cpufeature.h> 19 #include <asm/hardirq.h> 20 #include <asm/intel-family.h> 21 #include <asm/intel_pt.h> 22 #include <asm/apic.h> 23 #include <asm/cpu_device_id.h> 24 25 #include "../perf_event.h" 26 27 /* 28 * Intel PerfMon, used on Core and later. 29 */ 30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31 { 32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40 }; 41 42 static struct event_constraint intel_core_event_constraints[] __read_mostly = 43 { 44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50 EVENT_CONSTRAINT_END 51 }; 52 53 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54 { 55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68 EVENT_CONSTRAINT_END 69 }; 70 71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72 { 73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84 EVENT_CONSTRAINT_END 85 }; 86 87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88 { 89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92 EVENT_EXTRA_END 93 }; 94 95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96 { 97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104 EVENT_CONSTRAINT_END 105 }; 106 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108 { 109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121 122 /* 123 * When HT is off these events can only run on the bottom 4 counters 124 * When HT is on, they are impacted by the HT bug and require EXCL access 125 */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130 131 EVENT_CONSTRAINT_END 132 }; 133 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135 { 136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149 150 /* 151 * When HT is off these events can only run on the bottom 4 counters 152 * When HT is on, they are impacted by the HT bug and require EXCL access 153 */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158 159 EVENT_CONSTRAINT_END 160 }; 161 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163 { 164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168 EVENT_EXTRA_END 169 }; 170 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172 { 173 EVENT_CONSTRAINT_END 174 }; 175 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177 { 178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181 EVENT_CONSTRAINT_END 182 }; 183 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185 { 186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189 EVENT_CONSTRAINT_END 190 }; 191 192 static struct event_constraint intel_skl_event_constraints[] = { 193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 197 198 /* 199 * when HT is off, these can only run on the bottom 4 counters 200 */ 201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 206 207 EVENT_CONSTRAINT_END 208 }; 209 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213 EVENT_EXTRA_END 214 }; 215 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221 EVENT_EXTRA_END 222 }; 223 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229 EVENT_EXTRA_END 230 }; 231 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236 /* 237 * Note the low 8 bits eventsel code is not a continuous field, containing 238 * some #GPing bits. These are masked out. 239 */ 240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241 EVENT_EXTRA_END 242 }; 243 244 static struct event_constraint intel_icl_event_constraints[] = { 245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 247 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 248 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 249 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 250 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 254 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 255 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 256 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 257 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 258 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 259 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 260 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 261 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 262 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 263 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 264 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 265 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 266 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 267 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 268 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 269 EVENT_CONSTRAINT_END 270 }; 271 272 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 273 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 274 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 275 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 276 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 277 EVENT_EXTRA_END 278 }; 279 280 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 281 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 282 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 283 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 284 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 285 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 286 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 287 EVENT_EXTRA_END 288 }; 289 290 static struct event_constraint intel_spr_event_constraints[] = { 291 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 292 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 293 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 294 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 295 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 298 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 299 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 300 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 301 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 302 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 303 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 304 305 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 306 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 307 /* 308 * Generally event codes < 0x90 are restricted to counters 0-3. 309 * The 0x2E and 0x3C are exception, which has no restriction. 310 */ 311 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 312 313 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 314 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 315 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 316 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 317 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 318 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 319 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 320 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 321 /* 322 * Generally event codes >= 0x90 are likely to have no restrictions. 323 * The exception are defined as above. 324 */ 325 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 326 327 EVENT_CONSTRAINT_END 328 }; 329 330 331 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 332 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 333 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 334 335 static struct attribute *nhm_mem_events_attrs[] = { 336 EVENT_PTR(mem_ld_nhm), 337 NULL, 338 }; 339 340 /* 341 * topdown events for Intel Core CPUs. 342 * 343 * The events are all in slots, which is a free slot in a 4 wide 344 * pipeline. Some events are already reported in slots, for cycle 345 * events we multiply by the pipeline width (4). 346 * 347 * With Hyper Threading on, topdown metrics are either summed or averaged 348 * between the threads of a core: (count_t0 + count_t1). 349 * 350 * For the average case the metric is always scaled to pipeline width, 351 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 352 */ 353 354 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 355 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 356 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 357 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 358 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 359 "event=0xe,umask=0x1"); /* uops_issued.any */ 360 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 361 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 362 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 363 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 364 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 365 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 366 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 367 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 368 "4", "2"); 369 370 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 371 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 372 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 373 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 374 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 375 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 376 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 377 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 378 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 379 380 static struct attribute *snb_events_attrs[] = { 381 EVENT_PTR(td_slots_issued), 382 EVENT_PTR(td_slots_retired), 383 EVENT_PTR(td_fetch_bubbles), 384 EVENT_PTR(td_total_slots), 385 EVENT_PTR(td_total_slots_scale), 386 EVENT_PTR(td_recovery_bubbles), 387 EVENT_PTR(td_recovery_bubbles_scale), 388 NULL, 389 }; 390 391 static struct attribute *snb_mem_events_attrs[] = { 392 EVENT_PTR(mem_ld_snb), 393 EVENT_PTR(mem_st_snb), 394 NULL, 395 }; 396 397 static struct event_constraint intel_hsw_event_constraints[] = { 398 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 399 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 400 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 401 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 402 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 403 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 404 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 405 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 406 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 407 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 408 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 409 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 410 411 /* 412 * When HT is off these events can only run on the bottom 4 counters 413 * When HT is on, they are impacted by the HT bug and require EXCL access 414 */ 415 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 416 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 417 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 418 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 419 420 EVENT_CONSTRAINT_END 421 }; 422 423 static struct event_constraint intel_bdw_event_constraints[] = { 424 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 425 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 426 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 427 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 428 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 429 /* 430 * when HT is off, these can only run on the bottom 4 counters 431 */ 432 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 433 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 434 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 435 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 436 EVENT_CONSTRAINT_END 437 }; 438 439 static u64 intel_pmu_event_map(int hw_event) 440 { 441 return intel_perfmon_event_map[hw_event]; 442 } 443 444 static __initconst const u64 spr_hw_cache_event_ids 445 [PERF_COUNT_HW_CACHE_MAX] 446 [PERF_COUNT_HW_CACHE_OP_MAX] 447 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 448 { 449 [ C(L1D ) ] = { 450 [ C(OP_READ) ] = { 451 [ C(RESULT_ACCESS) ] = 0x81d0, 452 [ C(RESULT_MISS) ] = 0xe124, 453 }, 454 [ C(OP_WRITE) ] = { 455 [ C(RESULT_ACCESS) ] = 0x82d0, 456 }, 457 }, 458 [ C(L1I ) ] = { 459 [ C(OP_READ) ] = { 460 [ C(RESULT_MISS) ] = 0xe424, 461 }, 462 [ C(OP_WRITE) ] = { 463 [ C(RESULT_ACCESS) ] = -1, 464 [ C(RESULT_MISS) ] = -1, 465 }, 466 }, 467 [ C(LL ) ] = { 468 [ C(OP_READ) ] = { 469 [ C(RESULT_ACCESS) ] = 0x12a, 470 [ C(RESULT_MISS) ] = 0x12a, 471 }, 472 [ C(OP_WRITE) ] = { 473 [ C(RESULT_ACCESS) ] = 0x12a, 474 [ C(RESULT_MISS) ] = 0x12a, 475 }, 476 }, 477 [ C(DTLB) ] = { 478 [ C(OP_READ) ] = { 479 [ C(RESULT_ACCESS) ] = 0x81d0, 480 [ C(RESULT_MISS) ] = 0xe12, 481 }, 482 [ C(OP_WRITE) ] = { 483 [ C(RESULT_ACCESS) ] = 0x82d0, 484 [ C(RESULT_MISS) ] = 0xe13, 485 }, 486 }, 487 [ C(ITLB) ] = { 488 [ C(OP_READ) ] = { 489 [ C(RESULT_ACCESS) ] = -1, 490 [ C(RESULT_MISS) ] = 0xe11, 491 }, 492 [ C(OP_WRITE) ] = { 493 [ C(RESULT_ACCESS) ] = -1, 494 [ C(RESULT_MISS) ] = -1, 495 }, 496 [ C(OP_PREFETCH) ] = { 497 [ C(RESULT_ACCESS) ] = -1, 498 [ C(RESULT_MISS) ] = -1, 499 }, 500 }, 501 [ C(BPU ) ] = { 502 [ C(OP_READ) ] = { 503 [ C(RESULT_ACCESS) ] = 0x4c4, 504 [ C(RESULT_MISS) ] = 0x4c5, 505 }, 506 [ C(OP_WRITE) ] = { 507 [ C(RESULT_ACCESS) ] = -1, 508 [ C(RESULT_MISS) ] = -1, 509 }, 510 [ C(OP_PREFETCH) ] = { 511 [ C(RESULT_ACCESS) ] = -1, 512 [ C(RESULT_MISS) ] = -1, 513 }, 514 }, 515 [ C(NODE) ] = { 516 [ C(OP_READ) ] = { 517 [ C(RESULT_ACCESS) ] = 0x12a, 518 [ C(RESULT_MISS) ] = 0x12a, 519 }, 520 }, 521 }; 522 523 static __initconst const u64 spr_hw_cache_extra_regs 524 [PERF_COUNT_HW_CACHE_MAX] 525 [PERF_COUNT_HW_CACHE_OP_MAX] 526 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 527 { 528 [ C(LL ) ] = { 529 [ C(OP_READ) ] = { 530 [ C(RESULT_ACCESS) ] = 0x10001, 531 [ C(RESULT_MISS) ] = 0x3fbfc00001, 532 }, 533 [ C(OP_WRITE) ] = { 534 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 535 [ C(RESULT_MISS) ] = 0x3f3fc00002, 536 }, 537 }, 538 [ C(NODE) ] = { 539 [ C(OP_READ) ] = { 540 [ C(RESULT_ACCESS) ] = 0x10c000001, 541 [ C(RESULT_MISS) ] = 0x3fb3000001, 542 }, 543 }, 544 }; 545 546 /* 547 * Notes on the events: 548 * - data reads do not include code reads (comparable to earlier tables) 549 * - data counts include speculative execution (except L1 write, dtlb, bpu) 550 * - remote node access includes remote memory, remote cache, remote mmio. 551 * - prefetches are not included in the counts. 552 * - icache miss does not include decoded icache 553 */ 554 555 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 556 #define SKL_DEMAND_RFO BIT_ULL(1) 557 #define SKL_ANY_RESPONSE BIT_ULL(16) 558 #define SKL_SUPPLIER_NONE BIT_ULL(17) 559 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 560 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 561 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 562 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 563 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 564 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 565 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 566 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 567 #define SKL_SPL_HIT BIT_ULL(30) 568 #define SKL_SNOOP_NONE BIT_ULL(31) 569 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 570 #define SKL_SNOOP_MISS BIT_ULL(33) 571 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 572 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 573 #define SKL_SNOOP_HITM BIT_ULL(36) 574 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 575 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 576 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 577 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 578 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 579 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 580 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 581 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 582 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 583 SKL_SNOOP_HITM|SKL_SPL_HIT) 584 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 585 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 586 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 587 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 588 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 589 590 static __initconst const u64 skl_hw_cache_event_ids 591 [PERF_COUNT_HW_CACHE_MAX] 592 [PERF_COUNT_HW_CACHE_OP_MAX] 593 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 594 { 595 [ C(L1D ) ] = { 596 [ C(OP_READ) ] = { 597 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 598 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 599 }, 600 [ C(OP_WRITE) ] = { 601 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 602 [ C(RESULT_MISS) ] = 0x0, 603 }, 604 [ C(OP_PREFETCH) ] = { 605 [ C(RESULT_ACCESS) ] = 0x0, 606 [ C(RESULT_MISS) ] = 0x0, 607 }, 608 }, 609 [ C(L1I ) ] = { 610 [ C(OP_READ) ] = { 611 [ C(RESULT_ACCESS) ] = 0x0, 612 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 613 }, 614 [ C(OP_WRITE) ] = { 615 [ C(RESULT_ACCESS) ] = -1, 616 [ C(RESULT_MISS) ] = -1, 617 }, 618 [ C(OP_PREFETCH) ] = { 619 [ C(RESULT_ACCESS) ] = 0x0, 620 [ C(RESULT_MISS) ] = 0x0, 621 }, 622 }, 623 [ C(LL ) ] = { 624 [ C(OP_READ) ] = { 625 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 626 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 627 }, 628 [ C(OP_WRITE) ] = { 629 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 630 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 631 }, 632 [ C(OP_PREFETCH) ] = { 633 [ C(RESULT_ACCESS) ] = 0x0, 634 [ C(RESULT_MISS) ] = 0x0, 635 }, 636 }, 637 [ C(DTLB) ] = { 638 [ C(OP_READ) ] = { 639 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 640 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 641 }, 642 [ C(OP_WRITE) ] = { 643 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 644 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 645 }, 646 [ C(OP_PREFETCH) ] = { 647 [ C(RESULT_ACCESS) ] = 0x0, 648 [ C(RESULT_MISS) ] = 0x0, 649 }, 650 }, 651 [ C(ITLB) ] = { 652 [ C(OP_READ) ] = { 653 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 654 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 655 }, 656 [ C(OP_WRITE) ] = { 657 [ C(RESULT_ACCESS) ] = -1, 658 [ C(RESULT_MISS) ] = -1, 659 }, 660 [ C(OP_PREFETCH) ] = { 661 [ C(RESULT_ACCESS) ] = -1, 662 [ C(RESULT_MISS) ] = -1, 663 }, 664 }, 665 [ C(BPU ) ] = { 666 [ C(OP_READ) ] = { 667 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 668 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 669 }, 670 [ C(OP_WRITE) ] = { 671 [ C(RESULT_ACCESS) ] = -1, 672 [ C(RESULT_MISS) ] = -1, 673 }, 674 [ C(OP_PREFETCH) ] = { 675 [ C(RESULT_ACCESS) ] = -1, 676 [ C(RESULT_MISS) ] = -1, 677 }, 678 }, 679 [ C(NODE) ] = { 680 [ C(OP_READ) ] = { 681 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 682 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 683 }, 684 [ C(OP_WRITE) ] = { 685 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 686 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 687 }, 688 [ C(OP_PREFETCH) ] = { 689 [ C(RESULT_ACCESS) ] = 0x0, 690 [ C(RESULT_MISS) ] = 0x0, 691 }, 692 }, 693 }; 694 695 static __initconst const u64 skl_hw_cache_extra_regs 696 [PERF_COUNT_HW_CACHE_MAX] 697 [PERF_COUNT_HW_CACHE_OP_MAX] 698 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 699 { 700 [ C(LL ) ] = { 701 [ C(OP_READ) ] = { 702 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 703 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 704 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 705 SKL_L3_MISS|SKL_ANY_SNOOP| 706 SKL_SUPPLIER_NONE, 707 }, 708 [ C(OP_WRITE) ] = { 709 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 710 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 711 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 712 SKL_L3_MISS|SKL_ANY_SNOOP| 713 SKL_SUPPLIER_NONE, 714 }, 715 [ C(OP_PREFETCH) ] = { 716 [ C(RESULT_ACCESS) ] = 0x0, 717 [ C(RESULT_MISS) ] = 0x0, 718 }, 719 }, 720 [ C(NODE) ] = { 721 [ C(OP_READ) ] = { 722 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 723 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 724 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 725 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 726 }, 727 [ C(OP_WRITE) ] = { 728 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 729 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 730 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 731 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 732 }, 733 [ C(OP_PREFETCH) ] = { 734 [ C(RESULT_ACCESS) ] = 0x0, 735 [ C(RESULT_MISS) ] = 0x0, 736 }, 737 }, 738 }; 739 740 #define SNB_DMND_DATA_RD (1ULL << 0) 741 #define SNB_DMND_RFO (1ULL << 1) 742 #define SNB_DMND_IFETCH (1ULL << 2) 743 #define SNB_DMND_WB (1ULL << 3) 744 #define SNB_PF_DATA_RD (1ULL << 4) 745 #define SNB_PF_RFO (1ULL << 5) 746 #define SNB_PF_IFETCH (1ULL << 6) 747 #define SNB_LLC_DATA_RD (1ULL << 7) 748 #define SNB_LLC_RFO (1ULL << 8) 749 #define SNB_LLC_IFETCH (1ULL << 9) 750 #define SNB_BUS_LOCKS (1ULL << 10) 751 #define SNB_STRM_ST (1ULL << 11) 752 #define SNB_OTHER (1ULL << 15) 753 #define SNB_RESP_ANY (1ULL << 16) 754 #define SNB_NO_SUPP (1ULL << 17) 755 #define SNB_LLC_HITM (1ULL << 18) 756 #define SNB_LLC_HITE (1ULL << 19) 757 #define SNB_LLC_HITS (1ULL << 20) 758 #define SNB_LLC_HITF (1ULL << 21) 759 #define SNB_LOCAL (1ULL << 22) 760 #define SNB_REMOTE (0xffULL << 23) 761 #define SNB_SNP_NONE (1ULL << 31) 762 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 763 #define SNB_SNP_MISS (1ULL << 33) 764 #define SNB_NO_FWD (1ULL << 34) 765 #define SNB_SNP_FWD (1ULL << 35) 766 #define SNB_HITM (1ULL << 36) 767 #define SNB_NON_DRAM (1ULL << 37) 768 769 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 770 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 771 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 772 773 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 774 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 775 SNB_HITM) 776 777 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 778 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 779 780 #define SNB_L3_ACCESS SNB_RESP_ANY 781 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 782 783 static __initconst const u64 snb_hw_cache_extra_regs 784 [PERF_COUNT_HW_CACHE_MAX] 785 [PERF_COUNT_HW_CACHE_OP_MAX] 786 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 787 { 788 [ C(LL ) ] = { 789 [ C(OP_READ) ] = { 790 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 791 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 792 }, 793 [ C(OP_WRITE) ] = { 794 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 795 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 796 }, 797 [ C(OP_PREFETCH) ] = { 798 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 799 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 800 }, 801 }, 802 [ C(NODE) ] = { 803 [ C(OP_READ) ] = { 804 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 805 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 806 }, 807 [ C(OP_WRITE) ] = { 808 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 809 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 810 }, 811 [ C(OP_PREFETCH) ] = { 812 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 813 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 814 }, 815 }, 816 }; 817 818 static __initconst const u64 snb_hw_cache_event_ids 819 [PERF_COUNT_HW_CACHE_MAX] 820 [PERF_COUNT_HW_CACHE_OP_MAX] 821 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 822 { 823 [ C(L1D) ] = { 824 [ C(OP_READ) ] = { 825 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 826 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 827 }, 828 [ C(OP_WRITE) ] = { 829 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 830 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 831 }, 832 [ C(OP_PREFETCH) ] = { 833 [ C(RESULT_ACCESS) ] = 0x0, 834 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 835 }, 836 }, 837 [ C(L1I ) ] = { 838 [ C(OP_READ) ] = { 839 [ C(RESULT_ACCESS) ] = 0x0, 840 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 841 }, 842 [ C(OP_WRITE) ] = { 843 [ C(RESULT_ACCESS) ] = -1, 844 [ C(RESULT_MISS) ] = -1, 845 }, 846 [ C(OP_PREFETCH) ] = { 847 [ C(RESULT_ACCESS) ] = 0x0, 848 [ C(RESULT_MISS) ] = 0x0, 849 }, 850 }, 851 [ C(LL ) ] = { 852 [ C(OP_READ) ] = { 853 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 854 [ C(RESULT_ACCESS) ] = 0x01b7, 855 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 856 [ C(RESULT_MISS) ] = 0x01b7, 857 }, 858 [ C(OP_WRITE) ] = { 859 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 860 [ C(RESULT_ACCESS) ] = 0x01b7, 861 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 862 [ C(RESULT_MISS) ] = 0x01b7, 863 }, 864 [ C(OP_PREFETCH) ] = { 865 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 866 [ C(RESULT_ACCESS) ] = 0x01b7, 867 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 868 [ C(RESULT_MISS) ] = 0x01b7, 869 }, 870 }, 871 [ C(DTLB) ] = { 872 [ C(OP_READ) ] = { 873 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 874 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 875 }, 876 [ C(OP_WRITE) ] = { 877 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 878 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 879 }, 880 [ C(OP_PREFETCH) ] = { 881 [ C(RESULT_ACCESS) ] = 0x0, 882 [ C(RESULT_MISS) ] = 0x0, 883 }, 884 }, 885 [ C(ITLB) ] = { 886 [ C(OP_READ) ] = { 887 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 888 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 889 }, 890 [ C(OP_WRITE) ] = { 891 [ C(RESULT_ACCESS) ] = -1, 892 [ C(RESULT_MISS) ] = -1, 893 }, 894 [ C(OP_PREFETCH) ] = { 895 [ C(RESULT_ACCESS) ] = -1, 896 [ C(RESULT_MISS) ] = -1, 897 }, 898 }, 899 [ C(BPU ) ] = { 900 [ C(OP_READ) ] = { 901 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 902 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 903 }, 904 [ C(OP_WRITE) ] = { 905 [ C(RESULT_ACCESS) ] = -1, 906 [ C(RESULT_MISS) ] = -1, 907 }, 908 [ C(OP_PREFETCH) ] = { 909 [ C(RESULT_ACCESS) ] = -1, 910 [ C(RESULT_MISS) ] = -1, 911 }, 912 }, 913 [ C(NODE) ] = { 914 [ C(OP_READ) ] = { 915 [ C(RESULT_ACCESS) ] = 0x01b7, 916 [ C(RESULT_MISS) ] = 0x01b7, 917 }, 918 [ C(OP_WRITE) ] = { 919 [ C(RESULT_ACCESS) ] = 0x01b7, 920 [ C(RESULT_MISS) ] = 0x01b7, 921 }, 922 [ C(OP_PREFETCH) ] = { 923 [ C(RESULT_ACCESS) ] = 0x01b7, 924 [ C(RESULT_MISS) ] = 0x01b7, 925 }, 926 }, 927 928 }; 929 930 /* 931 * Notes on the events: 932 * - data reads do not include code reads (comparable to earlier tables) 933 * - data counts include speculative execution (except L1 write, dtlb, bpu) 934 * - remote node access includes remote memory, remote cache, remote mmio. 935 * - prefetches are not included in the counts because they are not 936 * reliably counted. 937 */ 938 939 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 940 #define HSW_DEMAND_RFO BIT_ULL(1) 941 #define HSW_ANY_RESPONSE BIT_ULL(16) 942 #define HSW_SUPPLIER_NONE BIT_ULL(17) 943 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 944 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 945 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 946 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 947 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 948 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 949 HSW_L3_MISS_REMOTE_HOP2P) 950 #define HSW_SNOOP_NONE BIT_ULL(31) 951 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 952 #define HSW_SNOOP_MISS BIT_ULL(33) 953 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 954 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 955 #define HSW_SNOOP_HITM BIT_ULL(36) 956 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 957 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 958 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 959 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 960 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 961 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 962 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 963 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 964 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 965 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 966 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 967 968 #define BDW_L3_MISS_LOCAL BIT(26) 969 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 970 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 971 HSW_L3_MISS_REMOTE_HOP2P) 972 973 974 static __initconst const u64 hsw_hw_cache_event_ids 975 [PERF_COUNT_HW_CACHE_MAX] 976 [PERF_COUNT_HW_CACHE_OP_MAX] 977 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 978 { 979 [ C(L1D ) ] = { 980 [ C(OP_READ) ] = { 981 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 982 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 983 }, 984 [ C(OP_WRITE) ] = { 985 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 986 [ C(RESULT_MISS) ] = 0x0, 987 }, 988 [ C(OP_PREFETCH) ] = { 989 [ C(RESULT_ACCESS) ] = 0x0, 990 [ C(RESULT_MISS) ] = 0x0, 991 }, 992 }, 993 [ C(L1I ) ] = { 994 [ C(OP_READ) ] = { 995 [ C(RESULT_ACCESS) ] = 0x0, 996 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 997 }, 998 [ C(OP_WRITE) ] = { 999 [ C(RESULT_ACCESS) ] = -1, 1000 [ C(RESULT_MISS) ] = -1, 1001 }, 1002 [ C(OP_PREFETCH) ] = { 1003 [ C(RESULT_ACCESS) ] = 0x0, 1004 [ C(RESULT_MISS) ] = 0x0, 1005 }, 1006 }, 1007 [ C(LL ) ] = { 1008 [ C(OP_READ) ] = { 1009 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1010 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1011 }, 1012 [ C(OP_WRITE) ] = { 1013 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1014 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1015 }, 1016 [ C(OP_PREFETCH) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x0, 1018 [ C(RESULT_MISS) ] = 0x0, 1019 }, 1020 }, 1021 [ C(DTLB) ] = { 1022 [ C(OP_READ) ] = { 1023 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1024 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1025 }, 1026 [ C(OP_WRITE) ] = { 1027 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1028 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1029 }, 1030 [ C(OP_PREFETCH) ] = { 1031 [ C(RESULT_ACCESS) ] = 0x0, 1032 [ C(RESULT_MISS) ] = 0x0, 1033 }, 1034 }, 1035 [ C(ITLB) ] = { 1036 [ C(OP_READ) ] = { 1037 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1038 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1039 }, 1040 [ C(OP_WRITE) ] = { 1041 [ C(RESULT_ACCESS) ] = -1, 1042 [ C(RESULT_MISS) ] = -1, 1043 }, 1044 [ C(OP_PREFETCH) ] = { 1045 [ C(RESULT_ACCESS) ] = -1, 1046 [ C(RESULT_MISS) ] = -1, 1047 }, 1048 }, 1049 [ C(BPU ) ] = { 1050 [ C(OP_READ) ] = { 1051 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1052 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1053 }, 1054 [ C(OP_WRITE) ] = { 1055 [ C(RESULT_ACCESS) ] = -1, 1056 [ C(RESULT_MISS) ] = -1, 1057 }, 1058 [ C(OP_PREFETCH) ] = { 1059 [ C(RESULT_ACCESS) ] = -1, 1060 [ C(RESULT_MISS) ] = -1, 1061 }, 1062 }, 1063 [ C(NODE) ] = { 1064 [ C(OP_READ) ] = { 1065 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1066 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1067 }, 1068 [ C(OP_WRITE) ] = { 1069 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1070 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1071 }, 1072 [ C(OP_PREFETCH) ] = { 1073 [ C(RESULT_ACCESS) ] = 0x0, 1074 [ C(RESULT_MISS) ] = 0x0, 1075 }, 1076 }, 1077 }; 1078 1079 static __initconst const u64 hsw_hw_cache_extra_regs 1080 [PERF_COUNT_HW_CACHE_MAX] 1081 [PERF_COUNT_HW_CACHE_OP_MAX] 1082 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1083 { 1084 [ C(LL ) ] = { 1085 [ C(OP_READ) ] = { 1086 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1087 HSW_LLC_ACCESS, 1088 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1089 HSW_L3_MISS|HSW_ANY_SNOOP, 1090 }, 1091 [ C(OP_WRITE) ] = { 1092 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1093 HSW_LLC_ACCESS, 1094 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1095 HSW_L3_MISS|HSW_ANY_SNOOP, 1096 }, 1097 [ C(OP_PREFETCH) ] = { 1098 [ C(RESULT_ACCESS) ] = 0x0, 1099 [ C(RESULT_MISS) ] = 0x0, 1100 }, 1101 }, 1102 [ C(NODE) ] = { 1103 [ C(OP_READ) ] = { 1104 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1105 HSW_L3_MISS_LOCAL_DRAM| 1106 HSW_SNOOP_DRAM, 1107 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1108 HSW_L3_MISS_REMOTE| 1109 HSW_SNOOP_DRAM, 1110 }, 1111 [ C(OP_WRITE) ] = { 1112 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1113 HSW_L3_MISS_LOCAL_DRAM| 1114 HSW_SNOOP_DRAM, 1115 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1116 HSW_L3_MISS_REMOTE| 1117 HSW_SNOOP_DRAM, 1118 }, 1119 [ C(OP_PREFETCH) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x0, 1121 [ C(RESULT_MISS) ] = 0x0, 1122 }, 1123 }, 1124 }; 1125 1126 static __initconst const u64 westmere_hw_cache_event_ids 1127 [PERF_COUNT_HW_CACHE_MAX] 1128 [PERF_COUNT_HW_CACHE_OP_MAX] 1129 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1130 { 1131 [ C(L1D) ] = { 1132 [ C(OP_READ) ] = { 1133 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1134 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1135 }, 1136 [ C(OP_WRITE) ] = { 1137 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1138 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1139 }, 1140 [ C(OP_PREFETCH) ] = { 1141 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1142 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1143 }, 1144 }, 1145 [ C(L1I ) ] = { 1146 [ C(OP_READ) ] = { 1147 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1148 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1149 }, 1150 [ C(OP_WRITE) ] = { 1151 [ C(RESULT_ACCESS) ] = -1, 1152 [ C(RESULT_MISS) ] = -1, 1153 }, 1154 [ C(OP_PREFETCH) ] = { 1155 [ C(RESULT_ACCESS) ] = 0x0, 1156 [ C(RESULT_MISS) ] = 0x0, 1157 }, 1158 }, 1159 [ C(LL ) ] = { 1160 [ C(OP_READ) ] = { 1161 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1162 [ C(RESULT_ACCESS) ] = 0x01b7, 1163 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1164 [ C(RESULT_MISS) ] = 0x01b7, 1165 }, 1166 /* 1167 * Use RFO, not WRITEBACK, because a write miss would typically occur 1168 * on RFO. 1169 */ 1170 [ C(OP_WRITE) ] = { 1171 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1172 [ C(RESULT_ACCESS) ] = 0x01b7, 1173 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1174 [ C(RESULT_MISS) ] = 0x01b7, 1175 }, 1176 [ C(OP_PREFETCH) ] = { 1177 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1178 [ C(RESULT_ACCESS) ] = 0x01b7, 1179 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1180 [ C(RESULT_MISS) ] = 0x01b7, 1181 }, 1182 }, 1183 [ C(DTLB) ] = { 1184 [ C(OP_READ) ] = { 1185 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1186 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1187 }, 1188 [ C(OP_WRITE) ] = { 1189 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1190 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1191 }, 1192 [ C(OP_PREFETCH) ] = { 1193 [ C(RESULT_ACCESS) ] = 0x0, 1194 [ C(RESULT_MISS) ] = 0x0, 1195 }, 1196 }, 1197 [ C(ITLB) ] = { 1198 [ C(OP_READ) ] = { 1199 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1200 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1201 }, 1202 [ C(OP_WRITE) ] = { 1203 [ C(RESULT_ACCESS) ] = -1, 1204 [ C(RESULT_MISS) ] = -1, 1205 }, 1206 [ C(OP_PREFETCH) ] = { 1207 [ C(RESULT_ACCESS) ] = -1, 1208 [ C(RESULT_MISS) ] = -1, 1209 }, 1210 }, 1211 [ C(BPU ) ] = { 1212 [ C(OP_READ) ] = { 1213 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1214 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1215 }, 1216 [ C(OP_WRITE) ] = { 1217 [ C(RESULT_ACCESS) ] = -1, 1218 [ C(RESULT_MISS) ] = -1, 1219 }, 1220 [ C(OP_PREFETCH) ] = { 1221 [ C(RESULT_ACCESS) ] = -1, 1222 [ C(RESULT_MISS) ] = -1, 1223 }, 1224 }, 1225 [ C(NODE) ] = { 1226 [ C(OP_READ) ] = { 1227 [ C(RESULT_ACCESS) ] = 0x01b7, 1228 [ C(RESULT_MISS) ] = 0x01b7, 1229 }, 1230 [ C(OP_WRITE) ] = { 1231 [ C(RESULT_ACCESS) ] = 0x01b7, 1232 [ C(RESULT_MISS) ] = 0x01b7, 1233 }, 1234 [ C(OP_PREFETCH) ] = { 1235 [ C(RESULT_ACCESS) ] = 0x01b7, 1236 [ C(RESULT_MISS) ] = 0x01b7, 1237 }, 1238 }, 1239 }; 1240 1241 /* 1242 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1243 * See IA32 SDM Vol 3B 30.6.1.3 1244 */ 1245 1246 #define NHM_DMND_DATA_RD (1 << 0) 1247 #define NHM_DMND_RFO (1 << 1) 1248 #define NHM_DMND_IFETCH (1 << 2) 1249 #define NHM_DMND_WB (1 << 3) 1250 #define NHM_PF_DATA_RD (1 << 4) 1251 #define NHM_PF_DATA_RFO (1 << 5) 1252 #define NHM_PF_IFETCH (1 << 6) 1253 #define NHM_OFFCORE_OTHER (1 << 7) 1254 #define NHM_UNCORE_HIT (1 << 8) 1255 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1256 #define NHM_OTHER_CORE_HITM (1 << 10) 1257 /* reserved */ 1258 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1259 #define NHM_REMOTE_DRAM (1 << 13) 1260 #define NHM_LOCAL_DRAM (1 << 14) 1261 #define NHM_NON_DRAM (1 << 15) 1262 1263 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1264 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1265 1266 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1267 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1268 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1269 1270 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1271 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1272 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1273 1274 static __initconst const u64 nehalem_hw_cache_extra_regs 1275 [PERF_COUNT_HW_CACHE_MAX] 1276 [PERF_COUNT_HW_CACHE_OP_MAX] 1277 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1278 { 1279 [ C(LL ) ] = { 1280 [ C(OP_READ) ] = { 1281 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1282 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1283 }, 1284 [ C(OP_WRITE) ] = { 1285 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1286 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1287 }, 1288 [ C(OP_PREFETCH) ] = { 1289 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1290 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1291 }, 1292 }, 1293 [ C(NODE) ] = { 1294 [ C(OP_READ) ] = { 1295 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1296 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1297 }, 1298 [ C(OP_WRITE) ] = { 1299 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1300 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1301 }, 1302 [ C(OP_PREFETCH) ] = { 1303 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1304 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1305 }, 1306 }, 1307 }; 1308 1309 static __initconst const u64 nehalem_hw_cache_event_ids 1310 [PERF_COUNT_HW_CACHE_MAX] 1311 [PERF_COUNT_HW_CACHE_OP_MAX] 1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1313 { 1314 [ C(L1D) ] = { 1315 [ C(OP_READ) ] = { 1316 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1317 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1318 }, 1319 [ C(OP_WRITE) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1321 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1322 }, 1323 [ C(OP_PREFETCH) ] = { 1324 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1325 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1326 }, 1327 }, 1328 [ C(L1I ) ] = { 1329 [ C(OP_READ) ] = { 1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1332 }, 1333 [ C(OP_WRITE) ] = { 1334 [ C(RESULT_ACCESS) ] = -1, 1335 [ C(RESULT_MISS) ] = -1, 1336 }, 1337 [ C(OP_PREFETCH) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x0, 1339 [ C(RESULT_MISS) ] = 0x0, 1340 }, 1341 }, 1342 [ C(LL ) ] = { 1343 [ C(OP_READ) ] = { 1344 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1345 [ C(RESULT_ACCESS) ] = 0x01b7, 1346 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1347 [ C(RESULT_MISS) ] = 0x01b7, 1348 }, 1349 /* 1350 * Use RFO, not WRITEBACK, because a write miss would typically occur 1351 * on RFO. 1352 */ 1353 [ C(OP_WRITE) ] = { 1354 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1355 [ C(RESULT_ACCESS) ] = 0x01b7, 1356 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1357 [ C(RESULT_MISS) ] = 0x01b7, 1358 }, 1359 [ C(OP_PREFETCH) ] = { 1360 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1361 [ C(RESULT_ACCESS) ] = 0x01b7, 1362 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1363 [ C(RESULT_MISS) ] = 0x01b7, 1364 }, 1365 }, 1366 [ C(DTLB) ] = { 1367 [ C(OP_READ) ] = { 1368 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1369 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1370 }, 1371 [ C(OP_WRITE) ] = { 1372 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1373 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1374 }, 1375 [ C(OP_PREFETCH) ] = { 1376 [ C(RESULT_ACCESS) ] = 0x0, 1377 [ C(RESULT_MISS) ] = 0x0, 1378 }, 1379 }, 1380 [ C(ITLB) ] = { 1381 [ C(OP_READ) ] = { 1382 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1383 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1384 }, 1385 [ C(OP_WRITE) ] = { 1386 [ C(RESULT_ACCESS) ] = -1, 1387 [ C(RESULT_MISS) ] = -1, 1388 }, 1389 [ C(OP_PREFETCH) ] = { 1390 [ C(RESULT_ACCESS) ] = -1, 1391 [ C(RESULT_MISS) ] = -1, 1392 }, 1393 }, 1394 [ C(BPU ) ] = { 1395 [ C(OP_READ) ] = { 1396 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1397 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1398 }, 1399 [ C(OP_WRITE) ] = { 1400 [ C(RESULT_ACCESS) ] = -1, 1401 [ C(RESULT_MISS) ] = -1, 1402 }, 1403 [ C(OP_PREFETCH) ] = { 1404 [ C(RESULT_ACCESS) ] = -1, 1405 [ C(RESULT_MISS) ] = -1, 1406 }, 1407 }, 1408 [ C(NODE) ] = { 1409 [ C(OP_READ) ] = { 1410 [ C(RESULT_ACCESS) ] = 0x01b7, 1411 [ C(RESULT_MISS) ] = 0x01b7, 1412 }, 1413 [ C(OP_WRITE) ] = { 1414 [ C(RESULT_ACCESS) ] = 0x01b7, 1415 [ C(RESULT_MISS) ] = 0x01b7, 1416 }, 1417 [ C(OP_PREFETCH) ] = { 1418 [ C(RESULT_ACCESS) ] = 0x01b7, 1419 [ C(RESULT_MISS) ] = 0x01b7, 1420 }, 1421 }, 1422 }; 1423 1424 static __initconst const u64 core2_hw_cache_event_ids 1425 [PERF_COUNT_HW_CACHE_MAX] 1426 [PERF_COUNT_HW_CACHE_OP_MAX] 1427 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1428 { 1429 [ C(L1D) ] = { 1430 [ C(OP_READ) ] = { 1431 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1432 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1433 }, 1434 [ C(OP_WRITE) ] = { 1435 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1436 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1437 }, 1438 [ C(OP_PREFETCH) ] = { 1439 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1440 [ C(RESULT_MISS) ] = 0, 1441 }, 1442 }, 1443 [ C(L1I ) ] = { 1444 [ C(OP_READ) ] = { 1445 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1446 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1447 }, 1448 [ C(OP_WRITE) ] = { 1449 [ C(RESULT_ACCESS) ] = -1, 1450 [ C(RESULT_MISS) ] = -1, 1451 }, 1452 [ C(OP_PREFETCH) ] = { 1453 [ C(RESULT_ACCESS) ] = 0, 1454 [ C(RESULT_MISS) ] = 0, 1455 }, 1456 }, 1457 [ C(LL ) ] = { 1458 [ C(OP_READ) ] = { 1459 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1460 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1461 }, 1462 [ C(OP_WRITE) ] = { 1463 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1464 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1465 }, 1466 [ C(OP_PREFETCH) ] = { 1467 [ C(RESULT_ACCESS) ] = 0, 1468 [ C(RESULT_MISS) ] = 0, 1469 }, 1470 }, 1471 [ C(DTLB) ] = { 1472 [ C(OP_READ) ] = { 1473 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1474 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1475 }, 1476 [ C(OP_WRITE) ] = { 1477 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1478 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1479 }, 1480 [ C(OP_PREFETCH) ] = { 1481 [ C(RESULT_ACCESS) ] = 0, 1482 [ C(RESULT_MISS) ] = 0, 1483 }, 1484 }, 1485 [ C(ITLB) ] = { 1486 [ C(OP_READ) ] = { 1487 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1488 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1489 }, 1490 [ C(OP_WRITE) ] = { 1491 [ C(RESULT_ACCESS) ] = -1, 1492 [ C(RESULT_MISS) ] = -1, 1493 }, 1494 [ C(OP_PREFETCH) ] = { 1495 [ C(RESULT_ACCESS) ] = -1, 1496 [ C(RESULT_MISS) ] = -1, 1497 }, 1498 }, 1499 [ C(BPU ) ] = { 1500 [ C(OP_READ) ] = { 1501 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1502 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1503 }, 1504 [ C(OP_WRITE) ] = { 1505 [ C(RESULT_ACCESS) ] = -1, 1506 [ C(RESULT_MISS) ] = -1, 1507 }, 1508 [ C(OP_PREFETCH) ] = { 1509 [ C(RESULT_ACCESS) ] = -1, 1510 [ C(RESULT_MISS) ] = -1, 1511 }, 1512 }, 1513 }; 1514 1515 static __initconst const u64 atom_hw_cache_event_ids 1516 [PERF_COUNT_HW_CACHE_MAX] 1517 [PERF_COUNT_HW_CACHE_OP_MAX] 1518 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1519 { 1520 [ C(L1D) ] = { 1521 [ C(OP_READ) ] = { 1522 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1523 [ C(RESULT_MISS) ] = 0, 1524 }, 1525 [ C(OP_WRITE) ] = { 1526 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1527 [ C(RESULT_MISS) ] = 0, 1528 }, 1529 [ C(OP_PREFETCH) ] = { 1530 [ C(RESULT_ACCESS) ] = 0x0, 1531 [ C(RESULT_MISS) ] = 0, 1532 }, 1533 }, 1534 [ C(L1I ) ] = { 1535 [ C(OP_READ) ] = { 1536 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1537 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1538 }, 1539 [ C(OP_WRITE) ] = { 1540 [ C(RESULT_ACCESS) ] = -1, 1541 [ C(RESULT_MISS) ] = -1, 1542 }, 1543 [ C(OP_PREFETCH) ] = { 1544 [ C(RESULT_ACCESS) ] = 0, 1545 [ C(RESULT_MISS) ] = 0, 1546 }, 1547 }, 1548 [ C(LL ) ] = { 1549 [ C(OP_READ) ] = { 1550 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1551 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1552 }, 1553 [ C(OP_WRITE) ] = { 1554 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1555 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1556 }, 1557 [ C(OP_PREFETCH) ] = { 1558 [ C(RESULT_ACCESS) ] = 0, 1559 [ C(RESULT_MISS) ] = 0, 1560 }, 1561 }, 1562 [ C(DTLB) ] = { 1563 [ C(OP_READ) ] = { 1564 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1565 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1566 }, 1567 [ C(OP_WRITE) ] = { 1568 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1569 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1570 }, 1571 [ C(OP_PREFETCH) ] = { 1572 [ C(RESULT_ACCESS) ] = 0, 1573 [ C(RESULT_MISS) ] = 0, 1574 }, 1575 }, 1576 [ C(ITLB) ] = { 1577 [ C(OP_READ) ] = { 1578 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1579 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1580 }, 1581 [ C(OP_WRITE) ] = { 1582 [ C(RESULT_ACCESS) ] = -1, 1583 [ C(RESULT_MISS) ] = -1, 1584 }, 1585 [ C(OP_PREFETCH) ] = { 1586 [ C(RESULT_ACCESS) ] = -1, 1587 [ C(RESULT_MISS) ] = -1, 1588 }, 1589 }, 1590 [ C(BPU ) ] = { 1591 [ C(OP_READ) ] = { 1592 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1593 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1594 }, 1595 [ C(OP_WRITE) ] = { 1596 [ C(RESULT_ACCESS) ] = -1, 1597 [ C(RESULT_MISS) ] = -1, 1598 }, 1599 [ C(OP_PREFETCH) ] = { 1600 [ C(RESULT_ACCESS) ] = -1, 1601 [ C(RESULT_MISS) ] = -1, 1602 }, 1603 }, 1604 }; 1605 1606 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1607 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1608 /* no_alloc_cycles.not_delivered */ 1609 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1610 "event=0xca,umask=0x50"); 1611 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1612 /* uops_retired.all */ 1613 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1614 "event=0xc2,umask=0x10"); 1615 /* uops_retired.all */ 1616 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1617 "event=0xc2,umask=0x10"); 1618 1619 static struct attribute *slm_events_attrs[] = { 1620 EVENT_PTR(td_total_slots_slm), 1621 EVENT_PTR(td_total_slots_scale_slm), 1622 EVENT_PTR(td_fetch_bubbles_slm), 1623 EVENT_PTR(td_fetch_bubbles_scale_slm), 1624 EVENT_PTR(td_slots_issued_slm), 1625 EVENT_PTR(td_slots_retired_slm), 1626 NULL 1627 }; 1628 1629 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1630 { 1631 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1632 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1633 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1634 EVENT_EXTRA_END 1635 }; 1636 1637 #define SLM_DMND_READ SNB_DMND_DATA_RD 1638 #define SLM_DMND_WRITE SNB_DMND_RFO 1639 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1640 1641 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1642 #define SLM_LLC_ACCESS SNB_RESP_ANY 1643 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1644 1645 static __initconst const u64 slm_hw_cache_extra_regs 1646 [PERF_COUNT_HW_CACHE_MAX] 1647 [PERF_COUNT_HW_CACHE_OP_MAX] 1648 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1649 { 1650 [ C(LL ) ] = { 1651 [ C(OP_READ) ] = { 1652 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1653 [ C(RESULT_MISS) ] = 0, 1654 }, 1655 [ C(OP_WRITE) ] = { 1656 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1657 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1658 }, 1659 [ C(OP_PREFETCH) ] = { 1660 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1661 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1662 }, 1663 }, 1664 }; 1665 1666 static __initconst const u64 slm_hw_cache_event_ids 1667 [PERF_COUNT_HW_CACHE_MAX] 1668 [PERF_COUNT_HW_CACHE_OP_MAX] 1669 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1670 { 1671 [ C(L1D) ] = { 1672 [ C(OP_READ) ] = { 1673 [ C(RESULT_ACCESS) ] = 0, 1674 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1675 }, 1676 [ C(OP_WRITE) ] = { 1677 [ C(RESULT_ACCESS) ] = 0, 1678 [ C(RESULT_MISS) ] = 0, 1679 }, 1680 [ C(OP_PREFETCH) ] = { 1681 [ C(RESULT_ACCESS) ] = 0, 1682 [ C(RESULT_MISS) ] = 0, 1683 }, 1684 }, 1685 [ C(L1I ) ] = { 1686 [ C(OP_READ) ] = { 1687 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1688 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1689 }, 1690 [ C(OP_WRITE) ] = { 1691 [ C(RESULT_ACCESS) ] = -1, 1692 [ C(RESULT_MISS) ] = -1, 1693 }, 1694 [ C(OP_PREFETCH) ] = { 1695 [ C(RESULT_ACCESS) ] = 0, 1696 [ C(RESULT_MISS) ] = 0, 1697 }, 1698 }, 1699 [ C(LL ) ] = { 1700 [ C(OP_READ) ] = { 1701 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1702 [ C(RESULT_ACCESS) ] = 0x01b7, 1703 [ C(RESULT_MISS) ] = 0, 1704 }, 1705 [ C(OP_WRITE) ] = { 1706 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1707 [ C(RESULT_ACCESS) ] = 0x01b7, 1708 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1709 [ C(RESULT_MISS) ] = 0x01b7, 1710 }, 1711 [ C(OP_PREFETCH) ] = { 1712 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1713 [ C(RESULT_ACCESS) ] = 0x01b7, 1714 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1715 [ C(RESULT_MISS) ] = 0x01b7, 1716 }, 1717 }, 1718 [ C(DTLB) ] = { 1719 [ C(OP_READ) ] = { 1720 [ C(RESULT_ACCESS) ] = 0, 1721 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1722 }, 1723 [ C(OP_WRITE) ] = { 1724 [ C(RESULT_ACCESS) ] = 0, 1725 [ C(RESULT_MISS) ] = 0, 1726 }, 1727 [ C(OP_PREFETCH) ] = { 1728 [ C(RESULT_ACCESS) ] = 0, 1729 [ C(RESULT_MISS) ] = 0, 1730 }, 1731 }, 1732 [ C(ITLB) ] = { 1733 [ C(OP_READ) ] = { 1734 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1735 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1736 }, 1737 [ C(OP_WRITE) ] = { 1738 [ C(RESULT_ACCESS) ] = -1, 1739 [ C(RESULT_MISS) ] = -1, 1740 }, 1741 [ C(OP_PREFETCH) ] = { 1742 [ C(RESULT_ACCESS) ] = -1, 1743 [ C(RESULT_MISS) ] = -1, 1744 }, 1745 }, 1746 [ C(BPU ) ] = { 1747 [ C(OP_READ) ] = { 1748 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1749 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1750 }, 1751 [ C(OP_WRITE) ] = { 1752 [ C(RESULT_ACCESS) ] = -1, 1753 [ C(RESULT_MISS) ] = -1, 1754 }, 1755 [ C(OP_PREFETCH) ] = { 1756 [ C(RESULT_ACCESS) ] = -1, 1757 [ C(RESULT_MISS) ] = -1, 1758 }, 1759 }, 1760 }; 1761 1762 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1763 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1764 /* UOPS_NOT_DELIVERED.ANY */ 1765 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1766 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1767 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1768 /* UOPS_RETIRED.ANY */ 1769 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1770 /* UOPS_ISSUED.ANY */ 1771 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1772 1773 static struct attribute *glm_events_attrs[] = { 1774 EVENT_PTR(td_total_slots_glm), 1775 EVENT_PTR(td_total_slots_scale_glm), 1776 EVENT_PTR(td_fetch_bubbles_glm), 1777 EVENT_PTR(td_recovery_bubbles_glm), 1778 EVENT_PTR(td_slots_issued_glm), 1779 EVENT_PTR(td_slots_retired_glm), 1780 NULL 1781 }; 1782 1783 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1784 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1785 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1786 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1787 EVENT_EXTRA_END 1788 }; 1789 1790 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1791 #define GLM_DEMAND_RFO BIT_ULL(1) 1792 #define GLM_ANY_RESPONSE BIT_ULL(16) 1793 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1794 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1795 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1796 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1797 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1798 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1799 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1800 1801 static __initconst const u64 glm_hw_cache_event_ids 1802 [PERF_COUNT_HW_CACHE_MAX] 1803 [PERF_COUNT_HW_CACHE_OP_MAX] 1804 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1805 [C(L1D)] = { 1806 [C(OP_READ)] = { 1807 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1808 [C(RESULT_MISS)] = 0x0, 1809 }, 1810 [C(OP_WRITE)] = { 1811 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1812 [C(RESULT_MISS)] = 0x0, 1813 }, 1814 [C(OP_PREFETCH)] = { 1815 [C(RESULT_ACCESS)] = 0x0, 1816 [C(RESULT_MISS)] = 0x0, 1817 }, 1818 }, 1819 [C(L1I)] = { 1820 [C(OP_READ)] = { 1821 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1822 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1823 }, 1824 [C(OP_WRITE)] = { 1825 [C(RESULT_ACCESS)] = -1, 1826 [C(RESULT_MISS)] = -1, 1827 }, 1828 [C(OP_PREFETCH)] = { 1829 [C(RESULT_ACCESS)] = 0x0, 1830 [C(RESULT_MISS)] = 0x0, 1831 }, 1832 }, 1833 [C(LL)] = { 1834 [C(OP_READ)] = { 1835 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1836 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1837 }, 1838 [C(OP_WRITE)] = { 1839 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1840 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1841 }, 1842 [C(OP_PREFETCH)] = { 1843 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1844 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1845 }, 1846 }, 1847 [C(DTLB)] = { 1848 [C(OP_READ)] = { 1849 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1850 [C(RESULT_MISS)] = 0x0, 1851 }, 1852 [C(OP_WRITE)] = { 1853 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1854 [C(RESULT_MISS)] = 0x0, 1855 }, 1856 [C(OP_PREFETCH)] = { 1857 [C(RESULT_ACCESS)] = 0x0, 1858 [C(RESULT_MISS)] = 0x0, 1859 }, 1860 }, 1861 [C(ITLB)] = { 1862 [C(OP_READ)] = { 1863 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1864 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1865 }, 1866 [C(OP_WRITE)] = { 1867 [C(RESULT_ACCESS)] = -1, 1868 [C(RESULT_MISS)] = -1, 1869 }, 1870 [C(OP_PREFETCH)] = { 1871 [C(RESULT_ACCESS)] = -1, 1872 [C(RESULT_MISS)] = -1, 1873 }, 1874 }, 1875 [C(BPU)] = { 1876 [C(OP_READ)] = { 1877 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1878 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1879 }, 1880 [C(OP_WRITE)] = { 1881 [C(RESULT_ACCESS)] = -1, 1882 [C(RESULT_MISS)] = -1, 1883 }, 1884 [C(OP_PREFETCH)] = { 1885 [C(RESULT_ACCESS)] = -1, 1886 [C(RESULT_MISS)] = -1, 1887 }, 1888 }, 1889 }; 1890 1891 static __initconst const u64 glm_hw_cache_extra_regs 1892 [PERF_COUNT_HW_CACHE_MAX] 1893 [PERF_COUNT_HW_CACHE_OP_MAX] 1894 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1895 [C(LL)] = { 1896 [C(OP_READ)] = { 1897 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1898 GLM_LLC_ACCESS, 1899 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1900 GLM_LLC_MISS, 1901 }, 1902 [C(OP_WRITE)] = { 1903 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1904 GLM_LLC_ACCESS, 1905 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1906 GLM_LLC_MISS, 1907 }, 1908 [C(OP_PREFETCH)] = { 1909 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1910 GLM_LLC_ACCESS, 1911 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1912 GLM_LLC_MISS, 1913 }, 1914 }, 1915 }; 1916 1917 static __initconst const u64 glp_hw_cache_event_ids 1918 [PERF_COUNT_HW_CACHE_MAX] 1919 [PERF_COUNT_HW_CACHE_OP_MAX] 1920 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1921 [C(L1D)] = { 1922 [C(OP_READ)] = { 1923 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1924 [C(RESULT_MISS)] = 0x0, 1925 }, 1926 [C(OP_WRITE)] = { 1927 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1928 [C(RESULT_MISS)] = 0x0, 1929 }, 1930 [C(OP_PREFETCH)] = { 1931 [C(RESULT_ACCESS)] = 0x0, 1932 [C(RESULT_MISS)] = 0x0, 1933 }, 1934 }, 1935 [C(L1I)] = { 1936 [C(OP_READ)] = { 1937 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1938 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1939 }, 1940 [C(OP_WRITE)] = { 1941 [C(RESULT_ACCESS)] = -1, 1942 [C(RESULT_MISS)] = -1, 1943 }, 1944 [C(OP_PREFETCH)] = { 1945 [C(RESULT_ACCESS)] = 0x0, 1946 [C(RESULT_MISS)] = 0x0, 1947 }, 1948 }, 1949 [C(LL)] = { 1950 [C(OP_READ)] = { 1951 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1953 }, 1954 [C(OP_WRITE)] = { 1955 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1956 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1957 }, 1958 [C(OP_PREFETCH)] = { 1959 [C(RESULT_ACCESS)] = 0x0, 1960 [C(RESULT_MISS)] = 0x0, 1961 }, 1962 }, 1963 [C(DTLB)] = { 1964 [C(OP_READ)] = { 1965 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1966 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1967 }, 1968 [C(OP_WRITE)] = { 1969 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1970 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1971 }, 1972 [C(OP_PREFETCH)] = { 1973 [C(RESULT_ACCESS)] = 0x0, 1974 [C(RESULT_MISS)] = 0x0, 1975 }, 1976 }, 1977 [C(ITLB)] = { 1978 [C(OP_READ)] = { 1979 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1980 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1981 }, 1982 [C(OP_WRITE)] = { 1983 [C(RESULT_ACCESS)] = -1, 1984 [C(RESULT_MISS)] = -1, 1985 }, 1986 [C(OP_PREFETCH)] = { 1987 [C(RESULT_ACCESS)] = -1, 1988 [C(RESULT_MISS)] = -1, 1989 }, 1990 }, 1991 [C(BPU)] = { 1992 [C(OP_READ)] = { 1993 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1994 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1995 }, 1996 [C(OP_WRITE)] = { 1997 [C(RESULT_ACCESS)] = -1, 1998 [C(RESULT_MISS)] = -1, 1999 }, 2000 [C(OP_PREFETCH)] = { 2001 [C(RESULT_ACCESS)] = -1, 2002 [C(RESULT_MISS)] = -1, 2003 }, 2004 }, 2005 }; 2006 2007 static __initconst const u64 glp_hw_cache_extra_regs 2008 [PERF_COUNT_HW_CACHE_MAX] 2009 [PERF_COUNT_HW_CACHE_OP_MAX] 2010 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2011 [C(LL)] = { 2012 [C(OP_READ)] = { 2013 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2014 GLM_LLC_ACCESS, 2015 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2016 GLM_LLC_MISS, 2017 }, 2018 [C(OP_WRITE)] = { 2019 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2020 GLM_LLC_ACCESS, 2021 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2022 GLM_LLC_MISS, 2023 }, 2024 [C(OP_PREFETCH)] = { 2025 [C(RESULT_ACCESS)] = 0x0, 2026 [C(RESULT_MISS)] = 0x0, 2027 }, 2028 }, 2029 }; 2030 2031 #define TNT_LOCAL_DRAM BIT_ULL(26) 2032 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2033 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2034 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2035 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2036 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2037 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2038 2039 static __initconst const u64 tnt_hw_cache_extra_regs 2040 [PERF_COUNT_HW_CACHE_MAX] 2041 [PERF_COUNT_HW_CACHE_OP_MAX] 2042 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2043 [C(LL)] = { 2044 [C(OP_READ)] = { 2045 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2046 TNT_LLC_ACCESS, 2047 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2048 TNT_LLC_MISS, 2049 }, 2050 [C(OP_WRITE)] = { 2051 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2052 TNT_LLC_ACCESS, 2053 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2054 TNT_LLC_MISS, 2055 }, 2056 [C(OP_PREFETCH)] = { 2057 [C(RESULT_ACCESS)] = 0x0, 2058 [C(RESULT_MISS)] = 0x0, 2059 }, 2060 }, 2061 }; 2062 2063 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2064 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2065 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2066 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2067 2068 static struct attribute *tnt_events_attrs[] = { 2069 EVENT_PTR(td_fe_bound_tnt), 2070 EVENT_PTR(td_retiring_tnt), 2071 EVENT_PTR(td_bad_spec_tnt), 2072 EVENT_PTR(td_be_bound_tnt), 2073 NULL, 2074 }; 2075 2076 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2077 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2078 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2079 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2080 EVENT_EXTRA_END 2081 }; 2082 2083 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2084 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2085 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2086 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2087 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2088 EVENT_EXTRA_END 2089 }; 2090 2091 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2092 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2093 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2094 #define KNL_MCDRAM_FAR BIT_ULL(22) 2095 #define KNL_DDR_LOCAL BIT_ULL(23) 2096 #define KNL_DDR_FAR BIT_ULL(24) 2097 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2098 KNL_DDR_LOCAL | KNL_DDR_FAR) 2099 #define KNL_L2_READ SLM_DMND_READ 2100 #define KNL_L2_WRITE SLM_DMND_WRITE 2101 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2102 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2103 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2104 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2105 SNB_NON_DRAM) 2106 2107 static __initconst const u64 knl_hw_cache_extra_regs 2108 [PERF_COUNT_HW_CACHE_MAX] 2109 [PERF_COUNT_HW_CACHE_OP_MAX] 2110 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2111 [C(LL)] = { 2112 [C(OP_READ)] = { 2113 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2114 [C(RESULT_MISS)] = 0, 2115 }, 2116 [C(OP_WRITE)] = { 2117 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2118 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2119 }, 2120 [C(OP_PREFETCH)] = { 2121 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2122 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2123 }, 2124 }, 2125 }; 2126 2127 /* 2128 * Used from PMIs where the LBRs are already disabled. 2129 * 2130 * This function could be called consecutively. It is required to remain in 2131 * disabled state if called consecutively. 2132 * 2133 * During consecutive calls, the same disable value will be written to related 2134 * registers, so the PMU state remains unchanged. 2135 * 2136 * intel_bts events don't coexist with intel PMU's BTS events because of 2137 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2138 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2139 * 2140 * Avoid PEBS_ENABLE MSR access in PMIs. 2141 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2142 * It doesn't matter if the PEBS is enabled or not. 2143 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2144 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2145 * However, there are some cases which may change PEBS status, e.g. PMI 2146 * throttle. The PEBS_ENABLE should be updated where the status changes. 2147 */ 2148 static __always_inline void __intel_pmu_disable_all(bool bts) 2149 { 2150 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2151 2152 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2153 2154 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2155 intel_pmu_disable_bts(); 2156 } 2157 2158 static __always_inline void intel_pmu_disable_all(void) 2159 { 2160 __intel_pmu_disable_all(true); 2161 intel_pmu_pebs_disable_all(); 2162 intel_pmu_lbr_disable_all(); 2163 } 2164 2165 static void __intel_pmu_enable_all(int added, bool pmi) 2166 { 2167 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2168 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2169 2170 intel_pmu_lbr_enable_all(pmi); 2171 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2172 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2173 2174 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2175 struct perf_event *event = 2176 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2177 2178 if (WARN_ON_ONCE(!event)) 2179 return; 2180 2181 intel_pmu_enable_bts(event->hw.config); 2182 } 2183 } 2184 2185 static void intel_pmu_enable_all(int added) 2186 { 2187 intel_pmu_pebs_enable_all(); 2188 __intel_pmu_enable_all(added, false); 2189 } 2190 2191 static noinline int 2192 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2193 unsigned int cnt, unsigned long flags) 2194 { 2195 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2196 2197 intel_pmu_lbr_read(); 2198 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2199 2200 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2201 intel_pmu_enable_all(0); 2202 local_irq_restore(flags); 2203 return cnt; 2204 } 2205 2206 static int 2207 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2208 { 2209 unsigned long flags; 2210 2211 /* must not have branches... */ 2212 local_irq_save(flags); 2213 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2214 __intel_pmu_pebs_disable_all(); 2215 __intel_pmu_lbr_disable(); 2216 /* ... until here */ 2217 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2218 } 2219 2220 static int 2221 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2222 { 2223 unsigned long flags; 2224 2225 /* must not have branches... */ 2226 local_irq_save(flags); 2227 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2228 __intel_pmu_pebs_disable_all(); 2229 __intel_pmu_arch_lbr_disable(); 2230 /* ... until here */ 2231 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2232 } 2233 2234 /* 2235 * Workaround for: 2236 * Intel Errata AAK100 (model 26) 2237 * Intel Errata AAP53 (model 30) 2238 * Intel Errata BD53 (model 44) 2239 * 2240 * The official story: 2241 * These chips need to be 'reset' when adding counters by programming the 2242 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2243 * in sequence on the same PMC or on different PMCs. 2244 * 2245 * In practice it appears some of these events do in fact count, and 2246 * we need to program all 4 events. 2247 */ 2248 static void intel_pmu_nhm_workaround(void) 2249 { 2250 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2251 static const unsigned long nhm_magic[4] = { 2252 0x4300B5, 2253 0x4300D2, 2254 0x4300B1, 2255 0x4300B1 2256 }; 2257 struct perf_event *event; 2258 int i; 2259 2260 /* 2261 * The Errata requires below steps: 2262 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2263 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2264 * the corresponding PMCx; 2265 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2266 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2267 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2268 */ 2269 2270 /* 2271 * The real steps we choose are a little different from above. 2272 * A) To reduce MSR operations, we don't run step 1) as they 2273 * are already cleared before this function is called; 2274 * B) Call x86_perf_event_update to save PMCx before configuring 2275 * PERFEVTSELx with magic number; 2276 * C) With step 5), we do clear only when the PERFEVTSELx is 2277 * not used currently. 2278 * D) Call x86_perf_event_set_period to restore PMCx; 2279 */ 2280 2281 /* We always operate 4 pairs of PERF Counters */ 2282 for (i = 0; i < 4; i++) { 2283 event = cpuc->events[i]; 2284 if (event) 2285 x86_perf_event_update(event); 2286 } 2287 2288 for (i = 0; i < 4; i++) { 2289 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2290 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2291 } 2292 2293 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2294 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2295 2296 for (i = 0; i < 4; i++) { 2297 event = cpuc->events[i]; 2298 2299 if (event) { 2300 x86_perf_event_set_period(event); 2301 __x86_pmu_enable_event(&event->hw, 2302 ARCH_PERFMON_EVENTSEL_ENABLE); 2303 } else 2304 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2305 } 2306 } 2307 2308 static void intel_pmu_nhm_enable_all(int added) 2309 { 2310 if (added) 2311 intel_pmu_nhm_workaround(); 2312 intel_pmu_enable_all(added); 2313 } 2314 2315 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2316 { 2317 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2318 2319 if (cpuc->tfa_shadow != val) { 2320 cpuc->tfa_shadow = val; 2321 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2322 } 2323 } 2324 2325 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2326 { 2327 /* 2328 * We're going to use PMC3, make sure TFA is set before we touch it. 2329 */ 2330 if (cntr == 3) 2331 intel_set_tfa(cpuc, true); 2332 } 2333 2334 static void intel_tfa_pmu_enable_all(int added) 2335 { 2336 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2337 2338 /* 2339 * If we find PMC3 is no longer used when we enable the PMU, we can 2340 * clear TFA. 2341 */ 2342 if (!test_bit(3, cpuc->active_mask)) 2343 intel_set_tfa(cpuc, false); 2344 2345 intel_pmu_enable_all(added); 2346 } 2347 2348 static inline u64 intel_pmu_get_status(void) 2349 { 2350 u64 status; 2351 2352 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2353 2354 return status; 2355 } 2356 2357 static inline void intel_pmu_ack_status(u64 ack) 2358 { 2359 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2360 } 2361 2362 static inline bool event_is_checkpointed(struct perf_event *event) 2363 { 2364 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2365 } 2366 2367 static inline void intel_set_masks(struct perf_event *event, int idx) 2368 { 2369 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2370 2371 if (event->attr.exclude_host) 2372 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2373 if (event->attr.exclude_guest) 2374 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2375 if (event_is_checkpointed(event)) 2376 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2377 } 2378 2379 static inline void intel_clear_masks(struct perf_event *event, int idx) 2380 { 2381 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2382 2383 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2384 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2385 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2386 } 2387 2388 static void intel_pmu_disable_fixed(struct perf_event *event) 2389 { 2390 struct hw_perf_event *hwc = &event->hw; 2391 u64 ctrl_val, mask; 2392 int idx = hwc->idx; 2393 2394 if (is_topdown_idx(idx)) { 2395 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2396 2397 /* 2398 * When there are other active TopDown events, 2399 * don't disable the fixed counter 3. 2400 */ 2401 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2402 return; 2403 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2404 } 2405 2406 intel_clear_masks(event, idx); 2407 2408 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2409 rdmsrl(hwc->config_base, ctrl_val); 2410 ctrl_val &= ~mask; 2411 wrmsrl(hwc->config_base, ctrl_val); 2412 } 2413 2414 static void intel_pmu_disable_event(struct perf_event *event) 2415 { 2416 struct hw_perf_event *hwc = &event->hw; 2417 int idx = hwc->idx; 2418 2419 switch (idx) { 2420 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2421 intel_clear_masks(event, idx); 2422 x86_pmu_disable_event(event); 2423 break; 2424 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2425 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2426 intel_pmu_disable_fixed(event); 2427 break; 2428 case INTEL_PMC_IDX_FIXED_BTS: 2429 intel_pmu_disable_bts(); 2430 intel_pmu_drain_bts_buffer(); 2431 return; 2432 case INTEL_PMC_IDX_FIXED_VLBR: 2433 intel_clear_masks(event, idx); 2434 break; 2435 default: 2436 intel_clear_masks(event, idx); 2437 pr_warn("Failed to disable the event with invalid index %d\n", 2438 idx); 2439 return; 2440 } 2441 2442 /* 2443 * Needs to be called after x86_pmu_disable_event, 2444 * so we don't trigger the event without PEBS bit set. 2445 */ 2446 if (unlikely(event->attr.precise_ip)) 2447 intel_pmu_pebs_disable(event); 2448 } 2449 2450 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2451 { 2452 if (is_pebs_pt(event)) 2453 perf_report_aux_output_id(event, idx); 2454 } 2455 2456 static void intel_pmu_del_event(struct perf_event *event) 2457 { 2458 if (needs_branch_stack(event)) 2459 intel_pmu_lbr_del(event); 2460 if (event->attr.precise_ip) 2461 intel_pmu_pebs_del(event); 2462 } 2463 2464 static int icl_set_topdown_event_period(struct perf_event *event) 2465 { 2466 struct hw_perf_event *hwc = &event->hw; 2467 s64 left = local64_read(&hwc->period_left); 2468 2469 /* 2470 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2471 * Software should start both registers, PERF_METRICS and fixed 2472 * counter 3, from zero. 2473 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2474 * After that, both MSRs will be cleared for each read. 2475 * Don't need to clear them again. 2476 */ 2477 if (left == x86_pmu.max_period) { 2478 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2479 wrmsrl(MSR_PERF_METRICS, 0); 2480 hwc->saved_slots = 0; 2481 hwc->saved_metric = 0; 2482 } 2483 2484 if ((hwc->saved_slots) && is_slots_event(event)) { 2485 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2486 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2487 } 2488 2489 perf_event_update_userpage(event); 2490 2491 return 0; 2492 } 2493 2494 static int adl_set_topdown_event_period(struct perf_event *event) 2495 { 2496 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2497 2498 if (pmu->cpu_type != hybrid_big) 2499 return 0; 2500 2501 return icl_set_topdown_event_period(event); 2502 } 2503 2504 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2505 { 2506 u32 val; 2507 2508 /* 2509 * The metric is reported as an 8bit integer fraction 2510 * summing up to 0xff. 2511 * slots-in-metric = (Metric / 0xff) * slots 2512 */ 2513 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2514 return mul_u64_u32_div(slots, val, 0xff); 2515 } 2516 2517 static u64 icl_get_topdown_value(struct perf_event *event, 2518 u64 slots, u64 metrics) 2519 { 2520 int idx = event->hw.idx; 2521 u64 delta; 2522 2523 if (is_metric_idx(idx)) 2524 delta = icl_get_metrics_event_value(metrics, slots, idx); 2525 else 2526 delta = slots; 2527 2528 return delta; 2529 } 2530 2531 static void __icl_update_topdown_event(struct perf_event *event, 2532 u64 slots, u64 metrics, 2533 u64 last_slots, u64 last_metrics) 2534 { 2535 u64 delta, last = 0; 2536 2537 delta = icl_get_topdown_value(event, slots, metrics); 2538 if (last_slots) 2539 last = icl_get_topdown_value(event, last_slots, last_metrics); 2540 2541 /* 2542 * The 8bit integer fraction of metric may be not accurate, 2543 * especially when the changes is very small. 2544 * For example, if only a few bad_spec happens, the fraction 2545 * may be reduced from 1 to 0. If so, the bad_spec event value 2546 * will be 0 which is definitely less than the last value. 2547 * Avoid update event->count for this case. 2548 */ 2549 if (delta > last) { 2550 delta -= last; 2551 local64_add(delta, &event->count); 2552 } 2553 } 2554 2555 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2556 u64 metrics, int metric_end) 2557 { 2558 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2559 struct perf_event *other; 2560 int idx; 2561 2562 event->hw.saved_slots = slots; 2563 event->hw.saved_metric = metrics; 2564 2565 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2566 if (!is_topdown_idx(idx)) 2567 continue; 2568 other = cpuc->events[idx]; 2569 other->hw.saved_slots = slots; 2570 other->hw.saved_metric = metrics; 2571 } 2572 } 2573 2574 /* 2575 * Update all active Topdown events. 2576 * 2577 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2578 * modify by a NMI. PMU has to be disabled before calling this function. 2579 */ 2580 2581 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2582 { 2583 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2584 struct perf_event *other; 2585 u64 slots, metrics; 2586 bool reset = true; 2587 int idx; 2588 2589 /* read Fixed counter 3 */ 2590 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2591 if (!slots) 2592 return 0; 2593 2594 /* read PERF_METRICS */ 2595 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2596 2597 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2598 if (!is_topdown_idx(idx)) 2599 continue; 2600 other = cpuc->events[idx]; 2601 __icl_update_topdown_event(other, slots, metrics, 2602 event ? event->hw.saved_slots : 0, 2603 event ? event->hw.saved_metric : 0); 2604 } 2605 2606 /* 2607 * Check and update this event, which may have been cleared 2608 * in active_mask e.g. x86_pmu_stop() 2609 */ 2610 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2611 __icl_update_topdown_event(event, slots, metrics, 2612 event->hw.saved_slots, 2613 event->hw.saved_metric); 2614 2615 /* 2616 * In x86_pmu_stop(), the event is cleared in active_mask first, 2617 * then drain the delta, which indicates context switch for 2618 * counting. 2619 * Save metric and slots for context switch. 2620 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2621 * Because the values will be restored in next schedule in. 2622 */ 2623 update_saved_topdown_regs(event, slots, metrics, metric_end); 2624 reset = false; 2625 } 2626 2627 if (reset) { 2628 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2629 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2630 wrmsrl(MSR_PERF_METRICS, 0); 2631 if (event) 2632 update_saved_topdown_regs(event, 0, 0, metric_end); 2633 } 2634 2635 return slots; 2636 } 2637 2638 static u64 icl_update_topdown_event(struct perf_event *event) 2639 { 2640 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2641 x86_pmu.num_topdown_events - 1); 2642 } 2643 2644 static u64 adl_update_topdown_event(struct perf_event *event) 2645 { 2646 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2647 2648 if (pmu->cpu_type != hybrid_big) 2649 return 0; 2650 2651 return icl_update_topdown_event(event); 2652 } 2653 2654 2655 static void intel_pmu_read_topdown_event(struct perf_event *event) 2656 { 2657 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2658 2659 /* Only need to call update_topdown_event() once for group read. */ 2660 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2661 !is_slots_event(event)) 2662 return; 2663 2664 perf_pmu_disable(event->pmu); 2665 x86_pmu.update_topdown_event(event); 2666 perf_pmu_enable(event->pmu); 2667 } 2668 2669 static void intel_pmu_read_event(struct perf_event *event) 2670 { 2671 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2672 intel_pmu_auto_reload_read(event); 2673 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 2674 intel_pmu_read_topdown_event(event); 2675 else 2676 x86_perf_event_update(event); 2677 } 2678 2679 static void intel_pmu_enable_fixed(struct perf_event *event) 2680 { 2681 struct hw_perf_event *hwc = &event->hw; 2682 u64 ctrl_val, mask, bits = 0; 2683 int idx = hwc->idx; 2684 2685 if (is_topdown_idx(idx)) { 2686 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2687 /* 2688 * When there are other active TopDown events, 2689 * don't enable the fixed counter 3 again. 2690 */ 2691 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2692 return; 2693 2694 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2695 } 2696 2697 intel_set_masks(event, idx); 2698 2699 /* 2700 * Enable IRQ generation (0x8), if not PEBS, 2701 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2702 * if requested: 2703 */ 2704 if (!event->attr.precise_ip) 2705 bits |= 0x8; 2706 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2707 bits |= 0x2; 2708 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2709 bits |= 0x1; 2710 2711 /* 2712 * ANY bit is supported in v3 and up 2713 */ 2714 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2715 bits |= 0x4; 2716 2717 idx -= INTEL_PMC_IDX_FIXED; 2718 bits <<= (idx * 4); 2719 mask = 0xfULL << (idx * 4); 2720 2721 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2722 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2723 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2724 } 2725 2726 rdmsrl(hwc->config_base, ctrl_val); 2727 ctrl_val &= ~mask; 2728 ctrl_val |= bits; 2729 wrmsrl(hwc->config_base, ctrl_val); 2730 } 2731 2732 static void intel_pmu_enable_event(struct perf_event *event) 2733 { 2734 struct hw_perf_event *hwc = &event->hw; 2735 int idx = hwc->idx; 2736 2737 if (unlikely(event->attr.precise_ip)) 2738 intel_pmu_pebs_enable(event); 2739 2740 switch (idx) { 2741 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2742 intel_set_masks(event, idx); 2743 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2744 break; 2745 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2746 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2747 intel_pmu_enable_fixed(event); 2748 break; 2749 case INTEL_PMC_IDX_FIXED_BTS: 2750 if (!__this_cpu_read(cpu_hw_events.enabled)) 2751 return; 2752 intel_pmu_enable_bts(hwc->config); 2753 break; 2754 case INTEL_PMC_IDX_FIXED_VLBR: 2755 intel_set_masks(event, idx); 2756 break; 2757 default: 2758 pr_warn("Failed to enable the event with invalid index %d\n", 2759 idx); 2760 } 2761 } 2762 2763 static void intel_pmu_add_event(struct perf_event *event) 2764 { 2765 if (event->attr.precise_ip) 2766 intel_pmu_pebs_add(event); 2767 if (needs_branch_stack(event)) 2768 intel_pmu_lbr_add(event); 2769 } 2770 2771 /* 2772 * Save and restart an expired event. Called by NMI contexts, 2773 * so it has to be careful about preempting normal event ops: 2774 */ 2775 int intel_pmu_save_and_restart(struct perf_event *event) 2776 { 2777 x86_perf_event_update(event); 2778 /* 2779 * For a checkpointed counter always reset back to 0. This 2780 * avoids a situation where the counter overflows, aborts the 2781 * transaction and is then set back to shortly before the 2782 * overflow, and overflows and aborts again. 2783 */ 2784 if (unlikely(event_is_checkpointed(event))) { 2785 /* No race with NMIs because the counter should not be armed */ 2786 wrmsrl(event->hw.event_base, 0); 2787 local64_set(&event->hw.prev_count, 0); 2788 } 2789 return x86_perf_event_set_period(event); 2790 } 2791 2792 static void intel_pmu_reset(void) 2793 { 2794 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2795 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2796 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2797 int num_counters = hybrid(cpuc->pmu, num_counters); 2798 unsigned long flags; 2799 int idx; 2800 2801 if (!num_counters) 2802 return; 2803 2804 local_irq_save(flags); 2805 2806 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2807 2808 for (idx = 0; idx < num_counters; idx++) { 2809 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2810 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2811 } 2812 for (idx = 0; idx < num_counters_fixed; idx++) { 2813 if (fixed_counter_disabled(idx, cpuc->pmu)) 2814 continue; 2815 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2816 } 2817 2818 if (ds) 2819 ds->bts_index = ds->bts_buffer_base; 2820 2821 /* Ack all overflows and disable fixed counters */ 2822 if (x86_pmu.version >= 2) { 2823 intel_pmu_ack_status(intel_pmu_get_status()); 2824 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2825 } 2826 2827 /* Reset LBRs and LBR freezing */ 2828 if (x86_pmu.lbr_nr) { 2829 update_debugctlmsr(get_debugctlmsr() & 2830 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2831 } 2832 2833 local_irq_restore(flags); 2834 } 2835 2836 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2837 { 2838 struct perf_sample_data data; 2839 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2840 int bit; 2841 int handled = 0; 2842 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2843 2844 inc_irq_stat(apic_perf_irqs); 2845 2846 /* 2847 * Ignore a range of extra bits in status that do not indicate 2848 * overflow by themselves. 2849 */ 2850 status &= ~(GLOBAL_STATUS_COND_CHG | 2851 GLOBAL_STATUS_ASIF | 2852 GLOBAL_STATUS_LBRS_FROZEN); 2853 if (!status) 2854 return 0; 2855 /* 2856 * In case multiple PEBS events are sampled at the same time, 2857 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2858 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2859 * having their bits set in the status register. This is a sign 2860 * that there was at least one PEBS record pending at the time 2861 * of the PMU interrupt. PEBS counters must only be processed 2862 * via the drain_pebs() calls and not via the regular sample 2863 * processing loop coming after that the function, otherwise 2864 * phony regular samples may be generated in the sampling buffer 2865 * not marked with the EXACT tag. Another possibility is to have 2866 * one PEBS event and at least one non-PEBS event which overflows 2867 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2868 * not be set, yet the overflow status bit for the PEBS counter will 2869 * be on Skylake. 2870 * 2871 * To avoid this problem, we systematically ignore the PEBS-enabled 2872 * counters from the GLOBAL_STATUS mask and we always process PEBS 2873 * events via drain_pebs(). 2874 */ 2875 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2876 status &= ~cpuc->pebs_enabled; 2877 else 2878 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2879 2880 /* 2881 * PEBS overflow sets bit 62 in the global status register 2882 */ 2883 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2884 u64 pebs_enabled = cpuc->pebs_enabled; 2885 2886 handled++; 2887 x86_pmu.drain_pebs(regs, &data); 2888 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2889 2890 /* 2891 * PMI throttle may be triggered, which stops the PEBS event. 2892 * Although cpuc->pebs_enabled is updated accordingly, the 2893 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2894 * cpuc->enabled has been forced to 0 in PMI. 2895 * Update the MSR if pebs_enabled is changed. 2896 */ 2897 if (pebs_enabled != cpuc->pebs_enabled) 2898 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2899 } 2900 2901 /* 2902 * Intel PT 2903 */ 2904 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2905 handled++; 2906 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 2907 perf_guest_cbs->handle_intel_pt_intr)) 2908 perf_guest_cbs->handle_intel_pt_intr(); 2909 else 2910 intel_pt_interrupt(); 2911 } 2912 2913 /* 2914 * Intel Perf metrics 2915 */ 2916 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 2917 handled++; 2918 if (x86_pmu.update_topdown_event) 2919 x86_pmu.update_topdown_event(NULL); 2920 } 2921 2922 /* 2923 * Checkpointed counters can lead to 'spurious' PMIs because the 2924 * rollback caused by the PMI will have cleared the overflow status 2925 * bit. Therefore always force probe these counters. 2926 */ 2927 status |= cpuc->intel_cp_status; 2928 2929 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2930 struct perf_event *event = cpuc->events[bit]; 2931 2932 handled++; 2933 2934 if (!test_bit(bit, cpuc->active_mask)) 2935 continue; 2936 2937 if (!intel_pmu_save_and_restart(event)) 2938 continue; 2939 2940 perf_sample_data_init(&data, 0, event->hw.last_period); 2941 2942 if (has_branch_stack(event)) 2943 data.br_stack = &cpuc->lbr_stack; 2944 2945 if (perf_event_overflow(event, &data, regs)) 2946 x86_pmu_stop(event, 0); 2947 } 2948 2949 return handled; 2950 } 2951 2952 /* 2953 * This handler is triggered by the local APIC, so the APIC IRQ handling 2954 * rules apply: 2955 */ 2956 static int intel_pmu_handle_irq(struct pt_regs *regs) 2957 { 2958 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2959 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 2960 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 2961 int loops; 2962 u64 status; 2963 int handled; 2964 int pmu_enabled; 2965 2966 /* 2967 * Save the PMU state. 2968 * It needs to be restored when leaving the handler. 2969 */ 2970 pmu_enabled = cpuc->enabled; 2971 /* 2972 * In general, the early ACK is only applied for old platforms. 2973 * For the big core starts from Haswell, the late ACK should be 2974 * applied. 2975 * For the small core after Tremont, we have to do the ACK right 2976 * before re-enabling counters, which is in the middle of the 2977 * NMI handler. 2978 */ 2979 if (!late_ack && !mid_ack) 2980 apic_write(APIC_LVTPC, APIC_DM_NMI); 2981 intel_bts_disable_local(); 2982 cpuc->enabled = 0; 2983 __intel_pmu_disable_all(true); 2984 handled = intel_pmu_drain_bts_buffer(); 2985 handled += intel_bts_interrupt(); 2986 status = intel_pmu_get_status(); 2987 if (!status) 2988 goto done; 2989 2990 loops = 0; 2991 again: 2992 intel_pmu_lbr_read(); 2993 intel_pmu_ack_status(status); 2994 if (++loops > 100) { 2995 static bool warned; 2996 2997 if (!warned) { 2998 WARN(1, "perfevents: irq loop stuck!\n"); 2999 perf_event_print_debug(); 3000 warned = true; 3001 } 3002 intel_pmu_reset(); 3003 goto done; 3004 } 3005 3006 handled += handle_pmi_common(regs, status); 3007 3008 /* 3009 * Repeat if there is more work to be done: 3010 */ 3011 status = intel_pmu_get_status(); 3012 if (status) 3013 goto again; 3014 3015 done: 3016 if (mid_ack) 3017 apic_write(APIC_LVTPC, APIC_DM_NMI); 3018 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3019 cpuc->enabled = pmu_enabled; 3020 if (pmu_enabled) 3021 __intel_pmu_enable_all(0, true); 3022 intel_bts_enable_local(); 3023 3024 /* 3025 * Only unmask the NMI after the overflow counters 3026 * have been reset. This avoids spurious NMIs on 3027 * Haswell CPUs. 3028 */ 3029 if (late_ack) 3030 apic_write(APIC_LVTPC, APIC_DM_NMI); 3031 return handled; 3032 } 3033 3034 static struct event_constraint * 3035 intel_bts_constraints(struct perf_event *event) 3036 { 3037 if (unlikely(intel_pmu_has_bts(event))) 3038 return &bts_constraint; 3039 3040 return NULL; 3041 } 3042 3043 /* 3044 * Note: matches a fake event, like Fixed2. 3045 */ 3046 static struct event_constraint * 3047 intel_vlbr_constraints(struct perf_event *event) 3048 { 3049 struct event_constraint *c = &vlbr_constraint; 3050 3051 if (unlikely(constraint_match(c, event->hw.config))) { 3052 event->hw.flags |= c->flags; 3053 return c; 3054 } 3055 3056 return NULL; 3057 } 3058 3059 static int intel_alt_er(struct cpu_hw_events *cpuc, 3060 int idx, u64 config) 3061 { 3062 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3063 int alt_idx = idx; 3064 3065 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3066 return idx; 3067 3068 if (idx == EXTRA_REG_RSP_0) 3069 alt_idx = EXTRA_REG_RSP_1; 3070 3071 if (idx == EXTRA_REG_RSP_1) 3072 alt_idx = EXTRA_REG_RSP_0; 3073 3074 if (config & ~extra_regs[alt_idx].valid_mask) 3075 return idx; 3076 3077 return alt_idx; 3078 } 3079 3080 static void intel_fixup_er(struct perf_event *event, int idx) 3081 { 3082 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3083 event->hw.extra_reg.idx = idx; 3084 3085 if (idx == EXTRA_REG_RSP_0) { 3086 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3087 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3088 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3089 } else if (idx == EXTRA_REG_RSP_1) { 3090 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3091 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3092 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3093 } 3094 } 3095 3096 /* 3097 * manage allocation of shared extra msr for certain events 3098 * 3099 * sharing can be: 3100 * per-cpu: to be shared between the various events on a single PMU 3101 * per-core: per-cpu + shared by HT threads 3102 */ 3103 static struct event_constraint * 3104 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3105 struct perf_event *event, 3106 struct hw_perf_event_extra *reg) 3107 { 3108 struct event_constraint *c = &emptyconstraint; 3109 struct er_account *era; 3110 unsigned long flags; 3111 int idx = reg->idx; 3112 3113 /* 3114 * reg->alloc can be set due to existing state, so for fake cpuc we 3115 * need to ignore this, otherwise we might fail to allocate proper fake 3116 * state for this extra reg constraint. Also see the comment below. 3117 */ 3118 if (reg->alloc && !cpuc->is_fake) 3119 return NULL; /* call x86_get_event_constraint() */ 3120 3121 again: 3122 era = &cpuc->shared_regs->regs[idx]; 3123 /* 3124 * we use spin_lock_irqsave() to avoid lockdep issues when 3125 * passing a fake cpuc 3126 */ 3127 raw_spin_lock_irqsave(&era->lock, flags); 3128 3129 if (!atomic_read(&era->ref) || era->config == reg->config) { 3130 3131 /* 3132 * If its a fake cpuc -- as per validate_{group,event}() we 3133 * shouldn't touch event state and we can avoid doing so 3134 * since both will only call get_event_constraints() once 3135 * on each event, this avoids the need for reg->alloc. 3136 * 3137 * Not doing the ER fixup will only result in era->reg being 3138 * wrong, but since we won't actually try and program hardware 3139 * this isn't a problem either. 3140 */ 3141 if (!cpuc->is_fake) { 3142 if (idx != reg->idx) 3143 intel_fixup_er(event, idx); 3144 3145 /* 3146 * x86_schedule_events() can call get_event_constraints() 3147 * multiple times on events in the case of incremental 3148 * scheduling(). reg->alloc ensures we only do the ER 3149 * allocation once. 3150 */ 3151 reg->alloc = 1; 3152 } 3153 3154 /* lock in msr value */ 3155 era->config = reg->config; 3156 era->reg = reg->reg; 3157 3158 /* one more user */ 3159 atomic_inc(&era->ref); 3160 3161 /* 3162 * need to call x86_get_event_constraint() 3163 * to check if associated event has constraints 3164 */ 3165 c = NULL; 3166 } else { 3167 idx = intel_alt_er(cpuc, idx, reg->config); 3168 if (idx != reg->idx) { 3169 raw_spin_unlock_irqrestore(&era->lock, flags); 3170 goto again; 3171 } 3172 } 3173 raw_spin_unlock_irqrestore(&era->lock, flags); 3174 3175 return c; 3176 } 3177 3178 static void 3179 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3180 struct hw_perf_event_extra *reg) 3181 { 3182 struct er_account *era; 3183 3184 /* 3185 * Only put constraint if extra reg was actually allocated. Also takes 3186 * care of event which do not use an extra shared reg. 3187 * 3188 * Also, if this is a fake cpuc we shouldn't touch any event state 3189 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3190 * either since it'll be thrown out. 3191 */ 3192 if (!reg->alloc || cpuc->is_fake) 3193 return; 3194 3195 era = &cpuc->shared_regs->regs[reg->idx]; 3196 3197 /* one fewer user */ 3198 atomic_dec(&era->ref); 3199 3200 /* allocate again next time */ 3201 reg->alloc = 0; 3202 } 3203 3204 static struct event_constraint * 3205 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3206 struct perf_event *event) 3207 { 3208 struct event_constraint *c = NULL, *d; 3209 struct hw_perf_event_extra *xreg, *breg; 3210 3211 xreg = &event->hw.extra_reg; 3212 if (xreg->idx != EXTRA_REG_NONE) { 3213 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3214 if (c == &emptyconstraint) 3215 return c; 3216 } 3217 breg = &event->hw.branch_reg; 3218 if (breg->idx != EXTRA_REG_NONE) { 3219 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3220 if (d == &emptyconstraint) { 3221 __intel_shared_reg_put_constraints(cpuc, xreg); 3222 c = d; 3223 } 3224 } 3225 return c; 3226 } 3227 3228 struct event_constraint * 3229 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3230 struct perf_event *event) 3231 { 3232 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3233 struct event_constraint *c; 3234 3235 if (event_constraints) { 3236 for_each_event_constraint(c, event_constraints) { 3237 if (constraint_match(c, event->hw.config)) { 3238 event->hw.flags |= c->flags; 3239 return c; 3240 } 3241 } 3242 } 3243 3244 return &hybrid_var(cpuc->pmu, unconstrained); 3245 } 3246 3247 static struct event_constraint * 3248 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3249 struct perf_event *event) 3250 { 3251 struct event_constraint *c; 3252 3253 c = intel_vlbr_constraints(event); 3254 if (c) 3255 return c; 3256 3257 c = intel_bts_constraints(event); 3258 if (c) 3259 return c; 3260 3261 c = intel_shared_regs_constraints(cpuc, event); 3262 if (c) 3263 return c; 3264 3265 c = intel_pebs_constraints(event); 3266 if (c) 3267 return c; 3268 3269 return x86_get_event_constraints(cpuc, idx, event); 3270 } 3271 3272 static void 3273 intel_start_scheduling(struct cpu_hw_events *cpuc) 3274 { 3275 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3276 struct intel_excl_states *xl; 3277 int tid = cpuc->excl_thread_id; 3278 3279 /* 3280 * nothing needed if in group validation mode 3281 */ 3282 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3283 return; 3284 3285 /* 3286 * no exclusion needed 3287 */ 3288 if (WARN_ON_ONCE(!excl_cntrs)) 3289 return; 3290 3291 xl = &excl_cntrs->states[tid]; 3292 3293 xl->sched_started = true; 3294 /* 3295 * lock shared state until we are done scheduling 3296 * in stop_event_scheduling() 3297 * makes scheduling appear as a transaction 3298 */ 3299 raw_spin_lock(&excl_cntrs->lock); 3300 } 3301 3302 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3303 { 3304 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3305 struct event_constraint *c = cpuc->event_constraint[idx]; 3306 struct intel_excl_states *xl; 3307 int tid = cpuc->excl_thread_id; 3308 3309 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3310 return; 3311 3312 if (WARN_ON_ONCE(!excl_cntrs)) 3313 return; 3314 3315 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3316 return; 3317 3318 xl = &excl_cntrs->states[tid]; 3319 3320 lockdep_assert_held(&excl_cntrs->lock); 3321 3322 if (c->flags & PERF_X86_EVENT_EXCL) 3323 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3324 else 3325 xl->state[cntr] = INTEL_EXCL_SHARED; 3326 } 3327 3328 static void 3329 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3330 { 3331 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3332 struct intel_excl_states *xl; 3333 int tid = cpuc->excl_thread_id; 3334 3335 /* 3336 * nothing needed if in group validation mode 3337 */ 3338 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3339 return; 3340 /* 3341 * no exclusion needed 3342 */ 3343 if (WARN_ON_ONCE(!excl_cntrs)) 3344 return; 3345 3346 xl = &excl_cntrs->states[tid]; 3347 3348 xl->sched_started = false; 3349 /* 3350 * release shared state lock (acquired in intel_start_scheduling()) 3351 */ 3352 raw_spin_unlock(&excl_cntrs->lock); 3353 } 3354 3355 static struct event_constraint * 3356 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3357 { 3358 WARN_ON_ONCE(!cpuc->constraint_list); 3359 3360 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3361 struct event_constraint *cx; 3362 3363 /* 3364 * grab pre-allocated constraint entry 3365 */ 3366 cx = &cpuc->constraint_list[idx]; 3367 3368 /* 3369 * initialize dynamic constraint 3370 * with static constraint 3371 */ 3372 *cx = *c; 3373 3374 /* 3375 * mark constraint as dynamic 3376 */ 3377 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3378 c = cx; 3379 } 3380 3381 return c; 3382 } 3383 3384 static struct event_constraint * 3385 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3386 int idx, struct event_constraint *c) 3387 { 3388 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3389 struct intel_excl_states *xlo; 3390 int tid = cpuc->excl_thread_id; 3391 int is_excl, i, w; 3392 3393 /* 3394 * validating a group does not require 3395 * enforcing cross-thread exclusion 3396 */ 3397 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3398 return c; 3399 3400 /* 3401 * no exclusion needed 3402 */ 3403 if (WARN_ON_ONCE(!excl_cntrs)) 3404 return c; 3405 3406 /* 3407 * because we modify the constraint, we need 3408 * to make a copy. Static constraints come 3409 * from static const tables. 3410 * 3411 * only needed when constraint has not yet 3412 * been cloned (marked dynamic) 3413 */ 3414 c = dyn_constraint(cpuc, c, idx); 3415 3416 /* 3417 * From here on, the constraint is dynamic. 3418 * Either it was just allocated above, or it 3419 * was allocated during a earlier invocation 3420 * of this function 3421 */ 3422 3423 /* 3424 * state of sibling HT 3425 */ 3426 xlo = &excl_cntrs->states[tid ^ 1]; 3427 3428 /* 3429 * event requires exclusive counter access 3430 * across HT threads 3431 */ 3432 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3433 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3434 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3435 if (!cpuc->n_excl++) 3436 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3437 } 3438 3439 /* 3440 * Modify static constraint with current dynamic 3441 * state of thread 3442 * 3443 * EXCLUSIVE: sibling counter measuring exclusive event 3444 * SHARED : sibling counter measuring non-exclusive event 3445 * UNUSED : sibling counter unused 3446 */ 3447 w = c->weight; 3448 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3449 /* 3450 * exclusive event in sibling counter 3451 * our corresponding counter cannot be used 3452 * regardless of our event 3453 */ 3454 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3455 __clear_bit(i, c->idxmsk); 3456 w--; 3457 continue; 3458 } 3459 /* 3460 * if measuring an exclusive event, sibling 3461 * measuring non-exclusive, then counter cannot 3462 * be used 3463 */ 3464 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3465 __clear_bit(i, c->idxmsk); 3466 w--; 3467 continue; 3468 } 3469 } 3470 3471 /* 3472 * if we return an empty mask, then switch 3473 * back to static empty constraint to avoid 3474 * the cost of freeing later on 3475 */ 3476 if (!w) 3477 c = &emptyconstraint; 3478 3479 c->weight = w; 3480 3481 return c; 3482 } 3483 3484 static struct event_constraint * 3485 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3486 struct perf_event *event) 3487 { 3488 struct event_constraint *c1, *c2; 3489 3490 c1 = cpuc->event_constraint[idx]; 3491 3492 /* 3493 * first time only 3494 * - static constraint: no change across incremental scheduling calls 3495 * - dynamic constraint: handled by intel_get_excl_constraints() 3496 */ 3497 c2 = __intel_get_event_constraints(cpuc, idx, event); 3498 if (c1) { 3499 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3500 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3501 c1->weight = c2->weight; 3502 c2 = c1; 3503 } 3504 3505 if (cpuc->excl_cntrs) 3506 return intel_get_excl_constraints(cpuc, event, idx, c2); 3507 3508 return c2; 3509 } 3510 3511 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3512 struct perf_event *event) 3513 { 3514 struct hw_perf_event *hwc = &event->hw; 3515 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3516 int tid = cpuc->excl_thread_id; 3517 struct intel_excl_states *xl; 3518 3519 /* 3520 * nothing needed if in group validation mode 3521 */ 3522 if (cpuc->is_fake) 3523 return; 3524 3525 if (WARN_ON_ONCE(!excl_cntrs)) 3526 return; 3527 3528 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3529 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3530 if (!--cpuc->n_excl) 3531 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3532 } 3533 3534 /* 3535 * If event was actually assigned, then mark the counter state as 3536 * unused now. 3537 */ 3538 if (hwc->idx >= 0) { 3539 xl = &excl_cntrs->states[tid]; 3540 3541 /* 3542 * put_constraint may be called from x86_schedule_events() 3543 * which already has the lock held so here make locking 3544 * conditional. 3545 */ 3546 if (!xl->sched_started) 3547 raw_spin_lock(&excl_cntrs->lock); 3548 3549 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3550 3551 if (!xl->sched_started) 3552 raw_spin_unlock(&excl_cntrs->lock); 3553 } 3554 } 3555 3556 static void 3557 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3558 struct perf_event *event) 3559 { 3560 struct hw_perf_event_extra *reg; 3561 3562 reg = &event->hw.extra_reg; 3563 if (reg->idx != EXTRA_REG_NONE) 3564 __intel_shared_reg_put_constraints(cpuc, reg); 3565 3566 reg = &event->hw.branch_reg; 3567 if (reg->idx != EXTRA_REG_NONE) 3568 __intel_shared_reg_put_constraints(cpuc, reg); 3569 } 3570 3571 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3572 struct perf_event *event) 3573 { 3574 intel_put_shared_regs_event_constraints(cpuc, event); 3575 3576 /* 3577 * is PMU has exclusive counter restrictions, then 3578 * all events are subject to and must call the 3579 * put_excl_constraints() routine 3580 */ 3581 if (cpuc->excl_cntrs) 3582 intel_put_excl_constraints(cpuc, event); 3583 } 3584 3585 static void intel_pebs_aliases_core2(struct perf_event *event) 3586 { 3587 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3588 /* 3589 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3590 * (0x003c) so that we can use it with PEBS. 3591 * 3592 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3593 * PEBS capable. However we can use INST_RETIRED.ANY_P 3594 * (0x00c0), which is a PEBS capable event, to get the same 3595 * count. 3596 * 3597 * INST_RETIRED.ANY_P counts the number of cycles that retires 3598 * CNTMASK instructions. By setting CNTMASK to a value (16) 3599 * larger than the maximum number of instructions that can be 3600 * retired per cycle (4) and then inverting the condition, we 3601 * count all cycles that retire 16 or less instructions, which 3602 * is every cycle. 3603 * 3604 * Thereby we gain a PEBS capable cycle counter. 3605 */ 3606 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3607 3608 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3609 event->hw.config = alt_config; 3610 } 3611 } 3612 3613 static void intel_pebs_aliases_snb(struct perf_event *event) 3614 { 3615 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3616 /* 3617 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3618 * (0x003c) so that we can use it with PEBS. 3619 * 3620 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3621 * PEBS capable. However we can use UOPS_RETIRED.ALL 3622 * (0x01c2), which is a PEBS capable event, to get the same 3623 * count. 3624 * 3625 * UOPS_RETIRED.ALL counts the number of cycles that retires 3626 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3627 * larger than the maximum number of micro-ops that can be 3628 * retired per cycle (4) and then inverting the condition, we 3629 * count all cycles that retire 16 or less micro-ops, which 3630 * is every cycle. 3631 * 3632 * Thereby we gain a PEBS capable cycle counter. 3633 */ 3634 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3635 3636 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3637 event->hw.config = alt_config; 3638 } 3639 } 3640 3641 static void intel_pebs_aliases_precdist(struct perf_event *event) 3642 { 3643 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3644 /* 3645 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3646 * (0x003c) so that we can use it with PEBS. 3647 * 3648 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3649 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3650 * (0x01c0), which is a PEBS capable event, to get the same 3651 * count. 3652 * 3653 * The PREC_DIST event has special support to minimize sample 3654 * shadowing effects. One drawback is that it can be 3655 * only programmed on counter 1, but that seems like an 3656 * acceptable trade off. 3657 */ 3658 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3659 3660 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3661 event->hw.config = alt_config; 3662 } 3663 } 3664 3665 static void intel_pebs_aliases_ivb(struct perf_event *event) 3666 { 3667 if (event->attr.precise_ip < 3) 3668 return intel_pebs_aliases_snb(event); 3669 return intel_pebs_aliases_precdist(event); 3670 } 3671 3672 static void intel_pebs_aliases_skl(struct perf_event *event) 3673 { 3674 if (event->attr.precise_ip < 3) 3675 return intel_pebs_aliases_core2(event); 3676 return intel_pebs_aliases_precdist(event); 3677 } 3678 3679 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3680 { 3681 unsigned long flags = x86_pmu.large_pebs_flags; 3682 3683 if (event->attr.use_clockid) 3684 flags &= ~PERF_SAMPLE_TIME; 3685 if (!event->attr.exclude_kernel) 3686 flags &= ~PERF_SAMPLE_REGS_USER; 3687 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3688 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3689 return flags; 3690 } 3691 3692 static int intel_pmu_bts_config(struct perf_event *event) 3693 { 3694 struct perf_event_attr *attr = &event->attr; 3695 3696 if (unlikely(intel_pmu_has_bts(event))) { 3697 /* BTS is not supported by this architecture. */ 3698 if (!x86_pmu.bts_active) 3699 return -EOPNOTSUPP; 3700 3701 /* BTS is currently only allowed for user-mode. */ 3702 if (!attr->exclude_kernel) 3703 return -EOPNOTSUPP; 3704 3705 /* BTS is not allowed for precise events. */ 3706 if (attr->precise_ip) 3707 return -EOPNOTSUPP; 3708 3709 /* disallow bts if conflicting events are present */ 3710 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3711 return -EBUSY; 3712 3713 event->destroy = hw_perf_lbr_event_destroy; 3714 } 3715 3716 return 0; 3717 } 3718 3719 static int core_pmu_hw_config(struct perf_event *event) 3720 { 3721 int ret = x86_pmu_hw_config(event); 3722 3723 if (ret) 3724 return ret; 3725 3726 return intel_pmu_bts_config(event); 3727 } 3728 3729 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3730 ((x86_pmu.num_topdown_events - 1) << 8)) 3731 3732 static bool is_available_metric_event(struct perf_event *event) 3733 { 3734 return is_metric_event(event) && 3735 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3736 } 3737 3738 static inline bool is_mem_loads_event(struct perf_event *event) 3739 { 3740 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3741 } 3742 3743 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3744 { 3745 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3746 } 3747 3748 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3749 { 3750 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3751 return false; 3752 3753 if (is_hybrid()) 3754 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3755 3756 return true; 3757 } 3758 3759 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3760 { 3761 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3762 3763 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3764 } 3765 3766 static int intel_pmu_hw_config(struct perf_event *event) 3767 { 3768 int ret = x86_pmu_hw_config(event); 3769 3770 if (ret) 3771 return ret; 3772 3773 ret = intel_pmu_bts_config(event); 3774 if (ret) 3775 return ret; 3776 3777 if (event->attr.precise_ip) { 3778 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3779 return -EINVAL; 3780 3781 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3782 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3783 if (!(event->attr.sample_type & 3784 ~intel_pmu_large_pebs_flags(event))) { 3785 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3786 event->attach_state |= PERF_ATTACH_SCHED_CB; 3787 } 3788 } 3789 if (x86_pmu.pebs_aliases) 3790 x86_pmu.pebs_aliases(event); 3791 3792 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3793 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3794 } 3795 3796 if (needs_branch_stack(event)) { 3797 ret = intel_pmu_setup_lbr_filter(event); 3798 if (ret) 3799 return ret; 3800 event->attach_state |= PERF_ATTACH_SCHED_CB; 3801 3802 /* 3803 * BTS is set up earlier in this path, so don't account twice 3804 */ 3805 if (!unlikely(intel_pmu_has_bts(event))) { 3806 /* disallow lbr if conflicting events are present */ 3807 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3808 return -EBUSY; 3809 3810 event->destroy = hw_perf_lbr_event_destroy; 3811 } 3812 } 3813 3814 if (event->attr.aux_output) { 3815 if (!event->attr.precise_ip) 3816 return -EINVAL; 3817 3818 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3819 } 3820 3821 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3822 (event->attr.type == PERF_TYPE_HW_CACHE)) 3823 return 0; 3824 3825 /* 3826 * Config Topdown slots and metric events 3827 * 3828 * The slots event on Fixed Counter 3 can support sampling, 3829 * which will be handled normally in x86_perf_event_update(). 3830 * 3831 * Metric events don't support sampling and require being paired 3832 * with a slots event as group leader. When the slots event 3833 * is used in a metrics group, it too cannot support sampling. 3834 */ 3835 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3836 if (event->attr.config1 || event->attr.config2) 3837 return -EINVAL; 3838 3839 /* 3840 * The TopDown metrics events and slots event don't 3841 * support any filters. 3842 */ 3843 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3844 return -EINVAL; 3845 3846 if (is_available_metric_event(event)) { 3847 struct perf_event *leader = event->group_leader; 3848 3849 /* The metric events don't support sampling. */ 3850 if (is_sampling_event(event)) 3851 return -EINVAL; 3852 3853 /* The metric events require a slots group leader. */ 3854 if (!is_slots_event(leader)) 3855 return -EINVAL; 3856 3857 /* 3858 * The leader/SLOTS must not be a sampling event for 3859 * metric use; hardware requires it starts at 0 when used 3860 * in conjunction with MSR_PERF_METRICS. 3861 */ 3862 if (is_sampling_event(leader)) 3863 return -EINVAL; 3864 3865 event->event_caps |= PERF_EV_CAP_SIBLING; 3866 /* 3867 * Only once we have a METRICs sibling do we 3868 * need TopDown magic. 3869 */ 3870 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3871 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3872 } 3873 } 3874 3875 /* 3876 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3877 * doesn't function quite right. As a work-around it needs to always be 3878 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3879 * The actual count of this second event is irrelevant it just needs 3880 * to be active to make the first event function correctly. 3881 * 3882 * In a group, the auxiliary event must be in front of the load latency 3883 * event. The rule is to simplify the implementation of the check. 3884 * That's because perf cannot have a complete group at the moment. 3885 */ 3886 if (require_mem_loads_aux_event(event) && 3887 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3888 is_mem_loads_event(event)) { 3889 struct perf_event *leader = event->group_leader; 3890 struct perf_event *sibling = NULL; 3891 3892 if (!is_mem_loads_aux_event(leader)) { 3893 for_each_sibling_event(sibling, leader) { 3894 if (is_mem_loads_aux_event(sibling)) 3895 break; 3896 } 3897 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3898 return -ENODATA; 3899 } 3900 } 3901 3902 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3903 return 0; 3904 3905 if (x86_pmu.version < 3) 3906 return -EINVAL; 3907 3908 ret = perf_allow_cpu(&event->attr); 3909 if (ret) 3910 return ret; 3911 3912 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3913 3914 return 0; 3915 } 3916 3917 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3918 { 3919 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3920 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3921 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3922 3923 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3924 arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3925 arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3926 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 3927 arr[0].guest &= ~cpuc->pebs_enabled; 3928 else 3929 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 3930 *nr = 1; 3931 3932 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3933 /* 3934 * If PMU counter has PEBS enabled it is not enough to 3935 * disable counter on a guest entry since PEBS memory 3936 * write can overshoot guest entry and corrupt guest 3937 * memory. Disabling PEBS solves the problem. 3938 * 3939 * Don't do this if the CPU already enforces it. 3940 */ 3941 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3942 arr[1].host = cpuc->pebs_enabled; 3943 arr[1].guest = 0; 3944 *nr = 2; 3945 } 3946 3947 return arr; 3948 } 3949 3950 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3951 { 3952 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3953 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3954 int idx; 3955 3956 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3957 struct perf_event *event = cpuc->events[idx]; 3958 3959 arr[idx].msr = x86_pmu_config_addr(idx); 3960 arr[idx].host = arr[idx].guest = 0; 3961 3962 if (!test_bit(idx, cpuc->active_mask)) 3963 continue; 3964 3965 arr[idx].host = arr[idx].guest = 3966 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3967 3968 if (event->attr.exclude_host) 3969 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3970 else if (event->attr.exclude_guest) 3971 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3972 } 3973 3974 *nr = x86_pmu.num_counters; 3975 return arr; 3976 } 3977 3978 static void core_pmu_enable_event(struct perf_event *event) 3979 { 3980 if (!event->attr.exclude_host) 3981 x86_pmu_enable_event(event); 3982 } 3983 3984 static void core_pmu_enable_all(int added) 3985 { 3986 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3987 int idx; 3988 3989 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3990 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3991 3992 if (!test_bit(idx, cpuc->active_mask) || 3993 cpuc->events[idx]->attr.exclude_host) 3994 continue; 3995 3996 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3997 } 3998 } 3999 4000 static int hsw_hw_config(struct perf_event *event) 4001 { 4002 int ret = intel_pmu_hw_config(event); 4003 4004 if (ret) 4005 return ret; 4006 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4007 return 0; 4008 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4009 4010 /* 4011 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4012 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4013 * this combination. 4014 */ 4015 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4016 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4017 event->attr.precise_ip > 0)) 4018 return -EOPNOTSUPP; 4019 4020 if (event_is_checkpointed(event)) { 4021 /* 4022 * Sampling of checkpointed events can cause situations where 4023 * the CPU constantly aborts because of a overflow, which is 4024 * then checkpointed back and ignored. Forbid checkpointing 4025 * for sampling. 4026 * 4027 * But still allow a long sampling period, so that perf stat 4028 * from KVM works. 4029 */ 4030 if (event->attr.sample_period > 0 && 4031 event->attr.sample_period < 0x7fffffff) 4032 return -EOPNOTSUPP; 4033 } 4034 return 0; 4035 } 4036 4037 static struct event_constraint counter0_constraint = 4038 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4039 4040 static struct event_constraint counter2_constraint = 4041 EVENT_CONSTRAINT(0, 0x4, 0); 4042 4043 static struct event_constraint fixed0_constraint = 4044 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4045 4046 static struct event_constraint fixed0_counter0_constraint = 4047 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4048 4049 static struct event_constraint * 4050 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4051 struct perf_event *event) 4052 { 4053 struct event_constraint *c; 4054 4055 c = intel_get_event_constraints(cpuc, idx, event); 4056 4057 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4058 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4059 if (c->idxmsk64 & (1U << 2)) 4060 return &counter2_constraint; 4061 return &emptyconstraint; 4062 } 4063 4064 return c; 4065 } 4066 4067 static struct event_constraint * 4068 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4069 struct perf_event *event) 4070 { 4071 /* 4072 * Fixed counter 0 has less skid. 4073 * Force instruction:ppp in Fixed counter 0 4074 */ 4075 if ((event->attr.precise_ip == 3) && 4076 constraint_match(&fixed0_constraint, event->hw.config)) 4077 return &fixed0_constraint; 4078 4079 return hsw_get_event_constraints(cpuc, idx, event); 4080 } 4081 4082 static struct event_constraint * 4083 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4084 struct perf_event *event) 4085 { 4086 struct event_constraint *c; 4087 4088 c = icl_get_event_constraints(cpuc, idx, event); 4089 4090 /* 4091 * The :ppp indicates the Precise Distribution (PDist) facility, which 4092 * is only supported on the GP counter 0. If a :ppp event which is not 4093 * available on the GP counter 0, error out. 4094 * Exception: Instruction PDIR is only available on the fixed counter 0. 4095 */ 4096 if ((event->attr.precise_ip == 3) && 4097 !constraint_match(&fixed0_constraint, event->hw.config)) { 4098 if (c->idxmsk64 & BIT_ULL(0)) 4099 return &counter0_constraint; 4100 4101 return &emptyconstraint; 4102 } 4103 4104 return c; 4105 } 4106 4107 static struct event_constraint * 4108 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4109 struct perf_event *event) 4110 { 4111 struct event_constraint *c; 4112 4113 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4114 if (event->attr.precise_ip == 3) 4115 return &counter0_constraint; 4116 4117 c = intel_get_event_constraints(cpuc, idx, event); 4118 4119 return c; 4120 } 4121 4122 static struct event_constraint * 4123 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4124 struct perf_event *event) 4125 { 4126 struct event_constraint *c; 4127 4128 /* 4129 * :ppp means to do reduced skid PEBS, 4130 * which is available on PMC0 and fixed counter 0. 4131 */ 4132 if (event->attr.precise_ip == 3) { 4133 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4134 if (constraint_match(&fixed0_constraint, event->hw.config)) 4135 return &fixed0_counter0_constraint; 4136 4137 return &counter0_constraint; 4138 } 4139 4140 c = intel_get_event_constraints(cpuc, idx, event); 4141 4142 return c; 4143 } 4144 4145 static bool allow_tsx_force_abort = true; 4146 4147 static struct event_constraint * 4148 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4149 struct perf_event *event) 4150 { 4151 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4152 4153 /* 4154 * Without TFA we must not use PMC3. 4155 */ 4156 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4157 c = dyn_constraint(cpuc, c, idx); 4158 c->idxmsk64 &= ~(1ULL << 3); 4159 c->weight--; 4160 } 4161 4162 return c; 4163 } 4164 4165 static struct event_constraint * 4166 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4167 struct perf_event *event) 4168 { 4169 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4170 4171 if (pmu->cpu_type == hybrid_big) 4172 return spr_get_event_constraints(cpuc, idx, event); 4173 else if (pmu->cpu_type == hybrid_small) 4174 return tnt_get_event_constraints(cpuc, idx, event); 4175 4176 WARN_ON(1); 4177 return &emptyconstraint; 4178 } 4179 4180 static int adl_hw_config(struct perf_event *event) 4181 { 4182 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4183 4184 if (pmu->cpu_type == hybrid_big) 4185 return hsw_hw_config(event); 4186 else if (pmu->cpu_type == hybrid_small) 4187 return intel_pmu_hw_config(event); 4188 4189 WARN_ON(1); 4190 return -EOPNOTSUPP; 4191 } 4192 4193 static u8 adl_get_hybrid_cpu_type(void) 4194 { 4195 return hybrid_big; 4196 } 4197 4198 /* 4199 * Broadwell: 4200 * 4201 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4202 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4203 * the two to enforce a minimum period of 128 (the smallest value that has bits 4204 * 0-5 cleared and >= 100). 4205 * 4206 * Because of how the code in x86_perf_event_set_period() works, the truncation 4207 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4208 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4209 * 4210 * Therefore the effective (average) period matches the requested period, 4211 * despite coarser hardware granularity. 4212 */ 4213 static u64 bdw_limit_period(struct perf_event *event, u64 left) 4214 { 4215 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4216 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4217 if (left < 128) 4218 left = 128; 4219 left &= ~0x3fULL; 4220 } 4221 return left; 4222 } 4223 4224 static u64 nhm_limit_period(struct perf_event *event, u64 left) 4225 { 4226 return max(left, 32ULL); 4227 } 4228 4229 static u64 spr_limit_period(struct perf_event *event, u64 left) 4230 { 4231 if (event->attr.precise_ip == 3) 4232 return max(left, 128ULL); 4233 4234 return left; 4235 } 4236 4237 PMU_FORMAT_ATTR(event, "config:0-7" ); 4238 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4239 PMU_FORMAT_ATTR(edge, "config:18" ); 4240 PMU_FORMAT_ATTR(pc, "config:19" ); 4241 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4242 PMU_FORMAT_ATTR(inv, "config:23" ); 4243 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4244 PMU_FORMAT_ATTR(in_tx, "config:32"); 4245 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4246 4247 static struct attribute *intel_arch_formats_attr[] = { 4248 &format_attr_event.attr, 4249 &format_attr_umask.attr, 4250 &format_attr_edge.attr, 4251 &format_attr_pc.attr, 4252 &format_attr_inv.attr, 4253 &format_attr_cmask.attr, 4254 NULL, 4255 }; 4256 4257 ssize_t intel_event_sysfs_show(char *page, u64 config) 4258 { 4259 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4260 4261 return x86_event_sysfs_show(page, config, event); 4262 } 4263 4264 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4265 { 4266 struct intel_shared_regs *regs; 4267 int i; 4268 4269 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4270 GFP_KERNEL, cpu_to_node(cpu)); 4271 if (regs) { 4272 /* 4273 * initialize the locks to keep lockdep happy 4274 */ 4275 for (i = 0; i < EXTRA_REG_MAX; i++) 4276 raw_spin_lock_init(®s->regs[i].lock); 4277 4278 regs->core_id = -1; 4279 } 4280 return regs; 4281 } 4282 4283 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4284 { 4285 struct intel_excl_cntrs *c; 4286 4287 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4288 GFP_KERNEL, cpu_to_node(cpu)); 4289 if (c) { 4290 raw_spin_lock_init(&c->lock); 4291 c->core_id = -1; 4292 } 4293 return c; 4294 } 4295 4296 4297 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4298 { 4299 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4300 4301 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4302 cpuc->shared_regs = allocate_shared_regs(cpu); 4303 if (!cpuc->shared_regs) 4304 goto err; 4305 } 4306 4307 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4308 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4309 4310 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4311 if (!cpuc->constraint_list) 4312 goto err_shared_regs; 4313 } 4314 4315 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4316 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4317 if (!cpuc->excl_cntrs) 4318 goto err_constraint_list; 4319 4320 cpuc->excl_thread_id = 0; 4321 } 4322 4323 return 0; 4324 4325 err_constraint_list: 4326 kfree(cpuc->constraint_list); 4327 cpuc->constraint_list = NULL; 4328 4329 err_shared_regs: 4330 kfree(cpuc->shared_regs); 4331 cpuc->shared_regs = NULL; 4332 4333 err: 4334 return -ENOMEM; 4335 } 4336 4337 static int intel_pmu_cpu_prepare(int cpu) 4338 { 4339 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4340 } 4341 4342 static void flip_smm_bit(void *data) 4343 { 4344 unsigned long set = *(unsigned long *)data; 4345 4346 if (set > 0) { 4347 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4348 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4349 } else { 4350 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4351 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4352 } 4353 } 4354 4355 static bool init_hybrid_pmu(int cpu) 4356 { 4357 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4358 u8 cpu_type = get_this_hybrid_cpu_type(); 4359 struct x86_hybrid_pmu *pmu = NULL; 4360 int i; 4361 4362 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4363 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4364 4365 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4366 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4367 pmu = &x86_pmu.hybrid_pmu[i]; 4368 break; 4369 } 4370 } 4371 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4372 cpuc->pmu = NULL; 4373 return false; 4374 } 4375 4376 /* Only check and dump the PMU information for the first CPU */ 4377 if (!cpumask_empty(&pmu->supported_cpus)) 4378 goto end; 4379 4380 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4381 return false; 4382 4383 pr_info("%s PMU driver: ", pmu->name); 4384 4385 if (pmu->intel_cap.pebs_output_pt_available) 4386 pr_cont("PEBS-via-PT "); 4387 4388 pr_cont("\n"); 4389 4390 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4391 pmu->intel_ctrl); 4392 4393 end: 4394 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4395 cpuc->pmu = &pmu->pmu; 4396 4397 x86_pmu_update_cpu_context(&pmu->pmu, cpu); 4398 4399 return true; 4400 } 4401 4402 static void intel_pmu_cpu_starting(int cpu) 4403 { 4404 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4405 int core_id = topology_core_id(cpu); 4406 int i; 4407 4408 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4409 return; 4410 4411 init_debug_store_on_cpu(cpu); 4412 /* 4413 * Deal with CPUs that don't clear their LBRs on power-up. 4414 */ 4415 intel_pmu_lbr_reset(); 4416 4417 cpuc->lbr_sel = NULL; 4418 4419 if (x86_pmu.flags & PMU_FL_TFA) { 4420 WARN_ON_ONCE(cpuc->tfa_shadow); 4421 cpuc->tfa_shadow = ~0ULL; 4422 intel_set_tfa(cpuc, false); 4423 } 4424 4425 if (x86_pmu.version > 1) 4426 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4427 4428 /* 4429 * Disable perf metrics if any added CPU doesn't support it. 4430 * 4431 * Turn off the check for a hybrid architecture, because the 4432 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4433 * the architecture features. The perf metrics is a model-specific 4434 * feature for now. The corresponding bit should always be 0 on 4435 * a hybrid platform, e.g., Alder Lake. 4436 */ 4437 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4438 union perf_capabilities perf_cap; 4439 4440 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4441 if (!perf_cap.perf_metrics) { 4442 x86_pmu.intel_cap.perf_metrics = 0; 4443 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4444 } 4445 } 4446 4447 if (!cpuc->shared_regs) 4448 return; 4449 4450 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4451 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4452 struct intel_shared_regs *pc; 4453 4454 pc = per_cpu(cpu_hw_events, i).shared_regs; 4455 if (pc && pc->core_id == core_id) { 4456 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4457 cpuc->shared_regs = pc; 4458 break; 4459 } 4460 } 4461 cpuc->shared_regs->core_id = core_id; 4462 cpuc->shared_regs->refcnt++; 4463 } 4464 4465 if (x86_pmu.lbr_sel_map) 4466 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4467 4468 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4469 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4470 struct cpu_hw_events *sibling; 4471 struct intel_excl_cntrs *c; 4472 4473 sibling = &per_cpu(cpu_hw_events, i); 4474 c = sibling->excl_cntrs; 4475 if (c && c->core_id == core_id) { 4476 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4477 cpuc->excl_cntrs = c; 4478 if (!sibling->excl_thread_id) 4479 cpuc->excl_thread_id = 1; 4480 break; 4481 } 4482 } 4483 cpuc->excl_cntrs->core_id = core_id; 4484 cpuc->excl_cntrs->refcnt++; 4485 } 4486 } 4487 4488 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4489 { 4490 struct intel_excl_cntrs *c; 4491 4492 c = cpuc->excl_cntrs; 4493 if (c) { 4494 if (c->core_id == -1 || --c->refcnt == 0) 4495 kfree(c); 4496 cpuc->excl_cntrs = NULL; 4497 } 4498 4499 kfree(cpuc->constraint_list); 4500 cpuc->constraint_list = NULL; 4501 } 4502 4503 static void intel_pmu_cpu_dying(int cpu) 4504 { 4505 fini_debug_store_on_cpu(cpu); 4506 } 4507 4508 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4509 { 4510 struct intel_shared_regs *pc; 4511 4512 pc = cpuc->shared_regs; 4513 if (pc) { 4514 if (pc->core_id == -1 || --pc->refcnt == 0) 4515 kfree(pc); 4516 cpuc->shared_regs = NULL; 4517 } 4518 4519 free_excl_cntrs(cpuc); 4520 } 4521 4522 static void intel_pmu_cpu_dead(int cpu) 4523 { 4524 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4525 4526 intel_cpuc_finish(cpuc); 4527 4528 if (is_hybrid() && cpuc->pmu) 4529 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4530 } 4531 4532 static void intel_pmu_sched_task(struct perf_event_context *ctx, 4533 bool sched_in) 4534 { 4535 intel_pmu_pebs_sched_task(ctx, sched_in); 4536 intel_pmu_lbr_sched_task(ctx, sched_in); 4537 } 4538 4539 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4540 struct perf_event_context *next) 4541 { 4542 intel_pmu_lbr_swap_task_ctx(prev, next); 4543 } 4544 4545 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4546 { 4547 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4548 } 4549 4550 static void intel_aux_output_init(void) 4551 { 4552 /* Refer also intel_pmu_aux_output_match() */ 4553 if (x86_pmu.intel_cap.pebs_output_pt_available) 4554 x86_pmu.assign = intel_pmu_assign_event; 4555 } 4556 4557 static int intel_pmu_aux_output_match(struct perf_event *event) 4558 { 4559 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 4560 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4561 return 0; 4562 4563 return is_intel_pt_event(event); 4564 } 4565 4566 static int intel_pmu_filter_match(struct perf_event *event) 4567 { 4568 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4569 unsigned int cpu = smp_processor_id(); 4570 4571 return cpumask_test_cpu(cpu, &pmu->supported_cpus); 4572 } 4573 4574 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4575 4576 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4577 4578 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4579 4580 static struct attribute *intel_arch3_formats_attr[] = { 4581 &format_attr_event.attr, 4582 &format_attr_umask.attr, 4583 &format_attr_edge.attr, 4584 &format_attr_pc.attr, 4585 &format_attr_any.attr, 4586 &format_attr_inv.attr, 4587 &format_attr_cmask.attr, 4588 NULL, 4589 }; 4590 4591 static struct attribute *hsw_format_attr[] = { 4592 &format_attr_in_tx.attr, 4593 &format_attr_in_tx_cp.attr, 4594 &format_attr_offcore_rsp.attr, 4595 &format_attr_ldlat.attr, 4596 NULL 4597 }; 4598 4599 static struct attribute *nhm_format_attr[] = { 4600 &format_attr_offcore_rsp.attr, 4601 &format_attr_ldlat.attr, 4602 NULL 4603 }; 4604 4605 static struct attribute *slm_format_attr[] = { 4606 &format_attr_offcore_rsp.attr, 4607 NULL 4608 }; 4609 4610 static struct attribute *skl_format_attr[] = { 4611 &format_attr_frontend.attr, 4612 NULL, 4613 }; 4614 4615 static __initconst const struct x86_pmu core_pmu = { 4616 .name = "core", 4617 .handle_irq = x86_pmu_handle_irq, 4618 .disable_all = x86_pmu_disable_all, 4619 .enable_all = core_pmu_enable_all, 4620 .enable = core_pmu_enable_event, 4621 .disable = x86_pmu_disable_event, 4622 .hw_config = core_pmu_hw_config, 4623 .schedule_events = x86_schedule_events, 4624 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4625 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4626 .event_map = intel_pmu_event_map, 4627 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4628 .apic = 1, 4629 .large_pebs_flags = LARGE_PEBS_FLAGS, 4630 4631 /* 4632 * Intel PMCs cannot be accessed sanely above 32-bit width, 4633 * so we install an artificial 1<<31 period regardless of 4634 * the generic event period: 4635 */ 4636 .max_period = (1ULL<<31) - 1, 4637 .get_event_constraints = intel_get_event_constraints, 4638 .put_event_constraints = intel_put_event_constraints, 4639 .event_constraints = intel_core_event_constraints, 4640 .guest_get_msrs = core_guest_get_msrs, 4641 .format_attrs = intel_arch_formats_attr, 4642 .events_sysfs_show = intel_event_sysfs_show, 4643 4644 /* 4645 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4646 * together with PMU version 1 and thus be using core_pmu with 4647 * shared_regs. We need following callbacks here to allocate 4648 * it properly. 4649 */ 4650 .cpu_prepare = intel_pmu_cpu_prepare, 4651 .cpu_starting = intel_pmu_cpu_starting, 4652 .cpu_dying = intel_pmu_cpu_dying, 4653 .cpu_dead = intel_pmu_cpu_dead, 4654 4655 .check_period = intel_pmu_check_period, 4656 4657 .lbr_reset = intel_pmu_lbr_reset_64, 4658 .lbr_read = intel_pmu_lbr_read_64, 4659 .lbr_save = intel_pmu_lbr_save, 4660 .lbr_restore = intel_pmu_lbr_restore, 4661 }; 4662 4663 static __initconst const struct x86_pmu intel_pmu = { 4664 .name = "Intel", 4665 .handle_irq = intel_pmu_handle_irq, 4666 .disable_all = intel_pmu_disable_all, 4667 .enable_all = intel_pmu_enable_all, 4668 .enable = intel_pmu_enable_event, 4669 .disable = intel_pmu_disable_event, 4670 .add = intel_pmu_add_event, 4671 .del = intel_pmu_del_event, 4672 .read = intel_pmu_read_event, 4673 .hw_config = intel_pmu_hw_config, 4674 .schedule_events = x86_schedule_events, 4675 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4676 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4677 .event_map = intel_pmu_event_map, 4678 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4679 .apic = 1, 4680 .large_pebs_flags = LARGE_PEBS_FLAGS, 4681 /* 4682 * Intel PMCs cannot be accessed sanely above 32 bit width, 4683 * so we install an artificial 1<<31 period regardless of 4684 * the generic event period: 4685 */ 4686 .max_period = (1ULL << 31) - 1, 4687 .get_event_constraints = intel_get_event_constraints, 4688 .put_event_constraints = intel_put_event_constraints, 4689 .pebs_aliases = intel_pebs_aliases_core2, 4690 4691 .format_attrs = intel_arch3_formats_attr, 4692 .events_sysfs_show = intel_event_sysfs_show, 4693 4694 .cpu_prepare = intel_pmu_cpu_prepare, 4695 .cpu_starting = intel_pmu_cpu_starting, 4696 .cpu_dying = intel_pmu_cpu_dying, 4697 .cpu_dead = intel_pmu_cpu_dead, 4698 4699 .guest_get_msrs = intel_guest_get_msrs, 4700 .sched_task = intel_pmu_sched_task, 4701 .swap_task_ctx = intel_pmu_swap_task_ctx, 4702 4703 .check_period = intel_pmu_check_period, 4704 4705 .aux_output_match = intel_pmu_aux_output_match, 4706 4707 .lbr_reset = intel_pmu_lbr_reset_64, 4708 .lbr_read = intel_pmu_lbr_read_64, 4709 .lbr_save = intel_pmu_lbr_save, 4710 .lbr_restore = intel_pmu_lbr_restore, 4711 }; 4712 4713 static __init void intel_clovertown_quirk(void) 4714 { 4715 /* 4716 * PEBS is unreliable due to: 4717 * 4718 * AJ67 - PEBS may experience CPL leaks 4719 * AJ68 - PEBS PMI may be delayed by one event 4720 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4721 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4722 * 4723 * AJ67 could be worked around by restricting the OS/USR flags. 4724 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4725 * 4726 * AJ106 could possibly be worked around by not allowing LBR 4727 * usage from PEBS, including the fixup. 4728 * AJ68 could possibly be worked around by always programming 4729 * a pebs_event_reset[0] value and coping with the lost events. 4730 * 4731 * But taken together it might just make sense to not enable PEBS on 4732 * these chips. 4733 */ 4734 pr_warn("PEBS disabled due to CPU errata\n"); 4735 x86_pmu.pebs = 0; 4736 x86_pmu.pebs_constraints = NULL; 4737 } 4738 4739 static const struct x86_cpu_desc isolation_ucodes[] = { 4740 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4741 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 4742 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 4743 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 4744 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4745 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 4746 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 4747 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 4748 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 4749 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 4750 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 4751 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 4752 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 4753 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4754 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 4755 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 4756 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 4757 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4758 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4759 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4760 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4761 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4762 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4763 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4764 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4765 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4766 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4767 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 4768 {} 4769 }; 4770 4771 static void intel_check_pebs_isolation(void) 4772 { 4773 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4774 } 4775 4776 static __init void intel_pebs_isolation_quirk(void) 4777 { 4778 WARN_ON_ONCE(x86_pmu.check_microcode); 4779 x86_pmu.check_microcode = intel_check_pebs_isolation; 4780 intel_check_pebs_isolation(); 4781 } 4782 4783 static const struct x86_cpu_desc pebs_ucodes[] = { 4784 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4785 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4786 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4787 {} 4788 }; 4789 4790 static bool intel_snb_pebs_broken(void) 4791 { 4792 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4793 } 4794 4795 static void intel_snb_check_microcode(void) 4796 { 4797 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4798 return; 4799 4800 /* 4801 * Serialized by the microcode lock.. 4802 */ 4803 if (x86_pmu.pebs_broken) { 4804 pr_info("PEBS enabled due to microcode update\n"); 4805 x86_pmu.pebs_broken = 0; 4806 } else { 4807 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4808 x86_pmu.pebs_broken = 1; 4809 } 4810 } 4811 4812 static bool is_lbr_from(unsigned long msr) 4813 { 4814 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4815 4816 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4817 } 4818 4819 /* 4820 * Under certain circumstances, access certain MSR may cause #GP. 4821 * The function tests if the input MSR can be safely accessed. 4822 */ 4823 static bool check_msr(unsigned long msr, u64 mask) 4824 { 4825 u64 val_old, val_new, val_tmp; 4826 4827 /* 4828 * Disable the check for real HW, so we don't 4829 * mess with potentially enabled registers: 4830 */ 4831 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4832 return true; 4833 4834 /* 4835 * Read the current value, change it and read it back to see if it 4836 * matches, this is needed to detect certain hardware emulators 4837 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4838 */ 4839 if (rdmsrl_safe(msr, &val_old)) 4840 return false; 4841 4842 /* 4843 * Only change the bits which can be updated by wrmsrl. 4844 */ 4845 val_tmp = val_old ^ mask; 4846 4847 if (is_lbr_from(msr)) 4848 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4849 4850 if (wrmsrl_safe(msr, val_tmp) || 4851 rdmsrl_safe(msr, &val_new)) 4852 return false; 4853 4854 /* 4855 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4856 * should equal rdmsrl()'s even with the quirk. 4857 */ 4858 if (val_new != val_tmp) 4859 return false; 4860 4861 if (is_lbr_from(msr)) 4862 val_old = lbr_from_signext_quirk_wr(val_old); 4863 4864 /* Here it's sure that the MSR can be safely accessed. 4865 * Restore the old value and return. 4866 */ 4867 wrmsrl(msr, val_old); 4868 4869 return true; 4870 } 4871 4872 static __init void intel_sandybridge_quirk(void) 4873 { 4874 x86_pmu.check_microcode = intel_snb_check_microcode; 4875 cpus_read_lock(); 4876 intel_snb_check_microcode(); 4877 cpus_read_unlock(); 4878 } 4879 4880 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4881 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4882 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4883 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4884 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4885 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4886 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4887 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4888 }; 4889 4890 static __init void intel_arch_events_quirk(void) 4891 { 4892 int bit; 4893 4894 /* disable event that reported as not present by cpuid */ 4895 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4896 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4897 pr_warn("CPUID marked event: \'%s\' unavailable\n", 4898 intel_arch_events_map[bit].name); 4899 } 4900 } 4901 4902 static __init void intel_nehalem_quirk(void) 4903 { 4904 union cpuid10_ebx ebx; 4905 4906 ebx.full = x86_pmu.events_maskl; 4907 if (ebx.split.no_branch_misses_retired) { 4908 /* 4909 * Erratum AAJ80 detected, we work it around by using 4910 * the BR_MISP_EXEC.ANY event. This will over-count 4911 * branch-misses, but it's still much better than the 4912 * architectural event which is often completely bogus: 4913 */ 4914 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4915 ebx.split.no_branch_misses_retired = 0; 4916 x86_pmu.events_maskl = ebx.full; 4917 pr_info("CPU erratum AAJ80 worked around\n"); 4918 } 4919 } 4920 4921 /* 4922 * enable software workaround for errata: 4923 * SNB: BJ122 4924 * IVB: BV98 4925 * HSW: HSD29 4926 * 4927 * Only needed when HT is enabled. However detecting 4928 * if HT is enabled is difficult (model specific). So instead, 4929 * we enable the workaround in the early boot, and verify if 4930 * it is needed in a later initcall phase once we have valid 4931 * topology information to check if HT is actually enabled 4932 */ 4933 static __init void intel_ht_bug(void) 4934 { 4935 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4936 4937 x86_pmu.start_scheduling = intel_start_scheduling; 4938 x86_pmu.commit_scheduling = intel_commit_scheduling; 4939 x86_pmu.stop_scheduling = intel_stop_scheduling; 4940 } 4941 4942 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4943 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4944 4945 /* Haswell special events */ 4946 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4947 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4948 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4949 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4950 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4951 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4952 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4953 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4954 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4955 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4956 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4957 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4958 4959 static struct attribute *hsw_events_attrs[] = { 4960 EVENT_PTR(td_slots_issued), 4961 EVENT_PTR(td_slots_retired), 4962 EVENT_PTR(td_fetch_bubbles), 4963 EVENT_PTR(td_total_slots), 4964 EVENT_PTR(td_total_slots_scale), 4965 EVENT_PTR(td_recovery_bubbles), 4966 EVENT_PTR(td_recovery_bubbles_scale), 4967 NULL 4968 }; 4969 4970 static struct attribute *hsw_mem_events_attrs[] = { 4971 EVENT_PTR(mem_ld_hsw), 4972 EVENT_PTR(mem_st_hsw), 4973 NULL, 4974 }; 4975 4976 static struct attribute *hsw_tsx_events_attrs[] = { 4977 EVENT_PTR(tx_start), 4978 EVENT_PTR(tx_commit), 4979 EVENT_PTR(tx_abort), 4980 EVENT_PTR(tx_capacity), 4981 EVENT_PTR(tx_conflict), 4982 EVENT_PTR(el_start), 4983 EVENT_PTR(el_commit), 4984 EVENT_PTR(el_abort), 4985 EVENT_PTR(el_capacity), 4986 EVENT_PTR(el_conflict), 4987 EVENT_PTR(cycles_t), 4988 EVENT_PTR(cycles_ct), 4989 NULL 4990 }; 4991 4992 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 4993 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 4994 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 4995 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 4996 4997 static struct attribute *icl_events_attrs[] = { 4998 EVENT_PTR(mem_ld_hsw), 4999 EVENT_PTR(mem_st_hsw), 5000 NULL, 5001 }; 5002 5003 static struct attribute *icl_td_events_attrs[] = { 5004 EVENT_PTR(slots), 5005 EVENT_PTR(td_retiring), 5006 EVENT_PTR(td_bad_spec), 5007 EVENT_PTR(td_fe_bound), 5008 EVENT_PTR(td_be_bound), 5009 NULL, 5010 }; 5011 5012 static struct attribute *icl_tsx_events_attrs[] = { 5013 EVENT_PTR(tx_start), 5014 EVENT_PTR(tx_abort), 5015 EVENT_PTR(tx_commit), 5016 EVENT_PTR(tx_capacity_read), 5017 EVENT_PTR(tx_capacity_write), 5018 EVENT_PTR(tx_conflict), 5019 EVENT_PTR(el_start), 5020 EVENT_PTR(el_abort), 5021 EVENT_PTR(el_commit), 5022 EVENT_PTR(el_capacity_read), 5023 EVENT_PTR(el_capacity_write), 5024 EVENT_PTR(el_conflict), 5025 EVENT_PTR(cycles_t), 5026 EVENT_PTR(cycles_ct), 5027 NULL, 5028 }; 5029 5030 5031 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5032 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5033 5034 static struct attribute *spr_events_attrs[] = { 5035 EVENT_PTR(mem_ld_hsw), 5036 EVENT_PTR(mem_st_spr), 5037 EVENT_PTR(mem_ld_aux), 5038 NULL, 5039 }; 5040 5041 static struct attribute *spr_td_events_attrs[] = { 5042 EVENT_PTR(slots), 5043 EVENT_PTR(td_retiring), 5044 EVENT_PTR(td_bad_spec), 5045 EVENT_PTR(td_fe_bound), 5046 EVENT_PTR(td_be_bound), 5047 EVENT_PTR(td_heavy_ops), 5048 EVENT_PTR(td_br_mispredict), 5049 EVENT_PTR(td_fetch_lat), 5050 EVENT_PTR(td_mem_bound), 5051 NULL, 5052 }; 5053 5054 static struct attribute *spr_tsx_events_attrs[] = { 5055 EVENT_PTR(tx_start), 5056 EVENT_PTR(tx_abort), 5057 EVENT_PTR(tx_commit), 5058 EVENT_PTR(tx_capacity_read), 5059 EVENT_PTR(tx_capacity_write), 5060 EVENT_PTR(tx_conflict), 5061 EVENT_PTR(cycles_t), 5062 EVENT_PTR(cycles_ct), 5063 NULL, 5064 }; 5065 5066 static ssize_t freeze_on_smi_show(struct device *cdev, 5067 struct device_attribute *attr, 5068 char *buf) 5069 { 5070 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5071 } 5072 5073 static DEFINE_MUTEX(freeze_on_smi_mutex); 5074 5075 static ssize_t freeze_on_smi_store(struct device *cdev, 5076 struct device_attribute *attr, 5077 const char *buf, size_t count) 5078 { 5079 unsigned long val; 5080 ssize_t ret; 5081 5082 ret = kstrtoul(buf, 0, &val); 5083 if (ret) 5084 return ret; 5085 5086 if (val > 1) 5087 return -EINVAL; 5088 5089 mutex_lock(&freeze_on_smi_mutex); 5090 5091 if (x86_pmu.attr_freeze_on_smi == val) 5092 goto done; 5093 5094 x86_pmu.attr_freeze_on_smi = val; 5095 5096 cpus_read_lock(); 5097 on_each_cpu(flip_smm_bit, &val, 1); 5098 cpus_read_unlock(); 5099 done: 5100 mutex_unlock(&freeze_on_smi_mutex); 5101 5102 return count; 5103 } 5104 5105 static void update_tfa_sched(void *ignored) 5106 { 5107 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5108 5109 /* 5110 * check if PMC3 is used 5111 * and if so force schedule out for all event types all contexts 5112 */ 5113 if (test_bit(3, cpuc->active_mask)) 5114 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5115 } 5116 5117 static ssize_t show_sysctl_tfa(struct device *cdev, 5118 struct device_attribute *attr, 5119 char *buf) 5120 { 5121 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5122 } 5123 5124 static ssize_t set_sysctl_tfa(struct device *cdev, 5125 struct device_attribute *attr, 5126 const char *buf, size_t count) 5127 { 5128 bool val; 5129 ssize_t ret; 5130 5131 ret = kstrtobool(buf, &val); 5132 if (ret) 5133 return ret; 5134 5135 /* no change */ 5136 if (val == allow_tsx_force_abort) 5137 return count; 5138 5139 allow_tsx_force_abort = val; 5140 5141 cpus_read_lock(); 5142 on_each_cpu(update_tfa_sched, NULL, 1); 5143 cpus_read_unlock(); 5144 5145 return count; 5146 } 5147 5148 5149 static DEVICE_ATTR_RW(freeze_on_smi); 5150 5151 static ssize_t branches_show(struct device *cdev, 5152 struct device_attribute *attr, 5153 char *buf) 5154 { 5155 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5156 } 5157 5158 static DEVICE_ATTR_RO(branches); 5159 5160 static struct attribute *lbr_attrs[] = { 5161 &dev_attr_branches.attr, 5162 NULL 5163 }; 5164 5165 static char pmu_name_str[30]; 5166 5167 static ssize_t pmu_name_show(struct device *cdev, 5168 struct device_attribute *attr, 5169 char *buf) 5170 { 5171 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5172 } 5173 5174 static DEVICE_ATTR_RO(pmu_name); 5175 5176 static struct attribute *intel_pmu_caps_attrs[] = { 5177 &dev_attr_pmu_name.attr, 5178 NULL 5179 }; 5180 5181 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5182 show_sysctl_tfa, 5183 set_sysctl_tfa); 5184 5185 static struct attribute *intel_pmu_attrs[] = { 5186 &dev_attr_freeze_on_smi.attr, 5187 &dev_attr_allow_tsx_force_abort.attr, 5188 NULL, 5189 }; 5190 5191 static umode_t 5192 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5193 { 5194 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5195 } 5196 5197 static umode_t 5198 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5199 { 5200 return x86_pmu.pebs ? attr->mode : 0; 5201 } 5202 5203 static umode_t 5204 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5205 { 5206 return x86_pmu.lbr_nr ? attr->mode : 0; 5207 } 5208 5209 static umode_t 5210 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5211 { 5212 return x86_pmu.version >= 2 ? attr->mode : 0; 5213 } 5214 5215 static umode_t 5216 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5217 { 5218 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5219 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5220 5221 return attr->mode; 5222 } 5223 5224 static struct attribute_group group_events_td = { 5225 .name = "events", 5226 }; 5227 5228 static struct attribute_group group_events_mem = { 5229 .name = "events", 5230 .is_visible = pebs_is_visible, 5231 }; 5232 5233 static struct attribute_group group_events_tsx = { 5234 .name = "events", 5235 .is_visible = tsx_is_visible, 5236 }; 5237 5238 static struct attribute_group group_caps_gen = { 5239 .name = "caps", 5240 .attrs = intel_pmu_caps_attrs, 5241 }; 5242 5243 static struct attribute_group group_caps_lbr = { 5244 .name = "caps", 5245 .attrs = lbr_attrs, 5246 .is_visible = lbr_is_visible, 5247 }; 5248 5249 static struct attribute_group group_format_extra = { 5250 .name = "format", 5251 .is_visible = exra_is_visible, 5252 }; 5253 5254 static struct attribute_group group_format_extra_skl = { 5255 .name = "format", 5256 .is_visible = exra_is_visible, 5257 }; 5258 5259 static struct attribute_group group_default = { 5260 .attrs = intel_pmu_attrs, 5261 .is_visible = default_is_visible, 5262 }; 5263 5264 static const struct attribute_group *attr_update[] = { 5265 &group_events_td, 5266 &group_events_mem, 5267 &group_events_tsx, 5268 &group_caps_gen, 5269 &group_caps_lbr, 5270 &group_format_extra, 5271 &group_format_extra_skl, 5272 &group_default, 5273 NULL, 5274 }; 5275 5276 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5277 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5278 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5279 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5280 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5281 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5282 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5283 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5284 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5285 5286 static struct attribute *adl_hybrid_events_attrs[] = { 5287 EVENT_PTR(slots_adl), 5288 EVENT_PTR(td_retiring_adl), 5289 EVENT_PTR(td_bad_spec_adl), 5290 EVENT_PTR(td_fe_bound_adl), 5291 EVENT_PTR(td_be_bound_adl), 5292 EVENT_PTR(td_heavy_ops_adl), 5293 EVENT_PTR(td_br_mis_adl), 5294 EVENT_PTR(td_fetch_lat_adl), 5295 EVENT_PTR(td_mem_bound_adl), 5296 NULL, 5297 }; 5298 5299 /* Must be in IDX order */ 5300 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5301 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5302 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5303 5304 static struct attribute *adl_hybrid_mem_attrs[] = { 5305 EVENT_PTR(mem_ld_adl), 5306 EVENT_PTR(mem_st_adl), 5307 EVENT_PTR(mem_ld_aux_adl), 5308 NULL, 5309 }; 5310 5311 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5312 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5313 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5314 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5315 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5316 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5317 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5318 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5319 5320 static struct attribute *adl_hybrid_tsx_attrs[] = { 5321 EVENT_PTR(tx_start_adl), 5322 EVENT_PTR(tx_abort_adl), 5323 EVENT_PTR(tx_commit_adl), 5324 EVENT_PTR(tx_capacity_read_adl), 5325 EVENT_PTR(tx_capacity_write_adl), 5326 EVENT_PTR(tx_conflict_adl), 5327 EVENT_PTR(cycles_t_adl), 5328 EVENT_PTR(cycles_ct_adl), 5329 NULL, 5330 }; 5331 5332 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5333 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5334 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5335 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5336 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5337 5338 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5339 FORMAT_HYBRID_PTR(in_tx), 5340 FORMAT_HYBRID_PTR(in_tx_cp), 5341 FORMAT_HYBRID_PTR(offcore_rsp), 5342 FORMAT_HYBRID_PTR(ldlat), 5343 FORMAT_HYBRID_PTR(frontend), 5344 NULL, 5345 }; 5346 5347 static struct attribute *adl_hybrid_extra_attr[] = { 5348 FORMAT_HYBRID_PTR(offcore_rsp), 5349 FORMAT_HYBRID_PTR(ldlat), 5350 FORMAT_HYBRID_PTR(frontend), 5351 NULL, 5352 }; 5353 5354 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5355 { 5356 struct device *dev = kobj_to_dev(kobj); 5357 struct x86_hybrid_pmu *pmu = 5358 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5359 struct perf_pmu_events_hybrid_attr *pmu_attr = 5360 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5361 5362 return pmu->cpu_type & pmu_attr->pmu_type; 5363 } 5364 5365 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5366 struct attribute *attr, int i) 5367 { 5368 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5369 } 5370 5371 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5372 { 5373 int cpu = cpumask_first(&pmu->supported_cpus); 5374 5375 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5376 } 5377 5378 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5379 struct attribute *attr, int i) 5380 { 5381 struct device *dev = kobj_to_dev(kobj); 5382 struct x86_hybrid_pmu *pmu = 5383 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5384 int cpu = hybrid_find_supported_cpu(pmu); 5385 5386 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5387 } 5388 5389 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5390 struct attribute *attr, int i) 5391 { 5392 struct device *dev = kobj_to_dev(kobj); 5393 struct x86_hybrid_pmu *pmu = 5394 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5395 struct perf_pmu_format_hybrid_attr *pmu_attr = 5396 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5397 int cpu = hybrid_find_supported_cpu(pmu); 5398 5399 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5400 } 5401 5402 static struct attribute_group hybrid_group_events_td = { 5403 .name = "events", 5404 .is_visible = hybrid_events_is_visible, 5405 }; 5406 5407 static struct attribute_group hybrid_group_events_mem = { 5408 .name = "events", 5409 .is_visible = hybrid_events_is_visible, 5410 }; 5411 5412 static struct attribute_group hybrid_group_events_tsx = { 5413 .name = "events", 5414 .is_visible = hybrid_tsx_is_visible, 5415 }; 5416 5417 static struct attribute_group hybrid_group_format_extra = { 5418 .name = "format", 5419 .is_visible = hybrid_format_is_visible, 5420 }; 5421 5422 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5423 struct device_attribute *attr, 5424 char *buf) 5425 { 5426 struct x86_hybrid_pmu *pmu = 5427 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5428 5429 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5430 } 5431 5432 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5433 static struct attribute *intel_hybrid_cpus_attrs[] = { 5434 &dev_attr_cpus.attr, 5435 NULL, 5436 }; 5437 5438 static struct attribute_group hybrid_group_cpus = { 5439 .attrs = intel_hybrid_cpus_attrs, 5440 }; 5441 5442 static const struct attribute_group *hybrid_attr_update[] = { 5443 &hybrid_group_events_td, 5444 &hybrid_group_events_mem, 5445 &hybrid_group_events_tsx, 5446 &group_caps_gen, 5447 &group_caps_lbr, 5448 &hybrid_group_format_extra, 5449 &group_default, 5450 &hybrid_group_cpus, 5451 NULL, 5452 }; 5453 5454 static struct attribute *empty_attrs; 5455 5456 static void intel_pmu_check_num_counters(int *num_counters, 5457 int *num_counters_fixed, 5458 u64 *intel_ctrl, u64 fixed_mask) 5459 { 5460 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5461 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5462 *num_counters, INTEL_PMC_MAX_GENERIC); 5463 *num_counters = INTEL_PMC_MAX_GENERIC; 5464 } 5465 *intel_ctrl = (1ULL << *num_counters) - 1; 5466 5467 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5468 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5469 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5470 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5471 } 5472 5473 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5474 } 5475 5476 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5477 int num_counters, 5478 int num_counters_fixed, 5479 u64 intel_ctrl) 5480 { 5481 struct event_constraint *c; 5482 5483 if (!event_constraints) 5484 return; 5485 5486 /* 5487 * event on fixed counter2 (REF_CYCLES) only works on this 5488 * counter, so do not extend mask to generic counters 5489 */ 5490 for_each_event_constraint(c, event_constraints) { 5491 /* 5492 * Don't extend the topdown slots and metrics 5493 * events to the generic counters. 5494 */ 5495 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5496 /* 5497 * Disable topdown slots and metrics events, 5498 * if slots event is not in CPUID. 5499 */ 5500 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5501 c->idxmsk64 = 0; 5502 c->weight = hweight64(c->idxmsk64); 5503 continue; 5504 } 5505 5506 if (c->cmask == FIXED_EVENT_FLAGS) { 5507 /* Disabled fixed counters which are not in CPUID */ 5508 c->idxmsk64 &= intel_ctrl; 5509 5510 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) 5511 c->idxmsk64 |= (1ULL << num_counters) - 1; 5512 } 5513 c->idxmsk64 &= 5514 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5515 c->weight = hweight64(c->idxmsk64); 5516 } 5517 } 5518 5519 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5520 { 5521 struct extra_reg *er; 5522 5523 /* 5524 * Access extra MSR may cause #GP under certain circumstances. 5525 * E.g. KVM doesn't support offcore event 5526 * Check all extra_regs here. 5527 */ 5528 if (!extra_regs) 5529 return; 5530 5531 for (er = extra_regs; er->msr; er++) { 5532 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5533 /* Disable LBR select mapping */ 5534 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5535 x86_pmu.lbr_sel_map = NULL; 5536 } 5537 } 5538 5539 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5540 { 5541 struct x86_hybrid_pmu *pmu; 5542 int i; 5543 5544 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5545 pmu = &x86_pmu.hybrid_pmu[i]; 5546 5547 intel_pmu_check_num_counters(&pmu->num_counters, 5548 &pmu->num_counters_fixed, 5549 &pmu->intel_ctrl, 5550 fixed_mask); 5551 5552 if (pmu->intel_cap.perf_metrics) { 5553 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5554 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5555 } 5556 5557 if (pmu->intel_cap.pebs_output_pt_available) 5558 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5559 5560 intel_pmu_check_event_constraints(pmu->event_constraints, 5561 pmu->num_counters, 5562 pmu->num_counters_fixed, 5563 pmu->intel_ctrl); 5564 5565 intel_pmu_check_extra_regs(pmu->extra_regs); 5566 } 5567 } 5568 5569 __init int intel_pmu_init(void) 5570 { 5571 struct attribute **extra_skl_attr = &empty_attrs; 5572 struct attribute **extra_attr = &empty_attrs; 5573 struct attribute **td_attr = &empty_attrs; 5574 struct attribute **mem_attr = &empty_attrs; 5575 struct attribute **tsx_attr = &empty_attrs; 5576 union cpuid10_edx edx; 5577 union cpuid10_eax eax; 5578 union cpuid10_ebx ebx; 5579 unsigned int fixed_mask; 5580 bool pmem = false; 5581 int version, i; 5582 char *name; 5583 struct x86_hybrid_pmu *pmu; 5584 5585 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5586 switch (boot_cpu_data.x86) { 5587 case 0x6: 5588 return p6_pmu_init(); 5589 case 0xb: 5590 return knc_pmu_init(); 5591 case 0xf: 5592 return p4_pmu_init(); 5593 } 5594 return -ENODEV; 5595 } 5596 5597 /* 5598 * Check whether the Architectural PerfMon supports 5599 * Branch Misses Retired hw_event or not. 5600 */ 5601 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5602 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5603 return -ENODEV; 5604 5605 version = eax.split.version_id; 5606 if (version < 2) 5607 x86_pmu = core_pmu; 5608 else 5609 x86_pmu = intel_pmu; 5610 5611 x86_pmu.version = version; 5612 x86_pmu.num_counters = eax.split.num_counters; 5613 x86_pmu.cntval_bits = eax.split.bit_width; 5614 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5615 5616 x86_pmu.events_maskl = ebx.full; 5617 x86_pmu.events_mask_len = eax.split.mask_length; 5618 5619 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5620 5621 /* 5622 * Quirk: v2 perfmon does not report fixed-purpose events, so 5623 * assume at least 3 events, when not running in a hypervisor: 5624 */ 5625 if (version > 1 && version < 5) { 5626 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5627 5628 x86_pmu.num_counters_fixed = 5629 max((int)edx.split.num_counters_fixed, assume); 5630 5631 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5632 } else if (version >= 5) 5633 x86_pmu.num_counters_fixed = fls(fixed_mask); 5634 5635 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5636 u64 capabilities; 5637 5638 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5639 x86_pmu.intel_cap.capabilities = capabilities; 5640 } 5641 5642 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5643 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5644 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5645 } 5646 5647 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5648 intel_pmu_arch_lbr_init(); 5649 5650 intel_ds_init(); 5651 5652 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5653 5654 if (version >= 5) { 5655 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5656 if (x86_pmu.intel_cap.anythread_deprecated) 5657 pr_cont(" AnyThread deprecated, "); 5658 } 5659 5660 /* 5661 * Install the hw-cache-events table: 5662 */ 5663 switch (boot_cpu_data.x86_model) { 5664 case INTEL_FAM6_CORE_YONAH: 5665 pr_cont("Core events, "); 5666 name = "core"; 5667 break; 5668 5669 case INTEL_FAM6_CORE2_MEROM: 5670 x86_add_quirk(intel_clovertown_quirk); 5671 fallthrough; 5672 5673 case INTEL_FAM6_CORE2_MEROM_L: 5674 case INTEL_FAM6_CORE2_PENRYN: 5675 case INTEL_FAM6_CORE2_DUNNINGTON: 5676 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5677 sizeof(hw_cache_event_ids)); 5678 5679 intel_pmu_lbr_init_core(); 5680 5681 x86_pmu.event_constraints = intel_core2_event_constraints; 5682 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5683 pr_cont("Core2 events, "); 5684 name = "core2"; 5685 break; 5686 5687 case INTEL_FAM6_NEHALEM: 5688 case INTEL_FAM6_NEHALEM_EP: 5689 case INTEL_FAM6_NEHALEM_EX: 5690 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5691 sizeof(hw_cache_event_ids)); 5692 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5693 sizeof(hw_cache_extra_regs)); 5694 5695 intel_pmu_lbr_init_nhm(); 5696 5697 x86_pmu.event_constraints = intel_nehalem_event_constraints; 5698 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5699 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5700 x86_pmu.extra_regs = intel_nehalem_extra_regs; 5701 x86_pmu.limit_period = nhm_limit_period; 5702 5703 mem_attr = nhm_mem_events_attrs; 5704 5705 /* UOPS_ISSUED.STALLED_CYCLES */ 5706 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5707 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5708 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5709 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5710 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5711 5712 intel_pmu_pebs_data_source_nhm(); 5713 x86_add_quirk(intel_nehalem_quirk); 5714 x86_pmu.pebs_no_tlb = 1; 5715 extra_attr = nhm_format_attr; 5716 5717 pr_cont("Nehalem events, "); 5718 name = "nehalem"; 5719 break; 5720 5721 case INTEL_FAM6_ATOM_BONNELL: 5722 case INTEL_FAM6_ATOM_BONNELL_MID: 5723 case INTEL_FAM6_ATOM_SALTWELL: 5724 case INTEL_FAM6_ATOM_SALTWELL_MID: 5725 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5726 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5727 sizeof(hw_cache_event_ids)); 5728 5729 intel_pmu_lbr_init_atom(); 5730 5731 x86_pmu.event_constraints = intel_gen_event_constraints; 5732 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5733 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5734 pr_cont("Atom events, "); 5735 name = "bonnell"; 5736 break; 5737 5738 case INTEL_FAM6_ATOM_SILVERMONT: 5739 case INTEL_FAM6_ATOM_SILVERMONT_D: 5740 case INTEL_FAM6_ATOM_SILVERMONT_MID: 5741 case INTEL_FAM6_ATOM_AIRMONT: 5742 case INTEL_FAM6_ATOM_AIRMONT_MID: 5743 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5744 sizeof(hw_cache_event_ids)); 5745 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5746 sizeof(hw_cache_extra_regs)); 5747 5748 intel_pmu_lbr_init_slm(); 5749 5750 x86_pmu.event_constraints = intel_slm_event_constraints; 5751 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5752 x86_pmu.extra_regs = intel_slm_extra_regs; 5753 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5754 td_attr = slm_events_attrs; 5755 extra_attr = slm_format_attr; 5756 pr_cont("Silvermont events, "); 5757 name = "silvermont"; 5758 break; 5759 5760 case INTEL_FAM6_ATOM_GOLDMONT: 5761 case INTEL_FAM6_ATOM_GOLDMONT_D: 5762 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 5763 sizeof(hw_cache_event_ids)); 5764 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 5765 sizeof(hw_cache_extra_regs)); 5766 5767 intel_pmu_lbr_init_skl(); 5768 5769 x86_pmu.event_constraints = intel_slm_event_constraints; 5770 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 5771 x86_pmu.extra_regs = intel_glm_extra_regs; 5772 /* 5773 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5774 * for precise cycles. 5775 * :pp is identical to :ppp 5776 */ 5777 x86_pmu.pebs_aliases = NULL; 5778 x86_pmu.pebs_prec_dist = true; 5779 x86_pmu.lbr_pt_coexist = true; 5780 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5781 td_attr = glm_events_attrs; 5782 extra_attr = slm_format_attr; 5783 pr_cont("Goldmont events, "); 5784 name = "goldmont"; 5785 break; 5786 5787 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5788 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5789 sizeof(hw_cache_event_ids)); 5790 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5791 sizeof(hw_cache_extra_regs)); 5792 5793 intel_pmu_lbr_init_skl(); 5794 5795 x86_pmu.event_constraints = intel_slm_event_constraints; 5796 x86_pmu.extra_regs = intel_glm_extra_regs; 5797 /* 5798 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5799 * for precise cycles. 5800 */ 5801 x86_pmu.pebs_aliases = NULL; 5802 x86_pmu.pebs_prec_dist = true; 5803 x86_pmu.lbr_pt_coexist = true; 5804 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5805 x86_pmu.flags |= PMU_FL_PEBS_ALL; 5806 x86_pmu.get_event_constraints = glp_get_event_constraints; 5807 td_attr = glm_events_attrs; 5808 /* Goldmont Plus has 4-wide pipeline */ 5809 event_attr_td_total_slots_scale_glm.event_str = "4"; 5810 extra_attr = slm_format_attr; 5811 pr_cont("Goldmont plus events, "); 5812 name = "goldmont_plus"; 5813 break; 5814 5815 case INTEL_FAM6_ATOM_TREMONT_D: 5816 case INTEL_FAM6_ATOM_TREMONT: 5817 case INTEL_FAM6_ATOM_TREMONT_L: 5818 x86_pmu.late_ack = true; 5819 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5820 sizeof(hw_cache_event_ids)); 5821 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5822 sizeof(hw_cache_extra_regs)); 5823 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5824 5825 intel_pmu_lbr_init_skl(); 5826 5827 x86_pmu.event_constraints = intel_slm_event_constraints; 5828 x86_pmu.extra_regs = intel_tnt_extra_regs; 5829 /* 5830 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5831 * for precise cycles. 5832 */ 5833 x86_pmu.pebs_aliases = NULL; 5834 x86_pmu.pebs_prec_dist = true; 5835 x86_pmu.lbr_pt_coexist = true; 5836 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5837 x86_pmu.get_event_constraints = tnt_get_event_constraints; 5838 td_attr = tnt_events_attrs; 5839 extra_attr = slm_format_attr; 5840 pr_cont("Tremont events, "); 5841 name = "Tremont"; 5842 break; 5843 5844 case INTEL_FAM6_WESTMERE: 5845 case INTEL_FAM6_WESTMERE_EP: 5846 case INTEL_FAM6_WESTMERE_EX: 5847 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5848 sizeof(hw_cache_event_ids)); 5849 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5850 sizeof(hw_cache_extra_regs)); 5851 5852 intel_pmu_lbr_init_nhm(); 5853 5854 x86_pmu.event_constraints = intel_westmere_event_constraints; 5855 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5856 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5857 x86_pmu.extra_regs = intel_westmere_extra_regs; 5858 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5859 5860 mem_attr = nhm_mem_events_attrs; 5861 5862 /* UOPS_ISSUED.STALLED_CYCLES */ 5863 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5864 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5865 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5866 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5867 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5868 5869 intel_pmu_pebs_data_source_nhm(); 5870 extra_attr = nhm_format_attr; 5871 pr_cont("Westmere events, "); 5872 name = "westmere"; 5873 break; 5874 5875 case INTEL_FAM6_SANDYBRIDGE: 5876 case INTEL_FAM6_SANDYBRIDGE_X: 5877 x86_add_quirk(intel_sandybridge_quirk); 5878 x86_add_quirk(intel_ht_bug); 5879 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5880 sizeof(hw_cache_event_ids)); 5881 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5882 sizeof(hw_cache_extra_regs)); 5883 5884 intel_pmu_lbr_init_snb(); 5885 5886 x86_pmu.event_constraints = intel_snb_event_constraints; 5887 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5888 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5889 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5890 x86_pmu.extra_regs = intel_snbep_extra_regs; 5891 else 5892 x86_pmu.extra_regs = intel_snb_extra_regs; 5893 5894 5895 /* all extra regs are per-cpu when HT is on */ 5896 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5897 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5898 5899 td_attr = snb_events_attrs; 5900 mem_attr = snb_mem_events_attrs; 5901 5902 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5903 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5904 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5905 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5906 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5907 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5908 5909 extra_attr = nhm_format_attr; 5910 5911 pr_cont("SandyBridge events, "); 5912 name = "sandybridge"; 5913 break; 5914 5915 case INTEL_FAM6_IVYBRIDGE: 5916 case INTEL_FAM6_IVYBRIDGE_X: 5917 x86_add_quirk(intel_ht_bug); 5918 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5919 sizeof(hw_cache_event_ids)); 5920 /* dTLB-load-misses on IVB is different than SNB */ 5921 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5922 5923 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5924 sizeof(hw_cache_extra_regs)); 5925 5926 intel_pmu_lbr_init_snb(); 5927 5928 x86_pmu.event_constraints = intel_ivb_event_constraints; 5929 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5930 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5931 x86_pmu.pebs_prec_dist = true; 5932 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5933 x86_pmu.extra_regs = intel_snbep_extra_regs; 5934 else 5935 x86_pmu.extra_regs = intel_snb_extra_regs; 5936 /* all extra regs are per-cpu when HT is on */ 5937 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5938 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5939 5940 td_attr = snb_events_attrs; 5941 mem_attr = snb_mem_events_attrs; 5942 5943 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5944 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5945 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5946 5947 extra_attr = nhm_format_attr; 5948 5949 pr_cont("IvyBridge events, "); 5950 name = "ivybridge"; 5951 break; 5952 5953 5954 case INTEL_FAM6_HASWELL: 5955 case INTEL_FAM6_HASWELL_X: 5956 case INTEL_FAM6_HASWELL_L: 5957 case INTEL_FAM6_HASWELL_G: 5958 x86_add_quirk(intel_ht_bug); 5959 x86_add_quirk(intel_pebs_isolation_quirk); 5960 x86_pmu.late_ack = true; 5961 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5962 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5963 5964 intel_pmu_lbr_init_hsw(); 5965 5966 x86_pmu.event_constraints = intel_hsw_event_constraints; 5967 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5968 x86_pmu.extra_regs = intel_snbep_extra_regs; 5969 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5970 x86_pmu.pebs_prec_dist = true; 5971 /* all extra regs are per-cpu when HT is on */ 5972 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5973 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5974 5975 x86_pmu.hw_config = hsw_hw_config; 5976 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5977 x86_pmu.lbr_double_abort = true; 5978 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5979 hsw_format_attr : nhm_format_attr; 5980 td_attr = hsw_events_attrs; 5981 mem_attr = hsw_mem_events_attrs; 5982 tsx_attr = hsw_tsx_events_attrs; 5983 pr_cont("Haswell events, "); 5984 name = "haswell"; 5985 break; 5986 5987 case INTEL_FAM6_BROADWELL: 5988 case INTEL_FAM6_BROADWELL_D: 5989 case INTEL_FAM6_BROADWELL_G: 5990 case INTEL_FAM6_BROADWELL_X: 5991 x86_add_quirk(intel_pebs_isolation_quirk); 5992 x86_pmu.late_ack = true; 5993 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5994 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5995 5996 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5997 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5998 BDW_L3_MISS|HSW_SNOOP_DRAM; 5999 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6000 HSW_SNOOP_DRAM; 6001 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6002 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6003 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6004 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6005 6006 intel_pmu_lbr_init_hsw(); 6007 6008 x86_pmu.event_constraints = intel_bdw_event_constraints; 6009 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6010 x86_pmu.extra_regs = intel_snbep_extra_regs; 6011 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6012 x86_pmu.pebs_prec_dist = true; 6013 /* all extra regs are per-cpu when HT is on */ 6014 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6015 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6016 6017 x86_pmu.hw_config = hsw_hw_config; 6018 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6019 x86_pmu.limit_period = bdw_limit_period; 6020 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6021 hsw_format_attr : nhm_format_attr; 6022 td_attr = hsw_events_attrs; 6023 mem_attr = hsw_mem_events_attrs; 6024 tsx_attr = hsw_tsx_events_attrs; 6025 pr_cont("Broadwell events, "); 6026 name = "broadwell"; 6027 break; 6028 6029 case INTEL_FAM6_XEON_PHI_KNL: 6030 case INTEL_FAM6_XEON_PHI_KNM: 6031 memcpy(hw_cache_event_ids, 6032 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6033 memcpy(hw_cache_extra_regs, 6034 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6035 intel_pmu_lbr_init_knl(); 6036 6037 x86_pmu.event_constraints = intel_slm_event_constraints; 6038 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6039 x86_pmu.extra_regs = intel_knl_extra_regs; 6040 6041 /* all extra regs are per-cpu when HT is on */ 6042 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6043 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6044 extra_attr = slm_format_attr; 6045 pr_cont("Knights Landing/Mill events, "); 6046 name = "knights-landing"; 6047 break; 6048 6049 case INTEL_FAM6_SKYLAKE_X: 6050 pmem = true; 6051 fallthrough; 6052 case INTEL_FAM6_SKYLAKE_L: 6053 case INTEL_FAM6_SKYLAKE: 6054 case INTEL_FAM6_KABYLAKE_L: 6055 case INTEL_FAM6_KABYLAKE: 6056 case INTEL_FAM6_COMETLAKE_L: 6057 case INTEL_FAM6_COMETLAKE: 6058 x86_add_quirk(intel_pebs_isolation_quirk); 6059 x86_pmu.late_ack = true; 6060 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6061 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6062 intel_pmu_lbr_init_skl(); 6063 6064 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6065 event_attr_td_recovery_bubbles.event_str_noht = 6066 "event=0xd,umask=0x1,cmask=1"; 6067 event_attr_td_recovery_bubbles.event_str_ht = 6068 "event=0xd,umask=0x1,cmask=1,any=1"; 6069 6070 x86_pmu.event_constraints = intel_skl_event_constraints; 6071 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6072 x86_pmu.extra_regs = intel_skl_extra_regs; 6073 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6074 x86_pmu.pebs_prec_dist = true; 6075 /* all extra regs are per-cpu when HT is on */ 6076 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6077 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6078 6079 x86_pmu.hw_config = hsw_hw_config; 6080 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6081 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6082 hsw_format_attr : nhm_format_attr; 6083 extra_skl_attr = skl_format_attr; 6084 td_attr = hsw_events_attrs; 6085 mem_attr = hsw_mem_events_attrs; 6086 tsx_attr = hsw_tsx_events_attrs; 6087 intel_pmu_pebs_data_source_skl(pmem); 6088 6089 /* 6090 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6091 * TSX force abort hooks are not required on these systems. Only deploy 6092 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6093 */ 6094 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6095 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6096 x86_pmu.flags |= PMU_FL_TFA; 6097 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6098 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6099 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6100 } 6101 6102 pr_cont("Skylake events, "); 6103 name = "skylake"; 6104 break; 6105 6106 case INTEL_FAM6_ICELAKE_X: 6107 case INTEL_FAM6_ICELAKE_D: 6108 pmem = true; 6109 fallthrough; 6110 case INTEL_FAM6_ICELAKE_L: 6111 case INTEL_FAM6_ICELAKE: 6112 case INTEL_FAM6_TIGERLAKE_L: 6113 case INTEL_FAM6_TIGERLAKE: 6114 case INTEL_FAM6_ROCKETLAKE: 6115 x86_pmu.late_ack = true; 6116 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6117 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6118 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6119 intel_pmu_lbr_init_skl(); 6120 6121 x86_pmu.event_constraints = intel_icl_event_constraints; 6122 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6123 x86_pmu.extra_regs = intel_icl_extra_regs; 6124 x86_pmu.pebs_aliases = NULL; 6125 x86_pmu.pebs_prec_dist = true; 6126 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6127 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6128 6129 x86_pmu.hw_config = hsw_hw_config; 6130 x86_pmu.get_event_constraints = icl_get_event_constraints; 6131 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6132 hsw_format_attr : nhm_format_attr; 6133 extra_skl_attr = skl_format_attr; 6134 mem_attr = icl_events_attrs; 6135 td_attr = icl_td_events_attrs; 6136 tsx_attr = icl_tsx_events_attrs; 6137 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6138 x86_pmu.lbr_pt_coexist = true; 6139 intel_pmu_pebs_data_source_skl(pmem); 6140 x86_pmu.num_topdown_events = 4; 6141 x86_pmu.update_topdown_event = icl_update_topdown_event; 6142 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6143 pr_cont("Icelake events, "); 6144 name = "icelake"; 6145 break; 6146 6147 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6148 pmem = true; 6149 x86_pmu.late_ack = true; 6150 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6151 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6152 6153 x86_pmu.event_constraints = intel_spr_event_constraints; 6154 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6155 x86_pmu.extra_regs = intel_spr_extra_regs; 6156 x86_pmu.limit_period = spr_limit_period; 6157 x86_pmu.pebs_aliases = NULL; 6158 x86_pmu.pebs_prec_dist = true; 6159 x86_pmu.pebs_block = true; 6160 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6161 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6162 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6163 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6164 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6165 6166 x86_pmu.hw_config = hsw_hw_config; 6167 x86_pmu.get_event_constraints = spr_get_event_constraints; 6168 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6169 hsw_format_attr : nhm_format_attr; 6170 extra_skl_attr = skl_format_attr; 6171 mem_attr = spr_events_attrs; 6172 td_attr = spr_td_events_attrs; 6173 tsx_attr = spr_tsx_events_attrs; 6174 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6175 x86_pmu.lbr_pt_coexist = true; 6176 intel_pmu_pebs_data_source_skl(pmem); 6177 x86_pmu.num_topdown_events = 8; 6178 x86_pmu.update_topdown_event = icl_update_topdown_event; 6179 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6180 pr_cont("Sapphire Rapids events, "); 6181 name = "sapphire_rapids"; 6182 break; 6183 6184 case INTEL_FAM6_ALDERLAKE: 6185 case INTEL_FAM6_ALDERLAKE_L: 6186 /* 6187 * Alder Lake has 2 types of CPU, core and atom. 6188 * 6189 * Initialize the common PerfMon capabilities here. 6190 */ 6191 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6192 sizeof(struct x86_hybrid_pmu), 6193 GFP_KERNEL); 6194 if (!x86_pmu.hybrid_pmu) 6195 return -ENOMEM; 6196 static_branch_enable(&perf_is_hybrid); 6197 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6198 6199 x86_pmu.pebs_aliases = NULL; 6200 x86_pmu.pebs_prec_dist = true; 6201 x86_pmu.pebs_block = true; 6202 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6203 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6204 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6205 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6206 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6207 x86_pmu.lbr_pt_coexist = true; 6208 intel_pmu_pebs_data_source_skl(false); 6209 x86_pmu.num_topdown_events = 8; 6210 x86_pmu.update_topdown_event = adl_update_topdown_event; 6211 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; 6212 6213 x86_pmu.filter_match = intel_pmu_filter_match; 6214 x86_pmu.get_event_constraints = adl_get_event_constraints; 6215 x86_pmu.hw_config = adl_hw_config; 6216 x86_pmu.limit_period = spr_limit_period; 6217 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6218 /* 6219 * The rtm_abort_event is used to check whether to enable GPRs 6220 * for the RTM abort event. Atom doesn't have the RTM abort 6221 * event. There is no harmful to set it in the common 6222 * x86_pmu.rtm_abort_event. 6223 */ 6224 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6225 6226 td_attr = adl_hybrid_events_attrs; 6227 mem_attr = adl_hybrid_mem_attrs; 6228 tsx_attr = adl_hybrid_tsx_attrs; 6229 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6230 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6231 6232 /* Initialize big core specific PerfMon capabilities.*/ 6233 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6234 pmu->name = "cpu_core"; 6235 pmu->cpu_type = hybrid_big; 6236 pmu->late_ack = true; 6237 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6238 pmu->num_counters = x86_pmu.num_counters + 2; 6239 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6240 } else { 6241 pmu->num_counters = x86_pmu.num_counters; 6242 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6243 } 6244 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6245 pmu->unconstrained = (struct event_constraint) 6246 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6247 0, pmu->num_counters, 0, 0); 6248 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6249 pmu->intel_cap.perf_metrics = 1; 6250 pmu->intel_cap.pebs_output_pt_available = 0; 6251 6252 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6253 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6254 pmu->event_constraints = intel_spr_event_constraints; 6255 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6256 pmu->extra_regs = intel_spr_extra_regs; 6257 6258 /* Initialize Atom core specific PerfMon capabilities.*/ 6259 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6260 pmu->name = "cpu_atom"; 6261 pmu->cpu_type = hybrid_small; 6262 pmu->mid_ack = true; 6263 pmu->num_counters = x86_pmu.num_counters; 6264 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6265 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6266 pmu->unconstrained = (struct event_constraint) 6267 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6268 0, pmu->num_counters, 0, 0); 6269 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6270 pmu->intel_cap.perf_metrics = 0; 6271 pmu->intel_cap.pebs_output_pt_available = 1; 6272 6273 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6274 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6275 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6276 pmu->event_constraints = intel_slm_event_constraints; 6277 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6278 pmu->extra_regs = intel_grt_extra_regs; 6279 pr_cont("Alderlake Hybrid events, "); 6280 name = "alderlake_hybrid"; 6281 break; 6282 6283 default: 6284 switch (x86_pmu.version) { 6285 case 1: 6286 x86_pmu.event_constraints = intel_v1_event_constraints; 6287 pr_cont("generic architected perfmon v1, "); 6288 name = "generic_arch_v1"; 6289 break; 6290 default: 6291 /* 6292 * default constraints for v2 and up 6293 */ 6294 x86_pmu.event_constraints = intel_gen_event_constraints; 6295 pr_cont("generic architected perfmon, "); 6296 name = "generic_arch_v2+"; 6297 break; 6298 } 6299 } 6300 6301 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6302 6303 if (!is_hybrid()) { 6304 group_events_td.attrs = td_attr; 6305 group_events_mem.attrs = mem_attr; 6306 group_events_tsx.attrs = tsx_attr; 6307 group_format_extra.attrs = extra_attr; 6308 group_format_extra_skl.attrs = extra_skl_attr; 6309 6310 x86_pmu.attr_update = attr_update; 6311 } else { 6312 hybrid_group_events_td.attrs = td_attr; 6313 hybrid_group_events_mem.attrs = mem_attr; 6314 hybrid_group_events_tsx.attrs = tsx_attr; 6315 hybrid_group_format_extra.attrs = extra_attr; 6316 6317 x86_pmu.attr_update = hybrid_attr_update; 6318 } 6319 6320 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6321 &x86_pmu.num_counters_fixed, 6322 &x86_pmu.intel_ctrl, 6323 (u64)fixed_mask); 6324 6325 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6326 if (x86_pmu.intel_cap.anythread_deprecated) 6327 x86_pmu.format_attrs = intel_arch_formats_attr; 6328 6329 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6330 x86_pmu.num_counters, 6331 x86_pmu.num_counters_fixed, 6332 x86_pmu.intel_ctrl); 6333 /* 6334 * Access LBR MSR may cause #GP under certain circumstances. 6335 * E.g. KVM doesn't support LBR MSR 6336 * Check all LBT MSR here. 6337 * Disable LBR access if any LBR MSRs can not be accessed. 6338 */ 6339 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6340 x86_pmu.lbr_nr = 0; 6341 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6342 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6343 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6344 x86_pmu.lbr_nr = 0; 6345 } 6346 6347 if (x86_pmu.lbr_nr) { 6348 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6349 6350 /* only support branch_stack snapshot for perfmon >= v2 */ 6351 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6352 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6353 static_call_update(perf_snapshot_branch_stack, 6354 intel_pmu_snapshot_arch_branch_stack); 6355 } else { 6356 static_call_update(perf_snapshot_branch_stack, 6357 intel_pmu_snapshot_branch_stack); 6358 } 6359 } 6360 } 6361 6362 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6363 6364 /* Support full width counters using alternative MSR range */ 6365 if (x86_pmu.intel_cap.full_width_write) { 6366 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6367 x86_pmu.perfctr = MSR_IA32_PMC0; 6368 pr_cont("full-width counters, "); 6369 } 6370 6371 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6372 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6373 6374 if (is_hybrid()) 6375 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6376 6377 intel_aux_output_init(); 6378 6379 return 0; 6380 } 6381 6382 /* 6383 * HT bug: phase 2 init 6384 * Called once we have valid topology information to check 6385 * whether or not HT is enabled 6386 * If HT is off, then we disable the workaround 6387 */ 6388 static __init int fixup_ht_bug(void) 6389 { 6390 int c; 6391 /* 6392 * problem not present on this CPU model, nothing to do 6393 */ 6394 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6395 return 0; 6396 6397 if (topology_max_smt_threads() > 1) { 6398 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6399 return 0; 6400 } 6401 6402 cpus_read_lock(); 6403 6404 hardlockup_detector_perf_stop(); 6405 6406 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6407 6408 x86_pmu.start_scheduling = NULL; 6409 x86_pmu.commit_scheduling = NULL; 6410 x86_pmu.stop_scheduling = NULL; 6411 6412 hardlockup_detector_perf_restart(); 6413 6414 for_each_online_cpu(c) 6415 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6416 6417 cpus_read_unlock(); 6418 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6419 return 0; 6420 } 6421 subsys_initcall(fixup_ht_bug) 6422