1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 18 #include <asm/cpufeature.h> 19 #include <asm/hardirq.h> 20 #include <asm/intel-family.h> 21 #include <asm/intel_pt.h> 22 #include <asm/apic.h> 23 #include <asm/cpu_device_id.h> 24 25 #include "../perf_event.h" 26 27 /* 28 * Intel PerfMon, used on Core and later. 29 */ 30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31 { 32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40 }; 41 42 static struct event_constraint intel_core_event_constraints[] __read_mostly = 43 { 44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50 EVENT_CONSTRAINT_END 51 }; 52 53 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54 { 55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68 EVENT_CONSTRAINT_END 69 }; 70 71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72 { 73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84 EVENT_CONSTRAINT_END 85 }; 86 87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88 { 89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92 EVENT_EXTRA_END 93 }; 94 95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96 { 97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104 EVENT_CONSTRAINT_END 105 }; 106 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108 { 109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121 122 /* 123 * When HT is off these events can only run on the bottom 4 counters 124 * When HT is on, they are impacted by the HT bug and require EXCL access 125 */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130 131 EVENT_CONSTRAINT_END 132 }; 133 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135 { 136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149 150 /* 151 * When HT is off these events can only run on the bottom 4 counters 152 * When HT is on, they are impacted by the HT bug and require EXCL access 153 */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158 159 EVENT_CONSTRAINT_END 160 }; 161 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163 { 164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168 EVENT_EXTRA_END 169 }; 170 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172 { 173 EVENT_CONSTRAINT_END 174 }; 175 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177 { 178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181 EVENT_CONSTRAINT_END 182 }; 183 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185 { 186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189 EVENT_CONSTRAINT_END 190 }; 191 192 static struct event_constraint intel_skl_event_constraints[] = { 193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 197 198 /* 199 * when HT is off, these can only run on the bottom 4 counters 200 */ 201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 206 207 EVENT_CONSTRAINT_END 208 }; 209 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213 EVENT_EXTRA_END 214 }; 215 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221 EVENT_EXTRA_END 222 }; 223 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229 EVENT_EXTRA_END 230 }; 231 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236 /* 237 * Note the low 8 bits eventsel code is not a continuous field, containing 238 * some #GPing bits. These are masked out. 239 */ 240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241 EVENT_EXTRA_END 242 }; 243 244 static struct event_constraint intel_icl_event_constraints[] = { 245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 247 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 248 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 249 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 250 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 254 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 255 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 256 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 257 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 258 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 259 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 260 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 261 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 262 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 263 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 264 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 265 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 266 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 267 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 268 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 269 EVENT_CONSTRAINT_END 270 }; 271 272 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 273 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 274 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 275 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 276 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 277 EVENT_EXTRA_END 278 }; 279 280 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 281 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 282 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 283 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 284 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 285 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 286 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 287 EVENT_EXTRA_END 288 }; 289 290 static struct event_constraint intel_spr_event_constraints[] = { 291 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 292 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 293 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 294 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 295 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 298 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 299 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 300 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 301 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 302 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 303 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 304 305 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 306 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 307 /* 308 * Generally event codes < 0x90 are restricted to counters 0-3. 309 * The 0x2E and 0x3C are exception, which has no restriction. 310 */ 311 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 312 313 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 314 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 315 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 316 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 317 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 318 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 319 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 320 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 321 /* 322 * Generally event codes >= 0x90 are likely to have no restrictions. 323 * The exception are defined as above. 324 */ 325 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 326 327 EVENT_CONSTRAINT_END 328 }; 329 330 331 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 332 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 333 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 334 335 static struct attribute *nhm_mem_events_attrs[] = { 336 EVENT_PTR(mem_ld_nhm), 337 NULL, 338 }; 339 340 /* 341 * topdown events for Intel Core CPUs. 342 * 343 * The events are all in slots, which is a free slot in a 4 wide 344 * pipeline. Some events are already reported in slots, for cycle 345 * events we multiply by the pipeline width (4). 346 * 347 * With Hyper Threading on, topdown metrics are either summed or averaged 348 * between the threads of a core: (count_t0 + count_t1). 349 * 350 * For the average case the metric is always scaled to pipeline width, 351 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 352 */ 353 354 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 355 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 356 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 357 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 358 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 359 "event=0xe,umask=0x1"); /* uops_issued.any */ 360 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 361 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 362 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 363 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 364 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 365 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 366 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 367 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 368 "4", "2"); 369 370 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 371 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 372 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 373 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 374 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 375 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 376 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 377 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 378 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 379 380 static struct attribute *snb_events_attrs[] = { 381 EVENT_PTR(td_slots_issued), 382 EVENT_PTR(td_slots_retired), 383 EVENT_PTR(td_fetch_bubbles), 384 EVENT_PTR(td_total_slots), 385 EVENT_PTR(td_total_slots_scale), 386 EVENT_PTR(td_recovery_bubbles), 387 EVENT_PTR(td_recovery_bubbles_scale), 388 NULL, 389 }; 390 391 static struct attribute *snb_mem_events_attrs[] = { 392 EVENT_PTR(mem_ld_snb), 393 EVENT_PTR(mem_st_snb), 394 NULL, 395 }; 396 397 static struct event_constraint intel_hsw_event_constraints[] = { 398 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 399 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 400 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 401 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 402 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 403 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 404 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 405 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 406 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 407 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 408 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 409 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 410 411 /* 412 * When HT is off these events can only run on the bottom 4 counters 413 * When HT is on, they are impacted by the HT bug and require EXCL access 414 */ 415 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 416 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 417 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 418 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 419 420 EVENT_CONSTRAINT_END 421 }; 422 423 static struct event_constraint intel_bdw_event_constraints[] = { 424 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 425 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 426 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 427 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 428 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 429 /* 430 * when HT is off, these can only run on the bottom 4 counters 431 */ 432 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 433 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 434 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 435 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 436 EVENT_CONSTRAINT_END 437 }; 438 439 static u64 intel_pmu_event_map(int hw_event) 440 { 441 return intel_perfmon_event_map[hw_event]; 442 } 443 444 static __initconst const u64 spr_hw_cache_event_ids 445 [PERF_COUNT_HW_CACHE_MAX] 446 [PERF_COUNT_HW_CACHE_OP_MAX] 447 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 448 { 449 [ C(L1D ) ] = { 450 [ C(OP_READ) ] = { 451 [ C(RESULT_ACCESS) ] = 0x81d0, 452 [ C(RESULT_MISS) ] = 0xe124, 453 }, 454 [ C(OP_WRITE) ] = { 455 [ C(RESULT_ACCESS) ] = 0x82d0, 456 }, 457 }, 458 [ C(L1I ) ] = { 459 [ C(OP_READ) ] = { 460 [ C(RESULT_MISS) ] = 0xe424, 461 }, 462 [ C(OP_WRITE) ] = { 463 [ C(RESULT_ACCESS) ] = -1, 464 [ C(RESULT_MISS) ] = -1, 465 }, 466 }, 467 [ C(LL ) ] = { 468 [ C(OP_READ) ] = { 469 [ C(RESULT_ACCESS) ] = 0x12a, 470 [ C(RESULT_MISS) ] = 0x12a, 471 }, 472 [ C(OP_WRITE) ] = { 473 [ C(RESULT_ACCESS) ] = 0x12a, 474 [ C(RESULT_MISS) ] = 0x12a, 475 }, 476 }, 477 [ C(DTLB) ] = { 478 [ C(OP_READ) ] = { 479 [ C(RESULT_ACCESS) ] = 0x81d0, 480 [ C(RESULT_MISS) ] = 0xe12, 481 }, 482 [ C(OP_WRITE) ] = { 483 [ C(RESULT_ACCESS) ] = 0x82d0, 484 [ C(RESULT_MISS) ] = 0xe13, 485 }, 486 }, 487 [ C(ITLB) ] = { 488 [ C(OP_READ) ] = { 489 [ C(RESULT_ACCESS) ] = -1, 490 [ C(RESULT_MISS) ] = 0xe11, 491 }, 492 [ C(OP_WRITE) ] = { 493 [ C(RESULT_ACCESS) ] = -1, 494 [ C(RESULT_MISS) ] = -1, 495 }, 496 [ C(OP_PREFETCH) ] = { 497 [ C(RESULT_ACCESS) ] = -1, 498 [ C(RESULT_MISS) ] = -1, 499 }, 500 }, 501 [ C(BPU ) ] = { 502 [ C(OP_READ) ] = { 503 [ C(RESULT_ACCESS) ] = 0x4c4, 504 [ C(RESULT_MISS) ] = 0x4c5, 505 }, 506 [ C(OP_WRITE) ] = { 507 [ C(RESULT_ACCESS) ] = -1, 508 [ C(RESULT_MISS) ] = -1, 509 }, 510 [ C(OP_PREFETCH) ] = { 511 [ C(RESULT_ACCESS) ] = -1, 512 [ C(RESULT_MISS) ] = -1, 513 }, 514 }, 515 [ C(NODE) ] = { 516 [ C(OP_READ) ] = { 517 [ C(RESULT_ACCESS) ] = 0x12a, 518 [ C(RESULT_MISS) ] = 0x12a, 519 }, 520 }, 521 }; 522 523 static __initconst const u64 spr_hw_cache_extra_regs 524 [PERF_COUNT_HW_CACHE_MAX] 525 [PERF_COUNT_HW_CACHE_OP_MAX] 526 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 527 { 528 [ C(LL ) ] = { 529 [ C(OP_READ) ] = { 530 [ C(RESULT_ACCESS) ] = 0x10001, 531 [ C(RESULT_MISS) ] = 0x3fbfc00001, 532 }, 533 [ C(OP_WRITE) ] = { 534 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 535 [ C(RESULT_MISS) ] = 0x3f3fc00002, 536 }, 537 }, 538 [ C(NODE) ] = { 539 [ C(OP_READ) ] = { 540 [ C(RESULT_ACCESS) ] = 0x10c000001, 541 [ C(RESULT_MISS) ] = 0x3fb3000001, 542 }, 543 }, 544 }; 545 546 /* 547 * Notes on the events: 548 * - data reads do not include code reads (comparable to earlier tables) 549 * - data counts include speculative execution (except L1 write, dtlb, bpu) 550 * - remote node access includes remote memory, remote cache, remote mmio. 551 * - prefetches are not included in the counts. 552 * - icache miss does not include decoded icache 553 */ 554 555 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 556 #define SKL_DEMAND_RFO BIT_ULL(1) 557 #define SKL_ANY_RESPONSE BIT_ULL(16) 558 #define SKL_SUPPLIER_NONE BIT_ULL(17) 559 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 560 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 561 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 562 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 563 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 564 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 565 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 566 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 567 #define SKL_SPL_HIT BIT_ULL(30) 568 #define SKL_SNOOP_NONE BIT_ULL(31) 569 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 570 #define SKL_SNOOP_MISS BIT_ULL(33) 571 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 572 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 573 #define SKL_SNOOP_HITM BIT_ULL(36) 574 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 575 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 576 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 577 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 578 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 579 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 580 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 581 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 582 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 583 SKL_SNOOP_HITM|SKL_SPL_HIT) 584 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 585 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 586 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 587 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 588 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 589 590 static __initconst const u64 skl_hw_cache_event_ids 591 [PERF_COUNT_HW_CACHE_MAX] 592 [PERF_COUNT_HW_CACHE_OP_MAX] 593 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 594 { 595 [ C(L1D ) ] = { 596 [ C(OP_READ) ] = { 597 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 598 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 599 }, 600 [ C(OP_WRITE) ] = { 601 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 602 [ C(RESULT_MISS) ] = 0x0, 603 }, 604 [ C(OP_PREFETCH) ] = { 605 [ C(RESULT_ACCESS) ] = 0x0, 606 [ C(RESULT_MISS) ] = 0x0, 607 }, 608 }, 609 [ C(L1I ) ] = { 610 [ C(OP_READ) ] = { 611 [ C(RESULT_ACCESS) ] = 0x0, 612 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 613 }, 614 [ C(OP_WRITE) ] = { 615 [ C(RESULT_ACCESS) ] = -1, 616 [ C(RESULT_MISS) ] = -1, 617 }, 618 [ C(OP_PREFETCH) ] = { 619 [ C(RESULT_ACCESS) ] = 0x0, 620 [ C(RESULT_MISS) ] = 0x0, 621 }, 622 }, 623 [ C(LL ) ] = { 624 [ C(OP_READ) ] = { 625 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 626 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 627 }, 628 [ C(OP_WRITE) ] = { 629 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 630 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 631 }, 632 [ C(OP_PREFETCH) ] = { 633 [ C(RESULT_ACCESS) ] = 0x0, 634 [ C(RESULT_MISS) ] = 0x0, 635 }, 636 }, 637 [ C(DTLB) ] = { 638 [ C(OP_READ) ] = { 639 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 640 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 641 }, 642 [ C(OP_WRITE) ] = { 643 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 644 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 645 }, 646 [ C(OP_PREFETCH) ] = { 647 [ C(RESULT_ACCESS) ] = 0x0, 648 [ C(RESULT_MISS) ] = 0x0, 649 }, 650 }, 651 [ C(ITLB) ] = { 652 [ C(OP_READ) ] = { 653 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 654 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 655 }, 656 [ C(OP_WRITE) ] = { 657 [ C(RESULT_ACCESS) ] = -1, 658 [ C(RESULT_MISS) ] = -1, 659 }, 660 [ C(OP_PREFETCH) ] = { 661 [ C(RESULT_ACCESS) ] = -1, 662 [ C(RESULT_MISS) ] = -1, 663 }, 664 }, 665 [ C(BPU ) ] = { 666 [ C(OP_READ) ] = { 667 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 668 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 669 }, 670 [ C(OP_WRITE) ] = { 671 [ C(RESULT_ACCESS) ] = -1, 672 [ C(RESULT_MISS) ] = -1, 673 }, 674 [ C(OP_PREFETCH) ] = { 675 [ C(RESULT_ACCESS) ] = -1, 676 [ C(RESULT_MISS) ] = -1, 677 }, 678 }, 679 [ C(NODE) ] = { 680 [ C(OP_READ) ] = { 681 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 682 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 683 }, 684 [ C(OP_WRITE) ] = { 685 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 686 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 687 }, 688 [ C(OP_PREFETCH) ] = { 689 [ C(RESULT_ACCESS) ] = 0x0, 690 [ C(RESULT_MISS) ] = 0x0, 691 }, 692 }, 693 }; 694 695 static __initconst const u64 skl_hw_cache_extra_regs 696 [PERF_COUNT_HW_CACHE_MAX] 697 [PERF_COUNT_HW_CACHE_OP_MAX] 698 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 699 { 700 [ C(LL ) ] = { 701 [ C(OP_READ) ] = { 702 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 703 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 704 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 705 SKL_L3_MISS|SKL_ANY_SNOOP| 706 SKL_SUPPLIER_NONE, 707 }, 708 [ C(OP_WRITE) ] = { 709 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 710 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 711 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 712 SKL_L3_MISS|SKL_ANY_SNOOP| 713 SKL_SUPPLIER_NONE, 714 }, 715 [ C(OP_PREFETCH) ] = { 716 [ C(RESULT_ACCESS) ] = 0x0, 717 [ C(RESULT_MISS) ] = 0x0, 718 }, 719 }, 720 [ C(NODE) ] = { 721 [ C(OP_READ) ] = { 722 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 723 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 724 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 725 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 726 }, 727 [ C(OP_WRITE) ] = { 728 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 729 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 730 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 731 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 732 }, 733 [ C(OP_PREFETCH) ] = { 734 [ C(RESULT_ACCESS) ] = 0x0, 735 [ C(RESULT_MISS) ] = 0x0, 736 }, 737 }, 738 }; 739 740 #define SNB_DMND_DATA_RD (1ULL << 0) 741 #define SNB_DMND_RFO (1ULL << 1) 742 #define SNB_DMND_IFETCH (1ULL << 2) 743 #define SNB_DMND_WB (1ULL << 3) 744 #define SNB_PF_DATA_RD (1ULL << 4) 745 #define SNB_PF_RFO (1ULL << 5) 746 #define SNB_PF_IFETCH (1ULL << 6) 747 #define SNB_LLC_DATA_RD (1ULL << 7) 748 #define SNB_LLC_RFO (1ULL << 8) 749 #define SNB_LLC_IFETCH (1ULL << 9) 750 #define SNB_BUS_LOCKS (1ULL << 10) 751 #define SNB_STRM_ST (1ULL << 11) 752 #define SNB_OTHER (1ULL << 15) 753 #define SNB_RESP_ANY (1ULL << 16) 754 #define SNB_NO_SUPP (1ULL << 17) 755 #define SNB_LLC_HITM (1ULL << 18) 756 #define SNB_LLC_HITE (1ULL << 19) 757 #define SNB_LLC_HITS (1ULL << 20) 758 #define SNB_LLC_HITF (1ULL << 21) 759 #define SNB_LOCAL (1ULL << 22) 760 #define SNB_REMOTE (0xffULL << 23) 761 #define SNB_SNP_NONE (1ULL << 31) 762 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 763 #define SNB_SNP_MISS (1ULL << 33) 764 #define SNB_NO_FWD (1ULL << 34) 765 #define SNB_SNP_FWD (1ULL << 35) 766 #define SNB_HITM (1ULL << 36) 767 #define SNB_NON_DRAM (1ULL << 37) 768 769 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 770 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 771 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 772 773 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 774 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 775 SNB_HITM) 776 777 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 778 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 779 780 #define SNB_L3_ACCESS SNB_RESP_ANY 781 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 782 783 static __initconst const u64 snb_hw_cache_extra_regs 784 [PERF_COUNT_HW_CACHE_MAX] 785 [PERF_COUNT_HW_CACHE_OP_MAX] 786 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 787 { 788 [ C(LL ) ] = { 789 [ C(OP_READ) ] = { 790 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 791 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 792 }, 793 [ C(OP_WRITE) ] = { 794 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 795 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 796 }, 797 [ C(OP_PREFETCH) ] = { 798 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 799 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 800 }, 801 }, 802 [ C(NODE) ] = { 803 [ C(OP_READ) ] = { 804 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 805 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 806 }, 807 [ C(OP_WRITE) ] = { 808 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 809 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 810 }, 811 [ C(OP_PREFETCH) ] = { 812 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 813 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 814 }, 815 }, 816 }; 817 818 static __initconst const u64 snb_hw_cache_event_ids 819 [PERF_COUNT_HW_CACHE_MAX] 820 [PERF_COUNT_HW_CACHE_OP_MAX] 821 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 822 { 823 [ C(L1D) ] = { 824 [ C(OP_READ) ] = { 825 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 826 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 827 }, 828 [ C(OP_WRITE) ] = { 829 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 830 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 831 }, 832 [ C(OP_PREFETCH) ] = { 833 [ C(RESULT_ACCESS) ] = 0x0, 834 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 835 }, 836 }, 837 [ C(L1I ) ] = { 838 [ C(OP_READ) ] = { 839 [ C(RESULT_ACCESS) ] = 0x0, 840 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 841 }, 842 [ C(OP_WRITE) ] = { 843 [ C(RESULT_ACCESS) ] = -1, 844 [ C(RESULT_MISS) ] = -1, 845 }, 846 [ C(OP_PREFETCH) ] = { 847 [ C(RESULT_ACCESS) ] = 0x0, 848 [ C(RESULT_MISS) ] = 0x0, 849 }, 850 }, 851 [ C(LL ) ] = { 852 [ C(OP_READ) ] = { 853 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 854 [ C(RESULT_ACCESS) ] = 0x01b7, 855 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 856 [ C(RESULT_MISS) ] = 0x01b7, 857 }, 858 [ C(OP_WRITE) ] = { 859 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 860 [ C(RESULT_ACCESS) ] = 0x01b7, 861 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 862 [ C(RESULT_MISS) ] = 0x01b7, 863 }, 864 [ C(OP_PREFETCH) ] = { 865 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 866 [ C(RESULT_ACCESS) ] = 0x01b7, 867 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 868 [ C(RESULT_MISS) ] = 0x01b7, 869 }, 870 }, 871 [ C(DTLB) ] = { 872 [ C(OP_READ) ] = { 873 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 874 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 875 }, 876 [ C(OP_WRITE) ] = { 877 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 878 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 879 }, 880 [ C(OP_PREFETCH) ] = { 881 [ C(RESULT_ACCESS) ] = 0x0, 882 [ C(RESULT_MISS) ] = 0x0, 883 }, 884 }, 885 [ C(ITLB) ] = { 886 [ C(OP_READ) ] = { 887 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 888 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 889 }, 890 [ C(OP_WRITE) ] = { 891 [ C(RESULT_ACCESS) ] = -1, 892 [ C(RESULT_MISS) ] = -1, 893 }, 894 [ C(OP_PREFETCH) ] = { 895 [ C(RESULT_ACCESS) ] = -1, 896 [ C(RESULT_MISS) ] = -1, 897 }, 898 }, 899 [ C(BPU ) ] = { 900 [ C(OP_READ) ] = { 901 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 902 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 903 }, 904 [ C(OP_WRITE) ] = { 905 [ C(RESULT_ACCESS) ] = -1, 906 [ C(RESULT_MISS) ] = -1, 907 }, 908 [ C(OP_PREFETCH) ] = { 909 [ C(RESULT_ACCESS) ] = -1, 910 [ C(RESULT_MISS) ] = -1, 911 }, 912 }, 913 [ C(NODE) ] = { 914 [ C(OP_READ) ] = { 915 [ C(RESULT_ACCESS) ] = 0x01b7, 916 [ C(RESULT_MISS) ] = 0x01b7, 917 }, 918 [ C(OP_WRITE) ] = { 919 [ C(RESULT_ACCESS) ] = 0x01b7, 920 [ C(RESULT_MISS) ] = 0x01b7, 921 }, 922 [ C(OP_PREFETCH) ] = { 923 [ C(RESULT_ACCESS) ] = 0x01b7, 924 [ C(RESULT_MISS) ] = 0x01b7, 925 }, 926 }, 927 928 }; 929 930 /* 931 * Notes on the events: 932 * - data reads do not include code reads (comparable to earlier tables) 933 * - data counts include speculative execution (except L1 write, dtlb, bpu) 934 * - remote node access includes remote memory, remote cache, remote mmio. 935 * - prefetches are not included in the counts because they are not 936 * reliably counted. 937 */ 938 939 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 940 #define HSW_DEMAND_RFO BIT_ULL(1) 941 #define HSW_ANY_RESPONSE BIT_ULL(16) 942 #define HSW_SUPPLIER_NONE BIT_ULL(17) 943 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 944 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 945 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 946 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 947 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 948 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 949 HSW_L3_MISS_REMOTE_HOP2P) 950 #define HSW_SNOOP_NONE BIT_ULL(31) 951 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 952 #define HSW_SNOOP_MISS BIT_ULL(33) 953 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 954 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 955 #define HSW_SNOOP_HITM BIT_ULL(36) 956 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 957 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 958 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 959 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 960 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 961 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 962 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 963 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 964 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 965 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 966 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 967 968 #define BDW_L3_MISS_LOCAL BIT(26) 969 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 970 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 971 HSW_L3_MISS_REMOTE_HOP2P) 972 973 974 static __initconst const u64 hsw_hw_cache_event_ids 975 [PERF_COUNT_HW_CACHE_MAX] 976 [PERF_COUNT_HW_CACHE_OP_MAX] 977 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 978 { 979 [ C(L1D ) ] = { 980 [ C(OP_READ) ] = { 981 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 982 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 983 }, 984 [ C(OP_WRITE) ] = { 985 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 986 [ C(RESULT_MISS) ] = 0x0, 987 }, 988 [ C(OP_PREFETCH) ] = { 989 [ C(RESULT_ACCESS) ] = 0x0, 990 [ C(RESULT_MISS) ] = 0x0, 991 }, 992 }, 993 [ C(L1I ) ] = { 994 [ C(OP_READ) ] = { 995 [ C(RESULT_ACCESS) ] = 0x0, 996 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 997 }, 998 [ C(OP_WRITE) ] = { 999 [ C(RESULT_ACCESS) ] = -1, 1000 [ C(RESULT_MISS) ] = -1, 1001 }, 1002 [ C(OP_PREFETCH) ] = { 1003 [ C(RESULT_ACCESS) ] = 0x0, 1004 [ C(RESULT_MISS) ] = 0x0, 1005 }, 1006 }, 1007 [ C(LL ) ] = { 1008 [ C(OP_READ) ] = { 1009 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1010 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1011 }, 1012 [ C(OP_WRITE) ] = { 1013 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1014 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1015 }, 1016 [ C(OP_PREFETCH) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x0, 1018 [ C(RESULT_MISS) ] = 0x0, 1019 }, 1020 }, 1021 [ C(DTLB) ] = { 1022 [ C(OP_READ) ] = { 1023 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1024 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1025 }, 1026 [ C(OP_WRITE) ] = { 1027 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1028 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1029 }, 1030 [ C(OP_PREFETCH) ] = { 1031 [ C(RESULT_ACCESS) ] = 0x0, 1032 [ C(RESULT_MISS) ] = 0x0, 1033 }, 1034 }, 1035 [ C(ITLB) ] = { 1036 [ C(OP_READ) ] = { 1037 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1038 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1039 }, 1040 [ C(OP_WRITE) ] = { 1041 [ C(RESULT_ACCESS) ] = -1, 1042 [ C(RESULT_MISS) ] = -1, 1043 }, 1044 [ C(OP_PREFETCH) ] = { 1045 [ C(RESULT_ACCESS) ] = -1, 1046 [ C(RESULT_MISS) ] = -1, 1047 }, 1048 }, 1049 [ C(BPU ) ] = { 1050 [ C(OP_READ) ] = { 1051 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1052 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1053 }, 1054 [ C(OP_WRITE) ] = { 1055 [ C(RESULT_ACCESS) ] = -1, 1056 [ C(RESULT_MISS) ] = -1, 1057 }, 1058 [ C(OP_PREFETCH) ] = { 1059 [ C(RESULT_ACCESS) ] = -1, 1060 [ C(RESULT_MISS) ] = -1, 1061 }, 1062 }, 1063 [ C(NODE) ] = { 1064 [ C(OP_READ) ] = { 1065 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1066 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1067 }, 1068 [ C(OP_WRITE) ] = { 1069 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1070 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1071 }, 1072 [ C(OP_PREFETCH) ] = { 1073 [ C(RESULT_ACCESS) ] = 0x0, 1074 [ C(RESULT_MISS) ] = 0x0, 1075 }, 1076 }, 1077 }; 1078 1079 static __initconst const u64 hsw_hw_cache_extra_regs 1080 [PERF_COUNT_HW_CACHE_MAX] 1081 [PERF_COUNT_HW_CACHE_OP_MAX] 1082 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1083 { 1084 [ C(LL ) ] = { 1085 [ C(OP_READ) ] = { 1086 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1087 HSW_LLC_ACCESS, 1088 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1089 HSW_L3_MISS|HSW_ANY_SNOOP, 1090 }, 1091 [ C(OP_WRITE) ] = { 1092 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1093 HSW_LLC_ACCESS, 1094 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1095 HSW_L3_MISS|HSW_ANY_SNOOP, 1096 }, 1097 [ C(OP_PREFETCH) ] = { 1098 [ C(RESULT_ACCESS) ] = 0x0, 1099 [ C(RESULT_MISS) ] = 0x0, 1100 }, 1101 }, 1102 [ C(NODE) ] = { 1103 [ C(OP_READ) ] = { 1104 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1105 HSW_L3_MISS_LOCAL_DRAM| 1106 HSW_SNOOP_DRAM, 1107 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1108 HSW_L3_MISS_REMOTE| 1109 HSW_SNOOP_DRAM, 1110 }, 1111 [ C(OP_WRITE) ] = { 1112 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1113 HSW_L3_MISS_LOCAL_DRAM| 1114 HSW_SNOOP_DRAM, 1115 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1116 HSW_L3_MISS_REMOTE| 1117 HSW_SNOOP_DRAM, 1118 }, 1119 [ C(OP_PREFETCH) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x0, 1121 [ C(RESULT_MISS) ] = 0x0, 1122 }, 1123 }, 1124 }; 1125 1126 static __initconst const u64 westmere_hw_cache_event_ids 1127 [PERF_COUNT_HW_CACHE_MAX] 1128 [PERF_COUNT_HW_CACHE_OP_MAX] 1129 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1130 { 1131 [ C(L1D) ] = { 1132 [ C(OP_READ) ] = { 1133 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1134 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1135 }, 1136 [ C(OP_WRITE) ] = { 1137 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1138 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1139 }, 1140 [ C(OP_PREFETCH) ] = { 1141 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1142 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1143 }, 1144 }, 1145 [ C(L1I ) ] = { 1146 [ C(OP_READ) ] = { 1147 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1148 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1149 }, 1150 [ C(OP_WRITE) ] = { 1151 [ C(RESULT_ACCESS) ] = -1, 1152 [ C(RESULT_MISS) ] = -1, 1153 }, 1154 [ C(OP_PREFETCH) ] = { 1155 [ C(RESULT_ACCESS) ] = 0x0, 1156 [ C(RESULT_MISS) ] = 0x0, 1157 }, 1158 }, 1159 [ C(LL ) ] = { 1160 [ C(OP_READ) ] = { 1161 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1162 [ C(RESULT_ACCESS) ] = 0x01b7, 1163 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1164 [ C(RESULT_MISS) ] = 0x01b7, 1165 }, 1166 /* 1167 * Use RFO, not WRITEBACK, because a write miss would typically occur 1168 * on RFO. 1169 */ 1170 [ C(OP_WRITE) ] = { 1171 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1172 [ C(RESULT_ACCESS) ] = 0x01b7, 1173 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1174 [ C(RESULT_MISS) ] = 0x01b7, 1175 }, 1176 [ C(OP_PREFETCH) ] = { 1177 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1178 [ C(RESULT_ACCESS) ] = 0x01b7, 1179 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1180 [ C(RESULT_MISS) ] = 0x01b7, 1181 }, 1182 }, 1183 [ C(DTLB) ] = { 1184 [ C(OP_READ) ] = { 1185 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1186 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1187 }, 1188 [ C(OP_WRITE) ] = { 1189 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1190 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1191 }, 1192 [ C(OP_PREFETCH) ] = { 1193 [ C(RESULT_ACCESS) ] = 0x0, 1194 [ C(RESULT_MISS) ] = 0x0, 1195 }, 1196 }, 1197 [ C(ITLB) ] = { 1198 [ C(OP_READ) ] = { 1199 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1200 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1201 }, 1202 [ C(OP_WRITE) ] = { 1203 [ C(RESULT_ACCESS) ] = -1, 1204 [ C(RESULT_MISS) ] = -1, 1205 }, 1206 [ C(OP_PREFETCH) ] = { 1207 [ C(RESULT_ACCESS) ] = -1, 1208 [ C(RESULT_MISS) ] = -1, 1209 }, 1210 }, 1211 [ C(BPU ) ] = { 1212 [ C(OP_READ) ] = { 1213 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1214 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1215 }, 1216 [ C(OP_WRITE) ] = { 1217 [ C(RESULT_ACCESS) ] = -1, 1218 [ C(RESULT_MISS) ] = -1, 1219 }, 1220 [ C(OP_PREFETCH) ] = { 1221 [ C(RESULT_ACCESS) ] = -1, 1222 [ C(RESULT_MISS) ] = -1, 1223 }, 1224 }, 1225 [ C(NODE) ] = { 1226 [ C(OP_READ) ] = { 1227 [ C(RESULT_ACCESS) ] = 0x01b7, 1228 [ C(RESULT_MISS) ] = 0x01b7, 1229 }, 1230 [ C(OP_WRITE) ] = { 1231 [ C(RESULT_ACCESS) ] = 0x01b7, 1232 [ C(RESULT_MISS) ] = 0x01b7, 1233 }, 1234 [ C(OP_PREFETCH) ] = { 1235 [ C(RESULT_ACCESS) ] = 0x01b7, 1236 [ C(RESULT_MISS) ] = 0x01b7, 1237 }, 1238 }, 1239 }; 1240 1241 /* 1242 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1243 * See IA32 SDM Vol 3B 30.6.1.3 1244 */ 1245 1246 #define NHM_DMND_DATA_RD (1 << 0) 1247 #define NHM_DMND_RFO (1 << 1) 1248 #define NHM_DMND_IFETCH (1 << 2) 1249 #define NHM_DMND_WB (1 << 3) 1250 #define NHM_PF_DATA_RD (1 << 4) 1251 #define NHM_PF_DATA_RFO (1 << 5) 1252 #define NHM_PF_IFETCH (1 << 6) 1253 #define NHM_OFFCORE_OTHER (1 << 7) 1254 #define NHM_UNCORE_HIT (1 << 8) 1255 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1256 #define NHM_OTHER_CORE_HITM (1 << 10) 1257 /* reserved */ 1258 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1259 #define NHM_REMOTE_DRAM (1 << 13) 1260 #define NHM_LOCAL_DRAM (1 << 14) 1261 #define NHM_NON_DRAM (1 << 15) 1262 1263 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1264 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1265 1266 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1267 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1268 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1269 1270 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1271 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1272 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1273 1274 static __initconst const u64 nehalem_hw_cache_extra_regs 1275 [PERF_COUNT_HW_CACHE_MAX] 1276 [PERF_COUNT_HW_CACHE_OP_MAX] 1277 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1278 { 1279 [ C(LL ) ] = { 1280 [ C(OP_READ) ] = { 1281 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1282 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1283 }, 1284 [ C(OP_WRITE) ] = { 1285 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1286 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1287 }, 1288 [ C(OP_PREFETCH) ] = { 1289 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1290 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1291 }, 1292 }, 1293 [ C(NODE) ] = { 1294 [ C(OP_READ) ] = { 1295 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1296 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1297 }, 1298 [ C(OP_WRITE) ] = { 1299 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1300 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1301 }, 1302 [ C(OP_PREFETCH) ] = { 1303 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1304 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1305 }, 1306 }, 1307 }; 1308 1309 static __initconst const u64 nehalem_hw_cache_event_ids 1310 [PERF_COUNT_HW_CACHE_MAX] 1311 [PERF_COUNT_HW_CACHE_OP_MAX] 1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1313 { 1314 [ C(L1D) ] = { 1315 [ C(OP_READ) ] = { 1316 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1317 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1318 }, 1319 [ C(OP_WRITE) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1321 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1322 }, 1323 [ C(OP_PREFETCH) ] = { 1324 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1325 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1326 }, 1327 }, 1328 [ C(L1I ) ] = { 1329 [ C(OP_READ) ] = { 1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1332 }, 1333 [ C(OP_WRITE) ] = { 1334 [ C(RESULT_ACCESS) ] = -1, 1335 [ C(RESULT_MISS) ] = -1, 1336 }, 1337 [ C(OP_PREFETCH) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x0, 1339 [ C(RESULT_MISS) ] = 0x0, 1340 }, 1341 }, 1342 [ C(LL ) ] = { 1343 [ C(OP_READ) ] = { 1344 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1345 [ C(RESULT_ACCESS) ] = 0x01b7, 1346 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1347 [ C(RESULT_MISS) ] = 0x01b7, 1348 }, 1349 /* 1350 * Use RFO, not WRITEBACK, because a write miss would typically occur 1351 * on RFO. 1352 */ 1353 [ C(OP_WRITE) ] = { 1354 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1355 [ C(RESULT_ACCESS) ] = 0x01b7, 1356 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1357 [ C(RESULT_MISS) ] = 0x01b7, 1358 }, 1359 [ C(OP_PREFETCH) ] = { 1360 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1361 [ C(RESULT_ACCESS) ] = 0x01b7, 1362 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1363 [ C(RESULT_MISS) ] = 0x01b7, 1364 }, 1365 }, 1366 [ C(DTLB) ] = { 1367 [ C(OP_READ) ] = { 1368 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1369 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1370 }, 1371 [ C(OP_WRITE) ] = { 1372 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1373 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1374 }, 1375 [ C(OP_PREFETCH) ] = { 1376 [ C(RESULT_ACCESS) ] = 0x0, 1377 [ C(RESULT_MISS) ] = 0x0, 1378 }, 1379 }, 1380 [ C(ITLB) ] = { 1381 [ C(OP_READ) ] = { 1382 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1383 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1384 }, 1385 [ C(OP_WRITE) ] = { 1386 [ C(RESULT_ACCESS) ] = -1, 1387 [ C(RESULT_MISS) ] = -1, 1388 }, 1389 [ C(OP_PREFETCH) ] = { 1390 [ C(RESULT_ACCESS) ] = -1, 1391 [ C(RESULT_MISS) ] = -1, 1392 }, 1393 }, 1394 [ C(BPU ) ] = { 1395 [ C(OP_READ) ] = { 1396 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1397 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1398 }, 1399 [ C(OP_WRITE) ] = { 1400 [ C(RESULT_ACCESS) ] = -1, 1401 [ C(RESULT_MISS) ] = -1, 1402 }, 1403 [ C(OP_PREFETCH) ] = { 1404 [ C(RESULT_ACCESS) ] = -1, 1405 [ C(RESULT_MISS) ] = -1, 1406 }, 1407 }, 1408 [ C(NODE) ] = { 1409 [ C(OP_READ) ] = { 1410 [ C(RESULT_ACCESS) ] = 0x01b7, 1411 [ C(RESULT_MISS) ] = 0x01b7, 1412 }, 1413 [ C(OP_WRITE) ] = { 1414 [ C(RESULT_ACCESS) ] = 0x01b7, 1415 [ C(RESULT_MISS) ] = 0x01b7, 1416 }, 1417 [ C(OP_PREFETCH) ] = { 1418 [ C(RESULT_ACCESS) ] = 0x01b7, 1419 [ C(RESULT_MISS) ] = 0x01b7, 1420 }, 1421 }, 1422 }; 1423 1424 static __initconst const u64 core2_hw_cache_event_ids 1425 [PERF_COUNT_HW_CACHE_MAX] 1426 [PERF_COUNT_HW_CACHE_OP_MAX] 1427 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1428 { 1429 [ C(L1D) ] = { 1430 [ C(OP_READ) ] = { 1431 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1432 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1433 }, 1434 [ C(OP_WRITE) ] = { 1435 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1436 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1437 }, 1438 [ C(OP_PREFETCH) ] = { 1439 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1440 [ C(RESULT_MISS) ] = 0, 1441 }, 1442 }, 1443 [ C(L1I ) ] = { 1444 [ C(OP_READ) ] = { 1445 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1446 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1447 }, 1448 [ C(OP_WRITE) ] = { 1449 [ C(RESULT_ACCESS) ] = -1, 1450 [ C(RESULT_MISS) ] = -1, 1451 }, 1452 [ C(OP_PREFETCH) ] = { 1453 [ C(RESULT_ACCESS) ] = 0, 1454 [ C(RESULT_MISS) ] = 0, 1455 }, 1456 }, 1457 [ C(LL ) ] = { 1458 [ C(OP_READ) ] = { 1459 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1460 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1461 }, 1462 [ C(OP_WRITE) ] = { 1463 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1464 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1465 }, 1466 [ C(OP_PREFETCH) ] = { 1467 [ C(RESULT_ACCESS) ] = 0, 1468 [ C(RESULT_MISS) ] = 0, 1469 }, 1470 }, 1471 [ C(DTLB) ] = { 1472 [ C(OP_READ) ] = { 1473 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1474 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1475 }, 1476 [ C(OP_WRITE) ] = { 1477 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1478 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1479 }, 1480 [ C(OP_PREFETCH) ] = { 1481 [ C(RESULT_ACCESS) ] = 0, 1482 [ C(RESULT_MISS) ] = 0, 1483 }, 1484 }, 1485 [ C(ITLB) ] = { 1486 [ C(OP_READ) ] = { 1487 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1488 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1489 }, 1490 [ C(OP_WRITE) ] = { 1491 [ C(RESULT_ACCESS) ] = -1, 1492 [ C(RESULT_MISS) ] = -1, 1493 }, 1494 [ C(OP_PREFETCH) ] = { 1495 [ C(RESULT_ACCESS) ] = -1, 1496 [ C(RESULT_MISS) ] = -1, 1497 }, 1498 }, 1499 [ C(BPU ) ] = { 1500 [ C(OP_READ) ] = { 1501 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1502 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1503 }, 1504 [ C(OP_WRITE) ] = { 1505 [ C(RESULT_ACCESS) ] = -1, 1506 [ C(RESULT_MISS) ] = -1, 1507 }, 1508 [ C(OP_PREFETCH) ] = { 1509 [ C(RESULT_ACCESS) ] = -1, 1510 [ C(RESULT_MISS) ] = -1, 1511 }, 1512 }, 1513 }; 1514 1515 static __initconst const u64 atom_hw_cache_event_ids 1516 [PERF_COUNT_HW_CACHE_MAX] 1517 [PERF_COUNT_HW_CACHE_OP_MAX] 1518 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1519 { 1520 [ C(L1D) ] = { 1521 [ C(OP_READ) ] = { 1522 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1523 [ C(RESULT_MISS) ] = 0, 1524 }, 1525 [ C(OP_WRITE) ] = { 1526 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1527 [ C(RESULT_MISS) ] = 0, 1528 }, 1529 [ C(OP_PREFETCH) ] = { 1530 [ C(RESULT_ACCESS) ] = 0x0, 1531 [ C(RESULT_MISS) ] = 0, 1532 }, 1533 }, 1534 [ C(L1I ) ] = { 1535 [ C(OP_READ) ] = { 1536 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1537 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1538 }, 1539 [ C(OP_WRITE) ] = { 1540 [ C(RESULT_ACCESS) ] = -1, 1541 [ C(RESULT_MISS) ] = -1, 1542 }, 1543 [ C(OP_PREFETCH) ] = { 1544 [ C(RESULT_ACCESS) ] = 0, 1545 [ C(RESULT_MISS) ] = 0, 1546 }, 1547 }, 1548 [ C(LL ) ] = { 1549 [ C(OP_READ) ] = { 1550 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1551 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1552 }, 1553 [ C(OP_WRITE) ] = { 1554 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1555 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1556 }, 1557 [ C(OP_PREFETCH) ] = { 1558 [ C(RESULT_ACCESS) ] = 0, 1559 [ C(RESULT_MISS) ] = 0, 1560 }, 1561 }, 1562 [ C(DTLB) ] = { 1563 [ C(OP_READ) ] = { 1564 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1565 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1566 }, 1567 [ C(OP_WRITE) ] = { 1568 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1569 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1570 }, 1571 [ C(OP_PREFETCH) ] = { 1572 [ C(RESULT_ACCESS) ] = 0, 1573 [ C(RESULT_MISS) ] = 0, 1574 }, 1575 }, 1576 [ C(ITLB) ] = { 1577 [ C(OP_READ) ] = { 1578 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1579 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1580 }, 1581 [ C(OP_WRITE) ] = { 1582 [ C(RESULT_ACCESS) ] = -1, 1583 [ C(RESULT_MISS) ] = -1, 1584 }, 1585 [ C(OP_PREFETCH) ] = { 1586 [ C(RESULT_ACCESS) ] = -1, 1587 [ C(RESULT_MISS) ] = -1, 1588 }, 1589 }, 1590 [ C(BPU ) ] = { 1591 [ C(OP_READ) ] = { 1592 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1593 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1594 }, 1595 [ C(OP_WRITE) ] = { 1596 [ C(RESULT_ACCESS) ] = -1, 1597 [ C(RESULT_MISS) ] = -1, 1598 }, 1599 [ C(OP_PREFETCH) ] = { 1600 [ C(RESULT_ACCESS) ] = -1, 1601 [ C(RESULT_MISS) ] = -1, 1602 }, 1603 }, 1604 }; 1605 1606 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1607 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1608 /* no_alloc_cycles.not_delivered */ 1609 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1610 "event=0xca,umask=0x50"); 1611 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1612 /* uops_retired.all */ 1613 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1614 "event=0xc2,umask=0x10"); 1615 /* uops_retired.all */ 1616 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1617 "event=0xc2,umask=0x10"); 1618 1619 static struct attribute *slm_events_attrs[] = { 1620 EVENT_PTR(td_total_slots_slm), 1621 EVENT_PTR(td_total_slots_scale_slm), 1622 EVENT_PTR(td_fetch_bubbles_slm), 1623 EVENT_PTR(td_fetch_bubbles_scale_slm), 1624 EVENT_PTR(td_slots_issued_slm), 1625 EVENT_PTR(td_slots_retired_slm), 1626 NULL 1627 }; 1628 1629 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1630 { 1631 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1632 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1633 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1634 EVENT_EXTRA_END 1635 }; 1636 1637 #define SLM_DMND_READ SNB_DMND_DATA_RD 1638 #define SLM_DMND_WRITE SNB_DMND_RFO 1639 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1640 1641 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1642 #define SLM_LLC_ACCESS SNB_RESP_ANY 1643 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1644 1645 static __initconst const u64 slm_hw_cache_extra_regs 1646 [PERF_COUNT_HW_CACHE_MAX] 1647 [PERF_COUNT_HW_CACHE_OP_MAX] 1648 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1649 { 1650 [ C(LL ) ] = { 1651 [ C(OP_READ) ] = { 1652 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1653 [ C(RESULT_MISS) ] = 0, 1654 }, 1655 [ C(OP_WRITE) ] = { 1656 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1657 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1658 }, 1659 [ C(OP_PREFETCH) ] = { 1660 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1661 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1662 }, 1663 }, 1664 }; 1665 1666 static __initconst const u64 slm_hw_cache_event_ids 1667 [PERF_COUNT_HW_CACHE_MAX] 1668 [PERF_COUNT_HW_CACHE_OP_MAX] 1669 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1670 { 1671 [ C(L1D) ] = { 1672 [ C(OP_READ) ] = { 1673 [ C(RESULT_ACCESS) ] = 0, 1674 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1675 }, 1676 [ C(OP_WRITE) ] = { 1677 [ C(RESULT_ACCESS) ] = 0, 1678 [ C(RESULT_MISS) ] = 0, 1679 }, 1680 [ C(OP_PREFETCH) ] = { 1681 [ C(RESULT_ACCESS) ] = 0, 1682 [ C(RESULT_MISS) ] = 0, 1683 }, 1684 }, 1685 [ C(L1I ) ] = { 1686 [ C(OP_READ) ] = { 1687 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1688 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1689 }, 1690 [ C(OP_WRITE) ] = { 1691 [ C(RESULT_ACCESS) ] = -1, 1692 [ C(RESULT_MISS) ] = -1, 1693 }, 1694 [ C(OP_PREFETCH) ] = { 1695 [ C(RESULT_ACCESS) ] = 0, 1696 [ C(RESULT_MISS) ] = 0, 1697 }, 1698 }, 1699 [ C(LL ) ] = { 1700 [ C(OP_READ) ] = { 1701 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1702 [ C(RESULT_ACCESS) ] = 0x01b7, 1703 [ C(RESULT_MISS) ] = 0, 1704 }, 1705 [ C(OP_WRITE) ] = { 1706 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1707 [ C(RESULT_ACCESS) ] = 0x01b7, 1708 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1709 [ C(RESULT_MISS) ] = 0x01b7, 1710 }, 1711 [ C(OP_PREFETCH) ] = { 1712 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1713 [ C(RESULT_ACCESS) ] = 0x01b7, 1714 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1715 [ C(RESULT_MISS) ] = 0x01b7, 1716 }, 1717 }, 1718 [ C(DTLB) ] = { 1719 [ C(OP_READ) ] = { 1720 [ C(RESULT_ACCESS) ] = 0, 1721 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1722 }, 1723 [ C(OP_WRITE) ] = { 1724 [ C(RESULT_ACCESS) ] = 0, 1725 [ C(RESULT_MISS) ] = 0, 1726 }, 1727 [ C(OP_PREFETCH) ] = { 1728 [ C(RESULT_ACCESS) ] = 0, 1729 [ C(RESULT_MISS) ] = 0, 1730 }, 1731 }, 1732 [ C(ITLB) ] = { 1733 [ C(OP_READ) ] = { 1734 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1735 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1736 }, 1737 [ C(OP_WRITE) ] = { 1738 [ C(RESULT_ACCESS) ] = -1, 1739 [ C(RESULT_MISS) ] = -1, 1740 }, 1741 [ C(OP_PREFETCH) ] = { 1742 [ C(RESULT_ACCESS) ] = -1, 1743 [ C(RESULT_MISS) ] = -1, 1744 }, 1745 }, 1746 [ C(BPU ) ] = { 1747 [ C(OP_READ) ] = { 1748 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1749 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1750 }, 1751 [ C(OP_WRITE) ] = { 1752 [ C(RESULT_ACCESS) ] = -1, 1753 [ C(RESULT_MISS) ] = -1, 1754 }, 1755 [ C(OP_PREFETCH) ] = { 1756 [ C(RESULT_ACCESS) ] = -1, 1757 [ C(RESULT_MISS) ] = -1, 1758 }, 1759 }, 1760 }; 1761 1762 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1763 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1764 /* UOPS_NOT_DELIVERED.ANY */ 1765 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1766 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1767 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1768 /* UOPS_RETIRED.ANY */ 1769 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1770 /* UOPS_ISSUED.ANY */ 1771 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1772 1773 static struct attribute *glm_events_attrs[] = { 1774 EVENT_PTR(td_total_slots_glm), 1775 EVENT_PTR(td_total_slots_scale_glm), 1776 EVENT_PTR(td_fetch_bubbles_glm), 1777 EVENT_PTR(td_recovery_bubbles_glm), 1778 EVENT_PTR(td_slots_issued_glm), 1779 EVENT_PTR(td_slots_retired_glm), 1780 NULL 1781 }; 1782 1783 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1784 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1785 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1786 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1787 EVENT_EXTRA_END 1788 }; 1789 1790 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1791 #define GLM_DEMAND_RFO BIT_ULL(1) 1792 #define GLM_ANY_RESPONSE BIT_ULL(16) 1793 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1794 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1795 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1796 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1797 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1798 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1799 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1800 1801 static __initconst const u64 glm_hw_cache_event_ids 1802 [PERF_COUNT_HW_CACHE_MAX] 1803 [PERF_COUNT_HW_CACHE_OP_MAX] 1804 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1805 [C(L1D)] = { 1806 [C(OP_READ)] = { 1807 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1808 [C(RESULT_MISS)] = 0x0, 1809 }, 1810 [C(OP_WRITE)] = { 1811 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1812 [C(RESULT_MISS)] = 0x0, 1813 }, 1814 [C(OP_PREFETCH)] = { 1815 [C(RESULT_ACCESS)] = 0x0, 1816 [C(RESULT_MISS)] = 0x0, 1817 }, 1818 }, 1819 [C(L1I)] = { 1820 [C(OP_READ)] = { 1821 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1822 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1823 }, 1824 [C(OP_WRITE)] = { 1825 [C(RESULT_ACCESS)] = -1, 1826 [C(RESULT_MISS)] = -1, 1827 }, 1828 [C(OP_PREFETCH)] = { 1829 [C(RESULT_ACCESS)] = 0x0, 1830 [C(RESULT_MISS)] = 0x0, 1831 }, 1832 }, 1833 [C(LL)] = { 1834 [C(OP_READ)] = { 1835 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1836 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1837 }, 1838 [C(OP_WRITE)] = { 1839 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1840 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1841 }, 1842 [C(OP_PREFETCH)] = { 1843 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1844 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1845 }, 1846 }, 1847 [C(DTLB)] = { 1848 [C(OP_READ)] = { 1849 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1850 [C(RESULT_MISS)] = 0x0, 1851 }, 1852 [C(OP_WRITE)] = { 1853 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1854 [C(RESULT_MISS)] = 0x0, 1855 }, 1856 [C(OP_PREFETCH)] = { 1857 [C(RESULT_ACCESS)] = 0x0, 1858 [C(RESULT_MISS)] = 0x0, 1859 }, 1860 }, 1861 [C(ITLB)] = { 1862 [C(OP_READ)] = { 1863 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1864 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1865 }, 1866 [C(OP_WRITE)] = { 1867 [C(RESULT_ACCESS)] = -1, 1868 [C(RESULT_MISS)] = -1, 1869 }, 1870 [C(OP_PREFETCH)] = { 1871 [C(RESULT_ACCESS)] = -1, 1872 [C(RESULT_MISS)] = -1, 1873 }, 1874 }, 1875 [C(BPU)] = { 1876 [C(OP_READ)] = { 1877 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1878 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1879 }, 1880 [C(OP_WRITE)] = { 1881 [C(RESULT_ACCESS)] = -1, 1882 [C(RESULT_MISS)] = -1, 1883 }, 1884 [C(OP_PREFETCH)] = { 1885 [C(RESULT_ACCESS)] = -1, 1886 [C(RESULT_MISS)] = -1, 1887 }, 1888 }, 1889 }; 1890 1891 static __initconst const u64 glm_hw_cache_extra_regs 1892 [PERF_COUNT_HW_CACHE_MAX] 1893 [PERF_COUNT_HW_CACHE_OP_MAX] 1894 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1895 [C(LL)] = { 1896 [C(OP_READ)] = { 1897 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1898 GLM_LLC_ACCESS, 1899 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1900 GLM_LLC_MISS, 1901 }, 1902 [C(OP_WRITE)] = { 1903 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1904 GLM_LLC_ACCESS, 1905 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1906 GLM_LLC_MISS, 1907 }, 1908 [C(OP_PREFETCH)] = { 1909 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1910 GLM_LLC_ACCESS, 1911 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1912 GLM_LLC_MISS, 1913 }, 1914 }, 1915 }; 1916 1917 static __initconst const u64 glp_hw_cache_event_ids 1918 [PERF_COUNT_HW_CACHE_MAX] 1919 [PERF_COUNT_HW_CACHE_OP_MAX] 1920 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1921 [C(L1D)] = { 1922 [C(OP_READ)] = { 1923 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1924 [C(RESULT_MISS)] = 0x0, 1925 }, 1926 [C(OP_WRITE)] = { 1927 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1928 [C(RESULT_MISS)] = 0x0, 1929 }, 1930 [C(OP_PREFETCH)] = { 1931 [C(RESULT_ACCESS)] = 0x0, 1932 [C(RESULT_MISS)] = 0x0, 1933 }, 1934 }, 1935 [C(L1I)] = { 1936 [C(OP_READ)] = { 1937 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1938 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1939 }, 1940 [C(OP_WRITE)] = { 1941 [C(RESULT_ACCESS)] = -1, 1942 [C(RESULT_MISS)] = -1, 1943 }, 1944 [C(OP_PREFETCH)] = { 1945 [C(RESULT_ACCESS)] = 0x0, 1946 [C(RESULT_MISS)] = 0x0, 1947 }, 1948 }, 1949 [C(LL)] = { 1950 [C(OP_READ)] = { 1951 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1953 }, 1954 [C(OP_WRITE)] = { 1955 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1956 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1957 }, 1958 [C(OP_PREFETCH)] = { 1959 [C(RESULT_ACCESS)] = 0x0, 1960 [C(RESULT_MISS)] = 0x0, 1961 }, 1962 }, 1963 [C(DTLB)] = { 1964 [C(OP_READ)] = { 1965 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1966 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1967 }, 1968 [C(OP_WRITE)] = { 1969 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1970 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1971 }, 1972 [C(OP_PREFETCH)] = { 1973 [C(RESULT_ACCESS)] = 0x0, 1974 [C(RESULT_MISS)] = 0x0, 1975 }, 1976 }, 1977 [C(ITLB)] = { 1978 [C(OP_READ)] = { 1979 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1980 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1981 }, 1982 [C(OP_WRITE)] = { 1983 [C(RESULT_ACCESS)] = -1, 1984 [C(RESULT_MISS)] = -1, 1985 }, 1986 [C(OP_PREFETCH)] = { 1987 [C(RESULT_ACCESS)] = -1, 1988 [C(RESULT_MISS)] = -1, 1989 }, 1990 }, 1991 [C(BPU)] = { 1992 [C(OP_READ)] = { 1993 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1994 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1995 }, 1996 [C(OP_WRITE)] = { 1997 [C(RESULT_ACCESS)] = -1, 1998 [C(RESULT_MISS)] = -1, 1999 }, 2000 [C(OP_PREFETCH)] = { 2001 [C(RESULT_ACCESS)] = -1, 2002 [C(RESULT_MISS)] = -1, 2003 }, 2004 }, 2005 }; 2006 2007 static __initconst const u64 glp_hw_cache_extra_regs 2008 [PERF_COUNT_HW_CACHE_MAX] 2009 [PERF_COUNT_HW_CACHE_OP_MAX] 2010 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2011 [C(LL)] = { 2012 [C(OP_READ)] = { 2013 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2014 GLM_LLC_ACCESS, 2015 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2016 GLM_LLC_MISS, 2017 }, 2018 [C(OP_WRITE)] = { 2019 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2020 GLM_LLC_ACCESS, 2021 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2022 GLM_LLC_MISS, 2023 }, 2024 [C(OP_PREFETCH)] = { 2025 [C(RESULT_ACCESS)] = 0x0, 2026 [C(RESULT_MISS)] = 0x0, 2027 }, 2028 }, 2029 }; 2030 2031 #define TNT_LOCAL_DRAM BIT_ULL(26) 2032 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2033 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2034 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2035 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2036 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2037 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2038 2039 static __initconst const u64 tnt_hw_cache_extra_regs 2040 [PERF_COUNT_HW_CACHE_MAX] 2041 [PERF_COUNT_HW_CACHE_OP_MAX] 2042 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2043 [C(LL)] = { 2044 [C(OP_READ)] = { 2045 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2046 TNT_LLC_ACCESS, 2047 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2048 TNT_LLC_MISS, 2049 }, 2050 [C(OP_WRITE)] = { 2051 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2052 TNT_LLC_ACCESS, 2053 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2054 TNT_LLC_MISS, 2055 }, 2056 [C(OP_PREFETCH)] = { 2057 [C(RESULT_ACCESS)] = 0x0, 2058 [C(RESULT_MISS)] = 0x0, 2059 }, 2060 }, 2061 }; 2062 2063 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2064 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2065 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2066 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2067 2068 static struct attribute *tnt_events_attrs[] = { 2069 EVENT_PTR(td_fe_bound_tnt), 2070 EVENT_PTR(td_retiring_tnt), 2071 EVENT_PTR(td_bad_spec_tnt), 2072 EVENT_PTR(td_be_bound_tnt), 2073 NULL, 2074 }; 2075 2076 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2077 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2078 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2079 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2080 EVENT_EXTRA_END 2081 }; 2082 2083 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2084 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2085 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2086 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2087 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2088 EVENT_EXTRA_END 2089 }; 2090 2091 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2092 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2093 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2094 #define KNL_MCDRAM_FAR BIT_ULL(22) 2095 #define KNL_DDR_LOCAL BIT_ULL(23) 2096 #define KNL_DDR_FAR BIT_ULL(24) 2097 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2098 KNL_DDR_LOCAL | KNL_DDR_FAR) 2099 #define KNL_L2_READ SLM_DMND_READ 2100 #define KNL_L2_WRITE SLM_DMND_WRITE 2101 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2102 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2103 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2104 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2105 SNB_NON_DRAM) 2106 2107 static __initconst const u64 knl_hw_cache_extra_regs 2108 [PERF_COUNT_HW_CACHE_MAX] 2109 [PERF_COUNT_HW_CACHE_OP_MAX] 2110 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2111 [C(LL)] = { 2112 [C(OP_READ)] = { 2113 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2114 [C(RESULT_MISS)] = 0, 2115 }, 2116 [C(OP_WRITE)] = { 2117 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2118 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2119 }, 2120 [C(OP_PREFETCH)] = { 2121 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2122 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2123 }, 2124 }, 2125 }; 2126 2127 /* 2128 * Used from PMIs where the LBRs are already disabled. 2129 * 2130 * This function could be called consecutively. It is required to remain in 2131 * disabled state if called consecutively. 2132 * 2133 * During consecutive calls, the same disable value will be written to related 2134 * registers, so the PMU state remains unchanged. 2135 * 2136 * intel_bts events don't coexist with intel PMU's BTS events because of 2137 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2138 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2139 * 2140 * Avoid PEBS_ENABLE MSR access in PMIs. 2141 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2142 * It doesn't matter if the PEBS is enabled or not. 2143 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2144 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2145 * However, there are some cases which may change PEBS status, e.g. PMI 2146 * throttle. The PEBS_ENABLE should be updated where the status changes. 2147 */ 2148 static __always_inline void __intel_pmu_disable_all(bool bts) 2149 { 2150 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2151 2152 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2153 2154 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2155 intel_pmu_disable_bts(); 2156 } 2157 2158 static __always_inline void intel_pmu_disable_all(void) 2159 { 2160 __intel_pmu_disable_all(true); 2161 intel_pmu_pebs_disable_all(); 2162 intel_pmu_lbr_disable_all(); 2163 } 2164 2165 static void __intel_pmu_enable_all(int added, bool pmi) 2166 { 2167 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2168 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2169 2170 intel_pmu_lbr_enable_all(pmi); 2171 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2172 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2173 2174 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2175 struct perf_event *event = 2176 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2177 2178 if (WARN_ON_ONCE(!event)) 2179 return; 2180 2181 intel_pmu_enable_bts(event->hw.config); 2182 } 2183 } 2184 2185 static void intel_pmu_enable_all(int added) 2186 { 2187 intel_pmu_pebs_enable_all(); 2188 __intel_pmu_enable_all(added, false); 2189 } 2190 2191 static noinline int 2192 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2193 unsigned int cnt, unsigned long flags) 2194 { 2195 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2196 2197 intel_pmu_lbr_read(); 2198 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2199 2200 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2201 intel_pmu_enable_all(0); 2202 local_irq_restore(flags); 2203 return cnt; 2204 } 2205 2206 static int 2207 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2208 { 2209 unsigned long flags; 2210 2211 /* must not have branches... */ 2212 local_irq_save(flags); 2213 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2214 __intel_pmu_pebs_disable_all(); 2215 __intel_pmu_lbr_disable(); 2216 /* ... until here */ 2217 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2218 } 2219 2220 static int 2221 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2222 { 2223 unsigned long flags; 2224 2225 /* must not have branches... */ 2226 local_irq_save(flags); 2227 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2228 __intel_pmu_pebs_disable_all(); 2229 __intel_pmu_arch_lbr_disable(); 2230 /* ... until here */ 2231 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2232 } 2233 2234 /* 2235 * Workaround for: 2236 * Intel Errata AAK100 (model 26) 2237 * Intel Errata AAP53 (model 30) 2238 * Intel Errata BD53 (model 44) 2239 * 2240 * The official story: 2241 * These chips need to be 'reset' when adding counters by programming the 2242 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2243 * in sequence on the same PMC or on different PMCs. 2244 * 2245 * In practice it appears some of these events do in fact count, and 2246 * we need to program all 4 events. 2247 */ 2248 static void intel_pmu_nhm_workaround(void) 2249 { 2250 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2251 static const unsigned long nhm_magic[4] = { 2252 0x4300B5, 2253 0x4300D2, 2254 0x4300B1, 2255 0x4300B1 2256 }; 2257 struct perf_event *event; 2258 int i; 2259 2260 /* 2261 * The Errata requires below steps: 2262 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2263 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2264 * the corresponding PMCx; 2265 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2266 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2267 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2268 */ 2269 2270 /* 2271 * The real steps we choose are a little different from above. 2272 * A) To reduce MSR operations, we don't run step 1) as they 2273 * are already cleared before this function is called; 2274 * B) Call x86_perf_event_update to save PMCx before configuring 2275 * PERFEVTSELx with magic number; 2276 * C) With step 5), we do clear only when the PERFEVTSELx is 2277 * not used currently. 2278 * D) Call x86_perf_event_set_period to restore PMCx; 2279 */ 2280 2281 /* We always operate 4 pairs of PERF Counters */ 2282 for (i = 0; i < 4; i++) { 2283 event = cpuc->events[i]; 2284 if (event) 2285 x86_perf_event_update(event); 2286 } 2287 2288 for (i = 0; i < 4; i++) { 2289 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2290 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2291 } 2292 2293 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2294 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2295 2296 for (i = 0; i < 4; i++) { 2297 event = cpuc->events[i]; 2298 2299 if (event) { 2300 x86_perf_event_set_period(event); 2301 __x86_pmu_enable_event(&event->hw, 2302 ARCH_PERFMON_EVENTSEL_ENABLE); 2303 } else 2304 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2305 } 2306 } 2307 2308 static void intel_pmu_nhm_enable_all(int added) 2309 { 2310 if (added) 2311 intel_pmu_nhm_workaround(); 2312 intel_pmu_enable_all(added); 2313 } 2314 2315 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2316 { 2317 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2318 2319 if (cpuc->tfa_shadow != val) { 2320 cpuc->tfa_shadow = val; 2321 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2322 } 2323 } 2324 2325 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2326 { 2327 /* 2328 * We're going to use PMC3, make sure TFA is set before we touch it. 2329 */ 2330 if (cntr == 3) 2331 intel_set_tfa(cpuc, true); 2332 } 2333 2334 static void intel_tfa_pmu_enable_all(int added) 2335 { 2336 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2337 2338 /* 2339 * If we find PMC3 is no longer used when we enable the PMU, we can 2340 * clear TFA. 2341 */ 2342 if (!test_bit(3, cpuc->active_mask)) 2343 intel_set_tfa(cpuc, false); 2344 2345 intel_pmu_enable_all(added); 2346 } 2347 2348 static inline u64 intel_pmu_get_status(void) 2349 { 2350 u64 status; 2351 2352 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2353 2354 return status; 2355 } 2356 2357 static inline void intel_pmu_ack_status(u64 ack) 2358 { 2359 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2360 } 2361 2362 static inline bool event_is_checkpointed(struct perf_event *event) 2363 { 2364 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2365 } 2366 2367 static inline void intel_set_masks(struct perf_event *event, int idx) 2368 { 2369 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2370 2371 if (event->attr.exclude_host) 2372 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2373 if (event->attr.exclude_guest) 2374 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2375 if (event_is_checkpointed(event)) 2376 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2377 } 2378 2379 static inline void intel_clear_masks(struct perf_event *event, int idx) 2380 { 2381 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2382 2383 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2384 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2385 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2386 } 2387 2388 static void intel_pmu_disable_fixed(struct perf_event *event) 2389 { 2390 struct hw_perf_event *hwc = &event->hw; 2391 u64 ctrl_val, mask; 2392 int idx = hwc->idx; 2393 2394 if (is_topdown_idx(idx)) { 2395 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2396 2397 /* 2398 * When there are other active TopDown events, 2399 * don't disable the fixed counter 3. 2400 */ 2401 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2402 return; 2403 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2404 } 2405 2406 intel_clear_masks(event, idx); 2407 2408 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2409 rdmsrl(hwc->config_base, ctrl_val); 2410 ctrl_val &= ~mask; 2411 wrmsrl(hwc->config_base, ctrl_val); 2412 } 2413 2414 static void intel_pmu_disable_event(struct perf_event *event) 2415 { 2416 struct hw_perf_event *hwc = &event->hw; 2417 int idx = hwc->idx; 2418 2419 switch (idx) { 2420 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2421 intel_clear_masks(event, idx); 2422 x86_pmu_disable_event(event); 2423 break; 2424 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2425 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2426 intel_pmu_disable_fixed(event); 2427 break; 2428 case INTEL_PMC_IDX_FIXED_BTS: 2429 intel_pmu_disable_bts(); 2430 intel_pmu_drain_bts_buffer(); 2431 return; 2432 case INTEL_PMC_IDX_FIXED_VLBR: 2433 intel_clear_masks(event, idx); 2434 break; 2435 default: 2436 intel_clear_masks(event, idx); 2437 pr_warn("Failed to disable the event with invalid index %d\n", 2438 idx); 2439 return; 2440 } 2441 2442 /* 2443 * Needs to be called after x86_pmu_disable_event, 2444 * so we don't trigger the event without PEBS bit set. 2445 */ 2446 if (unlikely(event->attr.precise_ip)) 2447 intel_pmu_pebs_disable(event); 2448 } 2449 2450 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2451 { 2452 if (is_pebs_pt(event)) 2453 perf_report_aux_output_id(event, idx); 2454 } 2455 2456 static void intel_pmu_del_event(struct perf_event *event) 2457 { 2458 if (needs_branch_stack(event)) 2459 intel_pmu_lbr_del(event); 2460 if (event->attr.precise_ip) 2461 intel_pmu_pebs_del(event); 2462 } 2463 2464 static int icl_set_topdown_event_period(struct perf_event *event) 2465 { 2466 struct hw_perf_event *hwc = &event->hw; 2467 s64 left = local64_read(&hwc->period_left); 2468 2469 /* 2470 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2471 * Software should start both registers, PERF_METRICS and fixed 2472 * counter 3, from zero. 2473 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2474 * After that, both MSRs will be cleared for each read. 2475 * Don't need to clear them again. 2476 */ 2477 if (left == x86_pmu.max_period) { 2478 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2479 wrmsrl(MSR_PERF_METRICS, 0); 2480 hwc->saved_slots = 0; 2481 hwc->saved_metric = 0; 2482 } 2483 2484 if ((hwc->saved_slots) && is_slots_event(event)) { 2485 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2486 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2487 } 2488 2489 perf_event_update_userpage(event); 2490 2491 return 0; 2492 } 2493 2494 static int adl_set_topdown_event_period(struct perf_event *event) 2495 { 2496 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2497 2498 if (pmu->cpu_type != hybrid_big) 2499 return 0; 2500 2501 return icl_set_topdown_event_period(event); 2502 } 2503 2504 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2505 { 2506 u32 val; 2507 2508 /* 2509 * The metric is reported as an 8bit integer fraction 2510 * summing up to 0xff. 2511 * slots-in-metric = (Metric / 0xff) * slots 2512 */ 2513 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2514 return mul_u64_u32_div(slots, val, 0xff); 2515 } 2516 2517 static u64 icl_get_topdown_value(struct perf_event *event, 2518 u64 slots, u64 metrics) 2519 { 2520 int idx = event->hw.idx; 2521 u64 delta; 2522 2523 if (is_metric_idx(idx)) 2524 delta = icl_get_metrics_event_value(metrics, slots, idx); 2525 else 2526 delta = slots; 2527 2528 return delta; 2529 } 2530 2531 static void __icl_update_topdown_event(struct perf_event *event, 2532 u64 slots, u64 metrics, 2533 u64 last_slots, u64 last_metrics) 2534 { 2535 u64 delta, last = 0; 2536 2537 delta = icl_get_topdown_value(event, slots, metrics); 2538 if (last_slots) 2539 last = icl_get_topdown_value(event, last_slots, last_metrics); 2540 2541 /* 2542 * The 8bit integer fraction of metric may be not accurate, 2543 * especially when the changes is very small. 2544 * For example, if only a few bad_spec happens, the fraction 2545 * may be reduced from 1 to 0. If so, the bad_spec event value 2546 * will be 0 which is definitely less than the last value. 2547 * Avoid update event->count for this case. 2548 */ 2549 if (delta > last) { 2550 delta -= last; 2551 local64_add(delta, &event->count); 2552 } 2553 } 2554 2555 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2556 u64 metrics, int metric_end) 2557 { 2558 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2559 struct perf_event *other; 2560 int idx; 2561 2562 event->hw.saved_slots = slots; 2563 event->hw.saved_metric = metrics; 2564 2565 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2566 if (!is_topdown_idx(idx)) 2567 continue; 2568 other = cpuc->events[idx]; 2569 other->hw.saved_slots = slots; 2570 other->hw.saved_metric = metrics; 2571 } 2572 } 2573 2574 /* 2575 * Update all active Topdown events. 2576 * 2577 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2578 * modify by a NMI. PMU has to be disabled before calling this function. 2579 */ 2580 2581 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2582 { 2583 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2584 struct perf_event *other; 2585 u64 slots, metrics; 2586 bool reset = true; 2587 int idx; 2588 2589 /* read Fixed counter 3 */ 2590 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2591 if (!slots) 2592 return 0; 2593 2594 /* read PERF_METRICS */ 2595 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2596 2597 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2598 if (!is_topdown_idx(idx)) 2599 continue; 2600 other = cpuc->events[idx]; 2601 __icl_update_topdown_event(other, slots, metrics, 2602 event ? event->hw.saved_slots : 0, 2603 event ? event->hw.saved_metric : 0); 2604 } 2605 2606 /* 2607 * Check and update this event, which may have been cleared 2608 * in active_mask e.g. x86_pmu_stop() 2609 */ 2610 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2611 __icl_update_topdown_event(event, slots, metrics, 2612 event->hw.saved_slots, 2613 event->hw.saved_metric); 2614 2615 /* 2616 * In x86_pmu_stop(), the event is cleared in active_mask first, 2617 * then drain the delta, which indicates context switch for 2618 * counting. 2619 * Save metric and slots for context switch. 2620 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2621 * Because the values will be restored in next schedule in. 2622 */ 2623 update_saved_topdown_regs(event, slots, metrics, metric_end); 2624 reset = false; 2625 } 2626 2627 if (reset) { 2628 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2629 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2630 wrmsrl(MSR_PERF_METRICS, 0); 2631 if (event) 2632 update_saved_topdown_regs(event, 0, 0, metric_end); 2633 } 2634 2635 return slots; 2636 } 2637 2638 static u64 icl_update_topdown_event(struct perf_event *event) 2639 { 2640 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2641 x86_pmu.num_topdown_events - 1); 2642 } 2643 2644 static u64 adl_update_topdown_event(struct perf_event *event) 2645 { 2646 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2647 2648 if (pmu->cpu_type != hybrid_big) 2649 return 0; 2650 2651 return icl_update_topdown_event(event); 2652 } 2653 2654 2655 static void intel_pmu_read_topdown_event(struct perf_event *event) 2656 { 2657 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2658 2659 /* Only need to call update_topdown_event() once for group read. */ 2660 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2661 !is_slots_event(event)) 2662 return; 2663 2664 perf_pmu_disable(event->pmu); 2665 x86_pmu.update_topdown_event(event); 2666 perf_pmu_enable(event->pmu); 2667 } 2668 2669 static void intel_pmu_read_event(struct perf_event *event) 2670 { 2671 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2672 intel_pmu_auto_reload_read(event); 2673 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 2674 intel_pmu_read_topdown_event(event); 2675 else 2676 x86_perf_event_update(event); 2677 } 2678 2679 static void intel_pmu_enable_fixed(struct perf_event *event) 2680 { 2681 struct hw_perf_event *hwc = &event->hw; 2682 u64 ctrl_val, mask, bits = 0; 2683 int idx = hwc->idx; 2684 2685 if (is_topdown_idx(idx)) { 2686 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2687 /* 2688 * When there are other active TopDown events, 2689 * don't enable the fixed counter 3 again. 2690 */ 2691 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2692 return; 2693 2694 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2695 } 2696 2697 intel_set_masks(event, idx); 2698 2699 /* 2700 * Enable IRQ generation (0x8), if not PEBS, 2701 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2702 * if requested: 2703 */ 2704 if (!event->attr.precise_ip) 2705 bits |= 0x8; 2706 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2707 bits |= 0x2; 2708 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2709 bits |= 0x1; 2710 2711 /* 2712 * ANY bit is supported in v3 and up 2713 */ 2714 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2715 bits |= 0x4; 2716 2717 idx -= INTEL_PMC_IDX_FIXED; 2718 bits <<= (idx * 4); 2719 mask = 0xfULL << (idx * 4); 2720 2721 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2722 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2723 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2724 } 2725 2726 rdmsrl(hwc->config_base, ctrl_val); 2727 ctrl_val &= ~mask; 2728 ctrl_val |= bits; 2729 wrmsrl(hwc->config_base, ctrl_val); 2730 } 2731 2732 static void intel_pmu_enable_event(struct perf_event *event) 2733 { 2734 struct hw_perf_event *hwc = &event->hw; 2735 int idx = hwc->idx; 2736 2737 if (unlikely(event->attr.precise_ip)) 2738 intel_pmu_pebs_enable(event); 2739 2740 switch (idx) { 2741 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2742 intel_set_masks(event, idx); 2743 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2744 break; 2745 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2746 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2747 intel_pmu_enable_fixed(event); 2748 break; 2749 case INTEL_PMC_IDX_FIXED_BTS: 2750 if (!__this_cpu_read(cpu_hw_events.enabled)) 2751 return; 2752 intel_pmu_enable_bts(hwc->config); 2753 break; 2754 case INTEL_PMC_IDX_FIXED_VLBR: 2755 intel_set_masks(event, idx); 2756 break; 2757 default: 2758 pr_warn("Failed to enable the event with invalid index %d\n", 2759 idx); 2760 } 2761 } 2762 2763 static void intel_pmu_add_event(struct perf_event *event) 2764 { 2765 if (event->attr.precise_ip) 2766 intel_pmu_pebs_add(event); 2767 if (needs_branch_stack(event)) 2768 intel_pmu_lbr_add(event); 2769 } 2770 2771 /* 2772 * Save and restart an expired event. Called by NMI contexts, 2773 * so it has to be careful about preempting normal event ops: 2774 */ 2775 int intel_pmu_save_and_restart(struct perf_event *event) 2776 { 2777 x86_perf_event_update(event); 2778 /* 2779 * For a checkpointed counter always reset back to 0. This 2780 * avoids a situation where the counter overflows, aborts the 2781 * transaction and is then set back to shortly before the 2782 * overflow, and overflows and aborts again. 2783 */ 2784 if (unlikely(event_is_checkpointed(event))) { 2785 /* No race with NMIs because the counter should not be armed */ 2786 wrmsrl(event->hw.event_base, 0); 2787 local64_set(&event->hw.prev_count, 0); 2788 } 2789 return x86_perf_event_set_period(event); 2790 } 2791 2792 static void intel_pmu_reset(void) 2793 { 2794 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2795 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2796 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2797 int num_counters = hybrid(cpuc->pmu, num_counters); 2798 unsigned long flags; 2799 int idx; 2800 2801 if (!num_counters) 2802 return; 2803 2804 local_irq_save(flags); 2805 2806 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2807 2808 for (idx = 0; idx < num_counters; idx++) { 2809 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2810 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2811 } 2812 for (idx = 0; idx < num_counters_fixed; idx++) { 2813 if (fixed_counter_disabled(idx, cpuc->pmu)) 2814 continue; 2815 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2816 } 2817 2818 if (ds) 2819 ds->bts_index = ds->bts_buffer_base; 2820 2821 /* Ack all overflows and disable fixed counters */ 2822 if (x86_pmu.version >= 2) { 2823 intel_pmu_ack_status(intel_pmu_get_status()); 2824 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2825 } 2826 2827 /* Reset LBRs and LBR freezing */ 2828 if (x86_pmu.lbr_nr) { 2829 update_debugctlmsr(get_debugctlmsr() & 2830 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2831 } 2832 2833 local_irq_restore(flags); 2834 } 2835 2836 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2837 { 2838 struct perf_sample_data data; 2839 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2840 int bit; 2841 int handled = 0; 2842 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2843 2844 inc_irq_stat(apic_perf_irqs); 2845 2846 /* 2847 * Ignore a range of extra bits in status that do not indicate 2848 * overflow by themselves. 2849 */ 2850 status &= ~(GLOBAL_STATUS_COND_CHG | 2851 GLOBAL_STATUS_ASIF | 2852 GLOBAL_STATUS_LBRS_FROZEN); 2853 if (!status) 2854 return 0; 2855 /* 2856 * In case multiple PEBS events are sampled at the same time, 2857 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2858 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2859 * having their bits set in the status register. This is a sign 2860 * that there was at least one PEBS record pending at the time 2861 * of the PMU interrupt. PEBS counters must only be processed 2862 * via the drain_pebs() calls and not via the regular sample 2863 * processing loop coming after that the function, otherwise 2864 * phony regular samples may be generated in the sampling buffer 2865 * not marked with the EXACT tag. Another possibility is to have 2866 * one PEBS event and at least one non-PEBS event which overflows 2867 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2868 * not be set, yet the overflow status bit for the PEBS counter will 2869 * be on Skylake. 2870 * 2871 * To avoid this problem, we systematically ignore the PEBS-enabled 2872 * counters from the GLOBAL_STATUS mask and we always process PEBS 2873 * events via drain_pebs(). 2874 */ 2875 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2876 status &= ~cpuc->pebs_enabled; 2877 else 2878 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2879 2880 /* 2881 * PEBS overflow sets bit 62 in the global status register 2882 */ 2883 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2884 u64 pebs_enabled = cpuc->pebs_enabled; 2885 2886 handled++; 2887 x86_pmu.drain_pebs(regs, &data); 2888 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2889 2890 /* 2891 * PMI throttle may be triggered, which stops the PEBS event. 2892 * Although cpuc->pebs_enabled is updated accordingly, the 2893 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2894 * cpuc->enabled has been forced to 0 in PMI. 2895 * Update the MSR if pebs_enabled is changed. 2896 */ 2897 if (pebs_enabled != cpuc->pebs_enabled) 2898 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2899 } 2900 2901 /* 2902 * Intel PT 2903 */ 2904 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2905 handled++; 2906 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 2907 perf_guest_cbs->handle_intel_pt_intr)) 2908 perf_guest_cbs->handle_intel_pt_intr(); 2909 else 2910 intel_pt_interrupt(); 2911 } 2912 2913 /* 2914 * Intel Perf metrics 2915 */ 2916 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 2917 handled++; 2918 if (x86_pmu.update_topdown_event) 2919 x86_pmu.update_topdown_event(NULL); 2920 } 2921 2922 /* 2923 * Checkpointed counters can lead to 'spurious' PMIs because the 2924 * rollback caused by the PMI will have cleared the overflow status 2925 * bit. Therefore always force probe these counters. 2926 */ 2927 status |= cpuc->intel_cp_status; 2928 2929 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2930 struct perf_event *event = cpuc->events[bit]; 2931 2932 handled++; 2933 2934 if (!test_bit(bit, cpuc->active_mask)) 2935 continue; 2936 2937 if (!intel_pmu_save_and_restart(event)) 2938 continue; 2939 2940 perf_sample_data_init(&data, 0, event->hw.last_period); 2941 2942 if (has_branch_stack(event)) 2943 data.br_stack = &cpuc->lbr_stack; 2944 2945 if (perf_event_overflow(event, &data, regs)) 2946 x86_pmu_stop(event, 0); 2947 } 2948 2949 return handled; 2950 } 2951 2952 /* 2953 * This handler is triggered by the local APIC, so the APIC IRQ handling 2954 * rules apply: 2955 */ 2956 static int intel_pmu_handle_irq(struct pt_regs *regs) 2957 { 2958 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2959 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 2960 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 2961 int loops; 2962 u64 status; 2963 int handled; 2964 int pmu_enabled; 2965 2966 /* 2967 * Save the PMU state. 2968 * It needs to be restored when leaving the handler. 2969 */ 2970 pmu_enabled = cpuc->enabled; 2971 /* 2972 * In general, the early ACK is only applied for old platforms. 2973 * For the big core starts from Haswell, the late ACK should be 2974 * applied. 2975 * For the small core after Tremont, we have to do the ACK right 2976 * before re-enabling counters, which is in the middle of the 2977 * NMI handler. 2978 */ 2979 if (!late_ack && !mid_ack) 2980 apic_write(APIC_LVTPC, APIC_DM_NMI); 2981 intel_bts_disable_local(); 2982 cpuc->enabled = 0; 2983 __intel_pmu_disable_all(true); 2984 handled = intel_pmu_drain_bts_buffer(); 2985 handled += intel_bts_interrupt(); 2986 status = intel_pmu_get_status(); 2987 if (!status) 2988 goto done; 2989 2990 loops = 0; 2991 again: 2992 intel_pmu_lbr_read(); 2993 intel_pmu_ack_status(status); 2994 if (++loops > 100) { 2995 static bool warned; 2996 2997 if (!warned) { 2998 WARN(1, "perfevents: irq loop stuck!\n"); 2999 perf_event_print_debug(); 3000 warned = true; 3001 } 3002 intel_pmu_reset(); 3003 goto done; 3004 } 3005 3006 handled += handle_pmi_common(regs, status); 3007 3008 /* 3009 * Repeat if there is more work to be done: 3010 */ 3011 status = intel_pmu_get_status(); 3012 if (status) 3013 goto again; 3014 3015 done: 3016 if (mid_ack) 3017 apic_write(APIC_LVTPC, APIC_DM_NMI); 3018 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3019 cpuc->enabled = pmu_enabled; 3020 if (pmu_enabled) 3021 __intel_pmu_enable_all(0, true); 3022 intel_bts_enable_local(); 3023 3024 /* 3025 * Only unmask the NMI after the overflow counters 3026 * have been reset. This avoids spurious NMIs on 3027 * Haswell CPUs. 3028 */ 3029 if (late_ack) 3030 apic_write(APIC_LVTPC, APIC_DM_NMI); 3031 return handled; 3032 } 3033 3034 static struct event_constraint * 3035 intel_bts_constraints(struct perf_event *event) 3036 { 3037 if (unlikely(intel_pmu_has_bts(event))) 3038 return &bts_constraint; 3039 3040 return NULL; 3041 } 3042 3043 /* 3044 * Note: matches a fake event, like Fixed2. 3045 */ 3046 static struct event_constraint * 3047 intel_vlbr_constraints(struct perf_event *event) 3048 { 3049 struct event_constraint *c = &vlbr_constraint; 3050 3051 if (unlikely(constraint_match(c, event->hw.config))) 3052 return c; 3053 3054 return NULL; 3055 } 3056 3057 static int intel_alt_er(struct cpu_hw_events *cpuc, 3058 int idx, u64 config) 3059 { 3060 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3061 int alt_idx = idx; 3062 3063 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3064 return idx; 3065 3066 if (idx == EXTRA_REG_RSP_0) 3067 alt_idx = EXTRA_REG_RSP_1; 3068 3069 if (idx == EXTRA_REG_RSP_1) 3070 alt_idx = EXTRA_REG_RSP_0; 3071 3072 if (config & ~extra_regs[alt_idx].valid_mask) 3073 return idx; 3074 3075 return alt_idx; 3076 } 3077 3078 static void intel_fixup_er(struct perf_event *event, int idx) 3079 { 3080 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3081 event->hw.extra_reg.idx = idx; 3082 3083 if (idx == EXTRA_REG_RSP_0) { 3084 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3085 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3086 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3087 } else if (idx == EXTRA_REG_RSP_1) { 3088 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3089 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3090 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3091 } 3092 } 3093 3094 /* 3095 * manage allocation of shared extra msr for certain events 3096 * 3097 * sharing can be: 3098 * per-cpu: to be shared between the various events on a single PMU 3099 * per-core: per-cpu + shared by HT threads 3100 */ 3101 static struct event_constraint * 3102 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3103 struct perf_event *event, 3104 struct hw_perf_event_extra *reg) 3105 { 3106 struct event_constraint *c = &emptyconstraint; 3107 struct er_account *era; 3108 unsigned long flags; 3109 int idx = reg->idx; 3110 3111 /* 3112 * reg->alloc can be set due to existing state, so for fake cpuc we 3113 * need to ignore this, otherwise we might fail to allocate proper fake 3114 * state for this extra reg constraint. Also see the comment below. 3115 */ 3116 if (reg->alloc && !cpuc->is_fake) 3117 return NULL; /* call x86_get_event_constraint() */ 3118 3119 again: 3120 era = &cpuc->shared_regs->regs[idx]; 3121 /* 3122 * we use spin_lock_irqsave() to avoid lockdep issues when 3123 * passing a fake cpuc 3124 */ 3125 raw_spin_lock_irqsave(&era->lock, flags); 3126 3127 if (!atomic_read(&era->ref) || era->config == reg->config) { 3128 3129 /* 3130 * If its a fake cpuc -- as per validate_{group,event}() we 3131 * shouldn't touch event state and we can avoid doing so 3132 * since both will only call get_event_constraints() once 3133 * on each event, this avoids the need for reg->alloc. 3134 * 3135 * Not doing the ER fixup will only result in era->reg being 3136 * wrong, but since we won't actually try and program hardware 3137 * this isn't a problem either. 3138 */ 3139 if (!cpuc->is_fake) { 3140 if (idx != reg->idx) 3141 intel_fixup_er(event, idx); 3142 3143 /* 3144 * x86_schedule_events() can call get_event_constraints() 3145 * multiple times on events in the case of incremental 3146 * scheduling(). reg->alloc ensures we only do the ER 3147 * allocation once. 3148 */ 3149 reg->alloc = 1; 3150 } 3151 3152 /* lock in msr value */ 3153 era->config = reg->config; 3154 era->reg = reg->reg; 3155 3156 /* one more user */ 3157 atomic_inc(&era->ref); 3158 3159 /* 3160 * need to call x86_get_event_constraint() 3161 * to check if associated event has constraints 3162 */ 3163 c = NULL; 3164 } else { 3165 idx = intel_alt_er(cpuc, idx, reg->config); 3166 if (idx != reg->idx) { 3167 raw_spin_unlock_irqrestore(&era->lock, flags); 3168 goto again; 3169 } 3170 } 3171 raw_spin_unlock_irqrestore(&era->lock, flags); 3172 3173 return c; 3174 } 3175 3176 static void 3177 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3178 struct hw_perf_event_extra *reg) 3179 { 3180 struct er_account *era; 3181 3182 /* 3183 * Only put constraint if extra reg was actually allocated. Also takes 3184 * care of event which do not use an extra shared reg. 3185 * 3186 * Also, if this is a fake cpuc we shouldn't touch any event state 3187 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3188 * either since it'll be thrown out. 3189 */ 3190 if (!reg->alloc || cpuc->is_fake) 3191 return; 3192 3193 era = &cpuc->shared_regs->regs[reg->idx]; 3194 3195 /* one fewer user */ 3196 atomic_dec(&era->ref); 3197 3198 /* allocate again next time */ 3199 reg->alloc = 0; 3200 } 3201 3202 static struct event_constraint * 3203 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3204 struct perf_event *event) 3205 { 3206 struct event_constraint *c = NULL, *d; 3207 struct hw_perf_event_extra *xreg, *breg; 3208 3209 xreg = &event->hw.extra_reg; 3210 if (xreg->idx != EXTRA_REG_NONE) { 3211 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3212 if (c == &emptyconstraint) 3213 return c; 3214 } 3215 breg = &event->hw.branch_reg; 3216 if (breg->idx != EXTRA_REG_NONE) { 3217 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3218 if (d == &emptyconstraint) { 3219 __intel_shared_reg_put_constraints(cpuc, xreg); 3220 c = d; 3221 } 3222 } 3223 return c; 3224 } 3225 3226 struct event_constraint * 3227 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3228 struct perf_event *event) 3229 { 3230 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3231 struct event_constraint *c; 3232 3233 if (event_constraints) { 3234 for_each_event_constraint(c, event_constraints) { 3235 if (constraint_match(c, event->hw.config)) { 3236 event->hw.flags |= c->flags; 3237 return c; 3238 } 3239 } 3240 } 3241 3242 return &hybrid_var(cpuc->pmu, unconstrained); 3243 } 3244 3245 static struct event_constraint * 3246 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3247 struct perf_event *event) 3248 { 3249 struct event_constraint *c; 3250 3251 c = intel_vlbr_constraints(event); 3252 if (c) 3253 return c; 3254 3255 c = intel_bts_constraints(event); 3256 if (c) 3257 return c; 3258 3259 c = intel_shared_regs_constraints(cpuc, event); 3260 if (c) 3261 return c; 3262 3263 c = intel_pebs_constraints(event); 3264 if (c) 3265 return c; 3266 3267 return x86_get_event_constraints(cpuc, idx, event); 3268 } 3269 3270 static void 3271 intel_start_scheduling(struct cpu_hw_events *cpuc) 3272 { 3273 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3274 struct intel_excl_states *xl; 3275 int tid = cpuc->excl_thread_id; 3276 3277 /* 3278 * nothing needed if in group validation mode 3279 */ 3280 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3281 return; 3282 3283 /* 3284 * no exclusion needed 3285 */ 3286 if (WARN_ON_ONCE(!excl_cntrs)) 3287 return; 3288 3289 xl = &excl_cntrs->states[tid]; 3290 3291 xl->sched_started = true; 3292 /* 3293 * lock shared state until we are done scheduling 3294 * in stop_event_scheduling() 3295 * makes scheduling appear as a transaction 3296 */ 3297 raw_spin_lock(&excl_cntrs->lock); 3298 } 3299 3300 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3301 { 3302 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3303 struct event_constraint *c = cpuc->event_constraint[idx]; 3304 struct intel_excl_states *xl; 3305 int tid = cpuc->excl_thread_id; 3306 3307 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3308 return; 3309 3310 if (WARN_ON_ONCE(!excl_cntrs)) 3311 return; 3312 3313 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3314 return; 3315 3316 xl = &excl_cntrs->states[tid]; 3317 3318 lockdep_assert_held(&excl_cntrs->lock); 3319 3320 if (c->flags & PERF_X86_EVENT_EXCL) 3321 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3322 else 3323 xl->state[cntr] = INTEL_EXCL_SHARED; 3324 } 3325 3326 static void 3327 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3328 { 3329 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3330 struct intel_excl_states *xl; 3331 int tid = cpuc->excl_thread_id; 3332 3333 /* 3334 * nothing needed if in group validation mode 3335 */ 3336 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3337 return; 3338 /* 3339 * no exclusion needed 3340 */ 3341 if (WARN_ON_ONCE(!excl_cntrs)) 3342 return; 3343 3344 xl = &excl_cntrs->states[tid]; 3345 3346 xl->sched_started = false; 3347 /* 3348 * release shared state lock (acquired in intel_start_scheduling()) 3349 */ 3350 raw_spin_unlock(&excl_cntrs->lock); 3351 } 3352 3353 static struct event_constraint * 3354 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3355 { 3356 WARN_ON_ONCE(!cpuc->constraint_list); 3357 3358 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3359 struct event_constraint *cx; 3360 3361 /* 3362 * grab pre-allocated constraint entry 3363 */ 3364 cx = &cpuc->constraint_list[idx]; 3365 3366 /* 3367 * initialize dynamic constraint 3368 * with static constraint 3369 */ 3370 *cx = *c; 3371 3372 /* 3373 * mark constraint as dynamic 3374 */ 3375 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3376 c = cx; 3377 } 3378 3379 return c; 3380 } 3381 3382 static struct event_constraint * 3383 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3384 int idx, struct event_constraint *c) 3385 { 3386 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3387 struct intel_excl_states *xlo; 3388 int tid = cpuc->excl_thread_id; 3389 int is_excl, i, w; 3390 3391 /* 3392 * validating a group does not require 3393 * enforcing cross-thread exclusion 3394 */ 3395 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3396 return c; 3397 3398 /* 3399 * no exclusion needed 3400 */ 3401 if (WARN_ON_ONCE(!excl_cntrs)) 3402 return c; 3403 3404 /* 3405 * because we modify the constraint, we need 3406 * to make a copy. Static constraints come 3407 * from static const tables. 3408 * 3409 * only needed when constraint has not yet 3410 * been cloned (marked dynamic) 3411 */ 3412 c = dyn_constraint(cpuc, c, idx); 3413 3414 /* 3415 * From here on, the constraint is dynamic. 3416 * Either it was just allocated above, or it 3417 * was allocated during a earlier invocation 3418 * of this function 3419 */ 3420 3421 /* 3422 * state of sibling HT 3423 */ 3424 xlo = &excl_cntrs->states[tid ^ 1]; 3425 3426 /* 3427 * event requires exclusive counter access 3428 * across HT threads 3429 */ 3430 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3431 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3432 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3433 if (!cpuc->n_excl++) 3434 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3435 } 3436 3437 /* 3438 * Modify static constraint with current dynamic 3439 * state of thread 3440 * 3441 * EXCLUSIVE: sibling counter measuring exclusive event 3442 * SHARED : sibling counter measuring non-exclusive event 3443 * UNUSED : sibling counter unused 3444 */ 3445 w = c->weight; 3446 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3447 /* 3448 * exclusive event in sibling counter 3449 * our corresponding counter cannot be used 3450 * regardless of our event 3451 */ 3452 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3453 __clear_bit(i, c->idxmsk); 3454 w--; 3455 continue; 3456 } 3457 /* 3458 * if measuring an exclusive event, sibling 3459 * measuring non-exclusive, then counter cannot 3460 * be used 3461 */ 3462 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3463 __clear_bit(i, c->idxmsk); 3464 w--; 3465 continue; 3466 } 3467 } 3468 3469 /* 3470 * if we return an empty mask, then switch 3471 * back to static empty constraint to avoid 3472 * the cost of freeing later on 3473 */ 3474 if (!w) 3475 c = &emptyconstraint; 3476 3477 c->weight = w; 3478 3479 return c; 3480 } 3481 3482 static struct event_constraint * 3483 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3484 struct perf_event *event) 3485 { 3486 struct event_constraint *c1, *c2; 3487 3488 c1 = cpuc->event_constraint[idx]; 3489 3490 /* 3491 * first time only 3492 * - static constraint: no change across incremental scheduling calls 3493 * - dynamic constraint: handled by intel_get_excl_constraints() 3494 */ 3495 c2 = __intel_get_event_constraints(cpuc, idx, event); 3496 if (c1) { 3497 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3498 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3499 c1->weight = c2->weight; 3500 c2 = c1; 3501 } 3502 3503 if (cpuc->excl_cntrs) 3504 return intel_get_excl_constraints(cpuc, event, idx, c2); 3505 3506 return c2; 3507 } 3508 3509 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3510 struct perf_event *event) 3511 { 3512 struct hw_perf_event *hwc = &event->hw; 3513 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3514 int tid = cpuc->excl_thread_id; 3515 struct intel_excl_states *xl; 3516 3517 /* 3518 * nothing needed if in group validation mode 3519 */ 3520 if (cpuc->is_fake) 3521 return; 3522 3523 if (WARN_ON_ONCE(!excl_cntrs)) 3524 return; 3525 3526 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3527 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3528 if (!--cpuc->n_excl) 3529 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3530 } 3531 3532 /* 3533 * If event was actually assigned, then mark the counter state as 3534 * unused now. 3535 */ 3536 if (hwc->idx >= 0) { 3537 xl = &excl_cntrs->states[tid]; 3538 3539 /* 3540 * put_constraint may be called from x86_schedule_events() 3541 * which already has the lock held so here make locking 3542 * conditional. 3543 */ 3544 if (!xl->sched_started) 3545 raw_spin_lock(&excl_cntrs->lock); 3546 3547 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3548 3549 if (!xl->sched_started) 3550 raw_spin_unlock(&excl_cntrs->lock); 3551 } 3552 } 3553 3554 static void 3555 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3556 struct perf_event *event) 3557 { 3558 struct hw_perf_event_extra *reg; 3559 3560 reg = &event->hw.extra_reg; 3561 if (reg->idx != EXTRA_REG_NONE) 3562 __intel_shared_reg_put_constraints(cpuc, reg); 3563 3564 reg = &event->hw.branch_reg; 3565 if (reg->idx != EXTRA_REG_NONE) 3566 __intel_shared_reg_put_constraints(cpuc, reg); 3567 } 3568 3569 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3570 struct perf_event *event) 3571 { 3572 intel_put_shared_regs_event_constraints(cpuc, event); 3573 3574 /* 3575 * is PMU has exclusive counter restrictions, then 3576 * all events are subject to and must call the 3577 * put_excl_constraints() routine 3578 */ 3579 if (cpuc->excl_cntrs) 3580 intel_put_excl_constraints(cpuc, event); 3581 } 3582 3583 static void intel_pebs_aliases_core2(struct perf_event *event) 3584 { 3585 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3586 /* 3587 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3588 * (0x003c) so that we can use it with PEBS. 3589 * 3590 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3591 * PEBS capable. However we can use INST_RETIRED.ANY_P 3592 * (0x00c0), which is a PEBS capable event, to get the same 3593 * count. 3594 * 3595 * INST_RETIRED.ANY_P counts the number of cycles that retires 3596 * CNTMASK instructions. By setting CNTMASK to a value (16) 3597 * larger than the maximum number of instructions that can be 3598 * retired per cycle (4) and then inverting the condition, we 3599 * count all cycles that retire 16 or less instructions, which 3600 * is every cycle. 3601 * 3602 * Thereby we gain a PEBS capable cycle counter. 3603 */ 3604 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3605 3606 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3607 event->hw.config = alt_config; 3608 } 3609 } 3610 3611 static void intel_pebs_aliases_snb(struct perf_event *event) 3612 { 3613 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3614 /* 3615 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3616 * (0x003c) so that we can use it with PEBS. 3617 * 3618 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3619 * PEBS capable. However we can use UOPS_RETIRED.ALL 3620 * (0x01c2), which is a PEBS capable event, to get the same 3621 * count. 3622 * 3623 * UOPS_RETIRED.ALL counts the number of cycles that retires 3624 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3625 * larger than the maximum number of micro-ops that can be 3626 * retired per cycle (4) and then inverting the condition, we 3627 * count all cycles that retire 16 or less micro-ops, which 3628 * is every cycle. 3629 * 3630 * Thereby we gain a PEBS capable cycle counter. 3631 */ 3632 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3633 3634 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3635 event->hw.config = alt_config; 3636 } 3637 } 3638 3639 static void intel_pebs_aliases_precdist(struct perf_event *event) 3640 { 3641 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3642 /* 3643 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3644 * (0x003c) so that we can use it with PEBS. 3645 * 3646 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3647 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3648 * (0x01c0), which is a PEBS capable event, to get the same 3649 * count. 3650 * 3651 * The PREC_DIST event has special support to minimize sample 3652 * shadowing effects. One drawback is that it can be 3653 * only programmed on counter 1, but that seems like an 3654 * acceptable trade off. 3655 */ 3656 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3657 3658 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3659 event->hw.config = alt_config; 3660 } 3661 } 3662 3663 static void intel_pebs_aliases_ivb(struct perf_event *event) 3664 { 3665 if (event->attr.precise_ip < 3) 3666 return intel_pebs_aliases_snb(event); 3667 return intel_pebs_aliases_precdist(event); 3668 } 3669 3670 static void intel_pebs_aliases_skl(struct perf_event *event) 3671 { 3672 if (event->attr.precise_ip < 3) 3673 return intel_pebs_aliases_core2(event); 3674 return intel_pebs_aliases_precdist(event); 3675 } 3676 3677 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3678 { 3679 unsigned long flags = x86_pmu.large_pebs_flags; 3680 3681 if (event->attr.use_clockid) 3682 flags &= ~PERF_SAMPLE_TIME; 3683 if (!event->attr.exclude_kernel) 3684 flags &= ~PERF_SAMPLE_REGS_USER; 3685 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3686 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3687 return flags; 3688 } 3689 3690 static int intel_pmu_bts_config(struct perf_event *event) 3691 { 3692 struct perf_event_attr *attr = &event->attr; 3693 3694 if (unlikely(intel_pmu_has_bts(event))) { 3695 /* BTS is not supported by this architecture. */ 3696 if (!x86_pmu.bts_active) 3697 return -EOPNOTSUPP; 3698 3699 /* BTS is currently only allowed for user-mode. */ 3700 if (!attr->exclude_kernel) 3701 return -EOPNOTSUPP; 3702 3703 /* BTS is not allowed for precise events. */ 3704 if (attr->precise_ip) 3705 return -EOPNOTSUPP; 3706 3707 /* disallow bts if conflicting events are present */ 3708 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3709 return -EBUSY; 3710 3711 event->destroy = hw_perf_lbr_event_destroy; 3712 } 3713 3714 return 0; 3715 } 3716 3717 static int core_pmu_hw_config(struct perf_event *event) 3718 { 3719 int ret = x86_pmu_hw_config(event); 3720 3721 if (ret) 3722 return ret; 3723 3724 return intel_pmu_bts_config(event); 3725 } 3726 3727 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3728 ((x86_pmu.num_topdown_events - 1) << 8)) 3729 3730 static bool is_available_metric_event(struct perf_event *event) 3731 { 3732 return is_metric_event(event) && 3733 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3734 } 3735 3736 static inline bool is_mem_loads_event(struct perf_event *event) 3737 { 3738 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3739 } 3740 3741 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3742 { 3743 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3744 } 3745 3746 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3747 { 3748 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3749 return false; 3750 3751 if (is_hybrid()) 3752 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3753 3754 return true; 3755 } 3756 3757 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3758 { 3759 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3760 3761 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3762 } 3763 3764 static int intel_pmu_hw_config(struct perf_event *event) 3765 { 3766 int ret = x86_pmu_hw_config(event); 3767 3768 if (ret) 3769 return ret; 3770 3771 ret = intel_pmu_bts_config(event); 3772 if (ret) 3773 return ret; 3774 3775 if (event->attr.precise_ip) { 3776 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3777 return -EINVAL; 3778 3779 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3780 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3781 if (!(event->attr.sample_type & 3782 ~intel_pmu_large_pebs_flags(event))) { 3783 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3784 event->attach_state |= PERF_ATTACH_SCHED_CB; 3785 } 3786 } 3787 if (x86_pmu.pebs_aliases) 3788 x86_pmu.pebs_aliases(event); 3789 3790 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3791 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3792 } 3793 3794 if (needs_branch_stack(event)) { 3795 ret = intel_pmu_setup_lbr_filter(event); 3796 if (ret) 3797 return ret; 3798 event->attach_state |= PERF_ATTACH_SCHED_CB; 3799 3800 /* 3801 * BTS is set up earlier in this path, so don't account twice 3802 */ 3803 if (!unlikely(intel_pmu_has_bts(event))) { 3804 /* disallow lbr if conflicting events are present */ 3805 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3806 return -EBUSY; 3807 3808 event->destroy = hw_perf_lbr_event_destroy; 3809 } 3810 } 3811 3812 if (event->attr.aux_output) { 3813 if (!event->attr.precise_ip) 3814 return -EINVAL; 3815 3816 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3817 } 3818 3819 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3820 (event->attr.type == PERF_TYPE_HW_CACHE)) 3821 return 0; 3822 3823 /* 3824 * Config Topdown slots and metric events 3825 * 3826 * The slots event on Fixed Counter 3 can support sampling, 3827 * which will be handled normally in x86_perf_event_update(). 3828 * 3829 * Metric events don't support sampling and require being paired 3830 * with a slots event as group leader. When the slots event 3831 * is used in a metrics group, it too cannot support sampling. 3832 */ 3833 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3834 if (event->attr.config1 || event->attr.config2) 3835 return -EINVAL; 3836 3837 /* 3838 * The TopDown metrics events and slots event don't 3839 * support any filters. 3840 */ 3841 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3842 return -EINVAL; 3843 3844 if (is_available_metric_event(event)) { 3845 struct perf_event *leader = event->group_leader; 3846 3847 /* The metric events don't support sampling. */ 3848 if (is_sampling_event(event)) 3849 return -EINVAL; 3850 3851 /* The metric events require a slots group leader. */ 3852 if (!is_slots_event(leader)) 3853 return -EINVAL; 3854 3855 /* 3856 * The leader/SLOTS must not be a sampling event for 3857 * metric use; hardware requires it starts at 0 when used 3858 * in conjunction with MSR_PERF_METRICS. 3859 */ 3860 if (is_sampling_event(leader)) 3861 return -EINVAL; 3862 3863 event->event_caps |= PERF_EV_CAP_SIBLING; 3864 /* 3865 * Only once we have a METRICs sibling do we 3866 * need TopDown magic. 3867 */ 3868 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3869 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3870 } 3871 } 3872 3873 /* 3874 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3875 * doesn't function quite right. As a work-around it needs to always be 3876 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3877 * The actual count of this second event is irrelevant it just needs 3878 * to be active to make the first event function correctly. 3879 * 3880 * In a group, the auxiliary event must be in front of the load latency 3881 * event. The rule is to simplify the implementation of the check. 3882 * That's because perf cannot have a complete group at the moment. 3883 */ 3884 if (require_mem_loads_aux_event(event) && 3885 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3886 is_mem_loads_event(event)) { 3887 struct perf_event *leader = event->group_leader; 3888 struct perf_event *sibling = NULL; 3889 3890 if (!is_mem_loads_aux_event(leader)) { 3891 for_each_sibling_event(sibling, leader) { 3892 if (is_mem_loads_aux_event(sibling)) 3893 break; 3894 } 3895 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3896 return -ENODATA; 3897 } 3898 } 3899 3900 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3901 return 0; 3902 3903 if (x86_pmu.version < 3) 3904 return -EINVAL; 3905 3906 ret = perf_allow_cpu(&event->attr); 3907 if (ret) 3908 return ret; 3909 3910 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3911 3912 return 0; 3913 } 3914 3915 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3916 { 3917 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3918 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3919 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3920 3921 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3922 arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3923 arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3924 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 3925 arr[0].guest &= ~cpuc->pebs_enabled; 3926 else 3927 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 3928 *nr = 1; 3929 3930 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3931 /* 3932 * If PMU counter has PEBS enabled it is not enough to 3933 * disable counter on a guest entry since PEBS memory 3934 * write can overshoot guest entry and corrupt guest 3935 * memory. Disabling PEBS solves the problem. 3936 * 3937 * Don't do this if the CPU already enforces it. 3938 */ 3939 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3940 arr[1].host = cpuc->pebs_enabled; 3941 arr[1].guest = 0; 3942 *nr = 2; 3943 } 3944 3945 return arr; 3946 } 3947 3948 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3949 { 3950 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3951 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3952 int idx; 3953 3954 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3955 struct perf_event *event = cpuc->events[idx]; 3956 3957 arr[idx].msr = x86_pmu_config_addr(idx); 3958 arr[idx].host = arr[idx].guest = 0; 3959 3960 if (!test_bit(idx, cpuc->active_mask)) 3961 continue; 3962 3963 arr[idx].host = arr[idx].guest = 3964 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3965 3966 if (event->attr.exclude_host) 3967 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3968 else if (event->attr.exclude_guest) 3969 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3970 } 3971 3972 *nr = x86_pmu.num_counters; 3973 return arr; 3974 } 3975 3976 static void core_pmu_enable_event(struct perf_event *event) 3977 { 3978 if (!event->attr.exclude_host) 3979 x86_pmu_enable_event(event); 3980 } 3981 3982 static void core_pmu_enable_all(int added) 3983 { 3984 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3985 int idx; 3986 3987 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3988 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3989 3990 if (!test_bit(idx, cpuc->active_mask) || 3991 cpuc->events[idx]->attr.exclude_host) 3992 continue; 3993 3994 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3995 } 3996 } 3997 3998 static int hsw_hw_config(struct perf_event *event) 3999 { 4000 int ret = intel_pmu_hw_config(event); 4001 4002 if (ret) 4003 return ret; 4004 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4005 return 0; 4006 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4007 4008 /* 4009 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4010 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4011 * this combination. 4012 */ 4013 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4014 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4015 event->attr.precise_ip > 0)) 4016 return -EOPNOTSUPP; 4017 4018 if (event_is_checkpointed(event)) { 4019 /* 4020 * Sampling of checkpointed events can cause situations where 4021 * the CPU constantly aborts because of a overflow, which is 4022 * then checkpointed back and ignored. Forbid checkpointing 4023 * for sampling. 4024 * 4025 * But still allow a long sampling period, so that perf stat 4026 * from KVM works. 4027 */ 4028 if (event->attr.sample_period > 0 && 4029 event->attr.sample_period < 0x7fffffff) 4030 return -EOPNOTSUPP; 4031 } 4032 return 0; 4033 } 4034 4035 static struct event_constraint counter0_constraint = 4036 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4037 4038 static struct event_constraint counter2_constraint = 4039 EVENT_CONSTRAINT(0, 0x4, 0); 4040 4041 static struct event_constraint fixed0_constraint = 4042 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4043 4044 static struct event_constraint fixed0_counter0_constraint = 4045 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4046 4047 static struct event_constraint * 4048 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4049 struct perf_event *event) 4050 { 4051 struct event_constraint *c; 4052 4053 c = intel_get_event_constraints(cpuc, idx, event); 4054 4055 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4056 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4057 if (c->idxmsk64 & (1U << 2)) 4058 return &counter2_constraint; 4059 return &emptyconstraint; 4060 } 4061 4062 return c; 4063 } 4064 4065 static struct event_constraint * 4066 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4067 struct perf_event *event) 4068 { 4069 /* 4070 * Fixed counter 0 has less skid. 4071 * Force instruction:ppp in Fixed counter 0 4072 */ 4073 if ((event->attr.precise_ip == 3) && 4074 constraint_match(&fixed0_constraint, event->hw.config)) 4075 return &fixed0_constraint; 4076 4077 return hsw_get_event_constraints(cpuc, idx, event); 4078 } 4079 4080 static struct event_constraint * 4081 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4082 struct perf_event *event) 4083 { 4084 struct event_constraint *c; 4085 4086 c = icl_get_event_constraints(cpuc, idx, event); 4087 4088 /* 4089 * The :ppp indicates the Precise Distribution (PDist) facility, which 4090 * is only supported on the GP counter 0. If a :ppp event which is not 4091 * available on the GP counter 0, error out. 4092 * Exception: Instruction PDIR is only available on the fixed counter 0. 4093 */ 4094 if ((event->attr.precise_ip == 3) && 4095 !constraint_match(&fixed0_constraint, event->hw.config)) { 4096 if (c->idxmsk64 & BIT_ULL(0)) 4097 return &counter0_constraint; 4098 4099 return &emptyconstraint; 4100 } 4101 4102 return c; 4103 } 4104 4105 static struct event_constraint * 4106 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4107 struct perf_event *event) 4108 { 4109 struct event_constraint *c; 4110 4111 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4112 if (event->attr.precise_ip == 3) 4113 return &counter0_constraint; 4114 4115 c = intel_get_event_constraints(cpuc, idx, event); 4116 4117 return c; 4118 } 4119 4120 static struct event_constraint * 4121 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4122 struct perf_event *event) 4123 { 4124 struct event_constraint *c; 4125 4126 /* 4127 * :ppp means to do reduced skid PEBS, 4128 * which is available on PMC0 and fixed counter 0. 4129 */ 4130 if (event->attr.precise_ip == 3) { 4131 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4132 if (constraint_match(&fixed0_constraint, event->hw.config)) 4133 return &fixed0_counter0_constraint; 4134 4135 return &counter0_constraint; 4136 } 4137 4138 c = intel_get_event_constraints(cpuc, idx, event); 4139 4140 return c; 4141 } 4142 4143 static bool allow_tsx_force_abort = true; 4144 4145 static struct event_constraint * 4146 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4147 struct perf_event *event) 4148 { 4149 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4150 4151 /* 4152 * Without TFA we must not use PMC3. 4153 */ 4154 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4155 c = dyn_constraint(cpuc, c, idx); 4156 c->idxmsk64 &= ~(1ULL << 3); 4157 c->weight--; 4158 } 4159 4160 return c; 4161 } 4162 4163 static struct event_constraint * 4164 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4165 struct perf_event *event) 4166 { 4167 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4168 4169 if (pmu->cpu_type == hybrid_big) 4170 return spr_get_event_constraints(cpuc, idx, event); 4171 else if (pmu->cpu_type == hybrid_small) 4172 return tnt_get_event_constraints(cpuc, idx, event); 4173 4174 WARN_ON(1); 4175 return &emptyconstraint; 4176 } 4177 4178 static int adl_hw_config(struct perf_event *event) 4179 { 4180 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4181 4182 if (pmu->cpu_type == hybrid_big) 4183 return hsw_hw_config(event); 4184 else if (pmu->cpu_type == hybrid_small) 4185 return intel_pmu_hw_config(event); 4186 4187 WARN_ON(1); 4188 return -EOPNOTSUPP; 4189 } 4190 4191 static u8 adl_get_hybrid_cpu_type(void) 4192 { 4193 return hybrid_big; 4194 } 4195 4196 /* 4197 * Broadwell: 4198 * 4199 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4200 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4201 * the two to enforce a minimum period of 128 (the smallest value that has bits 4202 * 0-5 cleared and >= 100). 4203 * 4204 * Because of how the code in x86_perf_event_set_period() works, the truncation 4205 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4206 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4207 * 4208 * Therefore the effective (average) period matches the requested period, 4209 * despite coarser hardware granularity. 4210 */ 4211 static u64 bdw_limit_period(struct perf_event *event, u64 left) 4212 { 4213 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4214 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4215 if (left < 128) 4216 left = 128; 4217 left &= ~0x3fULL; 4218 } 4219 return left; 4220 } 4221 4222 static u64 nhm_limit_period(struct perf_event *event, u64 left) 4223 { 4224 return max(left, 32ULL); 4225 } 4226 4227 static u64 spr_limit_period(struct perf_event *event, u64 left) 4228 { 4229 if (event->attr.precise_ip == 3) 4230 return max(left, 128ULL); 4231 4232 return left; 4233 } 4234 4235 PMU_FORMAT_ATTR(event, "config:0-7" ); 4236 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4237 PMU_FORMAT_ATTR(edge, "config:18" ); 4238 PMU_FORMAT_ATTR(pc, "config:19" ); 4239 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4240 PMU_FORMAT_ATTR(inv, "config:23" ); 4241 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4242 PMU_FORMAT_ATTR(in_tx, "config:32"); 4243 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4244 4245 static struct attribute *intel_arch_formats_attr[] = { 4246 &format_attr_event.attr, 4247 &format_attr_umask.attr, 4248 &format_attr_edge.attr, 4249 &format_attr_pc.attr, 4250 &format_attr_inv.attr, 4251 &format_attr_cmask.attr, 4252 NULL, 4253 }; 4254 4255 ssize_t intel_event_sysfs_show(char *page, u64 config) 4256 { 4257 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4258 4259 return x86_event_sysfs_show(page, config, event); 4260 } 4261 4262 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4263 { 4264 struct intel_shared_regs *regs; 4265 int i; 4266 4267 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4268 GFP_KERNEL, cpu_to_node(cpu)); 4269 if (regs) { 4270 /* 4271 * initialize the locks to keep lockdep happy 4272 */ 4273 for (i = 0; i < EXTRA_REG_MAX; i++) 4274 raw_spin_lock_init(®s->regs[i].lock); 4275 4276 regs->core_id = -1; 4277 } 4278 return regs; 4279 } 4280 4281 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4282 { 4283 struct intel_excl_cntrs *c; 4284 4285 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4286 GFP_KERNEL, cpu_to_node(cpu)); 4287 if (c) { 4288 raw_spin_lock_init(&c->lock); 4289 c->core_id = -1; 4290 } 4291 return c; 4292 } 4293 4294 4295 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4296 { 4297 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4298 4299 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4300 cpuc->shared_regs = allocate_shared_regs(cpu); 4301 if (!cpuc->shared_regs) 4302 goto err; 4303 } 4304 4305 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4306 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4307 4308 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4309 if (!cpuc->constraint_list) 4310 goto err_shared_regs; 4311 } 4312 4313 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4314 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4315 if (!cpuc->excl_cntrs) 4316 goto err_constraint_list; 4317 4318 cpuc->excl_thread_id = 0; 4319 } 4320 4321 return 0; 4322 4323 err_constraint_list: 4324 kfree(cpuc->constraint_list); 4325 cpuc->constraint_list = NULL; 4326 4327 err_shared_regs: 4328 kfree(cpuc->shared_regs); 4329 cpuc->shared_regs = NULL; 4330 4331 err: 4332 return -ENOMEM; 4333 } 4334 4335 static int intel_pmu_cpu_prepare(int cpu) 4336 { 4337 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4338 } 4339 4340 static void flip_smm_bit(void *data) 4341 { 4342 unsigned long set = *(unsigned long *)data; 4343 4344 if (set > 0) { 4345 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4346 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4347 } else { 4348 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4349 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4350 } 4351 } 4352 4353 static bool init_hybrid_pmu(int cpu) 4354 { 4355 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4356 u8 cpu_type = get_this_hybrid_cpu_type(); 4357 struct x86_hybrid_pmu *pmu = NULL; 4358 int i; 4359 4360 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4361 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4362 4363 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4364 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4365 pmu = &x86_pmu.hybrid_pmu[i]; 4366 break; 4367 } 4368 } 4369 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4370 cpuc->pmu = NULL; 4371 return false; 4372 } 4373 4374 /* Only check and dump the PMU information for the first CPU */ 4375 if (!cpumask_empty(&pmu->supported_cpus)) 4376 goto end; 4377 4378 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4379 return false; 4380 4381 pr_info("%s PMU driver: ", pmu->name); 4382 4383 if (pmu->intel_cap.pebs_output_pt_available) 4384 pr_cont("PEBS-via-PT "); 4385 4386 pr_cont("\n"); 4387 4388 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4389 pmu->intel_ctrl); 4390 4391 end: 4392 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4393 cpuc->pmu = &pmu->pmu; 4394 4395 x86_pmu_update_cpu_context(&pmu->pmu, cpu); 4396 4397 return true; 4398 } 4399 4400 static void intel_pmu_cpu_starting(int cpu) 4401 { 4402 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4403 int core_id = topology_core_id(cpu); 4404 int i; 4405 4406 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4407 return; 4408 4409 init_debug_store_on_cpu(cpu); 4410 /* 4411 * Deal with CPUs that don't clear their LBRs on power-up. 4412 */ 4413 intel_pmu_lbr_reset(); 4414 4415 cpuc->lbr_sel = NULL; 4416 4417 if (x86_pmu.flags & PMU_FL_TFA) { 4418 WARN_ON_ONCE(cpuc->tfa_shadow); 4419 cpuc->tfa_shadow = ~0ULL; 4420 intel_set_tfa(cpuc, false); 4421 } 4422 4423 if (x86_pmu.version > 1) 4424 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4425 4426 /* 4427 * Disable perf metrics if any added CPU doesn't support it. 4428 * 4429 * Turn off the check for a hybrid architecture, because the 4430 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4431 * the architecture features. The perf metrics is a model-specific 4432 * feature for now. The corresponding bit should always be 0 on 4433 * a hybrid platform, e.g., Alder Lake. 4434 */ 4435 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4436 union perf_capabilities perf_cap; 4437 4438 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4439 if (!perf_cap.perf_metrics) { 4440 x86_pmu.intel_cap.perf_metrics = 0; 4441 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4442 } 4443 } 4444 4445 if (!cpuc->shared_regs) 4446 return; 4447 4448 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4449 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4450 struct intel_shared_regs *pc; 4451 4452 pc = per_cpu(cpu_hw_events, i).shared_regs; 4453 if (pc && pc->core_id == core_id) { 4454 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4455 cpuc->shared_regs = pc; 4456 break; 4457 } 4458 } 4459 cpuc->shared_regs->core_id = core_id; 4460 cpuc->shared_regs->refcnt++; 4461 } 4462 4463 if (x86_pmu.lbr_sel_map) 4464 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4465 4466 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4467 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4468 struct cpu_hw_events *sibling; 4469 struct intel_excl_cntrs *c; 4470 4471 sibling = &per_cpu(cpu_hw_events, i); 4472 c = sibling->excl_cntrs; 4473 if (c && c->core_id == core_id) { 4474 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4475 cpuc->excl_cntrs = c; 4476 if (!sibling->excl_thread_id) 4477 cpuc->excl_thread_id = 1; 4478 break; 4479 } 4480 } 4481 cpuc->excl_cntrs->core_id = core_id; 4482 cpuc->excl_cntrs->refcnt++; 4483 } 4484 } 4485 4486 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4487 { 4488 struct intel_excl_cntrs *c; 4489 4490 c = cpuc->excl_cntrs; 4491 if (c) { 4492 if (c->core_id == -1 || --c->refcnt == 0) 4493 kfree(c); 4494 cpuc->excl_cntrs = NULL; 4495 } 4496 4497 kfree(cpuc->constraint_list); 4498 cpuc->constraint_list = NULL; 4499 } 4500 4501 static void intel_pmu_cpu_dying(int cpu) 4502 { 4503 fini_debug_store_on_cpu(cpu); 4504 } 4505 4506 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4507 { 4508 struct intel_shared_regs *pc; 4509 4510 pc = cpuc->shared_regs; 4511 if (pc) { 4512 if (pc->core_id == -1 || --pc->refcnt == 0) 4513 kfree(pc); 4514 cpuc->shared_regs = NULL; 4515 } 4516 4517 free_excl_cntrs(cpuc); 4518 } 4519 4520 static void intel_pmu_cpu_dead(int cpu) 4521 { 4522 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4523 4524 intel_cpuc_finish(cpuc); 4525 4526 if (is_hybrid() && cpuc->pmu) 4527 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4528 } 4529 4530 static void intel_pmu_sched_task(struct perf_event_context *ctx, 4531 bool sched_in) 4532 { 4533 intel_pmu_pebs_sched_task(ctx, sched_in); 4534 intel_pmu_lbr_sched_task(ctx, sched_in); 4535 } 4536 4537 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4538 struct perf_event_context *next) 4539 { 4540 intel_pmu_lbr_swap_task_ctx(prev, next); 4541 } 4542 4543 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4544 { 4545 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4546 } 4547 4548 static void intel_aux_output_init(void) 4549 { 4550 /* Refer also intel_pmu_aux_output_match() */ 4551 if (x86_pmu.intel_cap.pebs_output_pt_available) 4552 x86_pmu.assign = intel_pmu_assign_event; 4553 } 4554 4555 static int intel_pmu_aux_output_match(struct perf_event *event) 4556 { 4557 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 4558 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4559 return 0; 4560 4561 return is_intel_pt_event(event); 4562 } 4563 4564 static int intel_pmu_filter_match(struct perf_event *event) 4565 { 4566 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4567 unsigned int cpu = smp_processor_id(); 4568 4569 return cpumask_test_cpu(cpu, &pmu->supported_cpus); 4570 } 4571 4572 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4573 4574 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4575 4576 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4577 4578 static struct attribute *intel_arch3_formats_attr[] = { 4579 &format_attr_event.attr, 4580 &format_attr_umask.attr, 4581 &format_attr_edge.attr, 4582 &format_attr_pc.attr, 4583 &format_attr_any.attr, 4584 &format_attr_inv.attr, 4585 &format_attr_cmask.attr, 4586 NULL, 4587 }; 4588 4589 static struct attribute *hsw_format_attr[] = { 4590 &format_attr_in_tx.attr, 4591 &format_attr_in_tx_cp.attr, 4592 &format_attr_offcore_rsp.attr, 4593 &format_attr_ldlat.attr, 4594 NULL 4595 }; 4596 4597 static struct attribute *nhm_format_attr[] = { 4598 &format_attr_offcore_rsp.attr, 4599 &format_attr_ldlat.attr, 4600 NULL 4601 }; 4602 4603 static struct attribute *slm_format_attr[] = { 4604 &format_attr_offcore_rsp.attr, 4605 NULL 4606 }; 4607 4608 static struct attribute *skl_format_attr[] = { 4609 &format_attr_frontend.attr, 4610 NULL, 4611 }; 4612 4613 static __initconst const struct x86_pmu core_pmu = { 4614 .name = "core", 4615 .handle_irq = x86_pmu_handle_irq, 4616 .disable_all = x86_pmu_disable_all, 4617 .enable_all = core_pmu_enable_all, 4618 .enable = core_pmu_enable_event, 4619 .disable = x86_pmu_disable_event, 4620 .hw_config = core_pmu_hw_config, 4621 .schedule_events = x86_schedule_events, 4622 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4623 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4624 .event_map = intel_pmu_event_map, 4625 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4626 .apic = 1, 4627 .large_pebs_flags = LARGE_PEBS_FLAGS, 4628 4629 /* 4630 * Intel PMCs cannot be accessed sanely above 32-bit width, 4631 * so we install an artificial 1<<31 period regardless of 4632 * the generic event period: 4633 */ 4634 .max_period = (1ULL<<31) - 1, 4635 .get_event_constraints = intel_get_event_constraints, 4636 .put_event_constraints = intel_put_event_constraints, 4637 .event_constraints = intel_core_event_constraints, 4638 .guest_get_msrs = core_guest_get_msrs, 4639 .format_attrs = intel_arch_formats_attr, 4640 .events_sysfs_show = intel_event_sysfs_show, 4641 4642 /* 4643 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4644 * together with PMU version 1 and thus be using core_pmu with 4645 * shared_regs. We need following callbacks here to allocate 4646 * it properly. 4647 */ 4648 .cpu_prepare = intel_pmu_cpu_prepare, 4649 .cpu_starting = intel_pmu_cpu_starting, 4650 .cpu_dying = intel_pmu_cpu_dying, 4651 .cpu_dead = intel_pmu_cpu_dead, 4652 4653 .check_period = intel_pmu_check_period, 4654 4655 .lbr_reset = intel_pmu_lbr_reset_64, 4656 .lbr_read = intel_pmu_lbr_read_64, 4657 .lbr_save = intel_pmu_lbr_save, 4658 .lbr_restore = intel_pmu_lbr_restore, 4659 }; 4660 4661 static __initconst const struct x86_pmu intel_pmu = { 4662 .name = "Intel", 4663 .handle_irq = intel_pmu_handle_irq, 4664 .disable_all = intel_pmu_disable_all, 4665 .enable_all = intel_pmu_enable_all, 4666 .enable = intel_pmu_enable_event, 4667 .disable = intel_pmu_disable_event, 4668 .add = intel_pmu_add_event, 4669 .del = intel_pmu_del_event, 4670 .read = intel_pmu_read_event, 4671 .hw_config = intel_pmu_hw_config, 4672 .schedule_events = x86_schedule_events, 4673 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4674 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4675 .event_map = intel_pmu_event_map, 4676 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4677 .apic = 1, 4678 .large_pebs_flags = LARGE_PEBS_FLAGS, 4679 /* 4680 * Intel PMCs cannot be accessed sanely above 32 bit width, 4681 * so we install an artificial 1<<31 period regardless of 4682 * the generic event period: 4683 */ 4684 .max_period = (1ULL << 31) - 1, 4685 .get_event_constraints = intel_get_event_constraints, 4686 .put_event_constraints = intel_put_event_constraints, 4687 .pebs_aliases = intel_pebs_aliases_core2, 4688 4689 .format_attrs = intel_arch3_formats_attr, 4690 .events_sysfs_show = intel_event_sysfs_show, 4691 4692 .cpu_prepare = intel_pmu_cpu_prepare, 4693 .cpu_starting = intel_pmu_cpu_starting, 4694 .cpu_dying = intel_pmu_cpu_dying, 4695 .cpu_dead = intel_pmu_cpu_dead, 4696 4697 .guest_get_msrs = intel_guest_get_msrs, 4698 .sched_task = intel_pmu_sched_task, 4699 .swap_task_ctx = intel_pmu_swap_task_ctx, 4700 4701 .check_period = intel_pmu_check_period, 4702 4703 .aux_output_match = intel_pmu_aux_output_match, 4704 4705 .lbr_reset = intel_pmu_lbr_reset_64, 4706 .lbr_read = intel_pmu_lbr_read_64, 4707 .lbr_save = intel_pmu_lbr_save, 4708 .lbr_restore = intel_pmu_lbr_restore, 4709 }; 4710 4711 static __init void intel_clovertown_quirk(void) 4712 { 4713 /* 4714 * PEBS is unreliable due to: 4715 * 4716 * AJ67 - PEBS may experience CPL leaks 4717 * AJ68 - PEBS PMI may be delayed by one event 4718 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4719 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4720 * 4721 * AJ67 could be worked around by restricting the OS/USR flags. 4722 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4723 * 4724 * AJ106 could possibly be worked around by not allowing LBR 4725 * usage from PEBS, including the fixup. 4726 * AJ68 could possibly be worked around by always programming 4727 * a pebs_event_reset[0] value and coping with the lost events. 4728 * 4729 * But taken together it might just make sense to not enable PEBS on 4730 * these chips. 4731 */ 4732 pr_warn("PEBS disabled due to CPU errata\n"); 4733 x86_pmu.pebs = 0; 4734 x86_pmu.pebs_constraints = NULL; 4735 } 4736 4737 static const struct x86_cpu_desc isolation_ucodes[] = { 4738 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4739 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 4740 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 4741 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 4742 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4743 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 4744 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 4745 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 4746 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 4747 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 4748 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 4749 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 4750 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 4751 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4752 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 4753 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 4754 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 4755 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4756 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4757 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4758 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4759 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4760 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4761 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4762 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4763 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4764 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4765 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 4766 {} 4767 }; 4768 4769 static void intel_check_pebs_isolation(void) 4770 { 4771 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4772 } 4773 4774 static __init void intel_pebs_isolation_quirk(void) 4775 { 4776 WARN_ON_ONCE(x86_pmu.check_microcode); 4777 x86_pmu.check_microcode = intel_check_pebs_isolation; 4778 intel_check_pebs_isolation(); 4779 } 4780 4781 static const struct x86_cpu_desc pebs_ucodes[] = { 4782 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4783 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4784 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4785 {} 4786 }; 4787 4788 static bool intel_snb_pebs_broken(void) 4789 { 4790 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4791 } 4792 4793 static void intel_snb_check_microcode(void) 4794 { 4795 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4796 return; 4797 4798 /* 4799 * Serialized by the microcode lock.. 4800 */ 4801 if (x86_pmu.pebs_broken) { 4802 pr_info("PEBS enabled due to microcode update\n"); 4803 x86_pmu.pebs_broken = 0; 4804 } else { 4805 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4806 x86_pmu.pebs_broken = 1; 4807 } 4808 } 4809 4810 static bool is_lbr_from(unsigned long msr) 4811 { 4812 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4813 4814 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4815 } 4816 4817 /* 4818 * Under certain circumstances, access certain MSR may cause #GP. 4819 * The function tests if the input MSR can be safely accessed. 4820 */ 4821 static bool check_msr(unsigned long msr, u64 mask) 4822 { 4823 u64 val_old, val_new, val_tmp; 4824 4825 /* 4826 * Disable the check for real HW, so we don't 4827 * mess with potentially enabled registers: 4828 */ 4829 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4830 return true; 4831 4832 /* 4833 * Read the current value, change it and read it back to see if it 4834 * matches, this is needed to detect certain hardware emulators 4835 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4836 */ 4837 if (rdmsrl_safe(msr, &val_old)) 4838 return false; 4839 4840 /* 4841 * Only change the bits which can be updated by wrmsrl. 4842 */ 4843 val_tmp = val_old ^ mask; 4844 4845 if (is_lbr_from(msr)) 4846 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4847 4848 if (wrmsrl_safe(msr, val_tmp) || 4849 rdmsrl_safe(msr, &val_new)) 4850 return false; 4851 4852 /* 4853 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4854 * should equal rdmsrl()'s even with the quirk. 4855 */ 4856 if (val_new != val_tmp) 4857 return false; 4858 4859 if (is_lbr_from(msr)) 4860 val_old = lbr_from_signext_quirk_wr(val_old); 4861 4862 /* Here it's sure that the MSR can be safely accessed. 4863 * Restore the old value and return. 4864 */ 4865 wrmsrl(msr, val_old); 4866 4867 return true; 4868 } 4869 4870 static __init void intel_sandybridge_quirk(void) 4871 { 4872 x86_pmu.check_microcode = intel_snb_check_microcode; 4873 cpus_read_lock(); 4874 intel_snb_check_microcode(); 4875 cpus_read_unlock(); 4876 } 4877 4878 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4879 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4880 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4881 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4882 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4883 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4884 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4885 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4886 }; 4887 4888 static __init void intel_arch_events_quirk(void) 4889 { 4890 int bit; 4891 4892 /* disable event that reported as not present by cpuid */ 4893 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4894 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4895 pr_warn("CPUID marked event: \'%s\' unavailable\n", 4896 intel_arch_events_map[bit].name); 4897 } 4898 } 4899 4900 static __init void intel_nehalem_quirk(void) 4901 { 4902 union cpuid10_ebx ebx; 4903 4904 ebx.full = x86_pmu.events_maskl; 4905 if (ebx.split.no_branch_misses_retired) { 4906 /* 4907 * Erratum AAJ80 detected, we work it around by using 4908 * the BR_MISP_EXEC.ANY event. This will over-count 4909 * branch-misses, but it's still much better than the 4910 * architectural event which is often completely bogus: 4911 */ 4912 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4913 ebx.split.no_branch_misses_retired = 0; 4914 x86_pmu.events_maskl = ebx.full; 4915 pr_info("CPU erratum AAJ80 worked around\n"); 4916 } 4917 } 4918 4919 /* 4920 * enable software workaround for errata: 4921 * SNB: BJ122 4922 * IVB: BV98 4923 * HSW: HSD29 4924 * 4925 * Only needed when HT is enabled. However detecting 4926 * if HT is enabled is difficult (model specific). So instead, 4927 * we enable the workaround in the early boot, and verify if 4928 * it is needed in a later initcall phase once we have valid 4929 * topology information to check if HT is actually enabled 4930 */ 4931 static __init void intel_ht_bug(void) 4932 { 4933 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4934 4935 x86_pmu.start_scheduling = intel_start_scheduling; 4936 x86_pmu.commit_scheduling = intel_commit_scheduling; 4937 x86_pmu.stop_scheduling = intel_stop_scheduling; 4938 } 4939 4940 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4941 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4942 4943 /* Haswell special events */ 4944 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4945 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4946 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4947 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4948 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4949 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4950 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4951 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4952 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4953 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4954 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4955 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4956 4957 static struct attribute *hsw_events_attrs[] = { 4958 EVENT_PTR(td_slots_issued), 4959 EVENT_PTR(td_slots_retired), 4960 EVENT_PTR(td_fetch_bubbles), 4961 EVENT_PTR(td_total_slots), 4962 EVENT_PTR(td_total_slots_scale), 4963 EVENT_PTR(td_recovery_bubbles), 4964 EVENT_PTR(td_recovery_bubbles_scale), 4965 NULL 4966 }; 4967 4968 static struct attribute *hsw_mem_events_attrs[] = { 4969 EVENT_PTR(mem_ld_hsw), 4970 EVENT_PTR(mem_st_hsw), 4971 NULL, 4972 }; 4973 4974 static struct attribute *hsw_tsx_events_attrs[] = { 4975 EVENT_PTR(tx_start), 4976 EVENT_PTR(tx_commit), 4977 EVENT_PTR(tx_abort), 4978 EVENT_PTR(tx_capacity), 4979 EVENT_PTR(tx_conflict), 4980 EVENT_PTR(el_start), 4981 EVENT_PTR(el_commit), 4982 EVENT_PTR(el_abort), 4983 EVENT_PTR(el_capacity), 4984 EVENT_PTR(el_conflict), 4985 EVENT_PTR(cycles_t), 4986 EVENT_PTR(cycles_ct), 4987 NULL 4988 }; 4989 4990 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 4991 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 4992 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 4993 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 4994 4995 static struct attribute *icl_events_attrs[] = { 4996 EVENT_PTR(mem_ld_hsw), 4997 EVENT_PTR(mem_st_hsw), 4998 NULL, 4999 }; 5000 5001 static struct attribute *icl_td_events_attrs[] = { 5002 EVENT_PTR(slots), 5003 EVENT_PTR(td_retiring), 5004 EVENT_PTR(td_bad_spec), 5005 EVENT_PTR(td_fe_bound), 5006 EVENT_PTR(td_be_bound), 5007 NULL, 5008 }; 5009 5010 static struct attribute *icl_tsx_events_attrs[] = { 5011 EVENT_PTR(tx_start), 5012 EVENT_PTR(tx_abort), 5013 EVENT_PTR(tx_commit), 5014 EVENT_PTR(tx_capacity_read), 5015 EVENT_PTR(tx_capacity_write), 5016 EVENT_PTR(tx_conflict), 5017 EVENT_PTR(el_start), 5018 EVENT_PTR(el_abort), 5019 EVENT_PTR(el_commit), 5020 EVENT_PTR(el_capacity_read), 5021 EVENT_PTR(el_capacity_write), 5022 EVENT_PTR(el_conflict), 5023 EVENT_PTR(cycles_t), 5024 EVENT_PTR(cycles_ct), 5025 NULL, 5026 }; 5027 5028 5029 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5030 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5031 5032 static struct attribute *spr_events_attrs[] = { 5033 EVENT_PTR(mem_ld_hsw), 5034 EVENT_PTR(mem_st_spr), 5035 EVENT_PTR(mem_ld_aux), 5036 NULL, 5037 }; 5038 5039 static struct attribute *spr_td_events_attrs[] = { 5040 EVENT_PTR(slots), 5041 EVENT_PTR(td_retiring), 5042 EVENT_PTR(td_bad_spec), 5043 EVENT_PTR(td_fe_bound), 5044 EVENT_PTR(td_be_bound), 5045 EVENT_PTR(td_heavy_ops), 5046 EVENT_PTR(td_br_mispredict), 5047 EVENT_PTR(td_fetch_lat), 5048 EVENT_PTR(td_mem_bound), 5049 NULL, 5050 }; 5051 5052 static struct attribute *spr_tsx_events_attrs[] = { 5053 EVENT_PTR(tx_start), 5054 EVENT_PTR(tx_abort), 5055 EVENT_PTR(tx_commit), 5056 EVENT_PTR(tx_capacity_read), 5057 EVENT_PTR(tx_capacity_write), 5058 EVENT_PTR(tx_conflict), 5059 EVENT_PTR(cycles_t), 5060 EVENT_PTR(cycles_ct), 5061 NULL, 5062 }; 5063 5064 static ssize_t freeze_on_smi_show(struct device *cdev, 5065 struct device_attribute *attr, 5066 char *buf) 5067 { 5068 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5069 } 5070 5071 static DEFINE_MUTEX(freeze_on_smi_mutex); 5072 5073 static ssize_t freeze_on_smi_store(struct device *cdev, 5074 struct device_attribute *attr, 5075 const char *buf, size_t count) 5076 { 5077 unsigned long val; 5078 ssize_t ret; 5079 5080 ret = kstrtoul(buf, 0, &val); 5081 if (ret) 5082 return ret; 5083 5084 if (val > 1) 5085 return -EINVAL; 5086 5087 mutex_lock(&freeze_on_smi_mutex); 5088 5089 if (x86_pmu.attr_freeze_on_smi == val) 5090 goto done; 5091 5092 x86_pmu.attr_freeze_on_smi = val; 5093 5094 cpus_read_lock(); 5095 on_each_cpu(flip_smm_bit, &val, 1); 5096 cpus_read_unlock(); 5097 done: 5098 mutex_unlock(&freeze_on_smi_mutex); 5099 5100 return count; 5101 } 5102 5103 static void update_tfa_sched(void *ignored) 5104 { 5105 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5106 5107 /* 5108 * check if PMC3 is used 5109 * and if so force schedule out for all event types all contexts 5110 */ 5111 if (test_bit(3, cpuc->active_mask)) 5112 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5113 } 5114 5115 static ssize_t show_sysctl_tfa(struct device *cdev, 5116 struct device_attribute *attr, 5117 char *buf) 5118 { 5119 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5120 } 5121 5122 static ssize_t set_sysctl_tfa(struct device *cdev, 5123 struct device_attribute *attr, 5124 const char *buf, size_t count) 5125 { 5126 bool val; 5127 ssize_t ret; 5128 5129 ret = kstrtobool(buf, &val); 5130 if (ret) 5131 return ret; 5132 5133 /* no change */ 5134 if (val == allow_tsx_force_abort) 5135 return count; 5136 5137 allow_tsx_force_abort = val; 5138 5139 cpus_read_lock(); 5140 on_each_cpu(update_tfa_sched, NULL, 1); 5141 cpus_read_unlock(); 5142 5143 return count; 5144 } 5145 5146 5147 static DEVICE_ATTR_RW(freeze_on_smi); 5148 5149 static ssize_t branches_show(struct device *cdev, 5150 struct device_attribute *attr, 5151 char *buf) 5152 { 5153 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5154 } 5155 5156 static DEVICE_ATTR_RO(branches); 5157 5158 static struct attribute *lbr_attrs[] = { 5159 &dev_attr_branches.attr, 5160 NULL 5161 }; 5162 5163 static char pmu_name_str[30]; 5164 5165 static ssize_t pmu_name_show(struct device *cdev, 5166 struct device_attribute *attr, 5167 char *buf) 5168 { 5169 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5170 } 5171 5172 static DEVICE_ATTR_RO(pmu_name); 5173 5174 static struct attribute *intel_pmu_caps_attrs[] = { 5175 &dev_attr_pmu_name.attr, 5176 NULL 5177 }; 5178 5179 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5180 show_sysctl_tfa, 5181 set_sysctl_tfa); 5182 5183 static struct attribute *intel_pmu_attrs[] = { 5184 &dev_attr_freeze_on_smi.attr, 5185 &dev_attr_allow_tsx_force_abort.attr, 5186 NULL, 5187 }; 5188 5189 static umode_t 5190 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5191 { 5192 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5193 } 5194 5195 static umode_t 5196 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5197 { 5198 return x86_pmu.pebs ? attr->mode : 0; 5199 } 5200 5201 static umode_t 5202 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5203 { 5204 return x86_pmu.lbr_nr ? attr->mode : 0; 5205 } 5206 5207 static umode_t 5208 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5209 { 5210 return x86_pmu.version >= 2 ? attr->mode : 0; 5211 } 5212 5213 static umode_t 5214 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5215 { 5216 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5217 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5218 5219 return attr->mode; 5220 } 5221 5222 static struct attribute_group group_events_td = { 5223 .name = "events", 5224 }; 5225 5226 static struct attribute_group group_events_mem = { 5227 .name = "events", 5228 .is_visible = pebs_is_visible, 5229 }; 5230 5231 static struct attribute_group group_events_tsx = { 5232 .name = "events", 5233 .is_visible = tsx_is_visible, 5234 }; 5235 5236 static struct attribute_group group_caps_gen = { 5237 .name = "caps", 5238 .attrs = intel_pmu_caps_attrs, 5239 }; 5240 5241 static struct attribute_group group_caps_lbr = { 5242 .name = "caps", 5243 .attrs = lbr_attrs, 5244 .is_visible = lbr_is_visible, 5245 }; 5246 5247 static struct attribute_group group_format_extra = { 5248 .name = "format", 5249 .is_visible = exra_is_visible, 5250 }; 5251 5252 static struct attribute_group group_format_extra_skl = { 5253 .name = "format", 5254 .is_visible = exra_is_visible, 5255 }; 5256 5257 static struct attribute_group group_default = { 5258 .attrs = intel_pmu_attrs, 5259 .is_visible = default_is_visible, 5260 }; 5261 5262 static const struct attribute_group *attr_update[] = { 5263 &group_events_td, 5264 &group_events_mem, 5265 &group_events_tsx, 5266 &group_caps_gen, 5267 &group_caps_lbr, 5268 &group_format_extra, 5269 &group_format_extra_skl, 5270 &group_default, 5271 NULL, 5272 }; 5273 5274 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5275 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5276 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5277 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5278 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5279 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5280 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5281 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5282 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5283 5284 static struct attribute *adl_hybrid_events_attrs[] = { 5285 EVENT_PTR(slots_adl), 5286 EVENT_PTR(td_retiring_adl), 5287 EVENT_PTR(td_bad_spec_adl), 5288 EVENT_PTR(td_fe_bound_adl), 5289 EVENT_PTR(td_be_bound_adl), 5290 EVENT_PTR(td_heavy_ops_adl), 5291 EVENT_PTR(td_br_mis_adl), 5292 EVENT_PTR(td_fetch_lat_adl), 5293 EVENT_PTR(td_mem_bound_adl), 5294 NULL, 5295 }; 5296 5297 /* Must be in IDX order */ 5298 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5299 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5300 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5301 5302 static struct attribute *adl_hybrid_mem_attrs[] = { 5303 EVENT_PTR(mem_ld_adl), 5304 EVENT_PTR(mem_st_adl), 5305 EVENT_PTR(mem_ld_aux_adl), 5306 NULL, 5307 }; 5308 5309 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5310 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5311 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5312 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5313 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5314 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5315 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5316 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5317 5318 static struct attribute *adl_hybrid_tsx_attrs[] = { 5319 EVENT_PTR(tx_start_adl), 5320 EVENT_PTR(tx_abort_adl), 5321 EVENT_PTR(tx_commit_adl), 5322 EVENT_PTR(tx_capacity_read_adl), 5323 EVENT_PTR(tx_capacity_write_adl), 5324 EVENT_PTR(tx_conflict_adl), 5325 EVENT_PTR(cycles_t_adl), 5326 EVENT_PTR(cycles_ct_adl), 5327 NULL, 5328 }; 5329 5330 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5331 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5332 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5333 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5334 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5335 5336 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5337 FORMAT_HYBRID_PTR(in_tx), 5338 FORMAT_HYBRID_PTR(in_tx_cp), 5339 FORMAT_HYBRID_PTR(offcore_rsp), 5340 FORMAT_HYBRID_PTR(ldlat), 5341 FORMAT_HYBRID_PTR(frontend), 5342 NULL, 5343 }; 5344 5345 static struct attribute *adl_hybrid_extra_attr[] = { 5346 FORMAT_HYBRID_PTR(offcore_rsp), 5347 FORMAT_HYBRID_PTR(ldlat), 5348 FORMAT_HYBRID_PTR(frontend), 5349 NULL, 5350 }; 5351 5352 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5353 { 5354 struct device *dev = kobj_to_dev(kobj); 5355 struct x86_hybrid_pmu *pmu = 5356 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5357 struct perf_pmu_events_hybrid_attr *pmu_attr = 5358 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5359 5360 return pmu->cpu_type & pmu_attr->pmu_type; 5361 } 5362 5363 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5364 struct attribute *attr, int i) 5365 { 5366 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5367 } 5368 5369 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5370 { 5371 int cpu = cpumask_first(&pmu->supported_cpus); 5372 5373 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5374 } 5375 5376 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5377 struct attribute *attr, int i) 5378 { 5379 struct device *dev = kobj_to_dev(kobj); 5380 struct x86_hybrid_pmu *pmu = 5381 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5382 int cpu = hybrid_find_supported_cpu(pmu); 5383 5384 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5385 } 5386 5387 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5388 struct attribute *attr, int i) 5389 { 5390 struct device *dev = kobj_to_dev(kobj); 5391 struct x86_hybrid_pmu *pmu = 5392 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5393 struct perf_pmu_format_hybrid_attr *pmu_attr = 5394 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5395 int cpu = hybrid_find_supported_cpu(pmu); 5396 5397 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5398 } 5399 5400 static struct attribute_group hybrid_group_events_td = { 5401 .name = "events", 5402 .is_visible = hybrid_events_is_visible, 5403 }; 5404 5405 static struct attribute_group hybrid_group_events_mem = { 5406 .name = "events", 5407 .is_visible = hybrid_events_is_visible, 5408 }; 5409 5410 static struct attribute_group hybrid_group_events_tsx = { 5411 .name = "events", 5412 .is_visible = hybrid_tsx_is_visible, 5413 }; 5414 5415 static struct attribute_group hybrid_group_format_extra = { 5416 .name = "format", 5417 .is_visible = hybrid_format_is_visible, 5418 }; 5419 5420 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5421 struct device_attribute *attr, 5422 char *buf) 5423 { 5424 struct x86_hybrid_pmu *pmu = 5425 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5426 5427 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5428 } 5429 5430 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5431 static struct attribute *intel_hybrid_cpus_attrs[] = { 5432 &dev_attr_cpus.attr, 5433 NULL, 5434 }; 5435 5436 static struct attribute_group hybrid_group_cpus = { 5437 .attrs = intel_hybrid_cpus_attrs, 5438 }; 5439 5440 static const struct attribute_group *hybrid_attr_update[] = { 5441 &hybrid_group_events_td, 5442 &hybrid_group_events_mem, 5443 &hybrid_group_events_tsx, 5444 &group_caps_gen, 5445 &group_caps_lbr, 5446 &hybrid_group_format_extra, 5447 &group_default, 5448 &hybrid_group_cpus, 5449 NULL, 5450 }; 5451 5452 static struct attribute *empty_attrs; 5453 5454 static void intel_pmu_check_num_counters(int *num_counters, 5455 int *num_counters_fixed, 5456 u64 *intel_ctrl, u64 fixed_mask) 5457 { 5458 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5459 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5460 *num_counters, INTEL_PMC_MAX_GENERIC); 5461 *num_counters = INTEL_PMC_MAX_GENERIC; 5462 } 5463 *intel_ctrl = (1ULL << *num_counters) - 1; 5464 5465 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5466 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5467 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5468 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5469 } 5470 5471 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5472 } 5473 5474 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5475 int num_counters, 5476 int num_counters_fixed, 5477 u64 intel_ctrl) 5478 { 5479 struct event_constraint *c; 5480 5481 if (!event_constraints) 5482 return; 5483 5484 /* 5485 * event on fixed counter2 (REF_CYCLES) only works on this 5486 * counter, so do not extend mask to generic counters 5487 */ 5488 for_each_event_constraint(c, event_constraints) { 5489 /* 5490 * Don't extend the topdown slots and metrics 5491 * events to the generic counters. 5492 */ 5493 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5494 /* 5495 * Disable topdown slots and metrics events, 5496 * if slots event is not in CPUID. 5497 */ 5498 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5499 c->idxmsk64 = 0; 5500 c->weight = hweight64(c->idxmsk64); 5501 continue; 5502 } 5503 5504 if (c->cmask == FIXED_EVENT_FLAGS) { 5505 /* Disabled fixed counters which are not in CPUID */ 5506 c->idxmsk64 &= intel_ctrl; 5507 5508 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) 5509 c->idxmsk64 |= (1ULL << num_counters) - 1; 5510 } 5511 c->idxmsk64 &= 5512 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5513 c->weight = hweight64(c->idxmsk64); 5514 } 5515 } 5516 5517 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5518 { 5519 struct extra_reg *er; 5520 5521 /* 5522 * Access extra MSR may cause #GP under certain circumstances. 5523 * E.g. KVM doesn't support offcore event 5524 * Check all extra_regs here. 5525 */ 5526 if (!extra_regs) 5527 return; 5528 5529 for (er = extra_regs; er->msr; er++) { 5530 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5531 /* Disable LBR select mapping */ 5532 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5533 x86_pmu.lbr_sel_map = NULL; 5534 } 5535 } 5536 5537 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5538 { 5539 struct x86_hybrid_pmu *pmu; 5540 int i; 5541 5542 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5543 pmu = &x86_pmu.hybrid_pmu[i]; 5544 5545 intel_pmu_check_num_counters(&pmu->num_counters, 5546 &pmu->num_counters_fixed, 5547 &pmu->intel_ctrl, 5548 fixed_mask); 5549 5550 if (pmu->intel_cap.perf_metrics) { 5551 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5552 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5553 } 5554 5555 if (pmu->intel_cap.pebs_output_pt_available) 5556 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5557 5558 intel_pmu_check_event_constraints(pmu->event_constraints, 5559 pmu->num_counters, 5560 pmu->num_counters_fixed, 5561 pmu->intel_ctrl); 5562 5563 intel_pmu_check_extra_regs(pmu->extra_regs); 5564 } 5565 } 5566 5567 __init int intel_pmu_init(void) 5568 { 5569 struct attribute **extra_skl_attr = &empty_attrs; 5570 struct attribute **extra_attr = &empty_attrs; 5571 struct attribute **td_attr = &empty_attrs; 5572 struct attribute **mem_attr = &empty_attrs; 5573 struct attribute **tsx_attr = &empty_attrs; 5574 union cpuid10_edx edx; 5575 union cpuid10_eax eax; 5576 union cpuid10_ebx ebx; 5577 unsigned int fixed_mask; 5578 bool pmem = false; 5579 int version, i; 5580 char *name; 5581 struct x86_hybrid_pmu *pmu; 5582 5583 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5584 switch (boot_cpu_data.x86) { 5585 case 0x6: 5586 return p6_pmu_init(); 5587 case 0xb: 5588 return knc_pmu_init(); 5589 case 0xf: 5590 return p4_pmu_init(); 5591 } 5592 return -ENODEV; 5593 } 5594 5595 /* 5596 * Check whether the Architectural PerfMon supports 5597 * Branch Misses Retired hw_event or not. 5598 */ 5599 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5600 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5601 return -ENODEV; 5602 5603 version = eax.split.version_id; 5604 if (version < 2) 5605 x86_pmu = core_pmu; 5606 else 5607 x86_pmu = intel_pmu; 5608 5609 x86_pmu.version = version; 5610 x86_pmu.num_counters = eax.split.num_counters; 5611 x86_pmu.cntval_bits = eax.split.bit_width; 5612 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5613 5614 x86_pmu.events_maskl = ebx.full; 5615 x86_pmu.events_mask_len = eax.split.mask_length; 5616 5617 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5618 5619 /* 5620 * Quirk: v2 perfmon does not report fixed-purpose events, so 5621 * assume at least 3 events, when not running in a hypervisor: 5622 */ 5623 if (version > 1 && version < 5) { 5624 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5625 5626 x86_pmu.num_counters_fixed = 5627 max((int)edx.split.num_counters_fixed, assume); 5628 5629 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5630 } else if (version >= 5) 5631 x86_pmu.num_counters_fixed = fls(fixed_mask); 5632 5633 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5634 u64 capabilities; 5635 5636 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5637 x86_pmu.intel_cap.capabilities = capabilities; 5638 } 5639 5640 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5641 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5642 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5643 } 5644 5645 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5646 intel_pmu_arch_lbr_init(); 5647 5648 intel_ds_init(); 5649 5650 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5651 5652 if (version >= 5) { 5653 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5654 if (x86_pmu.intel_cap.anythread_deprecated) 5655 pr_cont(" AnyThread deprecated, "); 5656 } 5657 5658 /* 5659 * Install the hw-cache-events table: 5660 */ 5661 switch (boot_cpu_data.x86_model) { 5662 case INTEL_FAM6_CORE_YONAH: 5663 pr_cont("Core events, "); 5664 name = "core"; 5665 break; 5666 5667 case INTEL_FAM6_CORE2_MEROM: 5668 x86_add_quirk(intel_clovertown_quirk); 5669 fallthrough; 5670 5671 case INTEL_FAM6_CORE2_MEROM_L: 5672 case INTEL_FAM6_CORE2_PENRYN: 5673 case INTEL_FAM6_CORE2_DUNNINGTON: 5674 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5675 sizeof(hw_cache_event_ids)); 5676 5677 intel_pmu_lbr_init_core(); 5678 5679 x86_pmu.event_constraints = intel_core2_event_constraints; 5680 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5681 pr_cont("Core2 events, "); 5682 name = "core2"; 5683 break; 5684 5685 case INTEL_FAM6_NEHALEM: 5686 case INTEL_FAM6_NEHALEM_EP: 5687 case INTEL_FAM6_NEHALEM_EX: 5688 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5689 sizeof(hw_cache_event_ids)); 5690 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5691 sizeof(hw_cache_extra_regs)); 5692 5693 intel_pmu_lbr_init_nhm(); 5694 5695 x86_pmu.event_constraints = intel_nehalem_event_constraints; 5696 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5697 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5698 x86_pmu.extra_regs = intel_nehalem_extra_regs; 5699 x86_pmu.limit_period = nhm_limit_period; 5700 5701 mem_attr = nhm_mem_events_attrs; 5702 5703 /* UOPS_ISSUED.STALLED_CYCLES */ 5704 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5705 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5706 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5707 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5708 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5709 5710 intel_pmu_pebs_data_source_nhm(); 5711 x86_add_quirk(intel_nehalem_quirk); 5712 x86_pmu.pebs_no_tlb = 1; 5713 extra_attr = nhm_format_attr; 5714 5715 pr_cont("Nehalem events, "); 5716 name = "nehalem"; 5717 break; 5718 5719 case INTEL_FAM6_ATOM_BONNELL: 5720 case INTEL_FAM6_ATOM_BONNELL_MID: 5721 case INTEL_FAM6_ATOM_SALTWELL: 5722 case INTEL_FAM6_ATOM_SALTWELL_MID: 5723 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5724 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5725 sizeof(hw_cache_event_ids)); 5726 5727 intel_pmu_lbr_init_atom(); 5728 5729 x86_pmu.event_constraints = intel_gen_event_constraints; 5730 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5731 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5732 pr_cont("Atom events, "); 5733 name = "bonnell"; 5734 break; 5735 5736 case INTEL_FAM6_ATOM_SILVERMONT: 5737 case INTEL_FAM6_ATOM_SILVERMONT_D: 5738 case INTEL_FAM6_ATOM_SILVERMONT_MID: 5739 case INTEL_FAM6_ATOM_AIRMONT: 5740 case INTEL_FAM6_ATOM_AIRMONT_MID: 5741 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5742 sizeof(hw_cache_event_ids)); 5743 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5744 sizeof(hw_cache_extra_regs)); 5745 5746 intel_pmu_lbr_init_slm(); 5747 5748 x86_pmu.event_constraints = intel_slm_event_constraints; 5749 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5750 x86_pmu.extra_regs = intel_slm_extra_regs; 5751 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5752 td_attr = slm_events_attrs; 5753 extra_attr = slm_format_attr; 5754 pr_cont("Silvermont events, "); 5755 name = "silvermont"; 5756 break; 5757 5758 case INTEL_FAM6_ATOM_GOLDMONT: 5759 case INTEL_FAM6_ATOM_GOLDMONT_D: 5760 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 5761 sizeof(hw_cache_event_ids)); 5762 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 5763 sizeof(hw_cache_extra_regs)); 5764 5765 intel_pmu_lbr_init_skl(); 5766 5767 x86_pmu.event_constraints = intel_slm_event_constraints; 5768 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 5769 x86_pmu.extra_regs = intel_glm_extra_regs; 5770 /* 5771 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5772 * for precise cycles. 5773 * :pp is identical to :ppp 5774 */ 5775 x86_pmu.pebs_aliases = NULL; 5776 x86_pmu.pebs_prec_dist = true; 5777 x86_pmu.lbr_pt_coexist = true; 5778 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5779 td_attr = glm_events_attrs; 5780 extra_attr = slm_format_attr; 5781 pr_cont("Goldmont events, "); 5782 name = "goldmont"; 5783 break; 5784 5785 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5786 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5787 sizeof(hw_cache_event_ids)); 5788 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5789 sizeof(hw_cache_extra_regs)); 5790 5791 intel_pmu_lbr_init_skl(); 5792 5793 x86_pmu.event_constraints = intel_slm_event_constraints; 5794 x86_pmu.extra_regs = intel_glm_extra_regs; 5795 /* 5796 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5797 * for precise cycles. 5798 */ 5799 x86_pmu.pebs_aliases = NULL; 5800 x86_pmu.pebs_prec_dist = true; 5801 x86_pmu.lbr_pt_coexist = true; 5802 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5803 x86_pmu.flags |= PMU_FL_PEBS_ALL; 5804 x86_pmu.get_event_constraints = glp_get_event_constraints; 5805 td_attr = glm_events_attrs; 5806 /* Goldmont Plus has 4-wide pipeline */ 5807 event_attr_td_total_slots_scale_glm.event_str = "4"; 5808 extra_attr = slm_format_attr; 5809 pr_cont("Goldmont plus events, "); 5810 name = "goldmont_plus"; 5811 break; 5812 5813 case INTEL_FAM6_ATOM_TREMONT_D: 5814 case INTEL_FAM6_ATOM_TREMONT: 5815 case INTEL_FAM6_ATOM_TREMONT_L: 5816 x86_pmu.late_ack = true; 5817 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5818 sizeof(hw_cache_event_ids)); 5819 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5820 sizeof(hw_cache_extra_regs)); 5821 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5822 5823 intel_pmu_lbr_init_skl(); 5824 5825 x86_pmu.event_constraints = intel_slm_event_constraints; 5826 x86_pmu.extra_regs = intel_tnt_extra_regs; 5827 /* 5828 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5829 * for precise cycles. 5830 */ 5831 x86_pmu.pebs_aliases = NULL; 5832 x86_pmu.pebs_prec_dist = true; 5833 x86_pmu.lbr_pt_coexist = true; 5834 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5835 x86_pmu.get_event_constraints = tnt_get_event_constraints; 5836 td_attr = tnt_events_attrs; 5837 extra_attr = slm_format_attr; 5838 pr_cont("Tremont events, "); 5839 name = "Tremont"; 5840 break; 5841 5842 case INTEL_FAM6_WESTMERE: 5843 case INTEL_FAM6_WESTMERE_EP: 5844 case INTEL_FAM6_WESTMERE_EX: 5845 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5846 sizeof(hw_cache_event_ids)); 5847 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5848 sizeof(hw_cache_extra_regs)); 5849 5850 intel_pmu_lbr_init_nhm(); 5851 5852 x86_pmu.event_constraints = intel_westmere_event_constraints; 5853 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5854 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5855 x86_pmu.extra_regs = intel_westmere_extra_regs; 5856 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5857 5858 mem_attr = nhm_mem_events_attrs; 5859 5860 /* UOPS_ISSUED.STALLED_CYCLES */ 5861 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5862 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5863 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5864 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5865 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5866 5867 intel_pmu_pebs_data_source_nhm(); 5868 extra_attr = nhm_format_attr; 5869 pr_cont("Westmere events, "); 5870 name = "westmere"; 5871 break; 5872 5873 case INTEL_FAM6_SANDYBRIDGE: 5874 case INTEL_FAM6_SANDYBRIDGE_X: 5875 x86_add_quirk(intel_sandybridge_quirk); 5876 x86_add_quirk(intel_ht_bug); 5877 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5878 sizeof(hw_cache_event_ids)); 5879 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5880 sizeof(hw_cache_extra_regs)); 5881 5882 intel_pmu_lbr_init_snb(); 5883 5884 x86_pmu.event_constraints = intel_snb_event_constraints; 5885 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5886 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5887 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5888 x86_pmu.extra_regs = intel_snbep_extra_regs; 5889 else 5890 x86_pmu.extra_regs = intel_snb_extra_regs; 5891 5892 5893 /* all extra regs are per-cpu when HT is on */ 5894 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5895 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5896 5897 td_attr = snb_events_attrs; 5898 mem_attr = snb_mem_events_attrs; 5899 5900 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5901 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5902 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5903 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5904 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5905 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5906 5907 extra_attr = nhm_format_attr; 5908 5909 pr_cont("SandyBridge events, "); 5910 name = "sandybridge"; 5911 break; 5912 5913 case INTEL_FAM6_IVYBRIDGE: 5914 case INTEL_FAM6_IVYBRIDGE_X: 5915 x86_add_quirk(intel_ht_bug); 5916 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5917 sizeof(hw_cache_event_ids)); 5918 /* dTLB-load-misses on IVB is different than SNB */ 5919 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5920 5921 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5922 sizeof(hw_cache_extra_regs)); 5923 5924 intel_pmu_lbr_init_snb(); 5925 5926 x86_pmu.event_constraints = intel_ivb_event_constraints; 5927 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5928 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5929 x86_pmu.pebs_prec_dist = true; 5930 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5931 x86_pmu.extra_regs = intel_snbep_extra_regs; 5932 else 5933 x86_pmu.extra_regs = intel_snb_extra_regs; 5934 /* all extra regs are per-cpu when HT is on */ 5935 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5936 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5937 5938 td_attr = snb_events_attrs; 5939 mem_attr = snb_mem_events_attrs; 5940 5941 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5942 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5943 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5944 5945 extra_attr = nhm_format_attr; 5946 5947 pr_cont("IvyBridge events, "); 5948 name = "ivybridge"; 5949 break; 5950 5951 5952 case INTEL_FAM6_HASWELL: 5953 case INTEL_FAM6_HASWELL_X: 5954 case INTEL_FAM6_HASWELL_L: 5955 case INTEL_FAM6_HASWELL_G: 5956 x86_add_quirk(intel_ht_bug); 5957 x86_add_quirk(intel_pebs_isolation_quirk); 5958 x86_pmu.late_ack = true; 5959 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5960 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5961 5962 intel_pmu_lbr_init_hsw(); 5963 5964 x86_pmu.event_constraints = intel_hsw_event_constraints; 5965 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5966 x86_pmu.extra_regs = intel_snbep_extra_regs; 5967 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5968 x86_pmu.pebs_prec_dist = true; 5969 /* all extra regs are per-cpu when HT is on */ 5970 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5971 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5972 5973 x86_pmu.hw_config = hsw_hw_config; 5974 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5975 x86_pmu.lbr_double_abort = true; 5976 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5977 hsw_format_attr : nhm_format_attr; 5978 td_attr = hsw_events_attrs; 5979 mem_attr = hsw_mem_events_attrs; 5980 tsx_attr = hsw_tsx_events_attrs; 5981 pr_cont("Haswell events, "); 5982 name = "haswell"; 5983 break; 5984 5985 case INTEL_FAM6_BROADWELL: 5986 case INTEL_FAM6_BROADWELL_D: 5987 case INTEL_FAM6_BROADWELL_G: 5988 case INTEL_FAM6_BROADWELL_X: 5989 x86_add_quirk(intel_pebs_isolation_quirk); 5990 x86_pmu.late_ack = true; 5991 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5992 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5993 5994 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5995 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5996 BDW_L3_MISS|HSW_SNOOP_DRAM; 5997 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 5998 HSW_SNOOP_DRAM; 5999 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6000 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6001 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6002 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6003 6004 intel_pmu_lbr_init_hsw(); 6005 6006 x86_pmu.event_constraints = intel_bdw_event_constraints; 6007 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6008 x86_pmu.extra_regs = intel_snbep_extra_regs; 6009 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6010 x86_pmu.pebs_prec_dist = true; 6011 /* all extra regs are per-cpu when HT is on */ 6012 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6013 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6014 6015 x86_pmu.hw_config = hsw_hw_config; 6016 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6017 x86_pmu.limit_period = bdw_limit_period; 6018 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6019 hsw_format_attr : nhm_format_attr; 6020 td_attr = hsw_events_attrs; 6021 mem_attr = hsw_mem_events_attrs; 6022 tsx_attr = hsw_tsx_events_attrs; 6023 pr_cont("Broadwell events, "); 6024 name = "broadwell"; 6025 break; 6026 6027 case INTEL_FAM6_XEON_PHI_KNL: 6028 case INTEL_FAM6_XEON_PHI_KNM: 6029 memcpy(hw_cache_event_ids, 6030 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6031 memcpy(hw_cache_extra_regs, 6032 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6033 intel_pmu_lbr_init_knl(); 6034 6035 x86_pmu.event_constraints = intel_slm_event_constraints; 6036 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6037 x86_pmu.extra_regs = intel_knl_extra_regs; 6038 6039 /* all extra regs are per-cpu when HT is on */ 6040 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6041 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6042 extra_attr = slm_format_attr; 6043 pr_cont("Knights Landing/Mill events, "); 6044 name = "knights-landing"; 6045 break; 6046 6047 case INTEL_FAM6_SKYLAKE_X: 6048 pmem = true; 6049 fallthrough; 6050 case INTEL_FAM6_SKYLAKE_L: 6051 case INTEL_FAM6_SKYLAKE: 6052 case INTEL_FAM6_KABYLAKE_L: 6053 case INTEL_FAM6_KABYLAKE: 6054 case INTEL_FAM6_COMETLAKE_L: 6055 case INTEL_FAM6_COMETLAKE: 6056 x86_add_quirk(intel_pebs_isolation_quirk); 6057 x86_pmu.late_ack = true; 6058 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6059 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6060 intel_pmu_lbr_init_skl(); 6061 6062 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6063 event_attr_td_recovery_bubbles.event_str_noht = 6064 "event=0xd,umask=0x1,cmask=1"; 6065 event_attr_td_recovery_bubbles.event_str_ht = 6066 "event=0xd,umask=0x1,cmask=1,any=1"; 6067 6068 x86_pmu.event_constraints = intel_skl_event_constraints; 6069 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6070 x86_pmu.extra_regs = intel_skl_extra_regs; 6071 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6072 x86_pmu.pebs_prec_dist = true; 6073 /* all extra regs are per-cpu when HT is on */ 6074 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6075 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6076 6077 x86_pmu.hw_config = hsw_hw_config; 6078 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6079 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6080 hsw_format_attr : nhm_format_attr; 6081 extra_skl_attr = skl_format_attr; 6082 td_attr = hsw_events_attrs; 6083 mem_attr = hsw_mem_events_attrs; 6084 tsx_attr = hsw_tsx_events_attrs; 6085 intel_pmu_pebs_data_source_skl(pmem); 6086 6087 /* 6088 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6089 * TSX force abort hooks are not required on these systems. Only deploy 6090 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6091 */ 6092 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6093 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6094 x86_pmu.flags |= PMU_FL_TFA; 6095 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6096 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6097 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6098 } 6099 6100 pr_cont("Skylake events, "); 6101 name = "skylake"; 6102 break; 6103 6104 case INTEL_FAM6_ICELAKE_X: 6105 case INTEL_FAM6_ICELAKE_D: 6106 pmem = true; 6107 fallthrough; 6108 case INTEL_FAM6_ICELAKE_L: 6109 case INTEL_FAM6_ICELAKE: 6110 case INTEL_FAM6_TIGERLAKE_L: 6111 case INTEL_FAM6_TIGERLAKE: 6112 case INTEL_FAM6_ROCKETLAKE: 6113 x86_pmu.late_ack = true; 6114 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6115 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6116 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6117 intel_pmu_lbr_init_skl(); 6118 6119 x86_pmu.event_constraints = intel_icl_event_constraints; 6120 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6121 x86_pmu.extra_regs = intel_icl_extra_regs; 6122 x86_pmu.pebs_aliases = NULL; 6123 x86_pmu.pebs_prec_dist = true; 6124 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6125 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6126 6127 x86_pmu.hw_config = hsw_hw_config; 6128 x86_pmu.get_event_constraints = icl_get_event_constraints; 6129 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6130 hsw_format_attr : nhm_format_attr; 6131 extra_skl_attr = skl_format_attr; 6132 mem_attr = icl_events_attrs; 6133 td_attr = icl_td_events_attrs; 6134 tsx_attr = icl_tsx_events_attrs; 6135 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6136 x86_pmu.lbr_pt_coexist = true; 6137 intel_pmu_pebs_data_source_skl(pmem); 6138 x86_pmu.num_topdown_events = 4; 6139 x86_pmu.update_topdown_event = icl_update_topdown_event; 6140 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6141 pr_cont("Icelake events, "); 6142 name = "icelake"; 6143 break; 6144 6145 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6146 pmem = true; 6147 x86_pmu.late_ack = true; 6148 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6149 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6150 6151 x86_pmu.event_constraints = intel_spr_event_constraints; 6152 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6153 x86_pmu.extra_regs = intel_spr_extra_regs; 6154 x86_pmu.limit_period = spr_limit_period; 6155 x86_pmu.pebs_aliases = NULL; 6156 x86_pmu.pebs_prec_dist = true; 6157 x86_pmu.pebs_block = true; 6158 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6159 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6160 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6161 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6162 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6163 6164 x86_pmu.hw_config = hsw_hw_config; 6165 x86_pmu.get_event_constraints = spr_get_event_constraints; 6166 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6167 hsw_format_attr : nhm_format_attr; 6168 extra_skl_attr = skl_format_attr; 6169 mem_attr = spr_events_attrs; 6170 td_attr = spr_td_events_attrs; 6171 tsx_attr = spr_tsx_events_attrs; 6172 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6173 x86_pmu.lbr_pt_coexist = true; 6174 intel_pmu_pebs_data_source_skl(pmem); 6175 x86_pmu.num_topdown_events = 8; 6176 x86_pmu.update_topdown_event = icl_update_topdown_event; 6177 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6178 pr_cont("Sapphire Rapids events, "); 6179 name = "sapphire_rapids"; 6180 break; 6181 6182 case INTEL_FAM6_ALDERLAKE: 6183 case INTEL_FAM6_ALDERLAKE_L: 6184 /* 6185 * Alder Lake has 2 types of CPU, core and atom. 6186 * 6187 * Initialize the common PerfMon capabilities here. 6188 */ 6189 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6190 sizeof(struct x86_hybrid_pmu), 6191 GFP_KERNEL); 6192 if (!x86_pmu.hybrid_pmu) 6193 return -ENOMEM; 6194 static_branch_enable(&perf_is_hybrid); 6195 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6196 6197 x86_pmu.pebs_aliases = NULL; 6198 x86_pmu.pebs_prec_dist = true; 6199 x86_pmu.pebs_block = true; 6200 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6201 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6202 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6203 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6204 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6205 x86_pmu.lbr_pt_coexist = true; 6206 intel_pmu_pebs_data_source_skl(false); 6207 x86_pmu.num_topdown_events = 8; 6208 x86_pmu.update_topdown_event = adl_update_topdown_event; 6209 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; 6210 6211 x86_pmu.filter_match = intel_pmu_filter_match; 6212 x86_pmu.get_event_constraints = adl_get_event_constraints; 6213 x86_pmu.hw_config = adl_hw_config; 6214 x86_pmu.limit_period = spr_limit_period; 6215 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6216 /* 6217 * The rtm_abort_event is used to check whether to enable GPRs 6218 * for the RTM abort event. Atom doesn't have the RTM abort 6219 * event. There is no harmful to set it in the common 6220 * x86_pmu.rtm_abort_event. 6221 */ 6222 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6223 6224 td_attr = adl_hybrid_events_attrs; 6225 mem_attr = adl_hybrid_mem_attrs; 6226 tsx_attr = adl_hybrid_tsx_attrs; 6227 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6228 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6229 6230 /* Initialize big core specific PerfMon capabilities.*/ 6231 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6232 pmu->name = "cpu_core"; 6233 pmu->cpu_type = hybrid_big; 6234 pmu->late_ack = true; 6235 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6236 pmu->num_counters = x86_pmu.num_counters + 2; 6237 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6238 } else { 6239 pmu->num_counters = x86_pmu.num_counters; 6240 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6241 } 6242 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6243 pmu->unconstrained = (struct event_constraint) 6244 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6245 0, pmu->num_counters, 0, 0); 6246 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6247 pmu->intel_cap.perf_metrics = 1; 6248 pmu->intel_cap.pebs_output_pt_available = 0; 6249 6250 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6251 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6252 pmu->event_constraints = intel_spr_event_constraints; 6253 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6254 pmu->extra_regs = intel_spr_extra_regs; 6255 6256 /* Initialize Atom core specific PerfMon capabilities.*/ 6257 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6258 pmu->name = "cpu_atom"; 6259 pmu->cpu_type = hybrid_small; 6260 pmu->mid_ack = true; 6261 pmu->num_counters = x86_pmu.num_counters; 6262 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6263 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6264 pmu->unconstrained = (struct event_constraint) 6265 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6266 0, pmu->num_counters, 0, 0); 6267 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6268 pmu->intel_cap.perf_metrics = 0; 6269 pmu->intel_cap.pebs_output_pt_available = 1; 6270 6271 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6272 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6273 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6274 pmu->event_constraints = intel_slm_event_constraints; 6275 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6276 pmu->extra_regs = intel_grt_extra_regs; 6277 pr_cont("Alderlake Hybrid events, "); 6278 name = "alderlake_hybrid"; 6279 break; 6280 6281 default: 6282 switch (x86_pmu.version) { 6283 case 1: 6284 x86_pmu.event_constraints = intel_v1_event_constraints; 6285 pr_cont("generic architected perfmon v1, "); 6286 name = "generic_arch_v1"; 6287 break; 6288 default: 6289 /* 6290 * default constraints for v2 and up 6291 */ 6292 x86_pmu.event_constraints = intel_gen_event_constraints; 6293 pr_cont("generic architected perfmon, "); 6294 name = "generic_arch_v2+"; 6295 break; 6296 } 6297 } 6298 6299 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6300 6301 if (!is_hybrid()) { 6302 group_events_td.attrs = td_attr; 6303 group_events_mem.attrs = mem_attr; 6304 group_events_tsx.attrs = tsx_attr; 6305 group_format_extra.attrs = extra_attr; 6306 group_format_extra_skl.attrs = extra_skl_attr; 6307 6308 x86_pmu.attr_update = attr_update; 6309 } else { 6310 hybrid_group_events_td.attrs = td_attr; 6311 hybrid_group_events_mem.attrs = mem_attr; 6312 hybrid_group_events_tsx.attrs = tsx_attr; 6313 hybrid_group_format_extra.attrs = extra_attr; 6314 6315 x86_pmu.attr_update = hybrid_attr_update; 6316 } 6317 6318 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6319 &x86_pmu.num_counters_fixed, 6320 &x86_pmu.intel_ctrl, 6321 (u64)fixed_mask); 6322 6323 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6324 if (x86_pmu.intel_cap.anythread_deprecated) 6325 x86_pmu.format_attrs = intel_arch_formats_attr; 6326 6327 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6328 x86_pmu.num_counters, 6329 x86_pmu.num_counters_fixed, 6330 x86_pmu.intel_ctrl); 6331 /* 6332 * Access LBR MSR may cause #GP under certain circumstances. 6333 * E.g. KVM doesn't support LBR MSR 6334 * Check all LBT MSR here. 6335 * Disable LBR access if any LBR MSRs can not be accessed. 6336 */ 6337 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6338 x86_pmu.lbr_nr = 0; 6339 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6340 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6341 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6342 x86_pmu.lbr_nr = 0; 6343 } 6344 6345 if (x86_pmu.lbr_nr) { 6346 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6347 6348 /* only support branch_stack snapshot for perfmon >= v2 */ 6349 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6350 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6351 static_call_update(perf_snapshot_branch_stack, 6352 intel_pmu_snapshot_arch_branch_stack); 6353 } else { 6354 static_call_update(perf_snapshot_branch_stack, 6355 intel_pmu_snapshot_branch_stack); 6356 } 6357 } 6358 } 6359 6360 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6361 6362 /* Support full width counters using alternative MSR range */ 6363 if (x86_pmu.intel_cap.full_width_write) { 6364 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6365 x86_pmu.perfctr = MSR_IA32_PMC0; 6366 pr_cont("full-width counters, "); 6367 } 6368 6369 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6370 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6371 6372 if (is_hybrid()) 6373 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6374 6375 intel_aux_output_init(); 6376 6377 return 0; 6378 } 6379 6380 /* 6381 * HT bug: phase 2 init 6382 * Called once we have valid topology information to check 6383 * whether or not HT is enabled 6384 * If HT is off, then we disable the workaround 6385 */ 6386 static __init int fixup_ht_bug(void) 6387 { 6388 int c; 6389 /* 6390 * problem not present on this CPU model, nothing to do 6391 */ 6392 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6393 return 0; 6394 6395 if (topology_max_smt_threads() > 1) { 6396 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6397 return 0; 6398 } 6399 6400 cpus_read_lock(); 6401 6402 hardlockup_detector_perf_stop(); 6403 6404 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6405 6406 x86_pmu.start_scheduling = NULL; 6407 x86_pmu.commit_scheduling = NULL; 6408 x86_pmu.stop_scheduling = NULL; 6409 6410 hardlockup_detector_perf_restart(); 6411 6412 for_each_online_cpu(c) 6413 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6414 6415 cpus_read_unlock(); 6416 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6417 return 0; 6418 } 6419 subsys_initcall(fixup_ht_bug) 6420