1 /* 2 * Per core/cpu state 3 * 4 * Used to coordinate shared registers between HT threads or 5 * among events on a single PMU. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/stddef.h> 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/slab.h> 14 #include <linux/export.h> 15 #include <linux/nmi.h> 16 17 #include <asm/cpufeature.h> 18 #include <asm/hardirq.h> 19 #include <asm/intel-family.h> 20 #include <asm/apic.h> 21 #include <asm/cpu_device_id.h> 22 23 #include "../perf_event.h" 24 25 /* 26 * Intel PerfMon, used on Core and later. 27 */ 28 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 29 { 30 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 31 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 32 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 33 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 34 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 35 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 36 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 37 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 38 }; 39 40 static struct event_constraint intel_core_event_constraints[] __read_mostly = 41 { 42 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 43 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 44 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 45 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 46 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 47 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 48 EVENT_CONSTRAINT_END 49 }; 50 51 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 52 { 53 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 54 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 55 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 56 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 57 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 58 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 59 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 60 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 61 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 62 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 63 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 64 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 65 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 66 EVENT_CONSTRAINT_END 67 }; 68 69 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 70 { 71 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 72 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 73 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 74 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 75 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 76 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 77 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 78 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 79 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 80 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 81 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 82 EVENT_CONSTRAINT_END 83 }; 84 85 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 86 { 87 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 88 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 89 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 90 EVENT_EXTRA_END 91 }; 92 93 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 94 { 95 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 96 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 97 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 98 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 99 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 100 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 101 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 102 EVENT_CONSTRAINT_END 103 }; 104 105 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 106 { 107 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 108 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 109 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 110 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 111 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 112 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 113 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 114 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 116 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 117 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 118 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 119 120 /* 121 * When HT is off these events can only run on the bottom 4 counters 122 * When HT is on, they are impacted by the HT bug and require EXCL access 123 */ 124 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 125 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 128 129 EVENT_CONSTRAINT_END 130 }; 131 132 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 133 { 134 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 135 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 136 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 137 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 138 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 139 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 140 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 141 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 142 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 147 148 /* 149 * When HT is off these events can only run on the bottom 4 counters 150 * When HT is on, they are impacted by the HT bug and require EXCL access 151 */ 152 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 153 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 156 157 EVENT_CONSTRAINT_END 158 }; 159 160 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 161 { 162 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 163 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 164 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 165 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 166 EVENT_EXTRA_END 167 }; 168 169 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 170 { 171 EVENT_CONSTRAINT_END 172 }; 173 174 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 175 { 176 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 177 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 178 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 179 EVENT_CONSTRAINT_END 180 }; 181 182 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 183 { 184 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 185 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 186 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 187 EVENT_CONSTRAINT_END 188 }; 189 190 static struct event_constraint intel_skl_event_constraints[] = { 191 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 192 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 193 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 194 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 195 196 /* 197 * when HT is off, these can only run on the bottom 4 counters 198 */ 199 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 200 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 201 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 203 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 204 205 EVENT_CONSTRAINT_END 206 }; 207 208 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 209 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 210 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 211 EVENT_EXTRA_END 212 }; 213 214 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 215 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 216 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 217 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 218 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 219 EVENT_EXTRA_END 220 }; 221 222 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 223 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 224 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 225 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 226 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 227 EVENT_EXTRA_END 228 }; 229 230 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 231 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 232 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 233 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 234 /* 235 * Note the low 8 bits eventsel code is not a continuous field, containing 236 * some #GPing bits. These are masked out. 237 */ 238 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 239 EVENT_EXTRA_END 240 }; 241 242 static struct event_constraint intel_icl_event_constraints[] = { 243 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 244 INTEL_UEVENT_CONSTRAINT(0x1c0, 0), /* INST_RETIRED.PREC_DIST */ 245 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 246 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 247 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 248 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 249 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 250 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 251 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 252 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 253 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 254 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 255 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 256 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 257 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 258 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 259 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 260 EVENT_CONSTRAINT_END 261 }; 262 263 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 264 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0), 265 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1), 266 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 267 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 268 EVENT_EXTRA_END 269 }; 270 271 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 272 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 273 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 274 275 static struct attribute *nhm_mem_events_attrs[] = { 276 EVENT_PTR(mem_ld_nhm), 277 NULL, 278 }; 279 280 /* 281 * topdown events for Intel Core CPUs. 282 * 283 * The events are all in slots, which is a free slot in a 4 wide 284 * pipeline. Some events are already reported in slots, for cycle 285 * events we multiply by the pipeline width (4). 286 * 287 * With Hyper Threading on, topdown metrics are either summed or averaged 288 * between the threads of a core: (count_t0 + count_t1). 289 * 290 * For the average case the metric is always scaled to pipeline width, 291 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 292 */ 293 294 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 295 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 296 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 297 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 298 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 299 "event=0xe,umask=0x1"); /* uops_issued.any */ 300 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 301 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 302 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 303 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 304 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 305 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 306 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 307 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 308 "4", "2"); 309 310 static struct attribute *snb_events_attrs[] = { 311 EVENT_PTR(td_slots_issued), 312 EVENT_PTR(td_slots_retired), 313 EVENT_PTR(td_fetch_bubbles), 314 EVENT_PTR(td_total_slots), 315 EVENT_PTR(td_total_slots_scale), 316 EVENT_PTR(td_recovery_bubbles), 317 EVENT_PTR(td_recovery_bubbles_scale), 318 NULL, 319 }; 320 321 static struct attribute *snb_mem_events_attrs[] = { 322 EVENT_PTR(mem_ld_snb), 323 EVENT_PTR(mem_st_snb), 324 NULL, 325 }; 326 327 static struct event_constraint intel_hsw_event_constraints[] = { 328 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 329 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 330 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 331 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 332 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 333 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 334 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 335 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 336 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 337 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 338 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 339 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 340 341 /* 342 * When HT is off these events can only run on the bottom 4 counters 343 * When HT is on, they are impacted by the HT bug and require EXCL access 344 */ 345 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 346 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 347 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 348 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 349 350 EVENT_CONSTRAINT_END 351 }; 352 353 static struct event_constraint intel_bdw_event_constraints[] = { 354 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 355 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 356 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 357 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 358 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 359 /* 360 * when HT is off, these can only run on the bottom 4 counters 361 */ 362 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 363 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 364 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 365 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 366 EVENT_CONSTRAINT_END 367 }; 368 369 static u64 intel_pmu_event_map(int hw_event) 370 { 371 return intel_perfmon_event_map[hw_event]; 372 } 373 374 /* 375 * Notes on the events: 376 * - data reads do not include code reads (comparable to earlier tables) 377 * - data counts include speculative execution (except L1 write, dtlb, bpu) 378 * - remote node access includes remote memory, remote cache, remote mmio. 379 * - prefetches are not included in the counts. 380 * - icache miss does not include decoded icache 381 */ 382 383 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 384 #define SKL_DEMAND_RFO BIT_ULL(1) 385 #define SKL_ANY_RESPONSE BIT_ULL(16) 386 #define SKL_SUPPLIER_NONE BIT_ULL(17) 387 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 388 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 389 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 390 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 391 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 392 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 393 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 394 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 395 #define SKL_SPL_HIT BIT_ULL(30) 396 #define SKL_SNOOP_NONE BIT_ULL(31) 397 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 398 #define SKL_SNOOP_MISS BIT_ULL(33) 399 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 400 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 401 #define SKL_SNOOP_HITM BIT_ULL(36) 402 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 403 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 404 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 405 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 406 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 407 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 408 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 409 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 410 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 411 SKL_SNOOP_HITM|SKL_SPL_HIT) 412 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 413 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 414 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 415 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 416 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 417 418 static __initconst const u64 skl_hw_cache_event_ids 419 [PERF_COUNT_HW_CACHE_MAX] 420 [PERF_COUNT_HW_CACHE_OP_MAX] 421 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 422 { 423 [ C(L1D ) ] = { 424 [ C(OP_READ) ] = { 425 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 426 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 427 }, 428 [ C(OP_WRITE) ] = { 429 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 430 [ C(RESULT_MISS) ] = 0x0, 431 }, 432 [ C(OP_PREFETCH) ] = { 433 [ C(RESULT_ACCESS) ] = 0x0, 434 [ C(RESULT_MISS) ] = 0x0, 435 }, 436 }, 437 [ C(L1I ) ] = { 438 [ C(OP_READ) ] = { 439 [ C(RESULT_ACCESS) ] = 0x0, 440 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 441 }, 442 [ C(OP_WRITE) ] = { 443 [ C(RESULT_ACCESS) ] = -1, 444 [ C(RESULT_MISS) ] = -1, 445 }, 446 [ C(OP_PREFETCH) ] = { 447 [ C(RESULT_ACCESS) ] = 0x0, 448 [ C(RESULT_MISS) ] = 0x0, 449 }, 450 }, 451 [ C(LL ) ] = { 452 [ C(OP_READ) ] = { 453 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 454 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 455 }, 456 [ C(OP_WRITE) ] = { 457 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 458 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 459 }, 460 [ C(OP_PREFETCH) ] = { 461 [ C(RESULT_ACCESS) ] = 0x0, 462 [ C(RESULT_MISS) ] = 0x0, 463 }, 464 }, 465 [ C(DTLB) ] = { 466 [ C(OP_READ) ] = { 467 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 468 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 469 }, 470 [ C(OP_WRITE) ] = { 471 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 472 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 473 }, 474 [ C(OP_PREFETCH) ] = { 475 [ C(RESULT_ACCESS) ] = 0x0, 476 [ C(RESULT_MISS) ] = 0x0, 477 }, 478 }, 479 [ C(ITLB) ] = { 480 [ C(OP_READ) ] = { 481 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 482 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 483 }, 484 [ C(OP_WRITE) ] = { 485 [ C(RESULT_ACCESS) ] = -1, 486 [ C(RESULT_MISS) ] = -1, 487 }, 488 [ C(OP_PREFETCH) ] = { 489 [ C(RESULT_ACCESS) ] = -1, 490 [ C(RESULT_MISS) ] = -1, 491 }, 492 }, 493 [ C(BPU ) ] = { 494 [ C(OP_READ) ] = { 495 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 496 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 497 }, 498 [ C(OP_WRITE) ] = { 499 [ C(RESULT_ACCESS) ] = -1, 500 [ C(RESULT_MISS) ] = -1, 501 }, 502 [ C(OP_PREFETCH) ] = { 503 [ C(RESULT_ACCESS) ] = -1, 504 [ C(RESULT_MISS) ] = -1, 505 }, 506 }, 507 [ C(NODE) ] = { 508 [ C(OP_READ) ] = { 509 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 510 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 511 }, 512 [ C(OP_WRITE) ] = { 513 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 514 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 515 }, 516 [ C(OP_PREFETCH) ] = { 517 [ C(RESULT_ACCESS) ] = 0x0, 518 [ C(RESULT_MISS) ] = 0x0, 519 }, 520 }, 521 }; 522 523 static __initconst const u64 skl_hw_cache_extra_regs 524 [PERF_COUNT_HW_CACHE_MAX] 525 [PERF_COUNT_HW_CACHE_OP_MAX] 526 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 527 { 528 [ C(LL ) ] = { 529 [ C(OP_READ) ] = { 530 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 531 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 532 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 533 SKL_L3_MISS|SKL_ANY_SNOOP| 534 SKL_SUPPLIER_NONE, 535 }, 536 [ C(OP_WRITE) ] = { 537 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 538 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 539 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 540 SKL_L3_MISS|SKL_ANY_SNOOP| 541 SKL_SUPPLIER_NONE, 542 }, 543 [ C(OP_PREFETCH) ] = { 544 [ C(RESULT_ACCESS) ] = 0x0, 545 [ C(RESULT_MISS) ] = 0x0, 546 }, 547 }, 548 [ C(NODE) ] = { 549 [ C(OP_READ) ] = { 550 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 551 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 552 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 553 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 554 }, 555 [ C(OP_WRITE) ] = { 556 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 557 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 558 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 559 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 560 }, 561 [ C(OP_PREFETCH) ] = { 562 [ C(RESULT_ACCESS) ] = 0x0, 563 [ C(RESULT_MISS) ] = 0x0, 564 }, 565 }, 566 }; 567 568 #define SNB_DMND_DATA_RD (1ULL << 0) 569 #define SNB_DMND_RFO (1ULL << 1) 570 #define SNB_DMND_IFETCH (1ULL << 2) 571 #define SNB_DMND_WB (1ULL << 3) 572 #define SNB_PF_DATA_RD (1ULL << 4) 573 #define SNB_PF_RFO (1ULL << 5) 574 #define SNB_PF_IFETCH (1ULL << 6) 575 #define SNB_LLC_DATA_RD (1ULL << 7) 576 #define SNB_LLC_RFO (1ULL << 8) 577 #define SNB_LLC_IFETCH (1ULL << 9) 578 #define SNB_BUS_LOCKS (1ULL << 10) 579 #define SNB_STRM_ST (1ULL << 11) 580 #define SNB_OTHER (1ULL << 15) 581 #define SNB_RESP_ANY (1ULL << 16) 582 #define SNB_NO_SUPP (1ULL << 17) 583 #define SNB_LLC_HITM (1ULL << 18) 584 #define SNB_LLC_HITE (1ULL << 19) 585 #define SNB_LLC_HITS (1ULL << 20) 586 #define SNB_LLC_HITF (1ULL << 21) 587 #define SNB_LOCAL (1ULL << 22) 588 #define SNB_REMOTE (0xffULL << 23) 589 #define SNB_SNP_NONE (1ULL << 31) 590 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 591 #define SNB_SNP_MISS (1ULL << 33) 592 #define SNB_NO_FWD (1ULL << 34) 593 #define SNB_SNP_FWD (1ULL << 35) 594 #define SNB_HITM (1ULL << 36) 595 #define SNB_NON_DRAM (1ULL << 37) 596 597 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 598 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 599 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 600 601 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 602 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 603 SNB_HITM) 604 605 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 606 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 607 608 #define SNB_L3_ACCESS SNB_RESP_ANY 609 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 610 611 static __initconst const u64 snb_hw_cache_extra_regs 612 [PERF_COUNT_HW_CACHE_MAX] 613 [PERF_COUNT_HW_CACHE_OP_MAX] 614 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 615 { 616 [ C(LL ) ] = { 617 [ C(OP_READ) ] = { 618 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 619 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 620 }, 621 [ C(OP_WRITE) ] = { 622 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 623 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 624 }, 625 [ C(OP_PREFETCH) ] = { 626 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 627 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 628 }, 629 }, 630 [ C(NODE) ] = { 631 [ C(OP_READ) ] = { 632 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 633 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 634 }, 635 [ C(OP_WRITE) ] = { 636 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 637 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 638 }, 639 [ C(OP_PREFETCH) ] = { 640 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 641 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 642 }, 643 }, 644 }; 645 646 static __initconst const u64 snb_hw_cache_event_ids 647 [PERF_COUNT_HW_CACHE_MAX] 648 [PERF_COUNT_HW_CACHE_OP_MAX] 649 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 650 { 651 [ C(L1D) ] = { 652 [ C(OP_READ) ] = { 653 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 654 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 655 }, 656 [ C(OP_WRITE) ] = { 657 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 658 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 659 }, 660 [ C(OP_PREFETCH) ] = { 661 [ C(RESULT_ACCESS) ] = 0x0, 662 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 663 }, 664 }, 665 [ C(L1I ) ] = { 666 [ C(OP_READ) ] = { 667 [ C(RESULT_ACCESS) ] = 0x0, 668 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 669 }, 670 [ C(OP_WRITE) ] = { 671 [ C(RESULT_ACCESS) ] = -1, 672 [ C(RESULT_MISS) ] = -1, 673 }, 674 [ C(OP_PREFETCH) ] = { 675 [ C(RESULT_ACCESS) ] = 0x0, 676 [ C(RESULT_MISS) ] = 0x0, 677 }, 678 }, 679 [ C(LL ) ] = { 680 [ C(OP_READ) ] = { 681 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 682 [ C(RESULT_ACCESS) ] = 0x01b7, 683 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 684 [ C(RESULT_MISS) ] = 0x01b7, 685 }, 686 [ C(OP_WRITE) ] = { 687 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 688 [ C(RESULT_ACCESS) ] = 0x01b7, 689 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 690 [ C(RESULT_MISS) ] = 0x01b7, 691 }, 692 [ C(OP_PREFETCH) ] = { 693 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 694 [ C(RESULT_ACCESS) ] = 0x01b7, 695 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 696 [ C(RESULT_MISS) ] = 0x01b7, 697 }, 698 }, 699 [ C(DTLB) ] = { 700 [ C(OP_READ) ] = { 701 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 702 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 703 }, 704 [ C(OP_WRITE) ] = { 705 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 706 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 707 }, 708 [ C(OP_PREFETCH) ] = { 709 [ C(RESULT_ACCESS) ] = 0x0, 710 [ C(RESULT_MISS) ] = 0x0, 711 }, 712 }, 713 [ C(ITLB) ] = { 714 [ C(OP_READ) ] = { 715 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 716 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 717 }, 718 [ C(OP_WRITE) ] = { 719 [ C(RESULT_ACCESS) ] = -1, 720 [ C(RESULT_MISS) ] = -1, 721 }, 722 [ C(OP_PREFETCH) ] = { 723 [ C(RESULT_ACCESS) ] = -1, 724 [ C(RESULT_MISS) ] = -1, 725 }, 726 }, 727 [ C(BPU ) ] = { 728 [ C(OP_READ) ] = { 729 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 730 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 731 }, 732 [ C(OP_WRITE) ] = { 733 [ C(RESULT_ACCESS) ] = -1, 734 [ C(RESULT_MISS) ] = -1, 735 }, 736 [ C(OP_PREFETCH) ] = { 737 [ C(RESULT_ACCESS) ] = -1, 738 [ C(RESULT_MISS) ] = -1, 739 }, 740 }, 741 [ C(NODE) ] = { 742 [ C(OP_READ) ] = { 743 [ C(RESULT_ACCESS) ] = 0x01b7, 744 [ C(RESULT_MISS) ] = 0x01b7, 745 }, 746 [ C(OP_WRITE) ] = { 747 [ C(RESULT_ACCESS) ] = 0x01b7, 748 [ C(RESULT_MISS) ] = 0x01b7, 749 }, 750 [ C(OP_PREFETCH) ] = { 751 [ C(RESULT_ACCESS) ] = 0x01b7, 752 [ C(RESULT_MISS) ] = 0x01b7, 753 }, 754 }, 755 756 }; 757 758 /* 759 * Notes on the events: 760 * - data reads do not include code reads (comparable to earlier tables) 761 * - data counts include speculative execution (except L1 write, dtlb, bpu) 762 * - remote node access includes remote memory, remote cache, remote mmio. 763 * - prefetches are not included in the counts because they are not 764 * reliably counted. 765 */ 766 767 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 768 #define HSW_DEMAND_RFO BIT_ULL(1) 769 #define HSW_ANY_RESPONSE BIT_ULL(16) 770 #define HSW_SUPPLIER_NONE BIT_ULL(17) 771 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 772 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 773 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 774 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 775 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 776 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 777 HSW_L3_MISS_REMOTE_HOP2P) 778 #define HSW_SNOOP_NONE BIT_ULL(31) 779 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 780 #define HSW_SNOOP_MISS BIT_ULL(33) 781 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 782 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 783 #define HSW_SNOOP_HITM BIT_ULL(36) 784 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 785 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 786 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 787 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 788 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 789 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 790 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 791 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 792 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 793 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 794 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 795 796 #define BDW_L3_MISS_LOCAL BIT(26) 797 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 798 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 799 HSW_L3_MISS_REMOTE_HOP2P) 800 801 802 static __initconst const u64 hsw_hw_cache_event_ids 803 [PERF_COUNT_HW_CACHE_MAX] 804 [PERF_COUNT_HW_CACHE_OP_MAX] 805 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 806 { 807 [ C(L1D ) ] = { 808 [ C(OP_READ) ] = { 809 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 810 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 811 }, 812 [ C(OP_WRITE) ] = { 813 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 814 [ C(RESULT_MISS) ] = 0x0, 815 }, 816 [ C(OP_PREFETCH) ] = { 817 [ C(RESULT_ACCESS) ] = 0x0, 818 [ C(RESULT_MISS) ] = 0x0, 819 }, 820 }, 821 [ C(L1I ) ] = { 822 [ C(OP_READ) ] = { 823 [ C(RESULT_ACCESS) ] = 0x0, 824 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 825 }, 826 [ C(OP_WRITE) ] = { 827 [ C(RESULT_ACCESS) ] = -1, 828 [ C(RESULT_MISS) ] = -1, 829 }, 830 [ C(OP_PREFETCH) ] = { 831 [ C(RESULT_ACCESS) ] = 0x0, 832 [ C(RESULT_MISS) ] = 0x0, 833 }, 834 }, 835 [ C(LL ) ] = { 836 [ C(OP_READ) ] = { 837 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 838 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 839 }, 840 [ C(OP_WRITE) ] = { 841 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 842 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 843 }, 844 [ C(OP_PREFETCH) ] = { 845 [ C(RESULT_ACCESS) ] = 0x0, 846 [ C(RESULT_MISS) ] = 0x0, 847 }, 848 }, 849 [ C(DTLB) ] = { 850 [ C(OP_READ) ] = { 851 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 852 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 853 }, 854 [ C(OP_WRITE) ] = { 855 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 856 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 857 }, 858 [ C(OP_PREFETCH) ] = { 859 [ C(RESULT_ACCESS) ] = 0x0, 860 [ C(RESULT_MISS) ] = 0x0, 861 }, 862 }, 863 [ C(ITLB) ] = { 864 [ C(OP_READ) ] = { 865 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 866 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 867 }, 868 [ C(OP_WRITE) ] = { 869 [ C(RESULT_ACCESS) ] = -1, 870 [ C(RESULT_MISS) ] = -1, 871 }, 872 [ C(OP_PREFETCH) ] = { 873 [ C(RESULT_ACCESS) ] = -1, 874 [ C(RESULT_MISS) ] = -1, 875 }, 876 }, 877 [ C(BPU ) ] = { 878 [ C(OP_READ) ] = { 879 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 880 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 881 }, 882 [ C(OP_WRITE) ] = { 883 [ C(RESULT_ACCESS) ] = -1, 884 [ C(RESULT_MISS) ] = -1, 885 }, 886 [ C(OP_PREFETCH) ] = { 887 [ C(RESULT_ACCESS) ] = -1, 888 [ C(RESULT_MISS) ] = -1, 889 }, 890 }, 891 [ C(NODE) ] = { 892 [ C(OP_READ) ] = { 893 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 894 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 895 }, 896 [ C(OP_WRITE) ] = { 897 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 898 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 899 }, 900 [ C(OP_PREFETCH) ] = { 901 [ C(RESULT_ACCESS) ] = 0x0, 902 [ C(RESULT_MISS) ] = 0x0, 903 }, 904 }, 905 }; 906 907 static __initconst const u64 hsw_hw_cache_extra_regs 908 [PERF_COUNT_HW_CACHE_MAX] 909 [PERF_COUNT_HW_CACHE_OP_MAX] 910 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 911 { 912 [ C(LL ) ] = { 913 [ C(OP_READ) ] = { 914 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 915 HSW_LLC_ACCESS, 916 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 917 HSW_L3_MISS|HSW_ANY_SNOOP, 918 }, 919 [ C(OP_WRITE) ] = { 920 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 921 HSW_LLC_ACCESS, 922 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 923 HSW_L3_MISS|HSW_ANY_SNOOP, 924 }, 925 [ C(OP_PREFETCH) ] = { 926 [ C(RESULT_ACCESS) ] = 0x0, 927 [ C(RESULT_MISS) ] = 0x0, 928 }, 929 }, 930 [ C(NODE) ] = { 931 [ C(OP_READ) ] = { 932 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 933 HSW_L3_MISS_LOCAL_DRAM| 934 HSW_SNOOP_DRAM, 935 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 936 HSW_L3_MISS_REMOTE| 937 HSW_SNOOP_DRAM, 938 }, 939 [ C(OP_WRITE) ] = { 940 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 941 HSW_L3_MISS_LOCAL_DRAM| 942 HSW_SNOOP_DRAM, 943 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 944 HSW_L3_MISS_REMOTE| 945 HSW_SNOOP_DRAM, 946 }, 947 [ C(OP_PREFETCH) ] = { 948 [ C(RESULT_ACCESS) ] = 0x0, 949 [ C(RESULT_MISS) ] = 0x0, 950 }, 951 }, 952 }; 953 954 static __initconst const u64 westmere_hw_cache_event_ids 955 [PERF_COUNT_HW_CACHE_MAX] 956 [PERF_COUNT_HW_CACHE_OP_MAX] 957 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 958 { 959 [ C(L1D) ] = { 960 [ C(OP_READ) ] = { 961 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 962 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 963 }, 964 [ C(OP_WRITE) ] = { 965 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 966 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 967 }, 968 [ C(OP_PREFETCH) ] = { 969 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 970 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 971 }, 972 }, 973 [ C(L1I ) ] = { 974 [ C(OP_READ) ] = { 975 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 976 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 977 }, 978 [ C(OP_WRITE) ] = { 979 [ C(RESULT_ACCESS) ] = -1, 980 [ C(RESULT_MISS) ] = -1, 981 }, 982 [ C(OP_PREFETCH) ] = { 983 [ C(RESULT_ACCESS) ] = 0x0, 984 [ C(RESULT_MISS) ] = 0x0, 985 }, 986 }, 987 [ C(LL ) ] = { 988 [ C(OP_READ) ] = { 989 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 990 [ C(RESULT_ACCESS) ] = 0x01b7, 991 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 992 [ C(RESULT_MISS) ] = 0x01b7, 993 }, 994 /* 995 * Use RFO, not WRITEBACK, because a write miss would typically occur 996 * on RFO. 997 */ 998 [ C(OP_WRITE) ] = { 999 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1000 [ C(RESULT_ACCESS) ] = 0x01b7, 1001 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1002 [ C(RESULT_MISS) ] = 0x01b7, 1003 }, 1004 [ C(OP_PREFETCH) ] = { 1005 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1006 [ C(RESULT_ACCESS) ] = 0x01b7, 1007 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1008 [ C(RESULT_MISS) ] = 0x01b7, 1009 }, 1010 }, 1011 [ C(DTLB) ] = { 1012 [ C(OP_READ) ] = { 1013 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1014 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1015 }, 1016 [ C(OP_WRITE) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1018 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1019 }, 1020 [ C(OP_PREFETCH) ] = { 1021 [ C(RESULT_ACCESS) ] = 0x0, 1022 [ C(RESULT_MISS) ] = 0x0, 1023 }, 1024 }, 1025 [ C(ITLB) ] = { 1026 [ C(OP_READ) ] = { 1027 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1028 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1029 }, 1030 [ C(OP_WRITE) ] = { 1031 [ C(RESULT_ACCESS) ] = -1, 1032 [ C(RESULT_MISS) ] = -1, 1033 }, 1034 [ C(OP_PREFETCH) ] = { 1035 [ C(RESULT_ACCESS) ] = -1, 1036 [ C(RESULT_MISS) ] = -1, 1037 }, 1038 }, 1039 [ C(BPU ) ] = { 1040 [ C(OP_READ) ] = { 1041 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1042 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1043 }, 1044 [ C(OP_WRITE) ] = { 1045 [ C(RESULT_ACCESS) ] = -1, 1046 [ C(RESULT_MISS) ] = -1, 1047 }, 1048 [ C(OP_PREFETCH) ] = { 1049 [ C(RESULT_ACCESS) ] = -1, 1050 [ C(RESULT_MISS) ] = -1, 1051 }, 1052 }, 1053 [ C(NODE) ] = { 1054 [ C(OP_READ) ] = { 1055 [ C(RESULT_ACCESS) ] = 0x01b7, 1056 [ C(RESULT_MISS) ] = 0x01b7, 1057 }, 1058 [ C(OP_WRITE) ] = { 1059 [ C(RESULT_ACCESS) ] = 0x01b7, 1060 [ C(RESULT_MISS) ] = 0x01b7, 1061 }, 1062 [ C(OP_PREFETCH) ] = { 1063 [ C(RESULT_ACCESS) ] = 0x01b7, 1064 [ C(RESULT_MISS) ] = 0x01b7, 1065 }, 1066 }, 1067 }; 1068 1069 /* 1070 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1071 * See IA32 SDM Vol 3B 30.6.1.3 1072 */ 1073 1074 #define NHM_DMND_DATA_RD (1 << 0) 1075 #define NHM_DMND_RFO (1 << 1) 1076 #define NHM_DMND_IFETCH (1 << 2) 1077 #define NHM_DMND_WB (1 << 3) 1078 #define NHM_PF_DATA_RD (1 << 4) 1079 #define NHM_PF_DATA_RFO (1 << 5) 1080 #define NHM_PF_IFETCH (1 << 6) 1081 #define NHM_OFFCORE_OTHER (1 << 7) 1082 #define NHM_UNCORE_HIT (1 << 8) 1083 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1084 #define NHM_OTHER_CORE_HITM (1 << 10) 1085 /* reserved */ 1086 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1087 #define NHM_REMOTE_DRAM (1 << 13) 1088 #define NHM_LOCAL_DRAM (1 << 14) 1089 #define NHM_NON_DRAM (1 << 15) 1090 1091 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1092 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1093 1094 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1095 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1096 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1097 1098 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1099 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1100 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1101 1102 static __initconst const u64 nehalem_hw_cache_extra_regs 1103 [PERF_COUNT_HW_CACHE_MAX] 1104 [PERF_COUNT_HW_CACHE_OP_MAX] 1105 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1106 { 1107 [ C(LL ) ] = { 1108 [ C(OP_READ) ] = { 1109 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1110 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1111 }, 1112 [ C(OP_WRITE) ] = { 1113 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1114 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1115 }, 1116 [ C(OP_PREFETCH) ] = { 1117 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1118 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1119 }, 1120 }, 1121 [ C(NODE) ] = { 1122 [ C(OP_READ) ] = { 1123 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1124 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1125 }, 1126 [ C(OP_WRITE) ] = { 1127 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1128 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1129 }, 1130 [ C(OP_PREFETCH) ] = { 1131 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1132 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1133 }, 1134 }, 1135 }; 1136 1137 static __initconst const u64 nehalem_hw_cache_event_ids 1138 [PERF_COUNT_HW_CACHE_MAX] 1139 [PERF_COUNT_HW_CACHE_OP_MAX] 1140 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1141 { 1142 [ C(L1D) ] = { 1143 [ C(OP_READ) ] = { 1144 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1145 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1146 }, 1147 [ C(OP_WRITE) ] = { 1148 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1149 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1150 }, 1151 [ C(OP_PREFETCH) ] = { 1152 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1153 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1154 }, 1155 }, 1156 [ C(L1I ) ] = { 1157 [ C(OP_READ) ] = { 1158 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1159 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1160 }, 1161 [ C(OP_WRITE) ] = { 1162 [ C(RESULT_ACCESS) ] = -1, 1163 [ C(RESULT_MISS) ] = -1, 1164 }, 1165 [ C(OP_PREFETCH) ] = { 1166 [ C(RESULT_ACCESS) ] = 0x0, 1167 [ C(RESULT_MISS) ] = 0x0, 1168 }, 1169 }, 1170 [ C(LL ) ] = { 1171 [ C(OP_READ) ] = { 1172 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1173 [ C(RESULT_ACCESS) ] = 0x01b7, 1174 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1175 [ C(RESULT_MISS) ] = 0x01b7, 1176 }, 1177 /* 1178 * Use RFO, not WRITEBACK, because a write miss would typically occur 1179 * on RFO. 1180 */ 1181 [ C(OP_WRITE) ] = { 1182 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1183 [ C(RESULT_ACCESS) ] = 0x01b7, 1184 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1185 [ C(RESULT_MISS) ] = 0x01b7, 1186 }, 1187 [ C(OP_PREFETCH) ] = { 1188 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1189 [ C(RESULT_ACCESS) ] = 0x01b7, 1190 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1191 [ C(RESULT_MISS) ] = 0x01b7, 1192 }, 1193 }, 1194 [ C(DTLB) ] = { 1195 [ C(OP_READ) ] = { 1196 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1197 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1198 }, 1199 [ C(OP_WRITE) ] = { 1200 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1201 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1202 }, 1203 [ C(OP_PREFETCH) ] = { 1204 [ C(RESULT_ACCESS) ] = 0x0, 1205 [ C(RESULT_MISS) ] = 0x0, 1206 }, 1207 }, 1208 [ C(ITLB) ] = { 1209 [ C(OP_READ) ] = { 1210 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1211 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1212 }, 1213 [ C(OP_WRITE) ] = { 1214 [ C(RESULT_ACCESS) ] = -1, 1215 [ C(RESULT_MISS) ] = -1, 1216 }, 1217 [ C(OP_PREFETCH) ] = { 1218 [ C(RESULT_ACCESS) ] = -1, 1219 [ C(RESULT_MISS) ] = -1, 1220 }, 1221 }, 1222 [ C(BPU ) ] = { 1223 [ C(OP_READ) ] = { 1224 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1225 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1226 }, 1227 [ C(OP_WRITE) ] = { 1228 [ C(RESULT_ACCESS) ] = -1, 1229 [ C(RESULT_MISS) ] = -1, 1230 }, 1231 [ C(OP_PREFETCH) ] = { 1232 [ C(RESULT_ACCESS) ] = -1, 1233 [ C(RESULT_MISS) ] = -1, 1234 }, 1235 }, 1236 [ C(NODE) ] = { 1237 [ C(OP_READ) ] = { 1238 [ C(RESULT_ACCESS) ] = 0x01b7, 1239 [ C(RESULT_MISS) ] = 0x01b7, 1240 }, 1241 [ C(OP_WRITE) ] = { 1242 [ C(RESULT_ACCESS) ] = 0x01b7, 1243 [ C(RESULT_MISS) ] = 0x01b7, 1244 }, 1245 [ C(OP_PREFETCH) ] = { 1246 [ C(RESULT_ACCESS) ] = 0x01b7, 1247 [ C(RESULT_MISS) ] = 0x01b7, 1248 }, 1249 }, 1250 }; 1251 1252 static __initconst const u64 core2_hw_cache_event_ids 1253 [PERF_COUNT_HW_CACHE_MAX] 1254 [PERF_COUNT_HW_CACHE_OP_MAX] 1255 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1256 { 1257 [ C(L1D) ] = { 1258 [ C(OP_READ) ] = { 1259 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1260 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1261 }, 1262 [ C(OP_WRITE) ] = { 1263 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1264 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1265 }, 1266 [ C(OP_PREFETCH) ] = { 1267 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1268 [ C(RESULT_MISS) ] = 0, 1269 }, 1270 }, 1271 [ C(L1I ) ] = { 1272 [ C(OP_READ) ] = { 1273 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1274 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1275 }, 1276 [ C(OP_WRITE) ] = { 1277 [ C(RESULT_ACCESS) ] = -1, 1278 [ C(RESULT_MISS) ] = -1, 1279 }, 1280 [ C(OP_PREFETCH) ] = { 1281 [ C(RESULT_ACCESS) ] = 0, 1282 [ C(RESULT_MISS) ] = 0, 1283 }, 1284 }, 1285 [ C(LL ) ] = { 1286 [ C(OP_READ) ] = { 1287 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1288 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1289 }, 1290 [ C(OP_WRITE) ] = { 1291 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1292 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1293 }, 1294 [ C(OP_PREFETCH) ] = { 1295 [ C(RESULT_ACCESS) ] = 0, 1296 [ C(RESULT_MISS) ] = 0, 1297 }, 1298 }, 1299 [ C(DTLB) ] = { 1300 [ C(OP_READ) ] = { 1301 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1302 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1303 }, 1304 [ C(OP_WRITE) ] = { 1305 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1306 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1307 }, 1308 [ C(OP_PREFETCH) ] = { 1309 [ C(RESULT_ACCESS) ] = 0, 1310 [ C(RESULT_MISS) ] = 0, 1311 }, 1312 }, 1313 [ C(ITLB) ] = { 1314 [ C(OP_READ) ] = { 1315 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1316 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1317 }, 1318 [ C(OP_WRITE) ] = { 1319 [ C(RESULT_ACCESS) ] = -1, 1320 [ C(RESULT_MISS) ] = -1, 1321 }, 1322 [ C(OP_PREFETCH) ] = { 1323 [ C(RESULT_ACCESS) ] = -1, 1324 [ C(RESULT_MISS) ] = -1, 1325 }, 1326 }, 1327 [ C(BPU ) ] = { 1328 [ C(OP_READ) ] = { 1329 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1330 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1331 }, 1332 [ C(OP_WRITE) ] = { 1333 [ C(RESULT_ACCESS) ] = -1, 1334 [ C(RESULT_MISS) ] = -1, 1335 }, 1336 [ C(OP_PREFETCH) ] = { 1337 [ C(RESULT_ACCESS) ] = -1, 1338 [ C(RESULT_MISS) ] = -1, 1339 }, 1340 }, 1341 }; 1342 1343 static __initconst const u64 atom_hw_cache_event_ids 1344 [PERF_COUNT_HW_CACHE_MAX] 1345 [PERF_COUNT_HW_CACHE_OP_MAX] 1346 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1347 { 1348 [ C(L1D) ] = { 1349 [ C(OP_READ) ] = { 1350 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1351 [ C(RESULT_MISS) ] = 0, 1352 }, 1353 [ C(OP_WRITE) ] = { 1354 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1355 [ C(RESULT_MISS) ] = 0, 1356 }, 1357 [ C(OP_PREFETCH) ] = { 1358 [ C(RESULT_ACCESS) ] = 0x0, 1359 [ C(RESULT_MISS) ] = 0, 1360 }, 1361 }, 1362 [ C(L1I ) ] = { 1363 [ C(OP_READ) ] = { 1364 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1365 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1366 }, 1367 [ C(OP_WRITE) ] = { 1368 [ C(RESULT_ACCESS) ] = -1, 1369 [ C(RESULT_MISS) ] = -1, 1370 }, 1371 [ C(OP_PREFETCH) ] = { 1372 [ C(RESULT_ACCESS) ] = 0, 1373 [ C(RESULT_MISS) ] = 0, 1374 }, 1375 }, 1376 [ C(LL ) ] = { 1377 [ C(OP_READ) ] = { 1378 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1379 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1380 }, 1381 [ C(OP_WRITE) ] = { 1382 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1383 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1384 }, 1385 [ C(OP_PREFETCH) ] = { 1386 [ C(RESULT_ACCESS) ] = 0, 1387 [ C(RESULT_MISS) ] = 0, 1388 }, 1389 }, 1390 [ C(DTLB) ] = { 1391 [ C(OP_READ) ] = { 1392 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1393 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1394 }, 1395 [ C(OP_WRITE) ] = { 1396 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1397 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1398 }, 1399 [ C(OP_PREFETCH) ] = { 1400 [ C(RESULT_ACCESS) ] = 0, 1401 [ C(RESULT_MISS) ] = 0, 1402 }, 1403 }, 1404 [ C(ITLB) ] = { 1405 [ C(OP_READ) ] = { 1406 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1407 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1408 }, 1409 [ C(OP_WRITE) ] = { 1410 [ C(RESULT_ACCESS) ] = -1, 1411 [ C(RESULT_MISS) ] = -1, 1412 }, 1413 [ C(OP_PREFETCH) ] = { 1414 [ C(RESULT_ACCESS) ] = -1, 1415 [ C(RESULT_MISS) ] = -1, 1416 }, 1417 }, 1418 [ C(BPU ) ] = { 1419 [ C(OP_READ) ] = { 1420 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1421 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1422 }, 1423 [ C(OP_WRITE) ] = { 1424 [ C(RESULT_ACCESS) ] = -1, 1425 [ C(RESULT_MISS) ] = -1, 1426 }, 1427 [ C(OP_PREFETCH) ] = { 1428 [ C(RESULT_ACCESS) ] = -1, 1429 [ C(RESULT_MISS) ] = -1, 1430 }, 1431 }, 1432 }; 1433 1434 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1435 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1436 /* no_alloc_cycles.not_delivered */ 1437 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1438 "event=0xca,umask=0x50"); 1439 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1440 /* uops_retired.all */ 1441 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1442 "event=0xc2,umask=0x10"); 1443 /* uops_retired.all */ 1444 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1445 "event=0xc2,umask=0x10"); 1446 1447 static struct attribute *slm_events_attrs[] = { 1448 EVENT_PTR(td_total_slots_slm), 1449 EVENT_PTR(td_total_slots_scale_slm), 1450 EVENT_PTR(td_fetch_bubbles_slm), 1451 EVENT_PTR(td_fetch_bubbles_scale_slm), 1452 EVENT_PTR(td_slots_issued_slm), 1453 EVENT_PTR(td_slots_retired_slm), 1454 NULL 1455 }; 1456 1457 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1458 { 1459 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1460 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1461 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1462 EVENT_EXTRA_END 1463 }; 1464 1465 #define SLM_DMND_READ SNB_DMND_DATA_RD 1466 #define SLM_DMND_WRITE SNB_DMND_RFO 1467 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1468 1469 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1470 #define SLM_LLC_ACCESS SNB_RESP_ANY 1471 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1472 1473 static __initconst const u64 slm_hw_cache_extra_regs 1474 [PERF_COUNT_HW_CACHE_MAX] 1475 [PERF_COUNT_HW_CACHE_OP_MAX] 1476 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1477 { 1478 [ C(LL ) ] = { 1479 [ C(OP_READ) ] = { 1480 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1481 [ C(RESULT_MISS) ] = 0, 1482 }, 1483 [ C(OP_WRITE) ] = { 1484 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1485 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1486 }, 1487 [ C(OP_PREFETCH) ] = { 1488 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1489 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1490 }, 1491 }, 1492 }; 1493 1494 static __initconst const u64 slm_hw_cache_event_ids 1495 [PERF_COUNT_HW_CACHE_MAX] 1496 [PERF_COUNT_HW_CACHE_OP_MAX] 1497 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1498 { 1499 [ C(L1D) ] = { 1500 [ C(OP_READ) ] = { 1501 [ C(RESULT_ACCESS) ] = 0, 1502 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1503 }, 1504 [ C(OP_WRITE) ] = { 1505 [ C(RESULT_ACCESS) ] = 0, 1506 [ C(RESULT_MISS) ] = 0, 1507 }, 1508 [ C(OP_PREFETCH) ] = { 1509 [ C(RESULT_ACCESS) ] = 0, 1510 [ C(RESULT_MISS) ] = 0, 1511 }, 1512 }, 1513 [ C(L1I ) ] = { 1514 [ C(OP_READ) ] = { 1515 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1516 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1517 }, 1518 [ C(OP_WRITE) ] = { 1519 [ C(RESULT_ACCESS) ] = -1, 1520 [ C(RESULT_MISS) ] = -1, 1521 }, 1522 [ C(OP_PREFETCH) ] = { 1523 [ C(RESULT_ACCESS) ] = 0, 1524 [ C(RESULT_MISS) ] = 0, 1525 }, 1526 }, 1527 [ C(LL ) ] = { 1528 [ C(OP_READ) ] = { 1529 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1530 [ C(RESULT_ACCESS) ] = 0x01b7, 1531 [ C(RESULT_MISS) ] = 0, 1532 }, 1533 [ C(OP_WRITE) ] = { 1534 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1535 [ C(RESULT_ACCESS) ] = 0x01b7, 1536 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1537 [ C(RESULT_MISS) ] = 0x01b7, 1538 }, 1539 [ C(OP_PREFETCH) ] = { 1540 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1541 [ C(RESULT_ACCESS) ] = 0x01b7, 1542 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1543 [ C(RESULT_MISS) ] = 0x01b7, 1544 }, 1545 }, 1546 [ C(DTLB) ] = { 1547 [ C(OP_READ) ] = { 1548 [ C(RESULT_ACCESS) ] = 0, 1549 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1550 }, 1551 [ C(OP_WRITE) ] = { 1552 [ C(RESULT_ACCESS) ] = 0, 1553 [ C(RESULT_MISS) ] = 0, 1554 }, 1555 [ C(OP_PREFETCH) ] = { 1556 [ C(RESULT_ACCESS) ] = 0, 1557 [ C(RESULT_MISS) ] = 0, 1558 }, 1559 }, 1560 [ C(ITLB) ] = { 1561 [ C(OP_READ) ] = { 1562 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1563 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1564 }, 1565 [ C(OP_WRITE) ] = { 1566 [ C(RESULT_ACCESS) ] = -1, 1567 [ C(RESULT_MISS) ] = -1, 1568 }, 1569 [ C(OP_PREFETCH) ] = { 1570 [ C(RESULT_ACCESS) ] = -1, 1571 [ C(RESULT_MISS) ] = -1, 1572 }, 1573 }, 1574 [ C(BPU ) ] = { 1575 [ C(OP_READ) ] = { 1576 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1577 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1578 }, 1579 [ C(OP_WRITE) ] = { 1580 [ C(RESULT_ACCESS) ] = -1, 1581 [ C(RESULT_MISS) ] = -1, 1582 }, 1583 [ C(OP_PREFETCH) ] = { 1584 [ C(RESULT_ACCESS) ] = -1, 1585 [ C(RESULT_MISS) ] = -1, 1586 }, 1587 }, 1588 }; 1589 1590 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1591 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1592 /* UOPS_NOT_DELIVERED.ANY */ 1593 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1594 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1595 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1596 /* UOPS_RETIRED.ANY */ 1597 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1598 /* UOPS_ISSUED.ANY */ 1599 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1600 1601 static struct attribute *glm_events_attrs[] = { 1602 EVENT_PTR(td_total_slots_glm), 1603 EVENT_PTR(td_total_slots_scale_glm), 1604 EVENT_PTR(td_fetch_bubbles_glm), 1605 EVENT_PTR(td_recovery_bubbles_glm), 1606 EVENT_PTR(td_slots_issued_glm), 1607 EVENT_PTR(td_slots_retired_glm), 1608 NULL 1609 }; 1610 1611 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1612 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1613 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1614 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1615 EVENT_EXTRA_END 1616 }; 1617 1618 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1619 #define GLM_DEMAND_RFO BIT_ULL(1) 1620 #define GLM_ANY_RESPONSE BIT_ULL(16) 1621 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1622 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1623 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1624 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1625 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1626 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1627 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1628 1629 static __initconst const u64 glm_hw_cache_event_ids 1630 [PERF_COUNT_HW_CACHE_MAX] 1631 [PERF_COUNT_HW_CACHE_OP_MAX] 1632 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1633 [C(L1D)] = { 1634 [C(OP_READ)] = { 1635 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1636 [C(RESULT_MISS)] = 0x0, 1637 }, 1638 [C(OP_WRITE)] = { 1639 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1640 [C(RESULT_MISS)] = 0x0, 1641 }, 1642 [C(OP_PREFETCH)] = { 1643 [C(RESULT_ACCESS)] = 0x0, 1644 [C(RESULT_MISS)] = 0x0, 1645 }, 1646 }, 1647 [C(L1I)] = { 1648 [C(OP_READ)] = { 1649 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1650 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1651 }, 1652 [C(OP_WRITE)] = { 1653 [C(RESULT_ACCESS)] = -1, 1654 [C(RESULT_MISS)] = -1, 1655 }, 1656 [C(OP_PREFETCH)] = { 1657 [C(RESULT_ACCESS)] = 0x0, 1658 [C(RESULT_MISS)] = 0x0, 1659 }, 1660 }, 1661 [C(LL)] = { 1662 [C(OP_READ)] = { 1663 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1664 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1665 }, 1666 [C(OP_WRITE)] = { 1667 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1668 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1669 }, 1670 [C(OP_PREFETCH)] = { 1671 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1672 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1673 }, 1674 }, 1675 [C(DTLB)] = { 1676 [C(OP_READ)] = { 1677 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1678 [C(RESULT_MISS)] = 0x0, 1679 }, 1680 [C(OP_WRITE)] = { 1681 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1682 [C(RESULT_MISS)] = 0x0, 1683 }, 1684 [C(OP_PREFETCH)] = { 1685 [C(RESULT_ACCESS)] = 0x0, 1686 [C(RESULT_MISS)] = 0x0, 1687 }, 1688 }, 1689 [C(ITLB)] = { 1690 [C(OP_READ)] = { 1691 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1692 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1693 }, 1694 [C(OP_WRITE)] = { 1695 [C(RESULT_ACCESS)] = -1, 1696 [C(RESULT_MISS)] = -1, 1697 }, 1698 [C(OP_PREFETCH)] = { 1699 [C(RESULT_ACCESS)] = -1, 1700 [C(RESULT_MISS)] = -1, 1701 }, 1702 }, 1703 [C(BPU)] = { 1704 [C(OP_READ)] = { 1705 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1706 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1707 }, 1708 [C(OP_WRITE)] = { 1709 [C(RESULT_ACCESS)] = -1, 1710 [C(RESULT_MISS)] = -1, 1711 }, 1712 [C(OP_PREFETCH)] = { 1713 [C(RESULT_ACCESS)] = -1, 1714 [C(RESULT_MISS)] = -1, 1715 }, 1716 }, 1717 }; 1718 1719 static __initconst const u64 glm_hw_cache_extra_regs 1720 [PERF_COUNT_HW_CACHE_MAX] 1721 [PERF_COUNT_HW_CACHE_OP_MAX] 1722 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1723 [C(LL)] = { 1724 [C(OP_READ)] = { 1725 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1726 GLM_LLC_ACCESS, 1727 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1728 GLM_LLC_MISS, 1729 }, 1730 [C(OP_WRITE)] = { 1731 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1732 GLM_LLC_ACCESS, 1733 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1734 GLM_LLC_MISS, 1735 }, 1736 [C(OP_PREFETCH)] = { 1737 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1738 GLM_LLC_ACCESS, 1739 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1740 GLM_LLC_MISS, 1741 }, 1742 }, 1743 }; 1744 1745 static __initconst const u64 glp_hw_cache_event_ids 1746 [PERF_COUNT_HW_CACHE_MAX] 1747 [PERF_COUNT_HW_CACHE_OP_MAX] 1748 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1749 [C(L1D)] = { 1750 [C(OP_READ)] = { 1751 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1752 [C(RESULT_MISS)] = 0x0, 1753 }, 1754 [C(OP_WRITE)] = { 1755 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1756 [C(RESULT_MISS)] = 0x0, 1757 }, 1758 [C(OP_PREFETCH)] = { 1759 [C(RESULT_ACCESS)] = 0x0, 1760 [C(RESULT_MISS)] = 0x0, 1761 }, 1762 }, 1763 [C(L1I)] = { 1764 [C(OP_READ)] = { 1765 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1766 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1767 }, 1768 [C(OP_WRITE)] = { 1769 [C(RESULT_ACCESS)] = -1, 1770 [C(RESULT_MISS)] = -1, 1771 }, 1772 [C(OP_PREFETCH)] = { 1773 [C(RESULT_ACCESS)] = 0x0, 1774 [C(RESULT_MISS)] = 0x0, 1775 }, 1776 }, 1777 [C(LL)] = { 1778 [C(OP_READ)] = { 1779 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1780 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1781 }, 1782 [C(OP_WRITE)] = { 1783 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1784 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1785 }, 1786 [C(OP_PREFETCH)] = { 1787 [C(RESULT_ACCESS)] = 0x0, 1788 [C(RESULT_MISS)] = 0x0, 1789 }, 1790 }, 1791 [C(DTLB)] = { 1792 [C(OP_READ)] = { 1793 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1794 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1795 }, 1796 [C(OP_WRITE)] = { 1797 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1798 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1799 }, 1800 [C(OP_PREFETCH)] = { 1801 [C(RESULT_ACCESS)] = 0x0, 1802 [C(RESULT_MISS)] = 0x0, 1803 }, 1804 }, 1805 [C(ITLB)] = { 1806 [C(OP_READ)] = { 1807 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1808 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1809 }, 1810 [C(OP_WRITE)] = { 1811 [C(RESULT_ACCESS)] = -1, 1812 [C(RESULT_MISS)] = -1, 1813 }, 1814 [C(OP_PREFETCH)] = { 1815 [C(RESULT_ACCESS)] = -1, 1816 [C(RESULT_MISS)] = -1, 1817 }, 1818 }, 1819 [C(BPU)] = { 1820 [C(OP_READ)] = { 1821 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1822 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1823 }, 1824 [C(OP_WRITE)] = { 1825 [C(RESULT_ACCESS)] = -1, 1826 [C(RESULT_MISS)] = -1, 1827 }, 1828 [C(OP_PREFETCH)] = { 1829 [C(RESULT_ACCESS)] = -1, 1830 [C(RESULT_MISS)] = -1, 1831 }, 1832 }, 1833 }; 1834 1835 static __initconst const u64 glp_hw_cache_extra_regs 1836 [PERF_COUNT_HW_CACHE_MAX] 1837 [PERF_COUNT_HW_CACHE_OP_MAX] 1838 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1839 [C(LL)] = { 1840 [C(OP_READ)] = { 1841 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1842 GLM_LLC_ACCESS, 1843 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1844 GLM_LLC_MISS, 1845 }, 1846 [C(OP_WRITE)] = { 1847 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1848 GLM_LLC_ACCESS, 1849 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1850 GLM_LLC_MISS, 1851 }, 1852 [C(OP_PREFETCH)] = { 1853 [C(RESULT_ACCESS)] = 0x0, 1854 [C(RESULT_MISS)] = 0x0, 1855 }, 1856 }, 1857 }; 1858 1859 #define TNT_LOCAL_DRAM BIT_ULL(26) 1860 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 1861 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 1862 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 1863 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 1864 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 1865 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 1866 1867 static __initconst const u64 tnt_hw_cache_extra_regs 1868 [PERF_COUNT_HW_CACHE_MAX] 1869 [PERF_COUNT_HW_CACHE_OP_MAX] 1870 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1871 [C(LL)] = { 1872 [C(OP_READ)] = { 1873 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 1874 TNT_LLC_ACCESS, 1875 [C(RESULT_MISS)] = TNT_DEMAND_READ| 1876 TNT_LLC_MISS, 1877 }, 1878 [C(OP_WRITE)] = { 1879 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 1880 TNT_LLC_ACCESS, 1881 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 1882 TNT_LLC_MISS, 1883 }, 1884 [C(OP_PREFETCH)] = { 1885 [C(RESULT_ACCESS)] = 0x0, 1886 [C(RESULT_MISS)] = 0x0, 1887 }, 1888 }, 1889 }; 1890 1891 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 1892 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1893 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0), 1894 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1), 1895 EVENT_EXTRA_END 1896 }; 1897 1898 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1899 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1900 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1901 #define KNL_MCDRAM_FAR BIT_ULL(22) 1902 #define KNL_DDR_LOCAL BIT_ULL(23) 1903 #define KNL_DDR_FAR BIT_ULL(24) 1904 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1905 KNL_DDR_LOCAL | KNL_DDR_FAR) 1906 #define KNL_L2_READ SLM_DMND_READ 1907 #define KNL_L2_WRITE SLM_DMND_WRITE 1908 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1909 #define KNL_L2_ACCESS SLM_LLC_ACCESS 1910 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1911 KNL_DRAM_ANY | SNB_SNP_ANY | \ 1912 SNB_NON_DRAM) 1913 1914 static __initconst const u64 knl_hw_cache_extra_regs 1915 [PERF_COUNT_HW_CACHE_MAX] 1916 [PERF_COUNT_HW_CACHE_OP_MAX] 1917 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1918 [C(LL)] = { 1919 [C(OP_READ)] = { 1920 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1921 [C(RESULT_MISS)] = 0, 1922 }, 1923 [C(OP_WRITE)] = { 1924 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1925 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1926 }, 1927 [C(OP_PREFETCH)] = { 1928 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1929 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1930 }, 1931 }, 1932 }; 1933 1934 /* 1935 * Used from PMIs where the LBRs are already disabled. 1936 * 1937 * This function could be called consecutively. It is required to remain in 1938 * disabled state if called consecutively. 1939 * 1940 * During consecutive calls, the same disable value will be written to related 1941 * registers, so the PMU state remains unchanged. 1942 * 1943 * intel_bts events don't coexist with intel PMU's BTS events because of 1944 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1945 * disabled around intel PMU's event batching etc, only inside the PMI handler. 1946 */ 1947 static void __intel_pmu_disable_all(void) 1948 { 1949 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1950 1951 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1952 1953 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1954 intel_pmu_disable_bts(); 1955 1956 intel_pmu_pebs_disable_all(); 1957 } 1958 1959 static void intel_pmu_disable_all(void) 1960 { 1961 __intel_pmu_disable_all(); 1962 intel_pmu_lbr_disable_all(); 1963 } 1964 1965 static void __intel_pmu_enable_all(int added, bool pmi) 1966 { 1967 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1968 1969 intel_pmu_pebs_enable_all(); 1970 intel_pmu_lbr_enable_all(pmi); 1971 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1972 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1973 1974 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1975 struct perf_event *event = 1976 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1977 1978 if (WARN_ON_ONCE(!event)) 1979 return; 1980 1981 intel_pmu_enable_bts(event->hw.config); 1982 } 1983 } 1984 1985 static void intel_pmu_enable_all(int added) 1986 { 1987 __intel_pmu_enable_all(added, false); 1988 } 1989 1990 /* 1991 * Workaround for: 1992 * Intel Errata AAK100 (model 26) 1993 * Intel Errata AAP53 (model 30) 1994 * Intel Errata BD53 (model 44) 1995 * 1996 * The official story: 1997 * These chips need to be 'reset' when adding counters by programming the 1998 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 1999 * in sequence on the same PMC or on different PMCs. 2000 * 2001 * In practise it appears some of these events do in fact count, and 2002 * we need to program all 4 events. 2003 */ 2004 static void intel_pmu_nhm_workaround(void) 2005 { 2006 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2007 static const unsigned long nhm_magic[4] = { 2008 0x4300B5, 2009 0x4300D2, 2010 0x4300B1, 2011 0x4300B1 2012 }; 2013 struct perf_event *event; 2014 int i; 2015 2016 /* 2017 * The Errata requires below steps: 2018 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2019 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2020 * the corresponding PMCx; 2021 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2022 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2023 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2024 */ 2025 2026 /* 2027 * The real steps we choose are a little different from above. 2028 * A) To reduce MSR operations, we don't run step 1) as they 2029 * are already cleared before this function is called; 2030 * B) Call x86_perf_event_update to save PMCx before configuring 2031 * PERFEVTSELx with magic number; 2032 * C) With step 5), we do clear only when the PERFEVTSELx is 2033 * not used currently. 2034 * D) Call x86_perf_event_set_period to restore PMCx; 2035 */ 2036 2037 /* We always operate 4 pairs of PERF Counters */ 2038 for (i = 0; i < 4; i++) { 2039 event = cpuc->events[i]; 2040 if (event) 2041 x86_perf_event_update(event); 2042 } 2043 2044 for (i = 0; i < 4; i++) { 2045 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2046 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2047 } 2048 2049 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2050 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2051 2052 for (i = 0; i < 4; i++) { 2053 event = cpuc->events[i]; 2054 2055 if (event) { 2056 x86_perf_event_set_period(event); 2057 __x86_pmu_enable_event(&event->hw, 2058 ARCH_PERFMON_EVENTSEL_ENABLE); 2059 } else 2060 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2061 } 2062 } 2063 2064 static void intel_pmu_nhm_enable_all(int added) 2065 { 2066 if (added) 2067 intel_pmu_nhm_workaround(); 2068 intel_pmu_enable_all(added); 2069 } 2070 2071 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2072 { 2073 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2074 2075 if (cpuc->tfa_shadow != val) { 2076 cpuc->tfa_shadow = val; 2077 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2078 } 2079 } 2080 2081 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2082 { 2083 /* 2084 * We're going to use PMC3, make sure TFA is set before we touch it. 2085 */ 2086 if (cntr == 3) 2087 intel_set_tfa(cpuc, true); 2088 } 2089 2090 static void intel_tfa_pmu_enable_all(int added) 2091 { 2092 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2093 2094 /* 2095 * If we find PMC3 is no longer used when we enable the PMU, we can 2096 * clear TFA. 2097 */ 2098 if (!test_bit(3, cpuc->active_mask)) 2099 intel_set_tfa(cpuc, false); 2100 2101 intel_pmu_enable_all(added); 2102 } 2103 2104 static void enable_counter_freeze(void) 2105 { 2106 update_debugctlmsr(get_debugctlmsr() | 2107 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2108 } 2109 2110 static void disable_counter_freeze(void) 2111 { 2112 update_debugctlmsr(get_debugctlmsr() & 2113 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2114 } 2115 2116 static inline u64 intel_pmu_get_status(void) 2117 { 2118 u64 status; 2119 2120 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2121 2122 return status; 2123 } 2124 2125 static inline void intel_pmu_ack_status(u64 ack) 2126 { 2127 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2128 } 2129 2130 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 2131 { 2132 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2133 u64 ctrl_val, mask; 2134 2135 mask = 0xfULL << (idx * 4); 2136 2137 rdmsrl(hwc->config_base, ctrl_val); 2138 ctrl_val &= ~mask; 2139 wrmsrl(hwc->config_base, ctrl_val); 2140 } 2141 2142 static inline bool event_is_checkpointed(struct perf_event *event) 2143 { 2144 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2145 } 2146 2147 static void intel_pmu_disable_event(struct perf_event *event) 2148 { 2149 struct hw_perf_event *hwc = &event->hw; 2150 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2151 2152 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2153 intel_pmu_disable_bts(); 2154 intel_pmu_drain_bts_buffer(); 2155 return; 2156 } 2157 2158 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); 2159 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); 2160 cpuc->intel_cp_status &= ~(1ull << hwc->idx); 2161 2162 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2163 intel_pmu_disable_fixed(hwc); 2164 return; 2165 } 2166 2167 x86_pmu_disable_event(event); 2168 2169 /* 2170 * Needs to be called after x86_pmu_disable_event, 2171 * so we don't trigger the event without PEBS bit set. 2172 */ 2173 if (unlikely(event->attr.precise_ip)) 2174 intel_pmu_pebs_disable(event); 2175 } 2176 2177 static void intel_pmu_del_event(struct perf_event *event) 2178 { 2179 if (needs_branch_stack(event)) 2180 intel_pmu_lbr_del(event); 2181 if (event->attr.precise_ip) 2182 intel_pmu_pebs_del(event); 2183 } 2184 2185 static void intel_pmu_read_event(struct perf_event *event) 2186 { 2187 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2188 intel_pmu_auto_reload_read(event); 2189 else 2190 x86_perf_event_update(event); 2191 } 2192 2193 static void intel_pmu_enable_fixed(struct perf_event *event) 2194 { 2195 struct hw_perf_event *hwc = &event->hw; 2196 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2197 u64 ctrl_val, mask, bits = 0; 2198 2199 /* 2200 * Enable IRQ generation (0x8), if not PEBS, 2201 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2202 * if requested: 2203 */ 2204 if (!event->attr.precise_ip) 2205 bits |= 0x8; 2206 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2207 bits |= 0x2; 2208 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2209 bits |= 0x1; 2210 2211 /* 2212 * ANY bit is supported in v3 and up 2213 */ 2214 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2215 bits |= 0x4; 2216 2217 bits <<= (idx * 4); 2218 mask = 0xfULL << (idx * 4); 2219 2220 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2221 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2222 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2223 } 2224 2225 rdmsrl(hwc->config_base, ctrl_val); 2226 ctrl_val &= ~mask; 2227 ctrl_val |= bits; 2228 wrmsrl(hwc->config_base, ctrl_val); 2229 } 2230 2231 static void intel_pmu_enable_event(struct perf_event *event) 2232 { 2233 struct hw_perf_event *hwc = &event->hw; 2234 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2235 2236 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2237 if (!__this_cpu_read(cpu_hw_events.enabled)) 2238 return; 2239 2240 intel_pmu_enable_bts(hwc->config); 2241 return; 2242 } 2243 2244 if (event->attr.exclude_host) 2245 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); 2246 if (event->attr.exclude_guest) 2247 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); 2248 2249 if (unlikely(event_is_checkpointed(event))) 2250 cpuc->intel_cp_status |= (1ull << hwc->idx); 2251 2252 if (unlikely(event->attr.precise_ip)) 2253 intel_pmu_pebs_enable(event); 2254 2255 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2256 intel_pmu_enable_fixed(event); 2257 return; 2258 } 2259 2260 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2261 } 2262 2263 static void intel_pmu_add_event(struct perf_event *event) 2264 { 2265 if (event->attr.precise_ip) 2266 intel_pmu_pebs_add(event); 2267 if (needs_branch_stack(event)) 2268 intel_pmu_lbr_add(event); 2269 } 2270 2271 /* 2272 * Save and restart an expired event. Called by NMI contexts, 2273 * so it has to be careful about preempting normal event ops: 2274 */ 2275 int intel_pmu_save_and_restart(struct perf_event *event) 2276 { 2277 x86_perf_event_update(event); 2278 /* 2279 * For a checkpointed counter always reset back to 0. This 2280 * avoids a situation where the counter overflows, aborts the 2281 * transaction and is then set back to shortly before the 2282 * overflow, and overflows and aborts again. 2283 */ 2284 if (unlikely(event_is_checkpointed(event))) { 2285 /* No race with NMIs because the counter should not be armed */ 2286 wrmsrl(event->hw.event_base, 0); 2287 local64_set(&event->hw.prev_count, 0); 2288 } 2289 return x86_perf_event_set_period(event); 2290 } 2291 2292 static void intel_pmu_reset(void) 2293 { 2294 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2295 unsigned long flags; 2296 int idx; 2297 2298 if (!x86_pmu.num_counters) 2299 return; 2300 2301 local_irq_save(flags); 2302 2303 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2304 2305 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2306 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2307 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2308 } 2309 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2310 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2311 2312 if (ds) 2313 ds->bts_index = ds->bts_buffer_base; 2314 2315 /* Ack all overflows and disable fixed counters */ 2316 if (x86_pmu.version >= 2) { 2317 intel_pmu_ack_status(intel_pmu_get_status()); 2318 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2319 } 2320 2321 /* Reset LBRs and LBR freezing */ 2322 if (x86_pmu.lbr_nr) { 2323 update_debugctlmsr(get_debugctlmsr() & 2324 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2325 } 2326 2327 local_irq_restore(flags); 2328 } 2329 2330 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2331 { 2332 struct perf_sample_data data; 2333 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2334 int bit; 2335 int handled = 0; 2336 2337 inc_irq_stat(apic_perf_irqs); 2338 2339 /* 2340 * Ignore a range of extra bits in status that do not indicate 2341 * overflow by themselves. 2342 */ 2343 status &= ~(GLOBAL_STATUS_COND_CHG | 2344 GLOBAL_STATUS_ASIF | 2345 GLOBAL_STATUS_LBRS_FROZEN); 2346 if (!status) 2347 return 0; 2348 /* 2349 * In case multiple PEBS events are sampled at the same time, 2350 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2351 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2352 * having their bits set in the status register. This is a sign 2353 * that there was at least one PEBS record pending at the time 2354 * of the PMU interrupt. PEBS counters must only be processed 2355 * via the drain_pebs() calls and not via the regular sample 2356 * processing loop coming after that the function, otherwise 2357 * phony regular samples may be generated in the sampling buffer 2358 * not marked with the EXACT tag. Another possibility is to have 2359 * one PEBS event and at least one non-PEBS event whic hoverflows 2360 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2361 * not be set, yet the overflow status bit for the PEBS counter will 2362 * be on Skylake. 2363 * 2364 * To avoid this problem, we systematically ignore the PEBS-enabled 2365 * counters from the GLOBAL_STATUS mask and we always process PEBS 2366 * events via drain_pebs(). 2367 */ 2368 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2369 status &= ~cpuc->pebs_enabled; 2370 else 2371 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2372 2373 /* 2374 * PEBS overflow sets bit 62 in the global status register 2375 */ 2376 if (__test_and_clear_bit(62, (unsigned long *)&status)) { 2377 handled++; 2378 x86_pmu.drain_pebs(regs); 2379 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2380 } 2381 2382 /* 2383 * Intel PT 2384 */ 2385 if (__test_and_clear_bit(55, (unsigned long *)&status)) { 2386 handled++; 2387 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 2388 perf_guest_cbs->handle_intel_pt_intr)) 2389 perf_guest_cbs->handle_intel_pt_intr(); 2390 else 2391 intel_pt_interrupt(); 2392 } 2393 2394 /* 2395 * Checkpointed counters can lead to 'spurious' PMIs because the 2396 * rollback caused by the PMI will have cleared the overflow status 2397 * bit. Therefore always force probe these counters. 2398 */ 2399 status |= cpuc->intel_cp_status; 2400 2401 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2402 struct perf_event *event = cpuc->events[bit]; 2403 2404 handled++; 2405 2406 if (!test_bit(bit, cpuc->active_mask)) 2407 continue; 2408 2409 if (!intel_pmu_save_and_restart(event)) 2410 continue; 2411 2412 perf_sample_data_init(&data, 0, event->hw.last_period); 2413 2414 if (has_branch_stack(event)) 2415 data.br_stack = &cpuc->lbr_stack; 2416 2417 if (perf_event_overflow(event, &data, regs)) 2418 x86_pmu_stop(event, 0); 2419 } 2420 2421 return handled; 2422 } 2423 2424 static bool disable_counter_freezing = true; 2425 static int __init intel_perf_counter_freezing_setup(char *s) 2426 { 2427 bool res; 2428 2429 if (kstrtobool(s, &res)) 2430 return -EINVAL; 2431 2432 disable_counter_freezing = !res; 2433 return 1; 2434 } 2435 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup); 2436 2437 /* 2438 * Simplified handler for Arch Perfmon v4: 2439 * - We rely on counter freezing/unfreezing to enable/disable the PMU. 2440 * This is done automatically on PMU ack. 2441 * - Ack the PMU only after the APIC. 2442 */ 2443 2444 static int intel_pmu_handle_irq_v4(struct pt_regs *regs) 2445 { 2446 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2447 int handled = 0; 2448 bool bts = false; 2449 u64 status; 2450 int pmu_enabled = cpuc->enabled; 2451 int loops = 0; 2452 2453 /* PMU has been disabled because of counter freezing */ 2454 cpuc->enabled = 0; 2455 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2456 bts = true; 2457 intel_bts_disable_local(); 2458 handled = intel_pmu_drain_bts_buffer(); 2459 handled += intel_bts_interrupt(); 2460 } 2461 status = intel_pmu_get_status(); 2462 if (!status) 2463 goto done; 2464 again: 2465 intel_pmu_lbr_read(); 2466 if (++loops > 100) { 2467 static bool warned; 2468 2469 if (!warned) { 2470 WARN(1, "perfevents: irq loop stuck!\n"); 2471 perf_event_print_debug(); 2472 warned = true; 2473 } 2474 intel_pmu_reset(); 2475 goto done; 2476 } 2477 2478 2479 handled += handle_pmi_common(regs, status); 2480 done: 2481 /* Ack the PMI in the APIC */ 2482 apic_write(APIC_LVTPC, APIC_DM_NMI); 2483 2484 /* 2485 * The counters start counting immediately while ack the status. 2486 * Make it as close as possible to IRET. This avoids bogus 2487 * freezing on Skylake CPUs. 2488 */ 2489 if (status) { 2490 intel_pmu_ack_status(status); 2491 } else { 2492 /* 2493 * CPU may issues two PMIs very close to each other. 2494 * When the PMI handler services the first one, the 2495 * GLOBAL_STATUS is already updated to reflect both. 2496 * When it IRETs, the second PMI is immediately 2497 * handled and it sees clear status. At the meantime, 2498 * there may be a third PMI, because the freezing bit 2499 * isn't set since the ack in first PMI handlers. 2500 * Double check if there is more work to be done. 2501 */ 2502 status = intel_pmu_get_status(); 2503 if (status) 2504 goto again; 2505 } 2506 2507 if (bts) 2508 intel_bts_enable_local(); 2509 cpuc->enabled = pmu_enabled; 2510 return handled; 2511 } 2512 2513 /* 2514 * This handler is triggered by the local APIC, so the APIC IRQ handling 2515 * rules apply: 2516 */ 2517 static int intel_pmu_handle_irq(struct pt_regs *regs) 2518 { 2519 struct cpu_hw_events *cpuc; 2520 int loops; 2521 u64 status; 2522 int handled; 2523 int pmu_enabled; 2524 2525 cpuc = this_cpu_ptr(&cpu_hw_events); 2526 2527 /* 2528 * Save the PMU state. 2529 * It needs to be restored when leaving the handler. 2530 */ 2531 pmu_enabled = cpuc->enabled; 2532 /* 2533 * No known reason to not always do late ACK, 2534 * but just in case do it opt-in. 2535 */ 2536 if (!x86_pmu.late_ack) 2537 apic_write(APIC_LVTPC, APIC_DM_NMI); 2538 intel_bts_disable_local(); 2539 cpuc->enabled = 0; 2540 __intel_pmu_disable_all(); 2541 handled = intel_pmu_drain_bts_buffer(); 2542 handled += intel_bts_interrupt(); 2543 status = intel_pmu_get_status(); 2544 if (!status) 2545 goto done; 2546 2547 loops = 0; 2548 again: 2549 intel_pmu_lbr_read(); 2550 intel_pmu_ack_status(status); 2551 if (++loops > 100) { 2552 static bool warned; 2553 2554 if (!warned) { 2555 WARN(1, "perfevents: irq loop stuck!\n"); 2556 perf_event_print_debug(); 2557 warned = true; 2558 } 2559 intel_pmu_reset(); 2560 goto done; 2561 } 2562 2563 handled += handle_pmi_common(regs, status); 2564 2565 /* 2566 * Repeat if there is more work to be done: 2567 */ 2568 status = intel_pmu_get_status(); 2569 if (status) 2570 goto again; 2571 2572 done: 2573 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 2574 cpuc->enabled = pmu_enabled; 2575 if (pmu_enabled) 2576 __intel_pmu_enable_all(0, true); 2577 intel_bts_enable_local(); 2578 2579 /* 2580 * Only unmask the NMI after the overflow counters 2581 * have been reset. This avoids spurious NMIs on 2582 * Haswell CPUs. 2583 */ 2584 if (x86_pmu.late_ack) 2585 apic_write(APIC_LVTPC, APIC_DM_NMI); 2586 return handled; 2587 } 2588 2589 static struct event_constraint * 2590 intel_bts_constraints(struct perf_event *event) 2591 { 2592 if (unlikely(intel_pmu_has_bts(event))) 2593 return &bts_constraint; 2594 2595 return NULL; 2596 } 2597 2598 static int intel_alt_er(int idx, u64 config) 2599 { 2600 int alt_idx = idx; 2601 2602 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2603 return idx; 2604 2605 if (idx == EXTRA_REG_RSP_0) 2606 alt_idx = EXTRA_REG_RSP_1; 2607 2608 if (idx == EXTRA_REG_RSP_1) 2609 alt_idx = EXTRA_REG_RSP_0; 2610 2611 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2612 return idx; 2613 2614 return alt_idx; 2615 } 2616 2617 static void intel_fixup_er(struct perf_event *event, int idx) 2618 { 2619 event->hw.extra_reg.idx = idx; 2620 2621 if (idx == EXTRA_REG_RSP_0) { 2622 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2623 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2624 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2625 } else if (idx == EXTRA_REG_RSP_1) { 2626 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2627 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2628 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2629 } 2630 } 2631 2632 /* 2633 * manage allocation of shared extra msr for certain events 2634 * 2635 * sharing can be: 2636 * per-cpu: to be shared between the various events on a single PMU 2637 * per-core: per-cpu + shared by HT threads 2638 */ 2639 static struct event_constraint * 2640 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2641 struct perf_event *event, 2642 struct hw_perf_event_extra *reg) 2643 { 2644 struct event_constraint *c = &emptyconstraint; 2645 struct er_account *era; 2646 unsigned long flags; 2647 int idx = reg->idx; 2648 2649 /* 2650 * reg->alloc can be set due to existing state, so for fake cpuc we 2651 * need to ignore this, otherwise we might fail to allocate proper fake 2652 * state for this extra reg constraint. Also see the comment below. 2653 */ 2654 if (reg->alloc && !cpuc->is_fake) 2655 return NULL; /* call x86_get_event_constraint() */ 2656 2657 again: 2658 era = &cpuc->shared_regs->regs[idx]; 2659 /* 2660 * we use spin_lock_irqsave() to avoid lockdep issues when 2661 * passing a fake cpuc 2662 */ 2663 raw_spin_lock_irqsave(&era->lock, flags); 2664 2665 if (!atomic_read(&era->ref) || era->config == reg->config) { 2666 2667 /* 2668 * If its a fake cpuc -- as per validate_{group,event}() we 2669 * shouldn't touch event state and we can avoid doing so 2670 * since both will only call get_event_constraints() once 2671 * on each event, this avoids the need for reg->alloc. 2672 * 2673 * Not doing the ER fixup will only result in era->reg being 2674 * wrong, but since we won't actually try and program hardware 2675 * this isn't a problem either. 2676 */ 2677 if (!cpuc->is_fake) { 2678 if (idx != reg->idx) 2679 intel_fixup_er(event, idx); 2680 2681 /* 2682 * x86_schedule_events() can call get_event_constraints() 2683 * multiple times on events in the case of incremental 2684 * scheduling(). reg->alloc ensures we only do the ER 2685 * allocation once. 2686 */ 2687 reg->alloc = 1; 2688 } 2689 2690 /* lock in msr value */ 2691 era->config = reg->config; 2692 era->reg = reg->reg; 2693 2694 /* one more user */ 2695 atomic_inc(&era->ref); 2696 2697 /* 2698 * need to call x86_get_event_constraint() 2699 * to check if associated event has constraints 2700 */ 2701 c = NULL; 2702 } else { 2703 idx = intel_alt_er(idx, reg->config); 2704 if (idx != reg->idx) { 2705 raw_spin_unlock_irqrestore(&era->lock, flags); 2706 goto again; 2707 } 2708 } 2709 raw_spin_unlock_irqrestore(&era->lock, flags); 2710 2711 return c; 2712 } 2713 2714 static void 2715 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 2716 struct hw_perf_event_extra *reg) 2717 { 2718 struct er_account *era; 2719 2720 /* 2721 * Only put constraint if extra reg was actually allocated. Also takes 2722 * care of event which do not use an extra shared reg. 2723 * 2724 * Also, if this is a fake cpuc we shouldn't touch any event state 2725 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 2726 * either since it'll be thrown out. 2727 */ 2728 if (!reg->alloc || cpuc->is_fake) 2729 return; 2730 2731 era = &cpuc->shared_regs->regs[reg->idx]; 2732 2733 /* one fewer user */ 2734 atomic_dec(&era->ref); 2735 2736 /* allocate again next time */ 2737 reg->alloc = 0; 2738 } 2739 2740 static struct event_constraint * 2741 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 2742 struct perf_event *event) 2743 { 2744 struct event_constraint *c = NULL, *d; 2745 struct hw_perf_event_extra *xreg, *breg; 2746 2747 xreg = &event->hw.extra_reg; 2748 if (xreg->idx != EXTRA_REG_NONE) { 2749 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 2750 if (c == &emptyconstraint) 2751 return c; 2752 } 2753 breg = &event->hw.branch_reg; 2754 if (breg->idx != EXTRA_REG_NONE) { 2755 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 2756 if (d == &emptyconstraint) { 2757 __intel_shared_reg_put_constraints(cpuc, xreg); 2758 c = d; 2759 } 2760 } 2761 return c; 2762 } 2763 2764 struct event_constraint * 2765 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2766 struct perf_event *event) 2767 { 2768 struct event_constraint *c; 2769 2770 if (x86_pmu.event_constraints) { 2771 for_each_event_constraint(c, x86_pmu.event_constraints) { 2772 if (constraint_match(c, event->hw.config)) { 2773 event->hw.flags |= c->flags; 2774 return c; 2775 } 2776 } 2777 } 2778 2779 return &unconstrained; 2780 } 2781 2782 static struct event_constraint * 2783 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2784 struct perf_event *event) 2785 { 2786 struct event_constraint *c; 2787 2788 c = intel_bts_constraints(event); 2789 if (c) 2790 return c; 2791 2792 c = intel_shared_regs_constraints(cpuc, event); 2793 if (c) 2794 return c; 2795 2796 c = intel_pebs_constraints(event); 2797 if (c) 2798 return c; 2799 2800 return x86_get_event_constraints(cpuc, idx, event); 2801 } 2802 2803 static void 2804 intel_start_scheduling(struct cpu_hw_events *cpuc) 2805 { 2806 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2807 struct intel_excl_states *xl; 2808 int tid = cpuc->excl_thread_id; 2809 2810 /* 2811 * nothing needed if in group validation mode 2812 */ 2813 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2814 return; 2815 2816 /* 2817 * no exclusion needed 2818 */ 2819 if (WARN_ON_ONCE(!excl_cntrs)) 2820 return; 2821 2822 xl = &excl_cntrs->states[tid]; 2823 2824 xl->sched_started = true; 2825 /* 2826 * lock shared state until we are done scheduling 2827 * in stop_event_scheduling() 2828 * makes scheduling appear as a transaction 2829 */ 2830 raw_spin_lock(&excl_cntrs->lock); 2831 } 2832 2833 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2834 { 2835 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2836 struct event_constraint *c = cpuc->event_constraint[idx]; 2837 struct intel_excl_states *xl; 2838 int tid = cpuc->excl_thread_id; 2839 2840 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2841 return; 2842 2843 if (WARN_ON_ONCE(!excl_cntrs)) 2844 return; 2845 2846 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 2847 return; 2848 2849 xl = &excl_cntrs->states[tid]; 2850 2851 lockdep_assert_held(&excl_cntrs->lock); 2852 2853 if (c->flags & PERF_X86_EVENT_EXCL) 2854 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 2855 else 2856 xl->state[cntr] = INTEL_EXCL_SHARED; 2857 } 2858 2859 static void 2860 intel_stop_scheduling(struct cpu_hw_events *cpuc) 2861 { 2862 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2863 struct intel_excl_states *xl; 2864 int tid = cpuc->excl_thread_id; 2865 2866 /* 2867 * nothing needed if in group validation mode 2868 */ 2869 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2870 return; 2871 /* 2872 * no exclusion needed 2873 */ 2874 if (WARN_ON_ONCE(!excl_cntrs)) 2875 return; 2876 2877 xl = &excl_cntrs->states[tid]; 2878 2879 xl->sched_started = false; 2880 /* 2881 * release shared state lock (acquired in intel_start_scheduling()) 2882 */ 2883 raw_spin_unlock(&excl_cntrs->lock); 2884 } 2885 2886 static struct event_constraint * 2887 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 2888 { 2889 WARN_ON_ONCE(!cpuc->constraint_list); 2890 2891 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 2892 struct event_constraint *cx; 2893 2894 /* 2895 * grab pre-allocated constraint entry 2896 */ 2897 cx = &cpuc->constraint_list[idx]; 2898 2899 /* 2900 * initialize dynamic constraint 2901 * with static constraint 2902 */ 2903 *cx = *c; 2904 2905 /* 2906 * mark constraint as dynamic 2907 */ 2908 cx->flags |= PERF_X86_EVENT_DYNAMIC; 2909 c = cx; 2910 } 2911 2912 return c; 2913 } 2914 2915 static struct event_constraint * 2916 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 2917 int idx, struct event_constraint *c) 2918 { 2919 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2920 struct intel_excl_states *xlo; 2921 int tid = cpuc->excl_thread_id; 2922 int is_excl, i, w; 2923 2924 /* 2925 * validating a group does not require 2926 * enforcing cross-thread exclusion 2927 */ 2928 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2929 return c; 2930 2931 /* 2932 * no exclusion needed 2933 */ 2934 if (WARN_ON_ONCE(!excl_cntrs)) 2935 return c; 2936 2937 /* 2938 * because we modify the constraint, we need 2939 * to make a copy. Static constraints come 2940 * from static const tables. 2941 * 2942 * only needed when constraint has not yet 2943 * been cloned (marked dynamic) 2944 */ 2945 c = dyn_constraint(cpuc, c, idx); 2946 2947 /* 2948 * From here on, the constraint is dynamic. 2949 * Either it was just allocated above, or it 2950 * was allocated during a earlier invocation 2951 * of this function 2952 */ 2953 2954 /* 2955 * state of sibling HT 2956 */ 2957 xlo = &excl_cntrs->states[tid ^ 1]; 2958 2959 /* 2960 * event requires exclusive counter access 2961 * across HT threads 2962 */ 2963 is_excl = c->flags & PERF_X86_EVENT_EXCL; 2964 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 2965 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 2966 if (!cpuc->n_excl++) 2967 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 2968 } 2969 2970 /* 2971 * Modify static constraint with current dynamic 2972 * state of thread 2973 * 2974 * EXCLUSIVE: sibling counter measuring exclusive event 2975 * SHARED : sibling counter measuring non-exclusive event 2976 * UNUSED : sibling counter unused 2977 */ 2978 w = c->weight; 2979 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 2980 /* 2981 * exclusive event in sibling counter 2982 * our corresponding counter cannot be used 2983 * regardless of our event 2984 */ 2985 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 2986 __clear_bit(i, c->idxmsk); 2987 w--; 2988 continue; 2989 } 2990 /* 2991 * if measuring an exclusive event, sibling 2992 * measuring non-exclusive, then counter cannot 2993 * be used 2994 */ 2995 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 2996 __clear_bit(i, c->idxmsk); 2997 w--; 2998 continue; 2999 } 3000 } 3001 3002 /* 3003 * if we return an empty mask, then switch 3004 * back to static empty constraint to avoid 3005 * the cost of freeing later on 3006 */ 3007 if (!w) 3008 c = &emptyconstraint; 3009 3010 c->weight = w; 3011 3012 return c; 3013 } 3014 3015 static struct event_constraint * 3016 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3017 struct perf_event *event) 3018 { 3019 struct event_constraint *c1, *c2; 3020 3021 c1 = cpuc->event_constraint[idx]; 3022 3023 /* 3024 * first time only 3025 * - static constraint: no change across incremental scheduling calls 3026 * - dynamic constraint: handled by intel_get_excl_constraints() 3027 */ 3028 c2 = __intel_get_event_constraints(cpuc, idx, event); 3029 if (c1) { 3030 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3031 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3032 c1->weight = c2->weight; 3033 c2 = c1; 3034 } 3035 3036 if (cpuc->excl_cntrs) 3037 return intel_get_excl_constraints(cpuc, event, idx, c2); 3038 3039 return c2; 3040 } 3041 3042 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3043 struct perf_event *event) 3044 { 3045 struct hw_perf_event *hwc = &event->hw; 3046 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3047 int tid = cpuc->excl_thread_id; 3048 struct intel_excl_states *xl; 3049 3050 /* 3051 * nothing needed if in group validation mode 3052 */ 3053 if (cpuc->is_fake) 3054 return; 3055 3056 if (WARN_ON_ONCE(!excl_cntrs)) 3057 return; 3058 3059 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3060 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3061 if (!--cpuc->n_excl) 3062 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3063 } 3064 3065 /* 3066 * If event was actually assigned, then mark the counter state as 3067 * unused now. 3068 */ 3069 if (hwc->idx >= 0) { 3070 xl = &excl_cntrs->states[tid]; 3071 3072 /* 3073 * put_constraint may be called from x86_schedule_events() 3074 * which already has the lock held so here make locking 3075 * conditional. 3076 */ 3077 if (!xl->sched_started) 3078 raw_spin_lock(&excl_cntrs->lock); 3079 3080 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3081 3082 if (!xl->sched_started) 3083 raw_spin_unlock(&excl_cntrs->lock); 3084 } 3085 } 3086 3087 static void 3088 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3089 struct perf_event *event) 3090 { 3091 struct hw_perf_event_extra *reg; 3092 3093 reg = &event->hw.extra_reg; 3094 if (reg->idx != EXTRA_REG_NONE) 3095 __intel_shared_reg_put_constraints(cpuc, reg); 3096 3097 reg = &event->hw.branch_reg; 3098 if (reg->idx != EXTRA_REG_NONE) 3099 __intel_shared_reg_put_constraints(cpuc, reg); 3100 } 3101 3102 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3103 struct perf_event *event) 3104 { 3105 intel_put_shared_regs_event_constraints(cpuc, event); 3106 3107 /* 3108 * is PMU has exclusive counter restrictions, then 3109 * all events are subject to and must call the 3110 * put_excl_constraints() routine 3111 */ 3112 if (cpuc->excl_cntrs) 3113 intel_put_excl_constraints(cpuc, event); 3114 } 3115 3116 static void intel_pebs_aliases_core2(struct perf_event *event) 3117 { 3118 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3119 /* 3120 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3121 * (0x003c) so that we can use it with PEBS. 3122 * 3123 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3124 * PEBS capable. However we can use INST_RETIRED.ANY_P 3125 * (0x00c0), which is a PEBS capable event, to get the same 3126 * count. 3127 * 3128 * INST_RETIRED.ANY_P counts the number of cycles that retires 3129 * CNTMASK instructions. By setting CNTMASK to a value (16) 3130 * larger than the maximum number of instructions that can be 3131 * retired per cycle (4) and then inverting the condition, we 3132 * count all cycles that retire 16 or less instructions, which 3133 * is every cycle. 3134 * 3135 * Thereby we gain a PEBS capable cycle counter. 3136 */ 3137 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3138 3139 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3140 event->hw.config = alt_config; 3141 } 3142 } 3143 3144 static void intel_pebs_aliases_snb(struct perf_event *event) 3145 { 3146 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3147 /* 3148 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3149 * (0x003c) so that we can use it with PEBS. 3150 * 3151 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3152 * PEBS capable. However we can use UOPS_RETIRED.ALL 3153 * (0x01c2), which is a PEBS capable event, to get the same 3154 * count. 3155 * 3156 * UOPS_RETIRED.ALL counts the number of cycles that retires 3157 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3158 * larger than the maximum number of micro-ops that can be 3159 * retired per cycle (4) and then inverting the condition, we 3160 * count all cycles that retire 16 or less micro-ops, which 3161 * is every cycle. 3162 * 3163 * Thereby we gain a PEBS capable cycle counter. 3164 */ 3165 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3166 3167 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3168 event->hw.config = alt_config; 3169 } 3170 } 3171 3172 static void intel_pebs_aliases_precdist(struct perf_event *event) 3173 { 3174 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3175 /* 3176 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3177 * (0x003c) so that we can use it with PEBS. 3178 * 3179 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3180 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3181 * (0x01c0), which is a PEBS capable event, to get the same 3182 * count. 3183 * 3184 * The PREC_DIST event has special support to minimize sample 3185 * shadowing effects. One drawback is that it can be 3186 * only programmed on counter 1, but that seems like an 3187 * acceptable trade off. 3188 */ 3189 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3190 3191 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3192 event->hw.config = alt_config; 3193 } 3194 } 3195 3196 static void intel_pebs_aliases_ivb(struct perf_event *event) 3197 { 3198 if (event->attr.precise_ip < 3) 3199 return intel_pebs_aliases_snb(event); 3200 return intel_pebs_aliases_precdist(event); 3201 } 3202 3203 static void intel_pebs_aliases_skl(struct perf_event *event) 3204 { 3205 if (event->attr.precise_ip < 3) 3206 return intel_pebs_aliases_core2(event); 3207 return intel_pebs_aliases_precdist(event); 3208 } 3209 3210 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3211 { 3212 unsigned long flags = x86_pmu.large_pebs_flags; 3213 3214 if (event->attr.use_clockid) 3215 flags &= ~PERF_SAMPLE_TIME; 3216 if (!event->attr.exclude_kernel) 3217 flags &= ~PERF_SAMPLE_REGS_USER; 3218 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3219 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3220 return flags; 3221 } 3222 3223 static int intel_pmu_bts_config(struct perf_event *event) 3224 { 3225 struct perf_event_attr *attr = &event->attr; 3226 3227 if (unlikely(intel_pmu_has_bts(event))) { 3228 /* BTS is not supported by this architecture. */ 3229 if (!x86_pmu.bts_active) 3230 return -EOPNOTSUPP; 3231 3232 /* BTS is currently only allowed for user-mode. */ 3233 if (!attr->exclude_kernel) 3234 return -EOPNOTSUPP; 3235 3236 /* BTS is not allowed for precise events. */ 3237 if (attr->precise_ip) 3238 return -EOPNOTSUPP; 3239 3240 /* disallow bts if conflicting events are present */ 3241 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3242 return -EBUSY; 3243 3244 event->destroy = hw_perf_lbr_event_destroy; 3245 } 3246 3247 return 0; 3248 } 3249 3250 static int core_pmu_hw_config(struct perf_event *event) 3251 { 3252 int ret = x86_pmu_hw_config(event); 3253 3254 if (ret) 3255 return ret; 3256 3257 return intel_pmu_bts_config(event); 3258 } 3259 3260 static int intel_pmu_hw_config(struct perf_event *event) 3261 { 3262 int ret = x86_pmu_hw_config(event); 3263 3264 if (ret) 3265 return ret; 3266 3267 ret = intel_pmu_bts_config(event); 3268 if (ret) 3269 return ret; 3270 3271 if (event->attr.precise_ip) { 3272 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3273 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3274 if (!(event->attr.sample_type & 3275 ~intel_pmu_large_pebs_flags(event))) 3276 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3277 } 3278 if (x86_pmu.pebs_aliases) 3279 x86_pmu.pebs_aliases(event); 3280 3281 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3282 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3283 } 3284 3285 if (needs_branch_stack(event)) { 3286 ret = intel_pmu_setup_lbr_filter(event); 3287 if (ret) 3288 return ret; 3289 3290 /* 3291 * BTS is set up earlier in this path, so don't account twice 3292 */ 3293 if (!unlikely(intel_pmu_has_bts(event))) { 3294 /* disallow lbr if conflicting events are present */ 3295 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3296 return -EBUSY; 3297 3298 event->destroy = hw_perf_lbr_event_destroy; 3299 } 3300 } 3301 3302 if (event->attr.type != PERF_TYPE_RAW) 3303 return 0; 3304 3305 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3306 return 0; 3307 3308 if (x86_pmu.version < 3) 3309 return -EINVAL; 3310 3311 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) 3312 return -EACCES; 3313 3314 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3315 3316 return 0; 3317 } 3318 3319 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3320 { 3321 if (x86_pmu.guest_get_msrs) 3322 return x86_pmu.guest_get_msrs(nr); 3323 *nr = 0; 3324 return NULL; 3325 } 3326 EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3327 3328 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3329 { 3330 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3331 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3332 3333 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3334 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3335 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3336 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 3337 arr[0].guest &= ~cpuc->pebs_enabled; 3338 else 3339 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 3340 *nr = 1; 3341 3342 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3343 /* 3344 * If PMU counter has PEBS enabled it is not enough to 3345 * disable counter on a guest entry since PEBS memory 3346 * write can overshoot guest entry and corrupt guest 3347 * memory. Disabling PEBS solves the problem. 3348 * 3349 * Don't do this if the CPU already enforces it. 3350 */ 3351 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3352 arr[1].host = cpuc->pebs_enabled; 3353 arr[1].guest = 0; 3354 *nr = 2; 3355 } 3356 3357 return arr; 3358 } 3359 3360 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3361 { 3362 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3363 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3364 int idx; 3365 3366 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3367 struct perf_event *event = cpuc->events[idx]; 3368 3369 arr[idx].msr = x86_pmu_config_addr(idx); 3370 arr[idx].host = arr[idx].guest = 0; 3371 3372 if (!test_bit(idx, cpuc->active_mask)) 3373 continue; 3374 3375 arr[idx].host = arr[idx].guest = 3376 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3377 3378 if (event->attr.exclude_host) 3379 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3380 else if (event->attr.exclude_guest) 3381 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3382 } 3383 3384 *nr = x86_pmu.num_counters; 3385 return arr; 3386 } 3387 3388 static void core_pmu_enable_event(struct perf_event *event) 3389 { 3390 if (!event->attr.exclude_host) 3391 x86_pmu_enable_event(event); 3392 } 3393 3394 static void core_pmu_enable_all(int added) 3395 { 3396 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3397 int idx; 3398 3399 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3400 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3401 3402 if (!test_bit(idx, cpuc->active_mask) || 3403 cpuc->events[idx]->attr.exclude_host) 3404 continue; 3405 3406 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3407 } 3408 } 3409 3410 static int hsw_hw_config(struct perf_event *event) 3411 { 3412 int ret = intel_pmu_hw_config(event); 3413 3414 if (ret) 3415 return ret; 3416 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3417 return 0; 3418 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3419 3420 /* 3421 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3422 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3423 * this combination. 3424 */ 3425 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3426 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3427 event->attr.precise_ip > 0)) 3428 return -EOPNOTSUPP; 3429 3430 if (event_is_checkpointed(event)) { 3431 /* 3432 * Sampling of checkpointed events can cause situations where 3433 * the CPU constantly aborts because of a overflow, which is 3434 * then checkpointed back and ignored. Forbid checkpointing 3435 * for sampling. 3436 * 3437 * But still allow a long sampling period, so that perf stat 3438 * from KVM works. 3439 */ 3440 if (event->attr.sample_period > 0 && 3441 event->attr.sample_period < 0x7fffffff) 3442 return -EOPNOTSUPP; 3443 } 3444 return 0; 3445 } 3446 3447 static struct event_constraint counter0_constraint = 3448 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3449 3450 static struct event_constraint counter2_constraint = 3451 EVENT_CONSTRAINT(0, 0x4, 0); 3452 3453 static struct event_constraint fixed0_constraint = 3454 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 3455 3456 static struct event_constraint fixed0_counter0_constraint = 3457 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 3458 3459 static struct event_constraint * 3460 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3461 struct perf_event *event) 3462 { 3463 struct event_constraint *c; 3464 3465 c = intel_get_event_constraints(cpuc, idx, event); 3466 3467 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3468 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3469 if (c->idxmsk64 & (1U << 2)) 3470 return &counter2_constraint; 3471 return &emptyconstraint; 3472 } 3473 3474 return c; 3475 } 3476 3477 static struct event_constraint * 3478 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3479 struct perf_event *event) 3480 { 3481 /* 3482 * Fixed counter 0 has less skid. 3483 * Force instruction:ppp in Fixed counter 0 3484 */ 3485 if ((event->attr.precise_ip == 3) && 3486 constraint_match(&fixed0_constraint, event->hw.config)) 3487 return &fixed0_constraint; 3488 3489 return hsw_get_event_constraints(cpuc, idx, event); 3490 } 3491 3492 static struct event_constraint * 3493 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3494 struct perf_event *event) 3495 { 3496 struct event_constraint *c; 3497 3498 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3499 if (event->attr.precise_ip == 3) 3500 return &counter0_constraint; 3501 3502 c = intel_get_event_constraints(cpuc, idx, event); 3503 3504 return c; 3505 } 3506 3507 static struct event_constraint * 3508 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3509 struct perf_event *event) 3510 { 3511 struct event_constraint *c; 3512 3513 /* 3514 * :ppp means to do reduced skid PEBS, 3515 * which is available on PMC0 and fixed counter 0. 3516 */ 3517 if (event->attr.precise_ip == 3) { 3518 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 3519 if (constraint_match(&fixed0_constraint, event->hw.config)) 3520 return &fixed0_counter0_constraint; 3521 3522 return &counter0_constraint; 3523 } 3524 3525 c = intel_get_event_constraints(cpuc, idx, event); 3526 3527 return c; 3528 } 3529 3530 static bool allow_tsx_force_abort = true; 3531 3532 static struct event_constraint * 3533 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3534 struct perf_event *event) 3535 { 3536 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 3537 3538 /* 3539 * Without TFA we must not use PMC3. 3540 */ 3541 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 3542 c = dyn_constraint(cpuc, c, idx); 3543 c->idxmsk64 &= ~(1ULL << 3); 3544 c->weight--; 3545 } 3546 3547 return c; 3548 } 3549 3550 /* 3551 * Broadwell: 3552 * 3553 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3554 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3555 * the two to enforce a minimum period of 128 (the smallest value that has bits 3556 * 0-5 cleared and >= 100). 3557 * 3558 * Because of how the code in x86_perf_event_set_period() works, the truncation 3559 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3560 * to make up for the 'lost' events due to carrying the 'error' in period_left. 3561 * 3562 * Therefore the effective (average) period matches the requested period, 3563 * despite coarser hardware granularity. 3564 */ 3565 static u64 bdw_limit_period(struct perf_event *event, u64 left) 3566 { 3567 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3568 X86_CONFIG(.event=0xc0, .umask=0x01)) { 3569 if (left < 128) 3570 left = 128; 3571 left &= ~0x3fULL; 3572 } 3573 return left; 3574 } 3575 3576 PMU_FORMAT_ATTR(event, "config:0-7" ); 3577 PMU_FORMAT_ATTR(umask, "config:8-15" ); 3578 PMU_FORMAT_ATTR(edge, "config:18" ); 3579 PMU_FORMAT_ATTR(pc, "config:19" ); 3580 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3581 PMU_FORMAT_ATTR(inv, "config:23" ); 3582 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3583 PMU_FORMAT_ATTR(in_tx, "config:32"); 3584 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3585 3586 static struct attribute *intel_arch_formats_attr[] = { 3587 &format_attr_event.attr, 3588 &format_attr_umask.attr, 3589 &format_attr_edge.attr, 3590 &format_attr_pc.attr, 3591 &format_attr_inv.attr, 3592 &format_attr_cmask.attr, 3593 NULL, 3594 }; 3595 3596 ssize_t intel_event_sysfs_show(char *page, u64 config) 3597 { 3598 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3599 3600 return x86_event_sysfs_show(page, config, event); 3601 } 3602 3603 static struct intel_shared_regs *allocate_shared_regs(int cpu) 3604 { 3605 struct intel_shared_regs *regs; 3606 int i; 3607 3608 regs = kzalloc_node(sizeof(struct intel_shared_regs), 3609 GFP_KERNEL, cpu_to_node(cpu)); 3610 if (regs) { 3611 /* 3612 * initialize the locks to keep lockdep happy 3613 */ 3614 for (i = 0; i < EXTRA_REG_MAX; i++) 3615 raw_spin_lock_init(®s->regs[i].lock); 3616 3617 regs->core_id = -1; 3618 } 3619 return regs; 3620 } 3621 3622 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3623 { 3624 struct intel_excl_cntrs *c; 3625 3626 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3627 GFP_KERNEL, cpu_to_node(cpu)); 3628 if (c) { 3629 raw_spin_lock_init(&c->lock); 3630 c->core_id = -1; 3631 } 3632 return c; 3633 } 3634 3635 3636 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 3637 { 3638 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 3639 3640 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 3641 cpuc->shared_regs = allocate_shared_regs(cpu); 3642 if (!cpuc->shared_regs) 3643 goto err; 3644 } 3645 3646 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 3647 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 3648 3649 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 3650 if (!cpuc->constraint_list) 3651 goto err_shared_regs; 3652 } 3653 3654 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3655 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 3656 if (!cpuc->excl_cntrs) 3657 goto err_constraint_list; 3658 3659 cpuc->excl_thread_id = 0; 3660 } 3661 3662 return 0; 3663 3664 err_constraint_list: 3665 kfree(cpuc->constraint_list); 3666 cpuc->constraint_list = NULL; 3667 3668 err_shared_regs: 3669 kfree(cpuc->shared_regs); 3670 cpuc->shared_regs = NULL; 3671 3672 err: 3673 return -ENOMEM; 3674 } 3675 3676 static int intel_pmu_cpu_prepare(int cpu) 3677 { 3678 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 3679 } 3680 3681 static void flip_smm_bit(void *data) 3682 { 3683 unsigned long set = *(unsigned long *)data; 3684 3685 if (set > 0) { 3686 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 3687 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 3688 } else { 3689 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 3690 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 3691 } 3692 } 3693 3694 static void intel_pmu_cpu_starting(int cpu) 3695 { 3696 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3697 int core_id = topology_core_id(cpu); 3698 int i; 3699 3700 init_debug_store_on_cpu(cpu); 3701 /* 3702 * Deal with CPUs that don't clear their LBRs on power-up. 3703 */ 3704 intel_pmu_lbr_reset(); 3705 3706 cpuc->lbr_sel = NULL; 3707 3708 if (x86_pmu.flags & PMU_FL_TFA) { 3709 WARN_ON_ONCE(cpuc->tfa_shadow); 3710 cpuc->tfa_shadow = ~0ULL; 3711 intel_set_tfa(cpuc, false); 3712 } 3713 3714 if (x86_pmu.version > 1) 3715 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 3716 3717 if (x86_pmu.counter_freezing) 3718 enable_counter_freeze(); 3719 3720 if (!cpuc->shared_regs) 3721 return; 3722 3723 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 3724 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3725 struct intel_shared_regs *pc; 3726 3727 pc = per_cpu(cpu_hw_events, i).shared_regs; 3728 if (pc && pc->core_id == core_id) { 3729 cpuc->kfree_on_online[0] = cpuc->shared_regs; 3730 cpuc->shared_regs = pc; 3731 break; 3732 } 3733 } 3734 cpuc->shared_regs->core_id = core_id; 3735 cpuc->shared_regs->refcnt++; 3736 } 3737 3738 if (x86_pmu.lbr_sel_map) 3739 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 3740 3741 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3742 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3743 struct cpu_hw_events *sibling; 3744 struct intel_excl_cntrs *c; 3745 3746 sibling = &per_cpu(cpu_hw_events, i); 3747 c = sibling->excl_cntrs; 3748 if (c && c->core_id == core_id) { 3749 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 3750 cpuc->excl_cntrs = c; 3751 if (!sibling->excl_thread_id) 3752 cpuc->excl_thread_id = 1; 3753 break; 3754 } 3755 } 3756 cpuc->excl_cntrs->core_id = core_id; 3757 cpuc->excl_cntrs->refcnt++; 3758 } 3759 } 3760 3761 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 3762 { 3763 struct intel_excl_cntrs *c; 3764 3765 c = cpuc->excl_cntrs; 3766 if (c) { 3767 if (c->core_id == -1 || --c->refcnt == 0) 3768 kfree(c); 3769 cpuc->excl_cntrs = NULL; 3770 } 3771 3772 kfree(cpuc->constraint_list); 3773 cpuc->constraint_list = NULL; 3774 } 3775 3776 static void intel_pmu_cpu_dying(int cpu) 3777 { 3778 fini_debug_store_on_cpu(cpu); 3779 3780 if (x86_pmu.counter_freezing) 3781 disable_counter_freeze(); 3782 } 3783 3784 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 3785 { 3786 struct intel_shared_regs *pc; 3787 3788 pc = cpuc->shared_regs; 3789 if (pc) { 3790 if (pc->core_id == -1 || --pc->refcnt == 0) 3791 kfree(pc); 3792 cpuc->shared_regs = NULL; 3793 } 3794 3795 free_excl_cntrs(cpuc); 3796 } 3797 3798 static void intel_pmu_cpu_dead(int cpu) 3799 { 3800 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu)); 3801 } 3802 3803 static void intel_pmu_sched_task(struct perf_event_context *ctx, 3804 bool sched_in) 3805 { 3806 intel_pmu_pebs_sched_task(ctx, sched_in); 3807 intel_pmu_lbr_sched_task(ctx, sched_in); 3808 } 3809 3810 static int intel_pmu_check_period(struct perf_event *event, u64 value) 3811 { 3812 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 3813 } 3814 3815 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 3816 3817 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 3818 3819 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 3820 3821 static struct attribute *intel_arch3_formats_attr[] = { 3822 &format_attr_event.attr, 3823 &format_attr_umask.attr, 3824 &format_attr_edge.attr, 3825 &format_attr_pc.attr, 3826 &format_attr_any.attr, 3827 &format_attr_inv.attr, 3828 &format_attr_cmask.attr, 3829 NULL, 3830 }; 3831 3832 static struct attribute *hsw_format_attr[] = { 3833 &format_attr_in_tx.attr, 3834 &format_attr_in_tx_cp.attr, 3835 &format_attr_offcore_rsp.attr, 3836 &format_attr_ldlat.attr, 3837 NULL 3838 }; 3839 3840 static struct attribute *nhm_format_attr[] = { 3841 &format_attr_offcore_rsp.attr, 3842 &format_attr_ldlat.attr, 3843 NULL 3844 }; 3845 3846 static struct attribute *slm_format_attr[] = { 3847 &format_attr_offcore_rsp.attr, 3848 NULL 3849 }; 3850 3851 static struct attribute *skl_format_attr[] = { 3852 &format_attr_frontend.attr, 3853 NULL, 3854 }; 3855 3856 static __initconst const struct x86_pmu core_pmu = { 3857 .name = "core", 3858 .handle_irq = x86_pmu_handle_irq, 3859 .disable_all = x86_pmu_disable_all, 3860 .enable_all = core_pmu_enable_all, 3861 .enable = core_pmu_enable_event, 3862 .disable = x86_pmu_disable_event, 3863 .hw_config = core_pmu_hw_config, 3864 .schedule_events = x86_schedule_events, 3865 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3866 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3867 .event_map = intel_pmu_event_map, 3868 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3869 .apic = 1, 3870 .large_pebs_flags = LARGE_PEBS_FLAGS, 3871 3872 /* 3873 * Intel PMCs cannot be accessed sanely above 32-bit width, 3874 * so we install an artificial 1<<31 period regardless of 3875 * the generic event period: 3876 */ 3877 .max_period = (1ULL<<31) - 1, 3878 .get_event_constraints = intel_get_event_constraints, 3879 .put_event_constraints = intel_put_event_constraints, 3880 .event_constraints = intel_core_event_constraints, 3881 .guest_get_msrs = core_guest_get_msrs, 3882 .format_attrs = intel_arch_formats_attr, 3883 .events_sysfs_show = intel_event_sysfs_show, 3884 3885 /* 3886 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 3887 * together with PMU version 1 and thus be using core_pmu with 3888 * shared_regs. We need following callbacks here to allocate 3889 * it properly. 3890 */ 3891 .cpu_prepare = intel_pmu_cpu_prepare, 3892 .cpu_starting = intel_pmu_cpu_starting, 3893 .cpu_dying = intel_pmu_cpu_dying, 3894 .cpu_dead = intel_pmu_cpu_dead, 3895 3896 .check_period = intel_pmu_check_period, 3897 }; 3898 3899 static struct attribute *intel_pmu_attrs[]; 3900 3901 static __initconst const struct x86_pmu intel_pmu = { 3902 .name = "Intel", 3903 .handle_irq = intel_pmu_handle_irq, 3904 .disable_all = intel_pmu_disable_all, 3905 .enable_all = intel_pmu_enable_all, 3906 .enable = intel_pmu_enable_event, 3907 .disable = intel_pmu_disable_event, 3908 .add = intel_pmu_add_event, 3909 .del = intel_pmu_del_event, 3910 .read = intel_pmu_read_event, 3911 .hw_config = intel_pmu_hw_config, 3912 .schedule_events = x86_schedule_events, 3913 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3914 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3915 .event_map = intel_pmu_event_map, 3916 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3917 .apic = 1, 3918 .large_pebs_flags = LARGE_PEBS_FLAGS, 3919 /* 3920 * Intel PMCs cannot be accessed sanely above 32 bit width, 3921 * so we install an artificial 1<<31 period regardless of 3922 * the generic event period: 3923 */ 3924 .max_period = (1ULL << 31) - 1, 3925 .get_event_constraints = intel_get_event_constraints, 3926 .put_event_constraints = intel_put_event_constraints, 3927 .pebs_aliases = intel_pebs_aliases_core2, 3928 3929 .format_attrs = intel_arch3_formats_attr, 3930 .events_sysfs_show = intel_event_sysfs_show, 3931 3932 .attrs = intel_pmu_attrs, 3933 3934 .cpu_prepare = intel_pmu_cpu_prepare, 3935 .cpu_starting = intel_pmu_cpu_starting, 3936 .cpu_dying = intel_pmu_cpu_dying, 3937 .cpu_dead = intel_pmu_cpu_dead, 3938 3939 .guest_get_msrs = intel_guest_get_msrs, 3940 .sched_task = intel_pmu_sched_task, 3941 3942 .check_period = intel_pmu_check_period, 3943 }; 3944 3945 static __init void intel_clovertown_quirk(void) 3946 { 3947 /* 3948 * PEBS is unreliable due to: 3949 * 3950 * AJ67 - PEBS may experience CPL leaks 3951 * AJ68 - PEBS PMI may be delayed by one event 3952 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 3953 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 3954 * 3955 * AJ67 could be worked around by restricting the OS/USR flags. 3956 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 3957 * 3958 * AJ106 could possibly be worked around by not allowing LBR 3959 * usage from PEBS, including the fixup. 3960 * AJ68 could possibly be worked around by always programming 3961 * a pebs_event_reset[0] value and coping with the lost events. 3962 * 3963 * But taken together it might just make sense to not enable PEBS on 3964 * these chips. 3965 */ 3966 pr_warn("PEBS disabled due to CPU errata\n"); 3967 x86_pmu.pebs = 0; 3968 x86_pmu.pebs_constraints = NULL; 3969 } 3970 3971 static const struct x86_cpu_desc isolation_ucodes[] = { 3972 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_CORE, 3, 0x0000001f), 3973 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_ULT, 1, 0x0000001e), 3974 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_GT3E, 1, 0x00000015), 3975 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 3976 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 3977 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_CORE, 4, 0x00000023), 3978 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_GT3E, 1, 0x00000014), 3979 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 2, 0x00000010), 3980 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 3, 0x07000009), 3981 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 4, 0x0f000009), 3982 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 5, 0x0e000002), 3983 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014), 3984 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 3985 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 3986 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_MOBILE, 3, 0x0000007c), 3987 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_DESKTOP, 3, 0x0000007c), 3988 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 9, 0x0000004e), 3989 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 9, 0x0000004e), 3990 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 10, 0x0000004e), 3991 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 11, 0x0000004e), 3992 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 12, 0x0000004e), 3993 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 10, 0x0000004e), 3994 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 11, 0x0000004e), 3995 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 12, 0x0000004e), 3996 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 13, 0x0000004e), 3997 {} 3998 }; 3999 4000 static void intel_check_pebs_isolation(void) 4001 { 4002 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4003 } 4004 4005 static __init void intel_pebs_isolation_quirk(void) 4006 { 4007 WARN_ON_ONCE(x86_pmu.check_microcode); 4008 x86_pmu.check_microcode = intel_check_pebs_isolation; 4009 intel_check_pebs_isolation(); 4010 } 4011 4012 static const struct x86_cpu_desc pebs_ucodes[] = { 4013 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4014 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4015 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4016 {} 4017 }; 4018 4019 static bool intel_snb_pebs_broken(void) 4020 { 4021 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4022 } 4023 4024 static void intel_snb_check_microcode(void) 4025 { 4026 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4027 return; 4028 4029 /* 4030 * Serialized by the microcode lock.. 4031 */ 4032 if (x86_pmu.pebs_broken) { 4033 pr_info("PEBS enabled due to microcode update\n"); 4034 x86_pmu.pebs_broken = 0; 4035 } else { 4036 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4037 x86_pmu.pebs_broken = 1; 4038 } 4039 } 4040 4041 static bool is_lbr_from(unsigned long msr) 4042 { 4043 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4044 4045 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4046 } 4047 4048 /* 4049 * Under certain circumstances, access certain MSR may cause #GP. 4050 * The function tests if the input MSR can be safely accessed. 4051 */ 4052 static bool check_msr(unsigned long msr, u64 mask) 4053 { 4054 u64 val_old, val_new, val_tmp; 4055 4056 /* 4057 * Read the current value, change it and read it back to see if it 4058 * matches, this is needed to detect certain hardware emulators 4059 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4060 */ 4061 if (rdmsrl_safe(msr, &val_old)) 4062 return false; 4063 4064 /* 4065 * Only change the bits which can be updated by wrmsrl. 4066 */ 4067 val_tmp = val_old ^ mask; 4068 4069 if (is_lbr_from(msr)) 4070 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4071 4072 if (wrmsrl_safe(msr, val_tmp) || 4073 rdmsrl_safe(msr, &val_new)) 4074 return false; 4075 4076 /* 4077 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4078 * should equal rdmsrl()'s even with the quirk. 4079 */ 4080 if (val_new != val_tmp) 4081 return false; 4082 4083 if (is_lbr_from(msr)) 4084 val_old = lbr_from_signext_quirk_wr(val_old); 4085 4086 /* Here it's sure that the MSR can be safely accessed. 4087 * Restore the old value and return. 4088 */ 4089 wrmsrl(msr, val_old); 4090 4091 return true; 4092 } 4093 4094 static __init void intel_sandybridge_quirk(void) 4095 { 4096 x86_pmu.check_microcode = intel_snb_check_microcode; 4097 cpus_read_lock(); 4098 intel_snb_check_microcode(); 4099 cpus_read_unlock(); 4100 } 4101 4102 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4103 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4104 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4105 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4106 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4107 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4108 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4109 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4110 }; 4111 4112 static __init void intel_arch_events_quirk(void) 4113 { 4114 int bit; 4115 4116 /* disable event that reported as not presend by cpuid */ 4117 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4118 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4119 pr_warn("CPUID marked event: \'%s\' unavailable\n", 4120 intel_arch_events_map[bit].name); 4121 } 4122 } 4123 4124 static __init void intel_nehalem_quirk(void) 4125 { 4126 union cpuid10_ebx ebx; 4127 4128 ebx.full = x86_pmu.events_maskl; 4129 if (ebx.split.no_branch_misses_retired) { 4130 /* 4131 * Erratum AAJ80 detected, we work it around by using 4132 * the BR_MISP_EXEC.ANY event. This will over-count 4133 * branch-misses, but it's still much better than the 4134 * architectural event which is often completely bogus: 4135 */ 4136 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4137 ebx.split.no_branch_misses_retired = 0; 4138 x86_pmu.events_maskl = ebx.full; 4139 pr_info("CPU erratum AAJ80 worked around\n"); 4140 } 4141 } 4142 4143 static const struct x86_cpu_desc counter_freezing_ucodes[] = { 4144 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e), 4145 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e), 4146 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008), 4147 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_X, 1, 0x00000028), 4148 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028), 4149 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006), 4150 {} 4151 }; 4152 4153 static bool intel_counter_freezing_broken(void) 4154 { 4155 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes); 4156 } 4157 4158 static __init void intel_counter_freezing_quirk(void) 4159 { 4160 /* Check if it's already disabled */ 4161 if (disable_counter_freezing) 4162 return; 4163 4164 /* 4165 * If the system starts with the wrong ucode, leave the 4166 * counter-freezing feature permanently disabled. 4167 */ 4168 if (intel_counter_freezing_broken()) { 4169 pr_info("PMU counter freezing disabled due to CPU errata," 4170 "please upgrade microcode\n"); 4171 x86_pmu.counter_freezing = false; 4172 x86_pmu.handle_irq = intel_pmu_handle_irq; 4173 } 4174 } 4175 4176 /* 4177 * enable software workaround for errata: 4178 * SNB: BJ122 4179 * IVB: BV98 4180 * HSW: HSD29 4181 * 4182 * Only needed when HT is enabled. However detecting 4183 * if HT is enabled is difficult (model specific). So instead, 4184 * we enable the workaround in the early boot, and verify if 4185 * it is needed in a later initcall phase once we have valid 4186 * topology information to check if HT is actually enabled 4187 */ 4188 static __init void intel_ht_bug(void) 4189 { 4190 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4191 4192 x86_pmu.start_scheduling = intel_start_scheduling; 4193 x86_pmu.commit_scheduling = intel_commit_scheduling; 4194 x86_pmu.stop_scheduling = intel_stop_scheduling; 4195 } 4196 4197 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4198 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4199 4200 /* Haswell special events */ 4201 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4202 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4203 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4204 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4205 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4206 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4207 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4208 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4209 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4210 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4211 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4212 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4213 4214 static struct attribute *hsw_events_attrs[] = { 4215 EVENT_PTR(td_slots_issued), 4216 EVENT_PTR(td_slots_retired), 4217 EVENT_PTR(td_fetch_bubbles), 4218 EVENT_PTR(td_total_slots), 4219 EVENT_PTR(td_total_slots_scale), 4220 EVENT_PTR(td_recovery_bubbles), 4221 EVENT_PTR(td_recovery_bubbles_scale), 4222 NULL 4223 }; 4224 4225 static struct attribute *hsw_mem_events_attrs[] = { 4226 EVENT_PTR(mem_ld_hsw), 4227 EVENT_PTR(mem_st_hsw), 4228 NULL, 4229 }; 4230 4231 static struct attribute *hsw_tsx_events_attrs[] = { 4232 EVENT_PTR(tx_start), 4233 EVENT_PTR(tx_commit), 4234 EVENT_PTR(tx_abort), 4235 EVENT_PTR(tx_capacity), 4236 EVENT_PTR(tx_conflict), 4237 EVENT_PTR(el_start), 4238 EVENT_PTR(el_commit), 4239 EVENT_PTR(el_abort), 4240 EVENT_PTR(el_capacity), 4241 EVENT_PTR(el_conflict), 4242 EVENT_PTR(cycles_t), 4243 EVENT_PTR(cycles_ct), 4244 NULL 4245 }; 4246 4247 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 4248 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 4249 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 4250 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 4251 4252 static struct attribute *icl_events_attrs[] = { 4253 EVENT_PTR(mem_ld_hsw), 4254 EVENT_PTR(mem_st_hsw), 4255 NULL, 4256 }; 4257 4258 static struct attribute *icl_tsx_events_attrs[] = { 4259 EVENT_PTR(tx_start), 4260 EVENT_PTR(tx_abort), 4261 EVENT_PTR(tx_commit), 4262 EVENT_PTR(tx_capacity_read), 4263 EVENT_PTR(tx_capacity_write), 4264 EVENT_PTR(tx_conflict), 4265 EVENT_PTR(el_start), 4266 EVENT_PTR(el_abort), 4267 EVENT_PTR(el_commit), 4268 EVENT_PTR(el_capacity_read), 4269 EVENT_PTR(el_capacity_write), 4270 EVENT_PTR(el_conflict), 4271 EVENT_PTR(cycles_t), 4272 EVENT_PTR(cycles_ct), 4273 NULL, 4274 }; 4275 4276 static __init struct attribute **get_icl_events_attrs(void) 4277 { 4278 return boot_cpu_has(X86_FEATURE_RTM) ? 4279 merge_attr(icl_events_attrs, icl_tsx_events_attrs) : 4280 icl_events_attrs; 4281 } 4282 4283 static ssize_t freeze_on_smi_show(struct device *cdev, 4284 struct device_attribute *attr, 4285 char *buf) 4286 { 4287 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 4288 } 4289 4290 static DEFINE_MUTEX(freeze_on_smi_mutex); 4291 4292 static ssize_t freeze_on_smi_store(struct device *cdev, 4293 struct device_attribute *attr, 4294 const char *buf, size_t count) 4295 { 4296 unsigned long val; 4297 ssize_t ret; 4298 4299 ret = kstrtoul(buf, 0, &val); 4300 if (ret) 4301 return ret; 4302 4303 if (val > 1) 4304 return -EINVAL; 4305 4306 mutex_lock(&freeze_on_smi_mutex); 4307 4308 if (x86_pmu.attr_freeze_on_smi == val) 4309 goto done; 4310 4311 x86_pmu.attr_freeze_on_smi = val; 4312 4313 get_online_cpus(); 4314 on_each_cpu(flip_smm_bit, &val, 1); 4315 put_online_cpus(); 4316 done: 4317 mutex_unlock(&freeze_on_smi_mutex); 4318 4319 return count; 4320 } 4321 4322 static void update_tfa_sched(void *ignored) 4323 { 4324 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4325 4326 /* 4327 * check if PMC3 is used 4328 * and if so force schedule out for all event types all contexts 4329 */ 4330 if (test_bit(3, cpuc->active_mask)) 4331 perf_pmu_resched(x86_get_pmu()); 4332 } 4333 4334 static ssize_t show_sysctl_tfa(struct device *cdev, 4335 struct device_attribute *attr, 4336 char *buf) 4337 { 4338 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 4339 } 4340 4341 static ssize_t set_sysctl_tfa(struct device *cdev, 4342 struct device_attribute *attr, 4343 const char *buf, size_t count) 4344 { 4345 bool val; 4346 ssize_t ret; 4347 4348 ret = kstrtobool(buf, &val); 4349 if (ret) 4350 return ret; 4351 4352 /* no change */ 4353 if (val == allow_tsx_force_abort) 4354 return count; 4355 4356 allow_tsx_force_abort = val; 4357 4358 get_online_cpus(); 4359 on_each_cpu(update_tfa_sched, NULL, 1); 4360 put_online_cpus(); 4361 4362 return count; 4363 } 4364 4365 4366 static DEVICE_ATTR_RW(freeze_on_smi); 4367 4368 static ssize_t branches_show(struct device *cdev, 4369 struct device_attribute *attr, 4370 char *buf) 4371 { 4372 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4373 } 4374 4375 static DEVICE_ATTR_RO(branches); 4376 4377 static struct attribute *lbr_attrs[] = { 4378 &dev_attr_branches.attr, 4379 NULL 4380 }; 4381 4382 static char pmu_name_str[30]; 4383 4384 static ssize_t pmu_name_show(struct device *cdev, 4385 struct device_attribute *attr, 4386 char *buf) 4387 { 4388 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4389 } 4390 4391 static DEVICE_ATTR_RO(pmu_name); 4392 4393 static struct attribute *intel_pmu_caps_attrs[] = { 4394 &dev_attr_pmu_name.attr, 4395 NULL 4396 }; 4397 4398 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 4399 show_sysctl_tfa, 4400 set_sysctl_tfa); 4401 4402 static struct attribute *intel_pmu_attrs[] = { 4403 &dev_attr_freeze_on_smi.attr, 4404 NULL, /* &dev_attr_allow_tsx_force_abort.attr.attr */ 4405 NULL, 4406 }; 4407 4408 static __init struct attribute ** 4409 get_events_attrs(struct attribute **base, 4410 struct attribute **mem, 4411 struct attribute **tsx) 4412 { 4413 struct attribute **attrs = base; 4414 struct attribute **old; 4415 4416 if (mem && x86_pmu.pebs) 4417 attrs = merge_attr(attrs, mem); 4418 4419 if (tsx && boot_cpu_has(X86_FEATURE_RTM)) { 4420 old = attrs; 4421 attrs = merge_attr(attrs, tsx); 4422 if (old != base) 4423 kfree(old); 4424 } 4425 4426 return attrs; 4427 } 4428 4429 __init int intel_pmu_init(void) 4430 { 4431 struct attribute **extra_attr = NULL; 4432 struct attribute **mem_attr = NULL; 4433 struct attribute **tsx_attr = NULL; 4434 struct attribute **to_free = NULL; 4435 union cpuid10_edx edx; 4436 union cpuid10_eax eax; 4437 union cpuid10_ebx ebx; 4438 struct event_constraint *c; 4439 unsigned int unused; 4440 struct extra_reg *er; 4441 int version, i; 4442 char *name; 4443 4444 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4445 switch (boot_cpu_data.x86) { 4446 case 0x6: 4447 return p6_pmu_init(); 4448 case 0xb: 4449 return knc_pmu_init(); 4450 case 0xf: 4451 return p4_pmu_init(); 4452 } 4453 return -ENODEV; 4454 } 4455 4456 /* 4457 * Check whether the Architectural PerfMon supports 4458 * Branch Misses Retired hw_event or not. 4459 */ 4460 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4461 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4462 return -ENODEV; 4463 4464 version = eax.split.version_id; 4465 if (version < 2) 4466 x86_pmu = core_pmu; 4467 else 4468 x86_pmu = intel_pmu; 4469 4470 x86_pmu.version = version; 4471 x86_pmu.num_counters = eax.split.num_counters; 4472 x86_pmu.cntval_bits = eax.split.bit_width; 4473 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4474 4475 x86_pmu.events_maskl = ebx.full; 4476 x86_pmu.events_mask_len = eax.split.mask_length; 4477 4478 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4479 4480 /* 4481 * Quirk: v2 perfmon does not report fixed-purpose events, so 4482 * assume at least 3 events, when not running in a hypervisor: 4483 */ 4484 if (version > 1) { 4485 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4486 4487 x86_pmu.num_counters_fixed = 4488 max((int)edx.split.num_counters_fixed, assume); 4489 } 4490 4491 if (version >= 4) 4492 x86_pmu.counter_freezing = !disable_counter_freezing; 4493 4494 if (boot_cpu_has(X86_FEATURE_PDCM)) { 4495 u64 capabilities; 4496 4497 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4498 x86_pmu.intel_cap.capabilities = capabilities; 4499 } 4500 4501 intel_ds_init(); 4502 4503 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 4504 4505 /* 4506 * Install the hw-cache-events table: 4507 */ 4508 switch (boot_cpu_data.x86_model) { 4509 case INTEL_FAM6_CORE_YONAH: 4510 pr_cont("Core events, "); 4511 name = "core"; 4512 break; 4513 4514 case INTEL_FAM6_CORE2_MEROM: 4515 x86_add_quirk(intel_clovertown_quirk); 4516 /* fall through */ 4517 4518 case INTEL_FAM6_CORE2_MEROM_L: 4519 case INTEL_FAM6_CORE2_PENRYN: 4520 case INTEL_FAM6_CORE2_DUNNINGTON: 4521 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 4522 sizeof(hw_cache_event_ids)); 4523 4524 intel_pmu_lbr_init_core(); 4525 4526 x86_pmu.event_constraints = intel_core2_event_constraints; 4527 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 4528 pr_cont("Core2 events, "); 4529 name = "core2"; 4530 break; 4531 4532 case INTEL_FAM6_NEHALEM: 4533 case INTEL_FAM6_NEHALEM_EP: 4534 case INTEL_FAM6_NEHALEM_EX: 4535 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 4536 sizeof(hw_cache_event_ids)); 4537 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4538 sizeof(hw_cache_extra_regs)); 4539 4540 intel_pmu_lbr_init_nhm(); 4541 4542 x86_pmu.event_constraints = intel_nehalem_event_constraints; 4543 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 4544 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4545 x86_pmu.extra_regs = intel_nehalem_extra_regs; 4546 4547 mem_attr = nhm_mem_events_attrs; 4548 4549 /* UOPS_ISSUED.STALLED_CYCLES */ 4550 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4551 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4552 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4553 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4554 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4555 4556 intel_pmu_pebs_data_source_nhm(); 4557 x86_add_quirk(intel_nehalem_quirk); 4558 x86_pmu.pebs_no_tlb = 1; 4559 extra_attr = nhm_format_attr; 4560 4561 pr_cont("Nehalem events, "); 4562 name = "nehalem"; 4563 break; 4564 4565 case INTEL_FAM6_ATOM_BONNELL: 4566 case INTEL_FAM6_ATOM_BONNELL_MID: 4567 case INTEL_FAM6_ATOM_SALTWELL: 4568 case INTEL_FAM6_ATOM_SALTWELL_MID: 4569 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 4570 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 4571 sizeof(hw_cache_event_ids)); 4572 4573 intel_pmu_lbr_init_atom(); 4574 4575 x86_pmu.event_constraints = intel_gen_event_constraints; 4576 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 4577 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 4578 pr_cont("Atom events, "); 4579 name = "bonnell"; 4580 break; 4581 4582 case INTEL_FAM6_ATOM_SILVERMONT: 4583 case INTEL_FAM6_ATOM_SILVERMONT_X: 4584 case INTEL_FAM6_ATOM_SILVERMONT_MID: 4585 case INTEL_FAM6_ATOM_AIRMONT: 4586 case INTEL_FAM6_ATOM_AIRMONT_MID: 4587 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 4588 sizeof(hw_cache_event_ids)); 4589 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 4590 sizeof(hw_cache_extra_regs)); 4591 4592 intel_pmu_lbr_init_slm(); 4593 4594 x86_pmu.event_constraints = intel_slm_event_constraints; 4595 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4596 x86_pmu.extra_regs = intel_slm_extra_regs; 4597 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4598 x86_pmu.cpu_events = slm_events_attrs; 4599 extra_attr = slm_format_attr; 4600 pr_cont("Silvermont events, "); 4601 name = "silvermont"; 4602 break; 4603 4604 case INTEL_FAM6_ATOM_GOLDMONT: 4605 case INTEL_FAM6_ATOM_GOLDMONT_X: 4606 x86_add_quirk(intel_counter_freezing_quirk); 4607 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 4608 sizeof(hw_cache_event_ids)); 4609 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 4610 sizeof(hw_cache_extra_regs)); 4611 4612 intel_pmu_lbr_init_skl(); 4613 4614 x86_pmu.event_constraints = intel_slm_event_constraints; 4615 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 4616 x86_pmu.extra_regs = intel_glm_extra_regs; 4617 /* 4618 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4619 * for precise cycles. 4620 * :pp is identical to :ppp 4621 */ 4622 x86_pmu.pebs_aliases = NULL; 4623 x86_pmu.pebs_prec_dist = true; 4624 x86_pmu.lbr_pt_coexist = true; 4625 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4626 x86_pmu.cpu_events = glm_events_attrs; 4627 extra_attr = slm_format_attr; 4628 pr_cont("Goldmont events, "); 4629 name = "goldmont"; 4630 break; 4631 4632 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4633 x86_add_quirk(intel_counter_freezing_quirk); 4634 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4635 sizeof(hw_cache_event_ids)); 4636 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 4637 sizeof(hw_cache_extra_regs)); 4638 4639 intel_pmu_lbr_init_skl(); 4640 4641 x86_pmu.event_constraints = intel_slm_event_constraints; 4642 x86_pmu.extra_regs = intel_glm_extra_regs; 4643 /* 4644 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4645 * for precise cycles. 4646 */ 4647 x86_pmu.pebs_aliases = NULL; 4648 x86_pmu.pebs_prec_dist = true; 4649 x86_pmu.lbr_pt_coexist = true; 4650 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4651 x86_pmu.flags |= PMU_FL_PEBS_ALL; 4652 x86_pmu.get_event_constraints = glp_get_event_constraints; 4653 x86_pmu.cpu_events = glm_events_attrs; 4654 /* Goldmont Plus has 4-wide pipeline */ 4655 event_attr_td_total_slots_scale_glm.event_str = "4"; 4656 extra_attr = slm_format_attr; 4657 pr_cont("Goldmont plus events, "); 4658 name = "goldmont_plus"; 4659 break; 4660 4661 case INTEL_FAM6_ATOM_TREMONT_X: 4662 x86_pmu.late_ack = true; 4663 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4664 sizeof(hw_cache_event_ids)); 4665 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 4666 sizeof(hw_cache_extra_regs)); 4667 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 4668 4669 intel_pmu_lbr_init_skl(); 4670 4671 x86_pmu.event_constraints = intel_slm_event_constraints; 4672 x86_pmu.extra_regs = intel_tnt_extra_regs; 4673 /* 4674 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4675 * for precise cycles. 4676 */ 4677 x86_pmu.pebs_aliases = NULL; 4678 x86_pmu.pebs_prec_dist = true; 4679 x86_pmu.lbr_pt_coexist = true; 4680 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4681 x86_pmu.get_event_constraints = tnt_get_event_constraints; 4682 extra_attr = slm_format_attr; 4683 pr_cont("Tremont events, "); 4684 name = "Tremont"; 4685 break; 4686 4687 case INTEL_FAM6_WESTMERE: 4688 case INTEL_FAM6_WESTMERE_EP: 4689 case INTEL_FAM6_WESTMERE_EX: 4690 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 4691 sizeof(hw_cache_event_ids)); 4692 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4693 sizeof(hw_cache_extra_regs)); 4694 4695 intel_pmu_lbr_init_nhm(); 4696 4697 x86_pmu.event_constraints = intel_westmere_event_constraints; 4698 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4699 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 4700 x86_pmu.extra_regs = intel_westmere_extra_regs; 4701 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4702 4703 mem_attr = nhm_mem_events_attrs; 4704 4705 /* UOPS_ISSUED.STALLED_CYCLES */ 4706 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4707 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4708 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4709 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4710 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4711 4712 intel_pmu_pebs_data_source_nhm(); 4713 extra_attr = nhm_format_attr; 4714 pr_cont("Westmere events, "); 4715 name = "westmere"; 4716 break; 4717 4718 case INTEL_FAM6_SANDYBRIDGE: 4719 case INTEL_FAM6_SANDYBRIDGE_X: 4720 x86_add_quirk(intel_sandybridge_quirk); 4721 x86_add_quirk(intel_ht_bug); 4722 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4723 sizeof(hw_cache_event_ids)); 4724 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4725 sizeof(hw_cache_extra_regs)); 4726 4727 intel_pmu_lbr_init_snb(); 4728 4729 x86_pmu.event_constraints = intel_snb_event_constraints; 4730 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 4731 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 4732 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 4733 x86_pmu.extra_regs = intel_snbep_extra_regs; 4734 else 4735 x86_pmu.extra_regs = intel_snb_extra_regs; 4736 4737 4738 /* all extra regs are per-cpu when HT is on */ 4739 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4740 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4741 4742 x86_pmu.cpu_events = snb_events_attrs; 4743 mem_attr = snb_mem_events_attrs; 4744 4745 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4746 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4747 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4748 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 4749 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4750 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 4751 4752 extra_attr = nhm_format_attr; 4753 4754 pr_cont("SandyBridge events, "); 4755 name = "sandybridge"; 4756 break; 4757 4758 case INTEL_FAM6_IVYBRIDGE: 4759 case INTEL_FAM6_IVYBRIDGE_X: 4760 x86_add_quirk(intel_ht_bug); 4761 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4762 sizeof(hw_cache_event_ids)); 4763 /* dTLB-load-misses on IVB is different than SNB */ 4764 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 4765 4766 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4767 sizeof(hw_cache_extra_regs)); 4768 4769 intel_pmu_lbr_init_snb(); 4770 4771 x86_pmu.event_constraints = intel_ivb_event_constraints; 4772 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 4773 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4774 x86_pmu.pebs_prec_dist = true; 4775 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 4776 x86_pmu.extra_regs = intel_snbep_extra_regs; 4777 else 4778 x86_pmu.extra_regs = intel_snb_extra_regs; 4779 /* all extra regs are per-cpu when HT is on */ 4780 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4781 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4782 4783 x86_pmu.cpu_events = snb_events_attrs; 4784 mem_attr = snb_mem_events_attrs; 4785 4786 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4787 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4788 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4789 4790 extra_attr = nhm_format_attr; 4791 4792 pr_cont("IvyBridge events, "); 4793 name = "ivybridge"; 4794 break; 4795 4796 4797 case INTEL_FAM6_HASWELL_CORE: 4798 case INTEL_FAM6_HASWELL_X: 4799 case INTEL_FAM6_HASWELL_ULT: 4800 case INTEL_FAM6_HASWELL_GT3E: 4801 x86_add_quirk(intel_ht_bug); 4802 x86_add_quirk(intel_pebs_isolation_quirk); 4803 x86_pmu.late_ack = true; 4804 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4805 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4806 4807 intel_pmu_lbr_init_hsw(); 4808 4809 x86_pmu.event_constraints = intel_hsw_event_constraints; 4810 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 4811 x86_pmu.extra_regs = intel_snbep_extra_regs; 4812 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4813 x86_pmu.pebs_prec_dist = true; 4814 /* all extra regs are per-cpu when HT is on */ 4815 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4816 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4817 4818 x86_pmu.hw_config = hsw_hw_config; 4819 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4820 x86_pmu.cpu_events = hsw_events_attrs; 4821 x86_pmu.lbr_double_abort = true; 4822 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4823 hsw_format_attr : nhm_format_attr; 4824 mem_attr = hsw_mem_events_attrs; 4825 tsx_attr = hsw_tsx_events_attrs; 4826 pr_cont("Haswell events, "); 4827 name = "haswell"; 4828 break; 4829 4830 case INTEL_FAM6_BROADWELL_CORE: 4831 case INTEL_FAM6_BROADWELL_XEON_D: 4832 case INTEL_FAM6_BROADWELL_GT3E: 4833 case INTEL_FAM6_BROADWELL_X: 4834 x86_add_quirk(intel_pebs_isolation_quirk); 4835 x86_pmu.late_ack = true; 4836 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4837 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4838 4839 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 4840 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 4841 BDW_L3_MISS|HSW_SNOOP_DRAM; 4842 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 4843 HSW_SNOOP_DRAM; 4844 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 4845 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4846 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 4847 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4848 4849 intel_pmu_lbr_init_hsw(); 4850 4851 x86_pmu.event_constraints = intel_bdw_event_constraints; 4852 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 4853 x86_pmu.extra_regs = intel_snbep_extra_regs; 4854 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4855 x86_pmu.pebs_prec_dist = true; 4856 /* all extra regs are per-cpu when HT is on */ 4857 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4858 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4859 4860 x86_pmu.hw_config = hsw_hw_config; 4861 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4862 x86_pmu.cpu_events = hsw_events_attrs; 4863 x86_pmu.limit_period = bdw_limit_period; 4864 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4865 hsw_format_attr : nhm_format_attr; 4866 mem_attr = hsw_mem_events_attrs; 4867 tsx_attr = hsw_tsx_events_attrs; 4868 pr_cont("Broadwell events, "); 4869 name = "broadwell"; 4870 break; 4871 4872 case INTEL_FAM6_XEON_PHI_KNL: 4873 case INTEL_FAM6_XEON_PHI_KNM: 4874 memcpy(hw_cache_event_ids, 4875 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4876 memcpy(hw_cache_extra_regs, 4877 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4878 intel_pmu_lbr_init_knl(); 4879 4880 x86_pmu.event_constraints = intel_slm_event_constraints; 4881 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4882 x86_pmu.extra_regs = intel_knl_extra_regs; 4883 4884 /* all extra regs are per-cpu when HT is on */ 4885 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4886 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4887 extra_attr = slm_format_attr; 4888 pr_cont("Knights Landing/Mill events, "); 4889 name = "knights-landing"; 4890 break; 4891 4892 case INTEL_FAM6_SKYLAKE_MOBILE: 4893 case INTEL_FAM6_SKYLAKE_DESKTOP: 4894 case INTEL_FAM6_SKYLAKE_X: 4895 case INTEL_FAM6_KABYLAKE_MOBILE: 4896 case INTEL_FAM6_KABYLAKE_DESKTOP: 4897 x86_add_quirk(intel_pebs_isolation_quirk); 4898 x86_pmu.late_ack = true; 4899 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4900 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4901 intel_pmu_lbr_init_skl(); 4902 4903 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 4904 event_attr_td_recovery_bubbles.event_str_noht = 4905 "event=0xd,umask=0x1,cmask=1"; 4906 event_attr_td_recovery_bubbles.event_str_ht = 4907 "event=0xd,umask=0x1,cmask=1,any=1"; 4908 4909 x86_pmu.event_constraints = intel_skl_event_constraints; 4910 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 4911 x86_pmu.extra_regs = intel_skl_extra_regs; 4912 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 4913 x86_pmu.pebs_prec_dist = true; 4914 /* all extra regs are per-cpu when HT is on */ 4915 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4916 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4917 4918 x86_pmu.hw_config = hsw_hw_config; 4919 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4920 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4921 hsw_format_attr : nhm_format_attr; 4922 extra_attr = merge_attr(extra_attr, skl_format_attr); 4923 to_free = extra_attr; 4924 x86_pmu.cpu_events = hsw_events_attrs; 4925 mem_attr = hsw_mem_events_attrs; 4926 tsx_attr = hsw_tsx_events_attrs; 4927 intel_pmu_pebs_data_source_skl( 4928 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X); 4929 4930 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 4931 x86_pmu.flags |= PMU_FL_TFA; 4932 x86_pmu.get_event_constraints = tfa_get_event_constraints; 4933 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 4934 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 4935 intel_pmu_attrs[1] = &dev_attr_allow_tsx_force_abort.attr; 4936 } 4937 4938 pr_cont("Skylake events, "); 4939 name = "skylake"; 4940 break; 4941 4942 case INTEL_FAM6_ICELAKE_MOBILE: 4943 x86_pmu.late_ack = true; 4944 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4945 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4946 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 4947 intel_pmu_lbr_init_skl(); 4948 4949 x86_pmu.event_constraints = intel_icl_event_constraints; 4950 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 4951 x86_pmu.extra_regs = intel_icl_extra_regs; 4952 x86_pmu.pebs_aliases = NULL; 4953 x86_pmu.pebs_prec_dist = true; 4954 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4955 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4956 4957 x86_pmu.hw_config = hsw_hw_config; 4958 x86_pmu.get_event_constraints = icl_get_event_constraints; 4959 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4960 hsw_format_attr : nhm_format_attr; 4961 extra_attr = merge_attr(extra_attr, skl_format_attr); 4962 x86_pmu.cpu_events = get_icl_events_attrs(); 4963 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02); 4964 x86_pmu.lbr_pt_coexist = true; 4965 intel_pmu_pebs_data_source_skl(false); 4966 pr_cont("Icelake events, "); 4967 name = "icelake"; 4968 break; 4969 4970 default: 4971 switch (x86_pmu.version) { 4972 case 1: 4973 x86_pmu.event_constraints = intel_v1_event_constraints; 4974 pr_cont("generic architected perfmon v1, "); 4975 name = "generic_arch_v1"; 4976 break; 4977 default: 4978 /* 4979 * default constraints for v2 and up 4980 */ 4981 x86_pmu.event_constraints = intel_gen_event_constraints; 4982 pr_cont("generic architected perfmon, "); 4983 name = "generic_arch_v2+"; 4984 break; 4985 } 4986 } 4987 4988 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 4989 4990 if (version >= 2 && extra_attr) { 4991 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, 4992 extra_attr); 4993 WARN_ON(!x86_pmu.format_attrs); 4994 } 4995 4996 x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events, 4997 mem_attr, tsx_attr); 4998 4999 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 5000 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5001 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 5002 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 5003 } 5004 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 5005 5006 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5007 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5008 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 5009 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 5010 } 5011 5012 x86_pmu.intel_ctrl |= 5013 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 5014 5015 if (x86_pmu.event_constraints) { 5016 /* 5017 * event on fixed counter2 (REF_CYCLES) only works on this 5018 * counter, so do not extend mask to generic counters 5019 */ 5020 for_each_event_constraint(c, x86_pmu.event_constraints) { 5021 if (c->cmask == FIXED_EVENT_FLAGS 5022 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 5023 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 5024 } 5025 c->idxmsk64 &= 5026 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 5027 c->weight = hweight64(c->idxmsk64); 5028 } 5029 } 5030 5031 /* 5032 * Access LBR MSR may cause #GP under certain circumstances. 5033 * E.g. KVM doesn't support LBR MSR 5034 * Check all LBT MSR here. 5035 * Disable LBR access if any LBR MSRs can not be accessed. 5036 */ 5037 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 5038 x86_pmu.lbr_nr = 0; 5039 for (i = 0; i < x86_pmu.lbr_nr; i++) { 5040 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 5041 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 5042 x86_pmu.lbr_nr = 0; 5043 } 5044 5045 x86_pmu.caps_attrs = intel_pmu_caps_attrs; 5046 5047 if (x86_pmu.lbr_nr) { 5048 x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs); 5049 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 5050 } 5051 5052 /* 5053 * Access extra MSR may cause #GP under certain circumstances. 5054 * E.g. KVM doesn't support offcore event 5055 * Check all extra_regs here. 5056 */ 5057 if (x86_pmu.extra_regs) { 5058 for (er = x86_pmu.extra_regs; er->msr; er++) { 5059 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5060 /* Disable LBR select mapping */ 5061 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5062 x86_pmu.lbr_sel_map = NULL; 5063 } 5064 } 5065 5066 /* Support full width counters using alternative MSR range */ 5067 if (x86_pmu.intel_cap.full_width_write) { 5068 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 5069 x86_pmu.perfctr = MSR_IA32_PMC0; 5070 pr_cont("full-width counters, "); 5071 } 5072 5073 /* 5074 * For arch perfmon 4 use counter freezing to avoid 5075 * several MSR accesses in the PMI. 5076 */ 5077 if (x86_pmu.counter_freezing) 5078 x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 5079 5080 kfree(to_free); 5081 return 0; 5082 } 5083 5084 /* 5085 * HT bug: phase 2 init 5086 * Called once we have valid topology information to check 5087 * whether or not HT is enabled 5088 * If HT is off, then we disable the workaround 5089 */ 5090 static __init int fixup_ht_bug(void) 5091 { 5092 int c; 5093 /* 5094 * problem not present on this CPU model, nothing to do 5095 */ 5096 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 5097 return 0; 5098 5099 if (topology_max_smt_threads() > 1) { 5100 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 5101 return 0; 5102 } 5103 5104 cpus_read_lock(); 5105 5106 hardlockup_detector_perf_stop(); 5107 5108 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 5109 5110 x86_pmu.start_scheduling = NULL; 5111 x86_pmu.commit_scheduling = NULL; 5112 x86_pmu.stop_scheduling = NULL; 5113 5114 hardlockup_detector_perf_restart(); 5115 5116 for_each_online_cpu(c) 5117 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 5118 5119 cpus_read_unlock(); 5120 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 5121 return 0; 5122 } 5123 subsys_initcall(fixup_ht_bug) 5124