1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/hardirq.h> 21 #include <asm/intel-family.h> 22 #include <asm/intel_pt.h> 23 #include <asm/apic.h> 24 #include <asm/cpu_device_id.h> 25 26 #include "../perf_event.h" 27 28 /* 29 * Intel PerfMon, used on Core and later. 30 */ 31 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 32 { 33 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 34 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 35 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 36 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 37 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 38 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 39 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 40 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 41 }; 42 43 static struct event_constraint intel_core_event_constraints[] __read_mostly = 44 { 45 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 46 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 47 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 48 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 49 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 50 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 51 EVENT_CONSTRAINT_END 52 }; 53 54 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 55 { 56 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 57 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 58 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 59 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 60 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 61 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 62 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 63 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 64 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 65 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 66 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 67 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 68 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 69 EVENT_CONSTRAINT_END 70 }; 71 72 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 73 { 74 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 75 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 76 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 77 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 78 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 79 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 80 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 81 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 82 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 83 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 84 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 85 EVENT_CONSTRAINT_END 86 }; 87 88 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 89 { 90 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 91 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 92 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 93 EVENT_EXTRA_END 94 }; 95 96 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 97 { 98 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 99 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 100 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 101 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 102 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 103 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 104 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 105 EVENT_CONSTRAINT_END 106 }; 107 108 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 109 { 110 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 111 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 112 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 114 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 116 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 117 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 119 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 120 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 121 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 122 123 /* 124 * When HT is off these events can only run on the bottom 4 counters 125 * When HT is on, they are impacted by the HT bug and require EXCL access 126 */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 131 132 EVENT_CONSTRAINT_END 133 }; 134 135 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 136 { 137 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 138 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 139 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 140 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 141 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 142 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 143 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 145 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 150 151 /* 152 * When HT is off these events can only run on the bottom 4 counters 153 * When HT is on, they are impacted by the HT bug and require EXCL access 154 */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 159 160 EVENT_CONSTRAINT_END 161 }; 162 163 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 164 { 165 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 166 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 167 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 169 EVENT_EXTRA_END 170 }; 171 172 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 173 { 174 EVENT_CONSTRAINT_END 175 }; 176 177 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 178 { 179 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 180 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 181 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 182 EVENT_CONSTRAINT_END 183 }; 184 185 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 186 { 187 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 188 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 189 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 190 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 191 FIXED_EVENT_CONSTRAINT(0x0500, 4), 192 FIXED_EVENT_CONSTRAINT(0x0600, 5), 193 FIXED_EVENT_CONSTRAINT(0x0700, 6), 194 FIXED_EVENT_CONSTRAINT(0x0800, 7), 195 FIXED_EVENT_CONSTRAINT(0x0900, 8), 196 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 197 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 198 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 199 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 200 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 201 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 202 FIXED_EVENT_CONSTRAINT(0x1000, 15), 203 EVENT_CONSTRAINT_END 204 }; 205 206 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 207 { 208 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 210 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 211 EVENT_CONSTRAINT_END 212 }; 213 214 static struct event_constraint intel_skl_event_constraints[] = { 215 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 216 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 217 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 218 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 219 220 /* 221 * when HT is off, these can only run on the bottom 4 counters 222 */ 223 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 224 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 225 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 226 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 227 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 228 229 EVENT_CONSTRAINT_END 230 }; 231 232 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 235 EVENT_EXTRA_END 236 }; 237 238 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 239 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 240 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 241 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 242 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 243 EVENT_EXTRA_END 244 }; 245 246 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 247 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 248 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 249 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 250 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 251 EVENT_EXTRA_END 252 }; 253 254 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 255 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 256 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 257 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 258 /* 259 * Note the low 8 bits eventsel code is not a continuous field, containing 260 * some #GPing bits. These are masked out. 261 */ 262 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 263 EVENT_EXTRA_END 264 }; 265 266 static struct event_constraint intel_icl_event_constraints[] = { 267 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 268 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 269 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 270 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 271 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 272 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 273 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 274 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 275 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 276 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 277 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 278 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 279 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 280 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 281 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 282 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 283 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 284 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 285 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 286 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 287 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 288 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 289 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 290 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 291 EVENT_CONSTRAINT_END 292 }; 293 294 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 295 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 296 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 297 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 298 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 299 EVENT_EXTRA_END 300 }; 301 302 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 303 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 304 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 305 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 306 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 307 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 308 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 309 EVENT_EXTRA_END 310 }; 311 312 static struct event_constraint intel_spr_event_constraints[] = { 313 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 314 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 315 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 316 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 317 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 318 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 319 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 320 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 321 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 322 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 323 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 324 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 325 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 326 327 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 328 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 329 /* 330 * Generally event codes < 0x90 are restricted to counters 0-3. 331 * The 0x2E and 0x3C are exception, which has no restriction. 332 */ 333 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 334 335 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 336 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 337 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 338 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 339 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 340 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 341 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 342 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 343 /* 344 * Generally event codes >= 0x90 are likely to have no restrictions. 345 * The exception are defined as above. 346 */ 347 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 348 349 EVENT_CONSTRAINT_END 350 }; 351 352 static struct extra_reg intel_gnr_extra_regs[] __read_mostly = { 353 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 354 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 355 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 356 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 357 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 358 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 359 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 360 EVENT_EXTRA_END 361 }; 362 363 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 364 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 365 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 366 367 static struct attribute *nhm_mem_events_attrs[] = { 368 EVENT_PTR(mem_ld_nhm), 369 NULL, 370 }; 371 372 /* 373 * topdown events for Intel Core CPUs. 374 * 375 * The events are all in slots, which is a free slot in a 4 wide 376 * pipeline. Some events are already reported in slots, for cycle 377 * events we multiply by the pipeline width (4). 378 * 379 * With Hyper Threading on, topdown metrics are either summed or averaged 380 * between the threads of a core: (count_t0 + count_t1). 381 * 382 * For the average case the metric is always scaled to pipeline width, 383 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 384 */ 385 386 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 387 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 388 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 389 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 390 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 391 "event=0xe,umask=0x1"); /* uops_issued.any */ 392 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 393 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 394 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 395 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 396 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 397 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 398 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 399 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 400 "4", "2"); 401 402 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 403 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 404 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 405 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 406 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 407 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 408 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 409 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 410 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 411 412 static struct attribute *snb_events_attrs[] = { 413 EVENT_PTR(td_slots_issued), 414 EVENT_PTR(td_slots_retired), 415 EVENT_PTR(td_fetch_bubbles), 416 EVENT_PTR(td_total_slots), 417 EVENT_PTR(td_total_slots_scale), 418 EVENT_PTR(td_recovery_bubbles), 419 EVENT_PTR(td_recovery_bubbles_scale), 420 NULL, 421 }; 422 423 static struct attribute *snb_mem_events_attrs[] = { 424 EVENT_PTR(mem_ld_snb), 425 EVENT_PTR(mem_st_snb), 426 NULL, 427 }; 428 429 static struct event_constraint intel_hsw_event_constraints[] = { 430 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 431 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 432 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 433 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 434 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 435 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 436 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 437 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 438 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 439 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 440 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 441 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 442 443 /* 444 * When HT is off these events can only run on the bottom 4 counters 445 * When HT is on, they are impacted by the HT bug and require EXCL access 446 */ 447 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 448 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 449 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 450 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 451 452 EVENT_CONSTRAINT_END 453 }; 454 455 static struct event_constraint intel_bdw_event_constraints[] = { 456 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 457 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 458 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 459 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 460 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 461 /* 462 * when HT is off, these can only run on the bottom 4 counters 463 */ 464 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 465 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 466 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 467 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 468 EVENT_CONSTRAINT_END 469 }; 470 471 static u64 intel_pmu_event_map(int hw_event) 472 { 473 return intel_perfmon_event_map[hw_event]; 474 } 475 476 static __initconst const u64 spr_hw_cache_event_ids 477 [PERF_COUNT_HW_CACHE_MAX] 478 [PERF_COUNT_HW_CACHE_OP_MAX] 479 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 480 { 481 [ C(L1D ) ] = { 482 [ C(OP_READ) ] = { 483 [ C(RESULT_ACCESS) ] = 0x81d0, 484 [ C(RESULT_MISS) ] = 0xe124, 485 }, 486 [ C(OP_WRITE) ] = { 487 [ C(RESULT_ACCESS) ] = 0x82d0, 488 }, 489 }, 490 [ C(L1I ) ] = { 491 [ C(OP_READ) ] = { 492 [ C(RESULT_MISS) ] = 0xe424, 493 }, 494 [ C(OP_WRITE) ] = { 495 [ C(RESULT_ACCESS) ] = -1, 496 [ C(RESULT_MISS) ] = -1, 497 }, 498 }, 499 [ C(LL ) ] = { 500 [ C(OP_READ) ] = { 501 [ C(RESULT_ACCESS) ] = 0x12a, 502 [ C(RESULT_MISS) ] = 0x12a, 503 }, 504 [ C(OP_WRITE) ] = { 505 [ C(RESULT_ACCESS) ] = 0x12a, 506 [ C(RESULT_MISS) ] = 0x12a, 507 }, 508 }, 509 [ C(DTLB) ] = { 510 [ C(OP_READ) ] = { 511 [ C(RESULT_ACCESS) ] = 0x81d0, 512 [ C(RESULT_MISS) ] = 0xe12, 513 }, 514 [ C(OP_WRITE) ] = { 515 [ C(RESULT_ACCESS) ] = 0x82d0, 516 [ C(RESULT_MISS) ] = 0xe13, 517 }, 518 }, 519 [ C(ITLB) ] = { 520 [ C(OP_READ) ] = { 521 [ C(RESULT_ACCESS) ] = -1, 522 [ C(RESULT_MISS) ] = 0xe11, 523 }, 524 [ C(OP_WRITE) ] = { 525 [ C(RESULT_ACCESS) ] = -1, 526 [ C(RESULT_MISS) ] = -1, 527 }, 528 [ C(OP_PREFETCH) ] = { 529 [ C(RESULT_ACCESS) ] = -1, 530 [ C(RESULT_MISS) ] = -1, 531 }, 532 }, 533 [ C(BPU ) ] = { 534 [ C(OP_READ) ] = { 535 [ C(RESULT_ACCESS) ] = 0x4c4, 536 [ C(RESULT_MISS) ] = 0x4c5, 537 }, 538 [ C(OP_WRITE) ] = { 539 [ C(RESULT_ACCESS) ] = -1, 540 [ C(RESULT_MISS) ] = -1, 541 }, 542 [ C(OP_PREFETCH) ] = { 543 [ C(RESULT_ACCESS) ] = -1, 544 [ C(RESULT_MISS) ] = -1, 545 }, 546 }, 547 [ C(NODE) ] = { 548 [ C(OP_READ) ] = { 549 [ C(RESULT_ACCESS) ] = 0x12a, 550 [ C(RESULT_MISS) ] = 0x12a, 551 }, 552 }, 553 }; 554 555 static __initconst const u64 spr_hw_cache_extra_regs 556 [PERF_COUNT_HW_CACHE_MAX] 557 [PERF_COUNT_HW_CACHE_OP_MAX] 558 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 559 { 560 [ C(LL ) ] = { 561 [ C(OP_READ) ] = { 562 [ C(RESULT_ACCESS) ] = 0x10001, 563 [ C(RESULT_MISS) ] = 0x3fbfc00001, 564 }, 565 [ C(OP_WRITE) ] = { 566 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 567 [ C(RESULT_MISS) ] = 0x3f3fc00002, 568 }, 569 }, 570 [ C(NODE) ] = { 571 [ C(OP_READ) ] = { 572 [ C(RESULT_ACCESS) ] = 0x10c000001, 573 [ C(RESULT_MISS) ] = 0x3fb3000001, 574 }, 575 }, 576 }; 577 578 /* 579 * Notes on the events: 580 * - data reads do not include code reads (comparable to earlier tables) 581 * - data counts include speculative execution (except L1 write, dtlb, bpu) 582 * - remote node access includes remote memory, remote cache, remote mmio. 583 * - prefetches are not included in the counts. 584 * - icache miss does not include decoded icache 585 */ 586 587 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 588 #define SKL_DEMAND_RFO BIT_ULL(1) 589 #define SKL_ANY_RESPONSE BIT_ULL(16) 590 #define SKL_SUPPLIER_NONE BIT_ULL(17) 591 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 592 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 593 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 594 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 595 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 596 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 597 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 598 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 599 #define SKL_SPL_HIT BIT_ULL(30) 600 #define SKL_SNOOP_NONE BIT_ULL(31) 601 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 602 #define SKL_SNOOP_MISS BIT_ULL(33) 603 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 604 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 605 #define SKL_SNOOP_HITM BIT_ULL(36) 606 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 607 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 608 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 609 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 610 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 611 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 612 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 613 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 614 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 615 SKL_SNOOP_HITM|SKL_SPL_HIT) 616 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 617 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 618 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 619 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 620 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 621 622 static __initconst const u64 skl_hw_cache_event_ids 623 [PERF_COUNT_HW_CACHE_MAX] 624 [PERF_COUNT_HW_CACHE_OP_MAX] 625 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 626 { 627 [ C(L1D ) ] = { 628 [ C(OP_READ) ] = { 629 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 630 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 631 }, 632 [ C(OP_WRITE) ] = { 633 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 634 [ C(RESULT_MISS) ] = 0x0, 635 }, 636 [ C(OP_PREFETCH) ] = { 637 [ C(RESULT_ACCESS) ] = 0x0, 638 [ C(RESULT_MISS) ] = 0x0, 639 }, 640 }, 641 [ C(L1I ) ] = { 642 [ C(OP_READ) ] = { 643 [ C(RESULT_ACCESS) ] = 0x0, 644 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 645 }, 646 [ C(OP_WRITE) ] = { 647 [ C(RESULT_ACCESS) ] = -1, 648 [ C(RESULT_MISS) ] = -1, 649 }, 650 [ C(OP_PREFETCH) ] = { 651 [ C(RESULT_ACCESS) ] = 0x0, 652 [ C(RESULT_MISS) ] = 0x0, 653 }, 654 }, 655 [ C(LL ) ] = { 656 [ C(OP_READ) ] = { 657 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 658 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 659 }, 660 [ C(OP_WRITE) ] = { 661 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 662 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 663 }, 664 [ C(OP_PREFETCH) ] = { 665 [ C(RESULT_ACCESS) ] = 0x0, 666 [ C(RESULT_MISS) ] = 0x0, 667 }, 668 }, 669 [ C(DTLB) ] = { 670 [ C(OP_READ) ] = { 671 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 672 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 673 }, 674 [ C(OP_WRITE) ] = { 675 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 676 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 677 }, 678 [ C(OP_PREFETCH) ] = { 679 [ C(RESULT_ACCESS) ] = 0x0, 680 [ C(RESULT_MISS) ] = 0x0, 681 }, 682 }, 683 [ C(ITLB) ] = { 684 [ C(OP_READ) ] = { 685 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 686 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 687 }, 688 [ C(OP_WRITE) ] = { 689 [ C(RESULT_ACCESS) ] = -1, 690 [ C(RESULT_MISS) ] = -1, 691 }, 692 [ C(OP_PREFETCH) ] = { 693 [ C(RESULT_ACCESS) ] = -1, 694 [ C(RESULT_MISS) ] = -1, 695 }, 696 }, 697 [ C(BPU ) ] = { 698 [ C(OP_READ) ] = { 699 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 700 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 701 }, 702 [ C(OP_WRITE) ] = { 703 [ C(RESULT_ACCESS) ] = -1, 704 [ C(RESULT_MISS) ] = -1, 705 }, 706 [ C(OP_PREFETCH) ] = { 707 [ C(RESULT_ACCESS) ] = -1, 708 [ C(RESULT_MISS) ] = -1, 709 }, 710 }, 711 [ C(NODE) ] = { 712 [ C(OP_READ) ] = { 713 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 714 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 715 }, 716 [ C(OP_WRITE) ] = { 717 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 718 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 719 }, 720 [ C(OP_PREFETCH) ] = { 721 [ C(RESULT_ACCESS) ] = 0x0, 722 [ C(RESULT_MISS) ] = 0x0, 723 }, 724 }, 725 }; 726 727 static __initconst const u64 skl_hw_cache_extra_regs 728 [PERF_COUNT_HW_CACHE_MAX] 729 [PERF_COUNT_HW_CACHE_OP_MAX] 730 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 731 { 732 [ C(LL ) ] = { 733 [ C(OP_READ) ] = { 734 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 735 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 736 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 737 SKL_L3_MISS|SKL_ANY_SNOOP| 738 SKL_SUPPLIER_NONE, 739 }, 740 [ C(OP_WRITE) ] = { 741 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 742 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 743 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 744 SKL_L3_MISS|SKL_ANY_SNOOP| 745 SKL_SUPPLIER_NONE, 746 }, 747 [ C(OP_PREFETCH) ] = { 748 [ C(RESULT_ACCESS) ] = 0x0, 749 [ C(RESULT_MISS) ] = 0x0, 750 }, 751 }, 752 [ C(NODE) ] = { 753 [ C(OP_READ) ] = { 754 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 755 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 756 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 757 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 758 }, 759 [ C(OP_WRITE) ] = { 760 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 761 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 762 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 763 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 764 }, 765 [ C(OP_PREFETCH) ] = { 766 [ C(RESULT_ACCESS) ] = 0x0, 767 [ C(RESULT_MISS) ] = 0x0, 768 }, 769 }, 770 }; 771 772 #define SNB_DMND_DATA_RD (1ULL << 0) 773 #define SNB_DMND_RFO (1ULL << 1) 774 #define SNB_DMND_IFETCH (1ULL << 2) 775 #define SNB_DMND_WB (1ULL << 3) 776 #define SNB_PF_DATA_RD (1ULL << 4) 777 #define SNB_PF_RFO (1ULL << 5) 778 #define SNB_PF_IFETCH (1ULL << 6) 779 #define SNB_LLC_DATA_RD (1ULL << 7) 780 #define SNB_LLC_RFO (1ULL << 8) 781 #define SNB_LLC_IFETCH (1ULL << 9) 782 #define SNB_BUS_LOCKS (1ULL << 10) 783 #define SNB_STRM_ST (1ULL << 11) 784 #define SNB_OTHER (1ULL << 15) 785 #define SNB_RESP_ANY (1ULL << 16) 786 #define SNB_NO_SUPP (1ULL << 17) 787 #define SNB_LLC_HITM (1ULL << 18) 788 #define SNB_LLC_HITE (1ULL << 19) 789 #define SNB_LLC_HITS (1ULL << 20) 790 #define SNB_LLC_HITF (1ULL << 21) 791 #define SNB_LOCAL (1ULL << 22) 792 #define SNB_REMOTE (0xffULL << 23) 793 #define SNB_SNP_NONE (1ULL << 31) 794 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 795 #define SNB_SNP_MISS (1ULL << 33) 796 #define SNB_NO_FWD (1ULL << 34) 797 #define SNB_SNP_FWD (1ULL << 35) 798 #define SNB_HITM (1ULL << 36) 799 #define SNB_NON_DRAM (1ULL << 37) 800 801 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 802 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 803 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 804 805 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 806 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 807 SNB_HITM) 808 809 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 810 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 811 812 #define SNB_L3_ACCESS SNB_RESP_ANY 813 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 814 815 static __initconst const u64 snb_hw_cache_extra_regs 816 [PERF_COUNT_HW_CACHE_MAX] 817 [PERF_COUNT_HW_CACHE_OP_MAX] 818 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 819 { 820 [ C(LL ) ] = { 821 [ C(OP_READ) ] = { 822 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 823 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 824 }, 825 [ C(OP_WRITE) ] = { 826 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 827 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 828 }, 829 [ C(OP_PREFETCH) ] = { 830 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 831 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 832 }, 833 }, 834 [ C(NODE) ] = { 835 [ C(OP_READ) ] = { 836 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 837 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 838 }, 839 [ C(OP_WRITE) ] = { 840 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 841 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 842 }, 843 [ C(OP_PREFETCH) ] = { 844 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 845 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 846 }, 847 }, 848 }; 849 850 static __initconst const u64 snb_hw_cache_event_ids 851 [PERF_COUNT_HW_CACHE_MAX] 852 [PERF_COUNT_HW_CACHE_OP_MAX] 853 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 854 { 855 [ C(L1D) ] = { 856 [ C(OP_READ) ] = { 857 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 858 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 859 }, 860 [ C(OP_WRITE) ] = { 861 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 862 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 863 }, 864 [ C(OP_PREFETCH) ] = { 865 [ C(RESULT_ACCESS) ] = 0x0, 866 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 867 }, 868 }, 869 [ C(L1I ) ] = { 870 [ C(OP_READ) ] = { 871 [ C(RESULT_ACCESS) ] = 0x0, 872 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 873 }, 874 [ C(OP_WRITE) ] = { 875 [ C(RESULT_ACCESS) ] = -1, 876 [ C(RESULT_MISS) ] = -1, 877 }, 878 [ C(OP_PREFETCH) ] = { 879 [ C(RESULT_ACCESS) ] = 0x0, 880 [ C(RESULT_MISS) ] = 0x0, 881 }, 882 }, 883 [ C(LL ) ] = { 884 [ C(OP_READ) ] = { 885 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 886 [ C(RESULT_ACCESS) ] = 0x01b7, 887 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 888 [ C(RESULT_MISS) ] = 0x01b7, 889 }, 890 [ C(OP_WRITE) ] = { 891 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 892 [ C(RESULT_ACCESS) ] = 0x01b7, 893 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 894 [ C(RESULT_MISS) ] = 0x01b7, 895 }, 896 [ C(OP_PREFETCH) ] = { 897 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 898 [ C(RESULT_ACCESS) ] = 0x01b7, 899 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 900 [ C(RESULT_MISS) ] = 0x01b7, 901 }, 902 }, 903 [ C(DTLB) ] = { 904 [ C(OP_READ) ] = { 905 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 906 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 907 }, 908 [ C(OP_WRITE) ] = { 909 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 910 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 911 }, 912 [ C(OP_PREFETCH) ] = { 913 [ C(RESULT_ACCESS) ] = 0x0, 914 [ C(RESULT_MISS) ] = 0x0, 915 }, 916 }, 917 [ C(ITLB) ] = { 918 [ C(OP_READ) ] = { 919 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 920 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 921 }, 922 [ C(OP_WRITE) ] = { 923 [ C(RESULT_ACCESS) ] = -1, 924 [ C(RESULT_MISS) ] = -1, 925 }, 926 [ C(OP_PREFETCH) ] = { 927 [ C(RESULT_ACCESS) ] = -1, 928 [ C(RESULT_MISS) ] = -1, 929 }, 930 }, 931 [ C(BPU ) ] = { 932 [ C(OP_READ) ] = { 933 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 934 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 935 }, 936 [ C(OP_WRITE) ] = { 937 [ C(RESULT_ACCESS) ] = -1, 938 [ C(RESULT_MISS) ] = -1, 939 }, 940 [ C(OP_PREFETCH) ] = { 941 [ C(RESULT_ACCESS) ] = -1, 942 [ C(RESULT_MISS) ] = -1, 943 }, 944 }, 945 [ C(NODE) ] = { 946 [ C(OP_READ) ] = { 947 [ C(RESULT_ACCESS) ] = 0x01b7, 948 [ C(RESULT_MISS) ] = 0x01b7, 949 }, 950 [ C(OP_WRITE) ] = { 951 [ C(RESULT_ACCESS) ] = 0x01b7, 952 [ C(RESULT_MISS) ] = 0x01b7, 953 }, 954 [ C(OP_PREFETCH) ] = { 955 [ C(RESULT_ACCESS) ] = 0x01b7, 956 [ C(RESULT_MISS) ] = 0x01b7, 957 }, 958 }, 959 960 }; 961 962 /* 963 * Notes on the events: 964 * - data reads do not include code reads (comparable to earlier tables) 965 * - data counts include speculative execution (except L1 write, dtlb, bpu) 966 * - remote node access includes remote memory, remote cache, remote mmio. 967 * - prefetches are not included in the counts because they are not 968 * reliably counted. 969 */ 970 971 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 972 #define HSW_DEMAND_RFO BIT_ULL(1) 973 #define HSW_ANY_RESPONSE BIT_ULL(16) 974 #define HSW_SUPPLIER_NONE BIT_ULL(17) 975 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 976 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 977 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 978 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 979 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 980 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 981 HSW_L3_MISS_REMOTE_HOP2P) 982 #define HSW_SNOOP_NONE BIT_ULL(31) 983 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 984 #define HSW_SNOOP_MISS BIT_ULL(33) 985 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 986 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 987 #define HSW_SNOOP_HITM BIT_ULL(36) 988 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 989 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 990 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 991 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 992 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 993 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 994 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 995 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 996 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 997 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 998 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 999 1000 #define BDW_L3_MISS_LOCAL BIT(26) 1001 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1002 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1003 HSW_L3_MISS_REMOTE_HOP2P) 1004 1005 1006 static __initconst const u64 hsw_hw_cache_event_ids 1007 [PERF_COUNT_HW_CACHE_MAX] 1008 [PERF_COUNT_HW_CACHE_OP_MAX] 1009 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1010 { 1011 [ C(L1D ) ] = { 1012 [ C(OP_READ) ] = { 1013 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1014 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1015 }, 1016 [ C(OP_WRITE) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1018 [ C(RESULT_MISS) ] = 0x0, 1019 }, 1020 [ C(OP_PREFETCH) ] = { 1021 [ C(RESULT_ACCESS) ] = 0x0, 1022 [ C(RESULT_MISS) ] = 0x0, 1023 }, 1024 }, 1025 [ C(L1I ) ] = { 1026 [ C(OP_READ) ] = { 1027 [ C(RESULT_ACCESS) ] = 0x0, 1028 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1029 }, 1030 [ C(OP_WRITE) ] = { 1031 [ C(RESULT_ACCESS) ] = -1, 1032 [ C(RESULT_MISS) ] = -1, 1033 }, 1034 [ C(OP_PREFETCH) ] = { 1035 [ C(RESULT_ACCESS) ] = 0x0, 1036 [ C(RESULT_MISS) ] = 0x0, 1037 }, 1038 }, 1039 [ C(LL ) ] = { 1040 [ C(OP_READ) ] = { 1041 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1042 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1043 }, 1044 [ C(OP_WRITE) ] = { 1045 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1046 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1047 }, 1048 [ C(OP_PREFETCH) ] = { 1049 [ C(RESULT_ACCESS) ] = 0x0, 1050 [ C(RESULT_MISS) ] = 0x0, 1051 }, 1052 }, 1053 [ C(DTLB) ] = { 1054 [ C(OP_READ) ] = { 1055 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1056 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1057 }, 1058 [ C(OP_WRITE) ] = { 1059 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1060 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1061 }, 1062 [ C(OP_PREFETCH) ] = { 1063 [ C(RESULT_ACCESS) ] = 0x0, 1064 [ C(RESULT_MISS) ] = 0x0, 1065 }, 1066 }, 1067 [ C(ITLB) ] = { 1068 [ C(OP_READ) ] = { 1069 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1070 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1071 }, 1072 [ C(OP_WRITE) ] = { 1073 [ C(RESULT_ACCESS) ] = -1, 1074 [ C(RESULT_MISS) ] = -1, 1075 }, 1076 [ C(OP_PREFETCH) ] = { 1077 [ C(RESULT_ACCESS) ] = -1, 1078 [ C(RESULT_MISS) ] = -1, 1079 }, 1080 }, 1081 [ C(BPU ) ] = { 1082 [ C(OP_READ) ] = { 1083 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1084 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1085 }, 1086 [ C(OP_WRITE) ] = { 1087 [ C(RESULT_ACCESS) ] = -1, 1088 [ C(RESULT_MISS) ] = -1, 1089 }, 1090 [ C(OP_PREFETCH) ] = { 1091 [ C(RESULT_ACCESS) ] = -1, 1092 [ C(RESULT_MISS) ] = -1, 1093 }, 1094 }, 1095 [ C(NODE) ] = { 1096 [ C(OP_READ) ] = { 1097 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1098 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1099 }, 1100 [ C(OP_WRITE) ] = { 1101 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1102 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1103 }, 1104 [ C(OP_PREFETCH) ] = { 1105 [ C(RESULT_ACCESS) ] = 0x0, 1106 [ C(RESULT_MISS) ] = 0x0, 1107 }, 1108 }, 1109 }; 1110 1111 static __initconst const u64 hsw_hw_cache_extra_regs 1112 [PERF_COUNT_HW_CACHE_MAX] 1113 [PERF_COUNT_HW_CACHE_OP_MAX] 1114 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1115 { 1116 [ C(LL ) ] = { 1117 [ C(OP_READ) ] = { 1118 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1119 HSW_LLC_ACCESS, 1120 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1121 HSW_L3_MISS|HSW_ANY_SNOOP, 1122 }, 1123 [ C(OP_WRITE) ] = { 1124 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1125 HSW_LLC_ACCESS, 1126 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1127 HSW_L3_MISS|HSW_ANY_SNOOP, 1128 }, 1129 [ C(OP_PREFETCH) ] = { 1130 [ C(RESULT_ACCESS) ] = 0x0, 1131 [ C(RESULT_MISS) ] = 0x0, 1132 }, 1133 }, 1134 [ C(NODE) ] = { 1135 [ C(OP_READ) ] = { 1136 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1137 HSW_L3_MISS_LOCAL_DRAM| 1138 HSW_SNOOP_DRAM, 1139 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1140 HSW_L3_MISS_REMOTE| 1141 HSW_SNOOP_DRAM, 1142 }, 1143 [ C(OP_WRITE) ] = { 1144 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1145 HSW_L3_MISS_LOCAL_DRAM| 1146 HSW_SNOOP_DRAM, 1147 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1148 HSW_L3_MISS_REMOTE| 1149 HSW_SNOOP_DRAM, 1150 }, 1151 [ C(OP_PREFETCH) ] = { 1152 [ C(RESULT_ACCESS) ] = 0x0, 1153 [ C(RESULT_MISS) ] = 0x0, 1154 }, 1155 }, 1156 }; 1157 1158 static __initconst const u64 westmere_hw_cache_event_ids 1159 [PERF_COUNT_HW_CACHE_MAX] 1160 [PERF_COUNT_HW_CACHE_OP_MAX] 1161 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1162 { 1163 [ C(L1D) ] = { 1164 [ C(OP_READ) ] = { 1165 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1166 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1167 }, 1168 [ C(OP_WRITE) ] = { 1169 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1170 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1171 }, 1172 [ C(OP_PREFETCH) ] = { 1173 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1174 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1175 }, 1176 }, 1177 [ C(L1I ) ] = { 1178 [ C(OP_READ) ] = { 1179 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1180 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1181 }, 1182 [ C(OP_WRITE) ] = { 1183 [ C(RESULT_ACCESS) ] = -1, 1184 [ C(RESULT_MISS) ] = -1, 1185 }, 1186 [ C(OP_PREFETCH) ] = { 1187 [ C(RESULT_ACCESS) ] = 0x0, 1188 [ C(RESULT_MISS) ] = 0x0, 1189 }, 1190 }, 1191 [ C(LL ) ] = { 1192 [ C(OP_READ) ] = { 1193 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1194 [ C(RESULT_ACCESS) ] = 0x01b7, 1195 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1196 [ C(RESULT_MISS) ] = 0x01b7, 1197 }, 1198 /* 1199 * Use RFO, not WRITEBACK, because a write miss would typically occur 1200 * on RFO. 1201 */ 1202 [ C(OP_WRITE) ] = { 1203 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1204 [ C(RESULT_ACCESS) ] = 0x01b7, 1205 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1206 [ C(RESULT_MISS) ] = 0x01b7, 1207 }, 1208 [ C(OP_PREFETCH) ] = { 1209 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1210 [ C(RESULT_ACCESS) ] = 0x01b7, 1211 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1212 [ C(RESULT_MISS) ] = 0x01b7, 1213 }, 1214 }, 1215 [ C(DTLB) ] = { 1216 [ C(OP_READ) ] = { 1217 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1218 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1219 }, 1220 [ C(OP_WRITE) ] = { 1221 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1222 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1223 }, 1224 [ C(OP_PREFETCH) ] = { 1225 [ C(RESULT_ACCESS) ] = 0x0, 1226 [ C(RESULT_MISS) ] = 0x0, 1227 }, 1228 }, 1229 [ C(ITLB) ] = { 1230 [ C(OP_READ) ] = { 1231 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1232 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1233 }, 1234 [ C(OP_WRITE) ] = { 1235 [ C(RESULT_ACCESS) ] = -1, 1236 [ C(RESULT_MISS) ] = -1, 1237 }, 1238 [ C(OP_PREFETCH) ] = { 1239 [ C(RESULT_ACCESS) ] = -1, 1240 [ C(RESULT_MISS) ] = -1, 1241 }, 1242 }, 1243 [ C(BPU ) ] = { 1244 [ C(OP_READ) ] = { 1245 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1246 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1247 }, 1248 [ C(OP_WRITE) ] = { 1249 [ C(RESULT_ACCESS) ] = -1, 1250 [ C(RESULT_MISS) ] = -1, 1251 }, 1252 [ C(OP_PREFETCH) ] = { 1253 [ C(RESULT_ACCESS) ] = -1, 1254 [ C(RESULT_MISS) ] = -1, 1255 }, 1256 }, 1257 [ C(NODE) ] = { 1258 [ C(OP_READ) ] = { 1259 [ C(RESULT_ACCESS) ] = 0x01b7, 1260 [ C(RESULT_MISS) ] = 0x01b7, 1261 }, 1262 [ C(OP_WRITE) ] = { 1263 [ C(RESULT_ACCESS) ] = 0x01b7, 1264 [ C(RESULT_MISS) ] = 0x01b7, 1265 }, 1266 [ C(OP_PREFETCH) ] = { 1267 [ C(RESULT_ACCESS) ] = 0x01b7, 1268 [ C(RESULT_MISS) ] = 0x01b7, 1269 }, 1270 }, 1271 }; 1272 1273 /* 1274 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1275 * See IA32 SDM Vol 3B 30.6.1.3 1276 */ 1277 1278 #define NHM_DMND_DATA_RD (1 << 0) 1279 #define NHM_DMND_RFO (1 << 1) 1280 #define NHM_DMND_IFETCH (1 << 2) 1281 #define NHM_DMND_WB (1 << 3) 1282 #define NHM_PF_DATA_RD (1 << 4) 1283 #define NHM_PF_DATA_RFO (1 << 5) 1284 #define NHM_PF_IFETCH (1 << 6) 1285 #define NHM_OFFCORE_OTHER (1 << 7) 1286 #define NHM_UNCORE_HIT (1 << 8) 1287 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1288 #define NHM_OTHER_CORE_HITM (1 << 10) 1289 /* reserved */ 1290 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1291 #define NHM_REMOTE_DRAM (1 << 13) 1292 #define NHM_LOCAL_DRAM (1 << 14) 1293 #define NHM_NON_DRAM (1 << 15) 1294 1295 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1296 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1297 1298 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1299 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1300 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1301 1302 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1303 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1304 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1305 1306 static __initconst const u64 nehalem_hw_cache_extra_regs 1307 [PERF_COUNT_HW_CACHE_MAX] 1308 [PERF_COUNT_HW_CACHE_OP_MAX] 1309 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1310 { 1311 [ C(LL ) ] = { 1312 [ C(OP_READ) ] = { 1313 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1314 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1315 }, 1316 [ C(OP_WRITE) ] = { 1317 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1318 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1319 }, 1320 [ C(OP_PREFETCH) ] = { 1321 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1322 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1323 }, 1324 }, 1325 [ C(NODE) ] = { 1326 [ C(OP_READ) ] = { 1327 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1328 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1329 }, 1330 [ C(OP_WRITE) ] = { 1331 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1332 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1333 }, 1334 [ C(OP_PREFETCH) ] = { 1335 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1336 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1337 }, 1338 }, 1339 }; 1340 1341 static __initconst const u64 nehalem_hw_cache_event_ids 1342 [PERF_COUNT_HW_CACHE_MAX] 1343 [PERF_COUNT_HW_CACHE_OP_MAX] 1344 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1345 { 1346 [ C(L1D) ] = { 1347 [ C(OP_READ) ] = { 1348 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1349 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1350 }, 1351 [ C(OP_WRITE) ] = { 1352 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1353 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1354 }, 1355 [ C(OP_PREFETCH) ] = { 1356 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1357 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1358 }, 1359 }, 1360 [ C(L1I ) ] = { 1361 [ C(OP_READ) ] = { 1362 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1363 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1364 }, 1365 [ C(OP_WRITE) ] = { 1366 [ C(RESULT_ACCESS) ] = -1, 1367 [ C(RESULT_MISS) ] = -1, 1368 }, 1369 [ C(OP_PREFETCH) ] = { 1370 [ C(RESULT_ACCESS) ] = 0x0, 1371 [ C(RESULT_MISS) ] = 0x0, 1372 }, 1373 }, 1374 [ C(LL ) ] = { 1375 [ C(OP_READ) ] = { 1376 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1377 [ C(RESULT_ACCESS) ] = 0x01b7, 1378 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1379 [ C(RESULT_MISS) ] = 0x01b7, 1380 }, 1381 /* 1382 * Use RFO, not WRITEBACK, because a write miss would typically occur 1383 * on RFO. 1384 */ 1385 [ C(OP_WRITE) ] = { 1386 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1387 [ C(RESULT_ACCESS) ] = 0x01b7, 1388 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1389 [ C(RESULT_MISS) ] = 0x01b7, 1390 }, 1391 [ C(OP_PREFETCH) ] = { 1392 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1393 [ C(RESULT_ACCESS) ] = 0x01b7, 1394 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1395 [ C(RESULT_MISS) ] = 0x01b7, 1396 }, 1397 }, 1398 [ C(DTLB) ] = { 1399 [ C(OP_READ) ] = { 1400 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1401 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1402 }, 1403 [ C(OP_WRITE) ] = { 1404 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1405 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1406 }, 1407 [ C(OP_PREFETCH) ] = { 1408 [ C(RESULT_ACCESS) ] = 0x0, 1409 [ C(RESULT_MISS) ] = 0x0, 1410 }, 1411 }, 1412 [ C(ITLB) ] = { 1413 [ C(OP_READ) ] = { 1414 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1415 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1416 }, 1417 [ C(OP_WRITE) ] = { 1418 [ C(RESULT_ACCESS) ] = -1, 1419 [ C(RESULT_MISS) ] = -1, 1420 }, 1421 [ C(OP_PREFETCH) ] = { 1422 [ C(RESULT_ACCESS) ] = -1, 1423 [ C(RESULT_MISS) ] = -1, 1424 }, 1425 }, 1426 [ C(BPU ) ] = { 1427 [ C(OP_READ) ] = { 1428 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1429 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1430 }, 1431 [ C(OP_WRITE) ] = { 1432 [ C(RESULT_ACCESS) ] = -1, 1433 [ C(RESULT_MISS) ] = -1, 1434 }, 1435 [ C(OP_PREFETCH) ] = { 1436 [ C(RESULT_ACCESS) ] = -1, 1437 [ C(RESULT_MISS) ] = -1, 1438 }, 1439 }, 1440 [ C(NODE) ] = { 1441 [ C(OP_READ) ] = { 1442 [ C(RESULT_ACCESS) ] = 0x01b7, 1443 [ C(RESULT_MISS) ] = 0x01b7, 1444 }, 1445 [ C(OP_WRITE) ] = { 1446 [ C(RESULT_ACCESS) ] = 0x01b7, 1447 [ C(RESULT_MISS) ] = 0x01b7, 1448 }, 1449 [ C(OP_PREFETCH) ] = { 1450 [ C(RESULT_ACCESS) ] = 0x01b7, 1451 [ C(RESULT_MISS) ] = 0x01b7, 1452 }, 1453 }, 1454 }; 1455 1456 static __initconst const u64 core2_hw_cache_event_ids 1457 [PERF_COUNT_HW_CACHE_MAX] 1458 [PERF_COUNT_HW_CACHE_OP_MAX] 1459 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1460 { 1461 [ C(L1D) ] = { 1462 [ C(OP_READ) ] = { 1463 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1464 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1465 }, 1466 [ C(OP_WRITE) ] = { 1467 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1468 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1469 }, 1470 [ C(OP_PREFETCH) ] = { 1471 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1472 [ C(RESULT_MISS) ] = 0, 1473 }, 1474 }, 1475 [ C(L1I ) ] = { 1476 [ C(OP_READ) ] = { 1477 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1478 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1479 }, 1480 [ C(OP_WRITE) ] = { 1481 [ C(RESULT_ACCESS) ] = -1, 1482 [ C(RESULT_MISS) ] = -1, 1483 }, 1484 [ C(OP_PREFETCH) ] = { 1485 [ C(RESULT_ACCESS) ] = 0, 1486 [ C(RESULT_MISS) ] = 0, 1487 }, 1488 }, 1489 [ C(LL ) ] = { 1490 [ C(OP_READ) ] = { 1491 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1492 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1493 }, 1494 [ C(OP_WRITE) ] = { 1495 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1496 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1497 }, 1498 [ C(OP_PREFETCH) ] = { 1499 [ C(RESULT_ACCESS) ] = 0, 1500 [ C(RESULT_MISS) ] = 0, 1501 }, 1502 }, 1503 [ C(DTLB) ] = { 1504 [ C(OP_READ) ] = { 1505 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1506 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1507 }, 1508 [ C(OP_WRITE) ] = { 1509 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1510 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1511 }, 1512 [ C(OP_PREFETCH) ] = { 1513 [ C(RESULT_ACCESS) ] = 0, 1514 [ C(RESULT_MISS) ] = 0, 1515 }, 1516 }, 1517 [ C(ITLB) ] = { 1518 [ C(OP_READ) ] = { 1519 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1520 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1521 }, 1522 [ C(OP_WRITE) ] = { 1523 [ C(RESULT_ACCESS) ] = -1, 1524 [ C(RESULT_MISS) ] = -1, 1525 }, 1526 [ C(OP_PREFETCH) ] = { 1527 [ C(RESULT_ACCESS) ] = -1, 1528 [ C(RESULT_MISS) ] = -1, 1529 }, 1530 }, 1531 [ C(BPU ) ] = { 1532 [ C(OP_READ) ] = { 1533 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1534 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1535 }, 1536 [ C(OP_WRITE) ] = { 1537 [ C(RESULT_ACCESS) ] = -1, 1538 [ C(RESULT_MISS) ] = -1, 1539 }, 1540 [ C(OP_PREFETCH) ] = { 1541 [ C(RESULT_ACCESS) ] = -1, 1542 [ C(RESULT_MISS) ] = -1, 1543 }, 1544 }, 1545 }; 1546 1547 static __initconst const u64 atom_hw_cache_event_ids 1548 [PERF_COUNT_HW_CACHE_MAX] 1549 [PERF_COUNT_HW_CACHE_OP_MAX] 1550 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1551 { 1552 [ C(L1D) ] = { 1553 [ C(OP_READ) ] = { 1554 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1555 [ C(RESULT_MISS) ] = 0, 1556 }, 1557 [ C(OP_WRITE) ] = { 1558 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1559 [ C(RESULT_MISS) ] = 0, 1560 }, 1561 [ C(OP_PREFETCH) ] = { 1562 [ C(RESULT_ACCESS) ] = 0x0, 1563 [ C(RESULT_MISS) ] = 0, 1564 }, 1565 }, 1566 [ C(L1I ) ] = { 1567 [ C(OP_READ) ] = { 1568 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1569 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1570 }, 1571 [ C(OP_WRITE) ] = { 1572 [ C(RESULT_ACCESS) ] = -1, 1573 [ C(RESULT_MISS) ] = -1, 1574 }, 1575 [ C(OP_PREFETCH) ] = { 1576 [ C(RESULT_ACCESS) ] = 0, 1577 [ C(RESULT_MISS) ] = 0, 1578 }, 1579 }, 1580 [ C(LL ) ] = { 1581 [ C(OP_READ) ] = { 1582 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1583 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1584 }, 1585 [ C(OP_WRITE) ] = { 1586 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1587 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1588 }, 1589 [ C(OP_PREFETCH) ] = { 1590 [ C(RESULT_ACCESS) ] = 0, 1591 [ C(RESULT_MISS) ] = 0, 1592 }, 1593 }, 1594 [ C(DTLB) ] = { 1595 [ C(OP_READ) ] = { 1596 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1597 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1598 }, 1599 [ C(OP_WRITE) ] = { 1600 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1601 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1602 }, 1603 [ C(OP_PREFETCH) ] = { 1604 [ C(RESULT_ACCESS) ] = 0, 1605 [ C(RESULT_MISS) ] = 0, 1606 }, 1607 }, 1608 [ C(ITLB) ] = { 1609 [ C(OP_READ) ] = { 1610 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1611 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1612 }, 1613 [ C(OP_WRITE) ] = { 1614 [ C(RESULT_ACCESS) ] = -1, 1615 [ C(RESULT_MISS) ] = -1, 1616 }, 1617 [ C(OP_PREFETCH) ] = { 1618 [ C(RESULT_ACCESS) ] = -1, 1619 [ C(RESULT_MISS) ] = -1, 1620 }, 1621 }, 1622 [ C(BPU ) ] = { 1623 [ C(OP_READ) ] = { 1624 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1625 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1626 }, 1627 [ C(OP_WRITE) ] = { 1628 [ C(RESULT_ACCESS) ] = -1, 1629 [ C(RESULT_MISS) ] = -1, 1630 }, 1631 [ C(OP_PREFETCH) ] = { 1632 [ C(RESULT_ACCESS) ] = -1, 1633 [ C(RESULT_MISS) ] = -1, 1634 }, 1635 }, 1636 }; 1637 1638 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1639 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1640 /* no_alloc_cycles.not_delivered */ 1641 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1642 "event=0xca,umask=0x50"); 1643 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1644 /* uops_retired.all */ 1645 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1646 "event=0xc2,umask=0x10"); 1647 /* uops_retired.all */ 1648 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1649 "event=0xc2,umask=0x10"); 1650 1651 static struct attribute *slm_events_attrs[] = { 1652 EVENT_PTR(td_total_slots_slm), 1653 EVENT_PTR(td_total_slots_scale_slm), 1654 EVENT_PTR(td_fetch_bubbles_slm), 1655 EVENT_PTR(td_fetch_bubbles_scale_slm), 1656 EVENT_PTR(td_slots_issued_slm), 1657 EVENT_PTR(td_slots_retired_slm), 1658 NULL 1659 }; 1660 1661 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1662 { 1663 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1664 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1665 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1666 EVENT_EXTRA_END 1667 }; 1668 1669 #define SLM_DMND_READ SNB_DMND_DATA_RD 1670 #define SLM_DMND_WRITE SNB_DMND_RFO 1671 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1672 1673 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1674 #define SLM_LLC_ACCESS SNB_RESP_ANY 1675 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1676 1677 static __initconst const u64 slm_hw_cache_extra_regs 1678 [PERF_COUNT_HW_CACHE_MAX] 1679 [PERF_COUNT_HW_CACHE_OP_MAX] 1680 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1681 { 1682 [ C(LL ) ] = { 1683 [ C(OP_READ) ] = { 1684 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1685 [ C(RESULT_MISS) ] = 0, 1686 }, 1687 [ C(OP_WRITE) ] = { 1688 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1689 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1690 }, 1691 [ C(OP_PREFETCH) ] = { 1692 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1693 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1694 }, 1695 }, 1696 }; 1697 1698 static __initconst const u64 slm_hw_cache_event_ids 1699 [PERF_COUNT_HW_CACHE_MAX] 1700 [PERF_COUNT_HW_CACHE_OP_MAX] 1701 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1702 { 1703 [ C(L1D) ] = { 1704 [ C(OP_READ) ] = { 1705 [ C(RESULT_ACCESS) ] = 0, 1706 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1707 }, 1708 [ C(OP_WRITE) ] = { 1709 [ C(RESULT_ACCESS) ] = 0, 1710 [ C(RESULT_MISS) ] = 0, 1711 }, 1712 [ C(OP_PREFETCH) ] = { 1713 [ C(RESULT_ACCESS) ] = 0, 1714 [ C(RESULT_MISS) ] = 0, 1715 }, 1716 }, 1717 [ C(L1I ) ] = { 1718 [ C(OP_READ) ] = { 1719 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1720 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1721 }, 1722 [ C(OP_WRITE) ] = { 1723 [ C(RESULT_ACCESS) ] = -1, 1724 [ C(RESULT_MISS) ] = -1, 1725 }, 1726 [ C(OP_PREFETCH) ] = { 1727 [ C(RESULT_ACCESS) ] = 0, 1728 [ C(RESULT_MISS) ] = 0, 1729 }, 1730 }, 1731 [ C(LL ) ] = { 1732 [ C(OP_READ) ] = { 1733 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1734 [ C(RESULT_ACCESS) ] = 0x01b7, 1735 [ C(RESULT_MISS) ] = 0, 1736 }, 1737 [ C(OP_WRITE) ] = { 1738 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1739 [ C(RESULT_ACCESS) ] = 0x01b7, 1740 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1741 [ C(RESULT_MISS) ] = 0x01b7, 1742 }, 1743 [ C(OP_PREFETCH) ] = { 1744 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1745 [ C(RESULT_ACCESS) ] = 0x01b7, 1746 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1747 [ C(RESULT_MISS) ] = 0x01b7, 1748 }, 1749 }, 1750 [ C(DTLB) ] = { 1751 [ C(OP_READ) ] = { 1752 [ C(RESULT_ACCESS) ] = 0, 1753 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1754 }, 1755 [ C(OP_WRITE) ] = { 1756 [ C(RESULT_ACCESS) ] = 0, 1757 [ C(RESULT_MISS) ] = 0, 1758 }, 1759 [ C(OP_PREFETCH) ] = { 1760 [ C(RESULT_ACCESS) ] = 0, 1761 [ C(RESULT_MISS) ] = 0, 1762 }, 1763 }, 1764 [ C(ITLB) ] = { 1765 [ C(OP_READ) ] = { 1766 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1767 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1768 }, 1769 [ C(OP_WRITE) ] = { 1770 [ C(RESULT_ACCESS) ] = -1, 1771 [ C(RESULT_MISS) ] = -1, 1772 }, 1773 [ C(OP_PREFETCH) ] = { 1774 [ C(RESULT_ACCESS) ] = -1, 1775 [ C(RESULT_MISS) ] = -1, 1776 }, 1777 }, 1778 [ C(BPU ) ] = { 1779 [ C(OP_READ) ] = { 1780 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1781 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1782 }, 1783 [ C(OP_WRITE) ] = { 1784 [ C(RESULT_ACCESS) ] = -1, 1785 [ C(RESULT_MISS) ] = -1, 1786 }, 1787 [ C(OP_PREFETCH) ] = { 1788 [ C(RESULT_ACCESS) ] = -1, 1789 [ C(RESULT_MISS) ] = -1, 1790 }, 1791 }, 1792 }; 1793 1794 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1795 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1796 /* UOPS_NOT_DELIVERED.ANY */ 1797 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1798 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1799 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1800 /* UOPS_RETIRED.ANY */ 1801 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1802 /* UOPS_ISSUED.ANY */ 1803 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1804 1805 static struct attribute *glm_events_attrs[] = { 1806 EVENT_PTR(td_total_slots_glm), 1807 EVENT_PTR(td_total_slots_scale_glm), 1808 EVENT_PTR(td_fetch_bubbles_glm), 1809 EVENT_PTR(td_recovery_bubbles_glm), 1810 EVENT_PTR(td_slots_issued_glm), 1811 EVENT_PTR(td_slots_retired_glm), 1812 NULL 1813 }; 1814 1815 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1816 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1817 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1818 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1819 EVENT_EXTRA_END 1820 }; 1821 1822 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1823 #define GLM_DEMAND_RFO BIT_ULL(1) 1824 #define GLM_ANY_RESPONSE BIT_ULL(16) 1825 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1826 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1827 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1828 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1829 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1830 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1831 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1832 1833 static __initconst const u64 glm_hw_cache_event_ids 1834 [PERF_COUNT_HW_CACHE_MAX] 1835 [PERF_COUNT_HW_CACHE_OP_MAX] 1836 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1837 [C(L1D)] = { 1838 [C(OP_READ)] = { 1839 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1840 [C(RESULT_MISS)] = 0x0, 1841 }, 1842 [C(OP_WRITE)] = { 1843 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1844 [C(RESULT_MISS)] = 0x0, 1845 }, 1846 [C(OP_PREFETCH)] = { 1847 [C(RESULT_ACCESS)] = 0x0, 1848 [C(RESULT_MISS)] = 0x0, 1849 }, 1850 }, 1851 [C(L1I)] = { 1852 [C(OP_READ)] = { 1853 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1854 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1855 }, 1856 [C(OP_WRITE)] = { 1857 [C(RESULT_ACCESS)] = -1, 1858 [C(RESULT_MISS)] = -1, 1859 }, 1860 [C(OP_PREFETCH)] = { 1861 [C(RESULT_ACCESS)] = 0x0, 1862 [C(RESULT_MISS)] = 0x0, 1863 }, 1864 }, 1865 [C(LL)] = { 1866 [C(OP_READ)] = { 1867 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1868 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1869 }, 1870 [C(OP_WRITE)] = { 1871 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1872 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1873 }, 1874 [C(OP_PREFETCH)] = { 1875 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1876 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1877 }, 1878 }, 1879 [C(DTLB)] = { 1880 [C(OP_READ)] = { 1881 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1882 [C(RESULT_MISS)] = 0x0, 1883 }, 1884 [C(OP_WRITE)] = { 1885 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1886 [C(RESULT_MISS)] = 0x0, 1887 }, 1888 [C(OP_PREFETCH)] = { 1889 [C(RESULT_ACCESS)] = 0x0, 1890 [C(RESULT_MISS)] = 0x0, 1891 }, 1892 }, 1893 [C(ITLB)] = { 1894 [C(OP_READ)] = { 1895 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1896 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1897 }, 1898 [C(OP_WRITE)] = { 1899 [C(RESULT_ACCESS)] = -1, 1900 [C(RESULT_MISS)] = -1, 1901 }, 1902 [C(OP_PREFETCH)] = { 1903 [C(RESULT_ACCESS)] = -1, 1904 [C(RESULT_MISS)] = -1, 1905 }, 1906 }, 1907 [C(BPU)] = { 1908 [C(OP_READ)] = { 1909 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1910 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1911 }, 1912 [C(OP_WRITE)] = { 1913 [C(RESULT_ACCESS)] = -1, 1914 [C(RESULT_MISS)] = -1, 1915 }, 1916 [C(OP_PREFETCH)] = { 1917 [C(RESULT_ACCESS)] = -1, 1918 [C(RESULT_MISS)] = -1, 1919 }, 1920 }, 1921 }; 1922 1923 static __initconst const u64 glm_hw_cache_extra_regs 1924 [PERF_COUNT_HW_CACHE_MAX] 1925 [PERF_COUNT_HW_CACHE_OP_MAX] 1926 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1927 [C(LL)] = { 1928 [C(OP_READ)] = { 1929 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1930 GLM_LLC_ACCESS, 1931 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1932 GLM_LLC_MISS, 1933 }, 1934 [C(OP_WRITE)] = { 1935 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1936 GLM_LLC_ACCESS, 1937 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1938 GLM_LLC_MISS, 1939 }, 1940 [C(OP_PREFETCH)] = { 1941 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1942 GLM_LLC_ACCESS, 1943 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1944 GLM_LLC_MISS, 1945 }, 1946 }, 1947 }; 1948 1949 static __initconst const u64 glp_hw_cache_event_ids 1950 [PERF_COUNT_HW_CACHE_MAX] 1951 [PERF_COUNT_HW_CACHE_OP_MAX] 1952 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1953 [C(L1D)] = { 1954 [C(OP_READ)] = { 1955 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1956 [C(RESULT_MISS)] = 0x0, 1957 }, 1958 [C(OP_WRITE)] = { 1959 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1960 [C(RESULT_MISS)] = 0x0, 1961 }, 1962 [C(OP_PREFETCH)] = { 1963 [C(RESULT_ACCESS)] = 0x0, 1964 [C(RESULT_MISS)] = 0x0, 1965 }, 1966 }, 1967 [C(L1I)] = { 1968 [C(OP_READ)] = { 1969 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1970 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1971 }, 1972 [C(OP_WRITE)] = { 1973 [C(RESULT_ACCESS)] = -1, 1974 [C(RESULT_MISS)] = -1, 1975 }, 1976 [C(OP_PREFETCH)] = { 1977 [C(RESULT_ACCESS)] = 0x0, 1978 [C(RESULT_MISS)] = 0x0, 1979 }, 1980 }, 1981 [C(LL)] = { 1982 [C(OP_READ)] = { 1983 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1984 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1985 }, 1986 [C(OP_WRITE)] = { 1987 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1988 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1989 }, 1990 [C(OP_PREFETCH)] = { 1991 [C(RESULT_ACCESS)] = 0x0, 1992 [C(RESULT_MISS)] = 0x0, 1993 }, 1994 }, 1995 [C(DTLB)] = { 1996 [C(OP_READ)] = { 1997 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1998 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1999 }, 2000 [C(OP_WRITE)] = { 2001 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2002 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2003 }, 2004 [C(OP_PREFETCH)] = { 2005 [C(RESULT_ACCESS)] = 0x0, 2006 [C(RESULT_MISS)] = 0x0, 2007 }, 2008 }, 2009 [C(ITLB)] = { 2010 [C(OP_READ)] = { 2011 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2012 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2013 }, 2014 [C(OP_WRITE)] = { 2015 [C(RESULT_ACCESS)] = -1, 2016 [C(RESULT_MISS)] = -1, 2017 }, 2018 [C(OP_PREFETCH)] = { 2019 [C(RESULT_ACCESS)] = -1, 2020 [C(RESULT_MISS)] = -1, 2021 }, 2022 }, 2023 [C(BPU)] = { 2024 [C(OP_READ)] = { 2025 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2026 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2027 }, 2028 [C(OP_WRITE)] = { 2029 [C(RESULT_ACCESS)] = -1, 2030 [C(RESULT_MISS)] = -1, 2031 }, 2032 [C(OP_PREFETCH)] = { 2033 [C(RESULT_ACCESS)] = -1, 2034 [C(RESULT_MISS)] = -1, 2035 }, 2036 }, 2037 }; 2038 2039 static __initconst const u64 glp_hw_cache_extra_regs 2040 [PERF_COUNT_HW_CACHE_MAX] 2041 [PERF_COUNT_HW_CACHE_OP_MAX] 2042 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2043 [C(LL)] = { 2044 [C(OP_READ)] = { 2045 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2046 GLM_LLC_ACCESS, 2047 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2048 GLM_LLC_MISS, 2049 }, 2050 [C(OP_WRITE)] = { 2051 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2052 GLM_LLC_ACCESS, 2053 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2054 GLM_LLC_MISS, 2055 }, 2056 [C(OP_PREFETCH)] = { 2057 [C(RESULT_ACCESS)] = 0x0, 2058 [C(RESULT_MISS)] = 0x0, 2059 }, 2060 }, 2061 }; 2062 2063 #define TNT_LOCAL_DRAM BIT_ULL(26) 2064 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2065 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2066 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2067 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2068 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2069 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2070 2071 static __initconst const u64 tnt_hw_cache_extra_regs 2072 [PERF_COUNT_HW_CACHE_MAX] 2073 [PERF_COUNT_HW_CACHE_OP_MAX] 2074 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2075 [C(LL)] = { 2076 [C(OP_READ)] = { 2077 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2078 TNT_LLC_ACCESS, 2079 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2080 TNT_LLC_MISS, 2081 }, 2082 [C(OP_WRITE)] = { 2083 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2084 TNT_LLC_ACCESS, 2085 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2086 TNT_LLC_MISS, 2087 }, 2088 [C(OP_PREFETCH)] = { 2089 [C(RESULT_ACCESS)] = 0x0, 2090 [C(RESULT_MISS)] = 0x0, 2091 }, 2092 }, 2093 }; 2094 2095 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2096 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2097 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2098 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2099 2100 static struct attribute *tnt_events_attrs[] = { 2101 EVENT_PTR(td_fe_bound_tnt), 2102 EVENT_PTR(td_retiring_tnt), 2103 EVENT_PTR(td_bad_spec_tnt), 2104 EVENT_PTR(td_be_bound_tnt), 2105 NULL, 2106 }; 2107 2108 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2109 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2110 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2111 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2112 EVENT_EXTRA_END 2113 }; 2114 2115 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2116 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2117 2118 static struct attribute *grt_mem_attrs[] = { 2119 EVENT_PTR(mem_ld_grt), 2120 EVENT_PTR(mem_st_grt), 2121 NULL 2122 }; 2123 2124 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2125 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2126 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2127 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2128 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2129 EVENT_EXTRA_END 2130 }; 2131 2132 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2133 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2134 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2135 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2136 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2137 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2138 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2139 EVENT_EXTRA_END 2140 }; 2141 2142 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2143 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2144 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2145 #define KNL_MCDRAM_FAR BIT_ULL(22) 2146 #define KNL_DDR_LOCAL BIT_ULL(23) 2147 #define KNL_DDR_FAR BIT_ULL(24) 2148 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2149 KNL_DDR_LOCAL | KNL_DDR_FAR) 2150 #define KNL_L2_READ SLM_DMND_READ 2151 #define KNL_L2_WRITE SLM_DMND_WRITE 2152 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2153 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2154 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2155 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2156 SNB_NON_DRAM) 2157 2158 static __initconst const u64 knl_hw_cache_extra_regs 2159 [PERF_COUNT_HW_CACHE_MAX] 2160 [PERF_COUNT_HW_CACHE_OP_MAX] 2161 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2162 [C(LL)] = { 2163 [C(OP_READ)] = { 2164 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2165 [C(RESULT_MISS)] = 0, 2166 }, 2167 [C(OP_WRITE)] = { 2168 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2169 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2170 }, 2171 [C(OP_PREFETCH)] = { 2172 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2173 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2174 }, 2175 }, 2176 }; 2177 2178 /* 2179 * Used from PMIs where the LBRs are already disabled. 2180 * 2181 * This function could be called consecutively. It is required to remain in 2182 * disabled state if called consecutively. 2183 * 2184 * During consecutive calls, the same disable value will be written to related 2185 * registers, so the PMU state remains unchanged. 2186 * 2187 * intel_bts events don't coexist with intel PMU's BTS events because of 2188 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2189 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2190 * 2191 * Avoid PEBS_ENABLE MSR access in PMIs. 2192 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2193 * It doesn't matter if the PEBS is enabled or not. 2194 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2195 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2196 * However, there are some cases which may change PEBS status, e.g. PMI 2197 * throttle. The PEBS_ENABLE should be updated where the status changes. 2198 */ 2199 static __always_inline void __intel_pmu_disable_all(bool bts) 2200 { 2201 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2202 2203 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2204 2205 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2206 intel_pmu_disable_bts(); 2207 } 2208 2209 static __always_inline void intel_pmu_disable_all(void) 2210 { 2211 __intel_pmu_disable_all(true); 2212 intel_pmu_pebs_disable_all(); 2213 intel_pmu_lbr_disable_all(); 2214 } 2215 2216 static void __intel_pmu_enable_all(int added, bool pmi) 2217 { 2218 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2219 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2220 2221 intel_pmu_lbr_enable_all(pmi); 2222 2223 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2224 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2225 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2226 } 2227 2228 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2229 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2230 2231 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2232 struct perf_event *event = 2233 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2234 2235 if (WARN_ON_ONCE(!event)) 2236 return; 2237 2238 intel_pmu_enable_bts(event->hw.config); 2239 } 2240 } 2241 2242 static void intel_pmu_enable_all(int added) 2243 { 2244 intel_pmu_pebs_enable_all(); 2245 __intel_pmu_enable_all(added, false); 2246 } 2247 2248 static noinline int 2249 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2250 unsigned int cnt, unsigned long flags) 2251 { 2252 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2253 2254 intel_pmu_lbr_read(); 2255 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2256 2257 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2258 intel_pmu_enable_all(0); 2259 local_irq_restore(flags); 2260 return cnt; 2261 } 2262 2263 static int 2264 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2265 { 2266 unsigned long flags; 2267 2268 /* must not have branches... */ 2269 local_irq_save(flags); 2270 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2271 __intel_pmu_lbr_disable(); 2272 /* ... until here */ 2273 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2274 } 2275 2276 static int 2277 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2278 { 2279 unsigned long flags; 2280 2281 /* must not have branches... */ 2282 local_irq_save(flags); 2283 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2284 __intel_pmu_arch_lbr_disable(); 2285 /* ... until here */ 2286 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2287 } 2288 2289 /* 2290 * Workaround for: 2291 * Intel Errata AAK100 (model 26) 2292 * Intel Errata AAP53 (model 30) 2293 * Intel Errata BD53 (model 44) 2294 * 2295 * The official story: 2296 * These chips need to be 'reset' when adding counters by programming the 2297 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2298 * in sequence on the same PMC or on different PMCs. 2299 * 2300 * In practice it appears some of these events do in fact count, and 2301 * we need to program all 4 events. 2302 */ 2303 static void intel_pmu_nhm_workaround(void) 2304 { 2305 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2306 static const unsigned long nhm_magic[4] = { 2307 0x4300B5, 2308 0x4300D2, 2309 0x4300B1, 2310 0x4300B1 2311 }; 2312 struct perf_event *event; 2313 int i; 2314 2315 /* 2316 * The Errata requires below steps: 2317 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2318 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2319 * the corresponding PMCx; 2320 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2321 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2322 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2323 */ 2324 2325 /* 2326 * The real steps we choose are a little different from above. 2327 * A) To reduce MSR operations, we don't run step 1) as they 2328 * are already cleared before this function is called; 2329 * B) Call x86_perf_event_update to save PMCx before configuring 2330 * PERFEVTSELx with magic number; 2331 * C) With step 5), we do clear only when the PERFEVTSELx is 2332 * not used currently. 2333 * D) Call x86_perf_event_set_period to restore PMCx; 2334 */ 2335 2336 /* We always operate 4 pairs of PERF Counters */ 2337 for (i = 0; i < 4; i++) { 2338 event = cpuc->events[i]; 2339 if (event) 2340 static_call(x86_pmu_update)(event); 2341 } 2342 2343 for (i = 0; i < 4; i++) { 2344 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2345 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2346 } 2347 2348 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2349 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2350 2351 for (i = 0; i < 4; i++) { 2352 event = cpuc->events[i]; 2353 2354 if (event) { 2355 static_call(x86_pmu_set_period)(event); 2356 __x86_pmu_enable_event(&event->hw, 2357 ARCH_PERFMON_EVENTSEL_ENABLE); 2358 } else 2359 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2360 } 2361 } 2362 2363 static void intel_pmu_nhm_enable_all(int added) 2364 { 2365 if (added) 2366 intel_pmu_nhm_workaround(); 2367 intel_pmu_enable_all(added); 2368 } 2369 2370 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2371 { 2372 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2373 2374 if (cpuc->tfa_shadow != val) { 2375 cpuc->tfa_shadow = val; 2376 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2377 } 2378 } 2379 2380 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2381 { 2382 /* 2383 * We're going to use PMC3, make sure TFA is set before we touch it. 2384 */ 2385 if (cntr == 3) 2386 intel_set_tfa(cpuc, true); 2387 } 2388 2389 static void intel_tfa_pmu_enable_all(int added) 2390 { 2391 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2392 2393 /* 2394 * If we find PMC3 is no longer used when we enable the PMU, we can 2395 * clear TFA. 2396 */ 2397 if (!test_bit(3, cpuc->active_mask)) 2398 intel_set_tfa(cpuc, false); 2399 2400 intel_pmu_enable_all(added); 2401 } 2402 2403 static inline u64 intel_pmu_get_status(void) 2404 { 2405 u64 status; 2406 2407 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2408 2409 return status; 2410 } 2411 2412 static inline void intel_pmu_ack_status(u64 ack) 2413 { 2414 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2415 } 2416 2417 static inline bool event_is_checkpointed(struct perf_event *event) 2418 { 2419 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2420 } 2421 2422 static inline void intel_set_masks(struct perf_event *event, int idx) 2423 { 2424 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2425 2426 if (event->attr.exclude_host) 2427 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2428 if (event->attr.exclude_guest) 2429 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2430 if (event_is_checkpointed(event)) 2431 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2432 } 2433 2434 static inline void intel_clear_masks(struct perf_event *event, int idx) 2435 { 2436 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2437 2438 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2439 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2440 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2441 } 2442 2443 static void intel_pmu_disable_fixed(struct perf_event *event) 2444 { 2445 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2446 struct hw_perf_event *hwc = &event->hw; 2447 int idx = hwc->idx; 2448 u64 mask; 2449 2450 if (is_topdown_idx(idx)) { 2451 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2452 2453 /* 2454 * When there are other active TopDown events, 2455 * don't disable the fixed counter 3. 2456 */ 2457 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2458 return; 2459 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2460 } 2461 2462 intel_clear_masks(event, idx); 2463 2464 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2465 cpuc->fixed_ctrl_val &= ~mask; 2466 } 2467 2468 static void intel_pmu_disable_event(struct perf_event *event) 2469 { 2470 struct hw_perf_event *hwc = &event->hw; 2471 int idx = hwc->idx; 2472 2473 switch (idx) { 2474 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2475 intel_clear_masks(event, idx); 2476 x86_pmu_disable_event(event); 2477 break; 2478 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2479 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2480 intel_pmu_disable_fixed(event); 2481 break; 2482 case INTEL_PMC_IDX_FIXED_BTS: 2483 intel_pmu_disable_bts(); 2484 intel_pmu_drain_bts_buffer(); 2485 return; 2486 case INTEL_PMC_IDX_FIXED_VLBR: 2487 intel_clear_masks(event, idx); 2488 break; 2489 default: 2490 intel_clear_masks(event, idx); 2491 pr_warn("Failed to disable the event with invalid index %d\n", 2492 idx); 2493 return; 2494 } 2495 2496 /* 2497 * Needs to be called after x86_pmu_disable_event, 2498 * so we don't trigger the event without PEBS bit set. 2499 */ 2500 if (unlikely(event->attr.precise_ip)) 2501 intel_pmu_pebs_disable(event); 2502 } 2503 2504 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2505 { 2506 if (is_pebs_pt(event)) 2507 perf_report_aux_output_id(event, idx); 2508 } 2509 2510 static void intel_pmu_del_event(struct perf_event *event) 2511 { 2512 if (needs_branch_stack(event)) 2513 intel_pmu_lbr_del(event); 2514 if (event->attr.precise_ip) 2515 intel_pmu_pebs_del(event); 2516 } 2517 2518 static int icl_set_topdown_event_period(struct perf_event *event) 2519 { 2520 struct hw_perf_event *hwc = &event->hw; 2521 s64 left = local64_read(&hwc->period_left); 2522 2523 /* 2524 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2525 * Software should start both registers, PERF_METRICS and fixed 2526 * counter 3, from zero. 2527 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2528 * After that, both MSRs will be cleared for each read. 2529 * Don't need to clear them again. 2530 */ 2531 if (left == x86_pmu.max_period) { 2532 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2533 wrmsrl(MSR_PERF_METRICS, 0); 2534 hwc->saved_slots = 0; 2535 hwc->saved_metric = 0; 2536 } 2537 2538 if ((hwc->saved_slots) && is_slots_event(event)) { 2539 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2540 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2541 } 2542 2543 perf_event_update_userpage(event); 2544 2545 return 0; 2546 } 2547 2548 static int adl_set_topdown_event_period(struct perf_event *event) 2549 { 2550 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2551 2552 if (pmu->cpu_type != hybrid_big) 2553 return 0; 2554 2555 return icl_set_topdown_event_period(event); 2556 } 2557 2558 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2559 2560 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2561 { 2562 u32 val; 2563 2564 /* 2565 * The metric is reported as an 8bit integer fraction 2566 * summing up to 0xff. 2567 * slots-in-metric = (Metric / 0xff) * slots 2568 */ 2569 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2570 return mul_u64_u32_div(slots, val, 0xff); 2571 } 2572 2573 static u64 icl_get_topdown_value(struct perf_event *event, 2574 u64 slots, u64 metrics) 2575 { 2576 int idx = event->hw.idx; 2577 u64 delta; 2578 2579 if (is_metric_idx(idx)) 2580 delta = icl_get_metrics_event_value(metrics, slots, idx); 2581 else 2582 delta = slots; 2583 2584 return delta; 2585 } 2586 2587 static void __icl_update_topdown_event(struct perf_event *event, 2588 u64 slots, u64 metrics, 2589 u64 last_slots, u64 last_metrics) 2590 { 2591 u64 delta, last = 0; 2592 2593 delta = icl_get_topdown_value(event, slots, metrics); 2594 if (last_slots) 2595 last = icl_get_topdown_value(event, last_slots, last_metrics); 2596 2597 /* 2598 * The 8bit integer fraction of metric may be not accurate, 2599 * especially when the changes is very small. 2600 * For example, if only a few bad_spec happens, the fraction 2601 * may be reduced from 1 to 0. If so, the bad_spec event value 2602 * will be 0 which is definitely less than the last value. 2603 * Avoid update event->count for this case. 2604 */ 2605 if (delta > last) { 2606 delta -= last; 2607 local64_add(delta, &event->count); 2608 } 2609 } 2610 2611 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2612 u64 metrics, int metric_end) 2613 { 2614 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2615 struct perf_event *other; 2616 int idx; 2617 2618 event->hw.saved_slots = slots; 2619 event->hw.saved_metric = metrics; 2620 2621 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2622 if (!is_topdown_idx(idx)) 2623 continue; 2624 other = cpuc->events[idx]; 2625 other->hw.saved_slots = slots; 2626 other->hw.saved_metric = metrics; 2627 } 2628 } 2629 2630 /* 2631 * Update all active Topdown events. 2632 * 2633 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2634 * modify by a NMI. PMU has to be disabled before calling this function. 2635 */ 2636 2637 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2638 { 2639 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2640 struct perf_event *other; 2641 u64 slots, metrics; 2642 bool reset = true; 2643 int idx; 2644 2645 /* read Fixed counter 3 */ 2646 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2647 if (!slots) 2648 return 0; 2649 2650 /* read PERF_METRICS */ 2651 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2652 2653 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2654 if (!is_topdown_idx(idx)) 2655 continue; 2656 other = cpuc->events[idx]; 2657 __icl_update_topdown_event(other, slots, metrics, 2658 event ? event->hw.saved_slots : 0, 2659 event ? event->hw.saved_metric : 0); 2660 } 2661 2662 /* 2663 * Check and update this event, which may have been cleared 2664 * in active_mask e.g. x86_pmu_stop() 2665 */ 2666 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2667 __icl_update_topdown_event(event, slots, metrics, 2668 event->hw.saved_slots, 2669 event->hw.saved_metric); 2670 2671 /* 2672 * In x86_pmu_stop(), the event is cleared in active_mask first, 2673 * then drain the delta, which indicates context switch for 2674 * counting. 2675 * Save metric and slots for context switch. 2676 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2677 * Because the values will be restored in next schedule in. 2678 */ 2679 update_saved_topdown_regs(event, slots, metrics, metric_end); 2680 reset = false; 2681 } 2682 2683 if (reset) { 2684 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2685 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2686 wrmsrl(MSR_PERF_METRICS, 0); 2687 if (event) 2688 update_saved_topdown_regs(event, 0, 0, metric_end); 2689 } 2690 2691 return slots; 2692 } 2693 2694 static u64 icl_update_topdown_event(struct perf_event *event) 2695 { 2696 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2697 x86_pmu.num_topdown_events - 1); 2698 } 2699 2700 static u64 adl_update_topdown_event(struct perf_event *event) 2701 { 2702 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2703 2704 if (pmu->cpu_type != hybrid_big) 2705 return 0; 2706 2707 return icl_update_topdown_event(event); 2708 } 2709 2710 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update); 2711 2712 static void intel_pmu_read_topdown_event(struct perf_event *event) 2713 { 2714 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2715 2716 /* Only need to call update_topdown_event() once for group read. */ 2717 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2718 !is_slots_event(event)) 2719 return; 2720 2721 perf_pmu_disable(event->pmu); 2722 static_call(intel_pmu_update_topdown_event)(event); 2723 perf_pmu_enable(event->pmu); 2724 } 2725 2726 static void intel_pmu_read_event(struct perf_event *event) 2727 { 2728 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2729 intel_pmu_auto_reload_read(event); 2730 else if (is_topdown_count(event)) 2731 intel_pmu_read_topdown_event(event); 2732 else 2733 x86_perf_event_update(event); 2734 } 2735 2736 static void intel_pmu_enable_fixed(struct perf_event *event) 2737 { 2738 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2739 struct hw_perf_event *hwc = &event->hw; 2740 u64 mask, bits = 0; 2741 int idx = hwc->idx; 2742 2743 if (is_topdown_idx(idx)) { 2744 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2745 /* 2746 * When there are other active TopDown events, 2747 * don't enable the fixed counter 3 again. 2748 */ 2749 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2750 return; 2751 2752 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2753 } 2754 2755 intel_set_masks(event, idx); 2756 2757 /* 2758 * Enable IRQ generation (0x8), if not PEBS, 2759 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2760 * if requested: 2761 */ 2762 if (!event->attr.precise_ip) 2763 bits |= INTEL_FIXED_0_ENABLE_PMI; 2764 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2765 bits |= INTEL_FIXED_0_USER; 2766 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2767 bits |= INTEL_FIXED_0_KERNEL; 2768 2769 /* 2770 * ANY bit is supported in v3 and up 2771 */ 2772 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2773 bits |= INTEL_FIXED_0_ANYTHREAD; 2774 2775 idx -= INTEL_PMC_IDX_FIXED; 2776 bits = intel_fixed_bits_by_idx(idx, bits); 2777 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2778 2779 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2780 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2781 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2782 } 2783 2784 cpuc->fixed_ctrl_val &= ~mask; 2785 cpuc->fixed_ctrl_val |= bits; 2786 } 2787 2788 static void intel_pmu_enable_event(struct perf_event *event) 2789 { 2790 struct hw_perf_event *hwc = &event->hw; 2791 int idx = hwc->idx; 2792 2793 if (unlikely(event->attr.precise_ip)) 2794 intel_pmu_pebs_enable(event); 2795 2796 switch (idx) { 2797 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2798 intel_set_masks(event, idx); 2799 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2800 break; 2801 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2802 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2803 intel_pmu_enable_fixed(event); 2804 break; 2805 case INTEL_PMC_IDX_FIXED_BTS: 2806 if (!__this_cpu_read(cpu_hw_events.enabled)) 2807 return; 2808 intel_pmu_enable_bts(hwc->config); 2809 break; 2810 case INTEL_PMC_IDX_FIXED_VLBR: 2811 intel_set_masks(event, idx); 2812 break; 2813 default: 2814 pr_warn("Failed to enable the event with invalid index %d\n", 2815 idx); 2816 } 2817 } 2818 2819 static void intel_pmu_add_event(struct perf_event *event) 2820 { 2821 if (event->attr.precise_ip) 2822 intel_pmu_pebs_add(event); 2823 if (needs_branch_stack(event)) 2824 intel_pmu_lbr_add(event); 2825 } 2826 2827 /* 2828 * Save and restart an expired event. Called by NMI contexts, 2829 * so it has to be careful about preempting normal event ops: 2830 */ 2831 int intel_pmu_save_and_restart(struct perf_event *event) 2832 { 2833 static_call(x86_pmu_update)(event); 2834 /* 2835 * For a checkpointed counter always reset back to 0. This 2836 * avoids a situation where the counter overflows, aborts the 2837 * transaction and is then set back to shortly before the 2838 * overflow, and overflows and aborts again. 2839 */ 2840 if (unlikely(event_is_checkpointed(event))) { 2841 /* No race with NMIs because the counter should not be armed */ 2842 wrmsrl(event->hw.event_base, 0); 2843 local64_set(&event->hw.prev_count, 0); 2844 } 2845 return static_call(x86_pmu_set_period)(event); 2846 } 2847 2848 static int intel_pmu_set_period(struct perf_event *event) 2849 { 2850 if (unlikely(is_topdown_count(event))) 2851 return static_call(intel_pmu_set_topdown_event_period)(event); 2852 2853 return x86_perf_event_set_period(event); 2854 } 2855 2856 static u64 intel_pmu_update(struct perf_event *event) 2857 { 2858 if (unlikely(is_topdown_count(event))) 2859 return static_call(intel_pmu_update_topdown_event)(event); 2860 2861 return x86_perf_event_update(event); 2862 } 2863 2864 static void intel_pmu_reset(void) 2865 { 2866 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2867 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2868 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2869 int num_counters = hybrid(cpuc->pmu, num_counters); 2870 unsigned long flags; 2871 int idx; 2872 2873 if (!num_counters) 2874 return; 2875 2876 local_irq_save(flags); 2877 2878 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2879 2880 for (idx = 0; idx < num_counters; idx++) { 2881 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2882 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2883 } 2884 for (idx = 0; idx < num_counters_fixed; idx++) { 2885 if (fixed_counter_disabled(idx, cpuc->pmu)) 2886 continue; 2887 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2888 } 2889 2890 if (ds) 2891 ds->bts_index = ds->bts_buffer_base; 2892 2893 /* Ack all overflows and disable fixed counters */ 2894 if (x86_pmu.version >= 2) { 2895 intel_pmu_ack_status(intel_pmu_get_status()); 2896 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2897 } 2898 2899 /* Reset LBRs and LBR freezing */ 2900 if (x86_pmu.lbr_nr) { 2901 update_debugctlmsr(get_debugctlmsr() & 2902 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2903 } 2904 2905 local_irq_restore(flags); 2906 } 2907 2908 /* 2909 * We may be running with guest PEBS events created by KVM, and the 2910 * PEBS records are logged into the guest's DS and invisible to host. 2911 * 2912 * In the case of guest PEBS overflow, we only trigger a fake event 2913 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 2914 * The guest will then vm-entry and check the guest DS area to read 2915 * the guest PEBS records. 2916 * 2917 * The contents and other behavior of the guest event do not matter. 2918 */ 2919 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 2920 struct perf_sample_data *data) 2921 { 2922 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2923 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 2924 struct perf_event *event = NULL; 2925 int bit; 2926 2927 if (!unlikely(perf_guest_state())) 2928 return; 2929 2930 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 2931 !guest_pebs_idxs) 2932 return; 2933 2934 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, 2935 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) { 2936 event = cpuc->events[bit]; 2937 if (!event->attr.precise_ip) 2938 continue; 2939 2940 perf_sample_data_init(data, 0, event->hw.last_period); 2941 if (perf_event_overflow(event, data, regs)) 2942 x86_pmu_stop(event, 0); 2943 2944 /* Inject one fake event is enough. */ 2945 break; 2946 } 2947 } 2948 2949 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2950 { 2951 struct perf_sample_data data; 2952 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2953 int bit; 2954 int handled = 0; 2955 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2956 2957 inc_irq_stat(apic_perf_irqs); 2958 2959 /* 2960 * Ignore a range of extra bits in status that do not indicate 2961 * overflow by themselves. 2962 */ 2963 status &= ~(GLOBAL_STATUS_COND_CHG | 2964 GLOBAL_STATUS_ASIF | 2965 GLOBAL_STATUS_LBRS_FROZEN); 2966 if (!status) 2967 return 0; 2968 /* 2969 * In case multiple PEBS events are sampled at the same time, 2970 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2971 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2972 * having their bits set in the status register. This is a sign 2973 * that there was at least one PEBS record pending at the time 2974 * of the PMU interrupt. PEBS counters must only be processed 2975 * via the drain_pebs() calls and not via the regular sample 2976 * processing loop coming after that the function, otherwise 2977 * phony regular samples may be generated in the sampling buffer 2978 * not marked with the EXACT tag. Another possibility is to have 2979 * one PEBS event and at least one non-PEBS event which overflows 2980 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2981 * not be set, yet the overflow status bit for the PEBS counter will 2982 * be on Skylake. 2983 * 2984 * To avoid this problem, we systematically ignore the PEBS-enabled 2985 * counters from the GLOBAL_STATUS mask and we always process PEBS 2986 * events via drain_pebs(). 2987 */ 2988 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 2989 2990 /* 2991 * PEBS overflow sets bit 62 in the global status register 2992 */ 2993 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2994 u64 pebs_enabled = cpuc->pebs_enabled; 2995 2996 handled++; 2997 x86_pmu_handle_guest_pebs(regs, &data); 2998 x86_pmu.drain_pebs(regs, &data); 2999 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 3000 3001 /* 3002 * PMI throttle may be triggered, which stops the PEBS event. 3003 * Although cpuc->pebs_enabled is updated accordingly, the 3004 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3005 * cpuc->enabled has been forced to 0 in PMI. 3006 * Update the MSR if pebs_enabled is changed. 3007 */ 3008 if (pebs_enabled != cpuc->pebs_enabled) 3009 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3010 } 3011 3012 /* 3013 * Intel PT 3014 */ 3015 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3016 handled++; 3017 if (!perf_guest_handle_intel_pt_intr()) 3018 intel_pt_interrupt(); 3019 } 3020 3021 /* 3022 * Intel Perf metrics 3023 */ 3024 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3025 handled++; 3026 static_call(intel_pmu_update_topdown_event)(NULL); 3027 } 3028 3029 /* 3030 * Checkpointed counters can lead to 'spurious' PMIs because the 3031 * rollback caused by the PMI will have cleared the overflow status 3032 * bit. Therefore always force probe these counters. 3033 */ 3034 status |= cpuc->intel_cp_status; 3035 3036 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3037 struct perf_event *event = cpuc->events[bit]; 3038 3039 handled++; 3040 3041 if (!test_bit(bit, cpuc->active_mask)) 3042 continue; 3043 3044 if (!intel_pmu_save_and_restart(event)) 3045 continue; 3046 3047 perf_sample_data_init(&data, 0, event->hw.last_period); 3048 3049 if (has_branch_stack(event)) 3050 perf_sample_save_brstack(&data, event, &cpuc->lbr_stack); 3051 3052 if (perf_event_overflow(event, &data, regs)) 3053 x86_pmu_stop(event, 0); 3054 } 3055 3056 return handled; 3057 } 3058 3059 /* 3060 * This handler is triggered by the local APIC, so the APIC IRQ handling 3061 * rules apply: 3062 */ 3063 static int intel_pmu_handle_irq(struct pt_regs *regs) 3064 { 3065 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3066 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3067 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3068 int loops; 3069 u64 status; 3070 int handled; 3071 int pmu_enabled; 3072 3073 /* 3074 * Save the PMU state. 3075 * It needs to be restored when leaving the handler. 3076 */ 3077 pmu_enabled = cpuc->enabled; 3078 /* 3079 * In general, the early ACK is only applied for old platforms. 3080 * For the big core starts from Haswell, the late ACK should be 3081 * applied. 3082 * For the small core after Tremont, we have to do the ACK right 3083 * before re-enabling counters, which is in the middle of the 3084 * NMI handler. 3085 */ 3086 if (!late_ack && !mid_ack) 3087 apic_write(APIC_LVTPC, APIC_DM_NMI); 3088 intel_bts_disable_local(); 3089 cpuc->enabled = 0; 3090 __intel_pmu_disable_all(true); 3091 handled = intel_pmu_drain_bts_buffer(); 3092 handled += intel_bts_interrupt(); 3093 status = intel_pmu_get_status(); 3094 if (!status) 3095 goto done; 3096 3097 loops = 0; 3098 again: 3099 intel_pmu_lbr_read(); 3100 intel_pmu_ack_status(status); 3101 if (++loops > 100) { 3102 static bool warned; 3103 3104 if (!warned) { 3105 WARN(1, "perfevents: irq loop stuck!\n"); 3106 perf_event_print_debug(); 3107 warned = true; 3108 } 3109 intel_pmu_reset(); 3110 goto done; 3111 } 3112 3113 handled += handle_pmi_common(regs, status); 3114 3115 /* 3116 * Repeat if there is more work to be done: 3117 */ 3118 status = intel_pmu_get_status(); 3119 if (status) 3120 goto again; 3121 3122 done: 3123 if (mid_ack) 3124 apic_write(APIC_LVTPC, APIC_DM_NMI); 3125 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3126 cpuc->enabled = pmu_enabled; 3127 if (pmu_enabled) 3128 __intel_pmu_enable_all(0, true); 3129 intel_bts_enable_local(); 3130 3131 /* 3132 * Only unmask the NMI after the overflow counters 3133 * have been reset. This avoids spurious NMIs on 3134 * Haswell CPUs. 3135 */ 3136 if (late_ack) 3137 apic_write(APIC_LVTPC, APIC_DM_NMI); 3138 return handled; 3139 } 3140 3141 static struct event_constraint * 3142 intel_bts_constraints(struct perf_event *event) 3143 { 3144 if (unlikely(intel_pmu_has_bts(event))) 3145 return &bts_constraint; 3146 3147 return NULL; 3148 } 3149 3150 /* 3151 * Note: matches a fake event, like Fixed2. 3152 */ 3153 static struct event_constraint * 3154 intel_vlbr_constraints(struct perf_event *event) 3155 { 3156 struct event_constraint *c = &vlbr_constraint; 3157 3158 if (unlikely(constraint_match(c, event->hw.config))) { 3159 event->hw.flags |= c->flags; 3160 return c; 3161 } 3162 3163 return NULL; 3164 } 3165 3166 static int intel_alt_er(struct cpu_hw_events *cpuc, 3167 int idx, u64 config) 3168 { 3169 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3170 int alt_idx = idx; 3171 3172 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3173 return idx; 3174 3175 if (idx == EXTRA_REG_RSP_0) 3176 alt_idx = EXTRA_REG_RSP_1; 3177 3178 if (idx == EXTRA_REG_RSP_1) 3179 alt_idx = EXTRA_REG_RSP_0; 3180 3181 if (config & ~extra_regs[alt_idx].valid_mask) 3182 return idx; 3183 3184 return alt_idx; 3185 } 3186 3187 static void intel_fixup_er(struct perf_event *event, int idx) 3188 { 3189 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3190 event->hw.extra_reg.idx = idx; 3191 3192 if (idx == EXTRA_REG_RSP_0) { 3193 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3194 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3195 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3196 } else if (idx == EXTRA_REG_RSP_1) { 3197 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3198 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3199 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3200 } 3201 } 3202 3203 /* 3204 * manage allocation of shared extra msr for certain events 3205 * 3206 * sharing can be: 3207 * per-cpu: to be shared between the various events on a single PMU 3208 * per-core: per-cpu + shared by HT threads 3209 */ 3210 static struct event_constraint * 3211 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3212 struct perf_event *event, 3213 struct hw_perf_event_extra *reg) 3214 { 3215 struct event_constraint *c = &emptyconstraint; 3216 struct er_account *era; 3217 unsigned long flags; 3218 int idx = reg->idx; 3219 3220 /* 3221 * reg->alloc can be set due to existing state, so for fake cpuc we 3222 * need to ignore this, otherwise we might fail to allocate proper fake 3223 * state for this extra reg constraint. Also see the comment below. 3224 */ 3225 if (reg->alloc && !cpuc->is_fake) 3226 return NULL; /* call x86_get_event_constraint() */ 3227 3228 again: 3229 era = &cpuc->shared_regs->regs[idx]; 3230 /* 3231 * we use spin_lock_irqsave() to avoid lockdep issues when 3232 * passing a fake cpuc 3233 */ 3234 raw_spin_lock_irqsave(&era->lock, flags); 3235 3236 if (!atomic_read(&era->ref) || era->config == reg->config) { 3237 3238 /* 3239 * If its a fake cpuc -- as per validate_{group,event}() we 3240 * shouldn't touch event state and we can avoid doing so 3241 * since both will only call get_event_constraints() once 3242 * on each event, this avoids the need for reg->alloc. 3243 * 3244 * Not doing the ER fixup will only result in era->reg being 3245 * wrong, but since we won't actually try and program hardware 3246 * this isn't a problem either. 3247 */ 3248 if (!cpuc->is_fake) { 3249 if (idx != reg->idx) 3250 intel_fixup_er(event, idx); 3251 3252 /* 3253 * x86_schedule_events() can call get_event_constraints() 3254 * multiple times on events in the case of incremental 3255 * scheduling(). reg->alloc ensures we only do the ER 3256 * allocation once. 3257 */ 3258 reg->alloc = 1; 3259 } 3260 3261 /* lock in msr value */ 3262 era->config = reg->config; 3263 era->reg = reg->reg; 3264 3265 /* one more user */ 3266 atomic_inc(&era->ref); 3267 3268 /* 3269 * need to call x86_get_event_constraint() 3270 * to check if associated event has constraints 3271 */ 3272 c = NULL; 3273 } else { 3274 idx = intel_alt_er(cpuc, idx, reg->config); 3275 if (idx != reg->idx) { 3276 raw_spin_unlock_irqrestore(&era->lock, flags); 3277 goto again; 3278 } 3279 } 3280 raw_spin_unlock_irqrestore(&era->lock, flags); 3281 3282 return c; 3283 } 3284 3285 static void 3286 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3287 struct hw_perf_event_extra *reg) 3288 { 3289 struct er_account *era; 3290 3291 /* 3292 * Only put constraint if extra reg was actually allocated. Also takes 3293 * care of event which do not use an extra shared reg. 3294 * 3295 * Also, if this is a fake cpuc we shouldn't touch any event state 3296 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3297 * either since it'll be thrown out. 3298 */ 3299 if (!reg->alloc || cpuc->is_fake) 3300 return; 3301 3302 era = &cpuc->shared_regs->regs[reg->idx]; 3303 3304 /* one fewer user */ 3305 atomic_dec(&era->ref); 3306 3307 /* allocate again next time */ 3308 reg->alloc = 0; 3309 } 3310 3311 static struct event_constraint * 3312 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3313 struct perf_event *event) 3314 { 3315 struct event_constraint *c = NULL, *d; 3316 struct hw_perf_event_extra *xreg, *breg; 3317 3318 xreg = &event->hw.extra_reg; 3319 if (xreg->idx != EXTRA_REG_NONE) { 3320 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3321 if (c == &emptyconstraint) 3322 return c; 3323 } 3324 breg = &event->hw.branch_reg; 3325 if (breg->idx != EXTRA_REG_NONE) { 3326 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3327 if (d == &emptyconstraint) { 3328 __intel_shared_reg_put_constraints(cpuc, xreg); 3329 c = d; 3330 } 3331 } 3332 return c; 3333 } 3334 3335 struct event_constraint * 3336 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3337 struct perf_event *event) 3338 { 3339 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3340 struct event_constraint *c; 3341 3342 if (event_constraints) { 3343 for_each_event_constraint(c, event_constraints) { 3344 if (constraint_match(c, event->hw.config)) { 3345 event->hw.flags |= c->flags; 3346 return c; 3347 } 3348 } 3349 } 3350 3351 return &hybrid_var(cpuc->pmu, unconstrained); 3352 } 3353 3354 static struct event_constraint * 3355 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3356 struct perf_event *event) 3357 { 3358 struct event_constraint *c; 3359 3360 c = intel_vlbr_constraints(event); 3361 if (c) 3362 return c; 3363 3364 c = intel_bts_constraints(event); 3365 if (c) 3366 return c; 3367 3368 c = intel_shared_regs_constraints(cpuc, event); 3369 if (c) 3370 return c; 3371 3372 c = intel_pebs_constraints(event); 3373 if (c) 3374 return c; 3375 3376 return x86_get_event_constraints(cpuc, idx, event); 3377 } 3378 3379 static void 3380 intel_start_scheduling(struct cpu_hw_events *cpuc) 3381 { 3382 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3383 struct intel_excl_states *xl; 3384 int tid = cpuc->excl_thread_id; 3385 3386 /* 3387 * nothing needed if in group validation mode 3388 */ 3389 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3390 return; 3391 3392 /* 3393 * no exclusion needed 3394 */ 3395 if (WARN_ON_ONCE(!excl_cntrs)) 3396 return; 3397 3398 xl = &excl_cntrs->states[tid]; 3399 3400 xl->sched_started = true; 3401 /* 3402 * lock shared state until we are done scheduling 3403 * in stop_event_scheduling() 3404 * makes scheduling appear as a transaction 3405 */ 3406 raw_spin_lock(&excl_cntrs->lock); 3407 } 3408 3409 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3410 { 3411 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3412 struct event_constraint *c = cpuc->event_constraint[idx]; 3413 struct intel_excl_states *xl; 3414 int tid = cpuc->excl_thread_id; 3415 3416 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3417 return; 3418 3419 if (WARN_ON_ONCE(!excl_cntrs)) 3420 return; 3421 3422 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3423 return; 3424 3425 xl = &excl_cntrs->states[tid]; 3426 3427 lockdep_assert_held(&excl_cntrs->lock); 3428 3429 if (c->flags & PERF_X86_EVENT_EXCL) 3430 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3431 else 3432 xl->state[cntr] = INTEL_EXCL_SHARED; 3433 } 3434 3435 static void 3436 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3437 { 3438 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3439 struct intel_excl_states *xl; 3440 int tid = cpuc->excl_thread_id; 3441 3442 /* 3443 * nothing needed if in group validation mode 3444 */ 3445 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3446 return; 3447 /* 3448 * no exclusion needed 3449 */ 3450 if (WARN_ON_ONCE(!excl_cntrs)) 3451 return; 3452 3453 xl = &excl_cntrs->states[tid]; 3454 3455 xl->sched_started = false; 3456 /* 3457 * release shared state lock (acquired in intel_start_scheduling()) 3458 */ 3459 raw_spin_unlock(&excl_cntrs->lock); 3460 } 3461 3462 static struct event_constraint * 3463 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3464 { 3465 WARN_ON_ONCE(!cpuc->constraint_list); 3466 3467 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3468 struct event_constraint *cx; 3469 3470 /* 3471 * grab pre-allocated constraint entry 3472 */ 3473 cx = &cpuc->constraint_list[idx]; 3474 3475 /* 3476 * initialize dynamic constraint 3477 * with static constraint 3478 */ 3479 *cx = *c; 3480 3481 /* 3482 * mark constraint as dynamic 3483 */ 3484 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3485 c = cx; 3486 } 3487 3488 return c; 3489 } 3490 3491 static struct event_constraint * 3492 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3493 int idx, struct event_constraint *c) 3494 { 3495 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3496 struct intel_excl_states *xlo; 3497 int tid = cpuc->excl_thread_id; 3498 int is_excl, i, w; 3499 3500 /* 3501 * validating a group does not require 3502 * enforcing cross-thread exclusion 3503 */ 3504 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3505 return c; 3506 3507 /* 3508 * no exclusion needed 3509 */ 3510 if (WARN_ON_ONCE(!excl_cntrs)) 3511 return c; 3512 3513 /* 3514 * because we modify the constraint, we need 3515 * to make a copy. Static constraints come 3516 * from static const tables. 3517 * 3518 * only needed when constraint has not yet 3519 * been cloned (marked dynamic) 3520 */ 3521 c = dyn_constraint(cpuc, c, idx); 3522 3523 /* 3524 * From here on, the constraint is dynamic. 3525 * Either it was just allocated above, or it 3526 * was allocated during a earlier invocation 3527 * of this function 3528 */ 3529 3530 /* 3531 * state of sibling HT 3532 */ 3533 xlo = &excl_cntrs->states[tid ^ 1]; 3534 3535 /* 3536 * event requires exclusive counter access 3537 * across HT threads 3538 */ 3539 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3540 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3541 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3542 if (!cpuc->n_excl++) 3543 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3544 } 3545 3546 /* 3547 * Modify static constraint with current dynamic 3548 * state of thread 3549 * 3550 * EXCLUSIVE: sibling counter measuring exclusive event 3551 * SHARED : sibling counter measuring non-exclusive event 3552 * UNUSED : sibling counter unused 3553 */ 3554 w = c->weight; 3555 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3556 /* 3557 * exclusive event in sibling counter 3558 * our corresponding counter cannot be used 3559 * regardless of our event 3560 */ 3561 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3562 __clear_bit(i, c->idxmsk); 3563 w--; 3564 continue; 3565 } 3566 /* 3567 * if measuring an exclusive event, sibling 3568 * measuring non-exclusive, then counter cannot 3569 * be used 3570 */ 3571 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3572 __clear_bit(i, c->idxmsk); 3573 w--; 3574 continue; 3575 } 3576 } 3577 3578 /* 3579 * if we return an empty mask, then switch 3580 * back to static empty constraint to avoid 3581 * the cost of freeing later on 3582 */ 3583 if (!w) 3584 c = &emptyconstraint; 3585 3586 c->weight = w; 3587 3588 return c; 3589 } 3590 3591 static struct event_constraint * 3592 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3593 struct perf_event *event) 3594 { 3595 struct event_constraint *c1, *c2; 3596 3597 c1 = cpuc->event_constraint[idx]; 3598 3599 /* 3600 * first time only 3601 * - static constraint: no change across incremental scheduling calls 3602 * - dynamic constraint: handled by intel_get_excl_constraints() 3603 */ 3604 c2 = __intel_get_event_constraints(cpuc, idx, event); 3605 if (c1) { 3606 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3607 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3608 c1->weight = c2->weight; 3609 c2 = c1; 3610 } 3611 3612 if (cpuc->excl_cntrs) 3613 return intel_get_excl_constraints(cpuc, event, idx, c2); 3614 3615 return c2; 3616 } 3617 3618 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3619 struct perf_event *event) 3620 { 3621 struct hw_perf_event *hwc = &event->hw; 3622 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3623 int tid = cpuc->excl_thread_id; 3624 struct intel_excl_states *xl; 3625 3626 /* 3627 * nothing needed if in group validation mode 3628 */ 3629 if (cpuc->is_fake) 3630 return; 3631 3632 if (WARN_ON_ONCE(!excl_cntrs)) 3633 return; 3634 3635 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3636 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3637 if (!--cpuc->n_excl) 3638 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3639 } 3640 3641 /* 3642 * If event was actually assigned, then mark the counter state as 3643 * unused now. 3644 */ 3645 if (hwc->idx >= 0) { 3646 xl = &excl_cntrs->states[tid]; 3647 3648 /* 3649 * put_constraint may be called from x86_schedule_events() 3650 * which already has the lock held so here make locking 3651 * conditional. 3652 */ 3653 if (!xl->sched_started) 3654 raw_spin_lock(&excl_cntrs->lock); 3655 3656 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3657 3658 if (!xl->sched_started) 3659 raw_spin_unlock(&excl_cntrs->lock); 3660 } 3661 } 3662 3663 static void 3664 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3665 struct perf_event *event) 3666 { 3667 struct hw_perf_event_extra *reg; 3668 3669 reg = &event->hw.extra_reg; 3670 if (reg->idx != EXTRA_REG_NONE) 3671 __intel_shared_reg_put_constraints(cpuc, reg); 3672 3673 reg = &event->hw.branch_reg; 3674 if (reg->idx != EXTRA_REG_NONE) 3675 __intel_shared_reg_put_constraints(cpuc, reg); 3676 } 3677 3678 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3679 struct perf_event *event) 3680 { 3681 intel_put_shared_regs_event_constraints(cpuc, event); 3682 3683 /* 3684 * is PMU has exclusive counter restrictions, then 3685 * all events are subject to and must call the 3686 * put_excl_constraints() routine 3687 */ 3688 if (cpuc->excl_cntrs) 3689 intel_put_excl_constraints(cpuc, event); 3690 } 3691 3692 static void intel_pebs_aliases_core2(struct perf_event *event) 3693 { 3694 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3695 /* 3696 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3697 * (0x003c) so that we can use it with PEBS. 3698 * 3699 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3700 * PEBS capable. However we can use INST_RETIRED.ANY_P 3701 * (0x00c0), which is a PEBS capable event, to get the same 3702 * count. 3703 * 3704 * INST_RETIRED.ANY_P counts the number of cycles that retires 3705 * CNTMASK instructions. By setting CNTMASK to a value (16) 3706 * larger than the maximum number of instructions that can be 3707 * retired per cycle (4) and then inverting the condition, we 3708 * count all cycles that retire 16 or less instructions, which 3709 * is every cycle. 3710 * 3711 * Thereby we gain a PEBS capable cycle counter. 3712 */ 3713 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3714 3715 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3716 event->hw.config = alt_config; 3717 } 3718 } 3719 3720 static void intel_pebs_aliases_snb(struct perf_event *event) 3721 { 3722 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3723 /* 3724 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3725 * (0x003c) so that we can use it with PEBS. 3726 * 3727 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3728 * PEBS capable. However we can use UOPS_RETIRED.ALL 3729 * (0x01c2), which is a PEBS capable event, to get the same 3730 * count. 3731 * 3732 * UOPS_RETIRED.ALL counts the number of cycles that retires 3733 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3734 * larger than the maximum number of micro-ops that can be 3735 * retired per cycle (4) and then inverting the condition, we 3736 * count all cycles that retire 16 or less micro-ops, which 3737 * is every cycle. 3738 * 3739 * Thereby we gain a PEBS capable cycle counter. 3740 */ 3741 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3742 3743 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3744 event->hw.config = alt_config; 3745 } 3746 } 3747 3748 static void intel_pebs_aliases_precdist(struct perf_event *event) 3749 { 3750 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3751 /* 3752 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3753 * (0x003c) so that we can use it with PEBS. 3754 * 3755 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3756 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3757 * (0x01c0), which is a PEBS capable event, to get the same 3758 * count. 3759 * 3760 * The PREC_DIST event has special support to minimize sample 3761 * shadowing effects. One drawback is that it can be 3762 * only programmed on counter 1, but that seems like an 3763 * acceptable trade off. 3764 */ 3765 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3766 3767 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3768 event->hw.config = alt_config; 3769 } 3770 } 3771 3772 static void intel_pebs_aliases_ivb(struct perf_event *event) 3773 { 3774 if (event->attr.precise_ip < 3) 3775 return intel_pebs_aliases_snb(event); 3776 return intel_pebs_aliases_precdist(event); 3777 } 3778 3779 static void intel_pebs_aliases_skl(struct perf_event *event) 3780 { 3781 if (event->attr.precise_ip < 3) 3782 return intel_pebs_aliases_core2(event); 3783 return intel_pebs_aliases_precdist(event); 3784 } 3785 3786 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3787 { 3788 unsigned long flags = x86_pmu.large_pebs_flags; 3789 3790 if (event->attr.use_clockid) 3791 flags &= ~PERF_SAMPLE_TIME; 3792 if (!event->attr.exclude_kernel) 3793 flags &= ~PERF_SAMPLE_REGS_USER; 3794 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3795 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3796 return flags; 3797 } 3798 3799 static int intel_pmu_bts_config(struct perf_event *event) 3800 { 3801 struct perf_event_attr *attr = &event->attr; 3802 3803 if (unlikely(intel_pmu_has_bts(event))) { 3804 /* BTS is not supported by this architecture. */ 3805 if (!x86_pmu.bts_active) 3806 return -EOPNOTSUPP; 3807 3808 /* BTS is currently only allowed for user-mode. */ 3809 if (!attr->exclude_kernel) 3810 return -EOPNOTSUPP; 3811 3812 /* BTS is not allowed for precise events. */ 3813 if (attr->precise_ip) 3814 return -EOPNOTSUPP; 3815 3816 /* disallow bts if conflicting events are present */ 3817 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3818 return -EBUSY; 3819 3820 event->destroy = hw_perf_lbr_event_destroy; 3821 } 3822 3823 return 0; 3824 } 3825 3826 static int core_pmu_hw_config(struct perf_event *event) 3827 { 3828 int ret = x86_pmu_hw_config(event); 3829 3830 if (ret) 3831 return ret; 3832 3833 return intel_pmu_bts_config(event); 3834 } 3835 3836 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3837 ((x86_pmu.num_topdown_events - 1) << 8)) 3838 3839 static bool is_available_metric_event(struct perf_event *event) 3840 { 3841 return is_metric_event(event) && 3842 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3843 } 3844 3845 static inline bool is_mem_loads_event(struct perf_event *event) 3846 { 3847 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3848 } 3849 3850 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3851 { 3852 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3853 } 3854 3855 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3856 { 3857 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3858 return false; 3859 3860 if (is_hybrid()) 3861 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3862 3863 return true; 3864 } 3865 3866 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3867 { 3868 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3869 3870 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3871 } 3872 3873 static int intel_pmu_hw_config(struct perf_event *event) 3874 { 3875 int ret = x86_pmu_hw_config(event); 3876 3877 if (ret) 3878 return ret; 3879 3880 ret = intel_pmu_bts_config(event); 3881 if (ret) 3882 return ret; 3883 3884 if (event->attr.precise_ip) { 3885 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3886 return -EINVAL; 3887 3888 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3889 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3890 if (!(event->attr.sample_type & 3891 ~intel_pmu_large_pebs_flags(event))) { 3892 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3893 event->attach_state |= PERF_ATTACH_SCHED_CB; 3894 } 3895 } 3896 if (x86_pmu.pebs_aliases) 3897 x86_pmu.pebs_aliases(event); 3898 } 3899 3900 if (needs_branch_stack(event)) { 3901 ret = intel_pmu_setup_lbr_filter(event); 3902 if (ret) 3903 return ret; 3904 event->attach_state |= PERF_ATTACH_SCHED_CB; 3905 3906 /* 3907 * BTS is set up earlier in this path, so don't account twice 3908 */ 3909 if (!unlikely(intel_pmu_has_bts(event))) { 3910 /* disallow lbr if conflicting events are present */ 3911 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3912 return -EBUSY; 3913 3914 event->destroy = hw_perf_lbr_event_destroy; 3915 } 3916 } 3917 3918 if (event->attr.aux_output) { 3919 if (!event->attr.precise_ip) 3920 return -EINVAL; 3921 3922 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3923 } 3924 3925 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3926 (event->attr.type == PERF_TYPE_HW_CACHE)) 3927 return 0; 3928 3929 /* 3930 * Config Topdown slots and metric events 3931 * 3932 * The slots event on Fixed Counter 3 can support sampling, 3933 * which will be handled normally in x86_perf_event_update(). 3934 * 3935 * Metric events don't support sampling and require being paired 3936 * with a slots event as group leader. When the slots event 3937 * is used in a metrics group, it too cannot support sampling. 3938 */ 3939 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3940 if (event->attr.config1 || event->attr.config2) 3941 return -EINVAL; 3942 3943 /* 3944 * The TopDown metrics events and slots event don't 3945 * support any filters. 3946 */ 3947 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3948 return -EINVAL; 3949 3950 if (is_available_metric_event(event)) { 3951 struct perf_event *leader = event->group_leader; 3952 3953 /* The metric events don't support sampling. */ 3954 if (is_sampling_event(event)) 3955 return -EINVAL; 3956 3957 /* The metric events require a slots group leader. */ 3958 if (!is_slots_event(leader)) 3959 return -EINVAL; 3960 3961 /* 3962 * The leader/SLOTS must not be a sampling event for 3963 * metric use; hardware requires it starts at 0 when used 3964 * in conjunction with MSR_PERF_METRICS. 3965 */ 3966 if (is_sampling_event(leader)) 3967 return -EINVAL; 3968 3969 event->event_caps |= PERF_EV_CAP_SIBLING; 3970 /* 3971 * Only once we have a METRICs sibling do we 3972 * need TopDown magic. 3973 */ 3974 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3975 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3976 } 3977 } 3978 3979 /* 3980 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3981 * doesn't function quite right. As a work-around it needs to always be 3982 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3983 * The actual count of this second event is irrelevant it just needs 3984 * to be active to make the first event function correctly. 3985 * 3986 * In a group, the auxiliary event must be in front of the load latency 3987 * event. The rule is to simplify the implementation of the check. 3988 * That's because perf cannot have a complete group at the moment. 3989 */ 3990 if (require_mem_loads_aux_event(event) && 3991 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3992 is_mem_loads_event(event)) { 3993 struct perf_event *leader = event->group_leader; 3994 struct perf_event *sibling = NULL; 3995 3996 if (!is_mem_loads_aux_event(leader)) { 3997 for_each_sibling_event(sibling, leader) { 3998 if (is_mem_loads_aux_event(sibling)) 3999 break; 4000 } 4001 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4002 return -ENODATA; 4003 } 4004 } 4005 4006 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4007 return 0; 4008 4009 if (x86_pmu.version < 3) 4010 return -EINVAL; 4011 4012 ret = perf_allow_cpu(&event->attr); 4013 if (ret) 4014 return ret; 4015 4016 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4017 4018 return 0; 4019 } 4020 4021 /* 4022 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4023 * The host perf conext helps to prepare the values of the real hardware for 4024 * a set of msrs that need to be switched atomically in a vmx transaction. 4025 * 4026 * For example, the pseudocode needed to add a new msr should look like: 4027 * 4028 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4029 * .msr = the hardware msr address, 4030 * .host = the value the hardware has when it doesn't run a guest, 4031 * .guest = the value the hardware has when it runs a guest, 4032 * }; 4033 * 4034 * These values have nothing to do with the emulated values the guest sees 4035 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4036 * specifically in the intel_pmu_{get,set}_msr(). 4037 */ 4038 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4039 { 4040 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4041 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4042 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4043 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4044 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4045 int global_ctrl, pebs_enable; 4046 4047 *nr = 0; 4048 global_ctrl = (*nr)++; 4049 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4050 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4051 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4052 .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask), 4053 }; 4054 4055 if (!x86_pmu.pebs) 4056 return arr; 4057 4058 /* 4059 * If PMU counter has PEBS enabled it is not enough to 4060 * disable counter on a guest entry since PEBS memory 4061 * write can overshoot guest entry and corrupt guest 4062 * memory. Disabling PEBS solves the problem. 4063 * 4064 * Don't do this if the CPU already enforces it. 4065 */ 4066 if (x86_pmu.pebs_no_isolation) { 4067 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4068 .msr = MSR_IA32_PEBS_ENABLE, 4069 .host = cpuc->pebs_enabled, 4070 .guest = 0, 4071 }; 4072 return arr; 4073 } 4074 4075 if (!kvm_pmu || !x86_pmu.pebs_ept) 4076 return arr; 4077 4078 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4079 .msr = MSR_IA32_DS_AREA, 4080 .host = (unsigned long)cpuc->ds, 4081 .guest = kvm_pmu->ds_area, 4082 }; 4083 4084 if (x86_pmu.intel_cap.pebs_baseline) { 4085 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4086 .msr = MSR_PEBS_DATA_CFG, 4087 .host = cpuc->active_pebs_data_cfg, 4088 .guest = kvm_pmu->pebs_data_cfg, 4089 }; 4090 } 4091 4092 pebs_enable = (*nr)++; 4093 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4094 .msr = MSR_IA32_PEBS_ENABLE, 4095 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4096 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, 4097 }; 4098 4099 if (arr[pebs_enable].host) { 4100 /* Disable guest PEBS if host PEBS is enabled. */ 4101 arr[pebs_enable].guest = 0; 4102 } else { 4103 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4104 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4105 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4106 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4107 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4108 } 4109 4110 return arr; 4111 } 4112 4113 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4114 { 4115 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4116 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4117 int idx; 4118 4119 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4120 struct perf_event *event = cpuc->events[idx]; 4121 4122 arr[idx].msr = x86_pmu_config_addr(idx); 4123 arr[idx].host = arr[idx].guest = 0; 4124 4125 if (!test_bit(idx, cpuc->active_mask)) 4126 continue; 4127 4128 arr[idx].host = arr[idx].guest = 4129 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4130 4131 if (event->attr.exclude_host) 4132 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4133 else if (event->attr.exclude_guest) 4134 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4135 } 4136 4137 *nr = x86_pmu.num_counters; 4138 return arr; 4139 } 4140 4141 static void core_pmu_enable_event(struct perf_event *event) 4142 { 4143 if (!event->attr.exclude_host) 4144 x86_pmu_enable_event(event); 4145 } 4146 4147 static void core_pmu_enable_all(int added) 4148 { 4149 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4150 int idx; 4151 4152 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4153 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4154 4155 if (!test_bit(idx, cpuc->active_mask) || 4156 cpuc->events[idx]->attr.exclude_host) 4157 continue; 4158 4159 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4160 } 4161 } 4162 4163 static int hsw_hw_config(struct perf_event *event) 4164 { 4165 int ret = intel_pmu_hw_config(event); 4166 4167 if (ret) 4168 return ret; 4169 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4170 return 0; 4171 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4172 4173 /* 4174 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4175 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4176 * this combination. 4177 */ 4178 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4179 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4180 event->attr.precise_ip > 0)) 4181 return -EOPNOTSUPP; 4182 4183 if (event_is_checkpointed(event)) { 4184 /* 4185 * Sampling of checkpointed events can cause situations where 4186 * the CPU constantly aborts because of a overflow, which is 4187 * then checkpointed back and ignored. Forbid checkpointing 4188 * for sampling. 4189 * 4190 * But still allow a long sampling period, so that perf stat 4191 * from KVM works. 4192 */ 4193 if (event->attr.sample_period > 0 && 4194 event->attr.sample_period < 0x7fffffff) 4195 return -EOPNOTSUPP; 4196 } 4197 return 0; 4198 } 4199 4200 static struct event_constraint counter0_constraint = 4201 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4202 4203 static struct event_constraint counter1_constraint = 4204 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4205 4206 static struct event_constraint counter0_1_constraint = 4207 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4208 4209 static struct event_constraint counter2_constraint = 4210 EVENT_CONSTRAINT(0, 0x4, 0); 4211 4212 static struct event_constraint fixed0_constraint = 4213 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4214 4215 static struct event_constraint fixed0_counter0_constraint = 4216 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4217 4218 static struct event_constraint fixed0_counter0_1_constraint = 4219 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4220 4221 static struct event_constraint counters_1_7_constraint = 4222 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4223 4224 static struct event_constraint * 4225 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4226 struct perf_event *event) 4227 { 4228 struct event_constraint *c; 4229 4230 c = intel_get_event_constraints(cpuc, idx, event); 4231 4232 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4233 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4234 if (c->idxmsk64 & (1U << 2)) 4235 return &counter2_constraint; 4236 return &emptyconstraint; 4237 } 4238 4239 return c; 4240 } 4241 4242 static struct event_constraint * 4243 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4244 struct perf_event *event) 4245 { 4246 /* 4247 * Fixed counter 0 has less skid. 4248 * Force instruction:ppp in Fixed counter 0 4249 */ 4250 if ((event->attr.precise_ip == 3) && 4251 constraint_match(&fixed0_constraint, event->hw.config)) 4252 return &fixed0_constraint; 4253 4254 return hsw_get_event_constraints(cpuc, idx, event); 4255 } 4256 4257 static struct event_constraint * 4258 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4259 struct perf_event *event) 4260 { 4261 struct event_constraint *c; 4262 4263 c = icl_get_event_constraints(cpuc, idx, event); 4264 4265 /* 4266 * The :ppp indicates the Precise Distribution (PDist) facility, which 4267 * is only supported on the GP counter 0. If a :ppp event which is not 4268 * available on the GP counter 0, error out. 4269 * Exception: Instruction PDIR is only available on the fixed counter 0. 4270 */ 4271 if ((event->attr.precise_ip == 3) && 4272 !constraint_match(&fixed0_constraint, event->hw.config)) { 4273 if (c->idxmsk64 & BIT_ULL(0)) 4274 return &counter0_constraint; 4275 4276 return &emptyconstraint; 4277 } 4278 4279 return c; 4280 } 4281 4282 static struct event_constraint * 4283 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4284 struct perf_event *event) 4285 { 4286 struct event_constraint *c; 4287 4288 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4289 if (event->attr.precise_ip == 3) 4290 return &counter0_constraint; 4291 4292 c = intel_get_event_constraints(cpuc, idx, event); 4293 4294 return c; 4295 } 4296 4297 static struct event_constraint * 4298 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4299 struct perf_event *event) 4300 { 4301 struct event_constraint *c; 4302 4303 c = intel_get_event_constraints(cpuc, idx, event); 4304 4305 /* 4306 * :ppp means to do reduced skid PEBS, 4307 * which is available on PMC0 and fixed counter 0. 4308 */ 4309 if (event->attr.precise_ip == 3) { 4310 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4311 if (constraint_match(&fixed0_constraint, event->hw.config)) 4312 return &fixed0_counter0_constraint; 4313 4314 return &counter0_constraint; 4315 } 4316 4317 return c; 4318 } 4319 4320 static bool allow_tsx_force_abort = true; 4321 4322 static struct event_constraint * 4323 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4324 struct perf_event *event) 4325 { 4326 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4327 4328 /* 4329 * Without TFA we must not use PMC3. 4330 */ 4331 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4332 c = dyn_constraint(cpuc, c, idx); 4333 c->idxmsk64 &= ~(1ULL << 3); 4334 c->weight--; 4335 } 4336 4337 return c; 4338 } 4339 4340 static struct event_constraint * 4341 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4342 struct perf_event *event) 4343 { 4344 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4345 4346 if (pmu->cpu_type == hybrid_big) 4347 return spr_get_event_constraints(cpuc, idx, event); 4348 else if (pmu->cpu_type == hybrid_small) 4349 return tnt_get_event_constraints(cpuc, idx, event); 4350 4351 WARN_ON(1); 4352 return &emptyconstraint; 4353 } 4354 4355 static struct event_constraint * 4356 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4357 struct perf_event *event) 4358 { 4359 struct event_constraint *c; 4360 4361 c = intel_get_event_constraints(cpuc, idx, event); 4362 4363 /* 4364 * The :ppp indicates the Precise Distribution (PDist) facility, which 4365 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 4366 * If a :ppp event which is not available on the above eligible counters, 4367 * error out. 4368 */ 4369 if (event->attr.precise_ip == 3) { 4370 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 4371 if (constraint_match(&fixed0_constraint, event->hw.config)) 4372 return &fixed0_counter0_1_constraint; 4373 4374 switch (c->idxmsk64 & 0x3ull) { 4375 case 0x1: 4376 return &counter0_constraint; 4377 case 0x2: 4378 return &counter1_constraint; 4379 case 0x3: 4380 return &counter0_1_constraint; 4381 } 4382 return &emptyconstraint; 4383 } 4384 4385 return c; 4386 } 4387 4388 static struct event_constraint * 4389 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4390 struct perf_event *event) 4391 { 4392 struct event_constraint *c; 4393 4394 c = spr_get_event_constraints(cpuc, idx, event); 4395 4396 /* The Retire Latency is not supported by the fixed counter 0. */ 4397 if (event->attr.precise_ip && 4398 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 4399 constraint_match(&fixed0_constraint, event->hw.config)) { 4400 /* 4401 * The Instruction PDIR is only available 4402 * on the fixed counter 0. Error out for this case. 4403 */ 4404 if (event->attr.precise_ip == 3) 4405 return &emptyconstraint; 4406 return &counters_1_7_constraint; 4407 } 4408 4409 return c; 4410 } 4411 4412 static struct event_constraint * 4413 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4414 struct perf_event *event) 4415 { 4416 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4417 4418 if (pmu->cpu_type == hybrid_big) 4419 return rwc_get_event_constraints(cpuc, idx, event); 4420 if (pmu->cpu_type == hybrid_small) 4421 return cmt_get_event_constraints(cpuc, idx, event); 4422 4423 WARN_ON(1); 4424 return &emptyconstraint; 4425 } 4426 4427 static int adl_hw_config(struct perf_event *event) 4428 { 4429 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4430 4431 if (pmu->cpu_type == hybrid_big) 4432 return hsw_hw_config(event); 4433 else if (pmu->cpu_type == hybrid_small) 4434 return intel_pmu_hw_config(event); 4435 4436 WARN_ON(1); 4437 return -EOPNOTSUPP; 4438 } 4439 4440 static u8 adl_get_hybrid_cpu_type(void) 4441 { 4442 return hybrid_big; 4443 } 4444 4445 /* 4446 * Broadwell: 4447 * 4448 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4449 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4450 * the two to enforce a minimum period of 128 (the smallest value that has bits 4451 * 0-5 cleared and >= 100). 4452 * 4453 * Because of how the code in x86_perf_event_set_period() works, the truncation 4454 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4455 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4456 * 4457 * Therefore the effective (average) period matches the requested period, 4458 * despite coarser hardware granularity. 4459 */ 4460 static void bdw_limit_period(struct perf_event *event, s64 *left) 4461 { 4462 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4463 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4464 if (*left < 128) 4465 *left = 128; 4466 *left &= ~0x3fULL; 4467 } 4468 } 4469 4470 static void nhm_limit_period(struct perf_event *event, s64 *left) 4471 { 4472 *left = max(*left, 32LL); 4473 } 4474 4475 static void spr_limit_period(struct perf_event *event, s64 *left) 4476 { 4477 if (event->attr.precise_ip == 3) 4478 *left = max(*left, 128LL); 4479 } 4480 4481 PMU_FORMAT_ATTR(event, "config:0-7" ); 4482 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4483 PMU_FORMAT_ATTR(edge, "config:18" ); 4484 PMU_FORMAT_ATTR(pc, "config:19" ); 4485 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4486 PMU_FORMAT_ATTR(inv, "config:23" ); 4487 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4488 PMU_FORMAT_ATTR(in_tx, "config:32"); 4489 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4490 4491 static struct attribute *intel_arch_formats_attr[] = { 4492 &format_attr_event.attr, 4493 &format_attr_umask.attr, 4494 &format_attr_edge.attr, 4495 &format_attr_pc.attr, 4496 &format_attr_inv.attr, 4497 &format_attr_cmask.attr, 4498 NULL, 4499 }; 4500 4501 ssize_t intel_event_sysfs_show(char *page, u64 config) 4502 { 4503 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4504 4505 return x86_event_sysfs_show(page, config, event); 4506 } 4507 4508 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4509 { 4510 struct intel_shared_regs *regs; 4511 int i; 4512 4513 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4514 GFP_KERNEL, cpu_to_node(cpu)); 4515 if (regs) { 4516 /* 4517 * initialize the locks to keep lockdep happy 4518 */ 4519 for (i = 0; i < EXTRA_REG_MAX; i++) 4520 raw_spin_lock_init(®s->regs[i].lock); 4521 4522 regs->core_id = -1; 4523 } 4524 return regs; 4525 } 4526 4527 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4528 { 4529 struct intel_excl_cntrs *c; 4530 4531 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4532 GFP_KERNEL, cpu_to_node(cpu)); 4533 if (c) { 4534 raw_spin_lock_init(&c->lock); 4535 c->core_id = -1; 4536 } 4537 return c; 4538 } 4539 4540 4541 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4542 { 4543 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4544 4545 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4546 cpuc->shared_regs = allocate_shared_regs(cpu); 4547 if (!cpuc->shared_regs) 4548 goto err; 4549 } 4550 4551 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4552 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4553 4554 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4555 if (!cpuc->constraint_list) 4556 goto err_shared_regs; 4557 } 4558 4559 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4560 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4561 if (!cpuc->excl_cntrs) 4562 goto err_constraint_list; 4563 4564 cpuc->excl_thread_id = 0; 4565 } 4566 4567 return 0; 4568 4569 err_constraint_list: 4570 kfree(cpuc->constraint_list); 4571 cpuc->constraint_list = NULL; 4572 4573 err_shared_regs: 4574 kfree(cpuc->shared_regs); 4575 cpuc->shared_regs = NULL; 4576 4577 err: 4578 return -ENOMEM; 4579 } 4580 4581 static int intel_pmu_cpu_prepare(int cpu) 4582 { 4583 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4584 } 4585 4586 static void flip_smm_bit(void *data) 4587 { 4588 unsigned long set = *(unsigned long *)data; 4589 4590 if (set > 0) { 4591 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4592 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4593 } else { 4594 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4595 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4596 } 4597 } 4598 4599 static void intel_pmu_check_num_counters(int *num_counters, 4600 int *num_counters_fixed, 4601 u64 *intel_ctrl, u64 fixed_mask); 4602 4603 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) 4604 { 4605 unsigned int sub_bitmaps = cpuid_eax(ARCH_PERFMON_EXT_LEAF); 4606 unsigned int eax, ebx, ecx, edx; 4607 4608 if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { 4609 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 4610 &eax, &ebx, &ecx, &edx); 4611 pmu->num_counters = fls(eax); 4612 pmu->num_counters_fixed = fls(ebx); 4613 intel_pmu_check_num_counters(&pmu->num_counters, &pmu->num_counters_fixed, 4614 &pmu->intel_ctrl, ebx); 4615 } 4616 } 4617 4618 static bool init_hybrid_pmu(int cpu) 4619 { 4620 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4621 u8 cpu_type = get_this_hybrid_cpu_type(); 4622 struct x86_hybrid_pmu *pmu = NULL; 4623 int i; 4624 4625 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4626 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4627 4628 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4629 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4630 pmu = &x86_pmu.hybrid_pmu[i]; 4631 break; 4632 } 4633 } 4634 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4635 cpuc->pmu = NULL; 4636 return false; 4637 } 4638 4639 /* Only check and dump the PMU information for the first CPU */ 4640 if (!cpumask_empty(&pmu->supported_cpus)) 4641 goto end; 4642 4643 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 4644 update_pmu_cap(pmu); 4645 4646 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4647 return false; 4648 4649 pr_info("%s PMU driver: ", pmu->name); 4650 4651 if (pmu->intel_cap.pebs_output_pt_available) 4652 pr_cont("PEBS-via-PT "); 4653 4654 pr_cont("\n"); 4655 4656 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4657 pmu->intel_ctrl); 4658 4659 end: 4660 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4661 cpuc->pmu = &pmu->pmu; 4662 4663 return true; 4664 } 4665 4666 static void intel_pmu_cpu_starting(int cpu) 4667 { 4668 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4669 int core_id = topology_core_id(cpu); 4670 int i; 4671 4672 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4673 return; 4674 4675 init_debug_store_on_cpu(cpu); 4676 /* 4677 * Deal with CPUs that don't clear their LBRs on power-up. 4678 */ 4679 intel_pmu_lbr_reset(); 4680 4681 cpuc->lbr_sel = NULL; 4682 4683 if (x86_pmu.flags & PMU_FL_TFA) { 4684 WARN_ON_ONCE(cpuc->tfa_shadow); 4685 cpuc->tfa_shadow = ~0ULL; 4686 intel_set_tfa(cpuc, false); 4687 } 4688 4689 if (x86_pmu.version > 1) 4690 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4691 4692 /* 4693 * Disable perf metrics if any added CPU doesn't support it. 4694 * 4695 * Turn off the check for a hybrid architecture, because the 4696 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4697 * the architecture features. The perf metrics is a model-specific 4698 * feature for now. The corresponding bit should always be 0 on 4699 * a hybrid platform, e.g., Alder Lake. 4700 */ 4701 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4702 union perf_capabilities perf_cap; 4703 4704 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4705 if (!perf_cap.perf_metrics) { 4706 x86_pmu.intel_cap.perf_metrics = 0; 4707 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4708 } 4709 } 4710 4711 if (!cpuc->shared_regs) 4712 return; 4713 4714 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4715 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4716 struct intel_shared_regs *pc; 4717 4718 pc = per_cpu(cpu_hw_events, i).shared_regs; 4719 if (pc && pc->core_id == core_id) { 4720 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4721 cpuc->shared_regs = pc; 4722 break; 4723 } 4724 } 4725 cpuc->shared_regs->core_id = core_id; 4726 cpuc->shared_regs->refcnt++; 4727 } 4728 4729 if (x86_pmu.lbr_sel_map) 4730 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4731 4732 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4733 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4734 struct cpu_hw_events *sibling; 4735 struct intel_excl_cntrs *c; 4736 4737 sibling = &per_cpu(cpu_hw_events, i); 4738 c = sibling->excl_cntrs; 4739 if (c && c->core_id == core_id) { 4740 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4741 cpuc->excl_cntrs = c; 4742 if (!sibling->excl_thread_id) 4743 cpuc->excl_thread_id = 1; 4744 break; 4745 } 4746 } 4747 cpuc->excl_cntrs->core_id = core_id; 4748 cpuc->excl_cntrs->refcnt++; 4749 } 4750 } 4751 4752 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4753 { 4754 struct intel_excl_cntrs *c; 4755 4756 c = cpuc->excl_cntrs; 4757 if (c) { 4758 if (c->core_id == -1 || --c->refcnt == 0) 4759 kfree(c); 4760 cpuc->excl_cntrs = NULL; 4761 } 4762 4763 kfree(cpuc->constraint_list); 4764 cpuc->constraint_list = NULL; 4765 } 4766 4767 static void intel_pmu_cpu_dying(int cpu) 4768 { 4769 fini_debug_store_on_cpu(cpu); 4770 } 4771 4772 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4773 { 4774 struct intel_shared_regs *pc; 4775 4776 pc = cpuc->shared_regs; 4777 if (pc) { 4778 if (pc->core_id == -1 || --pc->refcnt == 0) 4779 kfree(pc); 4780 cpuc->shared_regs = NULL; 4781 } 4782 4783 free_excl_cntrs(cpuc); 4784 } 4785 4786 static void intel_pmu_cpu_dead(int cpu) 4787 { 4788 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4789 4790 intel_cpuc_finish(cpuc); 4791 4792 if (is_hybrid() && cpuc->pmu) 4793 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4794 } 4795 4796 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 4797 bool sched_in) 4798 { 4799 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 4800 intel_pmu_lbr_sched_task(pmu_ctx, sched_in); 4801 } 4802 4803 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc, 4804 struct perf_event_pmu_context *next_epc) 4805 { 4806 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc); 4807 } 4808 4809 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4810 { 4811 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4812 } 4813 4814 static void intel_aux_output_init(void) 4815 { 4816 /* Refer also intel_pmu_aux_output_match() */ 4817 if (x86_pmu.intel_cap.pebs_output_pt_available) 4818 x86_pmu.assign = intel_pmu_assign_event; 4819 } 4820 4821 static int intel_pmu_aux_output_match(struct perf_event *event) 4822 { 4823 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 4824 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4825 return 0; 4826 4827 return is_intel_pt_event(event); 4828 } 4829 4830 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 4831 { 4832 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 4833 4834 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 4835 } 4836 4837 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4838 4839 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4840 4841 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4842 4843 static struct attribute *intel_arch3_formats_attr[] = { 4844 &format_attr_event.attr, 4845 &format_attr_umask.attr, 4846 &format_attr_edge.attr, 4847 &format_attr_pc.attr, 4848 &format_attr_any.attr, 4849 &format_attr_inv.attr, 4850 &format_attr_cmask.attr, 4851 NULL, 4852 }; 4853 4854 static struct attribute *hsw_format_attr[] = { 4855 &format_attr_in_tx.attr, 4856 &format_attr_in_tx_cp.attr, 4857 &format_attr_offcore_rsp.attr, 4858 &format_attr_ldlat.attr, 4859 NULL 4860 }; 4861 4862 static struct attribute *nhm_format_attr[] = { 4863 &format_attr_offcore_rsp.attr, 4864 &format_attr_ldlat.attr, 4865 NULL 4866 }; 4867 4868 static struct attribute *slm_format_attr[] = { 4869 &format_attr_offcore_rsp.attr, 4870 NULL 4871 }; 4872 4873 static struct attribute *skl_format_attr[] = { 4874 &format_attr_frontend.attr, 4875 NULL, 4876 }; 4877 4878 static __initconst const struct x86_pmu core_pmu = { 4879 .name = "core", 4880 .handle_irq = x86_pmu_handle_irq, 4881 .disable_all = x86_pmu_disable_all, 4882 .enable_all = core_pmu_enable_all, 4883 .enable = core_pmu_enable_event, 4884 .disable = x86_pmu_disable_event, 4885 .hw_config = core_pmu_hw_config, 4886 .schedule_events = x86_schedule_events, 4887 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4888 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4889 .event_map = intel_pmu_event_map, 4890 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4891 .apic = 1, 4892 .large_pebs_flags = LARGE_PEBS_FLAGS, 4893 4894 /* 4895 * Intel PMCs cannot be accessed sanely above 32-bit width, 4896 * so we install an artificial 1<<31 period regardless of 4897 * the generic event period: 4898 */ 4899 .max_period = (1ULL<<31) - 1, 4900 .get_event_constraints = intel_get_event_constraints, 4901 .put_event_constraints = intel_put_event_constraints, 4902 .event_constraints = intel_core_event_constraints, 4903 .guest_get_msrs = core_guest_get_msrs, 4904 .format_attrs = intel_arch_formats_attr, 4905 .events_sysfs_show = intel_event_sysfs_show, 4906 4907 /* 4908 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4909 * together with PMU version 1 and thus be using core_pmu with 4910 * shared_regs. We need following callbacks here to allocate 4911 * it properly. 4912 */ 4913 .cpu_prepare = intel_pmu_cpu_prepare, 4914 .cpu_starting = intel_pmu_cpu_starting, 4915 .cpu_dying = intel_pmu_cpu_dying, 4916 .cpu_dead = intel_pmu_cpu_dead, 4917 4918 .check_period = intel_pmu_check_period, 4919 4920 .lbr_reset = intel_pmu_lbr_reset_64, 4921 .lbr_read = intel_pmu_lbr_read_64, 4922 .lbr_save = intel_pmu_lbr_save, 4923 .lbr_restore = intel_pmu_lbr_restore, 4924 }; 4925 4926 static __initconst const struct x86_pmu intel_pmu = { 4927 .name = "Intel", 4928 .handle_irq = intel_pmu_handle_irq, 4929 .disable_all = intel_pmu_disable_all, 4930 .enable_all = intel_pmu_enable_all, 4931 .enable = intel_pmu_enable_event, 4932 .disable = intel_pmu_disable_event, 4933 .add = intel_pmu_add_event, 4934 .del = intel_pmu_del_event, 4935 .read = intel_pmu_read_event, 4936 .set_period = intel_pmu_set_period, 4937 .update = intel_pmu_update, 4938 .hw_config = intel_pmu_hw_config, 4939 .schedule_events = x86_schedule_events, 4940 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4941 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4942 .event_map = intel_pmu_event_map, 4943 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4944 .apic = 1, 4945 .large_pebs_flags = LARGE_PEBS_FLAGS, 4946 /* 4947 * Intel PMCs cannot be accessed sanely above 32 bit width, 4948 * so we install an artificial 1<<31 period regardless of 4949 * the generic event period: 4950 */ 4951 .max_period = (1ULL << 31) - 1, 4952 .get_event_constraints = intel_get_event_constraints, 4953 .put_event_constraints = intel_put_event_constraints, 4954 .pebs_aliases = intel_pebs_aliases_core2, 4955 4956 .format_attrs = intel_arch3_formats_attr, 4957 .events_sysfs_show = intel_event_sysfs_show, 4958 4959 .cpu_prepare = intel_pmu_cpu_prepare, 4960 .cpu_starting = intel_pmu_cpu_starting, 4961 .cpu_dying = intel_pmu_cpu_dying, 4962 .cpu_dead = intel_pmu_cpu_dead, 4963 4964 .guest_get_msrs = intel_guest_get_msrs, 4965 .sched_task = intel_pmu_sched_task, 4966 .swap_task_ctx = intel_pmu_swap_task_ctx, 4967 4968 .check_period = intel_pmu_check_period, 4969 4970 .aux_output_match = intel_pmu_aux_output_match, 4971 4972 .lbr_reset = intel_pmu_lbr_reset_64, 4973 .lbr_read = intel_pmu_lbr_read_64, 4974 .lbr_save = intel_pmu_lbr_save, 4975 .lbr_restore = intel_pmu_lbr_restore, 4976 4977 /* 4978 * SMM has access to all 4 rings and while traditionally SMM code only 4979 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 4980 * 4981 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 4982 * between SMM or not, this results in what should be pure userspace 4983 * counters including SMM data. 4984 * 4985 * This is a clear privilege issue, therefore globally disable 4986 * counting SMM by default. 4987 */ 4988 .attr_freeze_on_smi = 1, 4989 }; 4990 4991 static __init void intel_clovertown_quirk(void) 4992 { 4993 /* 4994 * PEBS is unreliable due to: 4995 * 4996 * AJ67 - PEBS may experience CPL leaks 4997 * AJ68 - PEBS PMI may be delayed by one event 4998 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4999 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 5000 * 5001 * AJ67 could be worked around by restricting the OS/USR flags. 5002 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 5003 * 5004 * AJ106 could possibly be worked around by not allowing LBR 5005 * usage from PEBS, including the fixup. 5006 * AJ68 could possibly be worked around by always programming 5007 * a pebs_event_reset[0] value and coping with the lost events. 5008 * 5009 * But taken together it might just make sense to not enable PEBS on 5010 * these chips. 5011 */ 5012 pr_warn("PEBS disabled due to CPU errata\n"); 5013 x86_pmu.pebs = 0; 5014 x86_pmu.pebs_constraints = NULL; 5015 } 5016 5017 static const struct x86_cpu_desc isolation_ucodes[] = { 5018 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 5019 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 5020 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 5021 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 5022 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 5023 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 5024 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 5025 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 5026 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 5027 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 5028 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 5029 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 5030 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 5031 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 5032 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 5033 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 5034 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 5035 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 11, 0x00000000), 5036 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 5037 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 5038 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 5039 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 5040 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 5041 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 5042 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 5043 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 5044 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 5045 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 5046 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 5047 {} 5048 }; 5049 5050 static void intel_check_pebs_isolation(void) 5051 { 5052 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 5053 } 5054 5055 static __init void intel_pebs_isolation_quirk(void) 5056 { 5057 WARN_ON_ONCE(x86_pmu.check_microcode); 5058 x86_pmu.check_microcode = intel_check_pebs_isolation; 5059 intel_check_pebs_isolation(); 5060 } 5061 5062 static const struct x86_cpu_desc pebs_ucodes[] = { 5063 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 5064 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 5065 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 5066 {} 5067 }; 5068 5069 static bool intel_snb_pebs_broken(void) 5070 { 5071 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 5072 } 5073 5074 static void intel_snb_check_microcode(void) 5075 { 5076 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 5077 return; 5078 5079 /* 5080 * Serialized by the microcode lock.. 5081 */ 5082 if (x86_pmu.pebs_broken) { 5083 pr_info("PEBS enabled due to microcode update\n"); 5084 x86_pmu.pebs_broken = 0; 5085 } else { 5086 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 5087 x86_pmu.pebs_broken = 1; 5088 } 5089 } 5090 5091 static bool is_lbr_from(unsigned long msr) 5092 { 5093 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 5094 5095 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 5096 } 5097 5098 /* 5099 * Under certain circumstances, access certain MSR may cause #GP. 5100 * The function tests if the input MSR can be safely accessed. 5101 */ 5102 static bool check_msr(unsigned long msr, u64 mask) 5103 { 5104 u64 val_old, val_new, val_tmp; 5105 5106 /* 5107 * Disable the check for real HW, so we don't 5108 * mess with potentially enabled registers: 5109 */ 5110 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 5111 return true; 5112 5113 /* 5114 * Read the current value, change it and read it back to see if it 5115 * matches, this is needed to detect certain hardware emulators 5116 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5117 */ 5118 if (rdmsrl_safe(msr, &val_old)) 5119 return false; 5120 5121 /* 5122 * Only change the bits which can be updated by wrmsrl. 5123 */ 5124 val_tmp = val_old ^ mask; 5125 5126 if (is_lbr_from(msr)) 5127 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5128 5129 if (wrmsrl_safe(msr, val_tmp) || 5130 rdmsrl_safe(msr, &val_new)) 5131 return false; 5132 5133 /* 5134 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 5135 * should equal rdmsrl()'s even with the quirk. 5136 */ 5137 if (val_new != val_tmp) 5138 return false; 5139 5140 if (is_lbr_from(msr)) 5141 val_old = lbr_from_signext_quirk_wr(val_old); 5142 5143 /* Here it's sure that the MSR can be safely accessed. 5144 * Restore the old value and return. 5145 */ 5146 wrmsrl(msr, val_old); 5147 5148 return true; 5149 } 5150 5151 static __init void intel_sandybridge_quirk(void) 5152 { 5153 x86_pmu.check_microcode = intel_snb_check_microcode; 5154 cpus_read_lock(); 5155 intel_snb_check_microcode(); 5156 cpus_read_unlock(); 5157 } 5158 5159 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 5160 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 5161 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 5162 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 5163 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 5164 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 5165 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 5166 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 5167 }; 5168 5169 static __init void intel_arch_events_quirk(void) 5170 { 5171 int bit; 5172 5173 /* disable event that reported as not present by cpuid */ 5174 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 5175 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 5176 pr_warn("CPUID marked event: \'%s\' unavailable\n", 5177 intel_arch_events_map[bit].name); 5178 } 5179 } 5180 5181 static __init void intel_nehalem_quirk(void) 5182 { 5183 union cpuid10_ebx ebx; 5184 5185 ebx.full = x86_pmu.events_maskl; 5186 if (ebx.split.no_branch_misses_retired) { 5187 /* 5188 * Erratum AAJ80 detected, we work it around by using 5189 * the BR_MISP_EXEC.ANY event. This will over-count 5190 * branch-misses, but it's still much better than the 5191 * architectural event which is often completely bogus: 5192 */ 5193 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 5194 ebx.split.no_branch_misses_retired = 0; 5195 x86_pmu.events_maskl = ebx.full; 5196 pr_info("CPU erratum AAJ80 worked around\n"); 5197 } 5198 } 5199 5200 /* 5201 * enable software workaround for errata: 5202 * SNB: BJ122 5203 * IVB: BV98 5204 * HSW: HSD29 5205 * 5206 * Only needed when HT is enabled. However detecting 5207 * if HT is enabled is difficult (model specific). So instead, 5208 * we enable the workaround in the early boot, and verify if 5209 * it is needed in a later initcall phase once we have valid 5210 * topology information to check if HT is actually enabled 5211 */ 5212 static __init void intel_ht_bug(void) 5213 { 5214 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 5215 5216 x86_pmu.start_scheduling = intel_start_scheduling; 5217 x86_pmu.commit_scheduling = intel_commit_scheduling; 5218 x86_pmu.stop_scheduling = intel_stop_scheduling; 5219 } 5220 5221 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 5222 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5223 5224 /* Haswell special events */ 5225 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 5226 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 5227 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 5228 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 5229 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 5230 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 5231 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 5232 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 5233 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 5234 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 5235 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 5236 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 5237 5238 static struct attribute *hsw_events_attrs[] = { 5239 EVENT_PTR(td_slots_issued), 5240 EVENT_PTR(td_slots_retired), 5241 EVENT_PTR(td_fetch_bubbles), 5242 EVENT_PTR(td_total_slots), 5243 EVENT_PTR(td_total_slots_scale), 5244 EVENT_PTR(td_recovery_bubbles), 5245 EVENT_PTR(td_recovery_bubbles_scale), 5246 NULL 5247 }; 5248 5249 static struct attribute *hsw_mem_events_attrs[] = { 5250 EVENT_PTR(mem_ld_hsw), 5251 EVENT_PTR(mem_st_hsw), 5252 NULL, 5253 }; 5254 5255 static struct attribute *hsw_tsx_events_attrs[] = { 5256 EVENT_PTR(tx_start), 5257 EVENT_PTR(tx_commit), 5258 EVENT_PTR(tx_abort), 5259 EVENT_PTR(tx_capacity), 5260 EVENT_PTR(tx_conflict), 5261 EVENT_PTR(el_start), 5262 EVENT_PTR(el_commit), 5263 EVENT_PTR(el_abort), 5264 EVENT_PTR(el_capacity), 5265 EVENT_PTR(el_conflict), 5266 EVENT_PTR(cycles_t), 5267 EVENT_PTR(cycles_ct), 5268 NULL 5269 }; 5270 5271 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 5272 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 5273 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 5274 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 5275 5276 static struct attribute *icl_events_attrs[] = { 5277 EVENT_PTR(mem_ld_hsw), 5278 EVENT_PTR(mem_st_hsw), 5279 NULL, 5280 }; 5281 5282 static struct attribute *icl_td_events_attrs[] = { 5283 EVENT_PTR(slots), 5284 EVENT_PTR(td_retiring), 5285 EVENT_PTR(td_bad_spec), 5286 EVENT_PTR(td_fe_bound), 5287 EVENT_PTR(td_be_bound), 5288 NULL, 5289 }; 5290 5291 static struct attribute *icl_tsx_events_attrs[] = { 5292 EVENT_PTR(tx_start), 5293 EVENT_PTR(tx_abort), 5294 EVENT_PTR(tx_commit), 5295 EVENT_PTR(tx_capacity_read), 5296 EVENT_PTR(tx_capacity_write), 5297 EVENT_PTR(tx_conflict), 5298 EVENT_PTR(el_start), 5299 EVENT_PTR(el_abort), 5300 EVENT_PTR(el_commit), 5301 EVENT_PTR(el_capacity_read), 5302 EVENT_PTR(el_capacity_write), 5303 EVENT_PTR(el_conflict), 5304 EVENT_PTR(cycles_t), 5305 EVENT_PTR(cycles_ct), 5306 NULL, 5307 }; 5308 5309 5310 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5311 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5312 5313 static struct attribute *spr_events_attrs[] = { 5314 EVENT_PTR(mem_ld_hsw), 5315 EVENT_PTR(mem_st_spr), 5316 EVENT_PTR(mem_ld_aux), 5317 NULL, 5318 }; 5319 5320 static struct attribute *spr_td_events_attrs[] = { 5321 EVENT_PTR(slots), 5322 EVENT_PTR(td_retiring), 5323 EVENT_PTR(td_bad_spec), 5324 EVENT_PTR(td_fe_bound), 5325 EVENT_PTR(td_be_bound), 5326 EVENT_PTR(td_heavy_ops), 5327 EVENT_PTR(td_br_mispredict), 5328 EVENT_PTR(td_fetch_lat), 5329 EVENT_PTR(td_mem_bound), 5330 NULL, 5331 }; 5332 5333 static struct attribute *spr_tsx_events_attrs[] = { 5334 EVENT_PTR(tx_start), 5335 EVENT_PTR(tx_abort), 5336 EVENT_PTR(tx_commit), 5337 EVENT_PTR(tx_capacity_read), 5338 EVENT_PTR(tx_capacity_write), 5339 EVENT_PTR(tx_conflict), 5340 EVENT_PTR(cycles_t), 5341 EVENT_PTR(cycles_ct), 5342 NULL, 5343 }; 5344 5345 static ssize_t freeze_on_smi_show(struct device *cdev, 5346 struct device_attribute *attr, 5347 char *buf) 5348 { 5349 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5350 } 5351 5352 static DEFINE_MUTEX(freeze_on_smi_mutex); 5353 5354 static ssize_t freeze_on_smi_store(struct device *cdev, 5355 struct device_attribute *attr, 5356 const char *buf, size_t count) 5357 { 5358 unsigned long val; 5359 ssize_t ret; 5360 5361 ret = kstrtoul(buf, 0, &val); 5362 if (ret) 5363 return ret; 5364 5365 if (val > 1) 5366 return -EINVAL; 5367 5368 mutex_lock(&freeze_on_smi_mutex); 5369 5370 if (x86_pmu.attr_freeze_on_smi == val) 5371 goto done; 5372 5373 x86_pmu.attr_freeze_on_smi = val; 5374 5375 cpus_read_lock(); 5376 on_each_cpu(flip_smm_bit, &val, 1); 5377 cpus_read_unlock(); 5378 done: 5379 mutex_unlock(&freeze_on_smi_mutex); 5380 5381 return count; 5382 } 5383 5384 static void update_tfa_sched(void *ignored) 5385 { 5386 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5387 5388 /* 5389 * check if PMC3 is used 5390 * and if so force schedule out for all event types all contexts 5391 */ 5392 if (test_bit(3, cpuc->active_mask)) 5393 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5394 } 5395 5396 static ssize_t show_sysctl_tfa(struct device *cdev, 5397 struct device_attribute *attr, 5398 char *buf) 5399 { 5400 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5401 } 5402 5403 static ssize_t set_sysctl_tfa(struct device *cdev, 5404 struct device_attribute *attr, 5405 const char *buf, size_t count) 5406 { 5407 bool val; 5408 ssize_t ret; 5409 5410 ret = kstrtobool(buf, &val); 5411 if (ret) 5412 return ret; 5413 5414 /* no change */ 5415 if (val == allow_tsx_force_abort) 5416 return count; 5417 5418 allow_tsx_force_abort = val; 5419 5420 cpus_read_lock(); 5421 on_each_cpu(update_tfa_sched, NULL, 1); 5422 cpus_read_unlock(); 5423 5424 return count; 5425 } 5426 5427 5428 static DEVICE_ATTR_RW(freeze_on_smi); 5429 5430 static ssize_t branches_show(struct device *cdev, 5431 struct device_attribute *attr, 5432 char *buf) 5433 { 5434 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5435 } 5436 5437 static DEVICE_ATTR_RO(branches); 5438 5439 static struct attribute *lbr_attrs[] = { 5440 &dev_attr_branches.attr, 5441 NULL 5442 }; 5443 5444 static char pmu_name_str[30]; 5445 5446 static ssize_t pmu_name_show(struct device *cdev, 5447 struct device_attribute *attr, 5448 char *buf) 5449 { 5450 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5451 } 5452 5453 static DEVICE_ATTR_RO(pmu_name); 5454 5455 static struct attribute *intel_pmu_caps_attrs[] = { 5456 &dev_attr_pmu_name.attr, 5457 NULL 5458 }; 5459 5460 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5461 show_sysctl_tfa, 5462 set_sysctl_tfa); 5463 5464 static struct attribute *intel_pmu_attrs[] = { 5465 &dev_attr_freeze_on_smi.attr, 5466 &dev_attr_allow_tsx_force_abort.attr, 5467 NULL, 5468 }; 5469 5470 static umode_t 5471 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5472 { 5473 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5474 } 5475 5476 static umode_t 5477 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5478 { 5479 return x86_pmu.pebs ? attr->mode : 0; 5480 } 5481 5482 static umode_t 5483 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5484 { 5485 if (attr == &event_attr_mem_ld_aux.attr.attr) 5486 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 5487 5488 return pebs_is_visible(kobj, attr, i); 5489 } 5490 5491 static umode_t 5492 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5493 { 5494 return x86_pmu.lbr_nr ? attr->mode : 0; 5495 } 5496 5497 static umode_t 5498 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5499 { 5500 return x86_pmu.version >= 2 ? attr->mode : 0; 5501 } 5502 5503 static umode_t 5504 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5505 { 5506 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5507 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5508 5509 return attr->mode; 5510 } 5511 5512 static struct attribute_group group_events_td = { 5513 .name = "events", 5514 }; 5515 5516 static struct attribute_group group_events_mem = { 5517 .name = "events", 5518 .is_visible = mem_is_visible, 5519 }; 5520 5521 static struct attribute_group group_events_tsx = { 5522 .name = "events", 5523 .is_visible = tsx_is_visible, 5524 }; 5525 5526 static struct attribute_group group_caps_gen = { 5527 .name = "caps", 5528 .attrs = intel_pmu_caps_attrs, 5529 }; 5530 5531 static struct attribute_group group_caps_lbr = { 5532 .name = "caps", 5533 .attrs = lbr_attrs, 5534 .is_visible = lbr_is_visible, 5535 }; 5536 5537 static struct attribute_group group_format_extra = { 5538 .name = "format", 5539 .is_visible = exra_is_visible, 5540 }; 5541 5542 static struct attribute_group group_format_extra_skl = { 5543 .name = "format", 5544 .is_visible = exra_is_visible, 5545 }; 5546 5547 static struct attribute_group group_default = { 5548 .attrs = intel_pmu_attrs, 5549 .is_visible = default_is_visible, 5550 }; 5551 5552 static const struct attribute_group *attr_update[] = { 5553 &group_events_td, 5554 &group_events_mem, 5555 &group_events_tsx, 5556 &group_caps_gen, 5557 &group_caps_lbr, 5558 &group_format_extra, 5559 &group_format_extra_skl, 5560 &group_default, 5561 NULL, 5562 }; 5563 5564 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5565 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5566 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5567 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5568 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5569 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5570 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5571 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5572 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5573 5574 static struct attribute *adl_hybrid_events_attrs[] = { 5575 EVENT_PTR(slots_adl), 5576 EVENT_PTR(td_retiring_adl), 5577 EVENT_PTR(td_bad_spec_adl), 5578 EVENT_PTR(td_fe_bound_adl), 5579 EVENT_PTR(td_be_bound_adl), 5580 EVENT_PTR(td_heavy_ops_adl), 5581 EVENT_PTR(td_br_mis_adl), 5582 EVENT_PTR(td_fetch_lat_adl), 5583 EVENT_PTR(td_mem_bound_adl), 5584 NULL, 5585 }; 5586 5587 /* Must be in IDX order */ 5588 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5589 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5590 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5591 5592 static struct attribute *adl_hybrid_mem_attrs[] = { 5593 EVENT_PTR(mem_ld_adl), 5594 EVENT_PTR(mem_st_adl), 5595 EVENT_PTR(mem_ld_aux_adl), 5596 NULL, 5597 }; 5598 5599 static struct attribute *mtl_hybrid_mem_attrs[] = { 5600 EVENT_PTR(mem_ld_adl), 5601 EVENT_PTR(mem_st_adl), 5602 NULL 5603 }; 5604 5605 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5606 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5607 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5608 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5609 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5610 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5611 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5612 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5613 5614 static struct attribute *adl_hybrid_tsx_attrs[] = { 5615 EVENT_PTR(tx_start_adl), 5616 EVENT_PTR(tx_abort_adl), 5617 EVENT_PTR(tx_commit_adl), 5618 EVENT_PTR(tx_capacity_read_adl), 5619 EVENT_PTR(tx_capacity_write_adl), 5620 EVENT_PTR(tx_conflict_adl), 5621 EVENT_PTR(cycles_t_adl), 5622 EVENT_PTR(cycles_ct_adl), 5623 NULL, 5624 }; 5625 5626 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5627 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5628 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5629 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5630 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5631 5632 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 5633 FORMAT_HYBRID_PTR(in_tx), \ 5634 FORMAT_HYBRID_PTR(in_tx_cp) 5635 5636 #define ADL_HYBRID_FORMAT_ATTR \ 5637 FORMAT_HYBRID_PTR(offcore_rsp), \ 5638 FORMAT_HYBRID_PTR(ldlat), \ 5639 FORMAT_HYBRID_PTR(frontend) 5640 5641 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5642 ADL_HYBRID_RTM_FORMAT_ATTR, 5643 ADL_HYBRID_FORMAT_ATTR, 5644 NULL 5645 }; 5646 5647 static struct attribute *adl_hybrid_extra_attr[] = { 5648 ADL_HYBRID_FORMAT_ATTR, 5649 NULL 5650 }; 5651 5652 PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63"); 5653 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small); 5654 5655 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 5656 ADL_HYBRID_RTM_FORMAT_ATTR, 5657 ADL_HYBRID_FORMAT_ATTR, 5658 FORMAT_HYBRID_PTR(snoop_rsp), 5659 NULL 5660 }; 5661 5662 static struct attribute *mtl_hybrid_extra_attr[] = { 5663 ADL_HYBRID_FORMAT_ATTR, 5664 FORMAT_HYBRID_PTR(snoop_rsp), 5665 NULL 5666 }; 5667 5668 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5669 { 5670 struct device *dev = kobj_to_dev(kobj); 5671 struct x86_hybrid_pmu *pmu = 5672 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5673 struct perf_pmu_events_hybrid_attr *pmu_attr = 5674 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5675 5676 return pmu->cpu_type & pmu_attr->pmu_type; 5677 } 5678 5679 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5680 struct attribute *attr, int i) 5681 { 5682 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5683 } 5684 5685 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5686 { 5687 int cpu = cpumask_first(&pmu->supported_cpus); 5688 5689 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5690 } 5691 5692 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5693 struct attribute *attr, int i) 5694 { 5695 struct device *dev = kobj_to_dev(kobj); 5696 struct x86_hybrid_pmu *pmu = 5697 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5698 int cpu = hybrid_find_supported_cpu(pmu); 5699 5700 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5701 } 5702 5703 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5704 struct attribute *attr, int i) 5705 { 5706 struct device *dev = kobj_to_dev(kobj); 5707 struct x86_hybrid_pmu *pmu = 5708 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5709 struct perf_pmu_format_hybrid_attr *pmu_attr = 5710 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5711 int cpu = hybrid_find_supported_cpu(pmu); 5712 5713 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5714 } 5715 5716 static struct attribute_group hybrid_group_events_td = { 5717 .name = "events", 5718 .is_visible = hybrid_events_is_visible, 5719 }; 5720 5721 static struct attribute_group hybrid_group_events_mem = { 5722 .name = "events", 5723 .is_visible = hybrid_events_is_visible, 5724 }; 5725 5726 static struct attribute_group hybrid_group_events_tsx = { 5727 .name = "events", 5728 .is_visible = hybrid_tsx_is_visible, 5729 }; 5730 5731 static struct attribute_group hybrid_group_format_extra = { 5732 .name = "format", 5733 .is_visible = hybrid_format_is_visible, 5734 }; 5735 5736 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5737 struct device_attribute *attr, 5738 char *buf) 5739 { 5740 struct x86_hybrid_pmu *pmu = 5741 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5742 5743 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5744 } 5745 5746 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5747 static struct attribute *intel_hybrid_cpus_attrs[] = { 5748 &dev_attr_cpus.attr, 5749 NULL, 5750 }; 5751 5752 static struct attribute_group hybrid_group_cpus = { 5753 .attrs = intel_hybrid_cpus_attrs, 5754 }; 5755 5756 static const struct attribute_group *hybrid_attr_update[] = { 5757 &hybrid_group_events_td, 5758 &hybrid_group_events_mem, 5759 &hybrid_group_events_tsx, 5760 &group_caps_gen, 5761 &group_caps_lbr, 5762 &hybrid_group_format_extra, 5763 &group_default, 5764 &hybrid_group_cpus, 5765 NULL, 5766 }; 5767 5768 static struct attribute *empty_attrs; 5769 5770 static void intel_pmu_check_num_counters(int *num_counters, 5771 int *num_counters_fixed, 5772 u64 *intel_ctrl, u64 fixed_mask) 5773 { 5774 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5775 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5776 *num_counters, INTEL_PMC_MAX_GENERIC); 5777 *num_counters = INTEL_PMC_MAX_GENERIC; 5778 } 5779 *intel_ctrl = (1ULL << *num_counters) - 1; 5780 5781 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5782 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5783 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5784 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5785 } 5786 5787 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5788 } 5789 5790 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5791 int num_counters, 5792 int num_counters_fixed, 5793 u64 intel_ctrl) 5794 { 5795 struct event_constraint *c; 5796 5797 if (!event_constraints) 5798 return; 5799 5800 /* 5801 * event on fixed counter2 (REF_CYCLES) only works on this 5802 * counter, so do not extend mask to generic counters 5803 */ 5804 for_each_event_constraint(c, event_constraints) { 5805 /* 5806 * Don't extend the topdown slots and metrics 5807 * events to the generic counters. 5808 */ 5809 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5810 /* 5811 * Disable topdown slots and metrics events, 5812 * if slots event is not in CPUID. 5813 */ 5814 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5815 c->idxmsk64 = 0; 5816 c->weight = hweight64(c->idxmsk64); 5817 continue; 5818 } 5819 5820 if (c->cmask == FIXED_EVENT_FLAGS) { 5821 /* Disabled fixed counters which are not in CPUID */ 5822 c->idxmsk64 &= intel_ctrl; 5823 5824 /* 5825 * Don't extend the pseudo-encoding to the 5826 * generic counters 5827 */ 5828 if (!use_fixed_pseudo_encoding(c->code)) 5829 c->idxmsk64 |= (1ULL << num_counters) - 1; 5830 } 5831 c->idxmsk64 &= 5832 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5833 c->weight = hweight64(c->idxmsk64); 5834 } 5835 } 5836 5837 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5838 { 5839 struct extra_reg *er; 5840 5841 /* 5842 * Access extra MSR may cause #GP under certain circumstances. 5843 * E.g. KVM doesn't support offcore event 5844 * Check all extra_regs here. 5845 */ 5846 if (!extra_regs) 5847 return; 5848 5849 for (er = extra_regs; er->msr; er++) { 5850 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5851 /* Disable LBR select mapping */ 5852 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5853 x86_pmu.lbr_sel_map = NULL; 5854 } 5855 } 5856 5857 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5858 { 5859 struct x86_hybrid_pmu *pmu; 5860 int i; 5861 5862 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5863 pmu = &x86_pmu.hybrid_pmu[i]; 5864 5865 intel_pmu_check_num_counters(&pmu->num_counters, 5866 &pmu->num_counters_fixed, 5867 &pmu->intel_ctrl, 5868 fixed_mask); 5869 5870 if (pmu->intel_cap.perf_metrics) { 5871 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5872 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5873 } 5874 5875 if (pmu->intel_cap.pebs_output_pt_available) 5876 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5877 5878 intel_pmu_check_event_constraints(pmu->event_constraints, 5879 pmu->num_counters, 5880 pmu->num_counters_fixed, 5881 pmu->intel_ctrl); 5882 5883 intel_pmu_check_extra_regs(pmu->extra_regs); 5884 } 5885 } 5886 5887 static __always_inline bool is_mtl(u8 x86_model) 5888 { 5889 return (x86_model == INTEL_FAM6_METEORLAKE) || 5890 (x86_model == INTEL_FAM6_METEORLAKE_L); 5891 } 5892 5893 __init int intel_pmu_init(void) 5894 { 5895 struct attribute **extra_skl_attr = &empty_attrs; 5896 struct attribute **extra_attr = &empty_attrs; 5897 struct attribute **td_attr = &empty_attrs; 5898 struct attribute **mem_attr = &empty_attrs; 5899 struct attribute **tsx_attr = &empty_attrs; 5900 union cpuid10_edx edx; 5901 union cpuid10_eax eax; 5902 union cpuid10_ebx ebx; 5903 unsigned int fixed_mask; 5904 bool pmem = false; 5905 int version, i; 5906 char *name; 5907 struct x86_hybrid_pmu *pmu; 5908 5909 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5910 switch (boot_cpu_data.x86) { 5911 case 0x6: 5912 return p6_pmu_init(); 5913 case 0xb: 5914 return knc_pmu_init(); 5915 case 0xf: 5916 return p4_pmu_init(); 5917 } 5918 return -ENODEV; 5919 } 5920 5921 /* 5922 * Check whether the Architectural PerfMon supports 5923 * Branch Misses Retired hw_event or not. 5924 */ 5925 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5926 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5927 return -ENODEV; 5928 5929 version = eax.split.version_id; 5930 if (version < 2) 5931 x86_pmu = core_pmu; 5932 else 5933 x86_pmu = intel_pmu; 5934 5935 x86_pmu.version = version; 5936 x86_pmu.num_counters = eax.split.num_counters; 5937 x86_pmu.cntval_bits = eax.split.bit_width; 5938 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5939 5940 x86_pmu.events_maskl = ebx.full; 5941 x86_pmu.events_mask_len = eax.split.mask_length; 5942 5943 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5944 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 5945 5946 /* 5947 * Quirk: v2 perfmon does not report fixed-purpose events, so 5948 * assume at least 3 events, when not running in a hypervisor: 5949 */ 5950 if (version > 1 && version < 5) { 5951 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5952 5953 x86_pmu.num_counters_fixed = 5954 max((int)edx.split.num_counters_fixed, assume); 5955 5956 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5957 } else if (version >= 5) 5958 x86_pmu.num_counters_fixed = fls(fixed_mask); 5959 5960 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5961 u64 capabilities; 5962 5963 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5964 x86_pmu.intel_cap.capabilities = capabilities; 5965 } 5966 5967 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5968 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5969 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5970 } 5971 5972 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5973 intel_pmu_arch_lbr_init(); 5974 5975 intel_ds_init(); 5976 5977 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5978 5979 if (version >= 5) { 5980 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5981 if (x86_pmu.intel_cap.anythread_deprecated) 5982 pr_cont(" AnyThread deprecated, "); 5983 } 5984 5985 /* 5986 * Install the hw-cache-events table: 5987 */ 5988 switch (boot_cpu_data.x86_model) { 5989 case INTEL_FAM6_CORE_YONAH: 5990 pr_cont("Core events, "); 5991 name = "core"; 5992 break; 5993 5994 case INTEL_FAM6_CORE2_MEROM: 5995 x86_add_quirk(intel_clovertown_quirk); 5996 fallthrough; 5997 5998 case INTEL_FAM6_CORE2_MEROM_L: 5999 case INTEL_FAM6_CORE2_PENRYN: 6000 case INTEL_FAM6_CORE2_DUNNINGTON: 6001 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 6002 sizeof(hw_cache_event_ids)); 6003 6004 intel_pmu_lbr_init_core(); 6005 6006 x86_pmu.event_constraints = intel_core2_event_constraints; 6007 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 6008 pr_cont("Core2 events, "); 6009 name = "core2"; 6010 break; 6011 6012 case INTEL_FAM6_NEHALEM: 6013 case INTEL_FAM6_NEHALEM_EP: 6014 case INTEL_FAM6_NEHALEM_EX: 6015 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 6016 sizeof(hw_cache_event_ids)); 6017 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6018 sizeof(hw_cache_extra_regs)); 6019 6020 intel_pmu_lbr_init_nhm(); 6021 6022 x86_pmu.event_constraints = intel_nehalem_event_constraints; 6023 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 6024 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6025 x86_pmu.extra_regs = intel_nehalem_extra_regs; 6026 x86_pmu.limit_period = nhm_limit_period; 6027 6028 mem_attr = nhm_mem_events_attrs; 6029 6030 /* UOPS_ISSUED.STALLED_CYCLES */ 6031 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6032 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6033 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6034 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6035 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6036 6037 intel_pmu_pebs_data_source_nhm(); 6038 x86_add_quirk(intel_nehalem_quirk); 6039 x86_pmu.pebs_no_tlb = 1; 6040 extra_attr = nhm_format_attr; 6041 6042 pr_cont("Nehalem events, "); 6043 name = "nehalem"; 6044 break; 6045 6046 case INTEL_FAM6_ATOM_BONNELL: 6047 case INTEL_FAM6_ATOM_BONNELL_MID: 6048 case INTEL_FAM6_ATOM_SALTWELL: 6049 case INTEL_FAM6_ATOM_SALTWELL_MID: 6050 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 6051 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 6052 sizeof(hw_cache_event_ids)); 6053 6054 intel_pmu_lbr_init_atom(); 6055 6056 x86_pmu.event_constraints = intel_gen_event_constraints; 6057 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 6058 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 6059 pr_cont("Atom events, "); 6060 name = "bonnell"; 6061 break; 6062 6063 case INTEL_FAM6_ATOM_SILVERMONT: 6064 case INTEL_FAM6_ATOM_SILVERMONT_D: 6065 case INTEL_FAM6_ATOM_SILVERMONT_MID: 6066 case INTEL_FAM6_ATOM_AIRMONT: 6067 case INTEL_FAM6_ATOM_AIRMONT_MID: 6068 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 6069 sizeof(hw_cache_event_ids)); 6070 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 6071 sizeof(hw_cache_extra_regs)); 6072 6073 intel_pmu_lbr_init_slm(); 6074 6075 x86_pmu.event_constraints = intel_slm_event_constraints; 6076 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6077 x86_pmu.extra_regs = intel_slm_extra_regs; 6078 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6079 td_attr = slm_events_attrs; 6080 extra_attr = slm_format_attr; 6081 pr_cont("Silvermont events, "); 6082 name = "silvermont"; 6083 break; 6084 6085 case INTEL_FAM6_ATOM_GOLDMONT: 6086 case INTEL_FAM6_ATOM_GOLDMONT_D: 6087 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 6088 sizeof(hw_cache_event_ids)); 6089 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 6090 sizeof(hw_cache_extra_regs)); 6091 6092 intel_pmu_lbr_init_skl(); 6093 6094 x86_pmu.event_constraints = intel_slm_event_constraints; 6095 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 6096 x86_pmu.extra_regs = intel_glm_extra_regs; 6097 /* 6098 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6099 * for precise cycles. 6100 * :pp is identical to :ppp 6101 */ 6102 x86_pmu.pebs_aliases = NULL; 6103 x86_pmu.pebs_prec_dist = true; 6104 x86_pmu.lbr_pt_coexist = true; 6105 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6106 td_attr = glm_events_attrs; 6107 extra_attr = slm_format_attr; 6108 pr_cont("Goldmont events, "); 6109 name = "goldmont"; 6110 break; 6111 6112 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 6113 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6114 sizeof(hw_cache_event_ids)); 6115 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 6116 sizeof(hw_cache_extra_regs)); 6117 6118 intel_pmu_lbr_init_skl(); 6119 6120 x86_pmu.event_constraints = intel_slm_event_constraints; 6121 x86_pmu.extra_regs = intel_glm_extra_regs; 6122 /* 6123 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6124 * for precise cycles. 6125 */ 6126 x86_pmu.pebs_aliases = NULL; 6127 x86_pmu.pebs_prec_dist = true; 6128 x86_pmu.lbr_pt_coexist = true; 6129 x86_pmu.pebs_capable = ~0ULL; 6130 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6131 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6132 x86_pmu.get_event_constraints = glp_get_event_constraints; 6133 td_attr = glm_events_attrs; 6134 /* Goldmont Plus has 4-wide pipeline */ 6135 event_attr_td_total_slots_scale_glm.event_str = "4"; 6136 extra_attr = slm_format_attr; 6137 pr_cont("Goldmont plus events, "); 6138 name = "goldmont_plus"; 6139 break; 6140 6141 case INTEL_FAM6_ATOM_TREMONT_D: 6142 case INTEL_FAM6_ATOM_TREMONT: 6143 case INTEL_FAM6_ATOM_TREMONT_L: 6144 x86_pmu.late_ack = true; 6145 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6146 sizeof(hw_cache_event_ids)); 6147 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6148 sizeof(hw_cache_extra_regs)); 6149 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6150 6151 intel_pmu_lbr_init_skl(); 6152 6153 x86_pmu.event_constraints = intel_slm_event_constraints; 6154 x86_pmu.extra_regs = intel_tnt_extra_regs; 6155 /* 6156 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 6157 * for precise cycles. 6158 */ 6159 x86_pmu.pebs_aliases = NULL; 6160 x86_pmu.pebs_prec_dist = true; 6161 x86_pmu.lbr_pt_coexist = true; 6162 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6163 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6164 td_attr = tnt_events_attrs; 6165 extra_attr = slm_format_attr; 6166 pr_cont("Tremont events, "); 6167 name = "Tremont"; 6168 break; 6169 6170 case INTEL_FAM6_ALDERLAKE_N: 6171 x86_pmu.mid_ack = true; 6172 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 6173 sizeof(hw_cache_event_ids)); 6174 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 6175 sizeof(hw_cache_extra_regs)); 6176 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6177 6178 x86_pmu.event_constraints = intel_slm_event_constraints; 6179 x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints; 6180 x86_pmu.extra_regs = intel_grt_extra_regs; 6181 6182 x86_pmu.pebs_aliases = NULL; 6183 x86_pmu.pebs_prec_dist = true; 6184 x86_pmu.pebs_block = true; 6185 x86_pmu.lbr_pt_coexist = true; 6186 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6187 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6188 6189 intel_pmu_pebs_data_source_grt(); 6190 x86_pmu.pebs_latency_data = adl_latency_data_small; 6191 x86_pmu.get_event_constraints = tnt_get_event_constraints; 6192 x86_pmu.limit_period = spr_limit_period; 6193 td_attr = tnt_events_attrs; 6194 mem_attr = grt_mem_attrs; 6195 extra_attr = nhm_format_attr; 6196 pr_cont("Gracemont events, "); 6197 name = "gracemont"; 6198 break; 6199 6200 case INTEL_FAM6_WESTMERE: 6201 case INTEL_FAM6_WESTMERE_EP: 6202 case INTEL_FAM6_WESTMERE_EX: 6203 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 6204 sizeof(hw_cache_event_ids)); 6205 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 6206 sizeof(hw_cache_extra_regs)); 6207 6208 intel_pmu_lbr_init_nhm(); 6209 6210 x86_pmu.event_constraints = intel_westmere_event_constraints; 6211 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 6212 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 6213 x86_pmu.extra_regs = intel_westmere_extra_regs; 6214 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6215 6216 mem_attr = nhm_mem_events_attrs; 6217 6218 /* UOPS_ISSUED.STALLED_CYCLES */ 6219 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6220 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6221 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 6222 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6223 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 6224 6225 intel_pmu_pebs_data_source_nhm(); 6226 extra_attr = nhm_format_attr; 6227 pr_cont("Westmere events, "); 6228 name = "westmere"; 6229 break; 6230 6231 case INTEL_FAM6_SANDYBRIDGE: 6232 case INTEL_FAM6_SANDYBRIDGE_X: 6233 x86_add_quirk(intel_sandybridge_quirk); 6234 x86_add_quirk(intel_ht_bug); 6235 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6236 sizeof(hw_cache_event_ids)); 6237 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6238 sizeof(hw_cache_extra_regs)); 6239 6240 intel_pmu_lbr_init_snb(); 6241 6242 x86_pmu.event_constraints = intel_snb_event_constraints; 6243 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 6244 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 6245 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 6246 x86_pmu.extra_regs = intel_snbep_extra_regs; 6247 else 6248 x86_pmu.extra_regs = intel_snb_extra_regs; 6249 6250 6251 /* all extra regs are per-cpu when HT is on */ 6252 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6253 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6254 6255 td_attr = snb_events_attrs; 6256 mem_attr = snb_mem_events_attrs; 6257 6258 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6259 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6260 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6261 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 6262 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 6263 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 6264 6265 extra_attr = nhm_format_attr; 6266 6267 pr_cont("SandyBridge events, "); 6268 name = "sandybridge"; 6269 break; 6270 6271 case INTEL_FAM6_IVYBRIDGE: 6272 case INTEL_FAM6_IVYBRIDGE_X: 6273 x86_add_quirk(intel_ht_bug); 6274 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 6275 sizeof(hw_cache_event_ids)); 6276 /* dTLB-load-misses on IVB is different than SNB */ 6277 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 6278 6279 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 6280 sizeof(hw_cache_extra_regs)); 6281 6282 intel_pmu_lbr_init_snb(); 6283 6284 x86_pmu.event_constraints = intel_ivb_event_constraints; 6285 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 6286 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6287 x86_pmu.pebs_prec_dist = true; 6288 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 6289 x86_pmu.extra_regs = intel_snbep_extra_regs; 6290 else 6291 x86_pmu.extra_regs = intel_snb_extra_regs; 6292 /* all extra regs are per-cpu when HT is on */ 6293 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6294 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6295 6296 td_attr = snb_events_attrs; 6297 mem_attr = snb_mem_events_attrs; 6298 6299 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 6300 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 6301 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 6302 6303 extra_attr = nhm_format_attr; 6304 6305 pr_cont("IvyBridge events, "); 6306 name = "ivybridge"; 6307 break; 6308 6309 6310 case INTEL_FAM6_HASWELL: 6311 case INTEL_FAM6_HASWELL_X: 6312 case INTEL_FAM6_HASWELL_L: 6313 case INTEL_FAM6_HASWELL_G: 6314 x86_add_quirk(intel_ht_bug); 6315 x86_add_quirk(intel_pebs_isolation_quirk); 6316 x86_pmu.late_ack = true; 6317 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6318 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6319 6320 intel_pmu_lbr_init_hsw(); 6321 6322 x86_pmu.event_constraints = intel_hsw_event_constraints; 6323 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 6324 x86_pmu.extra_regs = intel_snbep_extra_regs; 6325 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6326 x86_pmu.pebs_prec_dist = true; 6327 /* all extra regs are per-cpu when HT is on */ 6328 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6329 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6330 6331 x86_pmu.hw_config = hsw_hw_config; 6332 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6333 x86_pmu.lbr_double_abort = true; 6334 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6335 hsw_format_attr : nhm_format_attr; 6336 td_attr = hsw_events_attrs; 6337 mem_attr = hsw_mem_events_attrs; 6338 tsx_attr = hsw_tsx_events_attrs; 6339 pr_cont("Haswell events, "); 6340 name = "haswell"; 6341 break; 6342 6343 case INTEL_FAM6_BROADWELL: 6344 case INTEL_FAM6_BROADWELL_D: 6345 case INTEL_FAM6_BROADWELL_G: 6346 case INTEL_FAM6_BROADWELL_X: 6347 x86_add_quirk(intel_pebs_isolation_quirk); 6348 x86_pmu.late_ack = true; 6349 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6350 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6351 6352 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 6353 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 6354 BDW_L3_MISS|HSW_SNOOP_DRAM; 6355 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6356 HSW_SNOOP_DRAM; 6357 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6358 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6359 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6360 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6361 6362 intel_pmu_lbr_init_hsw(); 6363 6364 x86_pmu.event_constraints = intel_bdw_event_constraints; 6365 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6366 x86_pmu.extra_regs = intel_snbep_extra_regs; 6367 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6368 x86_pmu.pebs_prec_dist = true; 6369 /* all extra regs are per-cpu when HT is on */ 6370 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6371 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6372 6373 x86_pmu.hw_config = hsw_hw_config; 6374 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6375 x86_pmu.limit_period = bdw_limit_period; 6376 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6377 hsw_format_attr : nhm_format_attr; 6378 td_attr = hsw_events_attrs; 6379 mem_attr = hsw_mem_events_attrs; 6380 tsx_attr = hsw_tsx_events_attrs; 6381 pr_cont("Broadwell events, "); 6382 name = "broadwell"; 6383 break; 6384 6385 case INTEL_FAM6_XEON_PHI_KNL: 6386 case INTEL_FAM6_XEON_PHI_KNM: 6387 memcpy(hw_cache_event_ids, 6388 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6389 memcpy(hw_cache_extra_regs, 6390 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6391 intel_pmu_lbr_init_knl(); 6392 6393 x86_pmu.event_constraints = intel_slm_event_constraints; 6394 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6395 x86_pmu.extra_regs = intel_knl_extra_regs; 6396 6397 /* all extra regs are per-cpu when HT is on */ 6398 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6399 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6400 extra_attr = slm_format_attr; 6401 pr_cont("Knights Landing/Mill events, "); 6402 name = "knights-landing"; 6403 break; 6404 6405 case INTEL_FAM6_SKYLAKE_X: 6406 pmem = true; 6407 fallthrough; 6408 case INTEL_FAM6_SKYLAKE_L: 6409 case INTEL_FAM6_SKYLAKE: 6410 case INTEL_FAM6_KABYLAKE_L: 6411 case INTEL_FAM6_KABYLAKE: 6412 case INTEL_FAM6_COMETLAKE_L: 6413 case INTEL_FAM6_COMETLAKE: 6414 x86_add_quirk(intel_pebs_isolation_quirk); 6415 x86_pmu.late_ack = true; 6416 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6417 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6418 intel_pmu_lbr_init_skl(); 6419 6420 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6421 event_attr_td_recovery_bubbles.event_str_noht = 6422 "event=0xd,umask=0x1,cmask=1"; 6423 event_attr_td_recovery_bubbles.event_str_ht = 6424 "event=0xd,umask=0x1,cmask=1,any=1"; 6425 6426 x86_pmu.event_constraints = intel_skl_event_constraints; 6427 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6428 x86_pmu.extra_regs = intel_skl_extra_regs; 6429 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6430 x86_pmu.pebs_prec_dist = true; 6431 /* all extra regs are per-cpu when HT is on */ 6432 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6433 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6434 6435 x86_pmu.hw_config = hsw_hw_config; 6436 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6437 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6438 hsw_format_attr : nhm_format_attr; 6439 extra_skl_attr = skl_format_attr; 6440 td_attr = hsw_events_attrs; 6441 mem_attr = hsw_mem_events_attrs; 6442 tsx_attr = hsw_tsx_events_attrs; 6443 intel_pmu_pebs_data_source_skl(pmem); 6444 6445 /* 6446 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6447 * TSX force abort hooks are not required on these systems. Only deploy 6448 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6449 */ 6450 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6451 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6452 x86_pmu.flags |= PMU_FL_TFA; 6453 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6454 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6455 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6456 } 6457 6458 pr_cont("Skylake events, "); 6459 name = "skylake"; 6460 break; 6461 6462 case INTEL_FAM6_ICELAKE_X: 6463 case INTEL_FAM6_ICELAKE_D: 6464 x86_pmu.pebs_ept = 1; 6465 pmem = true; 6466 fallthrough; 6467 case INTEL_FAM6_ICELAKE_L: 6468 case INTEL_FAM6_ICELAKE: 6469 case INTEL_FAM6_TIGERLAKE_L: 6470 case INTEL_FAM6_TIGERLAKE: 6471 case INTEL_FAM6_ROCKETLAKE: 6472 x86_pmu.late_ack = true; 6473 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6474 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6475 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6476 intel_pmu_lbr_init_skl(); 6477 6478 x86_pmu.event_constraints = intel_icl_event_constraints; 6479 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6480 x86_pmu.extra_regs = intel_icl_extra_regs; 6481 x86_pmu.pebs_aliases = NULL; 6482 x86_pmu.pebs_prec_dist = true; 6483 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6484 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6485 6486 x86_pmu.hw_config = hsw_hw_config; 6487 x86_pmu.get_event_constraints = icl_get_event_constraints; 6488 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6489 hsw_format_attr : nhm_format_attr; 6490 extra_skl_attr = skl_format_attr; 6491 mem_attr = icl_events_attrs; 6492 td_attr = icl_td_events_attrs; 6493 tsx_attr = icl_tsx_events_attrs; 6494 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6495 x86_pmu.lbr_pt_coexist = true; 6496 intel_pmu_pebs_data_source_skl(pmem); 6497 x86_pmu.num_topdown_events = 4; 6498 static_call_update(intel_pmu_update_topdown_event, 6499 &icl_update_topdown_event); 6500 static_call_update(intel_pmu_set_topdown_event_period, 6501 &icl_set_topdown_event_period); 6502 pr_cont("Icelake events, "); 6503 name = "icelake"; 6504 break; 6505 6506 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6507 case INTEL_FAM6_EMERALDRAPIDS_X: 6508 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6509 x86_pmu.extra_regs = intel_spr_extra_regs; 6510 fallthrough; 6511 case INTEL_FAM6_GRANITERAPIDS_X: 6512 case INTEL_FAM6_GRANITERAPIDS_D: 6513 pmem = true; 6514 x86_pmu.late_ack = true; 6515 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6516 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6517 6518 x86_pmu.event_constraints = intel_spr_event_constraints; 6519 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6520 if (!x86_pmu.extra_regs) 6521 x86_pmu.extra_regs = intel_gnr_extra_regs; 6522 x86_pmu.limit_period = spr_limit_period; 6523 x86_pmu.pebs_ept = 1; 6524 x86_pmu.pebs_aliases = NULL; 6525 x86_pmu.pebs_prec_dist = true; 6526 x86_pmu.pebs_block = true; 6527 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6528 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6529 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6530 6531 x86_pmu.hw_config = hsw_hw_config; 6532 x86_pmu.get_event_constraints = spr_get_event_constraints; 6533 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6534 hsw_format_attr : nhm_format_attr; 6535 extra_skl_attr = skl_format_attr; 6536 mem_attr = spr_events_attrs; 6537 td_attr = spr_td_events_attrs; 6538 tsx_attr = spr_tsx_events_attrs; 6539 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6540 x86_pmu.lbr_pt_coexist = true; 6541 intel_pmu_pebs_data_source_skl(pmem); 6542 x86_pmu.num_topdown_events = 8; 6543 static_call_update(intel_pmu_update_topdown_event, 6544 &icl_update_topdown_event); 6545 static_call_update(intel_pmu_set_topdown_event_period, 6546 &icl_set_topdown_event_period); 6547 pr_cont("Sapphire Rapids events, "); 6548 name = "sapphire_rapids"; 6549 break; 6550 6551 case INTEL_FAM6_ALDERLAKE: 6552 case INTEL_FAM6_ALDERLAKE_L: 6553 case INTEL_FAM6_RAPTORLAKE: 6554 case INTEL_FAM6_RAPTORLAKE_P: 6555 case INTEL_FAM6_RAPTORLAKE_S: 6556 case INTEL_FAM6_METEORLAKE: 6557 case INTEL_FAM6_METEORLAKE_L: 6558 /* 6559 * Alder Lake has 2 types of CPU, core and atom. 6560 * 6561 * Initialize the common PerfMon capabilities here. 6562 */ 6563 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6564 sizeof(struct x86_hybrid_pmu), 6565 GFP_KERNEL); 6566 if (!x86_pmu.hybrid_pmu) 6567 return -ENOMEM; 6568 static_branch_enable(&perf_is_hybrid); 6569 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6570 6571 x86_pmu.pebs_aliases = NULL; 6572 x86_pmu.pebs_prec_dist = true; 6573 x86_pmu.pebs_block = true; 6574 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6575 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6576 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6577 x86_pmu.lbr_pt_coexist = true; 6578 x86_pmu.pebs_latency_data = adl_latency_data_small; 6579 x86_pmu.num_topdown_events = 8; 6580 static_call_update(intel_pmu_update_topdown_event, 6581 &adl_update_topdown_event); 6582 static_call_update(intel_pmu_set_topdown_event_period, 6583 &adl_set_topdown_event_period); 6584 6585 x86_pmu.filter = intel_pmu_filter; 6586 x86_pmu.get_event_constraints = adl_get_event_constraints; 6587 x86_pmu.hw_config = adl_hw_config; 6588 x86_pmu.limit_period = spr_limit_period; 6589 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6590 /* 6591 * The rtm_abort_event is used to check whether to enable GPRs 6592 * for the RTM abort event. Atom doesn't have the RTM abort 6593 * event. There is no harmful to set it in the common 6594 * x86_pmu.rtm_abort_event. 6595 */ 6596 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6597 6598 td_attr = adl_hybrid_events_attrs; 6599 mem_attr = adl_hybrid_mem_attrs; 6600 tsx_attr = adl_hybrid_tsx_attrs; 6601 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6602 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6603 6604 /* Initialize big core specific PerfMon capabilities.*/ 6605 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6606 pmu->name = "cpu_core"; 6607 pmu->cpu_type = hybrid_big; 6608 pmu->late_ack = true; 6609 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6610 pmu->num_counters = x86_pmu.num_counters + 2; 6611 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6612 } else { 6613 pmu->num_counters = x86_pmu.num_counters; 6614 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6615 } 6616 6617 /* 6618 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 6619 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 6620 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 6621 * mistakenly add extra counters for P-cores. Correct the number of 6622 * counters here. 6623 */ 6624 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) { 6625 pmu->num_counters = x86_pmu.num_counters; 6626 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6627 } 6628 6629 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6630 pmu->unconstrained = (struct event_constraint) 6631 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6632 0, pmu->num_counters, 0, 0); 6633 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6634 pmu->intel_cap.perf_metrics = 1; 6635 pmu->intel_cap.pebs_output_pt_available = 0; 6636 6637 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6638 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6639 pmu->event_constraints = intel_spr_event_constraints; 6640 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6641 pmu->extra_regs = intel_spr_extra_regs; 6642 6643 /* Initialize Atom core specific PerfMon capabilities.*/ 6644 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6645 pmu->name = "cpu_atom"; 6646 pmu->cpu_type = hybrid_small; 6647 pmu->mid_ack = true; 6648 pmu->num_counters = x86_pmu.num_counters; 6649 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6650 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6651 pmu->unconstrained = (struct event_constraint) 6652 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6653 0, pmu->num_counters, 0, 0); 6654 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6655 pmu->intel_cap.perf_metrics = 0; 6656 pmu->intel_cap.pebs_output_pt_available = 1; 6657 6658 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6659 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6660 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6661 pmu->event_constraints = intel_slm_event_constraints; 6662 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6663 pmu->extra_regs = intel_grt_extra_regs; 6664 if (is_mtl(boot_cpu_data.x86_model)) { 6665 x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_gnr_extra_regs; 6666 x86_pmu.pebs_latency_data = mtl_latency_data_small; 6667 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6668 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 6669 mem_attr = mtl_hybrid_mem_attrs; 6670 intel_pmu_pebs_data_source_mtl(); 6671 x86_pmu.get_event_constraints = mtl_get_event_constraints; 6672 pmu->extra_regs = intel_cmt_extra_regs; 6673 pr_cont("Meteorlake Hybrid events, "); 6674 name = "meteorlake_hybrid"; 6675 } else { 6676 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6677 intel_pmu_pebs_data_source_adl(); 6678 pr_cont("Alderlake Hybrid events, "); 6679 name = "alderlake_hybrid"; 6680 } 6681 break; 6682 6683 default: 6684 switch (x86_pmu.version) { 6685 case 1: 6686 x86_pmu.event_constraints = intel_v1_event_constraints; 6687 pr_cont("generic architected perfmon v1, "); 6688 name = "generic_arch_v1"; 6689 break; 6690 case 2: 6691 case 3: 6692 case 4: 6693 /* 6694 * default constraints for v2 and up 6695 */ 6696 x86_pmu.event_constraints = intel_gen_event_constraints; 6697 pr_cont("generic architected perfmon, "); 6698 name = "generic_arch_v2+"; 6699 break; 6700 default: 6701 /* 6702 * The default constraints for v5 and up can support up to 6703 * 16 fixed counters. For the fixed counters 4 and later, 6704 * the pseudo-encoding is applied. 6705 * The constraints may be cut according to the CPUID enumeration 6706 * by inserting the EVENT_CONSTRAINT_END. 6707 */ 6708 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) 6709 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 6710 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1; 6711 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 6712 pr_cont("generic architected perfmon, "); 6713 name = "generic_arch_v5+"; 6714 break; 6715 } 6716 } 6717 6718 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6719 6720 if (!is_hybrid()) { 6721 group_events_td.attrs = td_attr; 6722 group_events_mem.attrs = mem_attr; 6723 group_events_tsx.attrs = tsx_attr; 6724 group_format_extra.attrs = extra_attr; 6725 group_format_extra_skl.attrs = extra_skl_attr; 6726 6727 x86_pmu.attr_update = attr_update; 6728 } else { 6729 hybrid_group_events_td.attrs = td_attr; 6730 hybrid_group_events_mem.attrs = mem_attr; 6731 hybrid_group_events_tsx.attrs = tsx_attr; 6732 hybrid_group_format_extra.attrs = extra_attr; 6733 6734 x86_pmu.attr_update = hybrid_attr_update; 6735 } 6736 6737 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6738 &x86_pmu.num_counters_fixed, 6739 &x86_pmu.intel_ctrl, 6740 (u64)fixed_mask); 6741 6742 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6743 if (x86_pmu.intel_cap.anythread_deprecated) 6744 x86_pmu.format_attrs = intel_arch_formats_attr; 6745 6746 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6747 x86_pmu.num_counters, 6748 x86_pmu.num_counters_fixed, 6749 x86_pmu.intel_ctrl); 6750 /* 6751 * Access LBR MSR may cause #GP under certain circumstances. 6752 * Check all LBR MSR here. 6753 * Disable LBR access if any LBR MSRs can not be accessed. 6754 */ 6755 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6756 x86_pmu.lbr_nr = 0; 6757 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6758 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6759 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6760 x86_pmu.lbr_nr = 0; 6761 } 6762 6763 if (x86_pmu.lbr_nr) { 6764 intel_pmu_lbr_init(); 6765 6766 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6767 6768 /* only support branch_stack snapshot for perfmon >= v2 */ 6769 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6770 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6771 static_call_update(perf_snapshot_branch_stack, 6772 intel_pmu_snapshot_arch_branch_stack); 6773 } else { 6774 static_call_update(perf_snapshot_branch_stack, 6775 intel_pmu_snapshot_branch_stack); 6776 } 6777 } 6778 } 6779 6780 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6781 6782 /* Support full width counters using alternative MSR range */ 6783 if (x86_pmu.intel_cap.full_width_write) { 6784 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6785 x86_pmu.perfctr = MSR_IA32_PMC0; 6786 pr_cont("full-width counters, "); 6787 } 6788 6789 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6790 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6791 6792 if (is_hybrid()) 6793 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6794 6795 if (x86_pmu.intel_cap.pebs_timing_info) 6796 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 6797 6798 intel_aux_output_init(); 6799 6800 return 0; 6801 } 6802 6803 /* 6804 * HT bug: phase 2 init 6805 * Called once we have valid topology information to check 6806 * whether or not HT is enabled 6807 * If HT is off, then we disable the workaround 6808 */ 6809 static __init int fixup_ht_bug(void) 6810 { 6811 int c; 6812 /* 6813 * problem not present on this CPU model, nothing to do 6814 */ 6815 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6816 return 0; 6817 6818 if (topology_max_smt_threads() > 1) { 6819 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6820 return 0; 6821 } 6822 6823 cpus_read_lock(); 6824 6825 hardlockup_detector_perf_stop(); 6826 6827 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6828 6829 x86_pmu.start_scheduling = NULL; 6830 x86_pmu.commit_scheduling = NULL; 6831 x86_pmu.stop_scheduling = NULL; 6832 6833 hardlockup_detector_perf_restart(); 6834 6835 for_each_online_cpu(c) 6836 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6837 6838 cpus_read_unlock(); 6839 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6840 return 0; 6841 } 6842 subsys_initcall(fixup_ht_bug) 6843