1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 18 #include <asm/cpufeature.h> 19 #include <asm/hardirq.h> 20 #include <asm/intel-family.h> 21 #include <asm/intel_pt.h> 22 #include <asm/apic.h> 23 #include <asm/cpu_device_id.h> 24 25 #include "../perf_event.h" 26 27 /* 28 * Intel PerfMon, used on Core and later. 29 */ 30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31 { 32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40 }; 41 42 static struct event_constraint intel_core_event_constraints[] __read_mostly = 43 { 44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50 EVENT_CONSTRAINT_END 51 }; 52 53 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54 { 55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68 EVENT_CONSTRAINT_END 69 }; 70 71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72 { 73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84 EVENT_CONSTRAINT_END 85 }; 86 87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88 { 89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92 EVENT_EXTRA_END 93 }; 94 95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96 { 97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104 EVENT_CONSTRAINT_END 105 }; 106 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108 { 109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121 122 /* 123 * When HT is off these events can only run on the bottom 4 counters 124 * When HT is on, they are impacted by the HT bug and require EXCL access 125 */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130 131 EVENT_CONSTRAINT_END 132 }; 133 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135 { 136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149 150 /* 151 * When HT is off these events can only run on the bottom 4 counters 152 * When HT is on, they are impacted by the HT bug and require EXCL access 153 */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158 159 EVENT_CONSTRAINT_END 160 }; 161 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163 { 164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168 EVENT_EXTRA_END 169 }; 170 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172 { 173 EVENT_CONSTRAINT_END 174 }; 175 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177 { 178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181 EVENT_CONSTRAINT_END 182 }; 183 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185 { 186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189 EVENT_CONSTRAINT_END 190 }; 191 192 static struct event_constraint intel_skl_event_constraints[] = { 193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 197 198 /* 199 * when HT is off, these can only run on the bottom 4 counters 200 */ 201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 206 207 EVENT_CONSTRAINT_END 208 }; 209 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213 EVENT_EXTRA_END 214 }; 215 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221 EVENT_EXTRA_END 222 }; 223 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229 EVENT_EXTRA_END 230 }; 231 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236 /* 237 * Note the low 8 bits eventsel code is not a continuous field, containing 238 * some #GPing bits. These are masked out. 239 */ 240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241 EVENT_EXTRA_END 242 }; 243 244 static struct event_constraint intel_icl_event_constraints[] = { 245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 247 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 248 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 249 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 250 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 254 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 255 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 256 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 257 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 258 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 259 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 260 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 261 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 262 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 263 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 264 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 265 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 266 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 267 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 268 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 269 EVENT_CONSTRAINT_END 270 }; 271 272 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 273 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 274 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 275 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 276 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 277 EVENT_EXTRA_END 278 }; 279 280 static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 281 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 282 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 283 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 284 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 285 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 286 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 287 EVENT_EXTRA_END 288 }; 289 290 static struct event_constraint intel_spr_event_constraints[] = { 291 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 292 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 293 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 294 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 295 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 298 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 299 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 300 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 301 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 302 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 303 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 304 305 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 306 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 307 /* 308 * Generally event codes < 0x90 are restricted to counters 0-3. 309 * The 0x2E and 0x3C are exception, which has no restriction. 310 */ 311 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 312 313 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 314 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 315 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 316 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 317 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 318 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 319 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 320 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 321 /* 322 * Generally event codes >= 0x90 are likely to have no restrictions. 323 * The exception are defined as above. 324 */ 325 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 326 327 EVENT_CONSTRAINT_END 328 }; 329 330 331 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 332 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 333 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 334 335 static struct attribute *nhm_mem_events_attrs[] = { 336 EVENT_PTR(mem_ld_nhm), 337 NULL, 338 }; 339 340 /* 341 * topdown events for Intel Core CPUs. 342 * 343 * The events are all in slots, which is a free slot in a 4 wide 344 * pipeline. Some events are already reported in slots, for cycle 345 * events we multiply by the pipeline width (4). 346 * 347 * With Hyper Threading on, topdown metrics are either summed or averaged 348 * between the threads of a core: (count_t0 + count_t1). 349 * 350 * For the average case the metric is always scaled to pipeline width, 351 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 352 */ 353 354 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 355 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 356 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 357 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 358 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 359 "event=0xe,umask=0x1"); /* uops_issued.any */ 360 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 361 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 362 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 363 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 364 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 365 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 366 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 367 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 368 "4", "2"); 369 370 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 371 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 372 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 373 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 374 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 375 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 376 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 377 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 378 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 379 380 static struct attribute *snb_events_attrs[] = { 381 EVENT_PTR(td_slots_issued), 382 EVENT_PTR(td_slots_retired), 383 EVENT_PTR(td_fetch_bubbles), 384 EVENT_PTR(td_total_slots), 385 EVENT_PTR(td_total_slots_scale), 386 EVENT_PTR(td_recovery_bubbles), 387 EVENT_PTR(td_recovery_bubbles_scale), 388 NULL, 389 }; 390 391 static struct attribute *snb_mem_events_attrs[] = { 392 EVENT_PTR(mem_ld_snb), 393 EVENT_PTR(mem_st_snb), 394 NULL, 395 }; 396 397 static struct event_constraint intel_hsw_event_constraints[] = { 398 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 399 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 400 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 401 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 402 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 403 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 404 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 405 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 406 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 407 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 408 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 409 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 410 411 /* 412 * When HT is off these events can only run on the bottom 4 counters 413 * When HT is on, they are impacted by the HT bug and require EXCL access 414 */ 415 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 416 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 417 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 418 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 419 420 EVENT_CONSTRAINT_END 421 }; 422 423 static struct event_constraint intel_bdw_event_constraints[] = { 424 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 425 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 426 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 427 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 428 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 429 /* 430 * when HT is off, these can only run on the bottom 4 counters 431 */ 432 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 433 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 434 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 435 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 436 EVENT_CONSTRAINT_END 437 }; 438 439 static u64 intel_pmu_event_map(int hw_event) 440 { 441 return intel_perfmon_event_map[hw_event]; 442 } 443 444 static __initconst const u64 spr_hw_cache_event_ids 445 [PERF_COUNT_HW_CACHE_MAX] 446 [PERF_COUNT_HW_CACHE_OP_MAX] 447 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 448 { 449 [ C(L1D ) ] = { 450 [ C(OP_READ) ] = { 451 [ C(RESULT_ACCESS) ] = 0x81d0, 452 [ C(RESULT_MISS) ] = 0xe124, 453 }, 454 [ C(OP_WRITE) ] = { 455 [ C(RESULT_ACCESS) ] = 0x82d0, 456 }, 457 }, 458 [ C(L1I ) ] = { 459 [ C(OP_READ) ] = { 460 [ C(RESULT_MISS) ] = 0xe424, 461 }, 462 [ C(OP_WRITE) ] = { 463 [ C(RESULT_ACCESS) ] = -1, 464 [ C(RESULT_MISS) ] = -1, 465 }, 466 }, 467 [ C(LL ) ] = { 468 [ C(OP_READ) ] = { 469 [ C(RESULT_ACCESS) ] = 0x12a, 470 [ C(RESULT_MISS) ] = 0x12a, 471 }, 472 [ C(OP_WRITE) ] = { 473 [ C(RESULT_ACCESS) ] = 0x12a, 474 [ C(RESULT_MISS) ] = 0x12a, 475 }, 476 }, 477 [ C(DTLB) ] = { 478 [ C(OP_READ) ] = { 479 [ C(RESULT_ACCESS) ] = 0x81d0, 480 [ C(RESULT_MISS) ] = 0xe12, 481 }, 482 [ C(OP_WRITE) ] = { 483 [ C(RESULT_ACCESS) ] = 0x82d0, 484 [ C(RESULT_MISS) ] = 0xe13, 485 }, 486 }, 487 [ C(ITLB) ] = { 488 [ C(OP_READ) ] = { 489 [ C(RESULT_ACCESS) ] = -1, 490 [ C(RESULT_MISS) ] = 0xe11, 491 }, 492 [ C(OP_WRITE) ] = { 493 [ C(RESULT_ACCESS) ] = -1, 494 [ C(RESULT_MISS) ] = -1, 495 }, 496 [ C(OP_PREFETCH) ] = { 497 [ C(RESULT_ACCESS) ] = -1, 498 [ C(RESULT_MISS) ] = -1, 499 }, 500 }, 501 [ C(BPU ) ] = { 502 [ C(OP_READ) ] = { 503 [ C(RESULT_ACCESS) ] = 0x4c4, 504 [ C(RESULT_MISS) ] = 0x4c5, 505 }, 506 [ C(OP_WRITE) ] = { 507 [ C(RESULT_ACCESS) ] = -1, 508 [ C(RESULT_MISS) ] = -1, 509 }, 510 [ C(OP_PREFETCH) ] = { 511 [ C(RESULT_ACCESS) ] = -1, 512 [ C(RESULT_MISS) ] = -1, 513 }, 514 }, 515 [ C(NODE) ] = { 516 [ C(OP_READ) ] = { 517 [ C(RESULT_ACCESS) ] = 0x12a, 518 [ C(RESULT_MISS) ] = 0x12a, 519 }, 520 }, 521 }; 522 523 static __initconst const u64 spr_hw_cache_extra_regs 524 [PERF_COUNT_HW_CACHE_MAX] 525 [PERF_COUNT_HW_CACHE_OP_MAX] 526 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 527 { 528 [ C(LL ) ] = { 529 [ C(OP_READ) ] = { 530 [ C(RESULT_ACCESS) ] = 0x10001, 531 [ C(RESULT_MISS) ] = 0x3fbfc00001, 532 }, 533 [ C(OP_WRITE) ] = { 534 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 535 [ C(RESULT_MISS) ] = 0x3f3fc00002, 536 }, 537 }, 538 [ C(NODE) ] = { 539 [ C(OP_READ) ] = { 540 [ C(RESULT_ACCESS) ] = 0x10c000001, 541 [ C(RESULT_MISS) ] = 0x3fb3000001, 542 }, 543 }, 544 }; 545 546 /* 547 * Notes on the events: 548 * - data reads do not include code reads (comparable to earlier tables) 549 * - data counts include speculative execution (except L1 write, dtlb, bpu) 550 * - remote node access includes remote memory, remote cache, remote mmio. 551 * - prefetches are not included in the counts. 552 * - icache miss does not include decoded icache 553 */ 554 555 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 556 #define SKL_DEMAND_RFO BIT_ULL(1) 557 #define SKL_ANY_RESPONSE BIT_ULL(16) 558 #define SKL_SUPPLIER_NONE BIT_ULL(17) 559 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 560 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 561 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 562 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 563 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 564 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 565 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 566 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 567 #define SKL_SPL_HIT BIT_ULL(30) 568 #define SKL_SNOOP_NONE BIT_ULL(31) 569 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 570 #define SKL_SNOOP_MISS BIT_ULL(33) 571 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 572 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 573 #define SKL_SNOOP_HITM BIT_ULL(36) 574 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 575 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 576 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 577 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 578 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 579 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 580 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 581 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 582 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 583 SKL_SNOOP_HITM|SKL_SPL_HIT) 584 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 585 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 586 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 587 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 588 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 589 590 static __initconst const u64 skl_hw_cache_event_ids 591 [PERF_COUNT_HW_CACHE_MAX] 592 [PERF_COUNT_HW_CACHE_OP_MAX] 593 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 594 { 595 [ C(L1D ) ] = { 596 [ C(OP_READ) ] = { 597 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 598 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 599 }, 600 [ C(OP_WRITE) ] = { 601 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 602 [ C(RESULT_MISS) ] = 0x0, 603 }, 604 [ C(OP_PREFETCH) ] = { 605 [ C(RESULT_ACCESS) ] = 0x0, 606 [ C(RESULT_MISS) ] = 0x0, 607 }, 608 }, 609 [ C(L1I ) ] = { 610 [ C(OP_READ) ] = { 611 [ C(RESULT_ACCESS) ] = 0x0, 612 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 613 }, 614 [ C(OP_WRITE) ] = { 615 [ C(RESULT_ACCESS) ] = -1, 616 [ C(RESULT_MISS) ] = -1, 617 }, 618 [ C(OP_PREFETCH) ] = { 619 [ C(RESULT_ACCESS) ] = 0x0, 620 [ C(RESULT_MISS) ] = 0x0, 621 }, 622 }, 623 [ C(LL ) ] = { 624 [ C(OP_READ) ] = { 625 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 626 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 627 }, 628 [ C(OP_WRITE) ] = { 629 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 630 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 631 }, 632 [ C(OP_PREFETCH) ] = { 633 [ C(RESULT_ACCESS) ] = 0x0, 634 [ C(RESULT_MISS) ] = 0x0, 635 }, 636 }, 637 [ C(DTLB) ] = { 638 [ C(OP_READ) ] = { 639 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 640 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 641 }, 642 [ C(OP_WRITE) ] = { 643 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 644 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 645 }, 646 [ C(OP_PREFETCH) ] = { 647 [ C(RESULT_ACCESS) ] = 0x0, 648 [ C(RESULT_MISS) ] = 0x0, 649 }, 650 }, 651 [ C(ITLB) ] = { 652 [ C(OP_READ) ] = { 653 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 654 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 655 }, 656 [ C(OP_WRITE) ] = { 657 [ C(RESULT_ACCESS) ] = -1, 658 [ C(RESULT_MISS) ] = -1, 659 }, 660 [ C(OP_PREFETCH) ] = { 661 [ C(RESULT_ACCESS) ] = -1, 662 [ C(RESULT_MISS) ] = -1, 663 }, 664 }, 665 [ C(BPU ) ] = { 666 [ C(OP_READ) ] = { 667 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 668 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 669 }, 670 [ C(OP_WRITE) ] = { 671 [ C(RESULT_ACCESS) ] = -1, 672 [ C(RESULT_MISS) ] = -1, 673 }, 674 [ C(OP_PREFETCH) ] = { 675 [ C(RESULT_ACCESS) ] = -1, 676 [ C(RESULT_MISS) ] = -1, 677 }, 678 }, 679 [ C(NODE) ] = { 680 [ C(OP_READ) ] = { 681 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 682 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 683 }, 684 [ C(OP_WRITE) ] = { 685 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 686 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 687 }, 688 [ C(OP_PREFETCH) ] = { 689 [ C(RESULT_ACCESS) ] = 0x0, 690 [ C(RESULT_MISS) ] = 0x0, 691 }, 692 }, 693 }; 694 695 static __initconst const u64 skl_hw_cache_extra_regs 696 [PERF_COUNT_HW_CACHE_MAX] 697 [PERF_COUNT_HW_CACHE_OP_MAX] 698 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 699 { 700 [ C(LL ) ] = { 701 [ C(OP_READ) ] = { 702 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 703 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 704 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 705 SKL_L3_MISS|SKL_ANY_SNOOP| 706 SKL_SUPPLIER_NONE, 707 }, 708 [ C(OP_WRITE) ] = { 709 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 710 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 711 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 712 SKL_L3_MISS|SKL_ANY_SNOOP| 713 SKL_SUPPLIER_NONE, 714 }, 715 [ C(OP_PREFETCH) ] = { 716 [ C(RESULT_ACCESS) ] = 0x0, 717 [ C(RESULT_MISS) ] = 0x0, 718 }, 719 }, 720 [ C(NODE) ] = { 721 [ C(OP_READ) ] = { 722 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 723 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 724 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 725 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 726 }, 727 [ C(OP_WRITE) ] = { 728 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 729 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 730 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 731 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 732 }, 733 [ C(OP_PREFETCH) ] = { 734 [ C(RESULT_ACCESS) ] = 0x0, 735 [ C(RESULT_MISS) ] = 0x0, 736 }, 737 }, 738 }; 739 740 #define SNB_DMND_DATA_RD (1ULL << 0) 741 #define SNB_DMND_RFO (1ULL << 1) 742 #define SNB_DMND_IFETCH (1ULL << 2) 743 #define SNB_DMND_WB (1ULL << 3) 744 #define SNB_PF_DATA_RD (1ULL << 4) 745 #define SNB_PF_RFO (1ULL << 5) 746 #define SNB_PF_IFETCH (1ULL << 6) 747 #define SNB_LLC_DATA_RD (1ULL << 7) 748 #define SNB_LLC_RFO (1ULL << 8) 749 #define SNB_LLC_IFETCH (1ULL << 9) 750 #define SNB_BUS_LOCKS (1ULL << 10) 751 #define SNB_STRM_ST (1ULL << 11) 752 #define SNB_OTHER (1ULL << 15) 753 #define SNB_RESP_ANY (1ULL << 16) 754 #define SNB_NO_SUPP (1ULL << 17) 755 #define SNB_LLC_HITM (1ULL << 18) 756 #define SNB_LLC_HITE (1ULL << 19) 757 #define SNB_LLC_HITS (1ULL << 20) 758 #define SNB_LLC_HITF (1ULL << 21) 759 #define SNB_LOCAL (1ULL << 22) 760 #define SNB_REMOTE (0xffULL << 23) 761 #define SNB_SNP_NONE (1ULL << 31) 762 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 763 #define SNB_SNP_MISS (1ULL << 33) 764 #define SNB_NO_FWD (1ULL << 34) 765 #define SNB_SNP_FWD (1ULL << 35) 766 #define SNB_HITM (1ULL << 36) 767 #define SNB_NON_DRAM (1ULL << 37) 768 769 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 770 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 771 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 772 773 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 774 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 775 SNB_HITM) 776 777 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 778 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 779 780 #define SNB_L3_ACCESS SNB_RESP_ANY 781 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 782 783 static __initconst const u64 snb_hw_cache_extra_regs 784 [PERF_COUNT_HW_CACHE_MAX] 785 [PERF_COUNT_HW_CACHE_OP_MAX] 786 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 787 { 788 [ C(LL ) ] = { 789 [ C(OP_READ) ] = { 790 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 791 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 792 }, 793 [ C(OP_WRITE) ] = { 794 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 795 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 796 }, 797 [ C(OP_PREFETCH) ] = { 798 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 799 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 800 }, 801 }, 802 [ C(NODE) ] = { 803 [ C(OP_READ) ] = { 804 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 805 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 806 }, 807 [ C(OP_WRITE) ] = { 808 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 809 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 810 }, 811 [ C(OP_PREFETCH) ] = { 812 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 813 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 814 }, 815 }, 816 }; 817 818 static __initconst const u64 snb_hw_cache_event_ids 819 [PERF_COUNT_HW_CACHE_MAX] 820 [PERF_COUNT_HW_CACHE_OP_MAX] 821 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 822 { 823 [ C(L1D) ] = { 824 [ C(OP_READ) ] = { 825 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 826 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 827 }, 828 [ C(OP_WRITE) ] = { 829 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 830 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 831 }, 832 [ C(OP_PREFETCH) ] = { 833 [ C(RESULT_ACCESS) ] = 0x0, 834 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 835 }, 836 }, 837 [ C(L1I ) ] = { 838 [ C(OP_READ) ] = { 839 [ C(RESULT_ACCESS) ] = 0x0, 840 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 841 }, 842 [ C(OP_WRITE) ] = { 843 [ C(RESULT_ACCESS) ] = -1, 844 [ C(RESULT_MISS) ] = -1, 845 }, 846 [ C(OP_PREFETCH) ] = { 847 [ C(RESULT_ACCESS) ] = 0x0, 848 [ C(RESULT_MISS) ] = 0x0, 849 }, 850 }, 851 [ C(LL ) ] = { 852 [ C(OP_READ) ] = { 853 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 854 [ C(RESULT_ACCESS) ] = 0x01b7, 855 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 856 [ C(RESULT_MISS) ] = 0x01b7, 857 }, 858 [ C(OP_WRITE) ] = { 859 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 860 [ C(RESULT_ACCESS) ] = 0x01b7, 861 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 862 [ C(RESULT_MISS) ] = 0x01b7, 863 }, 864 [ C(OP_PREFETCH) ] = { 865 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 866 [ C(RESULT_ACCESS) ] = 0x01b7, 867 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 868 [ C(RESULT_MISS) ] = 0x01b7, 869 }, 870 }, 871 [ C(DTLB) ] = { 872 [ C(OP_READ) ] = { 873 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 874 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 875 }, 876 [ C(OP_WRITE) ] = { 877 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 878 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 879 }, 880 [ C(OP_PREFETCH) ] = { 881 [ C(RESULT_ACCESS) ] = 0x0, 882 [ C(RESULT_MISS) ] = 0x0, 883 }, 884 }, 885 [ C(ITLB) ] = { 886 [ C(OP_READ) ] = { 887 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 888 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 889 }, 890 [ C(OP_WRITE) ] = { 891 [ C(RESULT_ACCESS) ] = -1, 892 [ C(RESULT_MISS) ] = -1, 893 }, 894 [ C(OP_PREFETCH) ] = { 895 [ C(RESULT_ACCESS) ] = -1, 896 [ C(RESULT_MISS) ] = -1, 897 }, 898 }, 899 [ C(BPU ) ] = { 900 [ C(OP_READ) ] = { 901 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 902 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 903 }, 904 [ C(OP_WRITE) ] = { 905 [ C(RESULT_ACCESS) ] = -1, 906 [ C(RESULT_MISS) ] = -1, 907 }, 908 [ C(OP_PREFETCH) ] = { 909 [ C(RESULT_ACCESS) ] = -1, 910 [ C(RESULT_MISS) ] = -1, 911 }, 912 }, 913 [ C(NODE) ] = { 914 [ C(OP_READ) ] = { 915 [ C(RESULT_ACCESS) ] = 0x01b7, 916 [ C(RESULT_MISS) ] = 0x01b7, 917 }, 918 [ C(OP_WRITE) ] = { 919 [ C(RESULT_ACCESS) ] = 0x01b7, 920 [ C(RESULT_MISS) ] = 0x01b7, 921 }, 922 [ C(OP_PREFETCH) ] = { 923 [ C(RESULT_ACCESS) ] = 0x01b7, 924 [ C(RESULT_MISS) ] = 0x01b7, 925 }, 926 }, 927 928 }; 929 930 /* 931 * Notes on the events: 932 * - data reads do not include code reads (comparable to earlier tables) 933 * - data counts include speculative execution (except L1 write, dtlb, bpu) 934 * - remote node access includes remote memory, remote cache, remote mmio. 935 * - prefetches are not included in the counts because they are not 936 * reliably counted. 937 */ 938 939 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 940 #define HSW_DEMAND_RFO BIT_ULL(1) 941 #define HSW_ANY_RESPONSE BIT_ULL(16) 942 #define HSW_SUPPLIER_NONE BIT_ULL(17) 943 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 944 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 945 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 946 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 947 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 948 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 949 HSW_L3_MISS_REMOTE_HOP2P) 950 #define HSW_SNOOP_NONE BIT_ULL(31) 951 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 952 #define HSW_SNOOP_MISS BIT_ULL(33) 953 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 954 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 955 #define HSW_SNOOP_HITM BIT_ULL(36) 956 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 957 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 958 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 959 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 960 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 961 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 962 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 963 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 964 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 965 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 966 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 967 968 #define BDW_L3_MISS_LOCAL BIT(26) 969 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 970 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 971 HSW_L3_MISS_REMOTE_HOP2P) 972 973 974 static __initconst const u64 hsw_hw_cache_event_ids 975 [PERF_COUNT_HW_CACHE_MAX] 976 [PERF_COUNT_HW_CACHE_OP_MAX] 977 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 978 { 979 [ C(L1D ) ] = { 980 [ C(OP_READ) ] = { 981 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 982 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 983 }, 984 [ C(OP_WRITE) ] = { 985 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 986 [ C(RESULT_MISS) ] = 0x0, 987 }, 988 [ C(OP_PREFETCH) ] = { 989 [ C(RESULT_ACCESS) ] = 0x0, 990 [ C(RESULT_MISS) ] = 0x0, 991 }, 992 }, 993 [ C(L1I ) ] = { 994 [ C(OP_READ) ] = { 995 [ C(RESULT_ACCESS) ] = 0x0, 996 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 997 }, 998 [ C(OP_WRITE) ] = { 999 [ C(RESULT_ACCESS) ] = -1, 1000 [ C(RESULT_MISS) ] = -1, 1001 }, 1002 [ C(OP_PREFETCH) ] = { 1003 [ C(RESULT_ACCESS) ] = 0x0, 1004 [ C(RESULT_MISS) ] = 0x0, 1005 }, 1006 }, 1007 [ C(LL ) ] = { 1008 [ C(OP_READ) ] = { 1009 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1010 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1011 }, 1012 [ C(OP_WRITE) ] = { 1013 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1014 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1015 }, 1016 [ C(OP_PREFETCH) ] = { 1017 [ C(RESULT_ACCESS) ] = 0x0, 1018 [ C(RESULT_MISS) ] = 0x0, 1019 }, 1020 }, 1021 [ C(DTLB) ] = { 1022 [ C(OP_READ) ] = { 1023 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1024 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1025 }, 1026 [ C(OP_WRITE) ] = { 1027 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1028 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1029 }, 1030 [ C(OP_PREFETCH) ] = { 1031 [ C(RESULT_ACCESS) ] = 0x0, 1032 [ C(RESULT_MISS) ] = 0x0, 1033 }, 1034 }, 1035 [ C(ITLB) ] = { 1036 [ C(OP_READ) ] = { 1037 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1038 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1039 }, 1040 [ C(OP_WRITE) ] = { 1041 [ C(RESULT_ACCESS) ] = -1, 1042 [ C(RESULT_MISS) ] = -1, 1043 }, 1044 [ C(OP_PREFETCH) ] = { 1045 [ C(RESULT_ACCESS) ] = -1, 1046 [ C(RESULT_MISS) ] = -1, 1047 }, 1048 }, 1049 [ C(BPU ) ] = { 1050 [ C(OP_READ) ] = { 1051 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1052 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1053 }, 1054 [ C(OP_WRITE) ] = { 1055 [ C(RESULT_ACCESS) ] = -1, 1056 [ C(RESULT_MISS) ] = -1, 1057 }, 1058 [ C(OP_PREFETCH) ] = { 1059 [ C(RESULT_ACCESS) ] = -1, 1060 [ C(RESULT_MISS) ] = -1, 1061 }, 1062 }, 1063 [ C(NODE) ] = { 1064 [ C(OP_READ) ] = { 1065 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1066 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1067 }, 1068 [ C(OP_WRITE) ] = { 1069 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1070 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1071 }, 1072 [ C(OP_PREFETCH) ] = { 1073 [ C(RESULT_ACCESS) ] = 0x0, 1074 [ C(RESULT_MISS) ] = 0x0, 1075 }, 1076 }, 1077 }; 1078 1079 static __initconst const u64 hsw_hw_cache_extra_regs 1080 [PERF_COUNT_HW_CACHE_MAX] 1081 [PERF_COUNT_HW_CACHE_OP_MAX] 1082 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1083 { 1084 [ C(LL ) ] = { 1085 [ C(OP_READ) ] = { 1086 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1087 HSW_LLC_ACCESS, 1088 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1089 HSW_L3_MISS|HSW_ANY_SNOOP, 1090 }, 1091 [ C(OP_WRITE) ] = { 1092 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1093 HSW_LLC_ACCESS, 1094 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1095 HSW_L3_MISS|HSW_ANY_SNOOP, 1096 }, 1097 [ C(OP_PREFETCH) ] = { 1098 [ C(RESULT_ACCESS) ] = 0x0, 1099 [ C(RESULT_MISS) ] = 0x0, 1100 }, 1101 }, 1102 [ C(NODE) ] = { 1103 [ C(OP_READ) ] = { 1104 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1105 HSW_L3_MISS_LOCAL_DRAM| 1106 HSW_SNOOP_DRAM, 1107 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1108 HSW_L3_MISS_REMOTE| 1109 HSW_SNOOP_DRAM, 1110 }, 1111 [ C(OP_WRITE) ] = { 1112 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1113 HSW_L3_MISS_LOCAL_DRAM| 1114 HSW_SNOOP_DRAM, 1115 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1116 HSW_L3_MISS_REMOTE| 1117 HSW_SNOOP_DRAM, 1118 }, 1119 [ C(OP_PREFETCH) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x0, 1121 [ C(RESULT_MISS) ] = 0x0, 1122 }, 1123 }, 1124 }; 1125 1126 static __initconst const u64 westmere_hw_cache_event_ids 1127 [PERF_COUNT_HW_CACHE_MAX] 1128 [PERF_COUNT_HW_CACHE_OP_MAX] 1129 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1130 { 1131 [ C(L1D) ] = { 1132 [ C(OP_READ) ] = { 1133 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1134 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1135 }, 1136 [ C(OP_WRITE) ] = { 1137 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1138 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1139 }, 1140 [ C(OP_PREFETCH) ] = { 1141 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1142 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1143 }, 1144 }, 1145 [ C(L1I ) ] = { 1146 [ C(OP_READ) ] = { 1147 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1148 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1149 }, 1150 [ C(OP_WRITE) ] = { 1151 [ C(RESULT_ACCESS) ] = -1, 1152 [ C(RESULT_MISS) ] = -1, 1153 }, 1154 [ C(OP_PREFETCH) ] = { 1155 [ C(RESULT_ACCESS) ] = 0x0, 1156 [ C(RESULT_MISS) ] = 0x0, 1157 }, 1158 }, 1159 [ C(LL ) ] = { 1160 [ C(OP_READ) ] = { 1161 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1162 [ C(RESULT_ACCESS) ] = 0x01b7, 1163 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1164 [ C(RESULT_MISS) ] = 0x01b7, 1165 }, 1166 /* 1167 * Use RFO, not WRITEBACK, because a write miss would typically occur 1168 * on RFO. 1169 */ 1170 [ C(OP_WRITE) ] = { 1171 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1172 [ C(RESULT_ACCESS) ] = 0x01b7, 1173 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1174 [ C(RESULT_MISS) ] = 0x01b7, 1175 }, 1176 [ C(OP_PREFETCH) ] = { 1177 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1178 [ C(RESULT_ACCESS) ] = 0x01b7, 1179 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1180 [ C(RESULT_MISS) ] = 0x01b7, 1181 }, 1182 }, 1183 [ C(DTLB) ] = { 1184 [ C(OP_READ) ] = { 1185 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1186 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1187 }, 1188 [ C(OP_WRITE) ] = { 1189 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1190 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1191 }, 1192 [ C(OP_PREFETCH) ] = { 1193 [ C(RESULT_ACCESS) ] = 0x0, 1194 [ C(RESULT_MISS) ] = 0x0, 1195 }, 1196 }, 1197 [ C(ITLB) ] = { 1198 [ C(OP_READ) ] = { 1199 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1200 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1201 }, 1202 [ C(OP_WRITE) ] = { 1203 [ C(RESULT_ACCESS) ] = -1, 1204 [ C(RESULT_MISS) ] = -1, 1205 }, 1206 [ C(OP_PREFETCH) ] = { 1207 [ C(RESULT_ACCESS) ] = -1, 1208 [ C(RESULT_MISS) ] = -1, 1209 }, 1210 }, 1211 [ C(BPU ) ] = { 1212 [ C(OP_READ) ] = { 1213 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1214 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1215 }, 1216 [ C(OP_WRITE) ] = { 1217 [ C(RESULT_ACCESS) ] = -1, 1218 [ C(RESULT_MISS) ] = -1, 1219 }, 1220 [ C(OP_PREFETCH) ] = { 1221 [ C(RESULT_ACCESS) ] = -1, 1222 [ C(RESULT_MISS) ] = -1, 1223 }, 1224 }, 1225 [ C(NODE) ] = { 1226 [ C(OP_READ) ] = { 1227 [ C(RESULT_ACCESS) ] = 0x01b7, 1228 [ C(RESULT_MISS) ] = 0x01b7, 1229 }, 1230 [ C(OP_WRITE) ] = { 1231 [ C(RESULT_ACCESS) ] = 0x01b7, 1232 [ C(RESULT_MISS) ] = 0x01b7, 1233 }, 1234 [ C(OP_PREFETCH) ] = { 1235 [ C(RESULT_ACCESS) ] = 0x01b7, 1236 [ C(RESULT_MISS) ] = 0x01b7, 1237 }, 1238 }, 1239 }; 1240 1241 /* 1242 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1243 * See IA32 SDM Vol 3B 30.6.1.3 1244 */ 1245 1246 #define NHM_DMND_DATA_RD (1 << 0) 1247 #define NHM_DMND_RFO (1 << 1) 1248 #define NHM_DMND_IFETCH (1 << 2) 1249 #define NHM_DMND_WB (1 << 3) 1250 #define NHM_PF_DATA_RD (1 << 4) 1251 #define NHM_PF_DATA_RFO (1 << 5) 1252 #define NHM_PF_IFETCH (1 << 6) 1253 #define NHM_OFFCORE_OTHER (1 << 7) 1254 #define NHM_UNCORE_HIT (1 << 8) 1255 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1256 #define NHM_OTHER_CORE_HITM (1 << 10) 1257 /* reserved */ 1258 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1259 #define NHM_REMOTE_DRAM (1 << 13) 1260 #define NHM_LOCAL_DRAM (1 << 14) 1261 #define NHM_NON_DRAM (1 << 15) 1262 1263 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1264 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1265 1266 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1267 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1268 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1269 1270 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1271 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1272 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1273 1274 static __initconst const u64 nehalem_hw_cache_extra_regs 1275 [PERF_COUNT_HW_CACHE_MAX] 1276 [PERF_COUNT_HW_CACHE_OP_MAX] 1277 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1278 { 1279 [ C(LL ) ] = { 1280 [ C(OP_READ) ] = { 1281 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1282 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1283 }, 1284 [ C(OP_WRITE) ] = { 1285 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1286 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1287 }, 1288 [ C(OP_PREFETCH) ] = { 1289 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1290 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1291 }, 1292 }, 1293 [ C(NODE) ] = { 1294 [ C(OP_READ) ] = { 1295 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1296 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1297 }, 1298 [ C(OP_WRITE) ] = { 1299 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1300 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1301 }, 1302 [ C(OP_PREFETCH) ] = { 1303 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1304 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1305 }, 1306 }, 1307 }; 1308 1309 static __initconst const u64 nehalem_hw_cache_event_ids 1310 [PERF_COUNT_HW_CACHE_MAX] 1311 [PERF_COUNT_HW_CACHE_OP_MAX] 1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1313 { 1314 [ C(L1D) ] = { 1315 [ C(OP_READ) ] = { 1316 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1317 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1318 }, 1319 [ C(OP_WRITE) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1321 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1322 }, 1323 [ C(OP_PREFETCH) ] = { 1324 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1325 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1326 }, 1327 }, 1328 [ C(L1I ) ] = { 1329 [ C(OP_READ) ] = { 1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1332 }, 1333 [ C(OP_WRITE) ] = { 1334 [ C(RESULT_ACCESS) ] = -1, 1335 [ C(RESULT_MISS) ] = -1, 1336 }, 1337 [ C(OP_PREFETCH) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x0, 1339 [ C(RESULT_MISS) ] = 0x0, 1340 }, 1341 }, 1342 [ C(LL ) ] = { 1343 [ C(OP_READ) ] = { 1344 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1345 [ C(RESULT_ACCESS) ] = 0x01b7, 1346 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1347 [ C(RESULT_MISS) ] = 0x01b7, 1348 }, 1349 /* 1350 * Use RFO, not WRITEBACK, because a write miss would typically occur 1351 * on RFO. 1352 */ 1353 [ C(OP_WRITE) ] = { 1354 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1355 [ C(RESULT_ACCESS) ] = 0x01b7, 1356 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1357 [ C(RESULT_MISS) ] = 0x01b7, 1358 }, 1359 [ C(OP_PREFETCH) ] = { 1360 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1361 [ C(RESULT_ACCESS) ] = 0x01b7, 1362 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1363 [ C(RESULT_MISS) ] = 0x01b7, 1364 }, 1365 }, 1366 [ C(DTLB) ] = { 1367 [ C(OP_READ) ] = { 1368 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1369 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1370 }, 1371 [ C(OP_WRITE) ] = { 1372 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1373 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1374 }, 1375 [ C(OP_PREFETCH) ] = { 1376 [ C(RESULT_ACCESS) ] = 0x0, 1377 [ C(RESULT_MISS) ] = 0x0, 1378 }, 1379 }, 1380 [ C(ITLB) ] = { 1381 [ C(OP_READ) ] = { 1382 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1383 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1384 }, 1385 [ C(OP_WRITE) ] = { 1386 [ C(RESULT_ACCESS) ] = -1, 1387 [ C(RESULT_MISS) ] = -1, 1388 }, 1389 [ C(OP_PREFETCH) ] = { 1390 [ C(RESULT_ACCESS) ] = -1, 1391 [ C(RESULT_MISS) ] = -1, 1392 }, 1393 }, 1394 [ C(BPU ) ] = { 1395 [ C(OP_READ) ] = { 1396 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1397 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1398 }, 1399 [ C(OP_WRITE) ] = { 1400 [ C(RESULT_ACCESS) ] = -1, 1401 [ C(RESULT_MISS) ] = -1, 1402 }, 1403 [ C(OP_PREFETCH) ] = { 1404 [ C(RESULT_ACCESS) ] = -1, 1405 [ C(RESULT_MISS) ] = -1, 1406 }, 1407 }, 1408 [ C(NODE) ] = { 1409 [ C(OP_READ) ] = { 1410 [ C(RESULT_ACCESS) ] = 0x01b7, 1411 [ C(RESULT_MISS) ] = 0x01b7, 1412 }, 1413 [ C(OP_WRITE) ] = { 1414 [ C(RESULT_ACCESS) ] = 0x01b7, 1415 [ C(RESULT_MISS) ] = 0x01b7, 1416 }, 1417 [ C(OP_PREFETCH) ] = { 1418 [ C(RESULT_ACCESS) ] = 0x01b7, 1419 [ C(RESULT_MISS) ] = 0x01b7, 1420 }, 1421 }, 1422 }; 1423 1424 static __initconst const u64 core2_hw_cache_event_ids 1425 [PERF_COUNT_HW_CACHE_MAX] 1426 [PERF_COUNT_HW_CACHE_OP_MAX] 1427 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1428 { 1429 [ C(L1D) ] = { 1430 [ C(OP_READ) ] = { 1431 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1432 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1433 }, 1434 [ C(OP_WRITE) ] = { 1435 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1436 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1437 }, 1438 [ C(OP_PREFETCH) ] = { 1439 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1440 [ C(RESULT_MISS) ] = 0, 1441 }, 1442 }, 1443 [ C(L1I ) ] = { 1444 [ C(OP_READ) ] = { 1445 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1446 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1447 }, 1448 [ C(OP_WRITE) ] = { 1449 [ C(RESULT_ACCESS) ] = -1, 1450 [ C(RESULT_MISS) ] = -1, 1451 }, 1452 [ C(OP_PREFETCH) ] = { 1453 [ C(RESULT_ACCESS) ] = 0, 1454 [ C(RESULT_MISS) ] = 0, 1455 }, 1456 }, 1457 [ C(LL ) ] = { 1458 [ C(OP_READ) ] = { 1459 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1460 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1461 }, 1462 [ C(OP_WRITE) ] = { 1463 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1464 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1465 }, 1466 [ C(OP_PREFETCH) ] = { 1467 [ C(RESULT_ACCESS) ] = 0, 1468 [ C(RESULT_MISS) ] = 0, 1469 }, 1470 }, 1471 [ C(DTLB) ] = { 1472 [ C(OP_READ) ] = { 1473 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1474 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1475 }, 1476 [ C(OP_WRITE) ] = { 1477 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1478 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1479 }, 1480 [ C(OP_PREFETCH) ] = { 1481 [ C(RESULT_ACCESS) ] = 0, 1482 [ C(RESULT_MISS) ] = 0, 1483 }, 1484 }, 1485 [ C(ITLB) ] = { 1486 [ C(OP_READ) ] = { 1487 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1488 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1489 }, 1490 [ C(OP_WRITE) ] = { 1491 [ C(RESULT_ACCESS) ] = -1, 1492 [ C(RESULT_MISS) ] = -1, 1493 }, 1494 [ C(OP_PREFETCH) ] = { 1495 [ C(RESULT_ACCESS) ] = -1, 1496 [ C(RESULT_MISS) ] = -1, 1497 }, 1498 }, 1499 [ C(BPU ) ] = { 1500 [ C(OP_READ) ] = { 1501 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1502 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1503 }, 1504 [ C(OP_WRITE) ] = { 1505 [ C(RESULT_ACCESS) ] = -1, 1506 [ C(RESULT_MISS) ] = -1, 1507 }, 1508 [ C(OP_PREFETCH) ] = { 1509 [ C(RESULT_ACCESS) ] = -1, 1510 [ C(RESULT_MISS) ] = -1, 1511 }, 1512 }, 1513 }; 1514 1515 static __initconst const u64 atom_hw_cache_event_ids 1516 [PERF_COUNT_HW_CACHE_MAX] 1517 [PERF_COUNT_HW_CACHE_OP_MAX] 1518 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1519 { 1520 [ C(L1D) ] = { 1521 [ C(OP_READ) ] = { 1522 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1523 [ C(RESULT_MISS) ] = 0, 1524 }, 1525 [ C(OP_WRITE) ] = { 1526 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1527 [ C(RESULT_MISS) ] = 0, 1528 }, 1529 [ C(OP_PREFETCH) ] = { 1530 [ C(RESULT_ACCESS) ] = 0x0, 1531 [ C(RESULT_MISS) ] = 0, 1532 }, 1533 }, 1534 [ C(L1I ) ] = { 1535 [ C(OP_READ) ] = { 1536 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1537 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1538 }, 1539 [ C(OP_WRITE) ] = { 1540 [ C(RESULT_ACCESS) ] = -1, 1541 [ C(RESULT_MISS) ] = -1, 1542 }, 1543 [ C(OP_PREFETCH) ] = { 1544 [ C(RESULT_ACCESS) ] = 0, 1545 [ C(RESULT_MISS) ] = 0, 1546 }, 1547 }, 1548 [ C(LL ) ] = { 1549 [ C(OP_READ) ] = { 1550 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1551 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1552 }, 1553 [ C(OP_WRITE) ] = { 1554 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1555 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1556 }, 1557 [ C(OP_PREFETCH) ] = { 1558 [ C(RESULT_ACCESS) ] = 0, 1559 [ C(RESULT_MISS) ] = 0, 1560 }, 1561 }, 1562 [ C(DTLB) ] = { 1563 [ C(OP_READ) ] = { 1564 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1565 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1566 }, 1567 [ C(OP_WRITE) ] = { 1568 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1569 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1570 }, 1571 [ C(OP_PREFETCH) ] = { 1572 [ C(RESULT_ACCESS) ] = 0, 1573 [ C(RESULT_MISS) ] = 0, 1574 }, 1575 }, 1576 [ C(ITLB) ] = { 1577 [ C(OP_READ) ] = { 1578 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1579 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1580 }, 1581 [ C(OP_WRITE) ] = { 1582 [ C(RESULT_ACCESS) ] = -1, 1583 [ C(RESULT_MISS) ] = -1, 1584 }, 1585 [ C(OP_PREFETCH) ] = { 1586 [ C(RESULT_ACCESS) ] = -1, 1587 [ C(RESULT_MISS) ] = -1, 1588 }, 1589 }, 1590 [ C(BPU ) ] = { 1591 [ C(OP_READ) ] = { 1592 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1593 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1594 }, 1595 [ C(OP_WRITE) ] = { 1596 [ C(RESULT_ACCESS) ] = -1, 1597 [ C(RESULT_MISS) ] = -1, 1598 }, 1599 [ C(OP_PREFETCH) ] = { 1600 [ C(RESULT_ACCESS) ] = -1, 1601 [ C(RESULT_MISS) ] = -1, 1602 }, 1603 }, 1604 }; 1605 1606 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1607 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1608 /* no_alloc_cycles.not_delivered */ 1609 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1610 "event=0xca,umask=0x50"); 1611 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1612 /* uops_retired.all */ 1613 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1614 "event=0xc2,umask=0x10"); 1615 /* uops_retired.all */ 1616 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1617 "event=0xc2,umask=0x10"); 1618 1619 static struct attribute *slm_events_attrs[] = { 1620 EVENT_PTR(td_total_slots_slm), 1621 EVENT_PTR(td_total_slots_scale_slm), 1622 EVENT_PTR(td_fetch_bubbles_slm), 1623 EVENT_PTR(td_fetch_bubbles_scale_slm), 1624 EVENT_PTR(td_slots_issued_slm), 1625 EVENT_PTR(td_slots_retired_slm), 1626 NULL 1627 }; 1628 1629 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1630 { 1631 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1632 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1633 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1634 EVENT_EXTRA_END 1635 }; 1636 1637 #define SLM_DMND_READ SNB_DMND_DATA_RD 1638 #define SLM_DMND_WRITE SNB_DMND_RFO 1639 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1640 1641 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1642 #define SLM_LLC_ACCESS SNB_RESP_ANY 1643 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1644 1645 static __initconst const u64 slm_hw_cache_extra_regs 1646 [PERF_COUNT_HW_CACHE_MAX] 1647 [PERF_COUNT_HW_CACHE_OP_MAX] 1648 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1649 { 1650 [ C(LL ) ] = { 1651 [ C(OP_READ) ] = { 1652 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1653 [ C(RESULT_MISS) ] = 0, 1654 }, 1655 [ C(OP_WRITE) ] = { 1656 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1657 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1658 }, 1659 [ C(OP_PREFETCH) ] = { 1660 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1661 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1662 }, 1663 }, 1664 }; 1665 1666 static __initconst const u64 slm_hw_cache_event_ids 1667 [PERF_COUNT_HW_CACHE_MAX] 1668 [PERF_COUNT_HW_CACHE_OP_MAX] 1669 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1670 { 1671 [ C(L1D) ] = { 1672 [ C(OP_READ) ] = { 1673 [ C(RESULT_ACCESS) ] = 0, 1674 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1675 }, 1676 [ C(OP_WRITE) ] = { 1677 [ C(RESULT_ACCESS) ] = 0, 1678 [ C(RESULT_MISS) ] = 0, 1679 }, 1680 [ C(OP_PREFETCH) ] = { 1681 [ C(RESULT_ACCESS) ] = 0, 1682 [ C(RESULT_MISS) ] = 0, 1683 }, 1684 }, 1685 [ C(L1I ) ] = { 1686 [ C(OP_READ) ] = { 1687 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1688 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1689 }, 1690 [ C(OP_WRITE) ] = { 1691 [ C(RESULT_ACCESS) ] = -1, 1692 [ C(RESULT_MISS) ] = -1, 1693 }, 1694 [ C(OP_PREFETCH) ] = { 1695 [ C(RESULT_ACCESS) ] = 0, 1696 [ C(RESULT_MISS) ] = 0, 1697 }, 1698 }, 1699 [ C(LL ) ] = { 1700 [ C(OP_READ) ] = { 1701 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1702 [ C(RESULT_ACCESS) ] = 0x01b7, 1703 [ C(RESULT_MISS) ] = 0, 1704 }, 1705 [ C(OP_WRITE) ] = { 1706 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1707 [ C(RESULT_ACCESS) ] = 0x01b7, 1708 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1709 [ C(RESULT_MISS) ] = 0x01b7, 1710 }, 1711 [ C(OP_PREFETCH) ] = { 1712 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1713 [ C(RESULT_ACCESS) ] = 0x01b7, 1714 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1715 [ C(RESULT_MISS) ] = 0x01b7, 1716 }, 1717 }, 1718 [ C(DTLB) ] = { 1719 [ C(OP_READ) ] = { 1720 [ C(RESULT_ACCESS) ] = 0, 1721 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1722 }, 1723 [ C(OP_WRITE) ] = { 1724 [ C(RESULT_ACCESS) ] = 0, 1725 [ C(RESULT_MISS) ] = 0, 1726 }, 1727 [ C(OP_PREFETCH) ] = { 1728 [ C(RESULT_ACCESS) ] = 0, 1729 [ C(RESULT_MISS) ] = 0, 1730 }, 1731 }, 1732 [ C(ITLB) ] = { 1733 [ C(OP_READ) ] = { 1734 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1735 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1736 }, 1737 [ C(OP_WRITE) ] = { 1738 [ C(RESULT_ACCESS) ] = -1, 1739 [ C(RESULT_MISS) ] = -1, 1740 }, 1741 [ C(OP_PREFETCH) ] = { 1742 [ C(RESULT_ACCESS) ] = -1, 1743 [ C(RESULT_MISS) ] = -1, 1744 }, 1745 }, 1746 [ C(BPU ) ] = { 1747 [ C(OP_READ) ] = { 1748 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1749 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1750 }, 1751 [ C(OP_WRITE) ] = { 1752 [ C(RESULT_ACCESS) ] = -1, 1753 [ C(RESULT_MISS) ] = -1, 1754 }, 1755 [ C(OP_PREFETCH) ] = { 1756 [ C(RESULT_ACCESS) ] = -1, 1757 [ C(RESULT_MISS) ] = -1, 1758 }, 1759 }, 1760 }; 1761 1762 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1763 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1764 /* UOPS_NOT_DELIVERED.ANY */ 1765 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1766 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1767 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1768 /* UOPS_RETIRED.ANY */ 1769 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1770 /* UOPS_ISSUED.ANY */ 1771 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1772 1773 static struct attribute *glm_events_attrs[] = { 1774 EVENT_PTR(td_total_slots_glm), 1775 EVENT_PTR(td_total_slots_scale_glm), 1776 EVENT_PTR(td_fetch_bubbles_glm), 1777 EVENT_PTR(td_recovery_bubbles_glm), 1778 EVENT_PTR(td_slots_issued_glm), 1779 EVENT_PTR(td_slots_retired_glm), 1780 NULL 1781 }; 1782 1783 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1784 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1785 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1786 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1787 EVENT_EXTRA_END 1788 }; 1789 1790 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1791 #define GLM_DEMAND_RFO BIT_ULL(1) 1792 #define GLM_ANY_RESPONSE BIT_ULL(16) 1793 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1794 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1795 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1796 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1797 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1798 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1799 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1800 1801 static __initconst const u64 glm_hw_cache_event_ids 1802 [PERF_COUNT_HW_CACHE_MAX] 1803 [PERF_COUNT_HW_CACHE_OP_MAX] 1804 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1805 [C(L1D)] = { 1806 [C(OP_READ)] = { 1807 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1808 [C(RESULT_MISS)] = 0x0, 1809 }, 1810 [C(OP_WRITE)] = { 1811 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1812 [C(RESULT_MISS)] = 0x0, 1813 }, 1814 [C(OP_PREFETCH)] = { 1815 [C(RESULT_ACCESS)] = 0x0, 1816 [C(RESULT_MISS)] = 0x0, 1817 }, 1818 }, 1819 [C(L1I)] = { 1820 [C(OP_READ)] = { 1821 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1822 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1823 }, 1824 [C(OP_WRITE)] = { 1825 [C(RESULT_ACCESS)] = -1, 1826 [C(RESULT_MISS)] = -1, 1827 }, 1828 [C(OP_PREFETCH)] = { 1829 [C(RESULT_ACCESS)] = 0x0, 1830 [C(RESULT_MISS)] = 0x0, 1831 }, 1832 }, 1833 [C(LL)] = { 1834 [C(OP_READ)] = { 1835 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1836 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1837 }, 1838 [C(OP_WRITE)] = { 1839 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1840 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1841 }, 1842 [C(OP_PREFETCH)] = { 1843 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1844 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1845 }, 1846 }, 1847 [C(DTLB)] = { 1848 [C(OP_READ)] = { 1849 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1850 [C(RESULT_MISS)] = 0x0, 1851 }, 1852 [C(OP_WRITE)] = { 1853 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1854 [C(RESULT_MISS)] = 0x0, 1855 }, 1856 [C(OP_PREFETCH)] = { 1857 [C(RESULT_ACCESS)] = 0x0, 1858 [C(RESULT_MISS)] = 0x0, 1859 }, 1860 }, 1861 [C(ITLB)] = { 1862 [C(OP_READ)] = { 1863 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1864 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1865 }, 1866 [C(OP_WRITE)] = { 1867 [C(RESULT_ACCESS)] = -1, 1868 [C(RESULT_MISS)] = -1, 1869 }, 1870 [C(OP_PREFETCH)] = { 1871 [C(RESULT_ACCESS)] = -1, 1872 [C(RESULT_MISS)] = -1, 1873 }, 1874 }, 1875 [C(BPU)] = { 1876 [C(OP_READ)] = { 1877 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1878 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1879 }, 1880 [C(OP_WRITE)] = { 1881 [C(RESULT_ACCESS)] = -1, 1882 [C(RESULT_MISS)] = -1, 1883 }, 1884 [C(OP_PREFETCH)] = { 1885 [C(RESULT_ACCESS)] = -1, 1886 [C(RESULT_MISS)] = -1, 1887 }, 1888 }, 1889 }; 1890 1891 static __initconst const u64 glm_hw_cache_extra_regs 1892 [PERF_COUNT_HW_CACHE_MAX] 1893 [PERF_COUNT_HW_CACHE_OP_MAX] 1894 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1895 [C(LL)] = { 1896 [C(OP_READ)] = { 1897 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1898 GLM_LLC_ACCESS, 1899 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1900 GLM_LLC_MISS, 1901 }, 1902 [C(OP_WRITE)] = { 1903 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1904 GLM_LLC_ACCESS, 1905 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1906 GLM_LLC_MISS, 1907 }, 1908 [C(OP_PREFETCH)] = { 1909 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1910 GLM_LLC_ACCESS, 1911 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1912 GLM_LLC_MISS, 1913 }, 1914 }, 1915 }; 1916 1917 static __initconst const u64 glp_hw_cache_event_ids 1918 [PERF_COUNT_HW_CACHE_MAX] 1919 [PERF_COUNT_HW_CACHE_OP_MAX] 1920 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1921 [C(L1D)] = { 1922 [C(OP_READ)] = { 1923 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1924 [C(RESULT_MISS)] = 0x0, 1925 }, 1926 [C(OP_WRITE)] = { 1927 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1928 [C(RESULT_MISS)] = 0x0, 1929 }, 1930 [C(OP_PREFETCH)] = { 1931 [C(RESULT_ACCESS)] = 0x0, 1932 [C(RESULT_MISS)] = 0x0, 1933 }, 1934 }, 1935 [C(L1I)] = { 1936 [C(OP_READ)] = { 1937 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1938 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1939 }, 1940 [C(OP_WRITE)] = { 1941 [C(RESULT_ACCESS)] = -1, 1942 [C(RESULT_MISS)] = -1, 1943 }, 1944 [C(OP_PREFETCH)] = { 1945 [C(RESULT_ACCESS)] = 0x0, 1946 [C(RESULT_MISS)] = 0x0, 1947 }, 1948 }, 1949 [C(LL)] = { 1950 [C(OP_READ)] = { 1951 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1953 }, 1954 [C(OP_WRITE)] = { 1955 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1956 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1957 }, 1958 [C(OP_PREFETCH)] = { 1959 [C(RESULT_ACCESS)] = 0x0, 1960 [C(RESULT_MISS)] = 0x0, 1961 }, 1962 }, 1963 [C(DTLB)] = { 1964 [C(OP_READ)] = { 1965 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1966 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1967 }, 1968 [C(OP_WRITE)] = { 1969 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1970 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1971 }, 1972 [C(OP_PREFETCH)] = { 1973 [C(RESULT_ACCESS)] = 0x0, 1974 [C(RESULT_MISS)] = 0x0, 1975 }, 1976 }, 1977 [C(ITLB)] = { 1978 [C(OP_READ)] = { 1979 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1980 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1981 }, 1982 [C(OP_WRITE)] = { 1983 [C(RESULT_ACCESS)] = -1, 1984 [C(RESULT_MISS)] = -1, 1985 }, 1986 [C(OP_PREFETCH)] = { 1987 [C(RESULT_ACCESS)] = -1, 1988 [C(RESULT_MISS)] = -1, 1989 }, 1990 }, 1991 [C(BPU)] = { 1992 [C(OP_READ)] = { 1993 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1994 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1995 }, 1996 [C(OP_WRITE)] = { 1997 [C(RESULT_ACCESS)] = -1, 1998 [C(RESULT_MISS)] = -1, 1999 }, 2000 [C(OP_PREFETCH)] = { 2001 [C(RESULT_ACCESS)] = -1, 2002 [C(RESULT_MISS)] = -1, 2003 }, 2004 }, 2005 }; 2006 2007 static __initconst const u64 glp_hw_cache_extra_regs 2008 [PERF_COUNT_HW_CACHE_MAX] 2009 [PERF_COUNT_HW_CACHE_OP_MAX] 2010 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2011 [C(LL)] = { 2012 [C(OP_READ)] = { 2013 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2014 GLM_LLC_ACCESS, 2015 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2016 GLM_LLC_MISS, 2017 }, 2018 [C(OP_WRITE)] = { 2019 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2020 GLM_LLC_ACCESS, 2021 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2022 GLM_LLC_MISS, 2023 }, 2024 [C(OP_PREFETCH)] = { 2025 [C(RESULT_ACCESS)] = 0x0, 2026 [C(RESULT_MISS)] = 0x0, 2027 }, 2028 }, 2029 }; 2030 2031 #define TNT_LOCAL_DRAM BIT_ULL(26) 2032 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2033 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2034 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2035 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2036 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2037 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2038 2039 static __initconst const u64 tnt_hw_cache_extra_regs 2040 [PERF_COUNT_HW_CACHE_MAX] 2041 [PERF_COUNT_HW_CACHE_OP_MAX] 2042 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2043 [C(LL)] = { 2044 [C(OP_READ)] = { 2045 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2046 TNT_LLC_ACCESS, 2047 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2048 TNT_LLC_MISS, 2049 }, 2050 [C(OP_WRITE)] = { 2051 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2052 TNT_LLC_ACCESS, 2053 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2054 TNT_LLC_MISS, 2055 }, 2056 [C(OP_PREFETCH)] = { 2057 [C(RESULT_ACCESS)] = 0x0, 2058 [C(RESULT_MISS)] = 0x0, 2059 }, 2060 }, 2061 }; 2062 2063 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2064 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2065 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2066 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2067 2068 static struct attribute *tnt_events_attrs[] = { 2069 EVENT_PTR(td_fe_bound_tnt), 2070 EVENT_PTR(td_retiring_tnt), 2071 EVENT_PTR(td_bad_spec_tnt), 2072 EVENT_PTR(td_be_bound_tnt), 2073 NULL, 2074 }; 2075 2076 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2077 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2078 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2079 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2080 EVENT_EXTRA_END 2081 }; 2082 2083 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2084 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2085 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2086 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2087 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2088 EVENT_EXTRA_END 2089 }; 2090 2091 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2092 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2093 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2094 #define KNL_MCDRAM_FAR BIT_ULL(22) 2095 #define KNL_DDR_LOCAL BIT_ULL(23) 2096 #define KNL_DDR_FAR BIT_ULL(24) 2097 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2098 KNL_DDR_LOCAL | KNL_DDR_FAR) 2099 #define KNL_L2_READ SLM_DMND_READ 2100 #define KNL_L2_WRITE SLM_DMND_WRITE 2101 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2102 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2103 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2104 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2105 SNB_NON_DRAM) 2106 2107 static __initconst const u64 knl_hw_cache_extra_regs 2108 [PERF_COUNT_HW_CACHE_MAX] 2109 [PERF_COUNT_HW_CACHE_OP_MAX] 2110 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2111 [C(LL)] = { 2112 [C(OP_READ)] = { 2113 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2114 [C(RESULT_MISS)] = 0, 2115 }, 2116 [C(OP_WRITE)] = { 2117 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2118 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2119 }, 2120 [C(OP_PREFETCH)] = { 2121 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2122 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2123 }, 2124 }, 2125 }; 2126 2127 /* 2128 * Used from PMIs where the LBRs are already disabled. 2129 * 2130 * This function could be called consecutively. It is required to remain in 2131 * disabled state if called consecutively. 2132 * 2133 * During consecutive calls, the same disable value will be written to related 2134 * registers, so the PMU state remains unchanged. 2135 * 2136 * intel_bts events don't coexist with intel PMU's BTS events because of 2137 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2138 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2139 * 2140 * Avoid PEBS_ENABLE MSR access in PMIs. 2141 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2142 * It doesn't matter if the PEBS is enabled or not. 2143 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2144 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2145 * However, there are some cases which may change PEBS status, e.g. PMI 2146 * throttle. The PEBS_ENABLE should be updated where the status changes. 2147 */ 2148 static __always_inline void __intel_pmu_disable_all(bool bts) 2149 { 2150 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2151 2152 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2153 2154 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2155 intel_pmu_disable_bts(); 2156 } 2157 2158 static __always_inline void intel_pmu_disable_all(void) 2159 { 2160 __intel_pmu_disable_all(true); 2161 intel_pmu_pebs_disable_all(); 2162 intel_pmu_lbr_disable_all(); 2163 } 2164 2165 static void __intel_pmu_enable_all(int added, bool pmi) 2166 { 2167 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2168 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2169 2170 intel_pmu_lbr_enable_all(pmi); 2171 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2172 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2173 2174 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2175 struct perf_event *event = 2176 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2177 2178 if (WARN_ON_ONCE(!event)) 2179 return; 2180 2181 intel_pmu_enable_bts(event->hw.config); 2182 } 2183 } 2184 2185 static void intel_pmu_enable_all(int added) 2186 { 2187 intel_pmu_pebs_enable_all(); 2188 __intel_pmu_enable_all(added, false); 2189 } 2190 2191 static noinline int 2192 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2193 unsigned int cnt, unsigned long flags) 2194 { 2195 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2196 2197 intel_pmu_lbr_read(); 2198 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2199 2200 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2201 intel_pmu_enable_all(0); 2202 local_irq_restore(flags); 2203 return cnt; 2204 } 2205 2206 static int 2207 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2208 { 2209 unsigned long flags; 2210 2211 /* must not have branches... */ 2212 local_irq_save(flags); 2213 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2214 __intel_pmu_lbr_disable(); 2215 /* ... until here */ 2216 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2217 } 2218 2219 static int 2220 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2221 { 2222 unsigned long flags; 2223 2224 /* must not have branches... */ 2225 local_irq_save(flags); 2226 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2227 __intel_pmu_arch_lbr_disable(); 2228 /* ... until here */ 2229 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2230 } 2231 2232 /* 2233 * Workaround for: 2234 * Intel Errata AAK100 (model 26) 2235 * Intel Errata AAP53 (model 30) 2236 * Intel Errata BD53 (model 44) 2237 * 2238 * The official story: 2239 * These chips need to be 'reset' when adding counters by programming the 2240 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2241 * in sequence on the same PMC or on different PMCs. 2242 * 2243 * In practice it appears some of these events do in fact count, and 2244 * we need to program all 4 events. 2245 */ 2246 static void intel_pmu_nhm_workaround(void) 2247 { 2248 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2249 static const unsigned long nhm_magic[4] = { 2250 0x4300B5, 2251 0x4300D2, 2252 0x4300B1, 2253 0x4300B1 2254 }; 2255 struct perf_event *event; 2256 int i; 2257 2258 /* 2259 * The Errata requires below steps: 2260 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2261 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2262 * the corresponding PMCx; 2263 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2264 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2265 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2266 */ 2267 2268 /* 2269 * The real steps we choose are a little different from above. 2270 * A) To reduce MSR operations, we don't run step 1) as they 2271 * are already cleared before this function is called; 2272 * B) Call x86_perf_event_update to save PMCx before configuring 2273 * PERFEVTSELx with magic number; 2274 * C) With step 5), we do clear only when the PERFEVTSELx is 2275 * not used currently. 2276 * D) Call x86_perf_event_set_period to restore PMCx; 2277 */ 2278 2279 /* We always operate 4 pairs of PERF Counters */ 2280 for (i = 0; i < 4; i++) { 2281 event = cpuc->events[i]; 2282 if (event) 2283 x86_perf_event_update(event); 2284 } 2285 2286 for (i = 0; i < 4; i++) { 2287 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2288 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2289 } 2290 2291 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2292 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2293 2294 for (i = 0; i < 4; i++) { 2295 event = cpuc->events[i]; 2296 2297 if (event) { 2298 x86_perf_event_set_period(event); 2299 __x86_pmu_enable_event(&event->hw, 2300 ARCH_PERFMON_EVENTSEL_ENABLE); 2301 } else 2302 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2303 } 2304 } 2305 2306 static void intel_pmu_nhm_enable_all(int added) 2307 { 2308 if (added) 2309 intel_pmu_nhm_workaround(); 2310 intel_pmu_enable_all(added); 2311 } 2312 2313 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2314 { 2315 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2316 2317 if (cpuc->tfa_shadow != val) { 2318 cpuc->tfa_shadow = val; 2319 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2320 } 2321 } 2322 2323 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2324 { 2325 /* 2326 * We're going to use PMC3, make sure TFA is set before we touch it. 2327 */ 2328 if (cntr == 3) 2329 intel_set_tfa(cpuc, true); 2330 } 2331 2332 static void intel_tfa_pmu_enable_all(int added) 2333 { 2334 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2335 2336 /* 2337 * If we find PMC3 is no longer used when we enable the PMU, we can 2338 * clear TFA. 2339 */ 2340 if (!test_bit(3, cpuc->active_mask)) 2341 intel_set_tfa(cpuc, false); 2342 2343 intel_pmu_enable_all(added); 2344 } 2345 2346 static inline u64 intel_pmu_get_status(void) 2347 { 2348 u64 status; 2349 2350 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2351 2352 return status; 2353 } 2354 2355 static inline void intel_pmu_ack_status(u64 ack) 2356 { 2357 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2358 } 2359 2360 static inline bool event_is_checkpointed(struct perf_event *event) 2361 { 2362 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2363 } 2364 2365 static inline void intel_set_masks(struct perf_event *event, int idx) 2366 { 2367 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2368 2369 if (event->attr.exclude_host) 2370 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2371 if (event->attr.exclude_guest) 2372 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2373 if (event_is_checkpointed(event)) 2374 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2375 } 2376 2377 static inline void intel_clear_masks(struct perf_event *event, int idx) 2378 { 2379 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2380 2381 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2382 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2383 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2384 } 2385 2386 static void intel_pmu_disable_fixed(struct perf_event *event) 2387 { 2388 struct hw_perf_event *hwc = &event->hw; 2389 u64 ctrl_val, mask; 2390 int idx = hwc->idx; 2391 2392 if (is_topdown_idx(idx)) { 2393 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2394 2395 /* 2396 * When there are other active TopDown events, 2397 * don't disable the fixed counter 3. 2398 */ 2399 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2400 return; 2401 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2402 } 2403 2404 intel_clear_masks(event, idx); 2405 2406 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2407 rdmsrl(hwc->config_base, ctrl_val); 2408 ctrl_val &= ~mask; 2409 wrmsrl(hwc->config_base, ctrl_val); 2410 } 2411 2412 static void intel_pmu_disable_event(struct perf_event *event) 2413 { 2414 struct hw_perf_event *hwc = &event->hw; 2415 int idx = hwc->idx; 2416 2417 switch (idx) { 2418 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2419 intel_clear_masks(event, idx); 2420 x86_pmu_disable_event(event); 2421 break; 2422 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2423 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2424 intel_pmu_disable_fixed(event); 2425 break; 2426 case INTEL_PMC_IDX_FIXED_BTS: 2427 intel_pmu_disable_bts(); 2428 intel_pmu_drain_bts_buffer(); 2429 return; 2430 case INTEL_PMC_IDX_FIXED_VLBR: 2431 intel_clear_masks(event, idx); 2432 break; 2433 default: 2434 intel_clear_masks(event, idx); 2435 pr_warn("Failed to disable the event with invalid index %d\n", 2436 idx); 2437 return; 2438 } 2439 2440 /* 2441 * Needs to be called after x86_pmu_disable_event, 2442 * so we don't trigger the event without PEBS bit set. 2443 */ 2444 if (unlikely(event->attr.precise_ip)) 2445 intel_pmu_pebs_disable(event); 2446 } 2447 2448 static void intel_pmu_assign_event(struct perf_event *event, int idx) 2449 { 2450 if (is_pebs_pt(event)) 2451 perf_report_aux_output_id(event, idx); 2452 } 2453 2454 static void intel_pmu_del_event(struct perf_event *event) 2455 { 2456 if (needs_branch_stack(event)) 2457 intel_pmu_lbr_del(event); 2458 if (event->attr.precise_ip) 2459 intel_pmu_pebs_del(event); 2460 } 2461 2462 static int icl_set_topdown_event_period(struct perf_event *event) 2463 { 2464 struct hw_perf_event *hwc = &event->hw; 2465 s64 left = local64_read(&hwc->period_left); 2466 2467 /* 2468 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2469 * Software should start both registers, PERF_METRICS and fixed 2470 * counter 3, from zero. 2471 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2472 * After that, both MSRs will be cleared for each read. 2473 * Don't need to clear them again. 2474 */ 2475 if (left == x86_pmu.max_period) { 2476 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2477 wrmsrl(MSR_PERF_METRICS, 0); 2478 hwc->saved_slots = 0; 2479 hwc->saved_metric = 0; 2480 } 2481 2482 if ((hwc->saved_slots) && is_slots_event(event)) { 2483 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2484 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2485 } 2486 2487 perf_event_update_userpage(event); 2488 2489 return 0; 2490 } 2491 2492 static int adl_set_topdown_event_period(struct perf_event *event) 2493 { 2494 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2495 2496 if (pmu->cpu_type != hybrid_big) 2497 return 0; 2498 2499 return icl_set_topdown_event_period(event); 2500 } 2501 2502 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2503 { 2504 u32 val; 2505 2506 /* 2507 * The metric is reported as an 8bit integer fraction 2508 * summing up to 0xff. 2509 * slots-in-metric = (Metric / 0xff) * slots 2510 */ 2511 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2512 return mul_u64_u32_div(slots, val, 0xff); 2513 } 2514 2515 static u64 icl_get_topdown_value(struct perf_event *event, 2516 u64 slots, u64 metrics) 2517 { 2518 int idx = event->hw.idx; 2519 u64 delta; 2520 2521 if (is_metric_idx(idx)) 2522 delta = icl_get_metrics_event_value(metrics, slots, idx); 2523 else 2524 delta = slots; 2525 2526 return delta; 2527 } 2528 2529 static void __icl_update_topdown_event(struct perf_event *event, 2530 u64 slots, u64 metrics, 2531 u64 last_slots, u64 last_metrics) 2532 { 2533 u64 delta, last = 0; 2534 2535 delta = icl_get_topdown_value(event, slots, metrics); 2536 if (last_slots) 2537 last = icl_get_topdown_value(event, last_slots, last_metrics); 2538 2539 /* 2540 * The 8bit integer fraction of metric may be not accurate, 2541 * especially when the changes is very small. 2542 * For example, if only a few bad_spec happens, the fraction 2543 * may be reduced from 1 to 0. If so, the bad_spec event value 2544 * will be 0 which is definitely less than the last value. 2545 * Avoid update event->count for this case. 2546 */ 2547 if (delta > last) { 2548 delta -= last; 2549 local64_add(delta, &event->count); 2550 } 2551 } 2552 2553 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2554 u64 metrics, int metric_end) 2555 { 2556 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2557 struct perf_event *other; 2558 int idx; 2559 2560 event->hw.saved_slots = slots; 2561 event->hw.saved_metric = metrics; 2562 2563 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2564 if (!is_topdown_idx(idx)) 2565 continue; 2566 other = cpuc->events[idx]; 2567 other->hw.saved_slots = slots; 2568 other->hw.saved_metric = metrics; 2569 } 2570 } 2571 2572 /* 2573 * Update all active Topdown events. 2574 * 2575 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2576 * modify by a NMI. PMU has to be disabled before calling this function. 2577 */ 2578 2579 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 2580 { 2581 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2582 struct perf_event *other; 2583 u64 slots, metrics; 2584 bool reset = true; 2585 int idx; 2586 2587 /* read Fixed counter 3 */ 2588 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2589 if (!slots) 2590 return 0; 2591 2592 /* read PERF_METRICS */ 2593 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2594 2595 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2596 if (!is_topdown_idx(idx)) 2597 continue; 2598 other = cpuc->events[idx]; 2599 __icl_update_topdown_event(other, slots, metrics, 2600 event ? event->hw.saved_slots : 0, 2601 event ? event->hw.saved_metric : 0); 2602 } 2603 2604 /* 2605 * Check and update this event, which may have been cleared 2606 * in active_mask e.g. x86_pmu_stop() 2607 */ 2608 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2609 __icl_update_topdown_event(event, slots, metrics, 2610 event->hw.saved_slots, 2611 event->hw.saved_metric); 2612 2613 /* 2614 * In x86_pmu_stop(), the event is cleared in active_mask first, 2615 * then drain the delta, which indicates context switch for 2616 * counting. 2617 * Save metric and slots for context switch. 2618 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2619 * Because the values will be restored in next schedule in. 2620 */ 2621 update_saved_topdown_regs(event, slots, metrics, metric_end); 2622 reset = false; 2623 } 2624 2625 if (reset) { 2626 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2627 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2628 wrmsrl(MSR_PERF_METRICS, 0); 2629 if (event) 2630 update_saved_topdown_regs(event, 0, 0, metric_end); 2631 } 2632 2633 return slots; 2634 } 2635 2636 static u64 icl_update_topdown_event(struct perf_event *event) 2637 { 2638 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2639 x86_pmu.num_topdown_events - 1); 2640 } 2641 2642 static u64 adl_update_topdown_event(struct perf_event *event) 2643 { 2644 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2645 2646 if (pmu->cpu_type != hybrid_big) 2647 return 0; 2648 2649 return icl_update_topdown_event(event); 2650 } 2651 2652 2653 static void intel_pmu_read_topdown_event(struct perf_event *event) 2654 { 2655 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2656 2657 /* Only need to call update_topdown_event() once for group read. */ 2658 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2659 !is_slots_event(event)) 2660 return; 2661 2662 perf_pmu_disable(event->pmu); 2663 x86_pmu.update_topdown_event(event); 2664 perf_pmu_enable(event->pmu); 2665 } 2666 2667 static void intel_pmu_read_event(struct perf_event *event) 2668 { 2669 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2670 intel_pmu_auto_reload_read(event); 2671 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 2672 intel_pmu_read_topdown_event(event); 2673 else 2674 x86_perf_event_update(event); 2675 } 2676 2677 static void intel_pmu_enable_fixed(struct perf_event *event) 2678 { 2679 struct hw_perf_event *hwc = &event->hw; 2680 u64 ctrl_val, mask, bits = 0; 2681 int idx = hwc->idx; 2682 2683 if (is_topdown_idx(idx)) { 2684 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2685 /* 2686 * When there are other active TopDown events, 2687 * don't enable the fixed counter 3 again. 2688 */ 2689 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2690 return; 2691 2692 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2693 } 2694 2695 intel_set_masks(event, idx); 2696 2697 /* 2698 * Enable IRQ generation (0x8), if not PEBS, 2699 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2700 * if requested: 2701 */ 2702 if (!event->attr.precise_ip) 2703 bits |= 0x8; 2704 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2705 bits |= 0x2; 2706 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2707 bits |= 0x1; 2708 2709 /* 2710 * ANY bit is supported in v3 and up 2711 */ 2712 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2713 bits |= 0x4; 2714 2715 idx -= INTEL_PMC_IDX_FIXED; 2716 bits <<= (idx * 4); 2717 mask = 0xfULL << (idx * 4); 2718 2719 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2720 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2721 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2722 } 2723 2724 rdmsrl(hwc->config_base, ctrl_val); 2725 ctrl_val &= ~mask; 2726 ctrl_val |= bits; 2727 wrmsrl(hwc->config_base, ctrl_val); 2728 } 2729 2730 static void intel_pmu_enable_event(struct perf_event *event) 2731 { 2732 struct hw_perf_event *hwc = &event->hw; 2733 int idx = hwc->idx; 2734 2735 if (unlikely(event->attr.precise_ip)) 2736 intel_pmu_pebs_enable(event); 2737 2738 switch (idx) { 2739 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2740 intel_set_masks(event, idx); 2741 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2742 break; 2743 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2744 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2745 intel_pmu_enable_fixed(event); 2746 break; 2747 case INTEL_PMC_IDX_FIXED_BTS: 2748 if (!__this_cpu_read(cpu_hw_events.enabled)) 2749 return; 2750 intel_pmu_enable_bts(hwc->config); 2751 break; 2752 case INTEL_PMC_IDX_FIXED_VLBR: 2753 intel_set_masks(event, idx); 2754 break; 2755 default: 2756 pr_warn("Failed to enable the event with invalid index %d\n", 2757 idx); 2758 } 2759 } 2760 2761 static void intel_pmu_add_event(struct perf_event *event) 2762 { 2763 if (event->attr.precise_ip) 2764 intel_pmu_pebs_add(event); 2765 if (needs_branch_stack(event)) 2766 intel_pmu_lbr_add(event); 2767 } 2768 2769 /* 2770 * Save and restart an expired event. Called by NMI contexts, 2771 * so it has to be careful about preempting normal event ops: 2772 */ 2773 int intel_pmu_save_and_restart(struct perf_event *event) 2774 { 2775 x86_perf_event_update(event); 2776 /* 2777 * For a checkpointed counter always reset back to 0. This 2778 * avoids a situation where the counter overflows, aborts the 2779 * transaction and is then set back to shortly before the 2780 * overflow, and overflows and aborts again. 2781 */ 2782 if (unlikely(event_is_checkpointed(event))) { 2783 /* No race with NMIs because the counter should not be armed */ 2784 wrmsrl(event->hw.event_base, 0); 2785 local64_set(&event->hw.prev_count, 0); 2786 } 2787 return x86_perf_event_set_period(event); 2788 } 2789 2790 static void intel_pmu_reset(void) 2791 { 2792 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2793 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2794 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2795 int num_counters = hybrid(cpuc->pmu, num_counters); 2796 unsigned long flags; 2797 int idx; 2798 2799 if (!num_counters) 2800 return; 2801 2802 local_irq_save(flags); 2803 2804 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2805 2806 for (idx = 0; idx < num_counters; idx++) { 2807 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2808 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2809 } 2810 for (idx = 0; idx < num_counters_fixed; idx++) { 2811 if (fixed_counter_disabled(idx, cpuc->pmu)) 2812 continue; 2813 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2814 } 2815 2816 if (ds) 2817 ds->bts_index = ds->bts_buffer_base; 2818 2819 /* Ack all overflows and disable fixed counters */ 2820 if (x86_pmu.version >= 2) { 2821 intel_pmu_ack_status(intel_pmu_get_status()); 2822 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2823 } 2824 2825 /* Reset LBRs and LBR freezing */ 2826 if (x86_pmu.lbr_nr) { 2827 update_debugctlmsr(get_debugctlmsr() & 2828 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2829 } 2830 2831 local_irq_restore(flags); 2832 } 2833 2834 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2835 { 2836 struct perf_sample_data data; 2837 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2838 int bit; 2839 int handled = 0; 2840 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2841 2842 inc_irq_stat(apic_perf_irqs); 2843 2844 /* 2845 * Ignore a range of extra bits in status that do not indicate 2846 * overflow by themselves. 2847 */ 2848 status &= ~(GLOBAL_STATUS_COND_CHG | 2849 GLOBAL_STATUS_ASIF | 2850 GLOBAL_STATUS_LBRS_FROZEN); 2851 if (!status) 2852 return 0; 2853 /* 2854 * In case multiple PEBS events are sampled at the same time, 2855 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2856 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2857 * having their bits set in the status register. This is a sign 2858 * that there was at least one PEBS record pending at the time 2859 * of the PMU interrupt. PEBS counters must only be processed 2860 * via the drain_pebs() calls and not via the regular sample 2861 * processing loop coming after that the function, otherwise 2862 * phony regular samples may be generated in the sampling buffer 2863 * not marked with the EXACT tag. Another possibility is to have 2864 * one PEBS event and at least one non-PEBS event which overflows 2865 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2866 * not be set, yet the overflow status bit for the PEBS counter will 2867 * be on Skylake. 2868 * 2869 * To avoid this problem, we systematically ignore the PEBS-enabled 2870 * counters from the GLOBAL_STATUS mask and we always process PEBS 2871 * events via drain_pebs(). 2872 */ 2873 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2874 status &= ~cpuc->pebs_enabled; 2875 else 2876 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2877 2878 /* 2879 * PEBS overflow sets bit 62 in the global status register 2880 */ 2881 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2882 u64 pebs_enabled = cpuc->pebs_enabled; 2883 2884 handled++; 2885 x86_pmu.drain_pebs(regs, &data); 2886 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2887 2888 /* 2889 * PMI throttle may be triggered, which stops the PEBS event. 2890 * Although cpuc->pebs_enabled is updated accordingly, the 2891 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2892 * cpuc->enabled has been forced to 0 in PMI. 2893 * Update the MSR if pebs_enabled is changed. 2894 */ 2895 if (pebs_enabled != cpuc->pebs_enabled) 2896 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2897 } 2898 2899 /* 2900 * Intel PT 2901 */ 2902 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2903 handled++; 2904 if (!perf_guest_handle_intel_pt_intr()) 2905 intel_pt_interrupt(); 2906 } 2907 2908 /* 2909 * Intel Perf metrics 2910 */ 2911 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 2912 handled++; 2913 if (x86_pmu.update_topdown_event) 2914 x86_pmu.update_topdown_event(NULL); 2915 } 2916 2917 /* 2918 * Checkpointed counters can lead to 'spurious' PMIs because the 2919 * rollback caused by the PMI will have cleared the overflow status 2920 * bit. Therefore always force probe these counters. 2921 */ 2922 status |= cpuc->intel_cp_status; 2923 2924 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2925 struct perf_event *event = cpuc->events[bit]; 2926 2927 handled++; 2928 2929 if (!test_bit(bit, cpuc->active_mask)) 2930 continue; 2931 2932 if (!intel_pmu_save_and_restart(event)) 2933 continue; 2934 2935 perf_sample_data_init(&data, 0, event->hw.last_period); 2936 2937 if (has_branch_stack(event)) 2938 data.br_stack = &cpuc->lbr_stack; 2939 2940 if (perf_event_overflow(event, &data, regs)) 2941 x86_pmu_stop(event, 0); 2942 } 2943 2944 return handled; 2945 } 2946 2947 /* 2948 * This handler is triggered by the local APIC, so the APIC IRQ handling 2949 * rules apply: 2950 */ 2951 static int intel_pmu_handle_irq(struct pt_regs *regs) 2952 { 2953 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2954 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 2955 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 2956 int loops; 2957 u64 status; 2958 int handled; 2959 int pmu_enabled; 2960 2961 /* 2962 * Save the PMU state. 2963 * It needs to be restored when leaving the handler. 2964 */ 2965 pmu_enabled = cpuc->enabled; 2966 /* 2967 * In general, the early ACK is only applied for old platforms. 2968 * For the big core starts from Haswell, the late ACK should be 2969 * applied. 2970 * For the small core after Tremont, we have to do the ACK right 2971 * before re-enabling counters, which is in the middle of the 2972 * NMI handler. 2973 */ 2974 if (!late_ack && !mid_ack) 2975 apic_write(APIC_LVTPC, APIC_DM_NMI); 2976 intel_bts_disable_local(); 2977 cpuc->enabled = 0; 2978 __intel_pmu_disable_all(true); 2979 handled = intel_pmu_drain_bts_buffer(); 2980 handled += intel_bts_interrupt(); 2981 status = intel_pmu_get_status(); 2982 if (!status) 2983 goto done; 2984 2985 loops = 0; 2986 again: 2987 intel_pmu_lbr_read(); 2988 intel_pmu_ack_status(status); 2989 if (++loops > 100) { 2990 static bool warned; 2991 2992 if (!warned) { 2993 WARN(1, "perfevents: irq loop stuck!\n"); 2994 perf_event_print_debug(); 2995 warned = true; 2996 } 2997 intel_pmu_reset(); 2998 goto done; 2999 } 3000 3001 handled += handle_pmi_common(regs, status); 3002 3003 /* 3004 * Repeat if there is more work to be done: 3005 */ 3006 status = intel_pmu_get_status(); 3007 if (status) 3008 goto again; 3009 3010 done: 3011 if (mid_ack) 3012 apic_write(APIC_LVTPC, APIC_DM_NMI); 3013 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3014 cpuc->enabled = pmu_enabled; 3015 if (pmu_enabled) 3016 __intel_pmu_enable_all(0, true); 3017 intel_bts_enable_local(); 3018 3019 /* 3020 * Only unmask the NMI after the overflow counters 3021 * have been reset. This avoids spurious NMIs on 3022 * Haswell CPUs. 3023 */ 3024 if (late_ack) 3025 apic_write(APIC_LVTPC, APIC_DM_NMI); 3026 return handled; 3027 } 3028 3029 static struct event_constraint * 3030 intel_bts_constraints(struct perf_event *event) 3031 { 3032 if (unlikely(intel_pmu_has_bts(event))) 3033 return &bts_constraint; 3034 3035 return NULL; 3036 } 3037 3038 /* 3039 * Note: matches a fake event, like Fixed2. 3040 */ 3041 static struct event_constraint * 3042 intel_vlbr_constraints(struct perf_event *event) 3043 { 3044 struct event_constraint *c = &vlbr_constraint; 3045 3046 if (unlikely(constraint_match(c, event->hw.config))) { 3047 event->hw.flags |= c->flags; 3048 return c; 3049 } 3050 3051 return NULL; 3052 } 3053 3054 static int intel_alt_er(struct cpu_hw_events *cpuc, 3055 int idx, u64 config) 3056 { 3057 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3058 int alt_idx = idx; 3059 3060 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3061 return idx; 3062 3063 if (idx == EXTRA_REG_RSP_0) 3064 alt_idx = EXTRA_REG_RSP_1; 3065 3066 if (idx == EXTRA_REG_RSP_1) 3067 alt_idx = EXTRA_REG_RSP_0; 3068 3069 if (config & ~extra_regs[alt_idx].valid_mask) 3070 return idx; 3071 3072 return alt_idx; 3073 } 3074 3075 static void intel_fixup_er(struct perf_event *event, int idx) 3076 { 3077 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3078 event->hw.extra_reg.idx = idx; 3079 3080 if (idx == EXTRA_REG_RSP_0) { 3081 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3082 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3083 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3084 } else if (idx == EXTRA_REG_RSP_1) { 3085 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3086 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3087 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3088 } 3089 } 3090 3091 /* 3092 * manage allocation of shared extra msr for certain events 3093 * 3094 * sharing can be: 3095 * per-cpu: to be shared between the various events on a single PMU 3096 * per-core: per-cpu + shared by HT threads 3097 */ 3098 static struct event_constraint * 3099 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3100 struct perf_event *event, 3101 struct hw_perf_event_extra *reg) 3102 { 3103 struct event_constraint *c = &emptyconstraint; 3104 struct er_account *era; 3105 unsigned long flags; 3106 int idx = reg->idx; 3107 3108 /* 3109 * reg->alloc can be set due to existing state, so for fake cpuc we 3110 * need to ignore this, otherwise we might fail to allocate proper fake 3111 * state for this extra reg constraint. Also see the comment below. 3112 */ 3113 if (reg->alloc && !cpuc->is_fake) 3114 return NULL; /* call x86_get_event_constraint() */ 3115 3116 again: 3117 era = &cpuc->shared_regs->regs[idx]; 3118 /* 3119 * we use spin_lock_irqsave() to avoid lockdep issues when 3120 * passing a fake cpuc 3121 */ 3122 raw_spin_lock_irqsave(&era->lock, flags); 3123 3124 if (!atomic_read(&era->ref) || era->config == reg->config) { 3125 3126 /* 3127 * If its a fake cpuc -- as per validate_{group,event}() we 3128 * shouldn't touch event state and we can avoid doing so 3129 * since both will only call get_event_constraints() once 3130 * on each event, this avoids the need for reg->alloc. 3131 * 3132 * Not doing the ER fixup will only result in era->reg being 3133 * wrong, but since we won't actually try and program hardware 3134 * this isn't a problem either. 3135 */ 3136 if (!cpuc->is_fake) { 3137 if (idx != reg->idx) 3138 intel_fixup_er(event, idx); 3139 3140 /* 3141 * x86_schedule_events() can call get_event_constraints() 3142 * multiple times on events in the case of incremental 3143 * scheduling(). reg->alloc ensures we only do the ER 3144 * allocation once. 3145 */ 3146 reg->alloc = 1; 3147 } 3148 3149 /* lock in msr value */ 3150 era->config = reg->config; 3151 era->reg = reg->reg; 3152 3153 /* one more user */ 3154 atomic_inc(&era->ref); 3155 3156 /* 3157 * need to call x86_get_event_constraint() 3158 * to check if associated event has constraints 3159 */ 3160 c = NULL; 3161 } else { 3162 idx = intel_alt_er(cpuc, idx, reg->config); 3163 if (idx != reg->idx) { 3164 raw_spin_unlock_irqrestore(&era->lock, flags); 3165 goto again; 3166 } 3167 } 3168 raw_spin_unlock_irqrestore(&era->lock, flags); 3169 3170 return c; 3171 } 3172 3173 static void 3174 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3175 struct hw_perf_event_extra *reg) 3176 { 3177 struct er_account *era; 3178 3179 /* 3180 * Only put constraint if extra reg was actually allocated. Also takes 3181 * care of event which do not use an extra shared reg. 3182 * 3183 * Also, if this is a fake cpuc we shouldn't touch any event state 3184 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3185 * either since it'll be thrown out. 3186 */ 3187 if (!reg->alloc || cpuc->is_fake) 3188 return; 3189 3190 era = &cpuc->shared_regs->regs[reg->idx]; 3191 3192 /* one fewer user */ 3193 atomic_dec(&era->ref); 3194 3195 /* allocate again next time */ 3196 reg->alloc = 0; 3197 } 3198 3199 static struct event_constraint * 3200 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3201 struct perf_event *event) 3202 { 3203 struct event_constraint *c = NULL, *d; 3204 struct hw_perf_event_extra *xreg, *breg; 3205 3206 xreg = &event->hw.extra_reg; 3207 if (xreg->idx != EXTRA_REG_NONE) { 3208 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3209 if (c == &emptyconstraint) 3210 return c; 3211 } 3212 breg = &event->hw.branch_reg; 3213 if (breg->idx != EXTRA_REG_NONE) { 3214 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3215 if (d == &emptyconstraint) { 3216 __intel_shared_reg_put_constraints(cpuc, xreg); 3217 c = d; 3218 } 3219 } 3220 return c; 3221 } 3222 3223 struct event_constraint * 3224 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3225 struct perf_event *event) 3226 { 3227 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3228 struct event_constraint *c; 3229 3230 if (event_constraints) { 3231 for_each_event_constraint(c, event_constraints) { 3232 if (constraint_match(c, event->hw.config)) { 3233 event->hw.flags |= c->flags; 3234 return c; 3235 } 3236 } 3237 } 3238 3239 return &hybrid_var(cpuc->pmu, unconstrained); 3240 } 3241 3242 static struct event_constraint * 3243 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3244 struct perf_event *event) 3245 { 3246 struct event_constraint *c; 3247 3248 c = intel_vlbr_constraints(event); 3249 if (c) 3250 return c; 3251 3252 c = intel_bts_constraints(event); 3253 if (c) 3254 return c; 3255 3256 c = intel_shared_regs_constraints(cpuc, event); 3257 if (c) 3258 return c; 3259 3260 c = intel_pebs_constraints(event); 3261 if (c) 3262 return c; 3263 3264 return x86_get_event_constraints(cpuc, idx, event); 3265 } 3266 3267 static void 3268 intel_start_scheduling(struct cpu_hw_events *cpuc) 3269 { 3270 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3271 struct intel_excl_states *xl; 3272 int tid = cpuc->excl_thread_id; 3273 3274 /* 3275 * nothing needed if in group validation mode 3276 */ 3277 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3278 return; 3279 3280 /* 3281 * no exclusion needed 3282 */ 3283 if (WARN_ON_ONCE(!excl_cntrs)) 3284 return; 3285 3286 xl = &excl_cntrs->states[tid]; 3287 3288 xl->sched_started = true; 3289 /* 3290 * lock shared state until we are done scheduling 3291 * in stop_event_scheduling() 3292 * makes scheduling appear as a transaction 3293 */ 3294 raw_spin_lock(&excl_cntrs->lock); 3295 } 3296 3297 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3298 { 3299 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3300 struct event_constraint *c = cpuc->event_constraint[idx]; 3301 struct intel_excl_states *xl; 3302 int tid = cpuc->excl_thread_id; 3303 3304 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3305 return; 3306 3307 if (WARN_ON_ONCE(!excl_cntrs)) 3308 return; 3309 3310 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3311 return; 3312 3313 xl = &excl_cntrs->states[tid]; 3314 3315 lockdep_assert_held(&excl_cntrs->lock); 3316 3317 if (c->flags & PERF_X86_EVENT_EXCL) 3318 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3319 else 3320 xl->state[cntr] = INTEL_EXCL_SHARED; 3321 } 3322 3323 static void 3324 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3325 { 3326 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3327 struct intel_excl_states *xl; 3328 int tid = cpuc->excl_thread_id; 3329 3330 /* 3331 * nothing needed if in group validation mode 3332 */ 3333 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3334 return; 3335 /* 3336 * no exclusion needed 3337 */ 3338 if (WARN_ON_ONCE(!excl_cntrs)) 3339 return; 3340 3341 xl = &excl_cntrs->states[tid]; 3342 3343 xl->sched_started = false; 3344 /* 3345 * release shared state lock (acquired in intel_start_scheduling()) 3346 */ 3347 raw_spin_unlock(&excl_cntrs->lock); 3348 } 3349 3350 static struct event_constraint * 3351 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3352 { 3353 WARN_ON_ONCE(!cpuc->constraint_list); 3354 3355 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3356 struct event_constraint *cx; 3357 3358 /* 3359 * grab pre-allocated constraint entry 3360 */ 3361 cx = &cpuc->constraint_list[idx]; 3362 3363 /* 3364 * initialize dynamic constraint 3365 * with static constraint 3366 */ 3367 *cx = *c; 3368 3369 /* 3370 * mark constraint as dynamic 3371 */ 3372 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3373 c = cx; 3374 } 3375 3376 return c; 3377 } 3378 3379 static struct event_constraint * 3380 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3381 int idx, struct event_constraint *c) 3382 { 3383 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3384 struct intel_excl_states *xlo; 3385 int tid = cpuc->excl_thread_id; 3386 int is_excl, i, w; 3387 3388 /* 3389 * validating a group does not require 3390 * enforcing cross-thread exclusion 3391 */ 3392 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3393 return c; 3394 3395 /* 3396 * no exclusion needed 3397 */ 3398 if (WARN_ON_ONCE(!excl_cntrs)) 3399 return c; 3400 3401 /* 3402 * because we modify the constraint, we need 3403 * to make a copy. Static constraints come 3404 * from static const tables. 3405 * 3406 * only needed when constraint has not yet 3407 * been cloned (marked dynamic) 3408 */ 3409 c = dyn_constraint(cpuc, c, idx); 3410 3411 /* 3412 * From here on, the constraint is dynamic. 3413 * Either it was just allocated above, or it 3414 * was allocated during a earlier invocation 3415 * of this function 3416 */ 3417 3418 /* 3419 * state of sibling HT 3420 */ 3421 xlo = &excl_cntrs->states[tid ^ 1]; 3422 3423 /* 3424 * event requires exclusive counter access 3425 * across HT threads 3426 */ 3427 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3428 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3429 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3430 if (!cpuc->n_excl++) 3431 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3432 } 3433 3434 /* 3435 * Modify static constraint with current dynamic 3436 * state of thread 3437 * 3438 * EXCLUSIVE: sibling counter measuring exclusive event 3439 * SHARED : sibling counter measuring non-exclusive event 3440 * UNUSED : sibling counter unused 3441 */ 3442 w = c->weight; 3443 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3444 /* 3445 * exclusive event in sibling counter 3446 * our corresponding counter cannot be used 3447 * regardless of our event 3448 */ 3449 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3450 __clear_bit(i, c->idxmsk); 3451 w--; 3452 continue; 3453 } 3454 /* 3455 * if measuring an exclusive event, sibling 3456 * measuring non-exclusive, then counter cannot 3457 * be used 3458 */ 3459 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3460 __clear_bit(i, c->idxmsk); 3461 w--; 3462 continue; 3463 } 3464 } 3465 3466 /* 3467 * if we return an empty mask, then switch 3468 * back to static empty constraint to avoid 3469 * the cost of freeing later on 3470 */ 3471 if (!w) 3472 c = &emptyconstraint; 3473 3474 c->weight = w; 3475 3476 return c; 3477 } 3478 3479 static struct event_constraint * 3480 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3481 struct perf_event *event) 3482 { 3483 struct event_constraint *c1, *c2; 3484 3485 c1 = cpuc->event_constraint[idx]; 3486 3487 /* 3488 * first time only 3489 * - static constraint: no change across incremental scheduling calls 3490 * - dynamic constraint: handled by intel_get_excl_constraints() 3491 */ 3492 c2 = __intel_get_event_constraints(cpuc, idx, event); 3493 if (c1) { 3494 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3495 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3496 c1->weight = c2->weight; 3497 c2 = c1; 3498 } 3499 3500 if (cpuc->excl_cntrs) 3501 return intel_get_excl_constraints(cpuc, event, idx, c2); 3502 3503 return c2; 3504 } 3505 3506 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3507 struct perf_event *event) 3508 { 3509 struct hw_perf_event *hwc = &event->hw; 3510 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3511 int tid = cpuc->excl_thread_id; 3512 struct intel_excl_states *xl; 3513 3514 /* 3515 * nothing needed if in group validation mode 3516 */ 3517 if (cpuc->is_fake) 3518 return; 3519 3520 if (WARN_ON_ONCE(!excl_cntrs)) 3521 return; 3522 3523 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3524 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3525 if (!--cpuc->n_excl) 3526 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3527 } 3528 3529 /* 3530 * If event was actually assigned, then mark the counter state as 3531 * unused now. 3532 */ 3533 if (hwc->idx >= 0) { 3534 xl = &excl_cntrs->states[tid]; 3535 3536 /* 3537 * put_constraint may be called from x86_schedule_events() 3538 * which already has the lock held so here make locking 3539 * conditional. 3540 */ 3541 if (!xl->sched_started) 3542 raw_spin_lock(&excl_cntrs->lock); 3543 3544 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3545 3546 if (!xl->sched_started) 3547 raw_spin_unlock(&excl_cntrs->lock); 3548 } 3549 } 3550 3551 static void 3552 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3553 struct perf_event *event) 3554 { 3555 struct hw_perf_event_extra *reg; 3556 3557 reg = &event->hw.extra_reg; 3558 if (reg->idx != EXTRA_REG_NONE) 3559 __intel_shared_reg_put_constraints(cpuc, reg); 3560 3561 reg = &event->hw.branch_reg; 3562 if (reg->idx != EXTRA_REG_NONE) 3563 __intel_shared_reg_put_constraints(cpuc, reg); 3564 } 3565 3566 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3567 struct perf_event *event) 3568 { 3569 intel_put_shared_regs_event_constraints(cpuc, event); 3570 3571 /* 3572 * is PMU has exclusive counter restrictions, then 3573 * all events are subject to and must call the 3574 * put_excl_constraints() routine 3575 */ 3576 if (cpuc->excl_cntrs) 3577 intel_put_excl_constraints(cpuc, event); 3578 } 3579 3580 static void intel_pebs_aliases_core2(struct perf_event *event) 3581 { 3582 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3583 /* 3584 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3585 * (0x003c) so that we can use it with PEBS. 3586 * 3587 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3588 * PEBS capable. However we can use INST_RETIRED.ANY_P 3589 * (0x00c0), which is a PEBS capable event, to get the same 3590 * count. 3591 * 3592 * INST_RETIRED.ANY_P counts the number of cycles that retires 3593 * CNTMASK instructions. By setting CNTMASK to a value (16) 3594 * larger than the maximum number of instructions that can be 3595 * retired per cycle (4) and then inverting the condition, we 3596 * count all cycles that retire 16 or less instructions, which 3597 * is every cycle. 3598 * 3599 * Thereby we gain a PEBS capable cycle counter. 3600 */ 3601 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3602 3603 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3604 event->hw.config = alt_config; 3605 } 3606 } 3607 3608 static void intel_pebs_aliases_snb(struct perf_event *event) 3609 { 3610 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3611 /* 3612 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3613 * (0x003c) so that we can use it with PEBS. 3614 * 3615 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3616 * PEBS capable. However we can use UOPS_RETIRED.ALL 3617 * (0x01c2), which is a PEBS capable event, to get the same 3618 * count. 3619 * 3620 * UOPS_RETIRED.ALL counts the number of cycles that retires 3621 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3622 * larger than the maximum number of micro-ops that can be 3623 * retired per cycle (4) and then inverting the condition, we 3624 * count all cycles that retire 16 or less micro-ops, which 3625 * is every cycle. 3626 * 3627 * Thereby we gain a PEBS capable cycle counter. 3628 */ 3629 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3630 3631 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3632 event->hw.config = alt_config; 3633 } 3634 } 3635 3636 static void intel_pebs_aliases_precdist(struct perf_event *event) 3637 { 3638 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3639 /* 3640 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3641 * (0x003c) so that we can use it with PEBS. 3642 * 3643 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3644 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3645 * (0x01c0), which is a PEBS capable event, to get the same 3646 * count. 3647 * 3648 * The PREC_DIST event has special support to minimize sample 3649 * shadowing effects. One drawback is that it can be 3650 * only programmed on counter 1, but that seems like an 3651 * acceptable trade off. 3652 */ 3653 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3654 3655 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3656 event->hw.config = alt_config; 3657 } 3658 } 3659 3660 static void intel_pebs_aliases_ivb(struct perf_event *event) 3661 { 3662 if (event->attr.precise_ip < 3) 3663 return intel_pebs_aliases_snb(event); 3664 return intel_pebs_aliases_precdist(event); 3665 } 3666 3667 static void intel_pebs_aliases_skl(struct perf_event *event) 3668 { 3669 if (event->attr.precise_ip < 3) 3670 return intel_pebs_aliases_core2(event); 3671 return intel_pebs_aliases_precdist(event); 3672 } 3673 3674 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3675 { 3676 unsigned long flags = x86_pmu.large_pebs_flags; 3677 3678 if (event->attr.use_clockid) 3679 flags &= ~PERF_SAMPLE_TIME; 3680 if (!event->attr.exclude_kernel) 3681 flags &= ~PERF_SAMPLE_REGS_USER; 3682 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3683 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3684 return flags; 3685 } 3686 3687 static int intel_pmu_bts_config(struct perf_event *event) 3688 { 3689 struct perf_event_attr *attr = &event->attr; 3690 3691 if (unlikely(intel_pmu_has_bts(event))) { 3692 /* BTS is not supported by this architecture. */ 3693 if (!x86_pmu.bts_active) 3694 return -EOPNOTSUPP; 3695 3696 /* BTS is currently only allowed for user-mode. */ 3697 if (!attr->exclude_kernel) 3698 return -EOPNOTSUPP; 3699 3700 /* BTS is not allowed for precise events. */ 3701 if (attr->precise_ip) 3702 return -EOPNOTSUPP; 3703 3704 /* disallow bts if conflicting events are present */ 3705 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3706 return -EBUSY; 3707 3708 event->destroy = hw_perf_lbr_event_destroy; 3709 } 3710 3711 return 0; 3712 } 3713 3714 static int core_pmu_hw_config(struct perf_event *event) 3715 { 3716 int ret = x86_pmu_hw_config(event); 3717 3718 if (ret) 3719 return ret; 3720 3721 return intel_pmu_bts_config(event); 3722 } 3723 3724 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 3725 ((x86_pmu.num_topdown_events - 1) << 8)) 3726 3727 static bool is_available_metric_event(struct perf_event *event) 3728 { 3729 return is_metric_event(event) && 3730 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 3731 } 3732 3733 static inline bool is_mem_loads_event(struct perf_event *event) 3734 { 3735 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3736 } 3737 3738 static inline bool is_mem_loads_aux_event(struct perf_event *event) 3739 { 3740 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3741 } 3742 3743 static inline bool require_mem_loads_aux_event(struct perf_event *event) 3744 { 3745 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3746 return false; 3747 3748 if (is_hybrid()) 3749 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3750 3751 return true; 3752 } 3753 3754 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3755 { 3756 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3757 3758 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3759 } 3760 3761 static int intel_pmu_hw_config(struct perf_event *event) 3762 { 3763 int ret = x86_pmu_hw_config(event); 3764 3765 if (ret) 3766 return ret; 3767 3768 ret = intel_pmu_bts_config(event); 3769 if (ret) 3770 return ret; 3771 3772 if (event->attr.precise_ip) { 3773 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 3774 return -EINVAL; 3775 3776 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3777 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3778 if (!(event->attr.sample_type & 3779 ~intel_pmu_large_pebs_flags(event))) { 3780 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3781 event->attach_state |= PERF_ATTACH_SCHED_CB; 3782 } 3783 } 3784 if (x86_pmu.pebs_aliases) 3785 x86_pmu.pebs_aliases(event); 3786 3787 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3788 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3789 } 3790 3791 if (needs_branch_stack(event)) { 3792 ret = intel_pmu_setup_lbr_filter(event); 3793 if (ret) 3794 return ret; 3795 event->attach_state |= PERF_ATTACH_SCHED_CB; 3796 3797 /* 3798 * BTS is set up earlier in this path, so don't account twice 3799 */ 3800 if (!unlikely(intel_pmu_has_bts(event))) { 3801 /* disallow lbr if conflicting events are present */ 3802 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3803 return -EBUSY; 3804 3805 event->destroy = hw_perf_lbr_event_destroy; 3806 } 3807 } 3808 3809 if (event->attr.aux_output) { 3810 if (!event->attr.precise_ip) 3811 return -EINVAL; 3812 3813 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3814 } 3815 3816 if ((event->attr.type == PERF_TYPE_HARDWARE) || 3817 (event->attr.type == PERF_TYPE_HW_CACHE)) 3818 return 0; 3819 3820 /* 3821 * Config Topdown slots and metric events 3822 * 3823 * The slots event on Fixed Counter 3 can support sampling, 3824 * which will be handled normally in x86_perf_event_update(). 3825 * 3826 * Metric events don't support sampling and require being paired 3827 * with a slots event as group leader. When the slots event 3828 * is used in a metrics group, it too cannot support sampling. 3829 */ 3830 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 3831 if (event->attr.config1 || event->attr.config2) 3832 return -EINVAL; 3833 3834 /* 3835 * The TopDown metrics events and slots event don't 3836 * support any filters. 3837 */ 3838 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3839 return -EINVAL; 3840 3841 if (is_available_metric_event(event)) { 3842 struct perf_event *leader = event->group_leader; 3843 3844 /* The metric events don't support sampling. */ 3845 if (is_sampling_event(event)) 3846 return -EINVAL; 3847 3848 /* The metric events require a slots group leader. */ 3849 if (!is_slots_event(leader)) 3850 return -EINVAL; 3851 3852 /* 3853 * The leader/SLOTS must not be a sampling event for 3854 * metric use; hardware requires it starts at 0 when used 3855 * in conjunction with MSR_PERF_METRICS. 3856 */ 3857 if (is_sampling_event(leader)) 3858 return -EINVAL; 3859 3860 event->event_caps |= PERF_EV_CAP_SIBLING; 3861 /* 3862 * Only once we have a METRICs sibling do we 3863 * need TopDown magic. 3864 */ 3865 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3866 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3867 } 3868 } 3869 3870 /* 3871 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3872 * doesn't function quite right. As a work-around it needs to always be 3873 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3874 * The actual count of this second event is irrelevant it just needs 3875 * to be active to make the first event function correctly. 3876 * 3877 * In a group, the auxiliary event must be in front of the load latency 3878 * event. The rule is to simplify the implementation of the check. 3879 * That's because perf cannot have a complete group at the moment. 3880 */ 3881 if (require_mem_loads_aux_event(event) && 3882 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3883 is_mem_loads_event(event)) { 3884 struct perf_event *leader = event->group_leader; 3885 struct perf_event *sibling = NULL; 3886 3887 if (!is_mem_loads_aux_event(leader)) { 3888 for_each_sibling_event(sibling, leader) { 3889 if (is_mem_loads_aux_event(sibling)) 3890 break; 3891 } 3892 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3893 return -ENODATA; 3894 } 3895 } 3896 3897 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3898 return 0; 3899 3900 if (x86_pmu.version < 3) 3901 return -EINVAL; 3902 3903 ret = perf_allow_cpu(&event->attr); 3904 if (ret) 3905 return ret; 3906 3907 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3908 3909 return 0; 3910 } 3911 3912 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3913 { 3914 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3915 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3916 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3917 3918 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3919 arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3920 arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3921 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 3922 arr[0].guest &= ~cpuc->pebs_enabled; 3923 else 3924 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 3925 *nr = 1; 3926 3927 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3928 /* 3929 * If PMU counter has PEBS enabled it is not enough to 3930 * disable counter on a guest entry since PEBS memory 3931 * write can overshoot guest entry and corrupt guest 3932 * memory. Disabling PEBS solves the problem. 3933 * 3934 * Don't do this if the CPU already enforces it. 3935 */ 3936 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3937 arr[1].host = cpuc->pebs_enabled; 3938 arr[1].guest = 0; 3939 *nr = 2; 3940 } 3941 3942 return arr; 3943 } 3944 3945 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3946 { 3947 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3948 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3949 int idx; 3950 3951 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3952 struct perf_event *event = cpuc->events[idx]; 3953 3954 arr[idx].msr = x86_pmu_config_addr(idx); 3955 arr[idx].host = arr[idx].guest = 0; 3956 3957 if (!test_bit(idx, cpuc->active_mask)) 3958 continue; 3959 3960 arr[idx].host = arr[idx].guest = 3961 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3962 3963 if (event->attr.exclude_host) 3964 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3965 else if (event->attr.exclude_guest) 3966 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3967 } 3968 3969 *nr = x86_pmu.num_counters; 3970 return arr; 3971 } 3972 3973 static void core_pmu_enable_event(struct perf_event *event) 3974 { 3975 if (!event->attr.exclude_host) 3976 x86_pmu_enable_event(event); 3977 } 3978 3979 static void core_pmu_enable_all(int added) 3980 { 3981 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3982 int idx; 3983 3984 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3985 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3986 3987 if (!test_bit(idx, cpuc->active_mask) || 3988 cpuc->events[idx]->attr.exclude_host) 3989 continue; 3990 3991 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3992 } 3993 } 3994 3995 static int hsw_hw_config(struct perf_event *event) 3996 { 3997 int ret = intel_pmu_hw_config(event); 3998 3999 if (ret) 4000 return ret; 4001 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4002 return 0; 4003 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4004 4005 /* 4006 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4007 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4008 * this combination. 4009 */ 4010 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4011 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4012 event->attr.precise_ip > 0)) 4013 return -EOPNOTSUPP; 4014 4015 if (event_is_checkpointed(event)) { 4016 /* 4017 * Sampling of checkpointed events can cause situations where 4018 * the CPU constantly aborts because of a overflow, which is 4019 * then checkpointed back and ignored. Forbid checkpointing 4020 * for sampling. 4021 * 4022 * But still allow a long sampling period, so that perf stat 4023 * from KVM works. 4024 */ 4025 if (event->attr.sample_period > 0 && 4026 event->attr.sample_period < 0x7fffffff) 4027 return -EOPNOTSUPP; 4028 } 4029 return 0; 4030 } 4031 4032 static struct event_constraint counter0_constraint = 4033 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4034 4035 static struct event_constraint counter2_constraint = 4036 EVENT_CONSTRAINT(0, 0x4, 0); 4037 4038 static struct event_constraint fixed0_constraint = 4039 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4040 4041 static struct event_constraint fixed0_counter0_constraint = 4042 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4043 4044 static struct event_constraint * 4045 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4046 struct perf_event *event) 4047 { 4048 struct event_constraint *c; 4049 4050 c = intel_get_event_constraints(cpuc, idx, event); 4051 4052 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4053 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4054 if (c->idxmsk64 & (1U << 2)) 4055 return &counter2_constraint; 4056 return &emptyconstraint; 4057 } 4058 4059 return c; 4060 } 4061 4062 static struct event_constraint * 4063 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4064 struct perf_event *event) 4065 { 4066 /* 4067 * Fixed counter 0 has less skid. 4068 * Force instruction:ppp in Fixed counter 0 4069 */ 4070 if ((event->attr.precise_ip == 3) && 4071 constraint_match(&fixed0_constraint, event->hw.config)) 4072 return &fixed0_constraint; 4073 4074 return hsw_get_event_constraints(cpuc, idx, event); 4075 } 4076 4077 static struct event_constraint * 4078 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4079 struct perf_event *event) 4080 { 4081 struct event_constraint *c; 4082 4083 c = icl_get_event_constraints(cpuc, idx, event); 4084 4085 /* 4086 * The :ppp indicates the Precise Distribution (PDist) facility, which 4087 * is only supported on the GP counter 0. If a :ppp event which is not 4088 * available on the GP counter 0, error out. 4089 * Exception: Instruction PDIR is only available on the fixed counter 0. 4090 */ 4091 if ((event->attr.precise_ip == 3) && 4092 !constraint_match(&fixed0_constraint, event->hw.config)) { 4093 if (c->idxmsk64 & BIT_ULL(0)) 4094 return &counter0_constraint; 4095 4096 return &emptyconstraint; 4097 } 4098 4099 return c; 4100 } 4101 4102 static struct event_constraint * 4103 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4104 struct perf_event *event) 4105 { 4106 struct event_constraint *c; 4107 4108 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4109 if (event->attr.precise_ip == 3) 4110 return &counter0_constraint; 4111 4112 c = intel_get_event_constraints(cpuc, idx, event); 4113 4114 return c; 4115 } 4116 4117 static struct event_constraint * 4118 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4119 struct perf_event *event) 4120 { 4121 struct event_constraint *c; 4122 4123 /* 4124 * :ppp means to do reduced skid PEBS, 4125 * which is available on PMC0 and fixed counter 0. 4126 */ 4127 if (event->attr.precise_ip == 3) { 4128 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 4129 if (constraint_match(&fixed0_constraint, event->hw.config)) 4130 return &fixed0_counter0_constraint; 4131 4132 return &counter0_constraint; 4133 } 4134 4135 c = intel_get_event_constraints(cpuc, idx, event); 4136 4137 return c; 4138 } 4139 4140 static bool allow_tsx_force_abort = true; 4141 4142 static struct event_constraint * 4143 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4144 struct perf_event *event) 4145 { 4146 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4147 4148 /* 4149 * Without TFA we must not use PMC3. 4150 */ 4151 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4152 c = dyn_constraint(cpuc, c, idx); 4153 c->idxmsk64 &= ~(1ULL << 3); 4154 c->weight--; 4155 } 4156 4157 return c; 4158 } 4159 4160 static struct event_constraint * 4161 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4162 struct perf_event *event) 4163 { 4164 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4165 4166 if (pmu->cpu_type == hybrid_big) 4167 return spr_get_event_constraints(cpuc, idx, event); 4168 else if (pmu->cpu_type == hybrid_small) 4169 return tnt_get_event_constraints(cpuc, idx, event); 4170 4171 WARN_ON(1); 4172 return &emptyconstraint; 4173 } 4174 4175 static int adl_hw_config(struct perf_event *event) 4176 { 4177 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4178 4179 if (pmu->cpu_type == hybrid_big) 4180 return hsw_hw_config(event); 4181 else if (pmu->cpu_type == hybrid_small) 4182 return intel_pmu_hw_config(event); 4183 4184 WARN_ON(1); 4185 return -EOPNOTSUPP; 4186 } 4187 4188 static u8 adl_get_hybrid_cpu_type(void) 4189 { 4190 return hybrid_big; 4191 } 4192 4193 /* 4194 * Broadwell: 4195 * 4196 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4197 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4198 * the two to enforce a minimum period of 128 (the smallest value that has bits 4199 * 0-5 cleared and >= 100). 4200 * 4201 * Because of how the code in x86_perf_event_set_period() works, the truncation 4202 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4203 * to make up for the 'lost' events due to carrying the 'error' in period_left. 4204 * 4205 * Therefore the effective (average) period matches the requested period, 4206 * despite coarser hardware granularity. 4207 */ 4208 static u64 bdw_limit_period(struct perf_event *event, u64 left) 4209 { 4210 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4211 X86_CONFIG(.event=0xc0, .umask=0x01)) { 4212 if (left < 128) 4213 left = 128; 4214 left &= ~0x3fULL; 4215 } 4216 return left; 4217 } 4218 4219 static u64 nhm_limit_period(struct perf_event *event, u64 left) 4220 { 4221 return max(left, 32ULL); 4222 } 4223 4224 static u64 spr_limit_period(struct perf_event *event, u64 left) 4225 { 4226 if (event->attr.precise_ip == 3) 4227 return max(left, 128ULL); 4228 4229 return left; 4230 } 4231 4232 PMU_FORMAT_ATTR(event, "config:0-7" ); 4233 PMU_FORMAT_ATTR(umask, "config:8-15" ); 4234 PMU_FORMAT_ATTR(edge, "config:18" ); 4235 PMU_FORMAT_ATTR(pc, "config:19" ); 4236 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4237 PMU_FORMAT_ATTR(inv, "config:23" ); 4238 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4239 PMU_FORMAT_ATTR(in_tx, "config:32"); 4240 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4241 4242 static struct attribute *intel_arch_formats_attr[] = { 4243 &format_attr_event.attr, 4244 &format_attr_umask.attr, 4245 &format_attr_edge.attr, 4246 &format_attr_pc.attr, 4247 &format_attr_inv.attr, 4248 &format_attr_cmask.attr, 4249 NULL, 4250 }; 4251 4252 ssize_t intel_event_sysfs_show(char *page, u64 config) 4253 { 4254 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4255 4256 return x86_event_sysfs_show(page, config, event); 4257 } 4258 4259 static struct intel_shared_regs *allocate_shared_regs(int cpu) 4260 { 4261 struct intel_shared_regs *regs; 4262 int i; 4263 4264 regs = kzalloc_node(sizeof(struct intel_shared_regs), 4265 GFP_KERNEL, cpu_to_node(cpu)); 4266 if (regs) { 4267 /* 4268 * initialize the locks to keep lockdep happy 4269 */ 4270 for (i = 0; i < EXTRA_REG_MAX; i++) 4271 raw_spin_lock_init(®s->regs[i].lock); 4272 4273 regs->core_id = -1; 4274 } 4275 return regs; 4276 } 4277 4278 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4279 { 4280 struct intel_excl_cntrs *c; 4281 4282 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4283 GFP_KERNEL, cpu_to_node(cpu)); 4284 if (c) { 4285 raw_spin_lock_init(&c->lock); 4286 c->core_id = -1; 4287 } 4288 return c; 4289 } 4290 4291 4292 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4293 { 4294 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4295 4296 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4297 cpuc->shared_regs = allocate_shared_regs(cpu); 4298 if (!cpuc->shared_regs) 4299 goto err; 4300 } 4301 4302 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4303 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4304 4305 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4306 if (!cpuc->constraint_list) 4307 goto err_shared_regs; 4308 } 4309 4310 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4311 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4312 if (!cpuc->excl_cntrs) 4313 goto err_constraint_list; 4314 4315 cpuc->excl_thread_id = 0; 4316 } 4317 4318 return 0; 4319 4320 err_constraint_list: 4321 kfree(cpuc->constraint_list); 4322 cpuc->constraint_list = NULL; 4323 4324 err_shared_regs: 4325 kfree(cpuc->shared_regs); 4326 cpuc->shared_regs = NULL; 4327 4328 err: 4329 return -ENOMEM; 4330 } 4331 4332 static int intel_pmu_cpu_prepare(int cpu) 4333 { 4334 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4335 } 4336 4337 static void flip_smm_bit(void *data) 4338 { 4339 unsigned long set = *(unsigned long *)data; 4340 4341 if (set > 0) { 4342 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4343 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4344 } else { 4345 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4346 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4347 } 4348 } 4349 4350 static bool init_hybrid_pmu(int cpu) 4351 { 4352 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4353 u8 cpu_type = get_this_hybrid_cpu_type(); 4354 struct x86_hybrid_pmu *pmu = NULL; 4355 int i; 4356 4357 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4358 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4359 4360 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4361 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4362 pmu = &x86_pmu.hybrid_pmu[i]; 4363 break; 4364 } 4365 } 4366 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4367 cpuc->pmu = NULL; 4368 return false; 4369 } 4370 4371 /* Only check and dump the PMU information for the first CPU */ 4372 if (!cpumask_empty(&pmu->supported_cpus)) 4373 goto end; 4374 4375 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4376 return false; 4377 4378 pr_info("%s PMU driver: ", pmu->name); 4379 4380 if (pmu->intel_cap.pebs_output_pt_available) 4381 pr_cont("PEBS-via-PT "); 4382 4383 pr_cont("\n"); 4384 4385 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4386 pmu->intel_ctrl); 4387 4388 end: 4389 cpumask_set_cpu(cpu, &pmu->supported_cpus); 4390 cpuc->pmu = &pmu->pmu; 4391 4392 x86_pmu_update_cpu_context(&pmu->pmu, cpu); 4393 4394 return true; 4395 } 4396 4397 static void intel_pmu_cpu_starting(int cpu) 4398 { 4399 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4400 int core_id = topology_core_id(cpu); 4401 int i; 4402 4403 if (is_hybrid() && !init_hybrid_pmu(cpu)) 4404 return; 4405 4406 init_debug_store_on_cpu(cpu); 4407 /* 4408 * Deal with CPUs that don't clear their LBRs on power-up. 4409 */ 4410 intel_pmu_lbr_reset(); 4411 4412 cpuc->lbr_sel = NULL; 4413 4414 if (x86_pmu.flags & PMU_FL_TFA) { 4415 WARN_ON_ONCE(cpuc->tfa_shadow); 4416 cpuc->tfa_shadow = ~0ULL; 4417 intel_set_tfa(cpuc, false); 4418 } 4419 4420 if (x86_pmu.version > 1) 4421 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4422 4423 /* 4424 * Disable perf metrics if any added CPU doesn't support it. 4425 * 4426 * Turn off the check for a hybrid architecture, because the 4427 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4428 * the architecture features. The perf metrics is a model-specific 4429 * feature for now. The corresponding bit should always be 0 on 4430 * a hybrid platform, e.g., Alder Lake. 4431 */ 4432 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 4433 union perf_capabilities perf_cap; 4434 4435 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4436 if (!perf_cap.perf_metrics) { 4437 x86_pmu.intel_cap.perf_metrics = 0; 4438 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4439 } 4440 } 4441 4442 if (!cpuc->shared_regs) 4443 return; 4444 4445 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4446 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4447 struct intel_shared_regs *pc; 4448 4449 pc = per_cpu(cpu_hw_events, i).shared_regs; 4450 if (pc && pc->core_id == core_id) { 4451 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4452 cpuc->shared_regs = pc; 4453 break; 4454 } 4455 } 4456 cpuc->shared_regs->core_id = core_id; 4457 cpuc->shared_regs->refcnt++; 4458 } 4459 4460 if (x86_pmu.lbr_sel_map) 4461 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4462 4463 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4464 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4465 struct cpu_hw_events *sibling; 4466 struct intel_excl_cntrs *c; 4467 4468 sibling = &per_cpu(cpu_hw_events, i); 4469 c = sibling->excl_cntrs; 4470 if (c && c->core_id == core_id) { 4471 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4472 cpuc->excl_cntrs = c; 4473 if (!sibling->excl_thread_id) 4474 cpuc->excl_thread_id = 1; 4475 break; 4476 } 4477 } 4478 cpuc->excl_cntrs->core_id = core_id; 4479 cpuc->excl_cntrs->refcnt++; 4480 } 4481 } 4482 4483 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4484 { 4485 struct intel_excl_cntrs *c; 4486 4487 c = cpuc->excl_cntrs; 4488 if (c) { 4489 if (c->core_id == -1 || --c->refcnt == 0) 4490 kfree(c); 4491 cpuc->excl_cntrs = NULL; 4492 } 4493 4494 kfree(cpuc->constraint_list); 4495 cpuc->constraint_list = NULL; 4496 } 4497 4498 static void intel_pmu_cpu_dying(int cpu) 4499 { 4500 fini_debug_store_on_cpu(cpu); 4501 } 4502 4503 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4504 { 4505 struct intel_shared_regs *pc; 4506 4507 pc = cpuc->shared_regs; 4508 if (pc) { 4509 if (pc->core_id == -1 || --pc->refcnt == 0) 4510 kfree(pc); 4511 cpuc->shared_regs = NULL; 4512 } 4513 4514 free_excl_cntrs(cpuc); 4515 } 4516 4517 static void intel_pmu_cpu_dead(int cpu) 4518 { 4519 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4520 4521 intel_cpuc_finish(cpuc); 4522 4523 if (is_hybrid() && cpuc->pmu) 4524 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4525 } 4526 4527 static void intel_pmu_sched_task(struct perf_event_context *ctx, 4528 bool sched_in) 4529 { 4530 intel_pmu_pebs_sched_task(ctx, sched_in); 4531 intel_pmu_lbr_sched_task(ctx, sched_in); 4532 } 4533 4534 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4535 struct perf_event_context *next) 4536 { 4537 intel_pmu_lbr_swap_task_ctx(prev, next); 4538 } 4539 4540 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4541 { 4542 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4543 } 4544 4545 static void intel_aux_output_init(void) 4546 { 4547 /* Refer also intel_pmu_aux_output_match() */ 4548 if (x86_pmu.intel_cap.pebs_output_pt_available) 4549 x86_pmu.assign = intel_pmu_assign_event; 4550 } 4551 4552 static int intel_pmu_aux_output_match(struct perf_event *event) 4553 { 4554 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 4555 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4556 return 0; 4557 4558 return is_intel_pt_event(event); 4559 } 4560 4561 static int intel_pmu_filter_match(struct perf_event *event) 4562 { 4563 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4564 unsigned int cpu = smp_processor_id(); 4565 4566 return cpumask_test_cpu(cpu, &pmu->supported_cpus); 4567 } 4568 4569 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4570 4571 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4572 4573 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4574 4575 static struct attribute *intel_arch3_formats_attr[] = { 4576 &format_attr_event.attr, 4577 &format_attr_umask.attr, 4578 &format_attr_edge.attr, 4579 &format_attr_pc.attr, 4580 &format_attr_any.attr, 4581 &format_attr_inv.attr, 4582 &format_attr_cmask.attr, 4583 NULL, 4584 }; 4585 4586 static struct attribute *hsw_format_attr[] = { 4587 &format_attr_in_tx.attr, 4588 &format_attr_in_tx_cp.attr, 4589 &format_attr_offcore_rsp.attr, 4590 &format_attr_ldlat.attr, 4591 NULL 4592 }; 4593 4594 static struct attribute *nhm_format_attr[] = { 4595 &format_attr_offcore_rsp.attr, 4596 &format_attr_ldlat.attr, 4597 NULL 4598 }; 4599 4600 static struct attribute *slm_format_attr[] = { 4601 &format_attr_offcore_rsp.attr, 4602 NULL 4603 }; 4604 4605 static struct attribute *skl_format_attr[] = { 4606 &format_attr_frontend.attr, 4607 NULL, 4608 }; 4609 4610 static __initconst const struct x86_pmu core_pmu = { 4611 .name = "core", 4612 .handle_irq = x86_pmu_handle_irq, 4613 .disable_all = x86_pmu_disable_all, 4614 .enable_all = core_pmu_enable_all, 4615 .enable = core_pmu_enable_event, 4616 .disable = x86_pmu_disable_event, 4617 .hw_config = core_pmu_hw_config, 4618 .schedule_events = x86_schedule_events, 4619 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4620 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4621 .event_map = intel_pmu_event_map, 4622 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4623 .apic = 1, 4624 .large_pebs_flags = LARGE_PEBS_FLAGS, 4625 4626 /* 4627 * Intel PMCs cannot be accessed sanely above 32-bit width, 4628 * so we install an artificial 1<<31 period regardless of 4629 * the generic event period: 4630 */ 4631 .max_period = (1ULL<<31) - 1, 4632 .get_event_constraints = intel_get_event_constraints, 4633 .put_event_constraints = intel_put_event_constraints, 4634 .event_constraints = intel_core_event_constraints, 4635 .guest_get_msrs = core_guest_get_msrs, 4636 .format_attrs = intel_arch_formats_attr, 4637 .events_sysfs_show = intel_event_sysfs_show, 4638 4639 /* 4640 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4641 * together with PMU version 1 and thus be using core_pmu with 4642 * shared_regs. We need following callbacks here to allocate 4643 * it properly. 4644 */ 4645 .cpu_prepare = intel_pmu_cpu_prepare, 4646 .cpu_starting = intel_pmu_cpu_starting, 4647 .cpu_dying = intel_pmu_cpu_dying, 4648 .cpu_dead = intel_pmu_cpu_dead, 4649 4650 .check_period = intel_pmu_check_period, 4651 4652 .lbr_reset = intel_pmu_lbr_reset_64, 4653 .lbr_read = intel_pmu_lbr_read_64, 4654 .lbr_save = intel_pmu_lbr_save, 4655 .lbr_restore = intel_pmu_lbr_restore, 4656 }; 4657 4658 static __initconst const struct x86_pmu intel_pmu = { 4659 .name = "Intel", 4660 .handle_irq = intel_pmu_handle_irq, 4661 .disable_all = intel_pmu_disable_all, 4662 .enable_all = intel_pmu_enable_all, 4663 .enable = intel_pmu_enable_event, 4664 .disable = intel_pmu_disable_event, 4665 .add = intel_pmu_add_event, 4666 .del = intel_pmu_del_event, 4667 .read = intel_pmu_read_event, 4668 .hw_config = intel_pmu_hw_config, 4669 .schedule_events = x86_schedule_events, 4670 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4671 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4672 .event_map = intel_pmu_event_map, 4673 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4674 .apic = 1, 4675 .large_pebs_flags = LARGE_PEBS_FLAGS, 4676 /* 4677 * Intel PMCs cannot be accessed sanely above 32 bit width, 4678 * so we install an artificial 1<<31 period regardless of 4679 * the generic event period: 4680 */ 4681 .max_period = (1ULL << 31) - 1, 4682 .get_event_constraints = intel_get_event_constraints, 4683 .put_event_constraints = intel_put_event_constraints, 4684 .pebs_aliases = intel_pebs_aliases_core2, 4685 4686 .format_attrs = intel_arch3_formats_attr, 4687 .events_sysfs_show = intel_event_sysfs_show, 4688 4689 .cpu_prepare = intel_pmu_cpu_prepare, 4690 .cpu_starting = intel_pmu_cpu_starting, 4691 .cpu_dying = intel_pmu_cpu_dying, 4692 .cpu_dead = intel_pmu_cpu_dead, 4693 4694 .guest_get_msrs = intel_guest_get_msrs, 4695 .sched_task = intel_pmu_sched_task, 4696 .swap_task_ctx = intel_pmu_swap_task_ctx, 4697 4698 .check_period = intel_pmu_check_period, 4699 4700 .aux_output_match = intel_pmu_aux_output_match, 4701 4702 .lbr_reset = intel_pmu_lbr_reset_64, 4703 .lbr_read = intel_pmu_lbr_read_64, 4704 .lbr_save = intel_pmu_lbr_save, 4705 .lbr_restore = intel_pmu_lbr_restore, 4706 }; 4707 4708 static __init void intel_clovertown_quirk(void) 4709 { 4710 /* 4711 * PEBS is unreliable due to: 4712 * 4713 * AJ67 - PEBS may experience CPL leaks 4714 * AJ68 - PEBS PMI may be delayed by one event 4715 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4716 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4717 * 4718 * AJ67 could be worked around by restricting the OS/USR flags. 4719 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4720 * 4721 * AJ106 could possibly be worked around by not allowing LBR 4722 * usage from PEBS, including the fixup. 4723 * AJ68 could possibly be worked around by always programming 4724 * a pebs_event_reset[0] value and coping with the lost events. 4725 * 4726 * But taken together it might just make sense to not enable PEBS on 4727 * these chips. 4728 */ 4729 pr_warn("PEBS disabled due to CPU errata\n"); 4730 x86_pmu.pebs = 0; 4731 x86_pmu.pebs_constraints = NULL; 4732 } 4733 4734 static const struct x86_cpu_desc isolation_ucodes[] = { 4735 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4736 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 4737 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 4738 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 4739 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4740 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 4741 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 4742 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 4743 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 4744 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 4745 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 4746 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 4747 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 4748 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4749 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 4750 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 4751 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 4752 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4753 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4754 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4755 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4756 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4757 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4758 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4759 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4760 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4761 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4762 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 4763 {} 4764 }; 4765 4766 static void intel_check_pebs_isolation(void) 4767 { 4768 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4769 } 4770 4771 static __init void intel_pebs_isolation_quirk(void) 4772 { 4773 WARN_ON_ONCE(x86_pmu.check_microcode); 4774 x86_pmu.check_microcode = intel_check_pebs_isolation; 4775 intel_check_pebs_isolation(); 4776 } 4777 4778 static const struct x86_cpu_desc pebs_ucodes[] = { 4779 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4780 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4781 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4782 {} 4783 }; 4784 4785 static bool intel_snb_pebs_broken(void) 4786 { 4787 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4788 } 4789 4790 static void intel_snb_check_microcode(void) 4791 { 4792 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4793 return; 4794 4795 /* 4796 * Serialized by the microcode lock.. 4797 */ 4798 if (x86_pmu.pebs_broken) { 4799 pr_info("PEBS enabled due to microcode update\n"); 4800 x86_pmu.pebs_broken = 0; 4801 } else { 4802 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4803 x86_pmu.pebs_broken = 1; 4804 } 4805 } 4806 4807 static bool is_lbr_from(unsigned long msr) 4808 { 4809 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4810 4811 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4812 } 4813 4814 /* 4815 * Under certain circumstances, access certain MSR may cause #GP. 4816 * The function tests if the input MSR can be safely accessed. 4817 */ 4818 static bool check_msr(unsigned long msr, u64 mask) 4819 { 4820 u64 val_old, val_new, val_tmp; 4821 4822 /* 4823 * Disable the check for real HW, so we don't 4824 * mess with potentially enabled registers: 4825 */ 4826 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4827 return true; 4828 4829 /* 4830 * Read the current value, change it and read it back to see if it 4831 * matches, this is needed to detect certain hardware emulators 4832 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4833 */ 4834 if (rdmsrl_safe(msr, &val_old)) 4835 return false; 4836 4837 /* 4838 * Only change the bits which can be updated by wrmsrl. 4839 */ 4840 val_tmp = val_old ^ mask; 4841 4842 if (is_lbr_from(msr)) 4843 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4844 4845 if (wrmsrl_safe(msr, val_tmp) || 4846 rdmsrl_safe(msr, &val_new)) 4847 return false; 4848 4849 /* 4850 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4851 * should equal rdmsrl()'s even with the quirk. 4852 */ 4853 if (val_new != val_tmp) 4854 return false; 4855 4856 if (is_lbr_from(msr)) 4857 val_old = lbr_from_signext_quirk_wr(val_old); 4858 4859 /* Here it's sure that the MSR can be safely accessed. 4860 * Restore the old value and return. 4861 */ 4862 wrmsrl(msr, val_old); 4863 4864 return true; 4865 } 4866 4867 static __init void intel_sandybridge_quirk(void) 4868 { 4869 x86_pmu.check_microcode = intel_snb_check_microcode; 4870 cpus_read_lock(); 4871 intel_snb_check_microcode(); 4872 cpus_read_unlock(); 4873 } 4874 4875 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4876 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4877 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4878 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4879 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4880 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4881 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4882 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4883 }; 4884 4885 static __init void intel_arch_events_quirk(void) 4886 { 4887 int bit; 4888 4889 /* disable event that reported as not present by cpuid */ 4890 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4891 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4892 pr_warn("CPUID marked event: \'%s\' unavailable\n", 4893 intel_arch_events_map[bit].name); 4894 } 4895 } 4896 4897 static __init void intel_nehalem_quirk(void) 4898 { 4899 union cpuid10_ebx ebx; 4900 4901 ebx.full = x86_pmu.events_maskl; 4902 if (ebx.split.no_branch_misses_retired) { 4903 /* 4904 * Erratum AAJ80 detected, we work it around by using 4905 * the BR_MISP_EXEC.ANY event. This will over-count 4906 * branch-misses, but it's still much better than the 4907 * architectural event which is often completely bogus: 4908 */ 4909 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4910 ebx.split.no_branch_misses_retired = 0; 4911 x86_pmu.events_maskl = ebx.full; 4912 pr_info("CPU erratum AAJ80 worked around\n"); 4913 } 4914 } 4915 4916 /* 4917 * enable software workaround for errata: 4918 * SNB: BJ122 4919 * IVB: BV98 4920 * HSW: HSD29 4921 * 4922 * Only needed when HT is enabled. However detecting 4923 * if HT is enabled is difficult (model specific). So instead, 4924 * we enable the workaround in the early boot, and verify if 4925 * it is needed in a later initcall phase once we have valid 4926 * topology information to check if HT is actually enabled 4927 */ 4928 static __init void intel_ht_bug(void) 4929 { 4930 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4931 4932 x86_pmu.start_scheduling = intel_start_scheduling; 4933 x86_pmu.commit_scheduling = intel_commit_scheduling; 4934 x86_pmu.stop_scheduling = intel_stop_scheduling; 4935 } 4936 4937 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4938 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4939 4940 /* Haswell special events */ 4941 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4942 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4943 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4944 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4945 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4946 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4947 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4948 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4949 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4950 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4951 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4952 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4953 4954 static struct attribute *hsw_events_attrs[] = { 4955 EVENT_PTR(td_slots_issued), 4956 EVENT_PTR(td_slots_retired), 4957 EVENT_PTR(td_fetch_bubbles), 4958 EVENT_PTR(td_total_slots), 4959 EVENT_PTR(td_total_slots_scale), 4960 EVENT_PTR(td_recovery_bubbles), 4961 EVENT_PTR(td_recovery_bubbles_scale), 4962 NULL 4963 }; 4964 4965 static struct attribute *hsw_mem_events_attrs[] = { 4966 EVENT_PTR(mem_ld_hsw), 4967 EVENT_PTR(mem_st_hsw), 4968 NULL, 4969 }; 4970 4971 static struct attribute *hsw_tsx_events_attrs[] = { 4972 EVENT_PTR(tx_start), 4973 EVENT_PTR(tx_commit), 4974 EVENT_PTR(tx_abort), 4975 EVENT_PTR(tx_capacity), 4976 EVENT_PTR(tx_conflict), 4977 EVENT_PTR(el_start), 4978 EVENT_PTR(el_commit), 4979 EVENT_PTR(el_abort), 4980 EVENT_PTR(el_capacity), 4981 EVENT_PTR(el_conflict), 4982 EVENT_PTR(cycles_t), 4983 EVENT_PTR(cycles_ct), 4984 NULL 4985 }; 4986 4987 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 4988 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 4989 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 4990 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 4991 4992 static struct attribute *icl_events_attrs[] = { 4993 EVENT_PTR(mem_ld_hsw), 4994 EVENT_PTR(mem_st_hsw), 4995 NULL, 4996 }; 4997 4998 static struct attribute *icl_td_events_attrs[] = { 4999 EVENT_PTR(slots), 5000 EVENT_PTR(td_retiring), 5001 EVENT_PTR(td_bad_spec), 5002 EVENT_PTR(td_fe_bound), 5003 EVENT_PTR(td_be_bound), 5004 NULL, 5005 }; 5006 5007 static struct attribute *icl_tsx_events_attrs[] = { 5008 EVENT_PTR(tx_start), 5009 EVENT_PTR(tx_abort), 5010 EVENT_PTR(tx_commit), 5011 EVENT_PTR(tx_capacity_read), 5012 EVENT_PTR(tx_capacity_write), 5013 EVENT_PTR(tx_conflict), 5014 EVENT_PTR(el_start), 5015 EVENT_PTR(el_abort), 5016 EVENT_PTR(el_commit), 5017 EVENT_PTR(el_capacity_read), 5018 EVENT_PTR(el_capacity_write), 5019 EVENT_PTR(el_conflict), 5020 EVENT_PTR(cycles_t), 5021 EVENT_PTR(cycles_ct), 5022 NULL, 5023 }; 5024 5025 5026 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5027 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 5028 5029 static struct attribute *spr_events_attrs[] = { 5030 EVENT_PTR(mem_ld_hsw), 5031 EVENT_PTR(mem_st_spr), 5032 EVENT_PTR(mem_ld_aux), 5033 NULL, 5034 }; 5035 5036 static struct attribute *spr_td_events_attrs[] = { 5037 EVENT_PTR(slots), 5038 EVENT_PTR(td_retiring), 5039 EVENT_PTR(td_bad_spec), 5040 EVENT_PTR(td_fe_bound), 5041 EVENT_PTR(td_be_bound), 5042 EVENT_PTR(td_heavy_ops), 5043 EVENT_PTR(td_br_mispredict), 5044 EVENT_PTR(td_fetch_lat), 5045 EVENT_PTR(td_mem_bound), 5046 NULL, 5047 }; 5048 5049 static struct attribute *spr_tsx_events_attrs[] = { 5050 EVENT_PTR(tx_start), 5051 EVENT_PTR(tx_abort), 5052 EVENT_PTR(tx_commit), 5053 EVENT_PTR(tx_capacity_read), 5054 EVENT_PTR(tx_capacity_write), 5055 EVENT_PTR(tx_conflict), 5056 EVENT_PTR(cycles_t), 5057 EVENT_PTR(cycles_ct), 5058 NULL, 5059 }; 5060 5061 static ssize_t freeze_on_smi_show(struct device *cdev, 5062 struct device_attribute *attr, 5063 char *buf) 5064 { 5065 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 5066 } 5067 5068 static DEFINE_MUTEX(freeze_on_smi_mutex); 5069 5070 static ssize_t freeze_on_smi_store(struct device *cdev, 5071 struct device_attribute *attr, 5072 const char *buf, size_t count) 5073 { 5074 unsigned long val; 5075 ssize_t ret; 5076 5077 ret = kstrtoul(buf, 0, &val); 5078 if (ret) 5079 return ret; 5080 5081 if (val > 1) 5082 return -EINVAL; 5083 5084 mutex_lock(&freeze_on_smi_mutex); 5085 5086 if (x86_pmu.attr_freeze_on_smi == val) 5087 goto done; 5088 5089 x86_pmu.attr_freeze_on_smi = val; 5090 5091 cpus_read_lock(); 5092 on_each_cpu(flip_smm_bit, &val, 1); 5093 cpus_read_unlock(); 5094 done: 5095 mutex_unlock(&freeze_on_smi_mutex); 5096 5097 return count; 5098 } 5099 5100 static void update_tfa_sched(void *ignored) 5101 { 5102 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5103 5104 /* 5105 * check if PMC3 is used 5106 * and if so force schedule out for all event types all contexts 5107 */ 5108 if (test_bit(3, cpuc->active_mask)) 5109 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5110 } 5111 5112 static ssize_t show_sysctl_tfa(struct device *cdev, 5113 struct device_attribute *attr, 5114 char *buf) 5115 { 5116 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5117 } 5118 5119 static ssize_t set_sysctl_tfa(struct device *cdev, 5120 struct device_attribute *attr, 5121 const char *buf, size_t count) 5122 { 5123 bool val; 5124 ssize_t ret; 5125 5126 ret = kstrtobool(buf, &val); 5127 if (ret) 5128 return ret; 5129 5130 /* no change */ 5131 if (val == allow_tsx_force_abort) 5132 return count; 5133 5134 allow_tsx_force_abort = val; 5135 5136 cpus_read_lock(); 5137 on_each_cpu(update_tfa_sched, NULL, 1); 5138 cpus_read_unlock(); 5139 5140 return count; 5141 } 5142 5143 5144 static DEVICE_ATTR_RW(freeze_on_smi); 5145 5146 static ssize_t branches_show(struct device *cdev, 5147 struct device_attribute *attr, 5148 char *buf) 5149 { 5150 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5151 } 5152 5153 static DEVICE_ATTR_RO(branches); 5154 5155 static struct attribute *lbr_attrs[] = { 5156 &dev_attr_branches.attr, 5157 NULL 5158 }; 5159 5160 static char pmu_name_str[30]; 5161 5162 static ssize_t pmu_name_show(struct device *cdev, 5163 struct device_attribute *attr, 5164 char *buf) 5165 { 5166 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5167 } 5168 5169 static DEVICE_ATTR_RO(pmu_name); 5170 5171 static struct attribute *intel_pmu_caps_attrs[] = { 5172 &dev_attr_pmu_name.attr, 5173 NULL 5174 }; 5175 5176 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5177 show_sysctl_tfa, 5178 set_sysctl_tfa); 5179 5180 static struct attribute *intel_pmu_attrs[] = { 5181 &dev_attr_freeze_on_smi.attr, 5182 &dev_attr_allow_tsx_force_abort.attr, 5183 NULL, 5184 }; 5185 5186 static umode_t 5187 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5188 { 5189 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5190 } 5191 5192 static umode_t 5193 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5194 { 5195 return x86_pmu.pebs ? attr->mode : 0; 5196 } 5197 5198 static umode_t 5199 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5200 { 5201 return x86_pmu.lbr_nr ? attr->mode : 0; 5202 } 5203 5204 static umode_t 5205 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5206 { 5207 return x86_pmu.version >= 2 ? attr->mode : 0; 5208 } 5209 5210 static umode_t 5211 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5212 { 5213 if (attr == &dev_attr_allow_tsx_force_abort.attr) 5214 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5215 5216 return attr->mode; 5217 } 5218 5219 static struct attribute_group group_events_td = { 5220 .name = "events", 5221 }; 5222 5223 static struct attribute_group group_events_mem = { 5224 .name = "events", 5225 .is_visible = pebs_is_visible, 5226 }; 5227 5228 static struct attribute_group group_events_tsx = { 5229 .name = "events", 5230 .is_visible = tsx_is_visible, 5231 }; 5232 5233 static struct attribute_group group_caps_gen = { 5234 .name = "caps", 5235 .attrs = intel_pmu_caps_attrs, 5236 }; 5237 5238 static struct attribute_group group_caps_lbr = { 5239 .name = "caps", 5240 .attrs = lbr_attrs, 5241 .is_visible = lbr_is_visible, 5242 }; 5243 5244 static struct attribute_group group_format_extra = { 5245 .name = "format", 5246 .is_visible = exra_is_visible, 5247 }; 5248 5249 static struct attribute_group group_format_extra_skl = { 5250 .name = "format", 5251 .is_visible = exra_is_visible, 5252 }; 5253 5254 static struct attribute_group group_default = { 5255 .attrs = intel_pmu_attrs, 5256 .is_visible = default_is_visible, 5257 }; 5258 5259 static const struct attribute_group *attr_update[] = { 5260 &group_events_td, 5261 &group_events_mem, 5262 &group_events_tsx, 5263 &group_caps_gen, 5264 &group_caps_lbr, 5265 &group_format_extra, 5266 &group_format_extra_skl, 5267 &group_default, 5268 NULL, 5269 }; 5270 5271 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5272 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5273 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5274 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5275 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5276 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5277 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5278 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5279 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5280 5281 static struct attribute *adl_hybrid_events_attrs[] = { 5282 EVENT_PTR(slots_adl), 5283 EVENT_PTR(td_retiring_adl), 5284 EVENT_PTR(td_bad_spec_adl), 5285 EVENT_PTR(td_fe_bound_adl), 5286 EVENT_PTR(td_be_bound_adl), 5287 EVENT_PTR(td_heavy_ops_adl), 5288 EVENT_PTR(td_br_mis_adl), 5289 EVENT_PTR(td_fetch_lat_adl), 5290 EVENT_PTR(td_mem_bound_adl), 5291 NULL, 5292 }; 5293 5294 /* Must be in IDX order */ 5295 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5296 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5297 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5298 5299 static struct attribute *adl_hybrid_mem_attrs[] = { 5300 EVENT_PTR(mem_ld_adl), 5301 EVENT_PTR(mem_st_adl), 5302 EVENT_PTR(mem_ld_aux_adl), 5303 NULL, 5304 }; 5305 5306 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5307 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5308 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5309 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5310 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5311 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5312 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5313 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5314 5315 static struct attribute *adl_hybrid_tsx_attrs[] = { 5316 EVENT_PTR(tx_start_adl), 5317 EVENT_PTR(tx_abort_adl), 5318 EVENT_PTR(tx_commit_adl), 5319 EVENT_PTR(tx_capacity_read_adl), 5320 EVENT_PTR(tx_capacity_write_adl), 5321 EVENT_PTR(tx_conflict_adl), 5322 EVENT_PTR(cycles_t_adl), 5323 EVENT_PTR(cycles_ct_adl), 5324 NULL, 5325 }; 5326 5327 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5328 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5329 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5330 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5331 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5332 5333 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5334 FORMAT_HYBRID_PTR(in_tx), 5335 FORMAT_HYBRID_PTR(in_tx_cp), 5336 FORMAT_HYBRID_PTR(offcore_rsp), 5337 FORMAT_HYBRID_PTR(ldlat), 5338 FORMAT_HYBRID_PTR(frontend), 5339 NULL, 5340 }; 5341 5342 static struct attribute *adl_hybrid_extra_attr[] = { 5343 FORMAT_HYBRID_PTR(offcore_rsp), 5344 FORMAT_HYBRID_PTR(ldlat), 5345 FORMAT_HYBRID_PTR(frontend), 5346 NULL, 5347 }; 5348 5349 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 5350 { 5351 struct device *dev = kobj_to_dev(kobj); 5352 struct x86_hybrid_pmu *pmu = 5353 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5354 struct perf_pmu_events_hybrid_attr *pmu_attr = 5355 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 5356 5357 return pmu->cpu_type & pmu_attr->pmu_type; 5358 } 5359 5360 static umode_t hybrid_events_is_visible(struct kobject *kobj, 5361 struct attribute *attr, int i) 5362 { 5363 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 5364 } 5365 5366 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 5367 { 5368 int cpu = cpumask_first(&pmu->supported_cpus); 5369 5370 return (cpu >= nr_cpu_ids) ? -1 : cpu; 5371 } 5372 5373 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 5374 struct attribute *attr, int i) 5375 { 5376 struct device *dev = kobj_to_dev(kobj); 5377 struct x86_hybrid_pmu *pmu = 5378 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5379 int cpu = hybrid_find_supported_cpu(pmu); 5380 5381 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 5382 } 5383 5384 static umode_t hybrid_format_is_visible(struct kobject *kobj, 5385 struct attribute *attr, int i) 5386 { 5387 struct device *dev = kobj_to_dev(kobj); 5388 struct x86_hybrid_pmu *pmu = 5389 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5390 struct perf_pmu_format_hybrid_attr *pmu_attr = 5391 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 5392 int cpu = hybrid_find_supported_cpu(pmu); 5393 5394 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 5395 } 5396 5397 static struct attribute_group hybrid_group_events_td = { 5398 .name = "events", 5399 .is_visible = hybrid_events_is_visible, 5400 }; 5401 5402 static struct attribute_group hybrid_group_events_mem = { 5403 .name = "events", 5404 .is_visible = hybrid_events_is_visible, 5405 }; 5406 5407 static struct attribute_group hybrid_group_events_tsx = { 5408 .name = "events", 5409 .is_visible = hybrid_tsx_is_visible, 5410 }; 5411 5412 static struct attribute_group hybrid_group_format_extra = { 5413 .name = "format", 5414 .is_visible = hybrid_format_is_visible, 5415 }; 5416 5417 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 5418 struct device_attribute *attr, 5419 char *buf) 5420 { 5421 struct x86_hybrid_pmu *pmu = 5422 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 5423 5424 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 5425 } 5426 5427 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 5428 static struct attribute *intel_hybrid_cpus_attrs[] = { 5429 &dev_attr_cpus.attr, 5430 NULL, 5431 }; 5432 5433 static struct attribute_group hybrid_group_cpus = { 5434 .attrs = intel_hybrid_cpus_attrs, 5435 }; 5436 5437 static const struct attribute_group *hybrid_attr_update[] = { 5438 &hybrid_group_events_td, 5439 &hybrid_group_events_mem, 5440 &hybrid_group_events_tsx, 5441 &group_caps_gen, 5442 &group_caps_lbr, 5443 &hybrid_group_format_extra, 5444 &group_default, 5445 &hybrid_group_cpus, 5446 NULL, 5447 }; 5448 5449 static struct attribute *empty_attrs; 5450 5451 static void intel_pmu_check_num_counters(int *num_counters, 5452 int *num_counters_fixed, 5453 u64 *intel_ctrl, u64 fixed_mask) 5454 { 5455 if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5456 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5457 *num_counters, INTEL_PMC_MAX_GENERIC); 5458 *num_counters = INTEL_PMC_MAX_GENERIC; 5459 } 5460 *intel_ctrl = (1ULL << *num_counters) - 1; 5461 5462 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5463 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5464 *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5465 *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5466 } 5467 5468 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5469 } 5470 5471 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5472 int num_counters, 5473 int num_counters_fixed, 5474 u64 intel_ctrl) 5475 { 5476 struct event_constraint *c; 5477 5478 if (!event_constraints) 5479 return; 5480 5481 /* 5482 * event on fixed counter2 (REF_CYCLES) only works on this 5483 * counter, so do not extend mask to generic counters 5484 */ 5485 for_each_event_constraint(c, event_constraints) { 5486 /* 5487 * Don't extend the topdown slots and metrics 5488 * events to the generic counters. 5489 */ 5490 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5491 /* 5492 * Disable topdown slots and metrics events, 5493 * if slots event is not in CPUID. 5494 */ 5495 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5496 c->idxmsk64 = 0; 5497 c->weight = hweight64(c->idxmsk64); 5498 continue; 5499 } 5500 5501 if (c->cmask == FIXED_EVENT_FLAGS) { 5502 /* Disabled fixed counters which are not in CPUID */ 5503 c->idxmsk64 &= intel_ctrl; 5504 5505 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) 5506 c->idxmsk64 |= (1ULL << num_counters) - 1; 5507 } 5508 c->idxmsk64 &= 5509 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5510 c->weight = hweight64(c->idxmsk64); 5511 } 5512 } 5513 5514 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 5515 { 5516 struct extra_reg *er; 5517 5518 /* 5519 * Access extra MSR may cause #GP under certain circumstances. 5520 * E.g. KVM doesn't support offcore event 5521 * Check all extra_regs here. 5522 */ 5523 if (!extra_regs) 5524 return; 5525 5526 for (er = extra_regs; er->msr; er++) { 5527 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5528 /* Disable LBR select mapping */ 5529 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5530 x86_pmu.lbr_sel_map = NULL; 5531 } 5532 } 5533 5534 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5535 { 5536 struct x86_hybrid_pmu *pmu; 5537 int i; 5538 5539 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5540 pmu = &x86_pmu.hybrid_pmu[i]; 5541 5542 intel_pmu_check_num_counters(&pmu->num_counters, 5543 &pmu->num_counters_fixed, 5544 &pmu->intel_ctrl, 5545 fixed_mask); 5546 5547 if (pmu->intel_cap.perf_metrics) { 5548 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5549 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5550 } 5551 5552 if (pmu->intel_cap.pebs_output_pt_available) 5553 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5554 5555 intel_pmu_check_event_constraints(pmu->event_constraints, 5556 pmu->num_counters, 5557 pmu->num_counters_fixed, 5558 pmu->intel_ctrl); 5559 5560 intel_pmu_check_extra_regs(pmu->extra_regs); 5561 } 5562 } 5563 5564 __init int intel_pmu_init(void) 5565 { 5566 struct attribute **extra_skl_attr = &empty_attrs; 5567 struct attribute **extra_attr = &empty_attrs; 5568 struct attribute **td_attr = &empty_attrs; 5569 struct attribute **mem_attr = &empty_attrs; 5570 struct attribute **tsx_attr = &empty_attrs; 5571 union cpuid10_edx edx; 5572 union cpuid10_eax eax; 5573 union cpuid10_ebx ebx; 5574 unsigned int fixed_mask; 5575 bool pmem = false; 5576 int version, i; 5577 char *name; 5578 struct x86_hybrid_pmu *pmu; 5579 5580 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5581 switch (boot_cpu_data.x86) { 5582 case 0x6: 5583 return p6_pmu_init(); 5584 case 0xb: 5585 return knc_pmu_init(); 5586 case 0xf: 5587 return p4_pmu_init(); 5588 } 5589 return -ENODEV; 5590 } 5591 5592 /* 5593 * Check whether the Architectural PerfMon supports 5594 * Branch Misses Retired hw_event or not. 5595 */ 5596 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5597 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5598 return -ENODEV; 5599 5600 version = eax.split.version_id; 5601 if (version < 2) 5602 x86_pmu = core_pmu; 5603 else 5604 x86_pmu = intel_pmu; 5605 5606 x86_pmu.version = version; 5607 x86_pmu.num_counters = eax.split.num_counters; 5608 x86_pmu.cntval_bits = eax.split.bit_width; 5609 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5610 5611 x86_pmu.events_maskl = ebx.full; 5612 x86_pmu.events_mask_len = eax.split.mask_length; 5613 5614 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5615 5616 /* 5617 * Quirk: v2 perfmon does not report fixed-purpose events, so 5618 * assume at least 3 events, when not running in a hypervisor: 5619 */ 5620 if (version > 1 && version < 5) { 5621 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5622 5623 x86_pmu.num_counters_fixed = 5624 max((int)edx.split.num_counters_fixed, assume); 5625 5626 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 5627 } else if (version >= 5) 5628 x86_pmu.num_counters_fixed = fls(fixed_mask); 5629 5630 if (boot_cpu_has(X86_FEATURE_PDCM)) { 5631 u64 capabilities; 5632 5633 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5634 x86_pmu.intel_cap.capabilities = capabilities; 5635 } 5636 5637 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 5638 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5639 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5640 } 5641 5642 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 5643 intel_pmu_arch_lbr_init(); 5644 5645 intel_ds_init(); 5646 5647 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5648 5649 if (version >= 5) { 5650 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5651 if (x86_pmu.intel_cap.anythread_deprecated) 5652 pr_cont(" AnyThread deprecated, "); 5653 } 5654 5655 /* 5656 * Install the hw-cache-events table: 5657 */ 5658 switch (boot_cpu_data.x86_model) { 5659 case INTEL_FAM6_CORE_YONAH: 5660 pr_cont("Core events, "); 5661 name = "core"; 5662 break; 5663 5664 case INTEL_FAM6_CORE2_MEROM: 5665 x86_add_quirk(intel_clovertown_quirk); 5666 fallthrough; 5667 5668 case INTEL_FAM6_CORE2_MEROM_L: 5669 case INTEL_FAM6_CORE2_PENRYN: 5670 case INTEL_FAM6_CORE2_DUNNINGTON: 5671 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5672 sizeof(hw_cache_event_ids)); 5673 5674 intel_pmu_lbr_init_core(); 5675 5676 x86_pmu.event_constraints = intel_core2_event_constraints; 5677 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5678 pr_cont("Core2 events, "); 5679 name = "core2"; 5680 break; 5681 5682 case INTEL_FAM6_NEHALEM: 5683 case INTEL_FAM6_NEHALEM_EP: 5684 case INTEL_FAM6_NEHALEM_EX: 5685 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5686 sizeof(hw_cache_event_ids)); 5687 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5688 sizeof(hw_cache_extra_regs)); 5689 5690 intel_pmu_lbr_init_nhm(); 5691 5692 x86_pmu.event_constraints = intel_nehalem_event_constraints; 5693 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5694 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5695 x86_pmu.extra_regs = intel_nehalem_extra_regs; 5696 x86_pmu.limit_period = nhm_limit_period; 5697 5698 mem_attr = nhm_mem_events_attrs; 5699 5700 /* UOPS_ISSUED.STALLED_CYCLES */ 5701 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5702 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5703 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5704 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5705 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5706 5707 intel_pmu_pebs_data_source_nhm(); 5708 x86_add_quirk(intel_nehalem_quirk); 5709 x86_pmu.pebs_no_tlb = 1; 5710 extra_attr = nhm_format_attr; 5711 5712 pr_cont("Nehalem events, "); 5713 name = "nehalem"; 5714 break; 5715 5716 case INTEL_FAM6_ATOM_BONNELL: 5717 case INTEL_FAM6_ATOM_BONNELL_MID: 5718 case INTEL_FAM6_ATOM_SALTWELL: 5719 case INTEL_FAM6_ATOM_SALTWELL_MID: 5720 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5721 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5722 sizeof(hw_cache_event_ids)); 5723 5724 intel_pmu_lbr_init_atom(); 5725 5726 x86_pmu.event_constraints = intel_gen_event_constraints; 5727 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5728 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5729 pr_cont("Atom events, "); 5730 name = "bonnell"; 5731 break; 5732 5733 case INTEL_FAM6_ATOM_SILVERMONT: 5734 case INTEL_FAM6_ATOM_SILVERMONT_D: 5735 case INTEL_FAM6_ATOM_SILVERMONT_MID: 5736 case INTEL_FAM6_ATOM_AIRMONT: 5737 case INTEL_FAM6_ATOM_AIRMONT_MID: 5738 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5739 sizeof(hw_cache_event_ids)); 5740 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5741 sizeof(hw_cache_extra_regs)); 5742 5743 intel_pmu_lbr_init_slm(); 5744 5745 x86_pmu.event_constraints = intel_slm_event_constraints; 5746 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5747 x86_pmu.extra_regs = intel_slm_extra_regs; 5748 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5749 td_attr = slm_events_attrs; 5750 extra_attr = slm_format_attr; 5751 pr_cont("Silvermont events, "); 5752 name = "silvermont"; 5753 break; 5754 5755 case INTEL_FAM6_ATOM_GOLDMONT: 5756 case INTEL_FAM6_ATOM_GOLDMONT_D: 5757 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 5758 sizeof(hw_cache_event_ids)); 5759 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 5760 sizeof(hw_cache_extra_regs)); 5761 5762 intel_pmu_lbr_init_skl(); 5763 5764 x86_pmu.event_constraints = intel_slm_event_constraints; 5765 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 5766 x86_pmu.extra_regs = intel_glm_extra_regs; 5767 /* 5768 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5769 * for precise cycles. 5770 * :pp is identical to :ppp 5771 */ 5772 x86_pmu.pebs_aliases = NULL; 5773 x86_pmu.pebs_prec_dist = true; 5774 x86_pmu.lbr_pt_coexist = true; 5775 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5776 td_attr = glm_events_attrs; 5777 extra_attr = slm_format_attr; 5778 pr_cont("Goldmont events, "); 5779 name = "goldmont"; 5780 break; 5781 5782 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5783 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5784 sizeof(hw_cache_event_ids)); 5785 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5786 sizeof(hw_cache_extra_regs)); 5787 5788 intel_pmu_lbr_init_skl(); 5789 5790 x86_pmu.event_constraints = intel_slm_event_constraints; 5791 x86_pmu.extra_regs = intel_glm_extra_regs; 5792 /* 5793 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5794 * for precise cycles. 5795 */ 5796 x86_pmu.pebs_aliases = NULL; 5797 x86_pmu.pebs_prec_dist = true; 5798 x86_pmu.lbr_pt_coexist = true; 5799 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5800 x86_pmu.flags |= PMU_FL_PEBS_ALL; 5801 x86_pmu.get_event_constraints = glp_get_event_constraints; 5802 td_attr = glm_events_attrs; 5803 /* Goldmont Plus has 4-wide pipeline */ 5804 event_attr_td_total_slots_scale_glm.event_str = "4"; 5805 extra_attr = slm_format_attr; 5806 pr_cont("Goldmont plus events, "); 5807 name = "goldmont_plus"; 5808 break; 5809 5810 case INTEL_FAM6_ATOM_TREMONT_D: 5811 case INTEL_FAM6_ATOM_TREMONT: 5812 case INTEL_FAM6_ATOM_TREMONT_L: 5813 x86_pmu.late_ack = true; 5814 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5815 sizeof(hw_cache_event_ids)); 5816 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5817 sizeof(hw_cache_extra_regs)); 5818 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5819 5820 intel_pmu_lbr_init_skl(); 5821 5822 x86_pmu.event_constraints = intel_slm_event_constraints; 5823 x86_pmu.extra_regs = intel_tnt_extra_regs; 5824 /* 5825 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5826 * for precise cycles. 5827 */ 5828 x86_pmu.pebs_aliases = NULL; 5829 x86_pmu.pebs_prec_dist = true; 5830 x86_pmu.lbr_pt_coexist = true; 5831 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5832 x86_pmu.get_event_constraints = tnt_get_event_constraints; 5833 td_attr = tnt_events_attrs; 5834 extra_attr = slm_format_attr; 5835 pr_cont("Tremont events, "); 5836 name = "Tremont"; 5837 break; 5838 5839 case INTEL_FAM6_WESTMERE: 5840 case INTEL_FAM6_WESTMERE_EP: 5841 case INTEL_FAM6_WESTMERE_EX: 5842 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5843 sizeof(hw_cache_event_ids)); 5844 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5845 sizeof(hw_cache_extra_regs)); 5846 5847 intel_pmu_lbr_init_nhm(); 5848 5849 x86_pmu.event_constraints = intel_westmere_event_constraints; 5850 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5851 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5852 x86_pmu.extra_regs = intel_westmere_extra_regs; 5853 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5854 5855 mem_attr = nhm_mem_events_attrs; 5856 5857 /* UOPS_ISSUED.STALLED_CYCLES */ 5858 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5859 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5860 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5861 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5862 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5863 5864 intel_pmu_pebs_data_source_nhm(); 5865 extra_attr = nhm_format_attr; 5866 pr_cont("Westmere events, "); 5867 name = "westmere"; 5868 break; 5869 5870 case INTEL_FAM6_SANDYBRIDGE: 5871 case INTEL_FAM6_SANDYBRIDGE_X: 5872 x86_add_quirk(intel_sandybridge_quirk); 5873 x86_add_quirk(intel_ht_bug); 5874 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5875 sizeof(hw_cache_event_ids)); 5876 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5877 sizeof(hw_cache_extra_regs)); 5878 5879 intel_pmu_lbr_init_snb(); 5880 5881 x86_pmu.event_constraints = intel_snb_event_constraints; 5882 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5883 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5884 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5885 x86_pmu.extra_regs = intel_snbep_extra_regs; 5886 else 5887 x86_pmu.extra_regs = intel_snb_extra_regs; 5888 5889 5890 /* all extra regs are per-cpu when HT is on */ 5891 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5892 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5893 5894 td_attr = snb_events_attrs; 5895 mem_attr = snb_mem_events_attrs; 5896 5897 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5898 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5899 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5900 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5901 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5902 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5903 5904 extra_attr = nhm_format_attr; 5905 5906 pr_cont("SandyBridge events, "); 5907 name = "sandybridge"; 5908 break; 5909 5910 case INTEL_FAM6_IVYBRIDGE: 5911 case INTEL_FAM6_IVYBRIDGE_X: 5912 x86_add_quirk(intel_ht_bug); 5913 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5914 sizeof(hw_cache_event_ids)); 5915 /* dTLB-load-misses on IVB is different than SNB */ 5916 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5917 5918 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5919 sizeof(hw_cache_extra_regs)); 5920 5921 intel_pmu_lbr_init_snb(); 5922 5923 x86_pmu.event_constraints = intel_ivb_event_constraints; 5924 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5925 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5926 x86_pmu.pebs_prec_dist = true; 5927 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5928 x86_pmu.extra_regs = intel_snbep_extra_regs; 5929 else 5930 x86_pmu.extra_regs = intel_snb_extra_regs; 5931 /* all extra regs are per-cpu when HT is on */ 5932 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5933 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5934 5935 td_attr = snb_events_attrs; 5936 mem_attr = snb_mem_events_attrs; 5937 5938 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5939 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5940 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5941 5942 extra_attr = nhm_format_attr; 5943 5944 pr_cont("IvyBridge events, "); 5945 name = "ivybridge"; 5946 break; 5947 5948 5949 case INTEL_FAM6_HASWELL: 5950 case INTEL_FAM6_HASWELL_X: 5951 case INTEL_FAM6_HASWELL_L: 5952 case INTEL_FAM6_HASWELL_G: 5953 x86_add_quirk(intel_ht_bug); 5954 x86_add_quirk(intel_pebs_isolation_quirk); 5955 x86_pmu.late_ack = true; 5956 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5957 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5958 5959 intel_pmu_lbr_init_hsw(); 5960 5961 x86_pmu.event_constraints = intel_hsw_event_constraints; 5962 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5963 x86_pmu.extra_regs = intel_snbep_extra_regs; 5964 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5965 x86_pmu.pebs_prec_dist = true; 5966 /* all extra regs are per-cpu when HT is on */ 5967 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5968 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5969 5970 x86_pmu.hw_config = hsw_hw_config; 5971 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5972 x86_pmu.lbr_double_abort = true; 5973 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5974 hsw_format_attr : nhm_format_attr; 5975 td_attr = hsw_events_attrs; 5976 mem_attr = hsw_mem_events_attrs; 5977 tsx_attr = hsw_tsx_events_attrs; 5978 pr_cont("Haswell events, "); 5979 name = "haswell"; 5980 break; 5981 5982 case INTEL_FAM6_BROADWELL: 5983 case INTEL_FAM6_BROADWELL_D: 5984 case INTEL_FAM6_BROADWELL_G: 5985 case INTEL_FAM6_BROADWELL_X: 5986 x86_add_quirk(intel_pebs_isolation_quirk); 5987 x86_pmu.late_ack = true; 5988 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5989 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5990 5991 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5992 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5993 BDW_L3_MISS|HSW_SNOOP_DRAM; 5994 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 5995 HSW_SNOOP_DRAM; 5996 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 5997 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5998 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 5999 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6000 6001 intel_pmu_lbr_init_hsw(); 6002 6003 x86_pmu.event_constraints = intel_bdw_event_constraints; 6004 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6005 x86_pmu.extra_regs = intel_snbep_extra_regs; 6006 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6007 x86_pmu.pebs_prec_dist = true; 6008 /* all extra regs are per-cpu when HT is on */ 6009 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6010 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6011 6012 x86_pmu.hw_config = hsw_hw_config; 6013 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6014 x86_pmu.limit_period = bdw_limit_period; 6015 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6016 hsw_format_attr : nhm_format_attr; 6017 td_attr = hsw_events_attrs; 6018 mem_attr = hsw_mem_events_attrs; 6019 tsx_attr = hsw_tsx_events_attrs; 6020 pr_cont("Broadwell events, "); 6021 name = "broadwell"; 6022 break; 6023 6024 case INTEL_FAM6_XEON_PHI_KNL: 6025 case INTEL_FAM6_XEON_PHI_KNM: 6026 memcpy(hw_cache_event_ids, 6027 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6028 memcpy(hw_cache_extra_regs, 6029 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6030 intel_pmu_lbr_init_knl(); 6031 6032 x86_pmu.event_constraints = intel_slm_event_constraints; 6033 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6034 x86_pmu.extra_regs = intel_knl_extra_regs; 6035 6036 /* all extra regs are per-cpu when HT is on */ 6037 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6038 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6039 extra_attr = slm_format_attr; 6040 pr_cont("Knights Landing/Mill events, "); 6041 name = "knights-landing"; 6042 break; 6043 6044 case INTEL_FAM6_SKYLAKE_X: 6045 pmem = true; 6046 fallthrough; 6047 case INTEL_FAM6_SKYLAKE_L: 6048 case INTEL_FAM6_SKYLAKE: 6049 case INTEL_FAM6_KABYLAKE_L: 6050 case INTEL_FAM6_KABYLAKE: 6051 case INTEL_FAM6_COMETLAKE_L: 6052 case INTEL_FAM6_COMETLAKE: 6053 x86_add_quirk(intel_pebs_isolation_quirk); 6054 x86_pmu.late_ack = true; 6055 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6056 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6057 intel_pmu_lbr_init_skl(); 6058 6059 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6060 event_attr_td_recovery_bubbles.event_str_noht = 6061 "event=0xd,umask=0x1,cmask=1"; 6062 event_attr_td_recovery_bubbles.event_str_ht = 6063 "event=0xd,umask=0x1,cmask=1,any=1"; 6064 6065 x86_pmu.event_constraints = intel_skl_event_constraints; 6066 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6067 x86_pmu.extra_regs = intel_skl_extra_regs; 6068 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6069 x86_pmu.pebs_prec_dist = true; 6070 /* all extra regs are per-cpu when HT is on */ 6071 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6072 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6073 6074 x86_pmu.hw_config = hsw_hw_config; 6075 x86_pmu.get_event_constraints = hsw_get_event_constraints; 6076 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6077 hsw_format_attr : nhm_format_attr; 6078 extra_skl_attr = skl_format_attr; 6079 td_attr = hsw_events_attrs; 6080 mem_attr = hsw_mem_events_attrs; 6081 tsx_attr = hsw_tsx_events_attrs; 6082 intel_pmu_pebs_data_source_skl(pmem); 6083 6084 /* 6085 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6086 * TSX force abort hooks are not required on these systems. Only deploy 6087 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6088 */ 6089 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6090 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6091 x86_pmu.flags |= PMU_FL_TFA; 6092 x86_pmu.get_event_constraints = tfa_get_event_constraints; 6093 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6094 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6095 } 6096 6097 pr_cont("Skylake events, "); 6098 name = "skylake"; 6099 break; 6100 6101 case INTEL_FAM6_ICELAKE_X: 6102 case INTEL_FAM6_ICELAKE_D: 6103 pmem = true; 6104 fallthrough; 6105 case INTEL_FAM6_ICELAKE_L: 6106 case INTEL_FAM6_ICELAKE: 6107 case INTEL_FAM6_TIGERLAKE_L: 6108 case INTEL_FAM6_TIGERLAKE: 6109 case INTEL_FAM6_ROCKETLAKE: 6110 x86_pmu.late_ack = true; 6111 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6112 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6113 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6114 intel_pmu_lbr_init_skl(); 6115 6116 x86_pmu.event_constraints = intel_icl_event_constraints; 6117 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 6118 x86_pmu.extra_regs = intel_icl_extra_regs; 6119 x86_pmu.pebs_aliases = NULL; 6120 x86_pmu.pebs_prec_dist = true; 6121 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6122 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6123 6124 x86_pmu.hw_config = hsw_hw_config; 6125 x86_pmu.get_event_constraints = icl_get_event_constraints; 6126 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6127 hsw_format_attr : nhm_format_attr; 6128 extra_skl_attr = skl_format_attr; 6129 mem_attr = icl_events_attrs; 6130 td_attr = icl_td_events_attrs; 6131 tsx_attr = icl_tsx_events_attrs; 6132 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6133 x86_pmu.lbr_pt_coexist = true; 6134 intel_pmu_pebs_data_source_skl(pmem); 6135 x86_pmu.num_topdown_events = 4; 6136 x86_pmu.update_topdown_event = icl_update_topdown_event; 6137 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6138 pr_cont("Icelake events, "); 6139 name = "icelake"; 6140 break; 6141 6142 case INTEL_FAM6_SAPPHIRERAPIDS_X: 6143 pmem = true; 6144 x86_pmu.late_ack = true; 6145 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6146 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6147 6148 x86_pmu.event_constraints = intel_spr_event_constraints; 6149 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 6150 x86_pmu.extra_regs = intel_spr_extra_regs; 6151 x86_pmu.limit_period = spr_limit_period; 6152 x86_pmu.pebs_aliases = NULL; 6153 x86_pmu.pebs_prec_dist = true; 6154 x86_pmu.pebs_block = true; 6155 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6156 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6157 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6158 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6159 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6160 6161 x86_pmu.hw_config = hsw_hw_config; 6162 x86_pmu.get_event_constraints = spr_get_event_constraints; 6163 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6164 hsw_format_attr : nhm_format_attr; 6165 extra_skl_attr = skl_format_attr; 6166 mem_attr = spr_events_attrs; 6167 td_attr = spr_td_events_attrs; 6168 tsx_attr = spr_tsx_events_attrs; 6169 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6170 x86_pmu.lbr_pt_coexist = true; 6171 intel_pmu_pebs_data_source_skl(pmem); 6172 x86_pmu.num_topdown_events = 8; 6173 x86_pmu.update_topdown_event = icl_update_topdown_event; 6174 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 6175 pr_cont("Sapphire Rapids events, "); 6176 name = "sapphire_rapids"; 6177 break; 6178 6179 case INTEL_FAM6_ALDERLAKE: 6180 case INTEL_FAM6_ALDERLAKE_L: 6181 /* 6182 * Alder Lake has 2 types of CPU, core and atom. 6183 * 6184 * Initialize the common PerfMon capabilities here. 6185 */ 6186 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6187 sizeof(struct x86_hybrid_pmu), 6188 GFP_KERNEL); 6189 if (!x86_pmu.hybrid_pmu) 6190 return -ENOMEM; 6191 static_branch_enable(&perf_is_hybrid); 6192 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6193 6194 x86_pmu.pebs_aliases = NULL; 6195 x86_pmu.pebs_prec_dist = true; 6196 x86_pmu.pebs_block = true; 6197 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6198 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6199 x86_pmu.flags |= PMU_FL_PEBS_ALL; 6200 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6201 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6202 x86_pmu.lbr_pt_coexist = true; 6203 intel_pmu_pebs_data_source_skl(false); 6204 x86_pmu.num_topdown_events = 8; 6205 x86_pmu.update_topdown_event = adl_update_topdown_event; 6206 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; 6207 6208 x86_pmu.filter_match = intel_pmu_filter_match; 6209 x86_pmu.get_event_constraints = adl_get_event_constraints; 6210 x86_pmu.hw_config = adl_hw_config; 6211 x86_pmu.limit_period = spr_limit_period; 6212 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6213 /* 6214 * The rtm_abort_event is used to check whether to enable GPRs 6215 * for the RTM abort event. Atom doesn't have the RTM abort 6216 * event. There is no harmful to set it in the common 6217 * x86_pmu.rtm_abort_event. 6218 */ 6219 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6220 6221 td_attr = adl_hybrid_events_attrs; 6222 mem_attr = adl_hybrid_mem_attrs; 6223 tsx_attr = adl_hybrid_tsx_attrs; 6224 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6225 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6226 6227 /* Initialize big core specific PerfMon capabilities.*/ 6228 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6229 pmu->name = "cpu_core"; 6230 pmu->cpu_type = hybrid_big; 6231 pmu->late_ack = true; 6232 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6233 pmu->num_counters = x86_pmu.num_counters + 2; 6234 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6235 } else { 6236 pmu->num_counters = x86_pmu.num_counters; 6237 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6238 } 6239 6240 /* 6241 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 6242 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 6243 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 6244 * mistakenly add extra counters for P-cores. Correct the number of 6245 * counters here. 6246 */ 6247 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) { 6248 pmu->num_counters = x86_pmu.num_counters; 6249 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6250 } 6251 6252 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6253 pmu->unconstrained = (struct event_constraint) 6254 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6255 0, pmu->num_counters, 0, 0); 6256 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6257 pmu->intel_cap.perf_metrics = 1; 6258 pmu->intel_cap.pebs_output_pt_available = 0; 6259 6260 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6261 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6262 pmu->event_constraints = intel_spr_event_constraints; 6263 pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6264 pmu->extra_regs = intel_spr_extra_regs; 6265 6266 /* Initialize Atom core specific PerfMon capabilities.*/ 6267 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6268 pmu->name = "cpu_atom"; 6269 pmu->cpu_type = hybrid_small; 6270 pmu->mid_ack = true; 6271 pmu->num_counters = x86_pmu.num_counters; 6272 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6273 pmu->max_pebs_events = x86_pmu.max_pebs_events; 6274 pmu->unconstrained = (struct event_constraint) 6275 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6276 0, pmu->num_counters, 0, 0); 6277 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6278 pmu->intel_cap.perf_metrics = 0; 6279 pmu->intel_cap.pebs_output_pt_available = 1; 6280 6281 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6282 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6283 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6284 pmu->event_constraints = intel_slm_event_constraints; 6285 pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6286 pmu->extra_regs = intel_grt_extra_regs; 6287 pr_cont("Alderlake Hybrid events, "); 6288 name = "alderlake_hybrid"; 6289 break; 6290 6291 default: 6292 switch (x86_pmu.version) { 6293 case 1: 6294 x86_pmu.event_constraints = intel_v1_event_constraints; 6295 pr_cont("generic architected perfmon v1, "); 6296 name = "generic_arch_v1"; 6297 break; 6298 default: 6299 /* 6300 * default constraints for v2 and up 6301 */ 6302 x86_pmu.event_constraints = intel_gen_event_constraints; 6303 pr_cont("generic architected perfmon, "); 6304 name = "generic_arch_v2+"; 6305 break; 6306 } 6307 } 6308 6309 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6310 6311 if (!is_hybrid()) { 6312 group_events_td.attrs = td_attr; 6313 group_events_mem.attrs = mem_attr; 6314 group_events_tsx.attrs = tsx_attr; 6315 group_format_extra.attrs = extra_attr; 6316 group_format_extra_skl.attrs = extra_skl_attr; 6317 6318 x86_pmu.attr_update = attr_update; 6319 } else { 6320 hybrid_group_events_td.attrs = td_attr; 6321 hybrid_group_events_mem.attrs = mem_attr; 6322 hybrid_group_events_tsx.attrs = tsx_attr; 6323 hybrid_group_format_extra.attrs = extra_attr; 6324 6325 x86_pmu.attr_update = hybrid_attr_update; 6326 } 6327 6328 intel_pmu_check_num_counters(&x86_pmu.num_counters, 6329 &x86_pmu.num_counters_fixed, 6330 &x86_pmu.intel_ctrl, 6331 (u64)fixed_mask); 6332 6333 /* AnyThread may be deprecated on arch perfmon v5 or later */ 6334 if (x86_pmu.intel_cap.anythread_deprecated) 6335 x86_pmu.format_attrs = intel_arch_formats_attr; 6336 6337 intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6338 x86_pmu.num_counters, 6339 x86_pmu.num_counters_fixed, 6340 x86_pmu.intel_ctrl); 6341 /* 6342 * Access LBR MSR may cause #GP under certain circumstances. 6343 * E.g. KVM doesn't support LBR MSR 6344 * Check all LBT MSR here. 6345 * Disable LBR access if any LBR MSRs can not be accessed. 6346 */ 6347 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6348 x86_pmu.lbr_nr = 0; 6349 for (i = 0; i < x86_pmu.lbr_nr; i++) { 6350 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6351 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6352 x86_pmu.lbr_nr = 0; 6353 } 6354 6355 if (x86_pmu.lbr_nr) { 6356 intel_pmu_lbr_init(); 6357 6358 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6359 6360 /* only support branch_stack snapshot for perfmon >= v2 */ 6361 if (x86_pmu.disable_all == intel_pmu_disable_all) { 6362 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6363 static_call_update(perf_snapshot_branch_stack, 6364 intel_pmu_snapshot_arch_branch_stack); 6365 } else { 6366 static_call_update(perf_snapshot_branch_stack, 6367 intel_pmu_snapshot_branch_stack); 6368 } 6369 } 6370 } 6371 6372 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6373 6374 /* Support full width counters using alternative MSR range */ 6375 if (x86_pmu.intel_cap.full_width_write) { 6376 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6377 x86_pmu.perfctr = MSR_IA32_PMC0; 6378 pr_cont("full-width counters, "); 6379 } 6380 6381 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 6382 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 6383 6384 if (is_hybrid()) 6385 intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6386 6387 intel_aux_output_init(); 6388 6389 return 0; 6390 } 6391 6392 /* 6393 * HT bug: phase 2 init 6394 * Called once we have valid topology information to check 6395 * whether or not HT is enabled 6396 * If HT is off, then we disable the workaround 6397 */ 6398 static __init int fixup_ht_bug(void) 6399 { 6400 int c; 6401 /* 6402 * problem not present on this CPU model, nothing to do 6403 */ 6404 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6405 return 0; 6406 6407 if (topology_max_smt_threads() > 1) { 6408 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6409 return 0; 6410 } 6411 6412 cpus_read_lock(); 6413 6414 hardlockup_detector_perf_stop(); 6415 6416 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6417 6418 x86_pmu.start_scheduling = NULL; 6419 x86_pmu.commit_scheduling = NULL; 6420 x86_pmu.stop_scheduling = NULL; 6421 6422 hardlockup_detector_perf_restart(); 6423 6424 for_each_online_cpu(c) 6425 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6426 6427 cpus_read_unlock(); 6428 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6429 return 0; 6430 } 6431 subsys_initcall(fixup_ht_bug) 6432