1 /* 2 * Per core/cpu state 3 * 4 * Used to coordinate shared registers between HT threads or 5 * among events on a single PMU. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/stddef.h> 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/slab.h> 14 #include <linux/export.h> 15 #include <linux/nmi.h> 16 17 #include <asm/cpufeature.h> 18 #include <asm/hardirq.h> 19 #include <asm/intel-family.h> 20 #include <asm/apic.h> 21 22 #include "../perf_event.h" 23 24 /* 25 * Intel PerfMon, used on Core and later. 26 */ 27 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 28 { 29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 37 }; 38 39 static struct event_constraint intel_core_event_constraints[] __read_mostly = 40 { 41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 47 EVENT_CONSTRAINT_END 48 }; 49 50 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 51 { 52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 65 EVENT_CONSTRAINT_END 66 }; 67 68 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 69 { 70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 81 EVENT_CONSTRAINT_END 82 }; 83 84 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 85 { 86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 89 EVENT_EXTRA_END 90 }; 91 92 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 93 { 94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 101 EVENT_CONSTRAINT_END 102 }; 103 104 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 105 { 106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 118 119 /* 120 * When HT is off these events can only run on the bottom 4 counters 121 * When HT is on, they are impacted by the HT bug and require EXCL access 122 */ 123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 127 128 EVENT_CONSTRAINT_END 129 }; 130 131 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 132 { 133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 146 147 /* 148 * When HT is off these events can only run on the bottom 4 counters 149 * When HT is on, they are impacted by the HT bug and require EXCL access 150 */ 151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 155 156 EVENT_CONSTRAINT_END 157 }; 158 159 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 160 { 161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 165 EVENT_EXTRA_END 166 }; 167 168 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 169 { 170 EVENT_CONSTRAINT_END 171 }; 172 173 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 174 { 175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 178 EVENT_CONSTRAINT_END 179 }; 180 181 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 182 { 183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 186 EVENT_CONSTRAINT_END 187 }; 188 189 static struct event_constraint intel_skl_event_constraints[] = { 190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 194 195 /* 196 * when HT is off, these can only run on the bottom 4 counters 197 */ 198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 203 204 EVENT_CONSTRAINT_END 205 }; 206 207 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 210 EVENT_EXTRA_END 211 }; 212 213 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 218 EVENT_EXTRA_END 219 }; 220 221 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 226 EVENT_EXTRA_END 227 }; 228 229 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 233 /* 234 * Note the low 8 bits eventsel code is not a continuous field, containing 235 * some #GPing bits. These are masked out. 236 */ 237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 238 EVENT_EXTRA_END 239 }; 240 241 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 242 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 243 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 244 245 static struct attribute *nhm_events_attrs[] = { 246 EVENT_PTR(mem_ld_nhm), 247 NULL, 248 }; 249 250 /* 251 * topdown events for Intel Core CPUs. 252 * 253 * The events are all in slots, which is a free slot in a 4 wide 254 * pipeline. Some events are already reported in slots, for cycle 255 * events we multiply by the pipeline width (4). 256 * 257 * With Hyper Threading on, topdown metrics are either summed or averaged 258 * between the threads of a core: (count_t0 + count_t1). 259 * 260 * For the average case the metric is always scaled to pipeline width, 261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 262 */ 263 264 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 267 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 268 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 269 "event=0xe,umask=0x1"); /* uops_issued.any */ 270 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 272 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 274 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 277 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 278 "4", "2"); 279 280 static struct attribute *snb_events_attrs[] = { 281 EVENT_PTR(mem_ld_snb), 282 EVENT_PTR(mem_st_snb), 283 EVENT_PTR(td_slots_issued), 284 EVENT_PTR(td_slots_retired), 285 EVENT_PTR(td_fetch_bubbles), 286 EVENT_PTR(td_total_slots), 287 EVENT_PTR(td_total_slots_scale), 288 EVENT_PTR(td_recovery_bubbles), 289 EVENT_PTR(td_recovery_bubbles_scale), 290 NULL, 291 }; 292 293 static struct event_constraint intel_hsw_event_constraints[] = { 294 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 295 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 296 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 300 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 302 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 304 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 306 307 /* 308 * When HT is off these events can only run on the bottom 4 counters 309 * When HT is on, they are impacted by the HT bug and require EXCL access 310 */ 311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 315 316 EVENT_CONSTRAINT_END 317 }; 318 319 static struct event_constraint intel_bdw_event_constraints[] = { 320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 321 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 322 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 325 /* 326 * when HT is off, these can only run on the bottom 4 counters 327 */ 328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 332 EVENT_CONSTRAINT_END 333 }; 334 335 static u64 intel_pmu_event_map(int hw_event) 336 { 337 return intel_perfmon_event_map[hw_event]; 338 } 339 340 /* 341 * Notes on the events: 342 * - data reads do not include code reads (comparable to earlier tables) 343 * - data counts include speculative execution (except L1 write, dtlb, bpu) 344 * - remote node access includes remote memory, remote cache, remote mmio. 345 * - prefetches are not included in the counts. 346 * - icache miss does not include decoded icache 347 */ 348 349 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 350 #define SKL_DEMAND_RFO BIT_ULL(1) 351 #define SKL_ANY_RESPONSE BIT_ULL(16) 352 #define SKL_SUPPLIER_NONE BIT_ULL(17) 353 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 354 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 355 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 356 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 357 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 360 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 361 #define SKL_SPL_HIT BIT_ULL(30) 362 #define SKL_SNOOP_NONE BIT_ULL(31) 363 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 364 #define SKL_SNOOP_MISS BIT_ULL(33) 365 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 366 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 367 #define SKL_SNOOP_HITM BIT_ULL(36) 368 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 369 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 373 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 374 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 377 SKL_SNOOP_HITM|SKL_SPL_HIT) 378 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 379 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 380 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 382 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 383 384 static __initconst const u64 skl_hw_cache_event_ids 385 [PERF_COUNT_HW_CACHE_MAX] 386 [PERF_COUNT_HW_CACHE_OP_MAX] 387 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 388 { 389 [ C(L1D ) ] = { 390 [ C(OP_READ) ] = { 391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 393 }, 394 [ C(OP_WRITE) ] = { 395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 396 [ C(RESULT_MISS) ] = 0x0, 397 }, 398 [ C(OP_PREFETCH) ] = { 399 [ C(RESULT_ACCESS) ] = 0x0, 400 [ C(RESULT_MISS) ] = 0x0, 401 }, 402 }, 403 [ C(L1I ) ] = { 404 [ C(OP_READ) ] = { 405 [ C(RESULT_ACCESS) ] = 0x0, 406 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 407 }, 408 [ C(OP_WRITE) ] = { 409 [ C(RESULT_ACCESS) ] = -1, 410 [ C(RESULT_MISS) ] = -1, 411 }, 412 [ C(OP_PREFETCH) ] = { 413 [ C(RESULT_ACCESS) ] = 0x0, 414 [ C(RESULT_MISS) ] = 0x0, 415 }, 416 }, 417 [ C(LL ) ] = { 418 [ C(OP_READ) ] = { 419 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 420 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 421 }, 422 [ C(OP_WRITE) ] = { 423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 425 }, 426 [ C(OP_PREFETCH) ] = { 427 [ C(RESULT_ACCESS) ] = 0x0, 428 [ C(RESULT_MISS) ] = 0x0, 429 }, 430 }, 431 [ C(DTLB) ] = { 432 [ C(OP_READ) ] = { 433 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 434 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 435 }, 436 [ C(OP_WRITE) ] = { 437 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 438 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 439 }, 440 [ C(OP_PREFETCH) ] = { 441 [ C(RESULT_ACCESS) ] = 0x0, 442 [ C(RESULT_MISS) ] = 0x0, 443 }, 444 }, 445 [ C(ITLB) ] = { 446 [ C(OP_READ) ] = { 447 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 448 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 449 }, 450 [ C(OP_WRITE) ] = { 451 [ C(RESULT_ACCESS) ] = -1, 452 [ C(RESULT_MISS) ] = -1, 453 }, 454 [ C(OP_PREFETCH) ] = { 455 [ C(RESULT_ACCESS) ] = -1, 456 [ C(RESULT_MISS) ] = -1, 457 }, 458 }, 459 [ C(BPU ) ] = { 460 [ C(OP_READ) ] = { 461 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 462 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 463 }, 464 [ C(OP_WRITE) ] = { 465 [ C(RESULT_ACCESS) ] = -1, 466 [ C(RESULT_MISS) ] = -1, 467 }, 468 [ C(OP_PREFETCH) ] = { 469 [ C(RESULT_ACCESS) ] = -1, 470 [ C(RESULT_MISS) ] = -1, 471 }, 472 }, 473 [ C(NODE) ] = { 474 [ C(OP_READ) ] = { 475 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 476 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 477 }, 478 [ C(OP_WRITE) ] = { 479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 481 }, 482 [ C(OP_PREFETCH) ] = { 483 [ C(RESULT_ACCESS) ] = 0x0, 484 [ C(RESULT_MISS) ] = 0x0, 485 }, 486 }, 487 }; 488 489 static __initconst const u64 skl_hw_cache_extra_regs 490 [PERF_COUNT_HW_CACHE_MAX] 491 [PERF_COUNT_HW_CACHE_OP_MAX] 492 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 493 { 494 [ C(LL ) ] = { 495 [ C(OP_READ) ] = { 496 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 497 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 498 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 499 SKL_L3_MISS|SKL_ANY_SNOOP| 500 SKL_SUPPLIER_NONE, 501 }, 502 [ C(OP_WRITE) ] = { 503 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 504 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 505 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 506 SKL_L3_MISS|SKL_ANY_SNOOP| 507 SKL_SUPPLIER_NONE, 508 }, 509 [ C(OP_PREFETCH) ] = { 510 [ C(RESULT_ACCESS) ] = 0x0, 511 [ C(RESULT_MISS) ] = 0x0, 512 }, 513 }, 514 [ C(NODE) ] = { 515 [ C(OP_READ) ] = { 516 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 517 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 518 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 519 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 520 }, 521 [ C(OP_WRITE) ] = { 522 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 523 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 524 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 525 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 526 }, 527 [ C(OP_PREFETCH) ] = { 528 [ C(RESULT_ACCESS) ] = 0x0, 529 [ C(RESULT_MISS) ] = 0x0, 530 }, 531 }, 532 }; 533 534 #define SNB_DMND_DATA_RD (1ULL << 0) 535 #define SNB_DMND_RFO (1ULL << 1) 536 #define SNB_DMND_IFETCH (1ULL << 2) 537 #define SNB_DMND_WB (1ULL << 3) 538 #define SNB_PF_DATA_RD (1ULL << 4) 539 #define SNB_PF_RFO (1ULL << 5) 540 #define SNB_PF_IFETCH (1ULL << 6) 541 #define SNB_LLC_DATA_RD (1ULL << 7) 542 #define SNB_LLC_RFO (1ULL << 8) 543 #define SNB_LLC_IFETCH (1ULL << 9) 544 #define SNB_BUS_LOCKS (1ULL << 10) 545 #define SNB_STRM_ST (1ULL << 11) 546 #define SNB_OTHER (1ULL << 15) 547 #define SNB_RESP_ANY (1ULL << 16) 548 #define SNB_NO_SUPP (1ULL << 17) 549 #define SNB_LLC_HITM (1ULL << 18) 550 #define SNB_LLC_HITE (1ULL << 19) 551 #define SNB_LLC_HITS (1ULL << 20) 552 #define SNB_LLC_HITF (1ULL << 21) 553 #define SNB_LOCAL (1ULL << 22) 554 #define SNB_REMOTE (0xffULL << 23) 555 #define SNB_SNP_NONE (1ULL << 31) 556 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 557 #define SNB_SNP_MISS (1ULL << 33) 558 #define SNB_NO_FWD (1ULL << 34) 559 #define SNB_SNP_FWD (1ULL << 35) 560 #define SNB_HITM (1ULL << 36) 561 #define SNB_NON_DRAM (1ULL << 37) 562 563 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 564 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 565 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 566 567 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 569 SNB_HITM) 570 571 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 572 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 573 574 #define SNB_L3_ACCESS SNB_RESP_ANY 575 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 576 577 static __initconst const u64 snb_hw_cache_extra_regs 578 [PERF_COUNT_HW_CACHE_MAX] 579 [PERF_COUNT_HW_CACHE_OP_MAX] 580 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 581 { 582 [ C(LL ) ] = { 583 [ C(OP_READ) ] = { 584 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 585 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 586 }, 587 [ C(OP_WRITE) ] = { 588 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 589 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 590 }, 591 [ C(OP_PREFETCH) ] = { 592 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 593 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 594 }, 595 }, 596 [ C(NODE) ] = { 597 [ C(OP_READ) ] = { 598 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 599 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 600 }, 601 [ C(OP_WRITE) ] = { 602 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 603 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 604 }, 605 [ C(OP_PREFETCH) ] = { 606 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 607 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 608 }, 609 }, 610 }; 611 612 static __initconst const u64 snb_hw_cache_event_ids 613 [PERF_COUNT_HW_CACHE_MAX] 614 [PERF_COUNT_HW_CACHE_OP_MAX] 615 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 616 { 617 [ C(L1D) ] = { 618 [ C(OP_READ) ] = { 619 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 620 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 621 }, 622 [ C(OP_WRITE) ] = { 623 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 624 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 625 }, 626 [ C(OP_PREFETCH) ] = { 627 [ C(RESULT_ACCESS) ] = 0x0, 628 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 629 }, 630 }, 631 [ C(L1I ) ] = { 632 [ C(OP_READ) ] = { 633 [ C(RESULT_ACCESS) ] = 0x0, 634 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 635 }, 636 [ C(OP_WRITE) ] = { 637 [ C(RESULT_ACCESS) ] = -1, 638 [ C(RESULT_MISS) ] = -1, 639 }, 640 [ C(OP_PREFETCH) ] = { 641 [ C(RESULT_ACCESS) ] = 0x0, 642 [ C(RESULT_MISS) ] = 0x0, 643 }, 644 }, 645 [ C(LL ) ] = { 646 [ C(OP_READ) ] = { 647 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 648 [ C(RESULT_ACCESS) ] = 0x01b7, 649 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 650 [ C(RESULT_MISS) ] = 0x01b7, 651 }, 652 [ C(OP_WRITE) ] = { 653 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 654 [ C(RESULT_ACCESS) ] = 0x01b7, 655 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 656 [ C(RESULT_MISS) ] = 0x01b7, 657 }, 658 [ C(OP_PREFETCH) ] = { 659 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 660 [ C(RESULT_ACCESS) ] = 0x01b7, 661 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 662 [ C(RESULT_MISS) ] = 0x01b7, 663 }, 664 }, 665 [ C(DTLB) ] = { 666 [ C(OP_READ) ] = { 667 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 668 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 669 }, 670 [ C(OP_WRITE) ] = { 671 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 672 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 673 }, 674 [ C(OP_PREFETCH) ] = { 675 [ C(RESULT_ACCESS) ] = 0x0, 676 [ C(RESULT_MISS) ] = 0x0, 677 }, 678 }, 679 [ C(ITLB) ] = { 680 [ C(OP_READ) ] = { 681 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 682 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 683 }, 684 [ C(OP_WRITE) ] = { 685 [ C(RESULT_ACCESS) ] = -1, 686 [ C(RESULT_MISS) ] = -1, 687 }, 688 [ C(OP_PREFETCH) ] = { 689 [ C(RESULT_ACCESS) ] = -1, 690 [ C(RESULT_MISS) ] = -1, 691 }, 692 }, 693 [ C(BPU ) ] = { 694 [ C(OP_READ) ] = { 695 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 696 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 697 }, 698 [ C(OP_WRITE) ] = { 699 [ C(RESULT_ACCESS) ] = -1, 700 [ C(RESULT_MISS) ] = -1, 701 }, 702 [ C(OP_PREFETCH) ] = { 703 [ C(RESULT_ACCESS) ] = -1, 704 [ C(RESULT_MISS) ] = -1, 705 }, 706 }, 707 [ C(NODE) ] = { 708 [ C(OP_READ) ] = { 709 [ C(RESULT_ACCESS) ] = 0x01b7, 710 [ C(RESULT_MISS) ] = 0x01b7, 711 }, 712 [ C(OP_WRITE) ] = { 713 [ C(RESULT_ACCESS) ] = 0x01b7, 714 [ C(RESULT_MISS) ] = 0x01b7, 715 }, 716 [ C(OP_PREFETCH) ] = { 717 [ C(RESULT_ACCESS) ] = 0x01b7, 718 [ C(RESULT_MISS) ] = 0x01b7, 719 }, 720 }, 721 722 }; 723 724 /* 725 * Notes on the events: 726 * - data reads do not include code reads (comparable to earlier tables) 727 * - data counts include speculative execution (except L1 write, dtlb, bpu) 728 * - remote node access includes remote memory, remote cache, remote mmio. 729 * - prefetches are not included in the counts because they are not 730 * reliably counted. 731 */ 732 733 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 734 #define HSW_DEMAND_RFO BIT_ULL(1) 735 #define HSW_ANY_RESPONSE BIT_ULL(16) 736 #define HSW_SUPPLIER_NONE BIT_ULL(17) 737 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 738 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 739 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 740 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 741 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 743 HSW_L3_MISS_REMOTE_HOP2P) 744 #define HSW_SNOOP_NONE BIT_ULL(31) 745 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 746 #define HSW_SNOOP_MISS BIT_ULL(33) 747 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 748 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 749 #define HSW_SNOOP_HITM BIT_ULL(36) 750 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 751 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 755 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 756 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 757 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 758 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 760 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 761 762 #define BDW_L3_MISS_LOCAL BIT(26) 763 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 765 HSW_L3_MISS_REMOTE_HOP2P) 766 767 768 static __initconst const u64 hsw_hw_cache_event_ids 769 [PERF_COUNT_HW_CACHE_MAX] 770 [PERF_COUNT_HW_CACHE_OP_MAX] 771 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 772 { 773 [ C(L1D ) ] = { 774 [ C(OP_READ) ] = { 775 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 776 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 777 }, 778 [ C(OP_WRITE) ] = { 779 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 780 [ C(RESULT_MISS) ] = 0x0, 781 }, 782 [ C(OP_PREFETCH) ] = { 783 [ C(RESULT_ACCESS) ] = 0x0, 784 [ C(RESULT_MISS) ] = 0x0, 785 }, 786 }, 787 [ C(L1I ) ] = { 788 [ C(OP_READ) ] = { 789 [ C(RESULT_ACCESS) ] = 0x0, 790 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 791 }, 792 [ C(OP_WRITE) ] = { 793 [ C(RESULT_ACCESS) ] = -1, 794 [ C(RESULT_MISS) ] = -1, 795 }, 796 [ C(OP_PREFETCH) ] = { 797 [ C(RESULT_ACCESS) ] = 0x0, 798 [ C(RESULT_MISS) ] = 0x0, 799 }, 800 }, 801 [ C(LL ) ] = { 802 [ C(OP_READ) ] = { 803 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 804 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 805 }, 806 [ C(OP_WRITE) ] = { 807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 809 }, 810 [ C(OP_PREFETCH) ] = { 811 [ C(RESULT_ACCESS) ] = 0x0, 812 [ C(RESULT_MISS) ] = 0x0, 813 }, 814 }, 815 [ C(DTLB) ] = { 816 [ C(OP_READ) ] = { 817 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 818 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 819 }, 820 [ C(OP_WRITE) ] = { 821 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 822 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 823 }, 824 [ C(OP_PREFETCH) ] = { 825 [ C(RESULT_ACCESS) ] = 0x0, 826 [ C(RESULT_MISS) ] = 0x0, 827 }, 828 }, 829 [ C(ITLB) ] = { 830 [ C(OP_READ) ] = { 831 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 832 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 833 }, 834 [ C(OP_WRITE) ] = { 835 [ C(RESULT_ACCESS) ] = -1, 836 [ C(RESULT_MISS) ] = -1, 837 }, 838 [ C(OP_PREFETCH) ] = { 839 [ C(RESULT_ACCESS) ] = -1, 840 [ C(RESULT_MISS) ] = -1, 841 }, 842 }, 843 [ C(BPU ) ] = { 844 [ C(OP_READ) ] = { 845 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 846 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 847 }, 848 [ C(OP_WRITE) ] = { 849 [ C(RESULT_ACCESS) ] = -1, 850 [ C(RESULT_MISS) ] = -1, 851 }, 852 [ C(OP_PREFETCH) ] = { 853 [ C(RESULT_ACCESS) ] = -1, 854 [ C(RESULT_MISS) ] = -1, 855 }, 856 }, 857 [ C(NODE) ] = { 858 [ C(OP_READ) ] = { 859 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 860 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 861 }, 862 [ C(OP_WRITE) ] = { 863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 865 }, 866 [ C(OP_PREFETCH) ] = { 867 [ C(RESULT_ACCESS) ] = 0x0, 868 [ C(RESULT_MISS) ] = 0x0, 869 }, 870 }, 871 }; 872 873 static __initconst const u64 hsw_hw_cache_extra_regs 874 [PERF_COUNT_HW_CACHE_MAX] 875 [PERF_COUNT_HW_CACHE_OP_MAX] 876 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 877 { 878 [ C(LL ) ] = { 879 [ C(OP_READ) ] = { 880 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 881 HSW_LLC_ACCESS, 882 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 883 HSW_L3_MISS|HSW_ANY_SNOOP, 884 }, 885 [ C(OP_WRITE) ] = { 886 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 887 HSW_LLC_ACCESS, 888 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 889 HSW_L3_MISS|HSW_ANY_SNOOP, 890 }, 891 [ C(OP_PREFETCH) ] = { 892 [ C(RESULT_ACCESS) ] = 0x0, 893 [ C(RESULT_MISS) ] = 0x0, 894 }, 895 }, 896 [ C(NODE) ] = { 897 [ C(OP_READ) ] = { 898 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 899 HSW_L3_MISS_LOCAL_DRAM| 900 HSW_SNOOP_DRAM, 901 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 902 HSW_L3_MISS_REMOTE| 903 HSW_SNOOP_DRAM, 904 }, 905 [ C(OP_WRITE) ] = { 906 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 907 HSW_L3_MISS_LOCAL_DRAM| 908 HSW_SNOOP_DRAM, 909 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 910 HSW_L3_MISS_REMOTE| 911 HSW_SNOOP_DRAM, 912 }, 913 [ C(OP_PREFETCH) ] = { 914 [ C(RESULT_ACCESS) ] = 0x0, 915 [ C(RESULT_MISS) ] = 0x0, 916 }, 917 }, 918 }; 919 920 static __initconst const u64 westmere_hw_cache_event_ids 921 [PERF_COUNT_HW_CACHE_MAX] 922 [PERF_COUNT_HW_CACHE_OP_MAX] 923 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 924 { 925 [ C(L1D) ] = { 926 [ C(OP_READ) ] = { 927 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 929 }, 930 [ C(OP_WRITE) ] = { 931 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 932 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 933 }, 934 [ C(OP_PREFETCH) ] = { 935 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 936 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 937 }, 938 }, 939 [ C(L1I ) ] = { 940 [ C(OP_READ) ] = { 941 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 942 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 943 }, 944 [ C(OP_WRITE) ] = { 945 [ C(RESULT_ACCESS) ] = -1, 946 [ C(RESULT_MISS) ] = -1, 947 }, 948 [ C(OP_PREFETCH) ] = { 949 [ C(RESULT_ACCESS) ] = 0x0, 950 [ C(RESULT_MISS) ] = 0x0, 951 }, 952 }, 953 [ C(LL ) ] = { 954 [ C(OP_READ) ] = { 955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 956 [ C(RESULT_ACCESS) ] = 0x01b7, 957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 958 [ C(RESULT_MISS) ] = 0x01b7, 959 }, 960 /* 961 * Use RFO, not WRITEBACK, because a write miss would typically occur 962 * on RFO. 963 */ 964 [ C(OP_WRITE) ] = { 965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 966 [ C(RESULT_ACCESS) ] = 0x01b7, 967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 968 [ C(RESULT_MISS) ] = 0x01b7, 969 }, 970 [ C(OP_PREFETCH) ] = { 971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 972 [ C(RESULT_ACCESS) ] = 0x01b7, 973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 974 [ C(RESULT_MISS) ] = 0x01b7, 975 }, 976 }, 977 [ C(DTLB) ] = { 978 [ C(OP_READ) ] = { 979 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 981 }, 982 [ C(OP_WRITE) ] = { 983 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 984 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 985 }, 986 [ C(OP_PREFETCH) ] = { 987 [ C(RESULT_ACCESS) ] = 0x0, 988 [ C(RESULT_MISS) ] = 0x0, 989 }, 990 }, 991 [ C(ITLB) ] = { 992 [ C(OP_READ) ] = { 993 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 995 }, 996 [ C(OP_WRITE) ] = { 997 [ C(RESULT_ACCESS) ] = -1, 998 [ C(RESULT_MISS) ] = -1, 999 }, 1000 [ C(OP_PREFETCH) ] = { 1001 [ C(RESULT_ACCESS) ] = -1, 1002 [ C(RESULT_MISS) ] = -1, 1003 }, 1004 }, 1005 [ C(BPU ) ] = { 1006 [ C(OP_READ) ] = { 1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1008 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1009 }, 1010 [ C(OP_WRITE) ] = { 1011 [ C(RESULT_ACCESS) ] = -1, 1012 [ C(RESULT_MISS) ] = -1, 1013 }, 1014 [ C(OP_PREFETCH) ] = { 1015 [ C(RESULT_ACCESS) ] = -1, 1016 [ C(RESULT_MISS) ] = -1, 1017 }, 1018 }, 1019 [ C(NODE) ] = { 1020 [ C(OP_READ) ] = { 1021 [ C(RESULT_ACCESS) ] = 0x01b7, 1022 [ C(RESULT_MISS) ] = 0x01b7, 1023 }, 1024 [ C(OP_WRITE) ] = { 1025 [ C(RESULT_ACCESS) ] = 0x01b7, 1026 [ C(RESULT_MISS) ] = 0x01b7, 1027 }, 1028 [ C(OP_PREFETCH) ] = { 1029 [ C(RESULT_ACCESS) ] = 0x01b7, 1030 [ C(RESULT_MISS) ] = 0x01b7, 1031 }, 1032 }, 1033 }; 1034 1035 /* 1036 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1037 * See IA32 SDM Vol 3B 30.6.1.3 1038 */ 1039 1040 #define NHM_DMND_DATA_RD (1 << 0) 1041 #define NHM_DMND_RFO (1 << 1) 1042 #define NHM_DMND_IFETCH (1 << 2) 1043 #define NHM_DMND_WB (1 << 3) 1044 #define NHM_PF_DATA_RD (1 << 4) 1045 #define NHM_PF_DATA_RFO (1 << 5) 1046 #define NHM_PF_IFETCH (1 << 6) 1047 #define NHM_OFFCORE_OTHER (1 << 7) 1048 #define NHM_UNCORE_HIT (1 << 8) 1049 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1050 #define NHM_OTHER_CORE_HITM (1 << 10) 1051 /* reserved */ 1052 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1053 #define NHM_REMOTE_DRAM (1 << 13) 1054 #define NHM_LOCAL_DRAM (1 << 14) 1055 #define NHM_NON_DRAM (1 << 15) 1056 1057 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1058 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1059 1060 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1061 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1062 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1063 1064 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1065 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1066 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1067 1068 static __initconst const u64 nehalem_hw_cache_extra_regs 1069 [PERF_COUNT_HW_CACHE_MAX] 1070 [PERF_COUNT_HW_CACHE_OP_MAX] 1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1072 { 1073 [ C(LL ) ] = { 1074 [ C(OP_READ) ] = { 1075 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1076 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1077 }, 1078 [ C(OP_WRITE) ] = { 1079 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1080 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1081 }, 1082 [ C(OP_PREFETCH) ] = { 1083 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1084 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1085 }, 1086 }, 1087 [ C(NODE) ] = { 1088 [ C(OP_READ) ] = { 1089 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1090 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1091 }, 1092 [ C(OP_WRITE) ] = { 1093 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1094 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1095 }, 1096 [ C(OP_PREFETCH) ] = { 1097 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1098 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1099 }, 1100 }, 1101 }; 1102 1103 static __initconst const u64 nehalem_hw_cache_event_ids 1104 [PERF_COUNT_HW_CACHE_MAX] 1105 [PERF_COUNT_HW_CACHE_OP_MAX] 1106 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1107 { 1108 [ C(L1D) ] = { 1109 [ C(OP_READ) ] = { 1110 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1111 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1112 }, 1113 [ C(OP_WRITE) ] = { 1114 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1115 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1116 }, 1117 [ C(OP_PREFETCH) ] = { 1118 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1119 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1120 }, 1121 }, 1122 [ C(L1I ) ] = { 1123 [ C(OP_READ) ] = { 1124 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1125 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1126 }, 1127 [ C(OP_WRITE) ] = { 1128 [ C(RESULT_ACCESS) ] = -1, 1129 [ C(RESULT_MISS) ] = -1, 1130 }, 1131 [ C(OP_PREFETCH) ] = { 1132 [ C(RESULT_ACCESS) ] = 0x0, 1133 [ C(RESULT_MISS) ] = 0x0, 1134 }, 1135 }, 1136 [ C(LL ) ] = { 1137 [ C(OP_READ) ] = { 1138 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1139 [ C(RESULT_ACCESS) ] = 0x01b7, 1140 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1141 [ C(RESULT_MISS) ] = 0x01b7, 1142 }, 1143 /* 1144 * Use RFO, not WRITEBACK, because a write miss would typically occur 1145 * on RFO. 1146 */ 1147 [ C(OP_WRITE) ] = { 1148 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1149 [ C(RESULT_ACCESS) ] = 0x01b7, 1150 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1151 [ C(RESULT_MISS) ] = 0x01b7, 1152 }, 1153 [ C(OP_PREFETCH) ] = { 1154 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1155 [ C(RESULT_ACCESS) ] = 0x01b7, 1156 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1157 [ C(RESULT_MISS) ] = 0x01b7, 1158 }, 1159 }, 1160 [ C(DTLB) ] = { 1161 [ C(OP_READ) ] = { 1162 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1163 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1164 }, 1165 [ C(OP_WRITE) ] = { 1166 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1167 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1168 }, 1169 [ C(OP_PREFETCH) ] = { 1170 [ C(RESULT_ACCESS) ] = 0x0, 1171 [ C(RESULT_MISS) ] = 0x0, 1172 }, 1173 }, 1174 [ C(ITLB) ] = { 1175 [ C(OP_READ) ] = { 1176 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1177 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1178 }, 1179 [ C(OP_WRITE) ] = { 1180 [ C(RESULT_ACCESS) ] = -1, 1181 [ C(RESULT_MISS) ] = -1, 1182 }, 1183 [ C(OP_PREFETCH) ] = { 1184 [ C(RESULT_ACCESS) ] = -1, 1185 [ C(RESULT_MISS) ] = -1, 1186 }, 1187 }, 1188 [ C(BPU ) ] = { 1189 [ C(OP_READ) ] = { 1190 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1191 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1192 }, 1193 [ C(OP_WRITE) ] = { 1194 [ C(RESULT_ACCESS) ] = -1, 1195 [ C(RESULT_MISS) ] = -1, 1196 }, 1197 [ C(OP_PREFETCH) ] = { 1198 [ C(RESULT_ACCESS) ] = -1, 1199 [ C(RESULT_MISS) ] = -1, 1200 }, 1201 }, 1202 [ C(NODE) ] = { 1203 [ C(OP_READ) ] = { 1204 [ C(RESULT_ACCESS) ] = 0x01b7, 1205 [ C(RESULT_MISS) ] = 0x01b7, 1206 }, 1207 [ C(OP_WRITE) ] = { 1208 [ C(RESULT_ACCESS) ] = 0x01b7, 1209 [ C(RESULT_MISS) ] = 0x01b7, 1210 }, 1211 [ C(OP_PREFETCH) ] = { 1212 [ C(RESULT_ACCESS) ] = 0x01b7, 1213 [ C(RESULT_MISS) ] = 0x01b7, 1214 }, 1215 }, 1216 }; 1217 1218 static __initconst const u64 core2_hw_cache_event_ids 1219 [PERF_COUNT_HW_CACHE_MAX] 1220 [PERF_COUNT_HW_CACHE_OP_MAX] 1221 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1222 { 1223 [ C(L1D) ] = { 1224 [ C(OP_READ) ] = { 1225 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1226 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1227 }, 1228 [ C(OP_WRITE) ] = { 1229 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1230 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1231 }, 1232 [ C(OP_PREFETCH) ] = { 1233 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1234 [ C(RESULT_MISS) ] = 0, 1235 }, 1236 }, 1237 [ C(L1I ) ] = { 1238 [ C(OP_READ) ] = { 1239 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1240 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1241 }, 1242 [ C(OP_WRITE) ] = { 1243 [ C(RESULT_ACCESS) ] = -1, 1244 [ C(RESULT_MISS) ] = -1, 1245 }, 1246 [ C(OP_PREFETCH) ] = { 1247 [ C(RESULT_ACCESS) ] = 0, 1248 [ C(RESULT_MISS) ] = 0, 1249 }, 1250 }, 1251 [ C(LL ) ] = { 1252 [ C(OP_READ) ] = { 1253 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1254 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1255 }, 1256 [ C(OP_WRITE) ] = { 1257 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1258 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1259 }, 1260 [ C(OP_PREFETCH) ] = { 1261 [ C(RESULT_ACCESS) ] = 0, 1262 [ C(RESULT_MISS) ] = 0, 1263 }, 1264 }, 1265 [ C(DTLB) ] = { 1266 [ C(OP_READ) ] = { 1267 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1268 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1269 }, 1270 [ C(OP_WRITE) ] = { 1271 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1272 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1273 }, 1274 [ C(OP_PREFETCH) ] = { 1275 [ C(RESULT_ACCESS) ] = 0, 1276 [ C(RESULT_MISS) ] = 0, 1277 }, 1278 }, 1279 [ C(ITLB) ] = { 1280 [ C(OP_READ) ] = { 1281 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1282 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1283 }, 1284 [ C(OP_WRITE) ] = { 1285 [ C(RESULT_ACCESS) ] = -1, 1286 [ C(RESULT_MISS) ] = -1, 1287 }, 1288 [ C(OP_PREFETCH) ] = { 1289 [ C(RESULT_ACCESS) ] = -1, 1290 [ C(RESULT_MISS) ] = -1, 1291 }, 1292 }, 1293 [ C(BPU ) ] = { 1294 [ C(OP_READ) ] = { 1295 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1296 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1297 }, 1298 [ C(OP_WRITE) ] = { 1299 [ C(RESULT_ACCESS) ] = -1, 1300 [ C(RESULT_MISS) ] = -1, 1301 }, 1302 [ C(OP_PREFETCH) ] = { 1303 [ C(RESULT_ACCESS) ] = -1, 1304 [ C(RESULT_MISS) ] = -1, 1305 }, 1306 }, 1307 }; 1308 1309 static __initconst const u64 atom_hw_cache_event_ids 1310 [PERF_COUNT_HW_CACHE_MAX] 1311 [PERF_COUNT_HW_CACHE_OP_MAX] 1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1313 { 1314 [ C(L1D) ] = { 1315 [ C(OP_READ) ] = { 1316 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1317 [ C(RESULT_MISS) ] = 0, 1318 }, 1319 [ C(OP_WRITE) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1321 [ C(RESULT_MISS) ] = 0, 1322 }, 1323 [ C(OP_PREFETCH) ] = { 1324 [ C(RESULT_ACCESS) ] = 0x0, 1325 [ C(RESULT_MISS) ] = 0, 1326 }, 1327 }, 1328 [ C(L1I ) ] = { 1329 [ C(OP_READ) ] = { 1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1332 }, 1333 [ C(OP_WRITE) ] = { 1334 [ C(RESULT_ACCESS) ] = -1, 1335 [ C(RESULT_MISS) ] = -1, 1336 }, 1337 [ C(OP_PREFETCH) ] = { 1338 [ C(RESULT_ACCESS) ] = 0, 1339 [ C(RESULT_MISS) ] = 0, 1340 }, 1341 }, 1342 [ C(LL ) ] = { 1343 [ C(OP_READ) ] = { 1344 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1345 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1346 }, 1347 [ C(OP_WRITE) ] = { 1348 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1349 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1350 }, 1351 [ C(OP_PREFETCH) ] = { 1352 [ C(RESULT_ACCESS) ] = 0, 1353 [ C(RESULT_MISS) ] = 0, 1354 }, 1355 }, 1356 [ C(DTLB) ] = { 1357 [ C(OP_READ) ] = { 1358 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1359 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1360 }, 1361 [ C(OP_WRITE) ] = { 1362 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1363 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1364 }, 1365 [ C(OP_PREFETCH) ] = { 1366 [ C(RESULT_ACCESS) ] = 0, 1367 [ C(RESULT_MISS) ] = 0, 1368 }, 1369 }, 1370 [ C(ITLB) ] = { 1371 [ C(OP_READ) ] = { 1372 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1373 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1374 }, 1375 [ C(OP_WRITE) ] = { 1376 [ C(RESULT_ACCESS) ] = -1, 1377 [ C(RESULT_MISS) ] = -1, 1378 }, 1379 [ C(OP_PREFETCH) ] = { 1380 [ C(RESULT_ACCESS) ] = -1, 1381 [ C(RESULT_MISS) ] = -1, 1382 }, 1383 }, 1384 [ C(BPU ) ] = { 1385 [ C(OP_READ) ] = { 1386 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1387 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1388 }, 1389 [ C(OP_WRITE) ] = { 1390 [ C(RESULT_ACCESS) ] = -1, 1391 [ C(RESULT_MISS) ] = -1, 1392 }, 1393 [ C(OP_PREFETCH) ] = { 1394 [ C(RESULT_ACCESS) ] = -1, 1395 [ C(RESULT_MISS) ] = -1, 1396 }, 1397 }, 1398 }; 1399 1400 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1401 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1402 /* no_alloc_cycles.not_delivered */ 1403 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1404 "event=0xca,umask=0x50"); 1405 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1406 /* uops_retired.all */ 1407 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1408 "event=0xc2,umask=0x10"); 1409 /* uops_retired.all */ 1410 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1411 "event=0xc2,umask=0x10"); 1412 1413 static struct attribute *slm_events_attrs[] = { 1414 EVENT_PTR(td_total_slots_slm), 1415 EVENT_PTR(td_total_slots_scale_slm), 1416 EVENT_PTR(td_fetch_bubbles_slm), 1417 EVENT_PTR(td_fetch_bubbles_scale_slm), 1418 EVENT_PTR(td_slots_issued_slm), 1419 EVENT_PTR(td_slots_retired_slm), 1420 NULL 1421 }; 1422 1423 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1424 { 1425 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1428 EVENT_EXTRA_END 1429 }; 1430 1431 #define SLM_DMND_READ SNB_DMND_DATA_RD 1432 #define SLM_DMND_WRITE SNB_DMND_RFO 1433 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1434 1435 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1436 #define SLM_LLC_ACCESS SNB_RESP_ANY 1437 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1438 1439 static __initconst const u64 slm_hw_cache_extra_regs 1440 [PERF_COUNT_HW_CACHE_MAX] 1441 [PERF_COUNT_HW_CACHE_OP_MAX] 1442 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1443 { 1444 [ C(LL ) ] = { 1445 [ C(OP_READ) ] = { 1446 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1447 [ C(RESULT_MISS) ] = 0, 1448 }, 1449 [ C(OP_WRITE) ] = { 1450 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1451 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1452 }, 1453 [ C(OP_PREFETCH) ] = { 1454 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1455 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1456 }, 1457 }, 1458 }; 1459 1460 static __initconst const u64 slm_hw_cache_event_ids 1461 [PERF_COUNT_HW_CACHE_MAX] 1462 [PERF_COUNT_HW_CACHE_OP_MAX] 1463 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1464 { 1465 [ C(L1D) ] = { 1466 [ C(OP_READ) ] = { 1467 [ C(RESULT_ACCESS) ] = 0, 1468 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1469 }, 1470 [ C(OP_WRITE) ] = { 1471 [ C(RESULT_ACCESS) ] = 0, 1472 [ C(RESULT_MISS) ] = 0, 1473 }, 1474 [ C(OP_PREFETCH) ] = { 1475 [ C(RESULT_ACCESS) ] = 0, 1476 [ C(RESULT_MISS) ] = 0, 1477 }, 1478 }, 1479 [ C(L1I ) ] = { 1480 [ C(OP_READ) ] = { 1481 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1482 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1483 }, 1484 [ C(OP_WRITE) ] = { 1485 [ C(RESULT_ACCESS) ] = -1, 1486 [ C(RESULT_MISS) ] = -1, 1487 }, 1488 [ C(OP_PREFETCH) ] = { 1489 [ C(RESULT_ACCESS) ] = 0, 1490 [ C(RESULT_MISS) ] = 0, 1491 }, 1492 }, 1493 [ C(LL ) ] = { 1494 [ C(OP_READ) ] = { 1495 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1496 [ C(RESULT_ACCESS) ] = 0x01b7, 1497 [ C(RESULT_MISS) ] = 0, 1498 }, 1499 [ C(OP_WRITE) ] = { 1500 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1501 [ C(RESULT_ACCESS) ] = 0x01b7, 1502 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1503 [ C(RESULT_MISS) ] = 0x01b7, 1504 }, 1505 [ C(OP_PREFETCH) ] = { 1506 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1507 [ C(RESULT_ACCESS) ] = 0x01b7, 1508 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1509 [ C(RESULT_MISS) ] = 0x01b7, 1510 }, 1511 }, 1512 [ C(DTLB) ] = { 1513 [ C(OP_READ) ] = { 1514 [ C(RESULT_ACCESS) ] = 0, 1515 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1516 }, 1517 [ C(OP_WRITE) ] = { 1518 [ C(RESULT_ACCESS) ] = 0, 1519 [ C(RESULT_MISS) ] = 0, 1520 }, 1521 [ C(OP_PREFETCH) ] = { 1522 [ C(RESULT_ACCESS) ] = 0, 1523 [ C(RESULT_MISS) ] = 0, 1524 }, 1525 }, 1526 [ C(ITLB) ] = { 1527 [ C(OP_READ) ] = { 1528 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1529 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1530 }, 1531 [ C(OP_WRITE) ] = { 1532 [ C(RESULT_ACCESS) ] = -1, 1533 [ C(RESULT_MISS) ] = -1, 1534 }, 1535 [ C(OP_PREFETCH) ] = { 1536 [ C(RESULT_ACCESS) ] = -1, 1537 [ C(RESULT_MISS) ] = -1, 1538 }, 1539 }, 1540 [ C(BPU ) ] = { 1541 [ C(OP_READ) ] = { 1542 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1543 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1544 }, 1545 [ C(OP_WRITE) ] = { 1546 [ C(RESULT_ACCESS) ] = -1, 1547 [ C(RESULT_MISS) ] = -1, 1548 }, 1549 [ C(OP_PREFETCH) ] = { 1550 [ C(RESULT_ACCESS) ] = -1, 1551 [ C(RESULT_MISS) ] = -1, 1552 }, 1553 }, 1554 }; 1555 1556 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1557 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1558 /* UOPS_NOT_DELIVERED.ANY */ 1559 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1560 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1561 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1562 /* UOPS_RETIRED.ANY */ 1563 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1564 /* UOPS_ISSUED.ANY */ 1565 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1566 1567 static struct attribute *glm_events_attrs[] = { 1568 EVENT_PTR(td_total_slots_glm), 1569 EVENT_PTR(td_total_slots_scale_glm), 1570 EVENT_PTR(td_fetch_bubbles_glm), 1571 EVENT_PTR(td_recovery_bubbles_glm), 1572 EVENT_PTR(td_slots_issued_glm), 1573 EVENT_PTR(td_slots_retired_glm), 1574 NULL 1575 }; 1576 1577 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1578 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1579 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1580 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1581 EVENT_EXTRA_END 1582 }; 1583 1584 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1585 #define GLM_DEMAND_RFO BIT_ULL(1) 1586 #define GLM_ANY_RESPONSE BIT_ULL(16) 1587 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1588 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1589 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1590 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1591 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1592 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1593 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1594 1595 static __initconst const u64 glm_hw_cache_event_ids 1596 [PERF_COUNT_HW_CACHE_MAX] 1597 [PERF_COUNT_HW_CACHE_OP_MAX] 1598 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1599 [C(L1D)] = { 1600 [C(OP_READ)] = { 1601 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1602 [C(RESULT_MISS)] = 0x0, 1603 }, 1604 [C(OP_WRITE)] = { 1605 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1606 [C(RESULT_MISS)] = 0x0, 1607 }, 1608 [C(OP_PREFETCH)] = { 1609 [C(RESULT_ACCESS)] = 0x0, 1610 [C(RESULT_MISS)] = 0x0, 1611 }, 1612 }, 1613 [C(L1I)] = { 1614 [C(OP_READ)] = { 1615 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1616 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1617 }, 1618 [C(OP_WRITE)] = { 1619 [C(RESULT_ACCESS)] = -1, 1620 [C(RESULT_MISS)] = -1, 1621 }, 1622 [C(OP_PREFETCH)] = { 1623 [C(RESULT_ACCESS)] = 0x0, 1624 [C(RESULT_MISS)] = 0x0, 1625 }, 1626 }, 1627 [C(LL)] = { 1628 [C(OP_READ)] = { 1629 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1630 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1631 }, 1632 [C(OP_WRITE)] = { 1633 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1634 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1635 }, 1636 [C(OP_PREFETCH)] = { 1637 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1638 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1639 }, 1640 }, 1641 [C(DTLB)] = { 1642 [C(OP_READ)] = { 1643 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1644 [C(RESULT_MISS)] = 0x0, 1645 }, 1646 [C(OP_WRITE)] = { 1647 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1648 [C(RESULT_MISS)] = 0x0, 1649 }, 1650 [C(OP_PREFETCH)] = { 1651 [C(RESULT_ACCESS)] = 0x0, 1652 [C(RESULT_MISS)] = 0x0, 1653 }, 1654 }, 1655 [C(ITLB)] = { 1656 [C(OP_READ)] = { 1657 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1658 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1659 }, 1660 [C(OP_WRITE)] = { 1661 [C(RESULT_ACCESS)] = -1, 1662 [C(RESULT_MISS)] = -1, 1663 }, 1664 [C(OP_PREFETCH)] = { 1665 [C(RESULT_ACCESS)] = -1, 1666 [C(RESULT_MISS)] = -1, 1667 }, 1668 }, 1669 [C(BPU)] = { 1670 [C(OP_READ)] = { 1671 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1672 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1673 }, 1674 [C(OP_WRITE)] = { 1675 [C(RESULT_ACCESS)] = -1, 1676 [C(RESULT_MISS)] = -1, 1677 }, 1678 [C(OP_PREFETCH)] = { 1679 [C(RESULT_ACCESS)] = -1, 1680 [C(RESULT_MISS)] = -1, 1681 }, 1682 }, 1683 }; 1684 1685 static __initconst const u64 glm_hw_cache_extra_regs 1686 [PERF_COUNT_HW_CACHE_MAX] 1687 [PERF_COUNT_HW_CACHE_OP_MAX] 1688 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1689 [C(LL)] = { 1690 [C(OP_READ)] = { 1691 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1692 GLM_LLC_ACCESS, 1693 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1694 GLM_LLC_MISS, 1695 }, 1696 [C(OP_WRITE)] = { 1697 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1698 GLM_LLC_ACCESS, 1699 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1700 GLM_LLC_MISS, 1701 }, 1702 [C(OP_PREFETCH)] = { 1703 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1704 GLM_LLC_ACCESS, 1705 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1706 GLM_LLC_MISS, 1707 }, 1708 }, 1709 }; 1710 1711 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1712 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1713 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1714 #define KNL_MCDRAM_FAR BIT_ULL(22) 1715 #define KNL_DDR_LOCAL BIT_ULL(23) 1716 #define KNL_DDR_FAR BIT_ULL(24) 1717 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1718 KNL_DDR_LOCAL | KNL_DDR_FAR) 1719 #define KNL_L2_READ SLM_DMND_READ 1720 #define KNL_L2_WRITE SLM_DMND_WRITE 1721 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1722 #define KNL_L2_ACCESS SLM_LLC_ACCESS 1723 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1724 KNL_DRAM_ANY | SNB_SNP_ANY | \ 1725 SNB_NON_DRAM) 1726 1727 static __initconst const u64 knl_hw_cache_extra_regs 1728 [PERF_COUNT_HW_CACHE_MAX] 1729 [PERF_COUNT_HW_CACHE_OP_MAX] 1730 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1731 [C(LL)] = { 1732 [C(OP_READ)] = { 1733 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1734 [C(RESULT_MISS)] = 0, 1735 }, 1736 [C(OP_WRITE)] = { 1737 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1738 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1739 }, 1740 [C(OP_PREFETCH)] = { 1741 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1742 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1743 }, 1744 }, 1745 }; 1746 1747 /* 1748 * Used from PMIs where the LBRs are already disabled. 1749 * 1750 * This function could be called consecutively. It is required to remain in 1751 * disabled state if called consecutively. 1752 * 1753 * During consecutive calls, the same disable value will be written to related 1754 * registers, so the PMU state remains unchanged. 1755 * 1756 * intel_bts events don't coexist with intel PMU's BTS events because of 1757 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1758 * disabled around intel PMU's event batching etc, only inside the PMI handler. 1759 */ 1760 static void __intel_pmu_disable_all(void) 1761 { 1762 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1763 1764 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1765 1766 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1767 intel_pmu_disable_bts(); 1768 1769 intel_pmu_pebs_disable_all(); 1770 } 1771 1772 static void intel_pmu_disable_all(void) 1773 { 1774 __intel_pmu_disable_all(); 1775 intel_pmu_lbr_disable_all(); 1776 } 1777 1778 static void __intel_pmu_enable_all(int added, bool pmi) 1779 { 1780 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1781 1782 intel_pmu_pebs_enable_all(); 1783 intel_pmu_lbr_enable_all(pmi); 1784 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1785 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1786 1787 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1788 struct perf_event *event = 1789 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1790 1791 if (WARN_ON_ONCE(!event)) 1792 return; 1793 1794 intel_pmu_enable_bts(event->hw.config); 1795 } 1796 } 1797 1798 static void intel_pmu_enable_all(int added) 1799 { 1800 __intel_pmu_enable_all(added, false); 1801 } 1802 1803 /* 1804 * Workaround for: 1805 * Intel Errata AAK100 (model 26) 1806 * Intel Errata AAP53 (model 30) 1807 * Intel Errata BD53 (model 44) 1808 * 1809 * The official story: 1810 * These chips need to be 'reset' when adding counters by programming the 1811 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 1812 * in sequence on the same PMC or on different PMCs. 1813 * 1814 * In practise it appears some of these events do in fact count, and 1815 * we need to programm all 4 events. 1816 */ 1817 static void intel_pmu_nhm_workaround(void) 1818 { 1819 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1820 static const unsigned long nhm_magic[4] = { 1821 0x4300B5, 1822 0x4300D2, 1823 0x4300B1, 1824 0x4300B1 1825 }; 1826 struct perf_event *event; 1827 int i; 1828 1829 /* 1830 * The Errata requires below steps: 1831 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 1832 * 2) Configure 4 PERFEVTSELx with the magic events and clear 1833 * the corresponding PMCx; 1834 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 1835 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 1836 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 1837 */ 1838 1839 /* 1840 * The real steps we choose are a little different from above. 1841 * A) To reduce MSR operations, we don't run step 1) as they 1842 * are already cleared before this function is called; 1843 * B) Call x86_perf_event_update to save PMCx before configuring 1844 * PERFEVTSELx with magic number; 1845 * C) With step 5), we do clear only when the PERFEVTSELx is 1846 * not used currently. 1847 * D) Call x86_perf_event_set_period to restore PMCx; 1848 */ 1849 1850 /* We always operate 4 pairs of PERF Counters */ 1851 for (i = 0; i < 4; i++) { 1852 event = cpuc->events[i]; 1853 if (event) 1854 x86_perf_event_update(event); 1855 } 1856 1857 for (i = 0; i < 4; i++) { 1858 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 1859 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 1860 } 1861 1862 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 1863 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 1864 1865 for (i = 0; i < 4; i++) { 1866 event = cpuc->events[i]; 1867 1868 if (event) { 1869 x86_perf_event_set_period(event); 1870 __x86_pmu_enable_event(&event->hw, 1871 ARCH_PERFMON_EVENTSEL_ENABLE); 1872 } else 1873 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 1874 } 1875 } 1876 1877 static void intel_pmu_nhm_enable_all(int added) 1878 { 1879 if (added) 1880 intel_pmu_nhm_workaround(); 1881 intel_pmu_enable_all(added); 1882 } 1883 1884 static inline u64 intel_pmu_get_status(void) 1885 { 1886 u64 status; 1887 1888 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 1889 1890 return status; 1891 } 1892 1893 static inline void intel_pmu_ack_status(u64 ack) 1894 { 1895 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 1896 } 1897 1898 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 1899 { 1900 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 1901 u64 ctrl_val, mask; 1902 1903 mask = 0xfULL << (idx * 4); 1904 1905 rdmsrl(hwc->config_base, ctrl_val); 1906 ctrl_val &= ~mask; 1907 wrmsrl(hwc->config_base, ctrl_val); 1908 } 1909 1910 static inline bool event_is_checkpointed(struct perf_event *event) 1911 { 1912 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 1913 } 1914 1915 static void intel_pmu_disable_event(struct perf_event *event) 1916 { 1917 struct hw_perf_event *hwc = &event->hw; 1918 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1919 1920 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 1921 intel_pmu_disable_bts(); 1922 intel_pmu_drain_bts_buffer(); 1923 return; 1924 } 1925 1926 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); 1927 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); 1928 cpuc->intel_cp_status &= ~(1ull << hwc->idx); 1929 1930 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 1931 intel_pmu_disable_fixed(hwc); 1932 return; 1933 } 1934 1935 x86_pmu_disable_event(event); 1936 1937 if (unlikely(event->attr.precise_ip)) 1938 intel_pmu_pebs_disable(event); 1939 } 1940 1941 static void intel_pmu_del_event(struct perf_event *event) 1942 { 1943 if (needs_branch_stack(event)) 1944 intel_pmu_lbr_del(event); 1945 if (event->attr.precise_ip) 1946 intel_pmu_pebs_del(event); 1947 } 1948 1949 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) 1950 { 1951 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 1952 u64 ctrl_val, bits, mask; 1953 1954 /* 1955 * Enable IRQ generation (0x8), 1956 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 1957 * if requested: 1958 */ 1959 bits = 0x8ULL; 1960 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 1961 bits |= 0x2; 1962 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 1963 bits |= 0x1; 1964 1965 /* 1966 * ANY bit is supported in v3 and up 1967 */ 1968 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 1969 bits |= 0x4; 1970 1971 bits <<= (idx * 4); 1972 mask = 0xfULL << (idx * 4); 1973 1974 rdmsrl(hwc->config_base, ctrl_val); 1975 ctrl_val &= ~mask; 1976 ctrl_val |= bits; 1977 wrmsrl(hwc->config_base, ctrl_val); 1978 } 1979 1980 static void intel_pmu_enable_event(struct perf_event *event) 1981 { 1982 struct hw_perf_event *hwc = &event->hw; 1983 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1984 1985 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 1986 if (!__this_cpu_read(cpu_hw_events.enabled)) 1987 return; 1988 1989 intel_pmu_enable_bts(hwc->config); 1990 return; 1991 } 1992 1993 if (event->attr.exclude_host) 1994 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); 1995 if (event->attr.exclude_guest) 1996 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); 1997 1998 if (unlikely(event_is_checkpointed(event))) 1999 cpuc->intel_cp_status |= (1ull << hwc->idx); 2000 2001 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2002 intel_pmu_enable_fixed(hwc); 2003 return; 2004 } 2005 2006 if (unlikely(event->attr.precise_ip)) 2007 intel_pmu_pebs_enable(event); 2008 2009 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2010 } 2011 2012 static void intel_pmu_add_event(struct perf_event *event) 2013 { 2014 if (event->attr.precise_ip) 2015 intel_pmu_pebs_add(event); 2016 if (needs_branch_stack(event)) 2017 intel_pmu_lbr_add(event); 2018 } 2019 2020 /* 2021 * Save and restart an expired event. Called by NMI contexts, 2022 * so it has to be careful about preempting normal event ops: 2023 */ 2024 int intel_pmu_save_and_restart(struct perf_event *event) 2025 { 2026 x86_perf_event_update(event); 2027 /* 2028 * For a checkpointed counter always reset back to 0. This 2029 * avoids a situation where the counter overflows, aborts the 2030 * transaction and is then set back to shortly before the 2031 * overflow, and overflows and aborts again. 2032 */ 2033 if (unlikely(event_is_checkpointed(event))) { 2034 /* No race with NMIs because the counter should not be armed */ 2035 wrmsrl(event->hw.event_base, 0); 2036 local64_set(&event->hw.prev_count, 0); 2037 } 2038 return x86_perf_event_set_period(event); 2039 } 2040 2041 static void intel_pmu_reset(void) 2042 { 2043 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2044 unsigned long flags; 2045 int idx; 2046 2047 if (!x86_pmu.num_counters) 2048 return; 2049 2050 local_irq_save(flags); 2051 2052 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2053 2054 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2055 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2056 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2057 } 2058 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2059 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2060 2061 if (ds) 2062 ds->bts_index = ds->bts_buffer_base; 2063 2064 /* Ack all overflows and disable fixed counters */ 2065 if (x86_pmu.version >= 2) { 2066 intel_pmu_ack_status(intel_pmu_get_status()); 2067 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2068 } 2069 2070 /* Reset LBRs and LBR freezing */ 2071 if (x86_pmu.lbr_nr) { 2072 update_debugctlmsr(get_debugctlmsr() & 2073 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2074 } 2075 2076 local_irq_restore(flags); 2077 } 2078 2079 /* 2080 * This handler is triggered by the local APIC, so the APIC IRQ handling 2081 * rules apply: 2082 */ 2083 static int intel_pmu_handle_irq(struct pt_regs *regs) 2084 { 2085 struct perf_sample_data data; 2086 struct cpu_hw_events *cpuc; 2087 int bit, loops; 2088 u64 status; 2089 int handled; 2090 2091 cpuc = this_cpu_ptr(&cpu_hw_events); 2092 2093 /* 2094 * No known reason to not always do late ACK, 2095 * but just in case do it opt-in. 2096 */ 2097 if (!x86_pmu.late_ack) 2098 apic_write(APIC_LVTPC, APIC_DM_NMI); 2099 intel_bts_disable_local(); 2100 __intel_pmu_disable_all(); 2101 handled = intel_pmu_drain_bts_buffer(); 2102 handled += intel_bts_interrupt(); 2103 status = intel_pmu_get_status(); 2104 if (!status) 2105 goto done; 2106 2107 loops = 0; 2108 again: 2109 intel_pmu_lbr_read(); 2110 intel_pmu_ack_status(status); 2111 if (++loops > 100) { 2112 static bool warned = false; 2113 if (!warned) { 2114 WARN(1, "perfevents: irq loop stuck!\n"); 2115 perf_event_print_debug(); 2116 warned = true; 2117 } 2118 intel_pmu_reset(); 2119 goto done; 2120 } 2121 2122 inc_irq_stat(apic_perf_irqs); 2123 2124 2125 /* 2126 * Ignore a range of extra bits in status that do not indicate 2127 * overflow by themselves. 2128 */ 2129 status &= ~(GLOBAL_STATUS_COND_CHG | 2130 GLOBAL_STATUS_ASIF | 2131 GLOBAL_STATUS_LBRS_FROZEN); 2132 if (!status) 2133 goto done; 2134 /* 2135 * In case multiple PEBS events are sampled at the same time, 2136 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2137 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2138 * having their bits set in the status register. This is a sign 2139 * that there was at least one PEBS record pending at the time 2140 * of the PMU interrupt. PEBS counters must only be processed 2141 * via the drain_pebs() calls and not via the regular sample 2142 * processing loop coming after that the function, otherwise 2143 * phony regular samples may be generated in the sampling buffer 2144 * not marked with the EXACT tag. Another possibility is to have 2145 * one PEBS event and at least one non-PEBS event whic hoverflows 2146 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2147 * not be set, yet the overflow status bit for the PEBS counter will 2148 * be on Skylake. 2149 * 2150 * To avoid this problem, we systematically ignore the PEBS-enabled 2151 * counters from the GLOBAL_STATUS mask and we always process PEBS 2152 * events via drain_pebs(). 2153 */ 2154 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2155 2156 /* 2157 * PEBS overflow sets bit 62 in the global status register 2158 */ 2159 if (__test_and_clear_bit(62, (unsigned long *)&status)) { 2160 handled++; 2161 x86_pmu.drain_pebs(regs); 2162 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2163 } 2164 2165 /* 2166 * Intel PT 2167 */ 2168 if (__test_and_clear_bit(55, (unsigned long *)&status)) { 2169 handled++; 2170 intel_pt_interrupt(); 2171 } 2172 2173 /* 2174 * Checkpointed counters can lead to 'spurious' PMIs because the 2175 * rollback caused by the PMI will have cleared the overflow status 2176 * bit. Therefore always force probe these counters. 2177 */ 2178 status |= cpuc->intel_cp_status; 2179 2180 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2181 struct perf_event *event = cpuc->events[bit]; 2182 2183 handled++; 2184 2185 if (!test_bit(bit, cpuc->active_mask)) 2186 continue; 2187 2188 if (!intel_pmu_save_and_restart(event)) 2189 continue; 2190 2191 perf_sample_data_init(&data, 0, event->hw.last_period); 2192 2193 if (has_branch_stack(event)) 2194 data.br_stack = &cpuc->lbr_stack; 2195 2196 if (perf_event_overflow(event, &data, regs)) 2197 x86_pmu_stop(event, 0); 2198 } 2199 2200 /* 2201 * Repeat if there is more work to be done: 2202 */ 2203 status = intel_pmu_get_status(); 2204 if (status) 2205 goto again; 2206 2207 done: 2208 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 2209 if (cpuc->enabled) 2210 __intel_pmu_enable_all(0, true); 2211 intel_bts_enable_local(); 2212 2213 /* 2214 * Only unmask the NMI after the overflow counters 2215 * have been reset. This avoids spurious NMIs on 2216 * Haswell CPUs. 2217 */ 2218 if (x86_pmu.late_ack) 2219 apic_write(APIC_LVTPC, APIC_DM_NMI); 2220 return handled; 2221 } 2222 2223 static struct event_constraint * 2224 intel_bts_constraints(struct perf_event *event) 2225 { 2226 struct hw_perf_event *hwc = &event->hw; 2227 unsigned int hw_event, bts_event; 2228 2229 if (event->attr.freq) 2230 return NULL; 2231 2232 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 2233 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 2234 2235 if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) 2236 return &bts_constraint; 2237 2238 return NULL; 2239 } 2240 2241 static int intel_alt_er(int idx, u64 config) 2242 { 2243 int alt_idx = idx; 2244 2245 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2246 return idx; 2247 2248 if (idx == EXTRA_REG_RSP_0) 2249 alt_idx = EXTRA_REG_RSP_1; 2250 2251 if (idx == EXTRA_REG_RSP_1) 2252 alt_idx = EXTRA_REG_RSP_0; 2253 2254 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2255 return idx; 2256 2257 return alt_idx; 2258 } 2259 2260 static void intel_fixup_er(struct perf_event *event, int idx) 2261 { 2262 event->hw.extra_reg.idx = idx; 2263 2264 if (idx == EXTRA_REG_RSP_0) { 2265 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2266 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2267 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2268 } else if (idx == EXTRA_REG_RSP_1) { 2269 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2270 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2271 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2272 } 2273 } 2274 2275 /* 2276 * manage allocation of shared extra msr for certain events 2277 * 2278 * sharing can be: 2279 * per-cpu: to be shared between the various events on a single PMU 2280 * per-core: per-cpu + shared by HT threads 2281 */ 2282 static struct event_constraint * 2283 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2284 struct perf_event *event, 2285 struct hw_perf_event_extra *reg) 2286 { 2287 struct event_constraint *c = &emptyconstraint; 2288 struct er_account *era; 2289 unsigned long flags; 2290 int idx = reg->idx; 2291 2292 /* 2293 * reg->alloc can be set due to existing state, so for fake cpuc we 2294 * need to ignore this, otherwise we might fail to allocate proper fake 2295 * state for this extra reg constraint. Also see the comment below. 2296 */ 2297 if (reg->alloc && !cpuc->is_fake) 2298 return NULL; /* call x86_get_event_constraint() */ 2299 2300 again: 2301 era = &cpuc->shared_regs->regs[idx]; 2302 /* 2303 * we use spin_lock_irqsave() to avoid lockdep issues when 2304 * passing a fake cpuc 2305 */ 2306 raw_spin_lock_irqsave(&era->lock, flags); 2307 2308 if (!atomic_read(&era->ref) || era->config == reg->config) { 2309 2310 /* 2311 * If its a fake cpuc -- as per validate_{group,event}() we 2312 * shouldn't touch event state and we can avoid doing so 2313 * since both will only call get_event_constraints() once 2314 * on each event, this avoids the need for reg->alloc. 2315 * 2316 * Not doing the ER fixup will only result in era->reg being 2317 * wrong, but since we won't actually try and program hardware 2318 * this isn't a problem either. 2319 */ 2320 if (!cpuc->is_fake) { 2321 if (idx != reg->idx) 2322 intel_fixup_er(event, idx); 2323 2324 /* 2325 * x86_schedule_events() can call get_event_constraints() 2326 * multiple times on events in the case of incremental 2327 * scheduling(). reg->alloc ensures we only do the ER 2328 * allocation once. 2329 */ 2330 reg->alloc = 1; 2331 } 2332 2333 /* lock in msr value */ 2334 era->config = reg->config; 2335 era->reg = reg->reg; 2336 2337 /* one more user */ 2338 atomic_inc(&era->ref); 2339 2340 /* 2341 * need to call x86_get_event_constraint() 2342 * to check if associated event has constraints 2343 */ 2344 c = NULL; 2345 } else { 2346 idx = intel_alt_er(idx, reg->config); 2347 if (idx != reg->idx) { 2348 raw_spin_unlock_irqrestore(&era->lock, flags); 2349 goto again; 2350 } 2351 } 2352 raw_spin_unlock_irqrestore(&era->lock, flags); 2353 2354 return c; 2355 } 2356 2357 static void 2358 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 2359 struct hw_perf_event_extra *reg) 2360 { 2361 struct er_account *era; 2362 2363 /* 2364 * Only put constraint if extra reg was actually allocated. Also takes 2365 * care of event which do not use an extra shared reg. 2366 * 2367 * Also, if this is a fake cpuc we shouldn't touch any event state 2368 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 2369 * either since it'll be thrown out. 2370 */ 2371 if (!reg->alloc || cpuc->is_fake) 2372 return; 2373 2374 era = &cpuc->shared_regs->regs[reg->idx]; 2375 2376 /* one fewer user */ 2377 atomic_dec(&era->ref); 2378 2379 /* allocate again next time */ 2380 reg->alloc = 0; 2381 } 2382 2383 static struct event_constraint * 2384 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 2385 struct perf_event *event) 2386 { 2387 struct event_constraint *c = NULL, *d; 2388 struct hw_perf_event_extra *xreg, *breg; 2389 2390 xreg = &event->hw.extra_reg; 2391 if (xreg->idx != EXTRA_REG_NONE) { 2392 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 2393 if (c == &emptyconstraint) 2394 return c; 2395 } 2396 breg = &event->hw.branch_reg; 2397 if (breg->idx != EXTRA_REG_NONE) { 2398 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 2399 if (d == &emptyconstraint) { 2400 __intel_shared_reg_put_constraints(cpuc, xreg); 2401 c = d; 2402 } 2403 } 2404 return c; 2405 } 2406 2407 struct event_constraint * 2408 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2409 struct perf_event *event) 2410 { 2411 struct event_constraint *c; 2412 2413 if (x86_pmu.event_constraints) { 2414 for_each_event_constraint(c, x86_pmu.event_constraints) { 2415 if ((event->hw.config & c->cmask) == c->code) { 2416 event->hw.flags |= c->flags; 2417 return c; 2418 } 2419 } 2420 } 2421 2422 return &unconstrained; 2423 } 2424 2425 static struct event_constraint * 2426 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2427 struct perf_event *event) 2428 { 2429 struct event_constraint *c; 2430 2431 c = intel_bts_constraints(event); 2432 if (c) 2433 return c; 2434 2435 c = intel_shared_regs_constraints(cpuc, event); 2436 if (c) 2437 return c; 2438 2439 c = intel_pebs_constraints(event); 2440 if (c) 2441 return c; 2442 2443 return x86_get_event_constraints(cpuc, idx, event); 2444 } 2445 2446 static void 2447 intel_start_scheduling(struct cpu_hw_events *cpuc) 2448 { 2449 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2450 struct intel_excl_states *xl; 2451 int tid = cpuc->excl_thread_id; 2452 2453 /* 2454 * nothing needed if in group validation mode 2455 */ 2456 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2457 return; 2458 2459 /* 2460 * no exclusion needed 2461 */ 2462 if (WARN_ON_ONCE(!excl_cntrs)) 2463 return; 2464 2465 xl = &excl_cntrs->states[tid]; 2466 2467 xl->sched_started = true; 2468 /* 2469 * lock shared state until we are done scheduling 2470 * in stop_event_scheduling() 2471 * makes scheduling appear as a transaction 2472 */ 2473 raw_spin_lock(&excl_cntrs->lock); 2474 } 2475 2476 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2477 { 2478 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2479 struct event_constraint *c = cpuc->event_constraint[idx]; 2480 struct intel_excl_states *xl; 2481 int tid = cpuc->excl_thread_id; 2482 2483 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2484 return; 2485 2486 if (WARN_ON_ONCE(!excl_cntrs)) 2487 return; 2488 2489 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 2490 return; 2491 2492 xl = &excl_cntrs->states[tid]; 2493 2494 lockdep_assert_held(&excl_cntrs->lock); 2495 2496 if (c->flags & PERF_X86_EVENT_EXCL) 2497 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 2498 else 2499 xl->state[cntr] = INTEL_EXCL_SHARED; 2500 } 2501 2502 static void 2503 intel_stop_scheduling(struct cpu_hw_events *cpuc) 2504 { 2505 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2506 struct intel_excl_states *xl; 2507 int tid = cpuc->excl_thread_id; 2508 2509 /* 2510 * nothing needed if in group validation mode 2511 */ 2512 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2513 return; 2514 /* 2515 * no exclusion needed 2516 */ 2517 if (WARN_ON_ONCE(!excl_cntrs)) 2518 return; 2519 2520 xl = &excl_cntrs->states[tid]; 2521 2522 xl->sched_started = false; 2523 /* 2524 * release shared state lock (acquired in intel_start_scheduling()) 2525 */ 2526 raw_spin_unlock(&excl_cntrs->lock); 2527 } 2528 2529 static struct event_constraint * 2530 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 2531 int idx, struct event_constraint *c) 2532 { 2533 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2534 struct intel_excl_states *xlo; 2535 int tid = cpuc->excl_thread_id; 2536 int is_excl, i; 2537 2538 /* 2539 * validating a group does not require 2540 * enforcing cross-thread exclusion 2541 */ 2542 if (cpuc->is_fake || !is_ht_workaround_enabled()) 2543 return c; 2544 2545 /* 2546 * no exclusion needed 2547 */ 2548 if (WARN_ON_ONCE(!excl_cntrs)) 2549 return c; 2550 2551 /* 2552 * because we modify the constraint, we need 2553 * to make a copy. Static constraints come 2554 * from static const tables. 2555 * 2556 * only needed when constraint has not yet 2557 * been cloned (marked dynamic) 2558 */ 2559 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 2560 struct event_constraint *cx; 2561 2562 /* 2563 * grab pre-allocated constraint entry 2564 */ 2565 cx = &cpuc->constraint_list[idx]; 2566 2567 /* 2568 * initialize dynamic constraint 2569 * with static constraint 2570 */ 2571 *cx = *c; 2572 2573 /* 2574 * mark constraint as dynamic, so we 2575 * can free it later on 2576 */ 2577 cx->flags |= PERF_X86_EVENT_DYNAMIC; 2578 c = cx; 2579 } 2580 2581 /* 2582 * From here on, the constraint is dynamic. 2583 * Either it was just allocated above, or it 2584 * was allocated during a earlier invocation 2585 * of this function 2586 */ 2587 2588 /* 2589 * state of sibling HT 2590 */ 2591 xlo = &excl_cntrs->states[tid ^ 1]; 2592 2593 /* 2594 * event requires exclusive counter access 2595 * across HT threads 2596 */ 2597 is_excl = c->flags & PERF_X86_EVENT_EXCL; 2598 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 2599 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 2600 if (!cpuc->n_excl++) 2601 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 2602 } 2603 2604 /* 2605 * Modify static constraint with current dynamic 2606 * state of thread 2607 * 2608 * EXCLUSIVE: sibling counter measuring exclusive event 2609 * SHARED : sibling counter measuring non-exclusive event 2610 * UNUSED : sibling counter unused 2611 */ 2612 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 2613 /* 2614 * exclusive event in sibling counter 2615 * our corresponding counter cannot be used 2616 * regardless of our event 2617 */ 2618 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) 2619 __clear_bit(i, c->idxmsk); 2620 /* 2621 * if measuring an exclusive event, sibling 2622 * measuring non-exclusive, then counter cannot 2623 * be used 2624 */ 2625 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) 2626 __clear_bit(i, c->idxmsk); 2627 } 2628 2629 /* 2630 * recompute actual bit weight for scheduling algorithm 2631 */ 2632 c->weight = hweight64(c->idxmsk64); 2633 2634 /* 2635 * if we return an empty mask, then switch 2636 * back to static empty constraint to avoid 2637 * the cost of freeing later on 2638 */ 2639 if (c->weight == 0) 2640 c = &emptyconstraint; 2641 2642 return c; 2643 } 2644 2645 static struct event_constraint * 2646 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2647 struct perf_event *event) 2648 { 2649 struct event_constraint *c1 = NULL; 2650 struct event_constraint *c2; 2651 2652 if (idx >= 0) /* fake does < 0 */ 2653 c1 = cpuc->event_constraint[idx]; 2654 2655 /* 2656 * first time only 2657 * - static constraint: no change across incremental scheduling calls 2658 * - dynamic constraint: handled by intel_get_excl_constraints() 2659 */ 2660 c2 = __intel_get_event_constraints(cpuc, idx, event); 2661 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) { 2662 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 2663 c1->weight = c2->weight; 2664 c2 = c1; 2665 } 2666 2667 if (cpuc->excl_cntrs) 2668 return intel_get_excl_constraints(cpuc, event, idx, c2); 2669 2670 return c2; 2671 } 2672 2673 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 2674 struct perf_event *event) 2675 { 2676 struct hw_perf_event *hwc = &event->hw; 2677 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2678 int tid = cpuc->excl_thread_id; 2679 struct intel_excl_states *xl; 2680 2681 /* 2682 * nothing needed if in group validation mode 2683 */ 2684 if (cpuc->is_fake) 2685 return; 2686 2687 if (WARN_ON_ONCE(!excl_cntrs)) 2688 return; 2689 2690 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 2691 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 2692 if (!--cpuc->n_excl) 2693 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 2694 } 2695 2696 /* 2697 * If event was actually assigned, then mark the counter state as 2698 * unused now. 2699 */ 2700 if (hwc->idx >= 0) { 2701 xl = &excl_cntrs->states[tid]; 2702 2703 /* 2704 * put_constraint may be called from x86_schedule_events() 2705 * which already has the lock held so here make locking 2706 * conditional. 2707 */ 2708 if (!xl->sched_started) 2709 raw_spin_lock(&excl_cntrs->lock); 2710 2711 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 2712 2713 if (!xl->sched_started) 2714 raw_spin_unlock(&excl_cntrs->lock); 2715 } 2716 } 2717 2718 static void 2719 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 2720 struct perf_event *event) 2721 { 2722 struct hw_perf_event_extra *reg; 2723 2724 reg = &event->hw.extra_reg; 2725 if (reg->idx != EXTRA_REG_NONE) 2726 __intel_shared_reg_put_constraints(cpuc, reg); 2727 2728 reg = &event->hw.branch_reg; 2729 if (reg->idx != EXTRA_REG_NONE) 2730 __intel_shared_reg_put_constraints(cpuc, reg); 2731 } 2732 2733 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 2734 struct perf_event *event) 2735 { 2736 intel_put_shared_regs_event_constraints(cpuc, event); 2737 2738 /* 2739 * is PMU has exclusive counter restrictions, then 2740 * all events are subject to and must call the 2741 * put_excl_constraints() routine 2742 */ 2743 if (cpuc->excl_cntrs) 2744 intel_put_excl_constraints(cpuc, event); 2745 } 2746 2747 static void intel_pebs_aliases_core2(struct perf_event *event) 2748 { 2749 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2750 /* 2751 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2752 * (0x003c) so that we can use it with PEBS. 2753 * 2754 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2755 * PEBS capable. However we can use INST_RETIRED.ANY_P 2756 * (0x00c0), which is a PEBS capable event, to get the same 2757 * count. 2758 * 2759 * INST_RETIRED.ANY_P counts the number of cycles that retires 2760 * CNTMASK instructions. By setting CNTMASK to a value (16) 2761 * larger than the maximum number of instructions that can be 2762 * retired per cycle (4) and then inverting the condition, we 2763 * count all cycles that retire 16 or less instructions, which 2764 * is every cycle. 2765 * 2766 * Thereby we gain a PEBS capable cycle counter. 2767 */ 2768 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 2769 2770 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 2771 event->hw.config = alt_config; 2772 } 2773 } 2774 2775 static void intel_pebs_aliases_snb(struct perf_event *event) 2776 { 2777 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2778 /* 2779 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2780 * (0x003c) so that we can use it with PEBS. 2781 * 2782 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2783 * PEBS capable. However we can use UOPS_RETIRED.ALL 2784 * (0x01c2), which is a PEBS capable event, to get the same 2785 * count. 2786 * 2787 * UOPS_RETIRED.ALL counts the number of cycles that retires 2788 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 2789 * larger than the maximum number of micro-ops that can be 2790 * retired per cycle (4) and then inverting the condition, we 2791 * count all cycles that retire 16 or less micro-ops, which 2792 * is every cycle. 2793 * 2794 * Thereby we gain a PEBS capable cycle counter. 2795 */ 2796 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 2797 2798 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 2799 event->hw.config = alt_config; 2800 } 2801 } 2802 2803 static void intel_pebs_aliases_precdist(struct perf_event *event) 2804 { 2805 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2806 /* 2807 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2808 * (0x003c) so that we can use it with PEBS. 2809 * 2810 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2811 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 2812 * (0x01c0), which is a PEBS capable event, to get the same 2813 * count. 2814 * 2815 * The PREC_DIST event has special support to minimize sample 2816 * shadowing effects. One drawback is that it can be 2817 * only programmed on counter 1, but that seems like an 2818 * acceptable trade off. 2819 */ 2820 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 2821 2822 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 2823 event->hw.config = alt_config; 2824 } 2825 } 2826 2827 static void intel_pebs_aliases_ivb(struct perf_event *event) 2828 { 2829 if (event->attr.precise_ip < 3) 2830 return intel_pebs_aliases_snb(event); 2831 return intel_pebs_aliases_precdist(event); 2832 } 2833 2834 static void intel_pebs_aliases_skl(struct perf_event *event) 2835 { 2836 if (event->attr.precise_ip < 3) 2837 return intel_pebs_aliases_core2(event); 2838 return intel_pebs_aliases_precdist(event); 2839 } 2840 2841 static unsigned long intel_pmu_free_running_flags(struct perf_event *event) 2842 { 2843 unsigned long flags = x86_pmu.free_running_flags; 2844 2845 if (event->attr.use_clockid) 2846 flags &= ~PERF_SAMPLE_TIME; 2847 return flags; 2848 } 2849 2850 static int intel_pmu_hw_config(struct perf_event *event) 2851 { 2852 int ret = x86_pmu_hw_config(event); 2853 2854 if (ret) 2855 return ret; 2856 2857 if (event->attr.precise_ip) { 2858 if (!event->attr.freq) { 2859 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 2860 if (!(event->attr.sample_type & 2861 ~intel_pmu_free_running_flags(event))) 2862 event->hw.flags |= PERF_X86_EVENT_FREERUNNING; 2863 } 2864 if (x86_pmu.pebs_aliases) 2865 x86_pmu.pebs_aliases(event); 2866 } 2867 2868 if (needs_branch_stack(event)) { 2869 ret = intel_pmu_setup_lbr_filter(event); 2870 if (ret) 2871 return ret; 2872 2873 /* 2874 * BTS is set up earlier in this path, so don't account twice 2875 */ 2876 if (!intel_pmu_has_bts(event)) { 2877 /* disallow lbr if conflicting events are present */ 2878 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 2879 return -EBUSY; 2880 2881 event->destroy = hw_perf_lbr_event_destroy; 2882 } 2883 } 2884 2885 if (event->attr.type != PERF_TYPE_RAW) 2886 return 0; 2887 2888 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 2889 return 0; 2890 2891 if (x86_pmu.version < 3) 2892 return -EINVAL; 2893 2894 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) 2895 return -EACCES; 2896 2897 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 2898 2899 return 0; 2900 } 2901 2902 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 2903 { 2904 if (x86_pmu.guest_get_msrs) 2905 return x86_pmu.guest_get_msrs(nr); 2906 *nr = 0; 2907 return NULL; 2908 } 2909 EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 2910 2911 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 2912 { 2913 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2914 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 2915 2916 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 2917 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 2918 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 2919 /* 2920 * If PMU counter has PEBS enabled it is not enough to disable counter 2921 * on a guest entry since PEBS memory write can overshoot guest entry 2922 * and corrupt guest memory. Disabling PEBS solves the problem. 2923 */ 2924 arr[1].msr = MSR_IA32_PEBS_ENABLE; 2925 arr[1].host = cpuc->pebs_enabled; 2926 arr[1].guest = 0; 2927 2928 *nr = 2; 2929 return arr; 2930 } 2931 2932 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 2933 { 2934 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2935 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 2936 int idx; 2937 2938 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2939 struct perf_event *event = cpuc->events[idx]; 2940 2941 arr[idx].msr = x86_pmu_config_addr(idx); 2942 arr[idx].host = arr[idx].guest = 0; 2943 2944 if (!test_bit(idx, cpuc->active_mask)) 2945 continue; 2946 2947 arr[idx].host = arr[idx].guest = 2948 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 2949 2950 if (event->attr.exclude_host) 2951 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 2952 else if (event->attr.exclude_guest) 2953 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 2954 } 2955 2956 *nr = x86_pmu.num_counters; 2957 return arr; 2958 } 2959 2960 static void core_pmu_enable_event(struct perf_event *event) 2961 { 2962 if (!event->attr.exclude_host) 2963 x86_pmu_enable_event(event); 2964 } 2965 2966 static void core_pmu_enable_all(int added) 2967 { 2968 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2969 int idx; 2970 2971 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2972 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 2973 2974 if (!test_bit(idx, cpuc->active_mask) || 2975 cpuc->events[idx]->attr.exclude_host) 2976 continue; 2977 2978 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2979 } 2980 } 2981 2982 static int hsw_hw_config(struct perf_event *event) 2983 { 2984 int ret = intel_pmu_hw_config(event); 2985 2986 if (ret) 2987 return ret; 2988 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 2989 return 0; 2990 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 2991 2992 /* 2993 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 2994 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 2995 * this combination. 2996 */ 2997 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 2998 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 2999 event->attr.precise_ip > 0)) 3000 return -EOPNOTSUPP; 3001 3002 if (event_is_checkpointed(event)) { 3003 /* 3004 * Sampling of checkpointed events can cause situations where 3005 * the CPU constantly aborts because of a overflow, which is 3006 * then checkpointed back and ignored. Forbid checkpointing 3007 * for sampling. 3008 * 3009 * But still allow a long sampling period, so that perf stat 3010 * from KVM works. 3011 */ 3012 if (event->attr.sample_period > 0 && 3013 event->attr.sample_period < 0x7fffffff) 3014 return -EOPNOTSUPP; 3015 } 3016 return 0; 3017 } 3018 3019 static struct event_constraint counter2_constraint = 3020 EVENT_CONSTRAINT(0, 0x4, 0); 3021 3022 static struct event_constraint * 3023 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3024 struct perf_event *event) 3025 { 3026 struct event_constraint *c; 3027 3028 c = intel_get_event_constraints(cpuc, idx, event); 3029 3030 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3031 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3032 if (c->idxmsk64 & (1U << 2)) 3033 return &counter2_constraint; 3034 return &emptyconstraint; 3035 } 3036 3037 return c; 3038 } 3039 3040 /* 3041 * Broadwell: 3042 * 3043 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3044 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3045 * the two to enforce a minimum period of 128 (the smallest value that has bits 3046 * 0-5 cleared and >= 100). 3047 * 3048 * Because of how the code in x86_perf_event_set_period() works, the truncation 3049 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3050 * to make up for the 'lost' events due to carrying the 'error' in period_left. 3051 * 3052 * Therefore the effective (average) period matches the requested period, 3053 * despite coarser hardware granularity. 3054 */ 3055 static unsigned bdw_limit_period(struct perf_event *event, unsigned left) 3056 { 3057 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3058 X86_CONFIG(.event=0xc0, .umask=0x01)) { 3059 if (left < 128) 3060 left = 128; 3061 left &= ~0x3fu; 3062 } 3063 return left; 3064 } 3065 3066 PMU_FORMAT_ATTR(event, "config:0-7" ); 3067 PMU_FORMAT_ATTR(umask, "config:8-15" ); 3068 PMU_FORMAT_ATTR(edge, "config:18" ); 3069 PMU_FORMAT_ATTR(pc, "config:19" ); 3070 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3071 PMU_FORMAT_ATTR(inv, "config:23" ); 3072 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3073 PMU_FORMAT_ATTR(in_tx, "config:32"); 3074 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3075 3076 static struct attribute *intel_arch_formats_attr[] = { 3077 &format_attr_event.attr, 3078 &format_attr_umask.attr, 3079 &format_attr_edge.attr, 3080 &format_attr_pc.attr, 3081 &format_attr_inv.attr, 3082 &format_attr_cmask.attr, 3083 NULL, 3084 }; 3085 3086 ssize_t intel_event_sysfs_show(char *page, u64 config) 3087 { 3088 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3089 3090 return x86_event_sysfs_show(page, config, event); 3091 } 3092 3093 struct intel_shared_regs *allocate_shared_regs(int cpu) 3094 { 3095 struct intel_shared_regs *regs; 3096 int i; 3097 3098 regs = kzalloc_node(sizeof(struct intel_shared_regs), 3099 GFP_KERNEL, cpu_to_node(cpu)); 3100 if (regs) { 3101 /* 3102 * initialize the locks to keep lockdep happy 3103 */ 3104 for (i = 0; i < EXTRA_REG_MAX; i++) 3105 raw_spin_lock_init(®s->regs[i].lock); 3106 3107 regs->core_id = -1; 3108 } 3109 return regs; 3110 } 3111 3112 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3113 { 3114 struct intel_excl_cntrs *c; 3115 3116 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3117 GFP_KERNEL, cpu_to_node(cpu)); 3118 if (c) { 3119 raw_spin_lock_init(&c->lock); 3120 c->core_id = -1; 3121 } 3122 return c; 3123 } 3124 3125 static int intel_pmu_cpu_prepare(int cpu) 3126 { 3127 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3128 3129 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 3130 cpuc->shared_regs = allocate_shared_regs(cpu); 3131 if (!cpuc->shared_regs) 3132 goto err; 3133 } 3134 3135 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3136 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 3137 3138 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL); 3139 if (!cpuc->constraint_list) 3140 goto err_shared_regs; 3141 3142 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 3143 if (!cpuc->excl_cntrs) 3144 goto err_constraint_list; 3145 3146 cpuc->excl_thread_id = 0; 3147 } 3148 3149 return 0; 3150 3151 err_constraint_list: 3152 kfree(cpuc->constraint_list); 3153 cpuc->constraint_list = NULL; 3154 3155 err_shared_regs: 3156 kfree(cpuc->shared_regs); 3157 cpuc->shared_regs = NULL; 3158 3159 err: 3160 return -ENOMEM; 3161 } 3162 3163 static void flip_smm_bit(void *data) 3164 { 3165 unsigned long set = *(unsigned long *)data; 3166 3167 if (set > 0) { 3168 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 3169 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 3170 } else { 3171 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 3172 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 3173 } 3174 } 3175 3176 static void intel_pmu_cpu_starting(int cpu) 3177 { 3178 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3179 int core_id = topology_core_id(cpu); 3180 int i; 3181 3182 init_debug_store_on_cpu(cpu); 3183 /* 3184 * Deal with CPUs that don't clear their LBRs on power-up. 3185 */ 3186 intel_pmu_lbr_reset(); 3187 3188 cpuc->lbr_sel = NULL; 3189 3190 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 3191 3192 if (!cpuc->shared_regs) 3193 return; 3194 3195 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 3196 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3197 struct intel_shared_regs *pc; 3198 3199 pc = per_cpu(cpu_hw_events, i).shared_regs; 3200 if (pc && pc->core_id == core_id) { 3201 cpuc->kfree_on_online[0] = cpuc->shared_regs; 3202 cpuc->shared_regs = pc; 3203 break; 3204 } 3205 } 3206 cpuc->shared_regs->core_id = core_id; 3207 cpuc->shared_regs->refcnt++; 3208 } 3209 3210 if (x86_pmu.lbr_sel_map) 3211 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 3212 3213 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3214 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3215 struct cpu_hw_events *sibling; 3216 struct intel_excl_cntrs *c; 3217 3218 sibling = &per_cpu(cpu_hw_events, i); 3219 c = sibling->excl_cntrs; 3220 if (c && c->core_id == core_id) { 3221 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 3222 cpuc->excl_cntrs = c; 3223 if (!sibling->excl_thread_id) 3224 cpuc->excl_thread_id = 1; 3225 break; 3226 } 3227 } 3228 cpuc->excl_cntrs->core_id = core_id; 3229 cpuc->excl_cntrs->refcnt++; 3230 } 3231 } 3232 3233 static void free_excl_cntrs(int cpu) 3234 { 3235 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3236 struct intel_excl_cntrs *c; 3237 3238 c = cpuc->excl_cntrs; 3239 if (c) { 3240 if (c->core_id == -1 || --c->refcnt == 0) 3241 kfree(c); 3242 cpuc->excl_cntrs = NULL; 3243 kfree(cpuc->constraint_list); 3244 cpuc->constraint_list = NULL; 3245 } 3246 } 3247 3248 static void intel_pmu_cpu_dying(int cpu) 3249 { 3250 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3251 struct intel_shared_regs *pc; 3252 3253 pc = cpuc->shared_regs; 3254 if (pc) { 3255 if (pc->core_id == -1 || --pc->refcnt == 0) 3256 kfree(pc); 3257 cpuc->shared_regs = NULL; 3258 } 3259 3260 free_excl_cntrs(cpu); 3261 3262 fini_debug_store_on_cpu(cpu); 3263 } 3264 3265 static void intel_pmu_sched_task(struct perf_event_context *ctx, 3266 bool sched_in) 3267 { 3268 if (x86_pmu.pebs_active) 3269 intel_pmu_pebs_sched_task(ctx, sched_in); 3270 if (x86_pmu.lbr_nr) 3271 intel_pmu_lbr_sched_task(ctx, sched_in); 3272 } 3273 3274 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 3275 3276 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 3277 3278 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 3279 3280 static struct attribute *intel_arch3_formats_attr[] = { 3281 &format_attr_event.attr, 3282 &format_attr_umask.attr, 3283 &format_attr_edge.attr, 3284 &format_attr_pc.attr, 3285 &format_attr_any.attr, 3286 &format_attr_inv.attr, 3287 &format_attr_cmask.attr, 3288 &format_attr_in_tx.attr, 3289 &format_attr_in_tx_cp.attr, 3290 3291 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */ 3292 &format_attr_ldlat.attr, /* PEBS load latency */ 3293 NULL, 3294 }; 3295 3296 static struct attribute *skl_format_attr[] = { 3297 &format_attr_frontend.attr, 3298 NULL, 3299 }; 3300 3301 static __initconst const struct x86_pmu core_pmu = { 3302 .name = "core", 3303 .handle_irq = x86_pmu_handle_irq, 3304 .disable_all = x86_pmu_disable_all, 3305 .enable_all = core_pmu_enable_all, 3306 .enable = core_pmu_enable_event, 3307 .disable = x86_pmu_disable_event, 3308 .hw_config = x86_pmu_hw_config, 3309 .schedule_events = x86_schedule_events, 3310 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3311 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3312 .event_map = intel_pmu_event_map, 3313 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3314 .apic = 1, 3315 .free_running_flags = PEBS_FREERUNNING_FLAGS, 3316 3317 /* 3318 * Intel PMCs cannot be accessed sanely above 32-bit width, 3319 * so we install an artificial 1<<31 period regardless of 3320 * the generic event period: 3321 */ 3322 .max_period = (1ULL<<31) - 1, 3323 .get_event_constraints = intel_get_event_constraints, 3324 .put_event_constraints = intel_put_event_constraints, 3325 .event_constraints = intel_core_event_constraints, 3326 .guest_get_msrs = core_guest_get_msrs, 3327 .format_attrs = intel_arch_formats_attr, 3328 .events_sysfs_show = intel_event_sysfs_show, 3329 3330 /* 3331 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 3332 * together with PMU version 1 and thus be using core_pmu with 3333 * shared_regs. We need following callbacks here to allocate 3334 * it properly. 3335 */ 3336 .cpu_prepare = intel_pmu_cpu_prepare, 3337 .cpu_starting = intel_pmu_cpu_starting, 3338 .cpu_dying = intel_pmu_cpu_dying, 3339 }; 3340 3341 static __initconst const struct x86_pmu intel_pmu = { 3342 .name = "Intel", 3343 .handle_irq = intel_pmu_handle_irq, 3344 .disable_all = intel_pmu_disable_all, 3345 .enable_all = intel_pmu_enable_all, 3346 .enable = intel_pmu_enable_event, 3347 .disable = intel_pmu_disable_event, 3348 .add = intel_pmu_add_event, 3349 .del = intel_pmu_del_event, 3350 .hw_config = intel_pmu_hw_config, 3351 .schedule_events = x86_schedule_events, 3352 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3353 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3354 .event_map = intel_pmu_event_map, 3355 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3356 .apic = 1, 3357 .free_running_flags = PEBS_FREERUNNING_FLAGS, 3358 /* 3359 * Intel PMCs cannot be accessed sanely above 32 bit width, 3360 * so we install an artificial 1<<31 period regardless of 3361 * the generic event period: 3362 */ 3363 .max_period = (1ULL << 31) - 1, 3364 .get_event_constraints = intel_get_event_constraints, 3365 .put_event_constraints = intel_put_event_constraints, 3366 .pebs_aliases = intel_pebs_aliases_core2, 3367 3368 .format_attrs = intel_arch3_formats_attr, 3369 .events_sysfs_show = intel_event_sysfs_show, 3370 3371 .cpu_prepare = intel_pmu_cpu_prepare, 3372 .cpu_starting = intel_pmu_cpu_starting, 3373 .cpu_dying = intel_pmu_cpu_dying, 3374 .guest_get_msrs = intel_guest_get_msrs, 3375 .sched_task = intel_pmu_sched_task, 3376 }; 3377 3378 static __init void intel_clovertown_quirk(void) 3379 { 3380 /* 3381 * PEBS is unreliable due to: 3382 * 3383 * AJ67 - PEBS may experience CPL leaks 3384 * AJ68 - PEBS PMI may be delayed by one event 3385 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 3386 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 3387 * 3388 * AJ67 could be worked around by restricting the OS/USR flags. 3389 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 3390 * 3391 * AJ106 could possibly be worked around by not allowing LBR 3392 * usage from PEBS, including the fixup. 3393 * AJ68 could possibly be worked around by always programming 3394 * a pebs_event_reset[0] value and coping with the lost events. 3395 * 3396 * But taken together it might just make sense to not enable PEBS on 3397 * these chips. 3398 */ 3399 pr_warn("PEBS disabled due to CPU errata\n"); 3400 x86_pmu.pebs = 0; 3401 x86_pmu.pebs_constraints = NULL; 3402 } 3403 3404 static int intel_snb_pebs_broken(int cpu) 3405 { 3406 u32 rev = UINT_MAX; /* default to broken for unknown models */ 3407 3408 switch (cpu_data(cpu).x86_model) { 3409 case INTEL_FAM6_SANDYBRIDGE: 3410 rev = 0x28; 3411 break; 3412 3413 case INTEL_FAM6_SANDYBRIDGE_X: 3414 switch (cpu_data(cpu).x86_mask) { 3415 case 6: rev = 0x618; break; 3416 case 7: rev = 0x70c; break; 3417 } 3418 } 3419 3420 return (cpu_data(cpu).microcode < rev); 3421 } 3422 3423 static void intel_snb_check_microcode(void) 3424 { 3425 int pebs_broken = 0; 3426 int cpu; 3427 3428 for_each_online_cpu(cpu) { 3429 if ((pebs_broken = intel_snb_pebs_broken(cpu))) 3430 break; 3431 } 3432 3433 if (pebs_broken == x86_pmu.pebs_broken) 3434 return; 3435 3436 /* 3437 * Serialized by the microcode lock.. 3438 */ 3439 if (x86_pmu.pebs_broken) { 3440 pr_info("PEBS enabled due to microcode update\n"); 3441 x86_pmu.pebs_broken = 0; 3442 } else { 3443 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 3444 x86_pmu.pebs_broken = 1; 3445 } 3446 } 3447 3448 static bool is_lbr_from(unsigned long msr) 3449 { 3450 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 3451 3452 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 3453 } 3454 3455 /* 3456 * Under certain circumstances, access certain MSR may cause #GP. 3457 * The function tests if the input MSR can be safely accessed. 3458 */ 3459 static bool check_msr(unsigned long msr, u64 mask) 3460 { 3461 u64 val_old, val_new, val_tmp; 3462 3463 /* 3464 * Read the current value, change it and read it back to see if it 3465 * matches, this is needed to detect certain hardware emulators 3466 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 3467 */ 3468 if (rdmsrl_safe(msr, &val_old)) 3469 return false; 3470 3471 /* 3472 * Only change the bits which can be updated by wrmsrl. 3473 */ 3474 val_tmp = val_old ^ mask; 3475 3476 if (is_lbr_from(msr)) 3477 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 3478 3479 if (wrmsrl_safe(msr, val_tmp) || 3480 rdmsrl_safe(msr, &val_new)) 3481 return false; 3482 3483 /* 3484 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 3485 * should equal rdmsrl()'s even with the quirk. 3486 */ 3487 if (val_new != val_tmp) 3488 return false; 3489 3490 if (is_lbr_from(msr)) 3491 val_old = lbr_from_signext_quirk_wr(val_old); 3492 3493 /* Here it's sure that the MSR can be safely accessed. 3494 * Restore the old value and return. 3495 */ 3496 wrmsrl(msr, val_old); 3497 3498 return true; 3499 } 3500 3501 static __init void intel_sandybridge_quirk(void) 3502 { 3503 x86_pmu.check_microcode = intel_snb_check_microcode; 3504 cpus_read_lock(); 3505 intel_snb_check_microcode(); 3506 cpus_read_unlock(); 3507 } 3508 3509 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 3510 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 3511 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 3512 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 3513 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 3514 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 3515 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 3516 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 3517 }; 3518 3519 static __init void intel_arch_events_quirk(void) 3520 { 3521 int bit; 3522 3523 /* disable event that reported as not presend by cpuid */ 3524 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 3525 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 3526 pr_warn("CPUID marked event: \'%s\' unavailable\n", 3527 intel_arch_events_map[bit].name); 3528 } 3529 } 3530 3531 static __init void intel_nehalem_quirk(void) 3532 { 3533 union cpuid10_ebx ebx; 3534 3535 ebx.full = x86_pmu.events_maskl; 3536 if (ebx.split.no_branch_misses_retired) { 3537 /* 3538 * Erratum AAJ80 detected, we work it around by using 3539 * the BR_MISP_EXEC.ANY event. This will over-count 3540 * branch-misses, but it's still much better than the 3541 * architectural event which is often completely bogus: 3542 */ 3543 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 3544 ebx.split.no_branch_misses_retired = 0; 3545 x86_pmu.events_maskl = ebx.full; 3546 pr_info("CPU erratum AAJ80 worked around\n"); 3547 } 3548 } 3549 3550 /* 3551 * enable software workaround for errata: 3552 * SNB: BJ122 3553 * IVB: BV98 3554 * HSW: HSD29 3555 * 3556 * Only needed when HT is enabled. However detecting 3557 * if HT is enabled is difficult (model specific). So instead, 3558 * we enable the workaround in the early boot, and verify if 3559 * it is needed in a later initcall phase once we have valid 3560 * topology information to check if HT is actually enabled 3561 */ 3562 static __init void intel_ht_bug(void) 3563 { 3564 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 3565 3566 x86_pmu.start_scheduling = intel_start_scheduling; 3567 x86_pmu.commit_scheduling = intel_commit_scheduling; 3568 x86_pmu.stop_scheduling = intel_stop_scheduling; 3569 } 3570 3571 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 3572 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 3573 3574 /* Haswell special events */ 3575 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 3576 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 3577 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 3578 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 3579 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 3580 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 3581 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 3582 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 3583 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 3584 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 3585 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 3586 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 3587 3588 static struct attribute *hsw_events_attrs[] = { 3589 EVENT_PTR(tx_start), 3590 EVENT_PTR(tx_commit), 3591 EVENT_PTR(tx_abort), 3592 EVENT_PTR(tx_capacity), 3593 EVENT_PTR(tx_conflict), 3594 EVENT_PTR(el_start), 3595 EVENT_PTR(el_commit), 3596 EVENT_PTR(el_abort), 3597 EVENT_PTR(el_capacity), 3598 EVENT_PTR(el_conflict), 3599 EVENT_PTR(cycles_t), 3600 EVENT_PTR(cycles_ct), 3601 EVENT_PTR(mem_ld_hsw), 3602 EVENT_PTR(mem_st_hsw), 3603 EVENT_PTR(td_slots_issued), 3604 EVENT_PTR(td_slots_retired), 3605 EVENT_PTR(td_fetch_bubbles), 3606 EVENT_PTR(td_total_slots), 3607 EVENT_PTR(td_total_slots_scale), 3608 EVENT_PTR(td_recovery_bubbles), 3609 EVENT_PTR(td_recovery_bubbles_scale), 3610 NULL 3611 }; 3612 3613 static ssize_t freeze_on_smi_show(struct device *cdev, 3614 struct device_attribute *attr, 3615 char *buf) 3616 { 3617 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 3618 } 3619 3620 static DEFINE_MUTEX(freeze_on_smi_mutex); 3621 3622 static ssize_t freeze_on_smi_store(struct device *cdev, 3623 struct device_attribute *attr, 3624 const char *buf, size_t count) 3625 { 3626 unsigned long val; 3627 ssize_t ret; 3628 3629 ret = kstrtoul(buf, 0, &val); 3630 if (ret) 3631 return ret; 3632 3633 if (val > 1) 3634 return -EINVAL; 3635 3636 mutex_lock(&freeze_on_smi_mutex); 3637 3638 if (x86_pmu.attr_freeze_on_smi == val) 3639 goto done; 3640 3641 x86_pmu.attr_freeze_on_smi = val; 3642 3643 get_online_cpus(); 3644 on_each_cpu(flip_smm_bit, &val, 1); 3645 put_online_cpus(); 3646 done: 3647 mutex_unlock(&freeze_on_smi_mutex); 3648 3649 return count; 3650 } 3651 3652 static DEVICE_ATTR_RW(freeze_on_smi); 3653 3654 static struct attribute *intel_pmu_attrs[] = { 3655 &dev_attr_freeze_on_smi.attr, 3656 NULL, 3657 }; 3658 3659 __init int intel_pmu_init(void) 3660 { 3661 union cpuid10_edx edx; 3662 union cpuid10_eax eax; 3663 union cpuid10_ebx ebx; 3664 struct event_constraint *c; 3665 unsigned int unused; 3666 struct extra_reg *er; 3667 int version, i; 3668 3669 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 3670 switch (boot_cpu_data.x86) { 3671 case 0x6: 3672 return p6_pmu_init(); 3673 case 0xb: 3674 return knc_pmu_init(); 3675 case 0xf: 3676 return p4_pmu_init(); 3677 } 3678 return -ENODEV; 3679 } 3680 3681 /* 3682 * Check whether the Architectural PerfMon supports 3683 * Branch Misses Retired hw_event or not. 3684 */ 3685 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 3686 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 3687 return -ENODEV; 3688 3689 version = eax.split.version_id; 3690 if (version < 2) 3691 x86_pmu = core_pmu; 3692 else 3693 x86_pmu = intel_pmu; 3694 3695 x86_pmu.version = version; 3696 x86_pmu.num_counters = eax.split.num_counters; 3697 x86_pmu.cntval_bits = eax.split.bit_width; 3698 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 3699 3700 x86_pmu.events_maskl = ebx.full; 3701 x86_pmu.events_mask_len = eax.split.mask_length; 3702 3703 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 3704 3705 3706 x86_pmu.attrs = intel_pmu_attrs; 3707 /* 3708 * Quirk: v2 perfmon does not report fixed-purpose events, so 3709 * assume at least 3 events, when not running in a hypervisor: 3710 */ 3711 if (version > 1) { 3712 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 3713 3714 x86_pmu.num_counters_fixed = 3715 max((int)edx.split.num_counters_fixed, assume); 3716 } 3717 3718 if (boot_cpu_has(X86_FEATURE_PDCM)) { 3719 u64 capabilities; 3720 3721 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 3722 x86_pmu.intel_cap.capabilities = capabilities; 3723 } 3724 3725 intel_ds_init(); 3726 3727 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 3728 3729 /* 3730 * Install the hw-cache-events table: 3731 */ 3732 switch (boot_cpu_data.x86_model) { 3733 case INTEL_FAM6_CORE_YONAH: 3734 pr_cont("Core events, "); 3735 break; 3736 3737 case INTEL_FAM6_CORE2_MEROM: 3738 x86_add_quirk(intel_clovertown_quirk); 3739 case INTEL_FAM6_CORE2_MEROM_L: 3740 case INTEL_FAM6_CORE2_PENRYN: 3741 case INTEL_FAM6_CORE2_DUNNINGTON: 3742 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 3743 sizeof(hw_cache_event_ids)); 3744 3745 intel_pmu_lbr_init_core(); 3746 3747 x86_pmu.event_constraints = intel_core2_event_constraints; 3748 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 3749 pr_cont("Core2 events, "); 3750 break; 3751 3752 case INTEL_FAM6_NEHALEM: 3753 case INTEL_FAM6_NEHALEM_EP: 3754 case INTEL_FAM6_NEHALEM_EX: 3755 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 3756 sizeof(hw_cache_event_ids)); 3757 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 3758 sizeof(hw_cache_extra_regs)); 3759 3760 intel_pmu_lbr_init_nhm(); 3761 3762 x86_pmu.event_constraints = intel_nehalem_event_constraints; 3763 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 3764 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 3765 x86_pmu.extra_regs = intel_nehalem_extra_regs; 3766 3767 x86_pmu.cpu_events = nhm_events_attrs; 3768 3769 /* UOPS_ISSUED.STALLED_CYCLES */ 3770 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 3771 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 3772 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 3773 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 3774 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 3775 3776 intel_pmu_pebs_data_source_nhm(); 3777 x86_add_quirk(intel_nehalem_quirk); 3778 3779 pr_cont("Nehalem events, "); 3780 break; 3781 3782 case INTEL_FAM6_ATOM_PINEVIEW: 3783 case INTEL_FAM6_ATOM_LINCROFT: 3784 case INTEL_FAM6_ATOM_PENWELL: 3785 case INTEL_FAM6_ATOM_CLOVERVIEW: 3786 case INTEL_FAM6_ATOM_CEDARVIEW: 3787 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 3788 sizeof(hw_cache_event_ids)); 3789 3790 intel_pmu_lbr_init_atom(); 3791 3792 x86_pmu.event_constraints = intel_gen_event_constraints; 3793 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 3794 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 3795 pr_cont("Atom events, "); 3796 break; 3797 3798 case INTEL_FAM6_ATOM_SILVERMONT1: 3799 case INTEL_FAM6_ATOM_SILVERMONT2: 3800 case INTEL_FAM6_ATOM_AIRMONT: 3801 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 3802 sizeof(hw_cache_event_ids)); 3803 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 3804 sizeof(hw_cache_extra_regs)); 3805 3806 intel_pmu_lbr_init_slm(); 3807 3808 x86_pmu.event_constraints = intel_slm_event_constraints; 3809 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 3810 x86_pmu.extra_regs = intel_slm_extra_regs; 3811 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3812 x86_pmu.cpu_events = slm_events_attrs; 3813 pr_cont("Silvermont events, "); 3814 break; 3815 3816 case INTEL_FAM6_ATOM_GOLDMONT: 3817 case INTEL_FAM6_ATOM_DENVERTON: 3818 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 3819 sizeof(hw_cache_event_ids)); 3820 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 3821 sizeof(hw_cache_extra_regs)); 3822 3823 intel_pmu_lbr_init_skl(); 3824 3825 x86_pmu.event_constraints = intel_slm_event_constraints; 3826 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 3827 x86_pmu.extra_regs = intel_glm_extra_regs; 3828 /* 3829 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 3830 * for precise cycles. 3831 * :pp is identical to :ppp 3832 */ 3833 x86_pmu.pebs_aliases = NULL; 3834 x86_pmu.pebs_prec_dist = true; 3835 x86_pmu.lbr_pt_coexist = true; 3836 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3837 x86_pmu.cpu_events = glm_events_attrs; 3838 pr_cont("Goldmont events, "); 3839 break; 3840 3841 case INTEL_FAM6_WESTMERE: 3842 case INTEL_FAM6_WESTMERE_EP: 3843 case INTEL_FAM6_WESTMERE_EX: 3844 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 3845 sizeof(hw_cache_event_ids)); 3846 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 3847 sizeof(hw_cache_extra_regs)); 3848 3849 intel_pmu_lbr_init_nhm(); 3850 3851 x86_pmu.event_constraints = intel_westmere_event_constraints; 3852 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 3853 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 3854 x86_pmu.extra_regs = intel_westmere_extra_regs; 3855 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3856 3857 x86_pmu.cpu_events = nhm_events_attrs; 3858 3859 /* UOPS_ISSUED.STALLED_CYCLES */ 3860 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 3861 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 3862 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 3863 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 3864 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 3865 3866 intel_pmu_pebs_data_source_nhm(); 3867 pr_cont("Westmere events, "); 3868 break; 3869 3870 case INTEL_FAM6_SANDYBRIDGE: 3871 case INTEL_FAM6_SANDYBRIDGE_X: 3872 x86_add_quirk(intel_sandybridge_quirk); 3873 x86_add_quirk(intel_ht_bug); 3874 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 3875 sizeof(hw_cache_event_ids)); 3876 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 3877 sizeof(hw_cache_extra_regs)); 3878 3879 intel_pmu_lbr_init_snb(); 3880 3881 x86_pmu.event_constraints = intel_snb_event_constraints; 3882 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 3883 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 3884 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 3885 x86_pmu.extra_regs = intel_snbep_extra_regs; 3886 else 3887 x86_pmu.extra_regs = intel_snb_extra_regs; 3888 3889 3890 /* all extra regs are per-cpu when HT is on */ 3891 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3892 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 3893 3894 x86_pmu.cpu_events = snb_events_attrs; 3895 3896 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 3897 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 3898 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 3899 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 3900 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 3901 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 3902 3903 pr_cont("SandyBridge events, "); 3904 break; 3905 3906 case INTEL_FAM6_IVYBRIDGE: 3907 case INTEL_FAM6_IVYBRIDGE_X: 3908 x86_add_quirk(intel_ht_bug); 3909 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 3910 sizeof(hw_cache_event_ids)); 3911 /* dTLB-load-misses on IVB is different than SNB */ 3912 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 3913 3914 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 3915 sizeof(hw_cache_extra_regs)); 3916 3917 intel_pmu_lbr_init_snb(); 3918 3919 x86_pmu.event_constraints = intel_ivb_event_constraints; 3920 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 3921 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 3922 x86_pmu.pebs_prec_dist = true; 3923 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 3924 x86_pmu.extra_regs = intel_snbep_extra_regs; 3925 else 3926 x86_pmu.extra_regs = intel_snb_extra_regs; 3927 /* all extra regs are per-cpu when HT is on */ 3928 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3929 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 3930 3931 x86_pmu.cpu_events = snb_events_attrs; 3932 3933 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 3934 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 3935 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 3936 3937 pr_cont("IvyBridge events, "); 3938 break; 3939 3940 3941 case INTEL_FAM6_HASWELL_CORE: 3942 case INTEL_FAM6_HASWELL_X: 3943 case INTEL_FAM6_HASWELL_ULT: 3944 case INTEL_FAM6_HASWELL_GT3E: 3945 x86_add_quirk(intel_ht_bug); 3946 x86_pmu.late_ack = true; 3947 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 3948 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 3949 3950 intel_pmu_lbr_init_hsw(); 3951 3952 x86_pmu.event_constraints = intel_hsw_event_constraints; 3953 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 3954 x86_pmu.extra_regs = intel_snbep_extra_regs; 3955 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 3956 x86_pmu.pebs_prec_dist = true; 3957 /* all extra regs are per-cpu when HT is on */ 3958 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3959 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 3960 3961 x86_pmu.hw_config = hsw_hw_config; 3962 x86_pmu.get_event_constraints = hsw_get_event_constraints; 3963 x86_pmu.cpu_events = hsw_events_attrs; 3964 x86_pmu.lbr_double_abort = true; 3965 pr_cont("Haswell events, "); 3966 break; 3967 3968 case INTEL_FAM6_BROADWELL_CORE: 3969 case INTEL_FAM6_BROADWELL_XEON_D: 3970 case INTEL_FAM6_BROADWELL_GT3E: 3971 case INTEL_FAM6_BROADWELL_X: 3972 x86_pmu.late_ack = true; 3973 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 3974 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 3975 3976 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 3977 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 3978 BDW_L3_MISS|HSW_SNOOP_DRAM; 3979 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 3980 HSW_SNOOP_DRAM; 3981 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 3982 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 3983 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 3984 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 3985 3986 intel_pmu_lbr_init_hsw(); 3987 3988 x86_pmu.event_constraints = intel_bdw_event_constraints; 3989 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 3990 x86_pmu.extra_regs = intel_snbep_extra_regs; 3991 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 3992 x86_pmu.pebs_prec_dist = true; 3993 /* all extra regs are per-cpu when HT is on */ 3994 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3995 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 3996 3997 x86_pmu.hw_config = hsw_hw_config; 3998 x86_pmu.get_event_constraints = hsw_get_event_constraints; 3999 x86_pmu.cpu_events = hsw_events_attrs; 4000 x86_pmu.limit_period = bdw_limit_period; 4001 pr_cont("Broadwell events, "); 4002 break; 4003 4004 case INTEL_FAM6_XEON_PHI_KNL: 4005 case INTEL_FAM6_XEON_PHI_KNM: 4006 memcpy(hw_cache_event_ids, 4007 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4008 memcpy(hw_cache_extra_regs, 4009 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4010 intel_pmu_lbr_init_knl(); 4011 4012 x86_pmu.event_constraints = intel_slm_event_constraints; 4013 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4014 x86_pmu.extra_regs = intel_knl_extra_regs; 4015 4016 /* all extra regs are per-cpu when HT is on */ 4017 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4018 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4019 4020 pr_cont("Knights Landing/Mill events, "); 4021 break; 4022 4023 case INTEL_FAM6_SKYLAKE_MOBILE: 4024 case INTEL_FAM6_SKYLAKE_DESKTOP: 4025 case INTEL_FAM6_SKYLAKE_X: 4026 case INTEL_FAM6_KABYLAKE_MOBILE: 4027 case INTEL_FAM6_KABYLAKE_DESKTOP: 4028 x86_pmu.late_ack = true; 4029 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4030 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4031 intel_pmu_lbr_init_skl(); 4032 4033 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 4034 event_attr_td_recovery_bubbles.event_str_noht = 4035 "event=0xd,umask=0x1,cmask=1"; 4036 event_attr_td_recovery_bubbles.event_str_ht = 4037 "event=0xd,umask=0x1,cmask=1,any=1"; 4038 4039 x86_pmu.event_constraints = intel_skl_event_constraints; 4040 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 4041 x86_pmu.extra_regs = intel_skl_extra_regs; 4042 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 4043 x86_pmu.pebs_prec_dist = true; 4044 /* all extra regs are per-cpu when HT is on */ 4045 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4046 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4047 4048 x86_pmu.hw_config = hsw_hw_config; 4049 x86_pmu.get_event_constraints = hsw_get_event_constraints; 4050 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, 4051 skl_format_attr); 4052 WARN_ON(!x86_pmu.format_attrs); 4053 x86_pmu.cpu_events = hsw_events_attrs; 4054 pr_cont("Skylake events, "); 4055 break; 4056 4057 default: 4058 switch (x86_pmu.version) { 4059 case 1: 4060 x86_pmu.event_constraints = intel_v1_event_constraints; 4061 pr_cont("generic architected perfmon v1, "); 4062 break; 4063 default: 4064 /* 4065 * default constraints for v2 and up 4066 */ 4067 x86_pmu.event_constraints = intel_gen_event_constraints; 4068 pr_cont("generic architected perfmon, "); 4069 break; 4070 } 4071 } 4072 4073 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 4074 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 4075 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 4076 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 4077 } 4078 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 4079 4080 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 4081 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 4082 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 4083 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 4084 } 4085 4086 x86_pmu.intel_ctrl |= 4087 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 4088 4089 if (x86_pmu.event_constraints) { 4090 /* 4091 * event on fixed counter2 (REF_CYCLES) only works on this 4092 * counter, so do not extend mask to generic counters 4093 */ 4094 for_each_event_constraint(c, x86_pmu.event_constraints) { 4095 if (c->cmask == FIXED_EVENT_FLAGS 4096 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 4097 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 4098 } 4099 c->idxmsk64 &= 4100 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 4101 c->weight = hweight64(c->idxmsk64); 4102 } 4103 } 4104 4105 /* 4106 * Access LBR MSR may cause #GP under certain circumstances. 4107 * E.g. KVM doesn't support LBR MSR 4108 * Check all LBT MSR here. 4109 * Disable LBR access if any LBR MSRs can not be accessed. 4110 */ 4111 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 4112 x86_pmu.lbr_nr = 0; 4113 for (i = 0; i < x86_pmu.lbr_nr; i++) { 4114 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 4115 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 4116 x86_pmu.lbr_nr = 0; 4117 } 4118 4119 if (x86_pmu.lbr_nr) 4120 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 4121 /* 4122 * Access extra MSR may cause #GP under certain circumstances. 4123 * E.g. KVM doesn't support offcore event 4124 * Check all extra_regs here. 4125 */ 4126 if (x86_pmu.extra_regs) { 4127 for (er = x86_pmu.extra_regs; er->msr; er++) { 4128 er->extra_msr_access = check_msr(er->msr, 0x11UL); 4129 /* Disable LBR select mapping */ 4130 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 4131 x86_pmu.lbr_sel_map = NULL; 4132 } 4133 } 4134 4135 /* Support full width counters using alternative MSR range */ 4136 if (x86_pmu.intel_cap.full_width_write) { 4137 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 4138 x86_pmu.perfctr = MSR_IA32_PMC0; 4139 pr_cont("full-width counters, "); 4140 } 4141 4142 return 0; 4143 } 4144 4145 /* 4146 * HT bug: phase 2 init 4147 * Called once we have valid topology information to check 4148 * whether or not HT is enabled 4149 * If HT is off, then we disable the workaround 4150 */ 4151 static __init int fixup_ht_bug(void) 4152 { 4153 int c; 4154 /* 4155 * problem not present on this CPU model, nothing to do 4156 */ 4157 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 4158 return 0; 4159 4160 if (topology_max_smt_threads() > 1) { 4161 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 4162 return 0; 4163 } 4164 4165 if (lockup_detector_suspend() != 0) { 4166 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n"); 4167 return 0; 4168 } 4169 4170 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 4171 4172 x86_pmu.start_scheduling = NULL; 4173 x86_pmu.commit_scheduling = NULL; 4174 x86_pmu.stop_scheduling = NULL; 4175 4176 lockup_detector_resume(); 4177 4178 cpus_read_lock(); 4179 4180 for_each_online_cpu(c) 4181 free_excl_cntrs(c); 4182 4183 cpus_read_unlock(); 4184 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 4185 return 0; 4186 } 4187 subsys_initcall(fixup_ht_bug) 4188