1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1069839SBorislav Petkov /* 3e1069839SBorislav Petkov * Per core/cpu state 4e1069839SBorislav Petkov * 5e1069839SBorislav Petkov * Used to coordinate shared registers between HT threads or 6e1069839SBorislav Petkov * among events on a single PMU. 7e1069839SBorislav Petkov */ 8e1069839SBorislav Petkov 9e1069839SBorislav Petkov #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10e1069839SBorislav Petkov 11e1069839SBorislav Petkov #include <linux/stddef.h> 12e1069839SBorislav Petkov #include <linux/types.h> 13e1069839SBorislav Petkov #include <linux/init.h> 14e1069839SBorislav Petkov #include <linux/slab.h> 15e1069839SBorislav Petkov #include <linux/export.h> 16e1069839SBorislav Petkov #include <linux/nmi.h> 17e1069839SBorislav Petkov 18e1069839SBorislav Petkov #include <asm/cpufeature.h> 19e1069839SBorislav Petkov #include <asm/hardirq.h> 20ef5f9f47SDave Hansen #include <asm/intel-family.h> 2142880f72SAlexander Shishkin #include <asm/intel_pt.h> 22e1069839SBorislav Petkov #include <asm/apic.h> 239b545c04SAndi Kleen #include <asm/cpu_device_id.h> 24e1069839SBorislav Petkov 2527f6d22bSBorislav Petkov #include "../perf_event.h" 26e1069839SBorislav Petkov 27e1069839SBorislav Petkov /* 28e1069839SBorislav Petkov * Intel PerfMon, used on Core and later. 29e1069839SBorislav Petkov */ 30e1069839SBorislav Petkov static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31e1069839SBorislav Petkov { 32e1069839SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33e1069839SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38e1069839SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39e1069839SBorislav Petkov [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40e1069839SBorislav Petkov }; 41e1069839SBorislav Petkov 42e1069839SBorislav Petkov static struct event_constraint intel_core_event_constraints[] __read_mostly = 43e1069839SBorislav Petkov { 44e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50e1069839SBorislav Petkov EVENT_CONSTRAINT_END 51e1069839SBorislav Petkov }; 52e1069839SBorislav Petkov 53e1069839SBorislav Petkov static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54e1069839SBorislav Petkov { 55e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68e1069839SBorislav Petkov EVENT_CONSTRAINT_END 69e1069839SBorislav Petkov }; 70e1069839SBorislav Petkov 71e1069839SBorislav Petkov static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72e1069839SBorislav Petkov { 73e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84e1069839SBorislav Petkov EVENT_CONSTRAINT_END 85e1069839SBorislav Petkov }; 86e1069839SBorislav Petkov 87e1069839SBorislav Petkov static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88e1069839SBorislav Petkov { 89e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92e1069839SBorislav Petkov EVENT_EXTRA_END 93e1069839SBorislav Petkov }; 94e1069839SBorislav Petkov 95e1069839SBorislav Petkov static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96e1069839SBorislav Petkov { 97e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104e1069839SBorislav Petkov EVENT_CONSTRAINT_END 105e1069839SBorislav Petkov }; 106e1069839SBorislav Petkov 107e1069839SBorislav Petkov static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108e1069839SBorislav Petkov { 109e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121e1069839SBorislav Petkov 1229010ae4aSStephane Eranian /* 1239010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1249010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1259010ae4aSStephane Eranian */ 126e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130e1069839SBorislav Petkov 131e1069839SBorislav Petkov EVENT_CONSTRAINT_END 132e1069839SBorislav Petkov }; 133e1069839SBorislav Petkov 134e1069839SBorislav Petkov static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135e1069839SBorislav Petkov { 136e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140d9f6e12fSIngo Molnar INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 141e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149e1069839SBorislav Petkov 1509010ae4aSStephane Eranian /* 1519010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1529010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1539010ae4aSStephane Eranian */ 154e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158e1069839SBorislav Petkov 159e1069839SBorislav Petkov EVENT_CONSTRAINT_END 160e1069839SBorislav Petkov }; 161e1069839SBorislav Petkov 162e1069839SBorislav Petkov static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163e1069839SBorislav Petkov { 164e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168e1069839SBorislav Petkov EVENT_EXTRA_END 169e1069839SBorislav Petkov }; 170e1069839SBorislav Petkov 171e1069839SBorislav Petkov static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172e1069839SBorislav Petkov { 173e1069839SBorislav Petkov EVENT_CONSTRAINT_END 174e1069839SBorislav Petkov }; 175e1069839SBorislav Petkov 176e1069839SBorislav Petkov static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177e1069839SBorislav Petkov { 178e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181e1069839SBorislav Petkov EVENT_CONSTRAINT_END 182e1069839SBorislav Petkov }; 183e1069839SBorislav Petkov 184*ee28855aSKan Liang static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 185*ee28855aSKan Liang { 186*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 189*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 190*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0500, 4), 191*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0600, 5), 192*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0700, 6), 193*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0800, 7), 194*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0900, 8), 195*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0a00, 9), 196*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0b00, 10), 197*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0c00, 11), 198*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0d00, 12), 199*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0e00, 13), 200*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x0f00, 14), 201*ee28855aSKan Liang FIXED_EVENT_CONSTRAINT(0x1000, 15), 202*ee28855aSKan Liang EVENT_CONSTRAINT_END 203*ee28855aSKan Liang }; 204*ee28855aSKan Liang 205e1069839SBorislav Petkov static struct event_constraint intel_slm_event_constraints[] __read_mostly = 206e1069839SBorislav Petkov { 207e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 208e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 209e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 210e1069839SBorislav Petkov EVENT_CONSTRAINT_END 211e1069839SBorislav Petkov }; 212e1069839SBorislav Petkov 21320f36278SLukasz Odzioba static struct event_constraint intel_skl_event_constraints[] = { 214e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 215e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 216e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 217e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 2189010ae4aSStephane Eranian 2199010ae4aSStephane Eranian /* 2209010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 2219010ae4aSStephane Eranian */ 2229010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 2239010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 2249010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 2259010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 2269010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 2279010ae4aSStephane Eranian 228e1069839SBorislav Petkov EVENT_CONSTRAINT_END 229e1069839SBorislav Petkov }; 230e1069839SBorislav Petkov 231e1069839SBorislav Petkov static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 2329c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 2339c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 234e1069839SBorislav Petkov EVENT_EXTRA_END 235e1069839SBorislav Petkov }; 236e1069839SBorislav Petkov 237e1069839SBorislav Petkov static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 238e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 239e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 240e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 241e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 242e1069839SBorislav Petkov EVENT_EXTRA_END 243e1069839SBorislav Petkov }; 244e1069839SBorislav Petkov 245e1069839SBorislav Petkov static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 246e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 247e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 248e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 249e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 250e1069839SBorislav Petkov EVENT_EXTRA_END 251e1069839SBorislav Petkov }; 252e1069839SBorislav Petkov 253e1069839SBorislav Petkov static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 254e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 255e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 256e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 257e1069839SBorislav Petkov /* 258e1069839SBorislav Petkov * Note the low 8 bits eventsel code is not a continuous field, containing 259e1069839SBorislav Petkov * some #GPing bits. These are masked out. 260e1069839SBorislav Petkov */ 261e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 262e1069839SBorislav Petkov EVENT_EXTRA_END 263e1069839SBorislav Petkov }; 264e1069839SBorislav Petkov 26560176089SKan Liang static struct event_constraint intel_icl_event_constraints[] = { 26660176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 2672de71ee1SStephane Eranian FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 2682de71ee1SStephane Eranian FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 26960176089SKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 27060176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 27160176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 27259a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 27359a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 27459a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 27559a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 27660176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 27760176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 27860176089SKan Liang INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 27960176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 28060176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 28160176089SKan Liang INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 282306e3e91SKan Liang INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 283306e3e91SKan Liang INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 28460176089SKan Liang INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 28560176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 28660176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 28760176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 288ecc2123eSKan Liang INTEL_EVENT_CONSTRAINT(0xef, 0xf), 28960176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 29060176089SKan Liang EVENT_CONSTRAINT_END 29160176089SKan Liang }; 29260176089SKan Liang 29360176089SKan Liang static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 2943b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 2953b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 29660176089SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 29760176089SKan Liang INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 29860176089SKan Liang EVENT_EXTRA_END 29960176089SKan Liang }; 30060176089SKan Liang 30161b985e3SKan Liang static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 30261b985e3SKan Liang INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 30361b985e3SKan Liang INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 30461b985e3SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 30561b985e3SKan Liang INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 306d18216faSKan Liang INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 307d18216faSKan Liang INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 30861b985e3SKan Liang EVENT_EXTRA_END 30961b985e3SKan Liang }; 31061b985e3SKan Liang 31161b985e3SKan Liang static struct event_constraint intel_spr_event_constraints[] = { 31261b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 3132de71ee1SStephane Eranian FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 31461b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 31561b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 31661b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 31761b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 31861b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 31961b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 32061b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 32161b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 32261b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 32361b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 32461b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 32561b985e3SKan Liang 32661b985e3SKan Liang INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 32761b985e3SKan Liang INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 32861b985e3SKan Liang /* 32961b985e3SKan Liang * Generally event codes < 0x90 are restricted to counters 0-3. 33061b985e3SKan Liang * The 0x2E and 0x3C are exception, which has no restriction. 33161b985e3SKan Liang */ 33261b985e3SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 33361b985e3SKan Liang 33461b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 33561b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 33661b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 33761b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 33861b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 33961b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 34061b985e3SKan Liang INTEL_EVENT_CONSTRAINT(0xce, 0x1), 34161b985e3SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 34261b985e3SKan Liang /* 34361b985e3SKan Liang * Generally event codes >= 0x90 are likely to have no restrictions. 34461b985e3SKan Liang * The exception are defined as above. 34561b985e3SKan Liang */ 34661b985e3SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 34761b985e3SKan Liang 34861b985e3SKan Liang EVENT_CONSTRAINT_END 34961b985e3SKan Liang }; 35061b985e3SKan Liang 35161b985e3SKan Liang 352e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 353e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 354e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 355e1069839SBorislav Petkov 356d4ae5529SJiri Olsa static struct attribute *nhm_mem_events_attrs[] = { 357e1069839SBorislav Petkov EVENT_PTR(mem_ld_nhm), 358e1069839SBorislav Petkov NULL, 359e1069839SBorislav Petkov }; 360e1069839SBorislav Petkov 361a39fcae7SAndi Kleen /* 362a39fcae7SAndi Kleen * topdown events for Intel Core CPUs. 363a39fcae7SAndi Kleen * 364a39fcae7SAndi Kleen * The events are all in slots, which is a free slot in a 4 wide 365a39fcae7SAndi Kleen * pipeline. Some events are already reported in slots, for cycle 366a39fcae7SAndi Kleen * events we multiply by the pipeline width (4). 367a39fcae7SAndi Kleen * 368a39fcae7SAndi Kleen * With Hyper Threading on, topdown metrics are either summed or averaged 369a39fcae7SAndi Kleen * between the threads of a core: (count_t0 + count_t1). 370a39fcae7SAndi Kleen * 371a39fcae7SAndi Kleen * For the average case the metric is always scaled to pipeline width, 372a39fcae7SAndi Kleen * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 373a39fcae7SAndi Kleen */ 374a39fcae7SAndi Kleen 375a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 376a39fcae7SAndi Kleen "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 377a39fcae7SAndi Kleen "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 378a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 379a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 380a39fcae7SAndi Kleen "event=0xe,umask=0x1"); /* uops_issued.any */ 381a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 382a39fcae7SAndi Kleen "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 383a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 384a39fcae7SAndi Kleen "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 385a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 386a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 387a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 388a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 389a39fcae7SAndi Kleen "4", "2"); 390a39fcae7SAndi Kleen 39159a854e2SKan Liang EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 39259a854e2SKan Liang EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 39359a854e2SKan Liang EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 39459a854e2SKan Liang EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 39559a854e2SKan Liang EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 39661b985e3SKan Liang EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 39761b985e3SKan Liang EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 39861b985e3SKan Liang EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 39961b985e3SKan Liang EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 40059a854e2SKan Liang 40120f36278SLukasz Odzioba static struct attribute *snb_events_attrs[] = { 402a39fcae7SAndi Kleen EVENT_PTR(td_slots_issued), 403a39fcae7SAndi Kleen EVENT_PTR(td_slots_retired), 404a39fcae7SAndi Kleen EVENT_PTR(td_fetch_bubbles), 405a39fcae7SAndi Kleen EVENT_PTR(td_total_slots), 406a39fcae7SAndi Kleen EVENT_PTR(td_total_slots_scale), 407a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles), 408a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 409e1069839SBorislav Petkov NULL, 410e1069839SBorislav Petkov }; 411e1069839SBorislav Petkov 412d4ae5529SJiri Olsa static struct attribute *snb_mem_events_attrs[] = { 413d4ae5529SJiri Olsa EVENT_PTR(mem_ld_snb), 414d4ae5529SJiri Olsa EVENT_PTR(mem_st_snb), 415d4ae5529SJiri Olsa NULL, 416d4ae5529SJiri Olsa }; 417d4ae5529SJiri Olsa 418e1069839SBorislav Petkov static struct event_constraint intel_hsw_event_constraints[] = { 419e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 420e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 421e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 422e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 423e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 424e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 425e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 426e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 427e1069839SBorislav Petkov /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 428e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 429e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 430e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 431e1069839SBorislav Petkov 4329010ae4aSStephane Eranian /* 4339010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 4349010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 4359010ae4aSStephane Eranian */ 436e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 437e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 438e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 439e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 440e1069839SBorislav Petkov 441e1069839SBorislav Petkov EVENT_CONSTRAINT_END 442e1069839SBorislav Petkov }; 443e1069839SBorislav Petkov 44420f36278SLukasz Odzioba static struct event_constraint intel_bdw_event_constraints[] = { 445e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 446e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 447e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 448e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 449e1069839SBorislav Petkov INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 4509010ae4aSStephane Eranian /* 4519010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 4529010ae4aSStephane Eranian */ 4539010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 4549010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 4559010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 4569010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 457e1069839SBorislav Petkov EVENT_CONSTRAINT_END 458e1069839SBorislav Petkov }; 459e1069839SBorislav Petkov 460e1069839SBorislav Petkov static u64 intel_pmu_event_map(int hw_event) 461e1069839SBorislav Petkov { 462e1069839SBorislav Petkov return intel_perfmon_event_map[hw_event]; 463e1069839SBorislav Petkov } 464e1069839SBorislav Petkov 46561b985e3SKan Liang static __initconst const u64 spr_hw_cache_event_ids 46661b985e3SKan Liang [PERF_COUNT_HW_CACHE_MAX] 46761b985e3SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 46861b985e3SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = 46961b985e3SKan Liang { 47061b985e3SKan Liang [ C(L1D ) ] = { 47161b985e3SKan Liang [ C(OP_READ) ] = { 47261b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x81d0, 47361b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe124, 47461b985e3SKan Liang }, 47561b985e3SKan Liang [ C(OP_WRITE) ] = { 47661b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x82d0, 47761b985e3SKan Liang }, 47861b985e3SKan Liang }, 47961b985e3SKan Liang [ C(L1I ) ] = { 48061b985e3SKan Liang [ C(OP_READ) ] = { 48161b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe424, 48261b985e3SKan Liang }, 48361b985e3SKan Liang [ C(OP_WRITE) ] = { 48461b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 48561b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 48661b985e3SKan Liang }, 48761b985e3SKan Liang }, 48861b985e3SKan Liang [ C(LL ) ] = { 48961b985e3SKan Liang [ C(OP_READ) ] = { 49061b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x12a, 49161b985e3SKan Liang [ C(RESULT_MISS) ] = 0x12a, 49261b985e3SKan Liang }, 49361b985e3SKan Liang [ C(OP_WRITE) ] = { 49461b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x12a, 49561b985e3SKan Liang [ C(RESULT_MISS) ] = 0x12a, 49661b985e3SKan Liang }, 49761b985e3SKan Liang }, 49861b985e3SKan Liang [ C(DTLB) ] = { 49961b985e3SKan Liang [ C(OP_READ) ] = { 50061b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x81d0, 50161b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe12, 50261b985e3SKan Liang }, 50361b985e3SKan Liang [ C(OP_WRITE) ] = { 50461b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x82d0, 50561b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe13, 50661b985e3SKan Liang }, 50761b985e3SKan Liang }, 50861b985e3SKan Liang [ C(ITLB) ] = { 50961b985e3SKan Liang [ C(OP_READ) ] = { 51061b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 51161b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe11, 51261b985e3SKan Liang }, 51361b985e3SKan Liang [ C(OP_WRITE) ] = { 51461b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 51561b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 51661b985e3SKan Liang }, 51761b985e3SKan Liang [ C(OP_PREFETCH) ] = { 51861b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 51961b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 52061b985e3SKan Liang }, 52161b985e3SKan Liang }, 52261b985e3SKan Liang [ C(BPU ) ] = { 52361b985e3SKan Liang [ C(OP_READ) ] = { 52461b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x4c4, 52561b985e3SKan Liang [ C(RESULT_MISS) ] = 0x4c5, 52661b985e3SKan Liang }, 52761b985e3SKan Liang [ C(OP_WRITE) ] = { 52861b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 52961b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 53061b985e3SKan Liang }, 53161b985e3SKan Liang [ C(OP_PREFETCH) ] = { 53261b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 53361b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 53461b985e3SKan Liang }, 53561b985e3SKan Liang }, 53661b985e3SKan Liang [ C(NODE) ] = { 53761b985e3SKan Liang [ C(OP_READ) ] = { 53861b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x12a, 53961b985e3SKan Liang [ C(RESULT_MISS) ] = 0x12a, 54061b985e3SKan Liang }, 54161b985e3SKan Liang }, 54261b985e3SKan Liang }; 54361b985e3SKan Liang 54461b985e3SKan Liang static __initconst const u64 spr_hw_cache_extra_regs 54561b985e3SKan Liang [PERF_COUNT_HW_CACHE_MAX] 54661b985e3SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 54761b985e3SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = 54861b985e3SKan Liang { 54961b985e3SKan Liang [ C(LL ) ] = { 55061b985e3SKan Liang [ C(OP_READ) ] = { 55161b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x10001, 55261b985e3SKan Liang [ C(RESULT_MISS) ] = 0x3fbfc00001, 55361b985e3SKan Liang }, 55461b985e3SKan Liang [ C(OP_WRITE) ] = { 55561b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 55661b985e3SKan Liang [ C(RESULT_MISS) ] = 0x3f3fc00002, 55761b985e3SKan Liang }, 55861b985e3SKan Liang }, 55961b985e3SKan Liang [ C(NODE) ] = { 56061b985e3SKan Liang [ C(OP_READ) ] = { 56161b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x10c000001, 56261b985e3SKan Liang [ C(RESULT_MISS) ] = 0x3fb3000001, 56361b985e3SKan Liang }, 56461b985e3SKan Liang }, 56561b985e3SKan Liang }; 56661b985e3SKan Liang 567e1069839SBorislav Petkov /* 568e1069839SBorislav Petkov * Notes on the events: 569e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 570e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 571e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 572e1069839SBorislav Petkov * - prefetches are not included in the counts. 573e1069839SBorislav Petkov * - icache miss does not include decoded icache 574e1069839SBorislav Petkov */ 575e1069839SBorislav Petkov 576e1069839SBorislav Petkov #define SKL_DEMAND_DATA_RD BIT_ULL(0) 577e1069839SBorislav Petkov #define SKL_DEMAND_RFO BIT_ULL(1) 578e1069839SBorislav Petkov #define SKL_ANY_RESPONSE BIT_ULL(16) 579e1069839SBorislav Petkov #define SKL_SUPPLIER_NONE BIT_ULL(17) 580e1069839SBorislav Petkov #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 581e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 582e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 583e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 584e1069839SBorislav Petkov #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 585e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 586e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 587e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 588e1069839SBorislav Petkov #define SKL_SPL_HIT BIT_ULL(30) 589e1069839SBorislav Petkov #define SKL_SNOOP_NONE BIT_ULL(31) 590e1069839SBorislav Petkov #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 591e1069839SBorislav Petkov #define SKL_SNOOP_MISS BIT_ULL(33) 592e1069839SBorislav Petkov #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 593e1069839SBorislav Petkov #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 594e1069839SBorislav Petkov #define SKL_SNOOP_HITM BIT_ULL(36) 595e1069839SBorislav Petkov #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 596e1069839SBorislav Petkov #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 597e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 598e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 599e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 600e1069839SBorislav Petkov #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 601e1069839SBorislav Petkov #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 602e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 603e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 604e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SPL_HIT) 605e1069839SBorislav Petkov #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 606e1069839SBorislav Petkov #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 607e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 608e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 609e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 610e1069839SBorislav Petkov 611e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_event_ids 612e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 613e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 614e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 615e1069839SBorislav Petkov { 616e1069839SBorislav Petkov [ C(L1D ) ] = { 617e1069839SBorislav Petkov [ C(OP_READ) ] = { 618e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 619e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 620e1069839SBorislav Petkov }, 621e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 622e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 623e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 624e1069839SBorislav Petkov }, 625e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 626e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 627e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 628e1069839SBorislav Petkov }, 629e1069839SBorislav Petkov }, 630e1069839SBorislav Petkov [ C(L1I ) ] = { 631e1069839SBorislav Petkov [ C(OP_READ) ] = { 632e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 633e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 634e1069839SBorislav Petkov }, 635e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 636e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 637e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 638e1069839SBorislav Petkov }, 639e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 640e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 641e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 642e1069839SBorislav Petkov }, 643e1069839SBorislav Petkov }, 644e1069839SBorislav Petkov [ C(LL ) ] = { 645e1069839SBorislav Petkov [ C(OP_READ) ] = { 646e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 647e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 648e1069839SBorislav Petkov }, 649e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 650e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 651e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 652e1069839SBorislav Petkov }, 653e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 654e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 655e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 656e1069839SBorislav Petkov }, 657e1069839SBorislav Petkov }, 658e1069839SBorislav Petkov [ C(DTLB) ] = { 659e1069839SBorislav Petkov [ C(OP_READ) ] = { 660e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 661fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 662e1069839SBorislav Petkov }, 663e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 664e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 665fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 666e1069839SBorislav Petkov }, 667e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 668e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 669e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 670e1069839SBorislav Petkov }, 671e1069839SBorislav Petkov }, 672e1069839SBorislav Petkov [ C(ITLB) ] = { 673e1069839SBorislav Petkov [ C(OP_READ) ] = { 674e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 675e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 676e1069839SBorislav Petkov }, 677e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 678e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 679e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 680e1069839SBorislav Petkov }, 681e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 682e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 683e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 684e1069839SBorislav Petkov }, 685e1069839SBorislav Petkov }, 686e1069839SBorislav Petkov [ C(BPU ) ] = { 687e1069839SBorislav Petkov [ C(OP_READ) ] = { 688e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 689e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 690e1069839SBorislav Petkov }, 691e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 692e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 693e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 694e1069839SBorislav Petkov }, 695e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 696e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 697e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 698e1069839SBorislav Petkov }, 699e1069839SBorislav Petkov }, 700e1069839SBorislav Petkov [ C(NODE) ] = { 701e1069839SBorislav Petkov [ C(OP_READ) ] = { 702e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 703e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 704e1069839SBorislav Petkov }, 705e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 706e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 707e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 708e1069839SBorislav Petkov }, 709e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 710e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 711e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 712e1069839SBorislav Petkov }, 713e1069839SBorislav Petkov }, 714e1069839SBorislav Petkov }; 715e1069839SBorislav Petkov 716e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_extra_regs 717e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 718e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 719e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 720e1069839SBorislav Petkov { 721e1069839SBorislav Petkov [ C(LL ) ] = { 722e1069839SBorislav Petkov [ C(OP_READ) ] = { 723e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 724e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 725e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 726e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 727e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 728e1069839SBorislav Petkov }, 729e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 730e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 731e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 732e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 733e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 734e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 735e1069839SBorislav Petkov }, 736e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 737e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 738e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 739e1069839SBorislav Petkov }, 740e1069839SBorislav Petkov }, 741e1069839SBorislav Petkov [ C(NODE) ] = { 742e1069839SBorislav Petkov [ C(OP_READ) ] = { 743e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 744e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 745e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 746e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 747e1069839SBorislav Petkov }, 748e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 749e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 750e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 751e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 752e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 753e1069839SBorislav Petkov }, 754e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 755e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 756e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 757e1069839SBorislav Petkov }, 758e1069839SBorislav Petkov }, 759e1069839SBorislav Petkov }; 760e1069839SBorislav Petkov 761e1069839SBorislav Petkov #define SNB_DMND_DATA_RD (1ULL << 0) 762e1069839SBorislav Petkov #define SNB_DMND_RFO (1ULL << 1) 763e1069839SBorislav Petkov #define SNB_DMND_IFETCH (1ULL << 2) 764e1069839SBorislav Petkov #define SNB_DMND_WB (1ULL << 3) 765e1069839SBorislav Petkov #define SNB_PF_DATA_RD (1ULL << 4) 766e1069839SBorislav Petkov #define SNB_PF_RFO (1ULL << 5) 767e1069839SBorislav Petkov #define SNB_PF_IFETCH (1ULL << 6) 768e1069839SBorislav Petkov #define SNB_LLC_DATA_RD (1ULL << 7) 769e1069839SBorislav Petkov #define SNB_LLC_RFO (1ULL << 8) 770e1069839SBorislav Petkov #define SNB_LLC_IFETCH (1ULL << 9) 771e1069839SBorislav Petkov #define SNB_BUS_LOCKS (1ULL << 10) 772e1069839SBorislav Petkov #define SNB_STRM_ST (1ULL << 11) 773e1069839SBorislav Petkov #define SNB_OTHER (1ULL << 15) 774e1069839SBorislav Petkov #define SNB_RESP_ANY (1ULL << 16) 775e1069839SBorislav Petkov #define SNB_NO_SUPP (1ULL << 17) 776e1069839SBorislav Petkov #define SNB_LLC_HITM (1ULL << 18) 777e1069839SBorislav Petkov #define SNB_LLC_HITE (1ULL << 19) 778e1069839SBorislav Petkov #define SNB_LLC_HITS (1ULL << 20) 779e1069839SBorislav Petkov #define SNB_LLC_HITF (1ULL << 21) 780e1069839SBorislav Petkov #define SNB_LOCAL (1ULL << 22) 781e1069839SBorislav Petkov #define SNB_REMOTE (0xffULL << 23) 782e1069839SBorislav Petkov #define SNB_SNP_NONE (1ULL << 31) 783e1069839SBorislav Petkov #define SNB_SNP_NOT_NEEDED (1ULL << 32) 784e1069839SBorislav Petkov #define SNB_SNP_MISS (1ULL << 33) 785e1069839SBorislav Petkov #define SNB_NO_FWD (1ULL << 34) 786e1069839SBorislav Petkov #define SNB_SNP_FWD (1ULL << 35) 787e1069839SBorislav Petkov #define SNB_HITM (1ULL << 36) 788e1069839SBorislav Petkov #define SNB_NON_DRAM (1ULL << 37) 789e1069839SBorislav Petkov 790e1069839SBorislav Petkov #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 791e1069839SBorislav Petkov #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 792e1069839SBorislav Petkov #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 793e1069839SBorislav Petkov 794e1069839SBorislav Petkov #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 795e1069839SBorislav Petkov SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 796e1069839SBorislav Petkov SNB_HITM) 797e1069839SBorislav Petkov 798e1069839SBorislav Petkov #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 799e1069839SBorislav Petkov #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 800e1069839SBorislav Petkov 801e1069839SBorislav Petkov #define SNB_L3_ACCESS SNB_RESP_ANY 802e1069839SBorislav Petkov #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 803e1069839SBorislav Petkov 804e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_extra_regs 805e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 806e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 807e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 808e1069839SBorislav Petkov { 809e1069839SBorislav Petkov [ C(LL ) ] = { 810e1069839SBorislav Petkov [ C(OP_READ) ] = { 811e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 812e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 813e1069839SBorislav Petkov }, 814e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 815e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 816e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 817e1069839SBorislav Petkov }, 818e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 819e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 820e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 821e1069839SBorislav Petkov }, 822e1069839SBorislav Petkov }, 823e1069839SBorislav Petkov [ C(NODE) ] = { 824e1069839SBorislav Petkov [ C(OP_READ) ] = { 825e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 826e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 827e1069839SBorislav Petkov }, 828e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 829e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 830e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 831e1069839SBorislav Petkov }, 832e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 833e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 834e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 835e1069839SBorislav Petkov }, 836e1069839SBorislav Petkov }, 837e1069839SBorislav Petkov }; 838e1069839SBorislav Petkov 839e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_event_ids 840e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 841e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 842e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 843e1069839SBorislav Petkov { 844e1069839SBorislav Petkov [ C(L1D) ] = { 845e1069839SBorislav Petkov [ C(OP_READ) ] = { 846e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 847e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 848e1069839SBorislav Petkov }, 849e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 850e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 851e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 852e1069839SBorislav Petkov }, 853e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 854e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 855e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 856e1069839SBorislav Petkov }, 857e1069839SBorislav Petkov }, 858e1069839SBorislav Petkov [ C(L1I ) ] = { 859e1069839SBorislav Petkov [ C(OP_READ) ] = { 860e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 861e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 862e1069839SBorislav Petkov }, 863e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 864e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 865e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 866e1069839SBorislav Petkov }, 867e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 868e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 869e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 870e1069839SBorislav Petkov }, 871e1069839SBorislav Petkov }, 872e1069839SBorislav Petkov [ C(LL ) ] = { 873e1069839SBorislav Petkov [ C(OP_READ) ] = { 874e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 875e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 876e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 877e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 878e1069839SBorislav Petkov }, 879e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 880e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 881e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 882e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 883e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 884e1069839SBorislav Petkov }, 885e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 886e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 887e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 888e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 889e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 890e1069839SBorislav Petkov }, 891e1069839SBorislav Petkov }, 892e1069839SBorislav Petkov [ C(DTLB) ] = { 893e1069839SBorislav Petkov [ C(OP_READ) ] = { 894e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 895e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 896e1069839SBorislav Petkov }, 897e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 898e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 899e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 900e1069839SBorislav Petkov }, 901e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 902e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 903e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 904e1069839SBorislav Petkov }, 905e1069839SBorislav Petkov }, 906e1069839SBorislav Petkov [ C(ITLB) ] = { 907e1069839SBorislav Petkov [ C(OP_READ) ] = { 908e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 909e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 910e1069839SBorislav Petkov }, 911e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 912e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 913e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 914e1069839SBorislav Petkov }, 915e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 916e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 917e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 918e1069839SBorislav Petkov }, 919e1069839SBorislav Petkov }, 920e1069839SBorislav Petkov [ C(BPU ) ] = { 921e1069839SBorislav Petkov [ C(OP_READ) ] = { 922e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 923e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 924e1069839SBorislav Petkov }, 925e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 926e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 927e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 928e1069839SBorislav Petkov }, 929e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 930e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 931e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 932e1069839SBorislav Petkov }, 933e1069839SBorislav Petkov }, 934e1069839SBorislav Petkov [ C(NODE) ] = { 935e1069839SBorislav Petkov [ C(OP_READ) ] = { 936e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 937e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 938e1069839SBorislav Petkov }, 939e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 940e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 941e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 942e1069839SBorislav Petkov }, 943e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 944e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 945e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 946e1069839SBorislav Petkov }, 947e1069839SBorislav Petkov }, 948e1069839SBorislav Petkov 949e1069839SBorislav Petkov }; 950e1069839SBorislav Petkov 951e1069839SBorislav Petkov /* 952e1069839SBorislav Petkov * Notes on the events: 953e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 954e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 955e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 956e1069839SBorislav Petkov * - prefetches are not included in the counts because they are not 957e1069839SBorislav Petkov * reliably counted. 958e1069839SBorislav Petkov */ 959e1069839SBorislav Petkov 960e1069839SBorislav Petkov #define HSW_DEMAND_DATA_RD BIT_ULL(0) 961e1069839SBorislav Petkov #define HSW_DEMAND_RFO BIT_ULL(1) 962e1069839SBorislav Petkov #define HSW_ANY_RESPONSE BIT_ULL(16) 963e1069839SBorislav Petkov #define HSW_SUPPLIER_NONE BIT_ULL(17) 964e1069839SBorislav Petkov #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 965e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 966e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 967e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 968e1069839SBorislav Petkov #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 969e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 970e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 971e1069839SBorislav Petkov #define HSW_SNOOP_NONE BIT_ULL(31) 972e1069839SBorislav Petkov #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 973e1069839SBorislav Petkov #define HSW_SNOOP_MISS BIT_ULL(33) 974e1069839SBorislav Petkov #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 975e1069839SBorislav Petkov #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 976e1069839SBorislav Petkov #define HSW_SNOOP_HITM BIT_ULL(36) 977e1069839SBorislav Petkov #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 978e1069839SBorislav Petkov #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 979e1069839SBorislav Petkov HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 980e1069839SBorislav Petkov HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 981e1069839SBorislav Petkov HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 982e1069839SBorislav Petkov #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 983e1069839SBorislav Petkov #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 984e1069839SBorislav Petkov #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 985e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 986e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 987e1069839SBorislav Petkov #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 988e1069839SBorislav Petkov 989e1069839SBorislav Petkov #define BDW_L3_MISS_LOCAL BIT(26) 990e1069839SBorislav Petkov #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 991e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 992e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 993e1069839SBorislav Petkov 994e1069839SBorislav Petkov 995e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_event_ids 996e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 997e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 998e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 999e1069839SBorislav Petkov { 1000e1069839SBorislav Petkov [ C(L1D ) ] = { 1001e1069839SBorislav Petkov [ C(OP_READ) ] = { 1002e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1003e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1004e1069839SBorislav Petkov }, 1005e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1006e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1007e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1008e1069839SBorislav Petkov }, 1009e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1010e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1011e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1012e1069839SBorislav Petkov }, 1013e1069839SBorislav Petkov }, 1014e1069839SBorislav Petkov [ C(L1I ) ] = { 1015e1069839SBorislav Petkov [ C(OP_READ) ] = { 1016e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1017e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1018e1069839SBorislav Petkov }, 1019e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1020e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1021e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1022e1069839SBorislav Petkov }, 1023e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1024e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1025e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1026e1069839SBorislav Petkov }, 1027e1069839SBorislav Petkov }, 1028e1069839SBorislav Petkov [ C(LL ) ] = { 1029e1069839SBorislav Petkov [ C(OP_READ) ] = { 1030e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1031e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1032e1069839SBorislav Petkov }, 1033e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1034e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1035e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1036e1069839SBorislav Petkov }, 1037e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1038e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1039e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1040e1069839SBorislav Petkov }, 1041e1069839SBorislav Petkov }, 1042e1069839SBorislav Petkov [ C(DTLB) ] = { 1043e1069839SBorislav Petkov [ C(OP_READ) ] = { 1044e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1045e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1046e1069839SBorislav Petkov }, 1047e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1048e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1049e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1050e1069839SBorislav Petkov }, 1051e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1052e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1053e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1054e1069839SBorislav Petkov }, 1055e1069839SBorislav Petkov }, 1056e1069839SBorislav Petkov [ C(ITLB) ] = { 1057e1069839SBorislav Petkov [ C(OP_READ) ] = { 1058e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1059e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1060e1069839SBorislav Petkov }, 1061e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1062e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1063e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1064e1069839SBorislav Petkov }, 1065e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1066e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1067e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1068e1069839SBorislav Petkov }, 1069e1069839SBorislav Petkov }, 1070e1069839SBorislav Petkov [ C(BPU ) ] = { 1071e1069839SBorislav Petkov [ C(OP_READ) ] = { 1072e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1073e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1074e1069839SBorislav Petkov }, 1075e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1076e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1077e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1078e1069839SBorislav Petkov }, 1079e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1080e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1081e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1082e1069839SBorislav Petkov }, 1083e1069839SBorislav Petkov }, 1084e1069839SBorislav Petkov [ C(NODE) ] = { 1085e1069839SBorislav Petkov [ C(OP_READ) ] = { 1086e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1087e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1088e1069839SBorislav Petkov }, 1089e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1090e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1091e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1092e1069839SBorislav Petkov }, 1093e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1094e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1095e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1096e1069839SBorislav Petkov }, 1097e1069839SBorislav Petkov }, 1098e1069839SBorislav Petkov }; 1099e1069839SBorislav Petkov 1100e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_extra_regs 1101e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1102e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1103e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1104e1069839SBorislav Petkov { 1105e1069839SBorislav Petkov [ C(LL ) ] = { 1106e1069839SBorislav Petkov [ C(OP_READ) ] = { 1107e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1108e1069839SBorislav Petkov HSW_LLC_ACCESS, 1109e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1110e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 1111e1069839SBorislav Petkov }, 1112e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1113e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1114e1069839SBorislav Petkov HSW_LLC_ACCESS, 1115e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1116e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 1117e1069839SBorislav Petkov }, 1118e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1119e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1120e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1121e1069839SBorislav Petkov }, 1122e1069839SBorislav Petkov }, 1123e1069839SBorislav Petkov [ C(NODE) ] = { 1124e1069839SBorislav Petkov [ C(OP_READ) ] = { 1125e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1126e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 1127e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1128e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1129e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 1130e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1131e1069839SBorislav Petkov }, 1132e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1133e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1134e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 1135e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1136e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1137e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 1138e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1139e1069839SBorislav Petkov }, 1140e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1141e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1142e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1143e1069839SBorislav Petkov }, 1144e1069839SBorislav Petkov }, 1145e1069839SBorislav Petkov }; 1146e1069839SBorislav Petkov 1147e1069839SBorislav Petkov static __initconst const u64 westmere_hw_cache_event_ids 1148e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1149e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1150e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1151e1069839SBorislav Petkov { 1152e1069839SBorislav Petkov [ C(L1D) ] = { 1153e1069839SBorislav Petkov [ C(OP_READ) ] = { 1154e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1155e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1156e1069839SBorislav Petkov }, 1157e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1158e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1159e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1160e1069839SBorislav Petkov }, 1161e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1162e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1163e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1164e1069839SBorislav Petkov }, 1165e1069839SBorislav Petkov }, 1166e1069839SBorislav Petkov [ C(L1I ) ] = { 1167e1069839SBorislav Petkov [ C(OP_READ) ] = { 1168e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1169e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1170e1069839SBorislav Petkov }, 1171e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1172e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1173e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1174e1069839SBorislav Petkov }, 1175e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1176e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1177e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1178e1069839SBorislav Petkov }, 1179e1069839SBorislav Petkov }, 1180e1069839SBorislav Petkov [ C(LL ) ] = { 1181e1069839SBorislav Petkov [ C(OP_READ) ] = { 1182e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1183e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1184e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1185e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1186e1069839SBorislav Petkov }, 1187e1069839SBorislav Petkov /* 1188e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1189e1069839SBorislav Petkov * on RFO. 1190e1069839SBorislav Petkov */ 1191e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1192e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1193e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1194e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1195e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1196e1069839SBorislav Petkov }, 1197e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1198e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1199e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1200e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1201e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1202e1069839SBorislav Petkov }, 1203e1069839SBorislav Petkov }, 1204e1069839SBorislav Petkov [ C(DTLB) ] = { 1205e1069839SBorislav Petkov [ C(OP_READ) ] = { 1206e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1207e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1208e1069839SBorislav Petkov }, 1209e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1210e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1211e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1212e1069839SBorislav Petkov }, 1213e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1214e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1215e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1216e1069839SBorislav Petkov }, 1217e1069839SBorislav Petkov }, 1218e1069839SBorislav Petkov [ C(ITLB) ] = { 1219e1069839SBorislav Petkov [ C(OP_READ) ] = { 1220e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1221e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1222e1069839SBorislav Petkov }, 1223e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1224e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1225e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1226e1069839SBorislav Petkov }, 1227e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1228e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1229e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1230e1069839SBorislav Petkov }, 1231e1069839SBorislav Petkov }, 1232e1069839SBorislav Petkov [ C(BPU ) ] = { 1233e1069839SBorislav Petkov [ C(OP_READ) ] = { 1234e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1235e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1236e1069839SBorislav Petkov }, 1237e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1238e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1239e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1240e1069839SBorislav Petkov }, 1241e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1242e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1243e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1244e1069839SBorislav Petkov }, 1245e1069839SBorislav Petkov }, 1246e1069839SBorislav Petkov [ C(NODE) ] = { 1247e1069839SBorislav Petkov [ C(OP_READ) ] = { 1248e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1249e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1250e1069839SBorislav Petkov }, 1251e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1252e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1253e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1254e1069839SBorislav Petkov }, 1255e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1256e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1257e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1258e1069839SBorislav Petkov }, 1259e1069839SBorislav Petkov }, 1260e1069839SBorislav Petkov }; 1261e1069839SBorislav Petkov 1262e1069839SBorislav Petkov /* 1263e1069839SBorislav Petkov * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1264e1069839SBorislav Petkov * See IA32 SDM Vol 3B 30.6.1.3 1265e1069839SBorislav Petkov */ 1266e1069839SBorislav Petkov 1267e1069839SBorislav Petkov #define NHM_DMND_DATA_RD (1 << 0) 1268e1069839SBorislav Petkov #define NHM_DMND_RFO (1 << 1) 1269e1069839SBorislav Petkov #define NHM_DMND_IFETCH (1 << 2) 1270e1069839SBorislav Petkov #define NHM_DMND_WB (1 << 3) 1271e1069839SBorislav Petkov #define NHM_PF_DATA_RD (1 << 4) 1272e1069839SBorislav Petkov #define NHM_PF_DATA_RFO (1 << 5) 1273e1069839SBorislav Petkov #define NHM_PF_IFETCH (1 << 6) 1274e1069839SBorislav Petkov #define NHM_OFFCORE_OTHER (1 << 7) 1275e1069839SBorislav Petkov #define NHM_UNCORE_HIT (1 << 8) 1276e1069839SBorislav Petkov #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1277e1069839SBorislav Petkov #define NHM_OTHER_CORE_HITM (1 << 10) 1278e1069839SBorislav Petkov /* reserved */ 1279e1069839SBorislav Petkov #define NHM_REMOTE_CACHE_FWD (1 << 12) 1280e1069839SBorislav Petkov #define NHM_REMOTE_DRAM (1 << 13) 1281e1069839SBorislav Petkov #define NHM_LOCAL_DRAM (1 << 14) 1282e1069839SBorislav Petkov #define NHM_NON_DRAM (1 << 15) 1283e1069839SBorislav Petkov 1284e1069839SBorislav Petkov #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1285e1069839SBorislav Petkov #define NHM_REMOTE (NHM_REMOTE_DRAM) 1286e1069839SBorislav Petkov 1287e1069839SBorislav Petkov #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1288e1069839SBorislav Petkov #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1289e1069839SBorislav Petkov #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1290e1069839SBorislav Petkov 1291e1069839SBorislav Petkov #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1292e1069839SBorislav Petkov #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1293e1069839SBorislav Petkov #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1294e1069839SBorislav Petkov 1295e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_extra_regs 1296e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1297e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1298e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1299e1069839SBorislav Petkov { 1300e1069839SBorislav Petkov [ C(LL ) ] = { 1301e1069839SBorislav Petkov [ C(OP_READ) ] = { 1302e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1303e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1304e1069839SBorislav Petkov }, 1305e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1306e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1307e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1308e1069839SBorislav Petkov }, 1309e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1310e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1311e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1312e1069839SBorislav Petkov }, 1313e1069839SBorislav Petkov }, 1314e1069839SBorislav Petkov [ C(NODE) ] = { 1315e1069839SBorislav Petkov [ C(OP_READ) ] = { 1316e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1317e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1318e1069839SBorislav Petkov }, 1319e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1320e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1321e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1322e1069839SBorislav Petkov }, 1323e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1324e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1325e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1326e1069839SBorislav Petkov }, 1327e1069839SBorislav Petkov }, 1328e1069839SBorislav Petkov }; 1329e1069839SBorislav Petkov 1330e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_event_ids 1331e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1332e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1333e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1334e1069839SBorislav Petkov { 1335e1069839SBorislav Petkov [ C(L1D) ] = { 1336e1069839SBorislav Petkov [ C(OP_READ) ] = { 1337e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1338e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1339e1069839SBorislav Petkov }, 1340e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1341e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1342e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1343e1069839SBorislav Petkov }, 1344e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1345e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1346e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1347e1069839SBorislav Petkov }, 1348e1069839SBorislav Petkov }, 1349e1069839SBorislav Petkov [ C(L1I ) ] = { 1350e1069839SBorislav Petkov [ C(OP_READ) ] = { 1351e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1352e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1353e1069839SBorislav Petkov }, 1354e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1355e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1356e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1357e1069839SBorislav Petkov }, 1358e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1359e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1360e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1361e1069839SBorislav Petkov }, 1362e1069839SBorislav Petkov }, 1363e1069839SBorislav Petkov [ C(LL ) ] = { 1364e1069839SBorislav Petkov [ C(OP_READ) ] = { 1365e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1366e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1367e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1368e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1369e1069839SBorislav Petkov }, 1370e1069839SBorislav Petkov /* 1371e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1372e1069839SBorislav Petkov * on RFO. 1373e1069839SBorislav Petkov */ 1374e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1375e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1376e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1377e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1378e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1379e1069839SBorislav Petkov }, 1380e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1381e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1382e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1383e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1384e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1385e1069839SBorislav Petkov }, 1386e1069839SBorislav Petkov }, 1387e1069839SBorislav Petkov [ C(DTLB) ] = { 1388e1069839SBorislav Petkov [ C(OP_READ) ] = { 1389e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1390e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1391e1069839SBorislav Petkov }, 1392e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1393e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1394e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1395e1069839SBorislav Petkov }, 1396e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1397e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1398e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1399e1069839SBorislav Petkov }, 1400e1069839SBorislav Petkov }, 1401e1069839SBorislav Petkov [ C(ITLB) ] = { 1402e1069839SBorislav Petkov [ C(OP_READ) ] = { 1403e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1404e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1405e1069839SBorislav Petkov }, 1406e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1407e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1408e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1409e1069839SBorislav Petkov }, 1410e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1411e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1412e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1413e1069839SBorislav Petkov }, 1414e1069839SBorislav Petkov }, 1415e1069839SBorislav Petkov [ C(BPU ) ] = { 1416e1069839SBorislav Petkov [ C(OP_READ) ] = { 1417e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1418e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1419e1069839SBorislav Petkov }, 1420e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1421e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1422e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1423e1069839SBorislav Petkov }, 1424e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1425e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1426e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1427e1069839SBorislav Petkov }, 1428e1069839SBorislav Petkov }, 1429e1069839SBorislav Petkov [ C(NODE) ] = { 1430e1069839SBorislav Petkov [ C(OP_READ) ] = { 1431e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1432e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1433e1069839SBorislav Petkov }, 1434e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1435e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1436e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1437e1069839SBorislav Petkov }, 1438e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1439e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1440e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1441e1069839SBorislav Petkov }, 1442e1069839SBorislav Petkov }, 1443e1069839SBorislav Petkov }; 1444e1069839SBorislav Petkov 1445e1069839SBorislav Petkov static __initconst const u64 core2_hw_cache_event_ids 1446e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1447e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1448e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1449e1069839SBorislav Petkov { 1450e1069839SBorislav Petkov [ C(L1D) ] = { 1451e1069839SBorislav Petkov [ C(OP_READ) ] = { 1452e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1453e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1454e1069839SBorislav Petkov }, 1455e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1456e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1457e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1458e1069839SBorislav Petkov }, 1459e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1460e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1461e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1462e1069839SBorislav Petkov }, 1463e1069839SBorislav Petkov }, 1464e1069839SBorislav Petkov [ C(L1I ) ] = { 1465e1069839SBorislav Petkov [ C(OP_READ) ] = { 1466e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1467e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1468e1069839SBorislav Petkov }, 1469e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1470e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1471e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1472e1069839SBorislav Petkov }, 1473e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1474e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1475e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1476e1069839SBorislav Petkov }, 1477e1069839SBorislav Petkov }, 1478e1069839SBorislav Petkov [ C(LL ) ] = { 1479e1069839SBorislav Petkov [ C(OP_READ) ] = { 1480e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1481e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1482e1069839SBorislav Petkov }, 1483e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1484e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1485e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1486e1069839SBorislav Petkov }, 1487e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1488e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1489e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1490e1069839SBorislav Petkov }, 1491e1069839SBorislav Petkov }, 1492e1069839SBorislav Petkov [ C(DTLB) ] = { 1493e1069839SBorislav Petkov [ C(OP_READ) ] = { 1494e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1495e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1496e1069839SBorislav Petkov }, 1497e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1498e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1499e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1500e1069839SBorislav Petkov }, 1501e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1502e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1503e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1504e1069839SBorislav Petkov }, 1505e1069839SBorislav Petkov }, 1506e1069839SBorislav Petkov [ C(ITLB) ] = { 1507e1069839SBorislav Petkov [ C(OP_READ) ] = { 1508e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1509e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1510e1069839SBorislav Petkov }, 1511e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1512e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1513e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1514e1069839SBorislav Petkov }, 1515e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1516e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1517e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1518e1069839SBorislav Petkov }, 1519e1069839SBorislav Petkov }, 1520e1069839SBorislav Petkov [ C(BPU ) ] = { 1521e1069839SBorislav Petkov [ C(OP_READ) ] = { 1522e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1523e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1524e1069839SBorislav Petkov }, 1525e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1526e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1527e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1528e1069839SBorislav Petkov }, 1529e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1530e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1531e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1532e1069839SBorislav Petkov }, 1533e1069839SBorislav Petkov }, 1534e1069839SBorislav Petkov }; 1535e1069839SBorislav Petkov 1536e1069839SBorislav Petkov static __initconst const u64 atom_hw_cache_event_ids 1537e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1538e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1539e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1540e1069839SBorislav Petkov { 1541e1069839SBorislav Petkov [ C(L1D) ] = { 1542e1069839SBorislav Petkov [ C(OP_READ) ] = { 1543e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1544e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1545e1069839SBorislav Petkov }, 1546e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1547e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1548e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1549e1069839SBorislav Petkov }, 1550e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1551e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1552e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1553e1069839SBorislav Petkov }, 1554e1069839SBorislav Petkov }, 1555e1069839SBorislav Petkov [ C(L1I ) ] = { 1556e1069839SBorislav Petkov [ C(OP_READ) ] = { 1557e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1558e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1559e1069839SBorislav Petkov }, 1560e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1561e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1562e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1563e1069839SBorislav Petkov }, 1564e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1565e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1566e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1567e1069839SBorislav Petkov }, 1568e1069839SBorislav Petkov }, 1569e1069839SBorislav Petkov [ C(LL ) ] = { 1570e1069839SBorislav Petkov [ C(OP_READ) ] = { 1571e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1572e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1573e1069839SBorislav Petkov }, 1574e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1575e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1576e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1577e1069839SBorislav Petkov }, 1578e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1579e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1580e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1581e1069839SBorislav Petkov }, 1582e1069839SBorislav Petkov }, 1583e1069839SBorislav Petkov [ C(DTLB) ] = { 1584e1069839SBorislav Petkov [ C(OP_READ) ] = { 1585e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1586e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1587e1069839SBorislav Petkov }, 1588e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1589e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1590e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1591e1069839SBorislav Petkov }, 1592e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1593e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1594e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1595e1069839SBorislav Petkov }, 1596e1069839SBorislav Petkov }, 1597e1069839SBorislav Petkov [ C(ITLB) ] = { 1598e1069839SBorislav Petkov [ C(OP_READ) ] = { 1599e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1600e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1601e1069839SBorislav Petkov }, 1602e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1603e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1604e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1605e1069839SBorislav Petkov }, 1606e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1607e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1608e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1609e1069839SBorislav Petkov }, 1610e1069839SBorislav Petkov }, 1611e1069839SBorislav Petkov [ C(BPU ) ] = { 1612e1069839SBorislav Petkov [ C(OP_READ) ] = { 1613e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1614e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1615e1069839SBorislav Petkov }, 1616e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1617e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1618e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1619e1069839SBorislav Petkov }, 1620e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1621e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1622e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1623e1069839SBorislav Petkov }, 1624e1069839SBorislav Petkov }, 1625e1069839SBorislav Petkov }; 1626e1069839SBorislav Petkov 1627eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1628eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1629eb12b8ecSAndi Kleen /* no_alloc_cycles.not_delivered */ 1630eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1631eb12b8ecSAndi Kleen "event=0xca,umask=0x50"); 1632eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1633eb12b8ecSAndi Kleen /* uops_retired.all */ 1634eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1635eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1636eb12b8ecSAndi Kleen /* uops_retired.all */ 1637eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1638eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1639eb12b8ecSAndi Kleen 1640eb12b8ecSAndi Kleen static struct attribute *slm_events_attrs[] = { 1641eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_slm), 1642eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_scale_slm), 1643eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_slm), 1644eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_scale_slm), 1645eb12b8ecSAndi Kleen EVENT_PTR(td_slots_issued_slm), 1646eb12b8ecSAndi Kleen EVENT_PTR(td_slots_retired_slm), 1647eb12b8ecSAndi Kleen NULL 1648eb12b8ecSAndi Kleen }; 1649eb12b8ecSAndi Kleen 1650e1069839SBorislav Petkov static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1651e1069839SBorislav Petkov { 1652e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1653e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1654e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1655e1069839SBorislav Petkov EVENT_EXTRA_END 1656e1069839SBorislav Petkov }; 1657e1069839SBorislav Petkov 1658e1069839SBorislav Petkov #define SLM_DMND_READ SNB_DMND_DATA_RD 1659e1069839SBorislav Petkov #define SLM_DMND_WRITE SNB_DMND_RFO 1660e1069839SBorislav Petkov #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1661e1069839SBorislav Petkov 1662e1069839SBorislav Petkov #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1663e1069839SBorislav Petkov #define SLM_LLC_ACCESS SNB_RESP_ANY 1664e1069839SBorislav Petkov #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1665e1069839SBorislav Petkov 1666e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_extra_regs 1667e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1668e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1669e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1670e1069839SBorislav Petkov { 1671e1069839SBorislav Petkov [ C(LL ) ] = { 1672e1069839SBorislav Petkov [ C(OP_READ) ] = { 1673e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1674e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1675e1069839SBorislav Petkov }, 1676e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1677e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1678e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1679e1069839SBorislav Petkov }, 1680e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1681e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1682e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1683e1069839SBorislav Petkov }, 1684e1069839SBorislav Petkov }, 1685e1069839SBorislav Petkov }; 1686e1069839SBorislav Petkov 1687e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_event_ids 1688e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1689e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1690e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1691e1069839SBorislav Petkov { 1692e1069839SBorislav Petkov [ C(L1D) ] = { 1693e1069839SBorislav Petkov [ C(OP_READ) ] = { 1694e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1695e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1696e1069839SBorislav Petkov }, 1697e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1698e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1699e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1700e1069839SBorislav Petkov }, 1701e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1702e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1703e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1704e1069839SBorislav Petkov }, 1705e1069839SBorislav Petkov }, 1706e1069839SBorislav Petkov [ C(L1I ) ] = { 1707e1069839SBorislav Petkov [ C(OP_READ) ] = { 1708e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1709e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1710e1069839SBorislav Petkov }, 1711e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1712e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1713e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1714e1069839SBorislav Petkov }, 1715e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1716e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1717e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1718e1069839SBorislav Petkov }, 1719e1069839SBorislav Petkov }, 1720e1069839SBorislav Petkov [ C(LL ) ] = { 1721e1069839SBorislav Petkov [ C(OP_READ) ] = { 1722e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1723e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1724e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1725e1069839SBorislav Petkov }, 1726e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1727e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1728e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1729e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1730e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1731e1069839SBorislav Petkov }, 1732e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1733e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1734e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1735e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1736e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1737e1069839SBorislav Petkov }, 1738e1069839SBorislav Petkov }, 1739e1069839SBorislav Petkov [ C(DTLB) ] = { 1740e1069839SBorislav Petkov [ C(OP_READ) ] = { 1741e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1742e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1743e1069839SBorislav Petkov }, 1744e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1745e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1746e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1747e1069839SBorislav Petkov }, 1748e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1749e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1750e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1751e1069839SBorislav Petkov }, 1752e1069839SBorislav Petkov }, 1753e1069839SBorislav Petkov [ C(ITLB) ] = { 1754e1069839SBorislav Petkov [ C(OP_READ) ] = { 1755e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1756e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1757e1069839SBorislav Petkov }, 1758e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1759e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1760e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1761e1069839SBorislav Petkov }, 1762e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1763e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1764e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1765e1069839SBorislav Petkov }, 1766e1069839SBorislav Petkov }, 1767e1069839SBorislav Petkov [ C(BPU ) ] = { 1768e1069839SBorislav Petkov [ C(OP_READ) ] = { 1769e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1770e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1771e1069839SBorislav Petkov }, 1772e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1773e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1774e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1775e1069839SBorislav Petkov }, 1776e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1777e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1778e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1779e1069839SBorislav Petkov }, 1780e1069839SBorislav Petkov }, 1781e1069839SBorislav Petkov }; 1782e1069839SBorislav Petkov 1783ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1784ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1785ed827adbSKan Liang /* UOPS_NOT_DELIVERED.ANY */ 1786ed827adbSKan Liang EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1787ed827adbSKan Liang /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1788ed827adbSKan Liang EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1789ed827adbSKan Liang /* UOPS_RETIRED.ANY */ 1790ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1791ed827adbSKan Liang /* UOPS_ISSUED.ANY */ 1792ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1793ed827adbSKan Liang 1794ed827adbSKan Liang static struct attribute *glm_events_attrs[] = { 1795ed827adbSKan Liang EVENT_PTR(td_total_slots_glm), 1796ed827adbSKan Liang EVENT_PTR(td_total_slots_scale_glm), 1797ed827adbSKan Liang EVENT_PTR(td_fetch_bubbles_glm), 1798ed827adbSKan Liang EVENT_PTR(td_recovery_bubbles_glm), 1799ed827adbSKan Liang EVENT_PTR(td_slots_issued_glm), 1800ed827adbSKan Liang EVENT_PTR(td_slots_retired_glm), 1801ed827adbSKan Liang NULL 1802ed827adbSKan Liang }; 1803ed827adbSKan Liang 18048b92c3a7SKan Liang static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 18058b92c3a7SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 18068b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 18078b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 18088b92c3a7SKan Liang EVENT_EXTRA_END 18098b92c3a7SKan Liang }; 18108b92c3a7SKan Liang 18118b92c3a7SKan Liang #define GLM_DEMAND_DATA_RD BIT_ULL(0) 18128b92c3a7SKan Liang #define GLM_DEMAND_RFO BIT_ULL(1) 18138b92c3a7SKan Liang #define GLM_ANY_RESPONSE BIT_ULL(16) 18148b92c3a7SKan Liang #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 18158b92c3a7SKan Liang #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 18168b92c3a7SKan Liang #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 18178b92c3a7SKan Liang #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 18188b92c3a7SKan Liang #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 18198b92c3a7SKan Liang #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 18208b92c3a7SKan Liang #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 18218b92c3a7SKan Liang 18228b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_event_ids 18238b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 18248b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 18258b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 18268b92c3a7SKan Liang [C(L1D)] = { 18278b92c3a7SKan Liang [C(OP_READ)] = { 18288b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 18298b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18308b92c3a7SKan Liang }, 18318b92c3a7SKan Liang [C(OP_WRITE)] = { 18328b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 18338b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18348b92c3a7SKan Liang }, 18358b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18368b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 18378b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18388b92c3a7SKan Liang }, 18398b92c3a7SKan Liang }, 18408b92c3a7SKan Liang [C(L1I)] = { 18418b92c3a7SKan Liang [C(OP_READ)] = { 18428b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 18438b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 18448b92c3a7SKan Liang }, 18458b92c3a7SKan Liang [C(OP_WRITE)] = { 18468b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18478b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18488b92c3a7SKan Liang }, 18498b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18508b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 18518b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18528b92c3a7SKan Liang }, 18538b92c3a7SKan Liang }, 18548b92c3a7SKan Liang [C(LL)] = { 18558b92c3a7SKan Liang [C(OP_READ)] = { 18568b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18578b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18588b92c3a7SKan Liang }, 18598b92c3a7SKan Liang [C(OP_WRITE)] = { 18608b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18618b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18628b92c3a7SKan Liang }, 18638b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18648b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18658b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18668b92c3a7SKan Liang }, 18678b92c3a7SKan Liang }, 18688b92c3a7SKan Liang [C(DTLB)] = { 18698b92c3a7SKan Liang [C(OP_READ)] = { 18708b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 18718b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18728b92c3a7SKan Liang }, 18738b92c3a7SKan Liang [C(OP_WRITE)] = { 18748b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 18758b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18768b92c3a7SKan Liang }, 18778b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18788b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 18798b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18808b92c3a7SKan Liang }, 18818b92c3a7SKan Liang }, 18828b92c3a7SKan Liang [C(ITLB)] = { 18838b92c3a7SKan Liang [C(OP_READ)] = { 18848b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 18858b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 18868b92c3a7SKan Liang }, 18878b92c3a7SKan Liang [C(OP_WRITE)] = { 18888b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18898b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18908b92c3a7SKan Liang }, 18918b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18928b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18938b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18948b92c3a7SKan Liang }, 18958b92c3a7SKan Liang }, 18968b92c3a7SKan Liang [C(BPU)] = { 18978b92c3a7SKan Liang [C(OP_READ)] = { 18988b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 18998b92c3a7SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 19008b92c3a7SKan Liang }, 19018b92c3a7SKan Liang [C(OP_WRITE)] = { 19028b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 19038b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 19048b92c3a7SKan Liang }, 19058b92c3a7SKan Liang [C(OP_PREFETCH)] = { 19068b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 19078b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 19088b92c3a7SKan Liang }, 19098b92c3a7SKan Liang }, 19108b92c3a7SKan Liang }; 19118b92c3a7SKan Liang 19128b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_extra_regs 19138b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 19148b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 19158b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 19168b92c3a7SKan Liang [C(LL)] = { 19178b92c3a7SKan Liang [C(OP_READ)] = { 19188b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 19198b92c3a7SKan Liang GLM_LLC_ACCESS, 19208b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 19218b92c3a7SKan Liang GLM_LLC_MISS, 19228b92c3a7SKan Liang }, 19238b92c3a7SKan Liang [C(OP_WRITE)] = { 19248b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 19258b92c3a7SKan Liang GLM_LLC_ACCESS, 19268b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 19278b92c3a7SKan Liang GLM_LLC_MISS, 19288b92c3a7SKan Liang }, 19298b92c3a7SKan Liang [C(OP_PREFETCH)] = { 19308b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 19318b92c3a7SKan Liang GLM_LLC_ACCESS, 19328b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 19338b92c3a7SKan Liang GLM_LLC_MISS, 19348b92c3a7SKan Liang }, 19358b92c3a7SKan Liang }, 19368b92c3a7SKan Liang }; 19378b92c3a7SKan Liang 1938dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_event_ids 1939dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1940dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1941dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1942dd0b06b5SKan Liang [C(L1D)] = { 1943dd0b06b5SKan Liang [C(OP_READ)] = { 1944dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1945dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1946dd0b06b5SKan Liang }, 1947dd0b06b5SKan Liang [C(OP_WRITE)] = { 1948dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1949dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1950dd0b06b5SKan Liang }, 1951dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1952dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1953dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1954dd0b06b5SKan Liang }, 1955dd0b06b5SKan Liang }, 1956dd0b06b5SKan Liang [C(L1I)] = { 1957dd0b06b5SKan Liang [C(OP_READ)] = { 1958dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1959dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1960dd0b06b5SKan Liang }, 1961dd0b06b5SKan Liang [C(OP_WRITE)] = { 1962dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1963dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1964dd0b06b5SKan Liang }, 1965dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1966dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1967dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1968dd0b06b5SKan Liang }, 1969dd0b06b5SKan Liang }, 1970dd0b06b5SKan Liang [C(LL)] = { 1971dd0b06b5SKan Liang [C(OP_READ)] = { 1972dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1973dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1974dd0b06b5SKan Liang }, 1975dd0b06b5SKan Liang [C(OP_WRITE)] = { 1976dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1977dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1978dd0b06b5SKan Liang }, 1979dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1980dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1981dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1982dd0b06b5SKan Liang }, 1983dd0b06b5SKan Liang }, 1984dd0b06b5SKan Liang [C(DTLB)] = { 1985dd0b06b5SKan Liang [C(OP_READ)] = { 1986dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1987dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1988dd0b06b5SKan Liang }, 1989dd0b06b5SKan Liang [C(OP_WRITE)] = { 1990dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1991dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1992dd0b06b5SKan Liang }, 1993dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1994dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1995dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1996dd0b06b5SKan Liang }, 1997dd0b06b5SKan Liang }, 1998dd0b06b5SKan Liang [C(ITLB)] = { 1999dd0b06b5SKan Liang [C(OP_READ)] = { 2000dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2001dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2002dd0b06b5SKan Liang }, 2003dd0b06b5SKan Liang [C(OP_WRITE)] = { 2004dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 2005dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 2006dd0b06b5SKan Liang }, 2007dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 2008dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 2009dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 2010dd0b06b5SKan Liang }, 2011dd0b06b5SKan Liang }, 2012dd0b06b5SKan Liang [C(BPU)] = { 2013dd0b06b5SKan Liang [C(OP_READ)] = { 2014dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2015dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2016dd0b06b5SKan Liang }, 2017dd0b06b5SKan Liang [C(OP_WRITE)] = { 2018dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 2019dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 2020dd0b06b5SKan Liang }, 2021dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 2022dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 2023dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 2024dd0b06b5SKan Liang }, 2025dd0b06b5SKan Liang }, 2026dd0b06b5SKan Liang }; 2027dd0b06b5SKan Liang 2028dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_extra_regs 2029dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 2030dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 2031dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2032dd0b06b5SKan Liang [C(LL)] = { 2033dd0b06b5SKan Liang [C(OP_READ)] = { 2034dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2035dd0b06b5SKan Liang GLM_LLC_ACCESS, 2036dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 2037dd0b06b5SKan Liang GLM_LLC_MISS, 2038dd0b06b5SKan Liang }, 2039dd0b06b5SKan Liang [C(OP_WRITE)] = { 2040dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2041dd0b06b5SKan Liang GLM_LLC_ACCESS, 2042dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2043dd0b06b5SKan Liang GLM_LLC_MISS, 2044dd0b06b5SKan Liang }, 2045dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 2046dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 2047dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 2048dd0b06b5SKan Liang }, 2049dd0b06b5SKan Liang }, 2050dd0b06b5SKan Liang }; 2051dd0b06b5SKan Liang 20526daeb873SKan Liang #define TNT_LOCAL_DRAM BIT_ULL(26) 20536daeb873SKan Liang #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 20546daeb873SKan Liang #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 20556daeb873SKan Liang #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 20566daeb873SKan Liang #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 20576daeb873SKan Liang SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 20586daeb873SKan Liang #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 20596daeb873SKan Liang 20606daeb873SKan Liang static __initconst const u64 tnt_hw_cache_extra_regs 20616daeb873SKan Liang [PERF_COUNT_HW_CACHE_MAX] 20626daeb873SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 20636daeb873SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 20646daeb873SKan Liang [C(LL)] = { 20656daeb873SKan Liang [C(OP_READ)] = { 20666daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 20676daeb873SKan Liang TNT_LLC_ACCESS, 20686daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_READ| 20696daeb873SKan Liang TNT_LLC_MISS, 20706daeb873SKan Liang }, 20716daeb873SKan Liang [C(OP_WRITE)] = { 20726daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 20736daeb873SKan Liang TNT_LLC_ACCESS, 20746daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 20756daeb873SKan Liang TNT_LLC_MISS, 20766daeb873SKan Liang }, 20776daeb873SKan Liang [C(OP_PREFETCH)] = { 20786daeb873SKan Liang [C(RESULT_ACCESS)] = 0x0, 20796daeb873SKan Liang [C(RESULT_MISS)] = 0x0, 20806daeb873SKan Liang }, 20816daeb873SKan Liang }, 20826daeb873SKan Liang }; 20836daeb873SKan Liang 2084c2208046SKan Liang EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2085c2208046SKan Liang EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2086c2208046SKan Liang EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2087c2208046SKan Liang EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2088c2208046SKan Liang 2089c2208046SKan Liang static struct attribute *tnt_events_attrs[] = { 2090c2208046SKan Liang EVENT_PTR(td_fe_bound_tnt), 2091c2208046SKan Liang EVENT_PTR(td_retiring_tnt), 2092c2208046SKan Liang EVENT_PTR(td_bad_spec_tnt), 2093c2208046SKan Liang EVENT_PTR(td_be_bound_tnt), 2094c2208046SKan Liang NULL, 2095c2208046SKan Liang }; 2096c2208046SKan Liang 20976daeb873SKan Liang static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 20986daeb873SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 20990813c405SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 21000813c405SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 21016daeb873SKan Liang EVENT_EXTRA_END 21026daeb873SKan Liang }; 21036daeb873SKan Liang 2104f83d2f91SKan Liang static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2105f83d2f91SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2106f83d2f91SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2107f83d2f91SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2108f83d2f91SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2109f83d2f91SKan Liang EVENT_EXTRA_END 2110f83d2f91SKan Liang }; 2111f83d2f91SKan Liang 2112e1069839SBorislav Petkov #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2113e1069839SBorislav Petkov #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2114e1069839SBorislav Petkov #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2115e1069839SBorislav Petkov #define KNL_MCDRAM_FAR BIT_ULL(22) 2116e1069839SBorislav Petkov #define KNL_DDR_LOCAL BIT_ULL(23) 2117e1069839SBorislav Petkov #define KNL_DDR_FAR BIT_ULL(24) 2118e1069839SBorislav Petkov #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2119e1069839SBorislav Petkov KNL_DDR_LOCAL | KNL_DDR_FAR) 2120e1069839SBorislav Petkov #define KNL_L2_READ SLM_DMND_READ 2121e1069839SBorislav Petkov #define KNL_L2_WRITE SLM_DMND_WRITE 2122e1069839SBorislav Petkov #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2123e1069839SBorislav Petkov #define KNL_L2_ACCESS SLM_LLC_ACCESS 2124e1069839SBorislav Petkov #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2125e1069839SBorislav Petkov KNL_DRAM_ANY | SNB_SNP_ANY | \ 2126e1069839SBorislav Petkov SNB_NON_DRAM) 2127e1069839SBorislav Petkov 2128e1069839SBorislav Petkov static __initconst const u64 knl_hw_cache_extra_regs 2129e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 2130e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 2131e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2132e1069839SBorislav Petkov [C(LL)] = { 2133e1069839SBorislav Petkov [C(OP_READ)] = { 2134e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2135e1069839SBorislav Petkov [C(RESULT_MISS)] = 0, 2136e1069839SBorislav Petkov }, 2137e1069839SBorislav Petkov [C(OP_WRITE)] = { 2138e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2139e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2140e1069839SBorislav Petkov }, 2141e1069839SBorislav Petkov [C(OP_PREFETCH)] = { 2142e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2143e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2144e1069839SBorislav Petkov }, 2145e1069839SBorislav Petkov }, 2146e1069839SBorislav Petkov }; 2147e1069839SBorislav Petkov 2148e1069839SBorislav Petkov /* 2149c3d266c8SKan Liang * Used from PMIs where the LBRs are already disabled. 2150c3d266c8SKan Liang * 2151c3d266c8SKan Liang * This function could be called consecutively. It is required to remain in 2152c3d266c8SKan Liang * disabled state if called consecutively. 2153c3d266c8SKan Liang * 2154c3d266c8SKan Liang * During consecutive calls, the same disable value will be written to related 2155cecf6235SAlexander Shishkin * registers, so the PMU state remains unchanged. 2156cecf6235SAlexander Shishkin * 2157cecf6235SAlexander Shishkin * intel_bts events don't coexist with intel PMU's BTS events because of 2158cecf6235SAlexander Shishkin * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2159cecf6235SAlexander Shishkin * disabled around intel PMU's event batching etc, only inside the PMI handler. 21606c1c07b3SKan Liang * 21616c1c07b3SKan Liang * Avoid PEBS_ENABLE MSR access in PMIs. 21626c1c07b3SKan Liang * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 21636c1c07b3SKan Liang * It doesn't matter if the PEBS is enabled or not. 21646c1c07b3SKan Liang * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 21656c1c07b3SKan Liang * access PEBS_ENABLE MSR in disable_all()/enable_all(). 21666c1c07b3SKan Liang * However, there are some cases which may change PEBS status, e.g. PMI 21676c1c07b3SKan Liang * throttle. The PEBS_ENABLE should be updated where the status changes. 2168e1069839SBorislav Petkov */ 2169c22ac2a3SSong Liu static __always_inline void __intel_pmu_disable_all(bool bts) 2170e1069839SBorislav Petkov { 2171e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2172e1069839SBorislav Petkov 2173e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2174e1069839SBorislav Petkov 2175c22ac2a3SSong Liu if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2176e1069839SBorislav Petkov intel_pmu_disable_bts(); 2177e1069839SBorislav Petkov } 2178e1069839SBorislav Petkov 2179c22ac2a3SSong Liu static __always_inline void intel_pmu_disable_all(void) 2180e1069839SBorislav Petkov { 2181c22ac2a3SSong Liu __intel_pmu_disable_all(true); 21826c1c07b3SKan Liang intel_pmu_pebs_disable_all(); 2183e1069839SBorislav Petkov intel_pmu_lbr_disable_all(); 2184e1069839SBorislav Petkov } 2185e1069839SBorislav Petkov 2186e1069839SBorislav Petkov static void __intel_pmu_enable_all(int added, bool pmi) 2187e1069839SBorislav Petkov { 2188e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2189fc4b8fcaSKan Liang u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2190e1069839SBorislav Petkov 2191e1069839SBorislav Petkov intel_pmu_lbr_enable_all(pmi); 2192e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2193fc4b8fcaSKan Liang intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2194e1069839SBorislav Petkov 2195e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2196e1069839SBorislav Petkov struct perf_event *event = 2197e1069839SBorislav Petkov cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2198e1069839SBorislav Petkov 2199e1069839SBorislav Petkov if (WARN_ON_ONCE(!event)) 2200e1069839SBorislav Petkov return; 2201e1069839SBorislav Petkov 2202e1069839SBorislav Petkov intel_pmu_enable_bts(event->hw.config); 2203cecf6235SAlexander Shishkin } 2204e1069839SBorislav Petkov } 2205e1069839SBorislav Petkov 2206e1069839SBorislav Petkov static void intel_pmu_enable_all(int added) 2207e1069839SBorislav Petkov { 22086c1c07b3SKan Liang intel_pmu_pebs_enable_all(); 2209e1069839SBorislav Petkov __intel_pmu_enable_all(added, false); 2210e1069839SBorislav Petkov } 2211e1069839SBorislav Petkov 2212c22ac2a3SSong Liu static noinline int 2213c22ac2a3SSong Liu __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2214c22ac2a3SSong Liu unsigned int cnt, unsigned long flags) 2215c22ac2a3SSong Liu { 2216c22ac2a3SSong Liu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2217c22ac2a3SSong Liu 2218c22ac2a3SSong Liu intel_pmu_lbr_read(); 2219c22ac2a3SSong Liu cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2220c22ac2a3SSong Liu 2221c22ac2a3SSong Liu memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2222c22ac2a3SSong Liu intel_pmu_enable_all(0); 2223c22ac2a3SSong Liu local_irq_restore(flags); 2224c22ac2a3SSong Liu return cnt; 2225c22ac2a3SSong Liu } 2226c22ac2a3SSong Liu 2227c22ac2a3SSong Liu static int 2228c22ac2a3SSong Liu intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2229c22ac2a3SSong Liu { 2230c22ac2a3SSong Liu unsigned long flags; 2231c22ac2a3SSong Liu 2232c22ac2a3SSong Liu /* must not have branches... */ 2233c22ac2a3SSong Liu local_irq_save(flags); 2234c22ac2a3SSong Liu __intel_pmu_disable_all(false); /* we don't care about BTS */ 2235c22ac2a3SSong Liu __intel_pmu_lbr_disable(); 2236c22ac2a3SSong Liu /* ... until here */ 2237c22ac2a3SSong Liu return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2238c22ac2a3SSong Liu } 2239c22ac2a3SSong Liu 2240c22ac2a3SSong Liu static int 2241c22ac2a3SSong Liu intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2242c22ac2a3SSong Liu { 2243c22ac2a3SSong Liu unsigned long flags; 2244c22ac2a3SSong Liu 2245c22ac2a3SSong Liu /* must not have branches... */ 2246c22ac2a3SSong Liu local_irq_save(flags); 2247c22ac2a3SSong Liu __intel_pmu_disable_all(false); /* we don't care about BTS */ 2248c22ac2a3SSong Liu __intel_pmu_arch_lbr_disable(); 2249c22ac2a3SSong Liu /* ... until here */ 2250c22ac2a3SSong Liu return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2251c22ac2a3SSong Liu } 2252c22ac2a3SSong Liu 2253e1069839SBorislav Petkov /* 2254e1069839SBorislav Petkov * Workaround for: 2255e1069839SBorislav Petkov * Intel Errata AAK100 (model 26) 2256e1069839SBorislav Petkov * Intel Errata AAP53 (model 30) 2257e1069839SBorislav Petkov * Intel Errata BD53 (model 44) 2258e1069839SBorislav Petkov * 2259e1069839SBorislav Petkov * The official story: 2260e1069839SBorislav Petkov * These chips need to be 'reset' when adding counters by programming the 2261e1069839SBorislav Petkov * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2262e1069839SBorislav Petkov * in sequence on the same PMC or on different PMCs. 2263e1069839SBorislav Petkov * 2264d9f6e12fSIngo Molnar * In practice it appears some of these events do in fact count, and 2265a97673a1SIngo Molnar * we need to program all 4 events. 2266e1069839SBorislav Petkov */ 2267e1069839SBorislav Petkov static void intel_pmu_nhm_workaround(void) 2268e1069839SBorislav Petkov { 2269e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2270e1069839SBorislav Petkov static const unsigned long nhm_magic[4] = { 2271e1069839SBorislav Petkov 0x4300B5, 2272e1069839SBorislav Petkov 0x4300D2, 2273e1069839SBorislav Petkov 0x4300B1, 2274e1069839SBorislav Petkov 0x4300B1 2275e1069839SBorislav Petkov }; 2276e1069839SBorislav Petkov struct perf_event *event; 2277e1069839SBorislav Petkov int i; 2278e1069839SBorislav Petkov 2279e1069839SBorislav Petkov /* 2280e1069839SBorislav Petkov * The Errata requires below steps: 2281e1069839SBorislav Petkov * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2282e1069839SBorislav Petkov * 2) Configure 4 PERFEVTSELx with the magic events and clear 2283e1069839SBorislav Petkov * the corresponding PMCx; 2284e1069839SBorislav Petkov * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2285e1069839SBorislav Petkov * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2286e1069839SBorislav Petkov * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2287e1069839SBorislav Petkov */ 2288e1069839SBorislav Petkov 2289e1069839SBorislav Petkov /* 2290e1069839SBorislav Petkov * The real steps we choose are a little different from above. 2291e1069839SBorislav Petkov * A) To reduce MSR operations, we don't run step 1) as they 2292e1069839SBorislav Petkov * are already cleared before this function is called; 2293e1069839SBorislav Petkov * B) Call x86_perf_event_update to save PMCx before configuring 2294e1069839SBorislav Petkov * PERFEVTSELx with magic number; 2295e1069839SBorislav Petkov * C) With step 5), we do clear only when the PERFEVTSELx is 2296e1069839SBorislav Petkov * not used currently. 2297e1069839SBorislav Petkov * D) Call x86_perf_event_set_period to restore PMCx; 2298e1069839SBorislav Petkov */ 2299e1069839SBorislav Petkov 2300e1069839SBorislav Petkov /* We always operate 4 pairs of PERF Counters */ 2301e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2302e1069839SBorislav Petkov event = cpuc->events[i]; 2303e1069839SBorislav Petkov if (event) 2304e1069839SBorislav Petkov x86_perf_event_update(event); 2305e1069839SBorislav Petkov } 2306e1069839SBorislav Petkov 2307e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2308e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2309e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2310e1069839SBorislav Petkov } 2311e1069839SBorislav Petkov 2312e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2313e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2314e1069839SBorislav Petkov 2315e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2316e1069839SBorislav Petkov event = cpuc->events[i]; 2317e1069839SBorislav Petkov 2318e1069839SBorislav Petkov if (event) { 2319e1069839SBorislav Petkov x86_perf_event_set_period(event); 2320e1069839SBorislav Petkov __x86_pmu_enable_event(&event->hw, 2321e1069839SBorislav Petkov ARCH_PERFMON_EVENTSEL_ENABLE); 2322e1069839SBorislav Petkov } else 2323e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2324e1069839SBorislav Petkov } 2325e1069839SBorislav Petkov } 2326e1069839SBorislav Petkov 2327e1069839SBorislav Petkov static void intel_pmu_nhm_enable_all(int added) 2328e1069839SBorislav Petkov { 2329e1069839SBorislav Petkov if (added) 2330e1069839SBorislav Petkov intel_pmu_nhm_workaround(); 2331e1069839SBorislav Petkov intel_pmu_enable_all(added); 2332e1069839SBorislav Petkov } 2333e1069839SBorislav Petkov 2334400816f6SPeter Zijlstra (Intel) static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2335400816f6SPeter Zijlstra (Intel) { 2336400816f6SPeter Zijlstra (Intel) u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2337400816f6SPeter Zijlstra (Intel) 2338400816f6SPeter Zijlstra (Intel) if (cpuc->tfa_shadow != val) { 2339400816f6SPeter Zijlstra (Intel) cpuc->tfa_shadow = val; 2340400816f6SPeter Zijlstra (Intel) wrmsrl(MSR_TSX_FORCE_ABORT, val); 2341400816f6SPeter Zijlstra (Intel) } 2342400816f6SPeter Zijlstra (Intel) } 2343400816f6SPeter Zijlstra (Intel) 2344400816f6SPeter Zijlstra (Intel) static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2345400816f6SPeter Zijlstra (Intel) { 2346400816f6SPeter Zijlstra (Intel) /* 2347400816f6SPeter Zijlstra (Intel) * We're going to use PMC3, make sure TFA is set before we touch it. 2348400816f6SPeter Zijlstra (Intel) */ 23491a81542aSPeter Zijlstra if (cntr == 3) 2350400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, true); 2351400816f6SPeter Zijlstra (Intel) } 2352400816f6SPeter Zijlstra (Intel) 2353400816f6SPeter Zijlstra (Intel) static void intel_tfa_pmu_enable_all(int added) 2354400816f6SPeter Zijlstra (Intel) { 2355400816f6SPeter Zijlstra (Intel) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2356400816f6SPeter Zijlstra (Intel) 2357400816f6SPeter Zijlstra (Intel) /* 2358400816f6SPeter Zijlstra (Intel) * If we find PMC3 is no longer used when we enable the PMU, we can 2359400816f6SPeter Zijlstra (Intel) * clear TFA. 2360400816f6SPeter Zijlstra (Intel) */ 2361400816f6SPeter Zijlstra (Intel) if (!test_bit(3, cpuc->active_mask)) 2362400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, false); 2363400816f6SPeter Zijlstra (Intel) 2364400816f6SPeter Zijlstra (Intel) intel_pmu_enable_all(added); 2365400816f6SPeter Zijlstra (Intel) } 2366400816f6SPeter Zijlstra (Intel) 2367e1069839SBorislav Petkov static inline u64 intel_pmu_get_status(void) 2368e1069839SBorislav Petkov { 2369e1069839SBorislav Petkov u64 status; 2370e1069839SBorislav Petkov 2371e1069839SBorislav Petkov rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2372e1069839SBorislav Petkov 2373e1069839SBorislav Petkov return status; 2374e1069839SBorislav Petkov } 2375e1069839SBorislav Petkov 2376e1069839SBorislav Petkov static inline void intel_pmu_ack_status(u64 ack) 2377e1069839SBorislav Petkov { 2378e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2379e1069839SBorislav Petkov } 2380e1069839SBorislav Petkov 2381027440b5SLike Xu static inline bool event_is_checkpointed(struct perf_event *event) 2382e1069839SBorislav Petkov { 2383027440b5SLike Xu return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2384027440b5SLike Xu } 2385027440b5SLike Xu 2386027440b5SLike Xu static inline void intel_set_masks(struct perf_event *event, int idx) 2387027440b5SLike Xu { 2388027440b5SLike Xu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2389027440b5SLike Xu 2390027440b5SLike Xu if (event->attr.exclude_host) 2391027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2392027440b5SLike Xu if (event->attr.exclude_guest) 2393027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2394027440b5SLike Xu if (event_is_checkpointed(event)) 2395027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2396027440b5SLike Xu } 2397027440b5SLike Xu 2398027440b5SLike Xu static inline void intel_clear_masks(struct perf_event *event, int idx) 2399027440b5SLike Xu { 2400027440b5SLike Xu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2401027440b5SLike Xu 2402027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2403027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2404027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2405027440b5SLike Xu } 2406027440b5SLike Xu 2407027440b5SLike Xu static void intel_pmu_disable_fixed(struct perf_event *event) 2408027440b5SLike Xu { 2409027440b5SLike Xu struct hw_perf_event *hwc = &event->hw; 2410e1069839SBorislav Petkov u64 ctrl_val, mask; 24117b2c05a1SKan Liang int idx = hwc->idx; 2412e1069839SBorislav Petkov 24137b2c05a1SKan Liang if (is_topdown_idx(idx)) { 24147b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2415e1069839SBorislav Petkov 24167b2c05a1SKan Liang /* 24177b2c05a1SKan Liang * When there are other active TopDown events, 24187b2c05a1SKan Liang * don't disable the fixed counter 3. 24197b2c05a1SKan Liang */ 24207b2c05a1SKan Liang if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 24217b2c05a1SKan Liang return; 24227b2c05a1SKan Liang idx = INTEL_PMC_IDX_FIXED_SLOTS; 24237b2c05a1SKan Liang } 24247b2c05a1SKan Liang 24257b2c05a1SKan Liang intel_clear_masks(event, idx); 24267b2c05a1SKan Liang 24277b2c05a1SKan Liang mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2428e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2429e1069839SBorislav Petkov ctrl_val &= ~mask; 2430e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2431e1069839SBorislav Petkov } 2432e1069839SBorislav Petkov 2433e1069839SBorislav Petkov static void intel_pmu_disable_event(struct perf_event *event) 2434e1069839SBorislav Petkov { 2435e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2436027440b5SLike Xu int idx = hwc->idx; 2437e1069839SBorislav Petkov 243858da7dbeSKan Liang switch (idx) { 243958da7dbeSKan Liang case 0 ... INTEL_PMC_IDX_FIXED - 1: 2440027440b5SLike Xu intel_clear_masks(event, idx); 2441027440b5SLike Xu x86_pmu_disable_event(event); 244258da7dbeSKan Liang break; 244358da7dbeSKan Liang case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 24447b2c05a1SKan Liang case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2445027440b5SLike Xu intel_pmu_disable_fixed(event); 244658da7dbeSKan Liang break; 244758da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_BTS: 2448e1069839SBorislav Petkov intel_pmu_disable_bts(); 2449e1069839SBorislav Petkov intel_pmu_drain_bts_buffer(); 245058da7dbeSKan Liang return; 245158da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_VLBR: 2452e1ad1ac2SLike Xu intel_clear_masks(event, idx); 245358da7dbeSKan Liang break; 245458da7dbeSKan Liang default: 245558da7dbeSKan Liang intel_clear_masks(event, idx); 245658da7dbeSKan Liang pr_warn("Failed to disable the event with invalid index %d\n", 245758da7dbeSKan Liang idx); 245858da7dbeSKan Liang return; 245958da7dbeSKan Liang } 2460e1069839SBorislav Petkov 24616f55967aSJiri Olsa /* 24626f55967aSJiri Olsa * Needs to be called after x86_pmu_disable_event, 24636f55967aSJiri Olsa * so we don't trigger the event without PEBS bit set. 24646f55967aSJiri Olsa */ 24656f55967aSJiri Olsa if (unlikely(event->attr.precise_ip)) 24666f55967aSJiri Olsa intel_pmu_pebs_disable(event); 2467e1069839SBorislav Petkov } 2468e1069839SBorislav Petkov 24698b8ff8ccSAdrian Hunter static void intel_pmu_assign_event(struct perf_event *event, int idx) 24708b8ff8ccSAdrian Hunter { 24718b8ff8ccSAdrian Hunter if (is_pebs_pt(event)) 24728b8ff8ccSAdrian Hunter perf_report_aux_output_id(event, idx); 24738b8ff8ccSAdrian Hunter } 24748b8ff8ccSAdrian Hunter 247568f7082fSPeter Zijlstra static void intel_pmu_del_event(struct perf_event *event) 247668f7082fSPeter Zijlstra { 247768f7082fSPeter Zijlstra if (needs_branch_stack(event)) 247868f7082fSPeter Zijlstra intel_pmu_lbr_del(event); 247968f7082fSPeter Zijlstra if (event->attr.precise_ip) 248068f7082fSPeter Zijlstra intel_pmu_pebs_del(event); 248168f7082fSPeter Zijlstra } 248268f7082fSPeter Zijlstra 248359a854e2SKan Liang static int icl_set_topdown_event_period(struct perf_event *event) 248459a854e2SKan Liang { 248559a854e2SKan Liang struct hw_perf_event *hwc = &event->hw; 248659a854e2SKan Liang s64 left = local64_read(&hwc->period_left); 248759a854e2SKan Liang 248859a854e2SKan Liang /* 248959a854e2SKan Liang * The values in PERF_METRICS MSR are derived from fixed counter 3. 249059a854e2SKan Liang * Software should start both registers, PERF_METRICS and fixed 249159a854e2SKan Liang * counter 3, from zero. 249259a854e2SKan Liang * Clear PERF_METRICS and Fixed counter 3 in initialization. 249359a854e2SKan Liang * After that, both MSRs will be cleared for each read. 249459a854e2SKan Liang * Don't need to clear them again. 249559a854e2SKan Liang */ 249659a854e2SKan Liang if (left == x86_pmu.max_period) { 249759a854e2SKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 249859a854e2SKan Liang wrmsrl(MSR_PERF_METRICS, 0); 24992cb5383bSKan Liang hwc->saved_slots = 0; 25002cb5383bSKan Liang hwc->saved_metric = 0; 25012cb5383bSKan Liang } 25022cb5383bSKan Liang 25032cb5383bSKan Liang if ((hwc->saved_slots) && is_slots_event(event)) { 25042cb5383bSKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 25052cb5383bSKan Liang wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 250659a854e2SKan Liang } 250759a854e2SKan Liang 250859a854e2SKan Liang perf_event_update_userpage(event); 250959a854e2SKan Liang 251059a854e2SKan Liang return 0; 251159a854e2SKan Liang } 251259a854e2SKan Liang 2513f83d2f91SKan Liang static int adl_set_topdown_event_period(struct perf_event *event) 2514f83d2f91SKan Liang { 2515f83d2f91SKan Liang struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2516f83d2f91SKan Liang 2517f83d2f91SKan Liang if (pmu->cpu_type != hybrid_big) 2518f83d2f91SKan Liang return 0; 2519f83d2f91SKan Liang 2520f83d2f91SKan Liang return icl_set_topdown_event_period(event); 2521f83d2f91SKan Liang } 2522f83d2f91SKan Liang 252359a854e2SKan Liang static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 252459a854e2SKan Liang { 252559a854e2SKan Liang u32 val; 252659a854e2SKan Liang 252759a854e2SKan Liang /* 252859a854e2SKan Liang * The metric is reported as an 8bit integer fraction 2529d9f6e12fSIngo Molnar * summing up to 0xff. 253059a854e2SKan Liang * slots-in-metric = (Metric / 0xff) * slots 253159a854e2SKan Liang */ 253259a854e2SKan Liang val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 253359a854e2SKan Liang return mul_u64_u32_div(slots, val, 0xff); 253459a854e2SKan Liang } 253559a854e2SKan Liang 25362cb5383bSKan Liang static u64 icl_get_topdown_value(struct perf_event *event, 253759a854e2SKan Liang u64 slots, u64 metrics) 253859a854e2SKan Liang { 253959a854e2SKan Liang int idx = event->hw.idx; 254059a854e2SKan Liang u64 delta; 254159a854e2SKan Liang 254259a854e2SKan Liang if (is_metric_idx(idx)) 254359a854e2SKan Liang delta = icl_get_metrics_event_value(metrics, slots, idx); 254459a854e2SKan Liang else 254559a854e2SKan Liang delta = slots; 254659a854e2SKan Liang 25472cb5383bSKan Liang return delta; 25482cb5383bSKan Liang } 25492cb5383bSKan Liang 25502cb5383bSKan Liang static void __icl_update_topdown_event(struct perf_event *event, 25512cb5383bSKan Liang u64 slots, u64 metrics, 25522cb5383bSKan Liang u64 last_slots, u64 last_metrics) 25532cb5383bSKan Liang { 25542cb5383bSKan Liang u64 delta, last = 0; 25552cb5383bSKan Liang 25562cb5383bSKan Liang delta = icl_get_topdown_value(event, slots, metrics); 25572cb5383bSKan Liang if (last_slots) 25582cb5383bSKan Liang last = icl_get_topdown_value(event, last_slots, last_metrics); 25592cb5383bSKan Liang 25602cb5383bSKan Liang /* 25612cb5383bSKan Liang * The 8bit integer fraction of metric may be not accurate, 25622cb5383bSKan Liang * especially when the changes is very small. 25632cb5383bSKan Liang * For example, if only a few bad_spec happens, the fraction 25642cb5383bSKan Liang * may be reduced from 1 to 0. If so, the bad_spec event value 25652cb5383bSKan Liang * will be 0 which is definitely less than the last value. 25662cb5383bSKan Liang * Avoid update event->count for this case. 25672cb5383bSKan Liang */ 25682cb5383bSKan Liang if (delta > last) { 25692cb5383bSKan Liang delta -= last; 257059a854e2SKan Liang local64_add(delta, &event->count); 257159a854e2SKan Liang } 25722cb5383bSKan Liang } 25732cb5383bSKan Liang 2574628d923aSKan Liang static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2575628d923aSKan Liang u64 metrics, int metric_end) 25762cb5383bSKan Liang { 25772cb5383bSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 25782cb5383bSKan Liang struct perf_event *other; 25792cb5383bSKan Liang int idx; 25802cb5383bSKan Liang 25812cb5383bSKan Liang event->hw.saved_slots = slots; 25822cb5383bSKan Liang event->hw.saved_metric = metrics; 25832cb5383bSKan Liang 2584628d923aSKan Liang for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 25852cb5383bSKan Liang if (!is_topdown_idx(idx)) 25862cb5383bSKan Liang continue; 25872cb5383bSKan Liang other = cpuc->events[idx]; 25882cb5383bSKan Liang other->hw.saved_slots = slots; 25892cb5383bSKan Liang other->hw.saved_metric = metrics; 25902cb5383bSKan Liang } 25912cb5383bSKan Liang } 259259a854e2SKan Liang 259359a854e2SKan Liang /* 259459a854e2SKan Liang * Update all active Topdown events. 259559a854e2SKan Liang * 259659a854e2SKan Liang * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 259759a854e2SKan Liang * modify by a NMI. PMU has to be disabled before calling this function. 259859a854e2SKan Liang */ 2599628d923aSKan Liang 2600628d923aSKan Liang static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 260159a854e2SKan Liang { 260259a854e2SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 260359a854e2SKan Liang struct perf_event *other; 260459a854e2SKan Liang u64 slots, metrics; 26052cb5383bSKan Liang bool reset = true; 260659a854e2SKan Liang int idx; 260759a854e2SKan Liang 260859a854e2SKan Liang /* read Fixed counter 3 */ 260959a854e2SKan Liang rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 261059a854e2SKan Liang if (!slots) 261159a854e2SKan Liang return 0; 261259a854e2SKan Liang 261359a854e2SKan Liang /* read PERF_METRICS */ 261459a854e2SKan Liang rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 261559a854e2SKan Liang 2616628d923aSKan Liang for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 261759a854e2SKan Liang if (!is_topdown_idx(idx)) 261859a854e2SKan Liang continue; 261959a854e2SKan Liang other = cpuc->events[idx]; 26202cb5383bSKan Liang __icl_update_topdown_event(other, slots, metrics, 26212cb5383bSKan Liang event ? event->hw.saved_slots : 0, 26222cb5383bSKan Liang event ? event->hw.saved_metric : 0); 262359a854e2SKan Liang } 262459a854e2SKan Liang 262559a854e2SKan Liang /* 262659a854e2SKan Liang * Check and update this event, which may have been cleared 262759a854e2SKan Liang * in active_mask e.g. x86_pmu_stop() 262859a854e2SKan Liang */ 26292cb5383bSKan Liang if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 26302cb5383bSKan Liang __icl_update_topdown_event(event, slots, metrics, 26312cb5383bSKan Liang event->hw.saved_slots, 26322cb5383bSKan Liang event->hw.saved_metric); 263359a854e2SKan Liang 26342cb5383bSKan Liang /* 26352cb5383bSKan Liang * In x86_pmu_stop(), the event is cleared in active_mask first, 26362cb5383bSKan Liang * then drain the delta, which indicates context switch for 26372cb5383bSKan Liang * counting. 26382cb5383bSKan Liang * Save metric and slots for context switch. 26392cb5383bSKan Liang * Don't need to reset the PERF_METRICS and Fixed counter 3. 26402cb5383bSKan Liang * Because the values will be restored in next schedule in. 26412cb5383bSKan Liang */ 2642628d923aSKan Liang update_saved_topdown_regs(event, slots, metrics, metric_end); 26432cb5383bSKan Liang reset = false; 26442cb5383bSKan Liang } 26452cb5383bSKan Liang 26462cb5383bSKan Liang if (reset) { 264759a854e2SKan Liang /* The fixed counter 3 has to be written before the PERF_METRICS. */ 264859a854e2SKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 264959a854e2SKan Liang wrmsrl(MSR_PERF_METRICS, 0); 26502cb5383bSKan Liang if (event) 2651628d923aSKan Liang update_saved_topdown_regs(event, 0, 0, metric_end); 26522cb5383bSKan Liang } 265359a854e2SKan Liang 265459a854e2SKan Liang return slots; 265559a854e2SKan Liang } 265659a854e2SKan Liang 2657628d923aSKan Liang static u64 icl_update_topdown_event(struct perf_event *event) 2658628d923aSKan Liang { 26591ab5f235SKan Liang return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 26601ab5f235SKan Liang x86_pmu.num_topdown_events - 1); 2661628d923aSKan Liang } 2662628d923aSKan Liang 2663f83d2f91SKan Liang static u64 adl_update_topdown_event(struct perf_event *event) 2664f83d2f91SKan Liang { 2665f83d2f91SKan Liang struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 2666f83d2f91SKan Liang 2667f83d2f91SKan Liang if (pmu->cpu_type != hybrid_big) 2668f83d2f91SKan Liang return 0; 2669f83d2f91SKan Liang 2670f83d2f91SKan Liang return icl_update_topdown_event(event); 2671f83d2f91SKan Liang } 2672f83d2f91SKan Liang 2673f83d2f91SKan Liang 26747b2c05a1SKan Liang static void intel_pmu_read_topdown_event(struct perf_event *event) 26757b2c05a1SKan Liang { 26767b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 26777b2c05a1SKan Liang 26787b2c05a1SKan Liang /* Only need to call update_topdown_event() once for group read. */ 26797b2c05a1SKan Liang if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 26807b2c05a1SKan Liang !is_slots_event(event)) 26817b2c05a1SKan Liang return; 26827b2c05a1SKan Liang 26837b2c05a1SKan Liang perf_pmu_disable(event->pmu); 26847b2c05a1SKan Liang x86_pmu.update_topdown_event(event); 26857b2c05a1SKan Liang perf_pmu_enable(event->pmu); 26867b2c05a1SKan Liang } 26877b2c05a1SKan Liang 2688ceb90d9eSKan Liang static void intel_pmu_read_event(struct perf_event *event) 2689ceb90d9eSKan Liang { 2690ceb90d9eSKan Liang if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2691ceb90d9eSKan Liang intel_pmu_auto_reload_read(event); 26927b2c05a1SKan Liang else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 26937b2c05a1SKan Liang intel_pmu_read_topdown_event(event); 2694ceb90d9eSKan Liang else 2695ceb90d9eSKan Liang x86_perf_event_update(event); 2696ceb90d9eSKan Liang } 2697ceb90d9eSKan Liang 26984f08b625SKan Liang static void intel_pmu_enable_fixed(struct perf_event *event) 2699e1069839SBorislav Petkov { 27004f08b625SKan Liang struct hw_perf_event *hwc = &event->hw; 27014f08b625SKan Liang u64 ctrl_val, mask, bits = 0; 27027b2c05a1SKan Liang int idx = hwc->idx; 27037b2c05a1SKan Liang 27047b2c05a1SKan Liang if (is_topdown_idx(idx)) { 27057b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 27067b2c05a1SKan Liang /* 27077b2c05a1SKan Liang * When there are other active TopDown events, 27087b2c05a1SKan Liang * don't enable the fixed counter 3 again. 27097b2c05a1SKan Liang */ 27107b2c05a1SKan Liang if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 27117b2c05a1SKan Liang return; 27127b2c05a1SKan Liang 27137b2c05a1SKan Liang idx = INTEL_PMC_IDX_FIXED_SLOTS; 27147b2c05a1SKan Liang } 27157b2c05a1SKan Liang 27167b2c05a1SKan Liang intel_set_masks(event, idx); 2717e1069839SBorislav Petkov 2718e1069839SBorislav Petkov /* 27194f08b625SKan Liang * Enable IRQ generation (0x8), if not PEBS, 2720e1069839SBorislav Petkov * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2721e1069839SBorislav Petkov * if requested: 2722e1069839SBorislav Petkov */ 27234f08b625SKan Liang if (!event->attr.precise_ip) 27244f08b625SKan Liang bits |= 0x8; 2725e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2726e1069839SBorislav Petkov bits |= 0x2; 2727e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2728e1069839SBorislav Petkov bits |= 0x1; 2729e1069839SBorislav Petkov 2730e1069839SBorislav Petkov /* 2731e1069839SBorislav Petkov * ANY bit is supported in v3 and up 2732e1069839SBorislav Petkov */ 2733e1069839SBorislav Petkov if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2734e1069839SBorislav Petkov bits |= 0x4; 2735e1069839SBorislav Petkov 27367b2c05a1SKan Liang idx -= INTEL_PMC_IDX_FIXED; 2737e1069839SBorislav Petkov bits <<= (idx * 4); 2738e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2739e1069839SBorislav Petkov 2740c22497f5SKan Liang if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2741c22497f5SKan Liang bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2742c22497f5SKan Liang mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2743c22497f5SKan Liang } 2744c22497f5SKan Liang 2745e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2746e1069839SBorislav Petkov ctrl_val &= ~mask; 2747e1069839SBorislav Petkov ctrl_val |= bits; 2748e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2749e1069839SBorislav Petkov } 2750e1069839SBorislav Petkov 2751e1069839SBorislav Petkov static void intel_pmu_enable_event(struct perf_event *event) 2752e1069839SBorislav Petkov { 2753e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2754027440b5SLike Xu int idx = hwc->idx; 2755e1069839SBorislav Petkov 2756e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2757e1069839SBorislav Petkov intel_pmu_pebs_enable(event); 2758e1069839SBorislav Petkov 275958da7dbeSKan Liang switch (idx) { 276058da7dbeSKan Liang case 0 ... INTEL_PMC_IDX_FIXED - 1: 2761027440b5SLike Xu intel_set_masks(event, idx); 2762e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 276358da7dbeSKan Liang break; 276458da7dbeSKan Liang case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 27657b2c05a1SKan Liang case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2766027440b5SLike Xu intel_pmu_enable_fixed(event); 276758da7dbeSKan Liang break; 276858da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_BTS: 2769027440b5SLike Xu if (!__this_cpu_read(cpu_hw_events.enabled)) 2770027440b5SLike Xu return; 2771027440b5SLike Xu intel_pmu_enable_bts(hwc->config); 277258da7dbeSKan Liang break; 277358da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_VLBR: 2774e1ad1ac2SLike Xu intel_set_masks(event, idx); 277558da7dbeSKan Liang break; 277658da7dbeSKan Liang default: 277758da7dbeSKan Liang pr_warn("Failed to enable the event with invalid index %d\n", 277858da7dbeSKan Liang idx); 277958da7dbeSKan Liang } 2780e1069839SBorislav Petkov } 2781e1069839SBorislav Petkov 278268f7082fSPeter Zijlstra static void intel_pmu_add_event(struct perf_event *event) 278368f7082fSPeter Zijlstra { 278468f7082fSPeter Zijlstra if (event->attr.precise_ip) 278568f7082fSPeter Zijlstra intel_pmu_pebs_add(event); 278668f7082fSPeter Zijlstra if (needs_branch_stack(event)) 278768f7082fSPeter Zijlstra intel_pmu_lbr_add(event); 278868f7082fSPeter Zijlstra } 278968f7082fSPeter Zijlstra 2790e1069839SBorislav Petkov /* 2791e1069839SBorislav Petkov * Save and restart an expired event. Called by NMI contexts, 2792e1069839SBorislav Petkov * so it has to be careful about preempting normal event ops: 2793e1069839SBorislav Petkov */ 2794e1069839SBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event) 2795e1069839SBorislav Petkov { 2796e1069839SBorislav Petkov x86_perf_event_update(event); 2797e1069839SBorislav Petkov /* 2798e1069839SBorislav Petkov * For a checkpointed counter always reset back to 0. This 2799e1069839SBorislav Petkov * avoids a situation where the counter overflows, aborts the 2800e1069839SBorislav Petkov * transaction and is then set back to shortly before the 2801e1069839SBorislav Petkov * overflow, and overflows and aborts again. 2802e1069839SBorislav Petkov */ 2803e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) { 2804e1069839SBorislav Petkov /* No race with NMIs because the counter should not be armed */ 2805e1069839SBorislav Petkov wrmsrl(event->hw.event_base, 0); 2806e1069839SBorislav Petkov local64_set(&event->hw.prev_count, 0); 2807e1069839SBorislav Petkov } 2808e1069839SBorislav Petkov return x86_perf_event_set_period(event); 2809e1069839SBorislav Petkov } 2810e1069839SBorislav Petkov 2811e1069839SBorislav Petkov static void intel_pmu_reset(void) 2812e1069839SBorislav Petkov { 2813e1069839SBorislav Petkov struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2814fc4b8fcaSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2815d4b294bfSKan Liang int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); 2816d4b294bfSKan Liang int num_counters = hybrid(cpuc->pmu, num_counters); 2817e1069839SBorislav Petkov unsigned long flags; 2818e1069839SBorislav Petkov int idx; 2819e1069839SBorislav Petkov 2820d4b294bfSKan Liang if (!num_counters) 2821e1069839SBorislav Petkov return; 2822e1069839SBorislav Petkov 2823e1069839SBorislav Petkov local_irq_save(flags); 2824e1069839SBorislav Petkov 2825e1069839SBorislav Petkov pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2826e1069839SBorislav Petkov 2827d4b294bfSKan Liang for (idx = 0; idx < num_counters; idx++) { 2828e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2829e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2830e1069839SBorislav Petkov } 2831d4b294bfSKan Liang for (idx = 0; idx < num_counters_fixed; idx++) { 2832fc4b8fcaSKan Liang if (fixed_counter_disabled(idx, cpuc->pmu)) 283332451614SKan Liang continue; 2834e1069839SBorislav Petkov wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 283532451614SKan Liang } 2836e1069839SBorislav Petkov 2837e1069839SBorislav Petkov if (ds) 2838e1069839SBorislav Petkov ds->bts_index = ds->bts_buffer_base; 2839e1069839SBorislav Petkov 2840e1069839SBorislav Petkov /* Ack all overflows and disable fixed counters */ 2841e1069839SBorislav Petkov if (x86_pmu.version >= 2) { 2842e1069839SBorislav Petkov intel_pmu_ack_status(intel_pmu_get_status()); 2843e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2844e1069839SBorislav Petkov } 2845e1069839SBorislav Petkov 2846e1069839SBorislav Petkov /* Reset LBRs and LBR freezing */ 2847e1069839SBorislav Petkov if (x86_pmu.lbr_nr) { 2848e1069839SBorislav Petkov update_debugctlmsr(get_debugctlmsr() & 2849e1069839SBorislav Petkov ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2850e1069839SBorislav Petkov } 2851e1069839SBorislav Petkov 2852e1069839SBorislav Petkov local_irq_restore(flags); 2853e1069839SBorislav Petkov } 2854e1069839SBorislav Petkov 2855ba12d20eSKan Liang static int handle_pmi_common(struct pt_regs *regs, u64 status) 2856e1069839SBorislav Petkov { 2857e1069839SBorislav Petkov struct perf_sample_data data; 2858ba12d20eSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2859ba12d20eSKan Liang int bit; 2860ba12d20eSKan Liang int handled = 0; 2861fc4b8fcaSKan Liang u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2862e1069839SBorislav Petkov 2863e1069839SBorislav Petkov inc_irq_stat(apic_perf_irqs); 2864e1069839SBorislav Petkov 2865e1069839SBorislav Petkov /* 2866e1069839SBorislav Petkov * Ignore a range of extra bits in status that do not indicate 2867e1069839SBorislav Petkov * overflow by themselves. 2868e1069839SBorislav Petkov */ 2869e1069839SBorislav Petkov status &= ~(GLOBAL_STATUS_COND_CHG | 2870e1069839SBorislav Petkov GLOBAL_STATUS_ASIF | 2871e1069839SBorislav Petkov GLOBAL_STATUS_LBRS_FROZEN); 2872e1069839SBorislav Petkov if (!status) 2873ba12d20eSKan Liang return 0; 2874daa864b8SStephane Eranian /* 2875daa864b8SStephane Eranian * In case multiple PEBS events are sampled at the same time, 2876daa864b8SStephane Eranian * it is possible to have GLOBAL_STATUS bit 62 set indicating 2877daa864b8SStephane Eranian * PEBS buffer overflow and also seeing at most 3 PEBS counters 2878daa864b8SStephane Eranian * having their bits set in the status register. This is a sign 2879daa864b8SStephane Eranian * that there was at least one PEBS record pending at the time 2880daa864b8SStephane Eranian * of the PMU interrupt. PEBS counters must only be processed 2881daa864b8SStephane Eranian * via the drain_pebs() calls and not via the regular sample 2882daa864b8SStephane Eranian * processing loop coming after that the function, otherwise 2883daa864b8SStephane Eranian * phony regular samples may be generated in the sampling buffer 2884daa864b8SStephane Eranian * not marked with the EXACT tag. Another possibility is to have 2885daa864b8SStephane Eranian * one PEBS event and at least one non-PEBS event which overflows 2886daa864b8SStephane Eranian * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2887daa864b8SStephane Eranian * not be set, yet the overflow status bit for the PEBS counter will 2888daa864b8SStephane Eranian * be on Skylake. 2889daa864b8SStephane Eranian * 2890daa864b8SStephane Eranian * To avoid this problem, we systematically ignore the PEBS-enabled 2891daa864b8SStephane Eranian * counters from the GLOBAL_STATUS mask and we always process PEBS 2892daa864b8SStephane Eranian * events via drain_pebs(). 2893daa864b8SStephane Eranian */ 2894ec71a398SKan Liang if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2895ec71a398SKan Liang status &= ~cpuc->pebs_enabled; 2896ec71a398SKan Liang else 2897fd583ad1SKan Liang status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2898e1069839SBorislav Petkov 2899e1069839SBorislav Petkov /* 2900e1069839SBorislav Petkov * PEBS overflow sets bit 62 in the global status register 2901e1069839SBorislav Petkov */ 290260a2a271SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 29036c1c07b3SKan Liang u64 pebs_enabled = cpuc->pebs_enabled; 29046c1c07b3SKan Liang 2905e1069839SBorislav Petkov handled++; 29069dfa9a5cSPeter Zijlstra x86_pmu.drain_pebs(regs, &data); 2907fc4b8fcaSKan Liang status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 29086c1c07b3SKan Liang 29096c1c07b3SKan Liang /* 29106c1c07b3SKan Liang * PMI throttle may be triggered, which stops the PEBS event. 29116c1c07b3SKan Liang * Although cpuc->pebs_enabled is updated accordingly, the 29126c1c07b3SKan Liang * MSR_IA32_PEBS_ENABLE is not updated. Because the 29136c1c07b3SKan Liang * cpuc->enabled has been forced to 0 in PMI. 29146c1c07b3SKan Liang * Update the MSR if pebs_enabled is changed. 29156c1c07b3SKan Liang */ 29166c1c07b3SKan Liang if (pebs_enabled != cpuc->pebs_enabled) 29176c1c07b3SKan Liang wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2918e1069839SBorislav Petkov } 2919e1069839SBorislav Petkov 2920e1069839SBorislav Petkov /* 2921e1069839SBorislav Petkov * Intel PT 2922e1069839SBorislav Petkov */ 292360a2a271SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2924e1069839SBorislav Petkov handled++; 29251c343051SSean Christopherson if (!perf_guest_handle_intel_pt_intr()) 2926e1069839SBorislav Petkov intel_pt_interrupt(); 2927e1069839SBorislav Petkov } 2928e1069839SBorislav Petkov 2929e1069839SBorislav Petkov /* 2930d9f6e12fSIngo Molnar * Intel Perf metrics 29317b2c05a1SKan Liang */ 29327b2c05a1SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 29337b2c05a1SKan Liang handled++; 29347b2c05a1SKan Liang if (x86_pmu.update_topdown_event) 29357b2c05a1SKan Liang x86_pmu.update_topdown_event(NULL); 29367b2c05a1SKan Liang } 29377b2c05a1SKan Liang 29387b2c05a1SKan Liang /* 2939e1069839SBorislav Petkov * Checkpointed counters can lead to 'spurious' PMIs because the 2940e1069839SBorislav Petkov * rollback caused by the PMI will have cleared the overflow status 2941e1069839SBorislav Petkov * bit. Therefore always force probe these counters. 2942e1069839SBorislav Petkov */ 2943e1069839SBorislav Petkov status |= cpuc->intel_cp_status; 2944e1069839SBorislav Petkov 2945e1069839SBorislav Petkov for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2946e1069839SBorislav Petkov struct perf_event *event = cpuc->events[bit]; 2947e1069839SBorislav Petkov 2948e1069839SBorislav Petkov handled++; 2949e1069839SBorislav Petkov 2950e1069839SBorislav Petkov if (!test_bit(bit, cpuc->active_mask)) 2951e1069839SBorislav Petkov continue; 2952e1069839SBorislav Petkov 2953e1069839SBorislav Petkov if (!intel_pmu_save_and_restart(event)) 2954e1069839SBorislav Petkov continue; 2955e1069839SBorislav Petkov 2956e1069839SBorislav Petkov perf_sample_data_init(&data, 0, event->hw.last_period); 2957e1069839SBorislav Petkov 2958e1069839SBorislav Petkov if (has_branch_stack(event)) 2959e1069839SBorislav Petkov data.br_stack = &cpuc->lbr_stack; 2960e1069839SBorislav Petkov 2961e1069839SBorislav Petkov if (perf_event_overflow(event, &data, regs)) 2962e1069839SBorislav Petkov x86_pmu_stop(event, 0); 2963e1069839SBorislav Petkov } 2964e1069839SBorislav Petkov 2965ba12d20eSKan Liang return handled; 2966ba12d20eSKan Liang } 2967ba12d20eSKan Liang 2968ba12d20eSKan Liang /* 2969ba12d20eSKan Liang * This handler is triggered by the local APIC, so the APIC IRQ handling 2970ba12d20eSKan Liang * rules apply: 2971ba12d20eSKan Liang */ 2972ba12d20eSKan Liang static int intel_pmu_handle_irq(struct pt_regs *regs) 2973ba12d20eSKan Liang { 2974acade637SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2975acade637SKan Liang bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 2976acade637SKan Liang bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 2977ba12d20eSKan Liang int loops; 2978ba12d20eSKan Liang u64 status; 2979ba12d20eSKan Liang int handled; 2980ba12d20eSKan Liang int pmu_enabled; 2981ba12d20eSKan Liang 2982ba12d20eSKan Liang /* 2983ba12d20eSKan Liang * Save the PMU state. 2984ba12d20eSKan Liang * It needs to be restored when leaving the handler. 2985ba12d20eSKan Liang */ 2986ba12d20eSKan Liang pmu_enabled = cpuc->enabled; 2987ba12d20eSKan Liang /* 2988acade637SKan Liang * In general, the early ACK is only applied for old platforms. 2989acade637SKan Liang * For the big core starts from Haswell, the late ACK should be 2990acade637SKan Liang * applied. 2991acade637SKan Liang * For the small core after Tremont, we have to do the ACK right 2992acade637SKan Liang * before re-enabling counters, which is in the middle of the 2993acade637SKan Liang * NMI handler. 2994ba12d20eSKan Liang */ 2995acade637SKan Liang if (!late_ack && !mid_ack) 2996ba12d20eSKan Liang apic_write(APIC_LVTPC, APIC_DM_NMI); 2997ba12d20eSKan Liang intel_bts_disable_local(); 2998ba12d20eSKan Liang cpuc->enabled = 0; 2999c22ac2a3SSong Liu __intel_pmu_disable_all(true); 3000ba12d20eSKan Liang handled = intel_pmu_drain_bts_buffer(); 3001ba12d20eSKan Liang handled += intel_bts_interrupt(); 3002ba12d20eSKan Liang status = intel_pmu_get_status(); 3003ba12d20eSKan Liang if (!status) 3004ba12d20eSKan Liang goto done; 3005ba12d20eSKan Liang 3006ba12d20eSKan Liang loops = 0; 3007ba12d20eSKan Liang again: 3008ba12d20eSKan Liang intel_pmu_lbr_read(); 3009ba12d20eSKan Liang intel_pmu_ack_status(status); 3010ba12d20eSKan Liang if (++loops > 100) { 3011ba12d20eSKan Liang static bool warned; 3012ba12d20eSKan Liang 3013ba12d20eSKan Liang if (!warned) { 3014ba12d20eSKan Liang WARN(1, "perfevents: irq loop stuck!\n"); 3015ba12d20eSKan Liang perf_event_print_debug(); 3016ba12d20eSKan Liang warned = true; 3017ba12d20eSKan Liang } 3018ba12d20eSKan Liang intel_pmu_reset(); 3019ba12d20eSKan Liang goto done; 3020ba12d20eSKan Liang } 3021ba12d20eSKan Liang 3022ba12d20eSKan Liang handled += handle_pmi_common(regs, status); 3023ba12d20eSKan Liang 3024e1069839SBorislav Petkov /* 3025e1069839SBorislav Petkov * Repeat if there is more work to be done: 3026e1069839SBorislav Petkov */ 3027e1069839SBorislav Petkov status = intel_pmu_get_status(); 3028e1069839SBorislav Petkov if (status) 3029e1069839SBorislav Petkov goto again; 3030e1069839SBorislav Petkov 3031e1069839SBorislav Petkov done: 3032acade637SKan Liang if (mid_ack) 3033acade637SKan Liang apic_write(APIC_LVTPC, APIC_DM_NMI); 3034c3d266c8SKan Liang /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 303582d71ed0SKan Liang cpuc->enabled = pmu_enabled; 303682d71ed0SKan Liang if (pmu_enabled) 3037e1069839SBorislav Petkov __intel_pmu_enable_all(0, true); 3038cecf6235SAlexander Shishkin intel_bts_enable_local(); 3039c3d266c8SKan Liang 3040e1069839SBorislav Petkov /* 3041e1069839SBorislav Petkov * Only unmask the NMI after the overflow counters 3042e1069839SBorislav Petkov * have been reset. This avoids spurious NMIs on 3043e1069839SBorislav Petkov * Haswell CPUs. 3044e1069839SBorislav Petkov */ 3045acade637SKan Liang if (late_ack) 3046e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 3047e1069839SBorislav Petkov return handled; 3048e1069839SBorislav Petkov } 3049e1069839SBorislav Petkov 3050e1069839SBorislav Petkov static struct event_constraint * 3051e1069839SBorislav Petkov intel_bts_constraints(struct perf_event *event) 3052e1069839SBorislav Petkov { 305367266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) 3054e1069839SBorislav Petkov return &bts_constraint; 3055e1069839SBorislav Petkov 3056e1069839SBorislav Petkov return NULL; 3057e1069839SBorislav Petkov } 3058e1069839SBorislav Petkov 3059097e4311SLike Xu /* 3060097e4311SLike Xu * Note: matches a fake event, like Fixed2. 3061097e4311SLike Xu */ 3062097e4311SLike Xu static struct event_constraint * 3063097e4311SLike Xu intel_vlbr_constraints(struct perf_event *event) 3064097e4311SLike Xu { 3065097e4311SLike Xu struct event_constraint *c = &vlbr_constraint; 3066097e4311SLike Xu 306758637025SLike Xu if (unlikely(constraint_match(c, event->hw.config))) { 306858637025SLike Xu event->hw.flags |= c->flags; 3069097e4311SLike Xu return c; 307058637025SLike Xu } 3071097e4311SLike Xu 3072097e4311SLike Xu return NULL; 3073097e4311SLike Xu } 3074097e4311SLike Xu 3075183af736SKan Liang static int intel_alt_er(struct cpu_hw_events *cpuc, 3076183af736SKan Liang int idx, u64 config) 3077e1069839SBorislav Petkov { 3078183af736SKan Liang struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3079e1069839SBorislav Petkov int alt_idx = idx; 3080e1069839SBorislav Petkov 3081e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3082e1069839SBorislav Petkov return idx; 3083e1069839SBorislav Petkov 3084e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) 3085e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_1; 3086e1069839SBorislav Petkov 3087e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_1) 3088e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_0; 3089e1069839SBorislav Petkov 3090183af736SKan Liang if (config & ~extra_regs[alt_idx].valid_mask) 3091e1069839SBorislav Petkov return idx; 3092e1069839SBorislav Petkov 3093e1069839SBorislav Petkov return alt_idx; 3094e1069839SBorislav Petkov } 3095e1069839SBorislav Petkov 3096e1069839SBorislav Petkov static void intel_fixup_er(struct perf_event *event, int idx) 3097e1069839SBorislav Petkov { 3098183af736SKan Liang struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3099e1069839SBorislav Petkov event->hw.extra_reg.idx = idx; 3100e1069839SBorislav Petkov 3101e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) { 3102e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3103183af736SKan Liang event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3104e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3105e1069839SBorislav Petkov } else if (idx == EXTRA_REG_RSP_1) { 3106e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3107183af736SKan Liang event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3108e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3109e1069839SBorislav Petkov } 3110e1069839SBorislav Petkov } 3111e1069839SBorislav Petkov 3112e1069839SBorislav Petkov /* 3113e1069839SBorislav Petkov * manage allocation of shared extra msr for certain events 3114e1069839SBorislav Petkov * 3115e1069839SBorislav Petkov * sharing can be: 3116e1069839SBorislav Petkov * per-cpu: to be shared between the various events on a single PMU 3117e1069839SBorislav Petkov * per-core: per-cpu + shared by HT threads 3118e1069839SBorislav Petkov */ 3119e1069839SBorislav Petkov static struct event_constraint * 3120e1069839SBorislav Petkov __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3121e1069839SBorislav Petkov struct perf_event *event, 3122e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 3123e1069839SBorislav Petkov { 3124e1069839SBorislav Petkov struct event_constraint *c = &emptyconstraint; 3125e1069839SBorislav Petkov struct er_account *era; 3126e1069839SBorislav Petkov unsigned long flags; 3127e1069839SBorislav Petkov int idx = reg->idx; 3128e1069839SBorislav Petkov 3129e1069839SBorislav Petkov /* 3130e1069839SBorislav Petkov * reg->alloc can be set due to existing state, so for fake cpuc we 3131e1069839SBorislav Petkov * need to ignore this, otherwise we might fail to allocate proper fake 3132e1069839SBorislav Petkov * state for this extra reg constraint. Also see the comment below. 3133e1069839SBorislav Petkov */ 3134e1069839SBorislav Petkov if (reg->alloc && !cpuc->is_fake) 3135e1069839SBorislav Petkov return NULL; /* call x86_get_event_constraint() */ 3136e1069839SBorislav Petkov 3137e1069839SBorislav Petkov again: 3138e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[idx]; 3139e1069839SBorislav Petkov /* 3140e1069839SBorislav Petkov * we use spin_lock_irqsave() to avoid lockdep issues when 3141e1069839SBorislav Petkov * passing a fake cpuc 3142e1069839SBorislav Petkov */ 3143e1069839SBorislav Petkov raw_spin_lock_irqsave(&era->lock, flags); 3144e1069839SBorislav Petkov 3145e1069839SBorislav Petkov if (!atomic_read(&era->ref) || era->config == reg->config) { 3146e1069839SBorislav Petkov 3147e1069839SBorislav Petkov /* 3148e1069839SBorislav Petkov * If its a fake cpuc -- as per validate_{group,event}() we 3149e1069839SBorislav Petkov * shouldn't touch event state and we can avoid doing so 3150e1069839SBorislav Petkov * since both will only call get_event_constraints() once 3151e1069839SBorislav Petkov * on each event, this avoids the need for reg->alloc. 3152e1069839SBorislav Petkov * 3153e1069839SBorislav Petkov * Not doing the ER fixup will only result in era->reg being 3154e1069839SBorislav Petkov * wrong, but since we won't actually try and program hardware 3155e1069839SBorislav Petkov * this isn't a problem either. 3156e1069839SBorislav Petkov */ 3157e1069839SBorislav Petkov if (!cpuc->is_fake) { 3158e1069839SBorislav Petkov if (idx != reg->idx) 3159e1069839SBorislav Petkov intel_fixup_er(event, idx); 3160e1069839SBorislav Petkov 3161e1069839SBorislav Petkov /* 3162e1069839SBorislav Petkov * x86_schedule_events() can call get_event_constraints() 3163e1069839SBorislav Petkov * multiple times on events in the case of incremental 3164e1069839SBorislav Petkov * scheduling(). reg->alloc ensures we only do the ER 3165e1069839SBorislav Petkov * allocation once. 3166e1069839SBorislav Petkov */ 3167e1069839SBorislav Petkov reg->alloc = 1; 3168e1069839SBorislav Petkov } 3169e1069839SBorislav Petkov 3170e1069839SBorislav Petkov /* lock in msr value */ 3171e1069839SBorislav Petkov era->config = reg->config; 3172e1069839SBorislav Petkov era->reg = reg->reg; 3173e1069839SBorislav Petkov 3174e1069839SBorislav Petkov /* one more user */ 3175e1069839SBorislav Petkov atomic_inc(&era->ref); 3176e1069839SBorislav Petkov 3177e1069839SBorislav Petkov /* 3178e1069839SBorislav Petkov * need to call x86_get_event_constraint() 3179e1069839SBorislav Petkov * to check if associated event has constraints 3180e1069839SBorislav Petkov */ 3181e1069839SBorislav Petkov c = NULL; 3182e1069839SBorislav Petkov } else { 3183183af736SKan Liang idx = intel_alt_er(cpuc, idx, reg->config); 3184e1069839SBorislav Petkov if (idx != reg->idx) { 3185e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 3186e1069839SBorislav Petkov goto again; 3187e1069839SBorislav Petkov } 3188e1069839SBorislav Petkov } 3189e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 3190e1069839SBorislav Petkov 3191e1069839SBorislav Petkov return c; 3192e1069839SBorislav Petkov } 3193e1069839SBorislav Petkov 3194e1069839SBorislav Petkov static void 3195e1069839SBorislav Petkov __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3196e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 3197e1069839SBorislav Petkov { 3198e1069839SBorislav Petkov struct er_account *era; 3199e1069839SBorislav Petkov 3200e1069839SBorislav Petkov /* 3201e1069839SBorislav Petkov * Only put constraint if extra reg was actually allocated. Also takes 3202e1069839SBorislav Petkov * care of event which do not use an extra shared reg. 3203e1069839SBorislav Petkov * 3204e1069839SBorislav Petkov * Also, if this is a fake cpuc we shouldn't touch any event state 3205e1069839SBorislav Petkov * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3206e1069839SBorislav Petkov * either since it'll be thrown out. 3207e1069839SBorislav Petkov */ 3208e1069839SBorislav Petkov if (!reg->alloc || cpuc->is_fake) 3209e1069839SBorislav Petkov return; 3210e1069839SBorislav Petkov 3211e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[reg->idx]; 3212e1069839SBorislav Petkov 3213e1069839SBorislav Petkov /* one fewer user */ 3214e1069839SBorislav Petkov atomic_dec(&era->ref); 3215e1069839SBorislav Petkov 3216e1069839SBorislav Petkov /* allocate again next time */ 3217e1069839SBorislav Petkov reg->alloc = 0; 3218e1069839SBorislav Petkov } 3219e1069839SBorislav Petkov 3220e1069839SBorislav Petkov static struct event_constraint * 3221e1069839SBorislav Petkov intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3222e1069839SBorislav Petkov struct perf_event *event) 3223e1069839SBorislav Petkov { 3224e1069839SBorislav Petkov struct event_constraint *c = NULL, *d; 3225e1069839SBorislav Petkov struct hw_perf_event_extra *xreg, *breg; 3226e1069839SBorislav Petkov 3227e1069839SBorislav Petkov xreg = &event->hw.extra_reg; 3228e1069839SBorislav Petkov if (xreg->idx != EXTRA_REG_NONE) { 3229e1069839SBorislav Petkov c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3230e1069839SBorislav Petkov if (c == &emptyconstraint) 3231e1069839SBorislav Petkov return c; 3232e1069839SBorislav Petkov } 3233e1069839SBorislav Petkov breg = &event->hw.branch_reg; 3234e1069839SBorislav Petkov if (breg->idx != EXTRA_REG_NONE) { 3235e1069839SBorislav Petkov d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3236e1069839SBorislav Petkov if (d == &emptyconstraint) { 3237e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, xreg); 3238e1069839SBorislav Petkov c = d; 3239e1069839SBorislav Petkov } 3240e1069839SBorislav Petkov } 3241e1069839SBorislav Petkov return c; 3242e1069839SBorislav Petkov } 3243e1069839SBorislav Petkov 3244e1069839SBorislav Petkov struct event_constraint * 3245e1069839SBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3246e1069839SBorislav Petkov struct perf_event *event) 3247e1069839SBorislav Petkov { 324824ee38ffSKan Liang struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3249e1069839SBorislav Petkov struct event_constraint *c; 3250e1069839SBorislav Petkov 325124ee38ffSKan Liang if (event_constraints) { 325224ee38ffSKan Liang for_each_event_constraint(c, event_constraints) { 325363b79f6eSPeter Zijlstra if (constraint_match(c, event->hw.config)) { 3254e1069839SBorislav Petkov event->hw.flags |= c->flags; 3255e1069839SBorislav Petkov return c; 3256e1069839SBorislav Petkov } 3257e1069839SBorislav Petkov } 3258e1069839SBorislav Petkov } 3259e1069839SBorislav Petkov 3260eaacf07dSKan Liang return &hybrid_var(cpuc->pmu, unconstrained); 3261e1069839SBorislav Petkov } 3262e1069839SBorislav Petkov 3263e1069839SBorislav Petkov static struct event_constraint * 3264e1069839SBorislav Petkov __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3265e1069839SBorislav Petkov struct perf_event *event) 3266e1069839SBorislav Petkov { 3267e1069839SBorislav Petkov struct event_constraint *c; 3268e1069839SBorislav Petkov 3269097e4311SLike Xu c = intel_vlbr_constraints(event); 3270097e4311SLike Xu if (c) 3271097e4311SLike Xu return c; 3272097e4311SLike Xu 3273e1069839SBorislav Petkov c = intel_bts_constraints(event); 3274e1069839SBorislav Petkov if (c) 3275e1069839SBorislav Petkov return c; 3276e1069839SBorislav Petkov 3277e1069839SBorislav Petkov c = intel_shared_regs_constraints(cpuc, event); 3278e1069839SBorislav Petkov if (c) 3279e1069839SBorislav Petkov return c; 3280e1069839SBorislav Petkov 3281e1069839SBorislav Petkov c = intel_pebs_constraints(event); 3282e1069839SBorislav Petkov if (c) 3283e1069839SBorislav Petkov return c; 3284e1069839SBorislav Petkov 3285e1069839SBorislav Petkov return x86_get_event_constraints(cpuc, idx, event); 3286e1069839SBorislav Petkov } 3287e1069839SBorislav Petkov 3288e1069839SBorislav Petkov static void 3289e1069839SBorislav Petkov intel_start_scheduling(struct cpu_hw_events *cpuc) 3290e1069839SBorislav Petkov { 3291e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3292e1069839SBorislav Petkov struct intel_excl_states *xl; 3293e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3294e1069839SBorislav Petkov 3295e1069839SBorislav Petkov /* 3296e1069839SBorislav Petkov * nothing needed if in group validation mode 3297e1069839SBorislav Petkov */ 3298e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3299e1069839SBorislav Petkov return; 3300e1069839SBorislav Petkov 3301e1069839SBorislav Petkov /* 3302e1069839SBorislav Petkov * no exclusion needed 3303e1069839SBorislav Petkov */ 3304e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3305e1069839SBorislav Petkov return; 3306e1069839SBorislav Petkov 3307e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3308e1069839SBorislav Petkov 3309e1069839SBorislav Petkov xl->sched_started = true; 3310e1069839SBorislav Petkov /* 3311e1069839SBorislav Petkov * lock shared state until we are done scheduling 3312e1069839SBorislav Petkov * in stop_event_scheduling() 3313e1069839SBorislav Petkov * makes scheduling appear as a transaction 3314e1069839SBorislav Petkov */ 3315e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3316e1069839SBorislav Petkov } 3317e1069839SBorislav Petkov 3318e1069839SBorislav Petkov static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3319e1069839SBorislav Petkov { 3320e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3321e1069839SBorislav Petkov struct event_constraint *c = cpuc->event_constraint[idx]; 3322e1069839SBorislav Petkov struct intel_excl_states *xl; 3323e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3324e1069839SBorislav Petkov 3325e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3326e1069839SBorislav Petkov return; 3327e1069839SBorislav Petkov 3328e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3329e1069839SBorislav Petkov return; 3330e1069839SBorislav Petkov 3331e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3332e1069839SBorislav Petkov return; 3333e1069839SBorislav Petkov 3334e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3335e1069839SBorislav Petkov 3336e1069839SBorislav Petkov lockdep_assert_held(&excl_cntrs->lock); 3337e1069839SBorislav Petkov 3338e1069839SBorislav Petkov if (c->flags & PERF_X86_EVENT_EXCL) 3339e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3340e1069839SBorislav Petkov else 3341e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_SHARED; 3342e1069839SBorislav Petkov } 3343e1069839SBorislav Petkov 3344e1069839SBorislav Petkov static void 3345e1069839SBorislav Petkov intel_stop_scheduling(struct cpu_hw_events *cpuc) 3346e1069839SBorislav Petkov { 3347e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3348e1069839SBorislav Petkov struct intel_excl_states *xl; 3349e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3350e1069839SBorislav Petkov 3351e1069839SBorislav Petkov /* 3352e1069839SBorislav Petkov * nothing needed if in group validation mode 3353e1069839SBorislav Petkov */ 3354e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3355e1069839SBorislav Petkov return; 3356e1069839SBorislav Petkov /* 3357e1069839SBorislav Petkov * no exclusion needed 3358e1069839SBorislav Petkov */ 3359e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3360e1069839SBorislav Petkov return; 3361e1069839SBorislav Petkov 3362e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3363e1069839SBorislav Petkov 3364e1069839SBorislav Petkov xl->sched_started = false; 3365e1069839SBorislav Petkov /* 3366e1069839SBorislav Petkov * release shared state lock (acquired in intel_start_scheduling()) 3367e1069839SBorislav Petkov */ 3368e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3369e1069839SBorislav Petkov } 3370e1069839SBorislav Petkov 3371e1069839SBorislav Petkov static struct event_constraint * 337211f8b2d6SPeter Zijlstra (Intel) dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 337311f8b2d6SPeter Zijlstra (Intel) { 337411f8b2d6SPeter Zijlstra (Intel) WARN_ON_ONCE(!cpuc->constraint_list); 337511f8b2d6SPeter Zijlstra (Intel) 337611f8b2d6SPeter Zijlstra (Intel) if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 337711f8b2d6SPeter Zijlstra (Intel) struct event_constraint *cx; 337811f8b2d6SPeter Zijlstra (Intel) 337911f8b2d6SPeter Zijlstra (Intel) /* 338011f8b2d6SPeter Zijlstra (Intel) * grab pre-allocated constraint entry 338111f8b2d6SPeter Zijlstra (Intel) */ 338211f8b2d6SPeter Zijlstra (Intel) cx = &cpuc->constraint_list[idx]; 338311f8b2d6SPeter Zijlstra (Intel) 338411f8b2d6SPeter Zijlstra (Intel) /* 338511f8b2d6SPeter Zijlstra (Intel) * initialize dynamic constraint 338611f8b2d6SPeter Zijlstra (Intel) * with static constraint 338711f8b2d6SPeter Zijlstra (Intel) */ 338811f8b2d6SPeter Zijlstra (Intel) *cx = *c; 338911f8b2d6SPeter Zijlstra (Intel) 339011f8b2d6SPeter Zijlstra (Intel) /* 339111f8b2d6SPeter Zijlstra (Intel) * mark constraint as dynamic 339211f8b2d6SPeter Zijlstra (Intel) */ 339311f8b2d6SPeter Zijlstra (Intel) cx->flags |= PERF_X86_EVENT_DYNAMIC; 339411f8b2d6SPeter Zijlstra (Intel) c = cx; 339511f8b2d6SPeter Zijlstra (Intel) } 339611f8b2d6SPeter Zijlstra (Intel) 339711f8b2d6SPeter Zijlstra (Intel) return c; 339811f8b2d6SPeter Zijlstra (Intel) } 339911f8b2d6SPeter Zijlstra (Intel) 340011f8b2d6SPeter Zijlstra (Intel) static struct event_constraint * 3401e1069839SBorislav Petkov intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3402e1069839SBorislav Petkov int idx, struct event_constraint *c) 3403e1069839SBorislav Petkov { 3404e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3405e1069839SBorislav Petkov struct intel_excl_states *xlo; 3406e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3407c090cb70SPeter Zijlstra int is_excl, i, w; 3408e1069839SBorislav Petkov 3409e1069839SBorislav Petkov /* 3410e1069839SBorislav Petkov * validating a group does not require 3411e1069839SBorislav Petkov * enforcing cross-thread exclusion 3412e1069839SBorislav Petkov */ 3413e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3414e1069839SBorislav Petkov return c; 3415e1069839SBorislav Petkov 3416e1069839SBorislav Petkov /* 3417e1069839SBorislav Petkov * no exclusion needed 3418e1069839SBorislav Petkov */ 3419e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3420e1069839SBorislav Petkov return c; 3421e1069839SBorislav Petkov 3422e1069839SBorislav Petkov /* 3423e1069839SBorislav Petkov * because we modify the constraint, we need 3424e1069839SBorislav Petkov * to make a copy. Static constraints come 3425e1069839SBorislav Petkov * from static const tables. 3426e1069839SBorislav Petkov * 3427e1069839SBorislav Petkov * only needed when constraint has not yet 3428e1069839SBorislav Petkov * been cloned (marked dynamic) 3429e1069839SBorislav Petkov */ 343011f8b2d6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 3431e1069839SBorislav Petkov 3432e1069839SBorislav Petkov /* 3433e1069839SBorislav Petkov * From here on, the constraint is dynamic. 3434e1069839SBorislav Petkov * Either it was just allocated above, or it 3435e1069839SBorislav Petkov * was allocated during a earlier invocation 3436e1069839SBorislav Petkov * of this function 3437e1069839SBorislav Petkov */ 3438e1069839SBorislav Petkov 3439e1069839SBorislav Petkov /* 3440e1069839SBorislav Petkov * state of sibling HT 3441e1069839SBorislav Petkov */ 3442e1069839SBorislav Petkov xlo = &excl_cntrs->states[tid ^ 1]; 3443e1069839SBorislav Petkov 3444e1069839SBorislav Petkov /* 3445e1069839SBorislav Petkov * event requires exclusive counter access 3446e1069839SBorislav Petkov * across HT threads 3447e1069839SBorislav Petkov */ 3448e1069839SBorislav Petkov is_excl = c->flags & PERF_X86_EVENT_EXCL; 3449e1069839SBorislav Petkov if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3450e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3451e1069839SBorislav Petkov if (!cpuc->n_excl++) 3452e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3453e1069839SBorislav Petkov } 3454e1069839SBorislav Petkov 3455e1069839SBorislav Petkov /* 3456e1069839SBorislav Petkov * Modify static constraint with current dynamic 3457e1069839SBorislav Petkov * state of thread 3458e1069839SBorislav Petkov * 3459e1069839SBorislav Petkov * EXCLUSIVE: sibling counter measuring exclusive event 3460e1069839SBorislav Petkov * SHARED : sibling counter measuring non-exclusive event 3461e1069839SBorislav Petkov * UNUSED : sibling counter unused 3462e1069839SBorislav Petkov */ 3463c090cb70SPeter Zijlstra w = c->weight; 3464e1069839SBorislav Petkov for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3465e1069839SBorislav Petkov /* 3466e1069839SBorislav Petkov * exclusive event in sibling counter 3467e1069839SBorislav Petkov * our corresponding counter cannot be used 3468e1069839SBorislav Petkov * regardless of our event 3469e1069839SBorislav Petkov */ 3470c090cb70SPeter Zijlstra if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3471e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 3472c090cb70SPeter Zijlstra w--; 3473c090cb70SPeter Zijlstra continue; 3474c090cb70SPeter Zijlstra } 3475e1069839SBorislav Petkov /* 3476e1069839SBorislav Petkov * if measuring an exclusive event, sibling 3477e1069839SBorislav Petkov * measuring non-exclusive, then counter cannot 3478e1069839SBorislav Petkov * be used 3479e1069839SBorislav Petkov */ 3480c090cb70SPeter Zijlstra if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3481e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 3482c090cb70SPeter Zijlstra w--; 3483c090cb70SPeter Zijlstra continue; 3484e1069839SBorislav Petkov } 3485c090cb70SPeter Zijlstra } 3486e1069839SBorislav Petkov 3487e1069839SBorislav Petkov /* 3488e1069839SBorislav Petkov * if we return an empty mask, then switch 3489e1069839SBorislav Petkov * back to static empty constraint to avoid 3490e1069839SBorislav Petkov * the cost of freeing later on 3491e1069839SBorislav Petkov */ 3492c090cb70SPeter Zijlstra if (!w) 3493e1069839SBorislav Petkov c = &emptyconstraint; 3494e1069839SBorislav Petkov 3495c090cb70SPeter Zijlstra c->weight = w; 3496c090cb70SPeter Zijlstra 3497e1069839SBorislav Petkov return c; 3498e1069839SBorislav Petkov } 3499e1069839SBorislav Petkov 3500e1069839SBorislav Petkov static struct event_constraint * 3501e1069839SBorislav Petkov intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3502e1069839SBorislav Petkov struct perf_event *event) 3503e1069839SBorislav Petkov { 350421d65555SPeter Zijlstra struct event_constraint *c1, *c2; 3505e1069839SBorislav Petkov 3506e1069839SBorislav Petkov c1 = cpuc->event_constraint[idx]; 3507e1069839SBorislav Petkov 3508e1069839SBorislav Petkov /* 3509e1069839SBorislav Petkov * first time only 3510e1069839SBorislav Petkov * - static constraint: no change across incremental scheduling calls 3511e1069839SBorislav Petkov * - dynamic constraint: handled by intel_get_excl_constraints() 3512e1069839SBorislav Petkov */ 3513e1069839SBorislav Petkov c2 = __intel_get_event_constraints(cpuc, idx, event); 3514109717deSPeter Zijlstra if (c1) { 3515109717deSPeter Zijlstra WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3516e1069839SBorislav Petkov bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3517e1069839SBorislav Petkov c1->weight = c2->weight; 3518e1069839SBorislav Petkov c2 = c1; 3519e1069839SBorislav Petkov } 3520e1069839SBorislav Petkov 3521e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3522e1069839SBorislav Petkov return intel_get_excl_constraints(cpuc, event, idx, c2); 3523e1069839SBorislav Petkov 3524e1069839SBorislav Petkov return c2; 3525e1069839SBorislav Petkov } 3526e1069839SBorislav Petkov 3527e1069839SBorislav Petkov static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3528e1069839SBorislav Petkov struct perf_event *event) 3529e1069839SBorislav Petkov { 3530e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 3531e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3532e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3533e1069839SBorislav Petkov struct intel_excl_states *xl; 3534e1069839SBorislav Petkov 3535e1069839SBorislav Petkov /* 3536e1069839SBorislav Petkov * nothing needed if in group validation mode 3537e1069839SBorislav Petkov */ 3538e1069839SBorislav Petkov if (cpuc->is_fake) 3539e1069839SBorislav Petkov return; 3540e1069839SBorislav Petkov 3541e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3542e1069839SBorislav Petkov return; 3543e1069839SBorislav Petkov 3544e1069839SBorislav Petkov if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3545e1069839SBorislav Petkov hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3546e1069839SBorislav Petkov if (!--cpuc->n_excl) 3547e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3548e1069839SBorislav Petkov } 3549e1069839SBorislav Petkov 3550e1069839SBorislav Petkov /* 3551e1069839SBorislav Petkov * If event was actually assigned, then mark the counter state as 3552e1069839SBorislav Petkov * unused now. 3553e1069839SBorislav Petkov */ 3554e1069839SBorislav Petkov if (hwc->idx >= 0) { 3555e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3556e1069839SBorislav Petkov 3557e1069839SBorislav Petkov /* 3558e1069839SBorislav Petkov * put_constraint may be called from x86_schedule_events() 3559e1069839SBorislav Petkov * which already has the lock held so here make locking 3560e1069839SBorislav Petkov * conditional. 3561e1069839SBorislav Petkov */ 3562e1069839SBorislav Petkov if (!xl->sched_started) 3563e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3564e1069839SBorislav Petkov 3565e1069839SBorislav Petkov xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3566e1069839SBorislav Petkov 3567e1069839SBorislav Petkov if (!xl->sched_started) 3568e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3569e1069839SBorislav Petkov } 3570e1069839SBorislav Petkov } 3571e1069839SBorislav Petkov 3572e1069839SBorislav Petkov static void 3573e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3574e1069839SBorislav Petkov struct perf_event *event) 3575e1069839SBorislav Petkov { 3576e1069839SBorislav Petkov struct hw_perf_event_extra *reg; 3577e1069839SBorislav Petkov 3578e1069839SBorislav Petkov reg = &event->hw.extra_reg; 3579e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3580e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3581e1069839SBorislav Petkov 3582e1069839SBorislav Petkov reg = &event->hw.branch_reg; 3583e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3584e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3585e1069839SBorislav Petkov } 3586e1069839SBorislav Petkov 3587e1069839SBorislav Petkov static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3588e1069839SBorislav Petkov struct perf_event *event) 3589e1069839SBorislav Petkov { 3590e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(cpuc, event); 3591e1069839SBorislav Petkov 3592e1069839SBorislav Petkov /* 3593e1069839SBorislav Petkov * is PMU has exclusive counter restrictions, then 3594e1069839SBorislav Petkov * all events are subject to and must call the 3595e1069839SBorislav Petkov * put_excl_constraints() routine 3596e1069839SBorislav Petkov */ 3597e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3598e1069839SBorislav Petkov intel_put_excl_constraints(cpuc, event); 3599e1069839SBorislav Petkov } 3600e1069839SBorislav Petkov 3601e1069839SBorislav Petkov static void intel_pebs_aliases_core2(struct perf_event *event) 3602e1069839SBorislav Petkov { 3603e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3604e1069839SBorislav Petkov /* 3605e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3606e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3607e1069839SBorislav Petkov * 3608e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3609e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.ANY_P 3610e1069839SBorislav Petkov * (0x00c0), which is a PEBS capable event, to get the same 3611e1069839SBorislav Petkov * count. 3612e1069839SBorislav Petkov * 3613e1069839SBorislav Petkov * INST_RETIRED.ANY_P counts the number of cycles that retires 3614e1069839SBorislav Petkov * CNTMASK instructions. By setting CNTMASK to a value (16) 3615e1069839SBorislav Petkov * larger than the maximum number of instructions that can be 3616e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3617e1069839SBorislav Petkov * count all cycles that retire 16 or less instructions, which 3618e1069839SBorislav Petkov * is every cycle. 3619e1069839SBorislav Petkov * 3620e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3621e1069839SBorislav Petkov */ 3622e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3623e1069839SBorislav Petkov 3624e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3625e1069839SBorislav Petkov event->hw.config = alt_config; 3626e1069839SBorislav Petkov } 3627e1069839SBorislav Petkov } 3628e1069839SBorislav Petkov 3629e1069839SBorislav Petkov static void intel_pebs_aliases_snb(struct perf_event *event) 3630e1069839SBorislav Petkov { 3631e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3632e1069839SBorislav Petkov /* 3633e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3634e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3635e1069839SBorislav Petkov * 3636e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3637e1069839SBorislav Petkov * PEBS capable. However we can use UOPS_RETIRED.ALL 3638e1069839SBorislav Petkov * (0x01c2), which is a PEBS capable event, to get the same 3639e1069839SBorislav Petkov * count. 3640e1069839SBorislav Petkov * 3641e1069839SBorislav Petkov * UOPS_RETIRED.ALL counts the number of cycles that retires 3642e1069839SBorislav Petkov * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3643e1069839SBorislav Petkov * larger than the maximum number of micro-ops that can be 3644e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3645e1069839SBorislav Petkov * count all cycles that retire 16 or less micro-ops, which 3646e1069839SBorislav Petkov * is every cycle. 3647e1069839SBorislav Petkov * 3648e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3649e1069839SBorislav Petkov */ 3650e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3651e1069839SBorislav Petkov 3652e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3653e1069839SBorislav Petkov event->hw.config = alt_config; 3654e1069839SBorislav Petkov } 3655e1069839SBorislav Petkov } 3656e1069839SBorislav Petkov 3657e1069839SBorislav Petkov static void intel_pebs_aliases_precdist(struct perf_event *event) 3658e1069839SBorislav Petkov { 3659e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3660e1069839SBorislav Petkov /* 3661e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3662e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3663e1069839SBorislav Petkov * 3664e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3665e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3666e1069839SBorislav Petkov * (0x01c0), which is a PEBS capable event, to get the same 3667e1069839SBorislav Petkov * count. 3668e1069839SBorislav Petkov * 3669e1069839SBorislav Petkov * The PREC_DIST event has special support to minimize sample 3670e1069839SBorislav Petkov * shadowing effects. One drawback is that it can be 3671e1069839SBorislav Petkov * only programmed on counter 1, but that seems like an 3672e1069839SBorislav Petkov * acceptable trade off. 3673e1069839SBorislav Petkov */ 3674e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3675e1069839SBorislav Petkov 3676e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3677e1069839SBorislav Petkov event->hw.config = alt_config; 3678e1069839SBorislav Petkov } 3679e1069839SBorislav Petkov } 3680e1069839SBorislav Petkov 3681e1069839SBorislav Petkov static void intel_pebs_aliases_ivb(struct perf_event *event) 3682e1069839SBorislav Petkov { 3683e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3684e1069839SBorislav Petkov return intel_pebs_aliases_snb(event); 3685e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3686e1069839SBorislav Petkov } 3687e1069839SBorislav Petkov 3688e1069839SBorislav Petkov static void intel_pebs_aliases_skl(struct perf_event *event) 3689e1069839SBorislav Petkov { 3690e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3691e1069839SBorislav Petkov return intel_pebs_aliases_core2(event); 3692e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3693e1069839SBorislav Petkov } 3694e1069839SBorislav Petkov 3695174afc3eSKan Liang static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3696e1069839SBorislav Petkov { 3697174afc3eSKan Liang unsigned long flags = x86_pmu.large_pebs_flags; 3698e1069839SBorislav Petkov 3699e1069839SBorislav Petkov if (event->attr.use_clockid) 3700e1069839SBorislav Petkov flags &= ~PERF_SAMPLE_TIME; 3701a47ba4d7SAndi Kleen if (!event->attr.exclude_kernel) 3702a47ba4d7SAndi Kleen flags &= ~PERF_SAMPLE_REGS_USER; 37039d5dcc93SKan Liang if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3704a47ba4d7SAndi Kleen flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3705e1069839SBorislav Petkov return flags; 3706e1069839SBorislav Petkov } 3707e1069839SBorislav Petkov 3708ed6101bbSJiri Olsa static int intel_pmu_bts_config(struct perf_event *event) 3709ed6101bbSJiri Olsa { 3710ed6101bbSJiri Olsa struct perf_event_attr *attr = &event->attr; 3711ed6101bbSJiri Olsa 371267266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) { 3713ed6101bbSJiri Olsa /* BTS is not supported by this architecture. */ 3714ed6101bbSJiri Olsa if (!x86_pmu.bts_active) 3715ed6101bbSJiri Olsa return -EOPNOTSUPP; 3716ed6101bbSJiri Olsa 3717ed6101bbSJiri Olsa /* BTS is currently only allowed for user-mode. */ 3718ed6101bbSJiri Olsa if (!attr->exclude_kernel) 3719ed6101bbSJiri Olsa return -EOPNOTSUPP; 3720ed6101bbSJiri Olsa 3721472de49fSJiri Olsa /* BTS is not allowed for precise events. */ 3722472de49fSJiri Olsa if (attr->precise_ip) 3723472de49fSJiri Olsa return -EOPNOTSUPP; 3724472de49fSJiri Olsa 3725ed6101bbSJiri Olsa /* disallow bts if conflicting events are present */ 3726ed6101bbSJiri Olsa if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3727ed6101bbSJiri Olsa return -EBUSY; 3728ed6101bbSJiri Olsa 3729ed6101bbSJiri Olsa event->destroy = hw_perf_lbr_event_destroy; 3730ed6101bbSJiri Olsa } 3731ed6101bbSJiri Olsa 3732ed6101bbSJiri Olsa return 0; 3733ed6101bbSJiri Olsa } 3734ed6101bbSJiri Olsa 3735ed6101bbSJiri Olsa static int core_pmu_hw_config(struct perf_event *event) 3736ed6101bbSJiri Olsa { 3737ed6101bbSJiri Olsa int ret = x86_pmu_hw_config(event); 3738ed6101bbSJiri Olsa 3739ed6101bbSJiri Olsa if (ret) 3740ed6101bbSJiri Olsa return ret; 3741ed6101bbSJiri Olsa 3742ed6101bbSJiri Olsa return intel_pmu_bts_config(event); 3743ed6101bbSJiri Olsa } 3744ed6101bbSJiri Olsa 37451ab5f235SKan Liang #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 37461ab5f235SKan Liang ((x86_pmu.num_topdown_events - 1) << 8)) 37471ab5f235SKan Liang 37481ab5f235SKan Liang static bool is_available_metric_event(struct perf_event *event) 37491ab5f235SKan Liang { 37501ab5f235SKan Liang return is_metric_event(event) && 37511ab5f235SKan Liang event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 37521ab5f235SKan Liang } 37531ab5f235SKan Liang 375461b985e3SKan Liang static inline bool is_mem_loads_event(struct perf_event *event) 375561b985e3SKan Liang { 375661b985e3SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 375761b985e3SKan Liang } 375861b985e3SKan Liang 375961b985e3SKan Liang static inline bool is_mem_loads_aux_event(struct perf_event *event) 376061b985e3SKan Liang { 376161b985e3SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 376261b985e3SKan Liang } 376361b985e3SKan Liang 3764f83d2f91SKan Liang static inline bool require_mem_loads_aux_event(struct perf_event *event) 3765f83d2f91SKan Liang { 3766f83d2f91SKan Liang if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 3767f83d2f91SKan Liang return false; 3768f83d2f91SKan Liang 3769f83d2f91SKan Liang if (is_hybrid()) 3770f83d2f91SKan Liang return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; 3771f83d2f91SKan Liang 3772f83d2f91SKan Liang return true; 3773f83d2f91SKan Liang } 3774f83d2f91SKan Liang 3775d0946a88SKan Liang static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 3776d0946a88SKan Liang { 3777d0946a88SKan Liang union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 3778d0946a88SKan Liang 3779d0946a88SKan Liang return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 3780d0946a88SKan Liang } 378161b985e3SKan Liang 3782e1069839SBorislav Petkov static int intel_pmu_hw_config(struct perf_event *event) 3783e1069839SBorislav Petkov { 3784e1069839SBorislav Petkov int ret = x86_pmu_hw_config(event); 3785e1069839SBorislav Petkov 3786e1069839SBorislav Petkov if (ret) 3787e1069839SBorislav Petkov return ret; 3788e1069839SBorislav Petkov 3789ed6101bbSJiri Olsa ret = intel_pmu_bts_config(event); 3790ed6101bbSJiri Olsa if (ret) 3791ed6101bbSJiri Olsa return ret; 3792ed6101bbSJiri Olsa 3793e1069839SBorislav Petkov if (event->attr.precise_ip) { 37942dc0572fSKan Liang if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 37952dc0572fSKan Liang return -EINVAL; 37962dc0572fSKan Liang 3797c7a28657SStephane Eranian if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3798e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3799e1069839SBorislav Petkov if (!(event->attr.sample_type & 3800afbef301SKan Liang ~intel_pmu_large_pebs_flags(event))) { 3801174afc3eSKan Liang event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3802afbef301SKan Liang event->attach_state |= PERF_ATTACH_SCHED_CB; 3803afbef301SKan Liang } 3804e1069839SBorislav Petkov } 3805e1069839SBorislav Petkov if (x86_pmu.pebs_aliases) 3806e1069839SBorislav Petkov x86_pmu.pebs_aliases(event); 38076cbc304fSPeter Zijlstra 38086cbc304fSPeter Zijlstra if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 38096cbc304fSPeter Zijlstra event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3810e1069839SBorislav Petkov } 3811e1069839SBorislav Petkov 3812e1069839SBorislav Petkov if (needs_branch_stack(event)) { 3813e1069839SBorislav Petkov ret = intel_pmu_setup_lbr_filter(event); 3814e1069839SBorislav Petkov if (ret) 3815e1069839SBorislav Petkov return ret; 3816afbef301SKan Liang event->attach_state |= PERF_ATTACH_SCHED_CB; 3817e1069839SBorislav Petkov 3818e1069839SBorislav Petkov /* 3819e1069839SBorislav Petkov * BTS is set up earlier in this path, so don't account twice 3820e1069839SBorislav Petkov */ 382167266c10SJiri Olsa if (!unlikely(intel_pmu_has_bts(event))) { 3822e1069839SBorislav Petkov /* disallow lbr if conflicting events are present */ 3823e1069839SBorislav Petkov if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3824e1069839SBorislav Petkov return -EBUSY; 3825e1069839SBorislav Petkov 3826e1069839SBorislav Petkov event->destroy = hw_perf_lbr_event_destroy; 3827e1069839SBorislav Petkov } 3828e1069839SBorislav Petkov } 3829e1069839SBorislav Petkov 383042880f72SAlexander Shishkin if (event->attr.aux_output) { 383142880f72SAlexander Shishkin if (!event->attr.precise_ip) 383242880f72SAlexander Shishkin return -EINVAL; 383342880f72SAlexander Shishkin 383442880f72SAlexander Shishkin event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 383542880f72SAlexander Shishkin } 383642880f72SAlexander Shishkin 3837d9977c43SKan Liang if ((event->attr.type == PERF_TYPE_HARDWARE) || 3838d9977c43SKan Liang (event->attr.type == PERF_TYPE_HW_CACHE)) 3839e1069839SBorislav Petkov return 0; 3840e1069839SBorislav Petkov 38417b2c05a1SKan Liang /* 38427b2c05a1SKan Liang * Config Topdown slots and metric events 38437b2c05a1SKan Liang * 38447b2c05a1SKan Liang * The slots event on Fixed Counter 3 can support sampling, 38457b2c05a1SKan Liang * which will be handled normally in x86_perf_event_update(). 38467b2c05a1SKan Liang * 38477b2c05a1SKan Liang * Metric events don't support sampling and require being paired 38487b2c05a1SKan Liang * with a slots event as group leader. When the slots event 38497b2c05a1SKan Liang * is used in a metrics group, it too cannot support sampling. 38507b2c05a1SKan Liang */ 3851d0946a88SKan Liang if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 38527b2c05a1SKan Liang if (event->attr.config1 || event->attr.config2) 38537b2c05a1SKan Liang return -EINVAL; 38547b2c05a1SKan Liang 38557b2c05a1SKan Liang /* 38567b2c05a1SKan Liang * The TopDown metrics events and slots event don't 38577b2c05a1SKan Liang * support any filters. 38587b2c05a1SKan Liang */ 38597b2c05a1SKan Liang if (event->attr.config & X86_ALL_EVENT_FLAGS) 38607b2c05a1SKan Liang return -EINVAL; 38617b2c05a1SKan Liang 38621ab5f235SKan Liang if (is_available_metric_event(event)) { 38637b2c05a1SKan Liang struct perf_event *leader = event->group_leader; 38647b2c05a1SKan Liang 38657b2c05a1SKan Liang /* The metric events don't support sampling. */ 38667b2c05a1SKan Liang if (is_sampling_event(event)) 38677b2c05a1SKan Liang return -EINVAL; 38687b2c05a1SKan Liang 38697b2c05a1SKan Liang /* The metric events require a slots group leader. */ 38707b2c05a1SKan Liang if (!is_slots_event(leader)) 38717b2c05a1SKan Liang return -EINVAL; 38727b2c05a1SKan Liang 38737b2c05a1SKan Liang /* 38747b2c05a1SKan Liang * The leader/SLOTS must not be a sampling event for 38757b2c05a1SKan Liang * metric use; hardware requires it starts at 0 when used 38767b2c05a1SKan Liang * in conjunction with MSR_PERF_METRICS. 38777b2c05a1SKan Liang */ 38787b2c05a1SKan Liang if (is_sampling_event(leader)) 38797b2c05a1SKan Liang return -EINVAL; 38807b2c05a1SKan Liang 38817b2c05a1SKan Liang event->event_caps |= PERF_EV_CAP_SIBLING; 38827b2c05a1SKan Liang /* 38837b2c05a1SKan Liang * Only once we have a METRICs sibling do we 38847b2c05a1SKan Liang * need TopDown magic. 38857b2c05a1SKan Liang */ 38867b2c05a1SKan Liang leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 38877b2c05a1SKan Liang event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 38887b2c05a1SKan Liang } 38897b2c05a1SKan Liang } 38907b2c05a1SKan Liang 389161b985e3SKan Liang /* 389261b985e3SKan Liang * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 389361b985e3SKan Liang * doesn't function quite right. As a work-around it needs to always be 389461b985e3SKan Liang * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 389561b985e3SKan Liang * The actual count of this second event is irrelevant it just needs 389661b985e3SKan Liang * to be active to make the first event function correctly. 389761b985e3SKan Liang * 389861b985e3SKan Liang * In a group, the auxiliary event must be in front of the load latency 389961b985e3SKan Liang * event. The rule is to simplify the implementation of the check. 390061b985e3SKan Liang * That's because perf cannot have a complete group at the moment. 390161b985e3SKan Liang */ 3902f83d2f91SKan Liang if (require_mem_loads_aux_event(event) && 390361b985e3SKan Liang (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 390461b985e3SKan Liang is_mem_loads_event(event)) { 390561b985e3SKan Liang struct perf_event *leader = event->group_leader; 390661b985e3SKan Liang struct perf_event *sibling = NULL; 390761b985e3SKan Liang 390861b985e3SKan Liang if (!is_mem_loads_aux_event(leader)) { 390961b985e3SKan Liang for_each_sibling_event(sibling, leader) { 391061b985e3SKan Liang if (is_mem_loads_aux_event(sibling)) 391161b985e3SKan Liang break; 391261b985e3SKan Liang } 391361b985e3SKan Liang if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 391461b985e3SKan Liang return -ENODATA; 391561b985e3SKan Liang } 391661b985e3SKan Liang } 391761b985e3SKan Liang 3918e1069839SBorislav Petkov if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3919e1069839SBorislav Petkov return 0; 3920e1069839SBorislav Petkov 3921e1069839SBorislav Petkov if (x86_pmu.version < 3) 3922e1069839SBorislav Petkov return -EINVAL; 3923e1069839SBorislav Petkov 3924da97e184SJoel Fernandes (Google) ret = perf_allow_cpu(&event->attr); 3925da97e184SJoel Fernandes (Google) if (ret) 3926da97e184SJoel Fernandes (Google) return ret; 3927e1069839SBorislav Petkov 3928e1069839SBorislav Petkov event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3929e1069839SBorislav Petkov 3930e1069839SBorislav Petkov return 0; 3931e1069839SBorislav Petkov } 3932e1069839SBorislav Petkov 3933e1069839SBorislav Petkov static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3934e1069839SBorislav Petkov { 3935e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3936e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3937fc4b8fcaSKan Liang u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 3938e1069839SBorislav Petkov 3939e1069839SBorislav Petkov arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3940fc4b8fcaSKan Liang arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3941fc4b8fcaSKan Liang arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask; 39429b545c04SAndi Kleen if (x86_pmu.flags & PMU_FL_PEBS_ALL) 39439b545c04SAndi Kleen arr[0].guest &= ~cpuc->pebs_enabled; 39449b545c04SAndi Kleen else 39459b545c04SAndi Kleen arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 39469b545c04SAndi Kleen *nr = 1; 39479b545c04SAndi Kleen 39489b545c04SAndi Kleen if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3949e1069839SBorislav Petkov /* 39509b545c04SAndi Kleen * If PMU counter has PEBS enabled it is not enough to 39519b545c04SAndi Kleen * disable counter on a guest entry since PEBS memory 39529b545c04SAndi Kleen * write can overshoot guest entry and corrupt guest 39539b545c04SAndi Kleen * memory. Disabling PEBS solves the problem. 39549b545c04SAndi Kleen * 39559b545c04SAndi Kleen * Don't do this if the CPU already enforces it. 3956e1069839SBorislav Petkov */ 3957e1069839SBorislav Petkov arr[1].msr = MSR_IA32_PEBS_ENABLE; 3958e1069839SBorislav Petkov arr[1].host = cpuc->pebs_enabled; 3959e1069839SBorislav Petkov arr[1].guest = 0; 3960e1069839SBorislav Petkov *nr = 2; 39619b545c04SAndi Kleen } 39629b545c04SAndi Kleen 3963e1069839SBorislav Petkov return arr; 3964e1069839SBorislav Petkov } 3965e1069839SBorislav Petkov 3966e1069839SBorislav Petkov static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3967e1069839SBorislav Petkov { 3968e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3969e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3970e1069839SBorislav Petkov int idx; 3971e1069839SBorislav Petkov 3972e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3973e1069839SBorislav Petkov struct perf_event *event = cpuc->events[idx]; 3974e1069839SBorislav Petkov 3975e1069839SBorislav Petkov arr[idx].msr = x86_pmu_config_addr(idx); 3976e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 0; 3977e1069839SBorislav Petkov 3978e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) 3979e1069839SBorislav Petkov continue; 3980e1069839SBorislav Petkov 3981e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 3982e1069839SBorislav Petkov event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3983e1069839SBorislav Petkov 3984e1069839SBorislav Petkov if (event->attr.exclude_host) 3985e1069839SBorislav Petkov arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3986e1069839SBorislav Petkov else if (event->attr.exclude_guest) 3987e1069839SBorislav Petkov arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3988e1069839SBorislav Petkov } 3989e1069839SBorislav Petkov 3990e1069839SBorislav Petkov *nr = x86_pmu.num_counters; 3991e1069839SBorislav Petkov return arr; 3992e1069839SBorislav Petkov } 3993e1069839SBorislav Petkov 3994e1069839SBorislav Petkov static void core_pmu_enable_event(struct perf_event *event) 3995e1069839SBorislav Petkov { 3996e1069839SBorislav Petkov if (!event->attr.exclude_host) 3997e1069839SBorislav Petkov x86_pmu_enable_event(event); 3998e1069839SBorislav Petkov } 3999e1069839SBorislav Petkov 4000e1069839SBorislav Petkov static void core_pmu_enable_all(int added) 4001e1069839SBorislav Petkov { 4002e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4003e1069839SBorislav Petkov int idx; 4004e1069839SBorislav Petkov 4005e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 4006e1069839SBorislav Petkov struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4007e1069839SBorislav Petkov 4008e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask) || 4009e1069839SBorislav Petkov cpuc->events[idx]->attr.exclude_host) 4010e1069839SBorislav Petkov continue; 4011e1069839SBorislav Petkov 4012e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4013e1069839SBorislav Petkov } 4014e1069839SBorislav Petkov } 4015e1069839SBorislav Petkov 4016e1069839SBorislav Petkov static int hsw_hw_config(struct perf_event *event) 4017e1069839SBorislav Petkov { 4018e1069839SBorislav Petkov int ret = intel_pmu_hw_config(event); 4019e1069839SBorislav Petkov 4020e1069839SBorislav Petkov if (ret) 4021e1069839SBorislav Petkov return ret; 4022e1069839SBorislav Petkov if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4023e1069839SBorislav Petkov return 0; 4024e1069839SBorislav Petkov event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4025e1069839SBorislav Petkov 4026e1069839SBorislav Petkov /* 4027e1069839SBorislav Petkov * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4028e1069839SBorislav Petkov * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4029e1069839SBorislav Petkov * this combination. 4030e1069839SBorislav Petkov */ 4031e1069839SBorislav Petkov if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4032e1069839SBorislav Petkov ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4033e1069839SBorislav Petkov event->attr.precise_ip > 0)) 4034e1069839SBorislav Petkov return -EOPNOTSUPP; 4035e1069839SBorislav Petkov 4036e1069839SBorislav Petkov if (event_is_checkpointed(event)) { 4037e1069839SBorislav Petkov /* 4038e1069839SBorislav Petkov * Sampling of checkpointed events can cause situations where 4039e1069839SBorislav Petkov * the CPU constantly aborts because of a overflow, which is 4040e1069839SBorislav Petkov * then checkpointed back and ignored. Forbid checkpointing 4041e1069839SBorislav Petkov * for sampling. 4042e1069839SBorislav Petkov * 4043e1069839SBorislav Petkov * But still allow a long sampling period, so that perf stat 4044e1069839SBorislav Petkov * from KVM works. 4045e1069839SBorislav Petkov */ 4046e1069839SBorislav Petkov if (event->attr.sample_period > 0 && 4047e1069839SBorislav Petkov event->attr.sample_period < 0x7fffffff) 4048e1069839SBorislav Petkov return -EOPNOTSUPP; 4049e1069839SBorislav Petkov } 4050e1069839SBorislav Petkov return 0; 4051e1069839SBorislav Petkov } 4052e1069839SBorislav Petkov 4053dd0b06b5SKan Liang static struct event_constraint counter0_constraint = 4054dd0b06b5SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4055dd0b06b5SKan Liang 4056e1069839SBorislav Petkov static struct event_constraint counter2_constraint = 4057e1069839SBorislav Petkov EVENT_CONSTRAINT(0, 0x4, 0); 4058e1069839SBorislav Petkov 405960176089SKan Liang static struct event_constraint fixed0_constraint = 406060176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0); 406160176089SKan Liang 40626daeb873SKan Liang static struct event_constraint fixed0_counter0_constraint = 40636daeb873SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 40646daeb873SKan Liang 4065e1069839SBorislav Petkov static struct event_constraint * 4066e1069839SBorislav Petkov hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4067e1069839SBorislav Petkov struct perf_event *event) 4068e1069839SBorislav Petkov { 4069e1069839SBorislav Petkov struct event_constraint *c; 4070e1069839SBorislav Petkov 4071e1069839SBorislav Petkov c = intel_get_event_constraints(cpuc, idx, event); 4072e1069839SBorislav Petkov 4073e1069839SBorislav Petkov /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4074e1069839SBorislav Petkov if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4075e1069839SBorislav Petkov if (c->idxmsk64 & (1U << 2)) 4076e1069839SBorislav Petkov return &counter2_constraint; 4077e1069839SBorislav Petkov return &emptyconstraint; 4078e1069839SBorislav Petkov } 4079e1069839SBorislav Petkov 4080e1069839SBorislav Petkov return c; 4081e1069839SBorislav Petkov } 4082e1069839SBorislav Petkov 4083dd0b06b5SKan Liang static struct event_constraint * 408460176089SKan Liang icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 408560176089SKan Liang struct perf_event *event) 408660176089SKan Liang { 408760176089SKan Liang /* 408860176089SKan Liang * Fixed counter 0 has less skid. 408960176089SKan Liang * Force instruction:ppp in Fixed counter 0 409060176089SKan Liang */ 409160176089SKan Liang if ((event->attr.precise_ip == 3) && 409260176089SKan Liang constraint_match(&fixed0_constraint, event->hw.config)) 409360176089SKan Liang return &fixed0_constraint; 409460176089SKan Liang 409560176089SKan Liang return hsw_get_event_constraints(cpuc, idx, event); 409660176089SKan Liang } 409760176089SKan Liang 409860176089SKan Liang static struct event_constraint * 409961b985e3SKan Liang spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 410061b985e3SKan Liang struct perf_event *event) 410161b985e3SKan Liang { 410261b985e3SKan Liang struct event_constraint *c; 410361b985e3SKan Liang 410461b985e3SKan Liang c = icl_get_event_constraints(cpuc, idx, event); 410561b985e3SKan Liang 410661b985e3SKan Liang /* 410761b985e3SKan Liang * The :ppp indicates the Precise Distribution (PDist) facility, which 410861b985e3SKan Liang * is only supported on the GP counter 0. If a :ppp event which is not 410961b985e3SKan Liang * available on the GP counter 0, error out. 41101d5c7880SKan Liang * Exception: Instruction PDIR is only available on the fixed counter 0. 411161b985e3SKan Liang */ 41121d5c7880SKan Liang if ((event->attr.precise_ip == 3) && 41131d5c7880SKan Liang !constraint_match(&fixed0_constraint, event->hw.config)) { 411461b985e3SKan Liang if (c->idxmsk64 & BIT_ULL(0)) 411561b985e3SKan Liang return &counter0_constraint; 411661b985e3SKan Liang 411761b985e3SKan Liang return &emptyconstraint; 411861b985e3SKan Liang } 411961b985e3SKan Liang 412061b985e3SKan Liang return c; 412161b985e3SKan Liang } 412261b985e3SKan Liang 412361b985e3SKan Liang static struct event_constraint * 4124dd0b06b5SKan Liang glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4125dd0b06b5SKan Liang struct perf_event *event) 4126dd0b06b5SKan Liang { 4127dd0b06b5SKan Liang struct event_constraint *c; 4128dd0b06b5SKan Liang 4129dd0b06b5SKan Liang /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4130dd0b06b5SKan Liang if (event->attr.precise_ip == 3) 4131dd0b06b5SKan Liang return &counter0_constraint; 4132dd0b06b5SKan Liang 4133dd0b06b5SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 4134dd0b06b5SKan Liang 4135dd0b06b5SKan Liang return c; 4136dd0b06b5SKan Liang } 4137dd0b06b5SKan Liang 41386daeb873SKan Liang static struct event_constraint * 41396daeb873SKan Liang tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 41406daeb873SKan Liang struct perf_event *event) 41416daeb873SKan Liang { 41426daeb873SKan Liang struct event_constraint *c; 41436daeb873SKan Liang 41446daeb873SKan Liang /* 41456daeb873SKan Liang * :ppp means to do reduced skid PEBS, 41466daeb873SKan Liang * which is available on PMC0 and fixed counter 0. 41476daeb873SKan Liang */ 41486daeb873SKan Liang if (event->attr.precise_ip == 3) { 41496daeb873SKan Liang /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 41506daeb873SKan Liang if (constraint_match(&fixed0_constraint, event->hw.config)) 41516daeb873SKan Liang return &fixed0_counter0_constraint; 41526daeb873SKan Liang 41536daeb873SKan Liang return &counter0_constraint; 41546daeb873SKan Liang } 41556daeb873SKan Liang 41566daeb873SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 41576daeb873SKan Liang 41586daeb873SKan Liang return c; 41596daeb873SKan Liang } 41606daeb873SKan Liang 4161400816f6SPeter Zijlstra (Intel) static bool allow_tsx_force_abort = true; 4162400816f6SPeter Zijlstra (Intel) 4163400816f6SPeter Zijlstra (Intel) static struct event_constraint * 4164400816f6SPeter Zijlstra (Intel) tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4165400816f6SPeter Zijlstra (Intel) struct perf_event *event) 4166400816f6SPeter Zijlstra (Intel) { 4167400816f6SPeter Zijlstra (Intel) struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4168400816f6SPeter Zijlstra (Intel) 4169400816f6SPeter Zijlstra (Intel) /* 4170400816f6SPeter Zijlstra (Intel) * Without TFA we must not use PMC3. 4171400816f6SPeter Zijlstra (Intel) */ 417221d65555SPeter Zijlstra if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4173400816f6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 4174400816f6SPeter Zijlstra (Intel) c->idxmsk64 &= ~(1ULL << 3); 4175400816f6SPeter Zijlstra (Intel) c->weight--; 4176400816f6SPeter Zijlstra (Intel) } 4177400816f6SPeter Zijlstra (Intel) 4178400816f6SPeter Zijlstra (Intel) return c; 4179400816f6SPeter Zijlstra (Intel) } 4180400816f6SPeter Zijlstra (Intel) 4181f83d2f91SKan Liang static struct event_constraint * 4182f83d2f91SKan Liang adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4183f83d2f91SKan Liang struct perf_event *event) 4184f83d2f91SKan Liang { 4185f83d2f91SKan Liang struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4186f83d2f91SKan Liang 4187f83d2f91SKan Liang if (pmu->cpu_type == hybrid_big) 4188f83d2f91SKan Liang return spr_get_event_constraints(cpuc, idx, event); 4189f83d2f91SKan Liang else if (pmu->cpu_type == hybrid_small) 4190f83d2f91SKan Liang return tnt_get_event_constraints(cpuc, idx, event); 4191f83d2f91SKan Liang 4192f83d2f91SKan Liang WARN_ON(1); 4193f83d2f91SKan Liang return &emptyconstraint; 4194f83d2f91SKan Liang } 4195f83d2f91SKan Liang 4196f83d2f91SKan Liang static int adl_hw_config(struct perf_event *event) 4197f83d2f91SKan Liang { 4198f83d2f91SKan Liang struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4199f83d2f91SKan Liang 4200f83d2f91SKan Liang if (pmu->cpu_type == hybrid_big) 4201f83d2f91SKan Liang return hsw_hw_config(event); 4202f83d2f91SKan Liang else if (pmu->cpu_type == hybrid_small) 4203f83d2f91SKan Liang return intel_pmu_hw_config(event); 4204f83d2f91SKan Liang 4205f83d2f91SKan Liang WARN_ON(1); 4206f83d2f91SKan Liang return -EOPNOTSUPP; 4207f83d2f91SKan Liang } 4208f83d2f91SKan Liang 4209f83d2f91SKan Liang static u8 adl_get_hybrid_cpu_type(void) 4210f83d2f91SKan Liang { 4211f83d2f91SKan Liang return hybrid_big; 4212f83d2f91SKan Liang } 4213f83d2f91SKan Liang 4214e1069839SBorislav Petkov /* 4215e1069839SBorislav Petkov * Broadwell: 4216e1069839SBorislav Petkov * 4217e1069839SBorislav Petkov * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4218e1069839SBorislav Petkov * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4219e1069839SBorislav Petkov * the two to enforce a minimum period of 128 (the smallest value that has bits 4220e1069839SBorislav Petkov * 0-5 cleared and >= 100). 4221e1069839SBorislav Petkov * 4222e1069839SBorislav Petkov * Because of how the code in x86_perf_event_set_period() works, the truncation 4223e1069839SBorislav Petkov * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4224e1069839SBorislav Petkov * to make up for the 'lost' events due to carrying the 'error' in period_left. 4225e1069839SBorislav Petkov * 4226e1069839SBorislav Petkov * Therefore the effective (average) period matches the requested period, 4227e1069839SBorislav Petkov * despite coarser hardware granularity. 4228e1069839SBorislav Petkov */ 4229f605cfcaSKan Liang static u64 bdw_limit_period(struct perf_event *event, u64 left) 4230e1069839SBorislav Petkov { 4231e1069839SBorislav Petkov if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4232e1069839SBorislav Petkov X86_CONFIG(.event=0xc0, .umask=0x01)) { 4233e1069839SBorislav Petkov if (left < 128) 4234e1069839SBorislav Petkov left = 128; 4235e5ea9b54SDan Carpenter left &= ~0x3fULL; 4236e1069839SBorislav Petkov } 4237e1069839SBorislav Petkov return left; 4238e1069839SBorislav Petkov } 4239e1069839SBorislav Petkov 424044d3bbb6SJosh Hunt static u64 nhm_limit_period(struct perf_event *event, u64 left) 424144d3bbb6SJosh Hunt { 424244d3bbb6SJosh Hunt return max(left, 32ULL); 424344d3bbb6SJosh Hunt } 424444d3bbb6SJosh Hunt 424561b985e3SKan Liang static u64 spr_limit_period(struct perf_event *event, u64 left) 424661b985e3SKan Liang { 424761b985e3SKan Liang if (event->attr.precise_ip == 3) 424861b985e3SKan Liang return max(left, 128ULL); 424961b985e3SKan Liang 425061b985e3SKan Liang return left; 425161b985e3SKan Liang } 425261b985e3SKan Liang 4253e1069839SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 4254e1069839SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 4255e1069839SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 4256e1069839SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 4257e1069839SBorislav Petkov PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4258e1069839SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 4259e1069839SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4260e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx, "config:32"); 4261e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4262e1069839SBorislav Petkov 4263e1069839SBorislav Petkov static struct attribute *intel_arch_formats_attr[] = { 4264e1069839SBorislav Petkov &format_attr_event.attr, 4265e1069839SBorislav Petkov &format_attr_umask.attr, 4266e1069839SBorislav Petkov &format_attr_edge.attr, 4267e1069839SBorislav Petkov &format_attr_pc.attr, 4268e1069839SBorislav Petkov &format_attr_inv.attr, 4269e1069839SBorislav Petkov &format_attr_cmask.attr, 4270e1069839SBorislav Petkov NULL, 4271e1069839SBorislav Petkov }; 4272e1069839SBorislav Petkov 4273e1069839SBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config) 4274e1069839SBorislav Petkov { 4275e1069839SBorislav Petkov u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4276e1069839SBorislav Petkov 4277e1069839SBorislav Petkov return x86_event_sysfs_show(page, config, event); 4278e1069839SBorislav Petkov } 4279e1069839SBorislav Petkov 4280d01b1f96SPeter Zijlstra (Intel) static struct intel_shared_regs *allocate_shared_regs(int cpu) 4281e1069839SBorislav Petkov { 4282e1069839SBorislav Petkov struct intel_shared_regs *regs; 4283e1069839SBorislav Petkov int i; 4284e1069839SBorislav Petkov 4285e1069839SBorislav Petkov regs = kzalloc_node(sizeof(struct intel_shared_regs), 4286e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 4287e1069839SBorislav Petkov if (regs) { 4288e1069839SBorislav Petkov /* 4289e1069839SBorislav Petkov * initialize the locks to keep lockdep happy 4290e1069839SBorislav Petkov */ 4291e1069839SBorislav Petkov for (i = 0; i < EXTRA_REG_MAX; i++) 4292e1069839SBorislav Petkov raw_spin_lock_init(®s->regs[i].lock); 4293e1069839SBorislav Petkov 4294e1069839SBorislav Petkov regs->core_id = -1; 4295e1069839SBorislav Petkov } 4296e1069839SBorislav Petkov return regs; 4297e1069839SBorislav Petkov } 4298e1069839SBorislav Petkov 4299e1069839SBorislav Petkov static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4300e1069839SBorislav Petkov { 4301e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4302e1069839SBorislav Petkov 4303e1069839SBorislav Petkov c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4304e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 4305e1069839SBorislav Petkov if (c) { 4306e1069839SBorislav Petkov raw_spin_lock_init(&c->lock); 4307e1069839SBorislav Petkov c->core_id = -1; 4308e1069839SBorislav Petkov } 4309e1069839SBorislav Petkov return c; 4310e1069839SBorislav Petkov } 4311e1069839SBorislav Petkov 4312e1069839SBorislav Petkov 4313d01b1f96SPeter Zijlstra (Intel) int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4314d01b1f96SPeter Zijlstra (Intel) { 4315c22497f5SKan Liang cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4316c22497f5SKan Liang 4317183af736SKan Liang if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4318e1069839SBorislav Petkov cpuc->shared_regs = allocate_shared_regs(cpu); 4319e1069839SBorislav Petkov if (!cpuc->shared_regs) 4320e1069839SBorislav Petkov goto err; 4321e1069839SBorislav Petkov } 4322e1069839SBorislav Petkov 4323400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4324e1069839SBorislav Petkov size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4325e1069839SBorislav Petkov 4326d01b1f96SPeter Zijlstra (Intel) cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4327e1069839SBorislav Petkov if (!cpuc->constraint_list) 4328e1069839SBorislav Petkov goto err_shared_regs; 4329400816f6SPeter Zijlstra (Intel) } 4330e1069839SBorislav Petkov 4331400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4332e1069839SBorislav Petkov cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4333e1069839SBorislav Petkov if (!cpuc->excl_cntrs) 4334e1069839SBorislav Petkov goto err_constraint_list; 4335e1069839SBorislav Petkov 4336e1069839SBorislav Petkov cpuc->excl_thread_id = 0; 4337e1069839SBorislav Petkov } 4338e1069839SBorislav Petkov 433995ca792cSThomas Gleixner return 0; 4340e1069839SBorislav Petkov 4341e1069839SBorislav Petkov err_constraint_list: 4342e1069839SBorislav Petkov kfree(cpuc->constraint_list); 4343e1069839SBorislav Petkov cpuc->constraint_list = NULL; 4344e1069839SBorislav Petkov 4345e1069839SBorislav Petkov err_shared_regs: 4346e1069839SBorislav Petkov kfree(cpuc->shared_regs); 4347e1069839SBorislav Petkov cpuc->shared_regs = NULL; 4348e1069839SBorislav Petkov 4349e1069839SBorislav Petkov err: 435095ca792cSThomas Gleixner return -ENOMEM; 4351e1069839SBorislav Petkov } 4352e1069839SBorislav Petkov 4353d01b1f96SPeter Zijlstra (Intel) static int intel_pmu_cpu_prepare(int cpu) 4354d01b1f96SPeter Zijlstra (Intel) { 4355d01b1f96SPeter Zijlstra (Intel) return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4356d01b1f96SPeter Zijlstra (Intel) } 4357d01b1f96SPeter Zijlstra (Intel) 43586089327fSKan Liang static void flip_smm_bit(void *data) 43596089327fSKan Liang { 43606089327fSKan Liang unsigned long set = *(unsigned long *)data; 43616089327fSKan Liang 43626089327fSKan Liang if (set > 0) { 43636089327fSKan Liang msr_set_bit(MSR_IA32_DEBUGCTLMSR, 43646089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 43656089327fSKan Liang } else { 43666089327fSKan Liang msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 43676089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 43686089327fSKan Liang } 43696089327fSKan Liang } 43706089327fSKan Liang 4371d9977c43SKan Liang static bool init_hybrid_pmu(int cpu) 4372d9977c43SKan Liang { 4373d9977c43SKan Liang struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4374d9977c43SKan Liang u8 cpu_type = get_this_hybrid_cpu_type(); 4375d9977c43SKan Liang struct x86_hybrid_pmu *pmu = NULL; 4376d9977c43SKan Liang int i; 4377d9977c43SKan Liang 4378d9977c43SKan Liang if (!cpu_type && x86_pmu.get_hybrid_cpu_type) 4379d9977c43SKan Liang cpu_type = x86_pmu.get_hybrid_cpu_type(); 4380d9977c43SKan Liang 4381d9977c43SKan Liang for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 4382d9977c43SKan Liang if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { 4383d9977c43SKan Liang pmu = &x86_pmu.hybrid_pmu[i]; 4384d9977c43SKan Liang break; 4385d9977c43SKan Liang } 4386d9977c43SKan Liang } 4387d9977c43SKan Liang if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 4388d9977c43SKan Liang cpuc->pmu = NULL; 4389d9977c43SKan Liang return false; 4390d9977c43SKan Liang } 4391d9977c43SKan Liang 4392d9977c43SKan Liang /* Only check and dump the PMU information for the first CPU */ 4393d9977c43SKan Liang if (!cpumask_empty(&pmu->supported_cpus)) 4394d9977c43SKan Liang goto end; 4395d9977c43SKan Liang 4396d9977c43SKan Liang if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) 4397d9977c43SKan Liang return false; 4398d9977c43SKan Liang 4399d9977c43SKan Liang pr_info("%s PMU driver: ", pmu->name); 4400d9977c43SKan Liang 4401d9977c43SKan Liang if (pmu->intel_cap.pebs_output_pt_available) 4402d9977c43SKan Liang pr_cont("PEBS-via-PT "); 4403d9977c43SKan Liang 4404d9977c43SKan Liang pr_cont("\n"); 4405d9977c43SKan Liang 4406d9977c43SKan Liang x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, 4407d9977c43SKan Liang pmu->intel_ctrl); 4408d9977c43SKan Liang 4409d9977c43SKan Liang end: 4410d9977c43SKan Liang cpumask_set_cpu(cpu, &pmu->supported_cpus); 4411d9977c43SKan Liang cpuc->pmu = &pmu->pmu; 4412d9977c43SKan Liang 4413d9977c43SKan Liang x86_pmu_update_cpu_context(&pmu->pmu, cpu); 4414d9977c43SKan Liang 4415d9977c43SKan Liang return true; 4416d9977c43SKan Liang } 4417d9977c43SKan Liang 4418e1069839SBorislav Petkov static void intel_pmu_cpu_starting(int cpu) 4419e1069839SBorislav Petkov { 4420e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4421e1069839SBorislav Petkov int core_id = topology_core_id(cpu); 4422e1069839SBorislav Petkov int i; 4423e1069839SBorislav Petkov 4424d9977c43SKan Liang if (is_hybrid() && !init_hybrid_pmu(cpu)) 4425d9977c43SKan Liang return; 4426d9977c43SKan Liang 4427e1069839SBorislav Petkov init_debug_store_on_cpu(cpu); 4428e1069839SBorislav Petkov /* 4429e1069839SBorislav Petkov * Deal with CPUs that don't clear their LBRs on power-up. 4430e1069839SBorislav Petkov */ 4431e1069839SBorislav Petkov intel_pmu_lbr_reset(); 4432e1069839SBorislav Petkov 4433e1069839SBorislav Petkov cpuc->lbr_sel = NULL; 4434e1069839SBorislav Petkov 4435d7262457SPeter Zijlstra if (x86_pmu.flags & PMU_FL_TFA) { 4436d7262457SPeter Zijlstra WARN_ON_ONCE(cpuc->tfa_shadow); 4437d7262457SPeter Zijlstra cpuc->tfa_shadow = ~0ULL; 4438d7262457SPeter Zijlstra intel_set_tfa(cpuc, false); 4439d7262457SPeter Zijlstra } 4440d7262457SPeter Zijlstra 44414e949e9bSKan Liang if (x86_pmu.version > 1) 44426089327fSKan Liang flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 44436089327fSKan Liang 4444d0946a88SKan Liang /* 4445d0946a88SKan Liang * Disable perf metrics if any added CPU doesn't support it. 4446d0946a88SKan Liang * 4447d0946a88SKan Liang * Turn off the check for a hybrid architecture, because the 4448d0946a88SKan Liang * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 4449d0946a88SKan Liang * the architecture features. The perf metrics is a model-specific 4450d0946a88SKan Liang * feature for now. The corresponding bit should always be 0 on 4451d0946a88SKan Liang * a hybrid platform, e.g., Alder Lake. 4452d0946a88SKan Liang */ 4453d0946a88SKan Liang if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 445480a5ce11SKan Liang union perf_capabilities perf_cap; 445580a5ce11SKan Liang 445680a5ce11SKan Liang rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 445780a5ce11SKan Liang if (!perf_cap.perf_metrics) { 445880a5ce11SKan Liang x86_pmu.intel_cap.perf_metrics = 0; 445980a5ce11SKan Liang x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 446080a5ce11SKan Liang } 446180a5ce11SKan Liang } 446280a5ce11SKan Liang 4463e1069839SBorislav Petkov if (!cpuc->shared_regs) 4464e1069839SBorislav Petkov return; 4465e1069839SBorislav Petkov 4466e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4467e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4468e1069839SBorislav Petkov struct intel_shared_regs *pc; 4469e1069839SBorislav Petkov 4470e1069839SBorislav Petkov pc = per_cpu(cpu_hw_events, i).shared_regs; 4471e1069839SBorislav Petkov if (pc && pc->core_id == core_id) { 4472e1069839SBorislav Petkov cpuc->kfree_on_online[0] = cpuc->shared_regs; 4473e1069839SBorislav Petkov cpuc->shared_regs = pc; 4474e1069839SBorislav Petkov break; 4475e1069839SBorislav Petkov } 4476e1069839SBorislav Petkov } 4477e1069839SBorislav Petkov cpuc->shared_regs->core_id = core_id; 4478e1069839SBorislav Petkov cpuc->shared_regs->refcnt++; 4479e1069839SBorislav Petkov } 4480e1069839SBorislav Petkov 4481e1069839SBorislav Petkov if (x86_pmu.lbr_sel_map) 4482e1069839SBorislav Petkov cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4483e1069839SBorislav Petkov 4484e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4485e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 44864e71de79SZhou Chengming struct cpu_hw_events *sibling; 4487e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4488e1069839SBorislav Petkov 44894e71de79SZhou Chengming sibling = &per_cpu(cpu_hw_events, i); 44904e71de79SZhou Chengming c = sibling->excl_cntrs; 4491e1069839SBorislav Petkov if (c && c->core_id == core_id) { 4492e1069839SBorislav Petkov cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4493e1069839SBorislav Petkov cpuc->excl_cntrs = c; 44944e71de79SZhou Chengming if (!sibling->excl_thread_id) 4495e1069839SBorislav Petkov cpuc->excl_thread_id = 1; 4496e1069839SBorislav Petkov break; 4497e1069839SBorislav Petkov } 4498e1069839SBorislav Petkov } 4499e1069839SBorislav Petkov cpuc->excl_cntrs->core_id = core_id; 4500e1069839SBorislav Petkov cpuc->excl_cntrs->refcnt++; 4501e1069839SBorislav Petkov } 4502e1069839SBorislav Petkov } 4503e1069839SBorislav Petkov 4504d01b1f96SPeter Zijlstra (Intel) static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4505e1069839SBorislav Petkov { 4506e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4507e1069839SBorislav Petkov 4508e1069839SBorislav Petkov c = cpuc->excl_cntrs; 4509e1069839SBorislav Petkov if (c) { 4510e1069839SBorislav Petkov if (c->core_id == -1 || --c->refcnt == 0) 4511e1069839SBorislav Petkov kfree(c); 4512e1069839SBorislav Petkov cpuc->excl_cntrs = NULL; 4513400816f6SPeter Zijlstra (Intel) } 4514400816f6SPeter Zijlstra (Intel) 4515e1069839SBorislav Petkov kfree(cpuc->constraint_list); 4516e1069839SBorislav Petkov cpuc->constraint_list = NULL; 4517e1069839SBorislav Petkov } 4518e1069839SBorislav Petkov 4519e1069839SBorislav Petkov static void intel_pmu_cpu_dying(int cpu) 4520e1069839SBorislav Petkov { 4521602cae04SPeter Zijlstra fini_debug_store_on_cpu(cpu); 4522602cae04SPeter Zijlstra } 4523602cae04SPeter Zijlstra 4524d01b1f96SPeter Zijlstra (Intel) void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4525602cae04SPeter Zijlstra { 4526e1069839SBorislav Petkov struct intel_shared_regs *pc; 4527e1069839SBorislav Petkov 4528e1069839SBorislav Petkov pc = cpuc->shared_regs; 4529e1069839SBorislav Petkov if (pc) { 4530e1069839SBorislav Petkov if (pc->core_id == -1 || --pc->refcnt == 0) 4531e1069839SBorislav Petkov kfree(pc); 4532e1069839SBorislav Petkov cpuc->shared_regs = NULL; 4533e1069839SBorislav Petkov } 4534e1069839SBorislav Petkov 4535d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(cpuc); 4536d01b1f96SPeter Zijlstra (Intel) } 4537d01b1f96SPeter Zijlstra (Intel) 4538d01b1f96SPeter Zijlstra (Intel) static void intel_pmu_cpu_dead(int cpu) 4539d01b1f96SPeter Zijlstra (Intel) { 4540d9977c43SKan Liang struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4541d9977c43SKan Liang 4542d9977c43SKan Liang intel_cpuc_finish(cpuc); 4543d9977c43SKan Liang 4544d9977c43SKan Liang if (is_hybrid() && cpuc->pmu) 4545d9977c43SKan Liang cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 4546e1069839SBorislav Petkov } 4547e1069839SBorislav Petkov 4548e1069839SBorislav Petkov static void intel_pmu_sched_task(struct perf_event_context *ctx, 4549e1069839SBorislav Petkov bool sched_in) 4550e1069839SBorislav Petkov { 4551e1069839SBorislav Petkov intel_pmu_pebs_sched_task(ctx, sched_in); 4552e1069839SBorislav Petkov intel_pmu_lbr_sched_task(ctx, sched_in); 4553e1069839SBorislav Petkov } 4554e1069839SBorislav Petkov 4555c2b98a86SAlexey Budankov static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4556c2b98a86SAlexey Budankov struct perf_event_context *next) 4557c2b98a86SAlexey Budankov { 4558c2b98a86SAlexey Budankov intel_pmu_lbr_swap_task_ctx(prev, next); 4559c2b98a86SAlexey Budankov } 4560c2b98a86SAlexey Budankov 456181ec3f3cSJiri Olsa static int intel_pmu_check_period(struct perf_event *event, u64 value) 456281ec3f3cSJiri Olsa { 456381ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 456481ec3f3cSJiri Olsa } 456581ec3f3cSJiri Olsa 45668b8ff8ccSAdrian Hunter static void intel_aux_output_init(void) 45678b8ff8ccSAdrian Hunter { 45688b8ff8ccSAdrian Hunter /* Refer also intel_pmu_aux_output_match() */ 45698b8ff8ccSAdrian Hunter if (x86_pmu.intel_cap.pebs_output_pt_available) 45708b8ff8ccSAdrian Hunter x86_pmu.assign = intel_pmu_assign_event; 45718b8ff8ccSAdrian Hunter } 45728b8ff8ccSAdrian Hunter 457342880f72SAlexander Shishkin static int intel_pmu_aux_output_match(struct perf_event *event) 457442880f72SAlexander Shishkin { 45758b8ff8ccSAdrian Hunter /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 457642880f72SAlexander Shishkin if (!x86_pmu.intel_cap.pebs_output_pt_available) 457742880f72SAlexander Shishkin return 0; 457842880f72SAlexander Shishkin 457942880f72SAlexander Shishkin return is_intel_pt_event(event); 458042880f72SAlexander Shishkin } 458142880f72SAlexander Shishkin 4582f83d2f91SKan Liang static int intel_pmu_filter_match(struct perf_event *event) 4583f83d2f91SKan Liang { 4584f83d2f91SKan Liang struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 4585f83d2f91SKan Liang unsigned int cpu = smp_processor_id(); 4586f83d2f91SKan Liang 4587f83d2f91SKan Liang return cpumask_test_cpu(cpu, &pmu->supported_cpus); 4588f83d2f91SKan Liang } 4589f83d2f91SKan Liang 4590e1069839SBorislav Petkov PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4591e1069839SBorislav Petkov 4592e1069839SBorislav Petkov PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4593e1069839SBorislav Petkov 4594e1069839SBorislav Petkov PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4595e1069839SBorislav Petkov 4596e1069839SBorislav Petkov static struct attribute *intel_arch3_formats_attr[] = { 4597e1069839SBorislav Petkov &format_attr_event.attr, 4598e1069839SBorislav Petkov &format_attr_umask.attr, 4599e1069839SBorislav Petkov &format_attr_edge.attr, 4600e1069839SBorislav Petkov &format_attr_pc.attr, 4601e1069839SBorislav Petkov &format_attr_any.attr, 4602e1069839SBorislav Petkov &format_attr_inv.attr, 4603e1069839SBorislav Petkov &format_attr_cmask.attr, 4604a5df70c3SAndi Kleen NULL, 4605a5df70c3SAndi Kleen }; 4606a5df70c3SAndi Kleen 4607a5df70c3SAndi Kleen static struct attribute *hsw_format_attr[] = { 4608e1069839SBorislav Petkov &format_attr_in_tx.attr, 4609e1069839SBorislav Petkov &format_attr_in_tx_cp.attr, 4610a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4611a5df70c3SAndi Kleen &format_attr_ldlat.attr, 4612a5df70c3SAndi Kleen NULL 4613a5df70c3SAndi Kleen }; 4614e1069839SBorislav Petkov 4615a5df70c3SAndi Kleen static struct attribute *nhm_format_attr[] = { 4616a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4617a5df70c3SAndi Kleen &format_attr_ldlat.attr, 4618a5df70c3SAndi Kleen NULL 4619a5df70c3SAndi Kleen }; 4620a5df70c3SAndi Kleen 4621a5df70c3SAndi Kleen static struct attribute *slm_format_attr[] = { 4622a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4623a5df70c3SAndi Kleen NULL 4624e1069839SBorislav Petkov }; 4625e1069839SBorislav Petkov 4626e1069839SBorislav Petkov static struct attribute *skl_format_attr[] = { 4627e1069839SBorislav Petkov &format_attr_frontend.attr, 4628e1069839SBorislav Petkov NULL, 4629e1069839SBorislav Petkov }; 4630e1069839SBorislav Petkov 4631e1069839SBorislav Petkov static __initconst const struct x86_pmu core_pmu = { 4632e1069839SBorislav Petkov .name = "core", 4633e1069839SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 4634e1069839SBorislav Petkov .disable_all = x86_pmu_disable_all, 4635e1069839SBorislav Petkov .enable_all = core_pmu_enable_all, 4636e1069839SBorislav Petkov .enable = core_pmu_enable_event, 4637e1069839SBorislav Petkov .disable = x86_pmu_disable_event, 4638ed6101bbSJiri Olsa .hw_config = core_pmu_hw_config, 4639e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 4640e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4641e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4642e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 4643e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4644e1069839SBorislav Petkov .apic = 1, 4645174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 4646e1069839SBorislav Petkov 4647e1069839SBorislav Petkov /* 4648e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32-bit width, 4649e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 4650e1069839SBorislav Petkov * the generic event period: 4651e1069839SBorislav Petkov */ 4652e1069839SBorislav Petkov .max_period = (1ULL<<31) - 1, 4653e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 4654e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 4655e1069839SBorislav Petkov .event_constraints = intel_core_event_constraints, 4656e1069839SBorislav Petkov .guest_get_msrs = core_guest_get_msrs, 4657e1069839SBorislav Petkov .format_attrs = intel_arch_formats_attr, 4658e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 4659e1069839SBorislav Petkov 4660e1069839SBorislav Petkov /* 4661e1069839SBorislav Petkov * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4662e1069839SBorislav Petkov * together with PMU version 1 and thus be using core_pmu with 4663e1069839SBorislav Petkov * shared_regs. We need following callbacks here to allocate 4664e1069839SBorislav Petkov * it properly. 4665e1069839SBorislav Petkov */ 4666e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 4667e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 4668e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 4669602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 467081ec3f3cSJiri Olsa 467181ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 46729f354a72SKan Liang 46739f354a72SKan Liang .lbr_reset = intel_pmu_lbr_reset_64, 4674c301b1d8SKan Liang .lbr_read = intel_pmu_lbr_read_64, 4675799571bfSKan Liang .lbr_save = intel_pmu_lbr_save, 4676799571bfSKan Liang .lbr_restore = intel_pmu_lbr_restore, 4677e1069839SBorislav Petkov }; 4678e1069839SBorislav Petkov 4679e1069839SBorislav Petkov static __initconst const struct x86_pmu intel_pmu = { 4680e1069839SBorislav Petkov .name = "Intel", 4681e1069839SBorislav Petkov .handle_irq = intel_pmu_handle_irq, 4682e1069839SBorislav Petkov .disable_all = intel_pmu_disable_all, 4683e1069839SBorislav Petkov .enable_all = intel_pmu_enable_all, 4684e1069839SBorislav Petkov .enable = intel_pmu_enable_event, 4685e1069839SBorislav Petkov .disable = intel_pmu_disable_event, 468668f7082fSPeter Zijlstra .add = intel_pmu_add_event, 468768f7082fSPeter Zijlstra .del = intel_pmu_del_event, 4688ceb90d9eSKan Liang .read = intel_pmu_read_event, 4689e1069839SBorislav Petkov .hw_config = intel_pmu_hw_config, 4690e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 4691e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4692e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4693e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 4694e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4695e1069839SBorislav Petkov .apic = 1, 4696174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 4697e1069839SBorislav Petkov /* 4698e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32 bit width, 4699e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 4700e1069839SBorislav Petkov * the generic event period: 4701e1069839SBorislav Petkov */ 4702e1069839SBorislav Petkov .max_period = (1ULL << 31) - 1, 4703e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 4704e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 4705e1069839SBorislav Petkov .pebs_aliases = intel_pebs_aliases_core2, 4706e1069839SBorislav Petkov 4707e1069839SBorislav Petkov .format_attrs = intel_arch3_formats_attr, 4708e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 4709e1069839SBorislav Petkov 4710e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 4711e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 4712e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 4713602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 4714602cae04SPeter Zijlstra 4715e1069839SBorislav Petkov .guest_get_msrs = intel_guest_get_msrs, 4716e1069839SBorislav Petkov .sched_task = intel_pmu_sched_task, 4717c2b98a86SAlexey Budankov .swap_task_ctx = intel_pmu_swap_task_ctx, 471881ec3f3cSJiri Olsa 471981ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 472042880f72SAlexander Shishkin 472142880f72SAlexander Shishkin .aux_output_match = intel_pmu_aux_output_match, 47229f354a72SKan Liang 47239f354a72SKan Liang .lbr_reset = intel_pmu_lbr_reset_64, 4724c301b1d8SKan Liang .lbr_read = intel_pmu_lbr_read_64, 4725799571bfSKan Liang .lbr_save = intel_pmu_lbr_save, 4726799571bfSKan Liang .lbr_restore = intel_pmu_lbr_restore, 4727e1069839SBorislav Petkov }; 4728e1069839SBorislav Petkov 4729e1069839SBorislav Petkov static __init void intel_clovertown_quirk(void) 4730e1069839SBorislav Petkov { 4731e1069839SBorislav Petkov /* 4732e1069839SBorislav Petkov * PEBS is unreliable due to: 4733e1069839SBorislav Petkov * 4734e1069839SBorislav Petkov * AJ67 - PEBS may experience CPL leaks 4735e1069839SBorislav Petkov * AJ68 - PEBS PMI may be delayed by one event 4736e1069839SBorislav Petkov * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4737e1069839SBorislav Petkov * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4738e1069839SBorislav Petkov * 4739e1069839SBorislav Petkov * AJ67 could be worked around by restricting the OS/USR flags. 4740e1069839SBorislav Petkov * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4741e1069839SBorislav Petkov * 4742e1069839SBorislav Petkov * AJ106 could possibly be worked around by not allowing LBR 4743e1069839SBorislav Petkov * usage from PEBS, including the fixup. 4744e1069839SBorislav Petkov * AJ68 could possibly be worked around by always programming 4745e1069839SBorislav Petkov * a pebs_event_reset[0] value and coping with the lost events. 4746e1069839SBorislav Petkov * 4747e1069839SBorislav Petkov * But taken together it might just make sense to not enable PEBS on 4748e1069839SBorislav Petkov * these chips. 4749e1069839SBorislav Petkov */ 4750e1069839SBorislav Petkov pr_warn("PEBS disabled due to CPU errata\n"); 4751e1069839SBorislav Petkov x86_pmu.pebs = 0; 4752e1069839SBorislav Petkov x86_pmu.pebs_constraints = NULL; 4753e1069839SBorislav Petkov } 4754e1069839SBorislav Petkov 47559b545c04SAndi Kleen static const struct x86_cpu_desc isolation_ucodes[] = { 4756c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4757af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 47585e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 47599b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 47609b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4761c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 47625e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 47635ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 47645ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 47655ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 47665ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 47674b2f1e59SJim Mattson INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), 47689b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 47699b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4770b3c3361fSJim Mattson INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), 4771b3c3361fSJim Mattson INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), 4772b3c3361fSJim Mattson INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), 4773af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4774c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4775c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4776af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4777af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4778af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4779af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4780c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4781c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4782c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4783c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 47849b545c04SAndi Kleen {} 47859b545c04SAndi Kleen }; 47869b545c04SAndi Kleen 47879b545c04SAndi Kleen static void intel_check_pebs_isolation(void) 47889b545c04SAndi Kleen { 47899b545c04SAndi Kleen x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 47909b545c04SAndi Kleen } 47919b545c04SAndi Kleen 47929b545c04SAndi Kleen static __init void intel_pebs_isolation_quirk(void) 47939b545c04SAndi Kleen { 47949b545c04SAndi Kleen WARN_ON_ONCE(x86_pmu.check_microcode); 47959b545c04SAndi Kleen x86_pmu.check_microcode = intel_check_pebs_isolation; 47969b545c04SAndi Kleen intel_check_pebs_isolation(); 47979b545c04SAndi Kleen } 47989b545c04SAndi Kleen 4799a96fff8dSKan Liang static const struct x86_cpu_desc pebs_ucodes[] = { 4800a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4801a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4802a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4803a96fff8dSKan Liang {} 4804a96fff8dSKan Liang }; 4805a96fff8dSKan Liang 4806a96fff8dSKan Liang static bool intel_snb_pebs_broken(void) 4807e1069839SBorislav Petkov { 4808a96fff8dSKan Liang return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4809e1069839SBorislav Petkov } 4810e1069839SBorislav Petkov 4811e1069839SBorislav Petkov static void intel_snb_check_microcode(void) 4812e1069839SBorislav Petkov { 4813a96fff8dSKan Liang if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4814e1069839SBorislav Petkov return; 4815e1069839SBorislav Petkov 4816e1069839SBorislav Petkov /* 4817e1069839SBorislav Petkov * Serialized by the microcode lock.. 4818e1069839SBorislav Petkov */ 4819e1069839SBorislav Petkov if (x86_pmu.pebs_broken) { 4820e1069839SBorislav Petkov pr_info("PEBS enabled due to microcode update\n"); 4821e1069839SBorislav Petkov x86_pmu.pebs_broken = 0; 4822e1069839SBorislav Petkov } else { 4823e1069839SBorislav Petkov pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4824e1069839SBorislav Petkov x86_pmu.pebs_broken = 1; 4825e1069839SBorislav Petkov } 4826e1069839SBorislav Petkov } 4827e1069839SBorislav Petkov 482819fc9dddSDavid Carrillo-Cisneros static bool is_lbr_from(unsigned long msr) 482919fc9dddSDavid Carrillo-Cisneros { 483019fc9dddSDavid Carrillo-Cisneros unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 483119fc9dddSDavid Carrillo-Cisneros 483219fc9dddSDavid Carrillo-Cisneros return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 483319fc9dddSDavid Carrillo-Cisneros } 483419fc9dddSDavid Carrillo-Cisneros 4835e1069839SBorislav Petkov /* 4836e1069839SBorislav Petkov * Under certain circumstances, access certain MSR may cause #GP. 4837e1069839SBorislav Petkov * The function tests if the input MSR can be safely accessed. 4838e1069839SBorislav Petkov */ 4839e1069839SBorislav Petkov static bool check_msr(unsigned long msr, u64 mask) 4840e1069839SBorislav Petkov { 4841e1069839SBorislav Petkov u64 val_old, val_new, val_tmp; 4842e1069839SBorislav Petkov 4843e1069839SBorislav Petkov /* 4844d0e1a507SJiri Olsa * Disable the check for real HW, so we don't 4845d9f6e12fSIngo Molnar * mess with potentially enabled registers: 4846d0e1a507SJiri Olsa */ 48475ea3f6fbSZhenzhong Duan if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4848d0e1a507SJiri Olsa return true; 4849d0e1a507SJiri Olsa 4850d0e1a507SJiri Olsa /* 4851e1069839SBorislav Petkov * Read the current value, change it and read it back to see if it 4852e1069839SBorislav Petkov * matches, this is needed to detect certain hardware emulators 4853e1069839SBorislav Petkov * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4854e1069839SBorislav Petkov */ 4855e1069839SBorislav Petkov if (rdmsrl_safe(msr, &val_old)) 4856e1069839SBorislav Petkov return false; 4857e1069839SBorislav Petkov 4858e1069839SBorislav Petkov /* 4859e1069839SBorislav Petkov * Only change the bits which can be updated by wrmsrl. 4860e1069839SBorislav Petkov */ 4861e1069839SBorislav Petkov val_tmp = val_old ^ mask; 486219fc9dddSDavid Carrillo-Cisneros 486319fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 486419fc9dddSDavid Carrillo-Cisneros val_tmp = lbr_from_signext_quirk_wr(val_tmp); 486519fc9dddSDavid Carrillo-Cisneros 4866e1069839SBorislav Petkov if (wrmsrl_safe(msr, val_tmp) || 4867e1069839SBorislav Petkov rdmsrl_safe(msr, &val_new)) 4868e1069839SBorislav Petkov return false; 4869e1069839SBorislav Petkov 487019fc9dddSDavid Carrillo-Cisneros /* 487119fc9dddSDavid Carrillo-Cisneros * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 487219fc9dddSDavid Carrillo-Cisneros * should equal rdmsrl()'s even with the quirk. 487319fc9dddSDavid Carrillo-Cisneros */ 4874e1069839SBorislav Petkov if (val_new != val_tmp) 4875e1069839SBorislav Petkov return false; 4876e1069839SBorislav Petkov 487719fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 487819fc9dddSDavid Carrillo-Cisneros val_old = lbr_from_signext_quirk_wr(val_old); 487919fc9dddSDavid Carrillo-Cisneros 4880e1069839SBorislav Petkov /* Here it's sure that the MSR can be safely accessed. 4881e1069839SBorislav Petkov * Restore the old value and return. 4882e1069839SBorislav Petkov */ 4883e1069839SBorislav Petkov wrmsrl(msr, val_old); 4884e1069839SBorislav Petkov 4885e1069839SBorislav Petkov return true; 4886e1069839SBorislav Petkov } 4887e1069839SBorislav Petkov 4888e1069839SBorislav Petkov static __init void intel_sandybridge_quirk(void) 4889e1069839SBorislav Petkov { 4890e1069839SBorislav Petkov x86_pmu.check_microcode = intel_snb_check_microcode; 48911ba143a5SSebastian Andrzej Siewior cpus_read_lock(); 4892e1069839SBorislav Petkov intel_snb_check_microcode(); 48931ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 4894e1069839SBorislav Petkov } 4895e1069839SBorislav Petkov 4896e1069839SBorislav Petkov static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4897e1069839SBorislav Petkov { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4898e1069839SBorislav Petkov { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4899e1069839SBorislav Petkov { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4900e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4901e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4902e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4903e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4904e1069839SBorislav Petkov }; 4905e1069839SBorislav Petkov 4906e1069839SBorislav Petkov static __init void intel_arch_events_quirk(void) 4907e1069839SBorislav Petkov { 4908e1069839SBorislav Petkov int bit; 4909e1069839SBorislav Petkov 4910d9f6e12fSIngo Molnar /* disable event that reported as not present by cpuid */ 4911e1069839SBorislav Petkov for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4912e1069839SBorislav Petkov intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4913e1069839SBorislav Petkov pr_warn("CPUID marked event: \'%s\' unavailable\n", 4914e1069839SBorislav Petkov intel_arch_events_map[bit].name); 4915e1069839SBorislav Petkov } 4916e1069839SBorislav Petkov } 4917e1069839SBorislav Petkov 4918e1069839SBorislav Petkov static __init void intel_nehalem_quirk(void) 4919e1069839SBorislav Petkov { 4920e1069839SBorislav Petkov union cpuid10_ebx ebx; 4921e1069839SBorislav Petkov 4922e1069839SBorislav Petkov ebx.full = x86_pmu.events_maskl; 4923e1069839SBorislav Petkov if (ebx.split.no_branch_misses_retired) { 4924e1069839SBorislav Petkov /* 4925e1069839SBorislav Petkov * Erratum AAJ80 detected, we work it around by using 4926e1069839SBorislav Petkov * the BR_MISP_EXEC.ANY event. This will over-count 4927e1069839SBorislav Petkov * branch-misses, but it's still much better than the 4928e1069839SBorislav Petkov * architectural event which is often completely bogus: 4929e1069839SBorislav Petkov */ 4930e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4931e1069839SBorislav Petkov ebx.split.no_branch_misses_retired = 0; 4932e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4933e1069839SBorislav Petkov pr_info("CPU erratum AAJ80 worked around\n"); 4934e1069839SBorislav Petkov } 4935e1069839SBorislav Petkov } 4936e1069839SBorislav Petkov 4937e1069839SBorislav Petkov /* 4938e1069839SBorislav Petkov * enable software workaround for errata: 4939e1069839SBorislav Petkov * SNB: BJ122 4940e1069839SBorislav Petkov * IVB: BV98 4941e1069839SBorislav Petkov * HSW: HSD29 4942e1069839SBorislav Petkov * 4943e1069839SBorislav Petkov * Only needed when HT is enabled. However detecting 4944e1069839SBorislav Petkov * if HT is enabled is difficult (model specific). So instead, 4945e1069839SBorislav Petkov * we enable the workaround in the early boot, and verify if 4946e1069839SBorislav Petkov * it is needed in a later initcall phase once we have valid 4947e1069839SBorislav Petkov * topology information to check if HT is actually enabled 4948e1069839SBorislav Petkov */ 4949e1069839SBorislav Petkov static __init void intel_ht_bug(void) 4950e1069839SBorislav Petkov { 4951e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4952e1069839SBorislav Petkov 4953e1069839SBorislav Petkov x86_pmu.start_scheduling = intel_start_scheduling; 4954e1069839SBorislav Petkov x86_pmu.commit_scheduling = intel_commit_scheduling; 4955e1069839SBorislav Petkov x86_pmu.stop_scheduling = intel_stop_scheduling; 4956e1069839SBorislav Petkov } 4957e1069839SBorislav Petkov 4958e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4959e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4960e1069839SBorislav Petkov 4961e1069839SBorislav Petkov /* Haswell special events */ 4962e1069839SBorislav Petkov EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4963e1069839SBorislav Petkov EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4964e1069839SBorislav Petkov EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4965e1069839SBorislav Petkov EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4966e1069839SBorislav Petkov EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4967e1069839SBorislav Petkov EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4968e1069839SBorislav Petkov EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4969e1069839SBorislav Petkov EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4970e1069839SBorislav Petkov EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4971e1069839SBorislav Petkov EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4972e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4973e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4974e1069839SBorislav Petkov 4975e1069839SBorislav Petkov static struct attribute *hsw_events_attrs[] = { 497658ba4d5aSAndi Kleen EVENT_PTR(td_slots_issued), 497758ba4d5aSAndi Kleen EVENT_PTR(td_slots_retired), 497858ba4d5aSAndi Kleen EVENT_PTR(td_fetch_bubbles), 497958ba4d5aSAndi Kleen EVENT_PTR(td_total_slots), 498058ba4d5aSAndi Kleen EVENT_PTR(td_total_slots_scale), 498158ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles), 498258ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 498358ba4d5aSAndi Kleen NULL 498458ba4d5aSAndi Kleen }; 498558ba4d5aSAndi Kleen 4986d4ae5529SJiri Olsa static struct attribute *hsw_mem_events_attrs[] = { 4987d4ae5529SJiri Olsa EVENT_PTR(mem_ld_hsw), 4988d4ae5529SJiri Olsa EVENT_PTR(mem_st_hsw), 4989d4ae5529SJiri Olsa NULL, 4990d4ae5529SJiri Olsa }; 4991d4ae5529SJiri Olsa 499258ba4d5aSAndi Kleen static struct attribute *hsw_tsx_events_attrs[] = { 4993e1069839SBorislav Petkov EVENT_PTR(tx_start), 4994e1069839SBorislav Petkov EVENT_PTR(tx_commit), 4995e1069839SBorislav Petkov EVENT_PTR(tx_abort), 4996e1069839SBorislav Petkov EVENT_PTR(tx_capacity), 4997e1069839SBorislav Petkov EVENT_PTR(tx_conflict), 4998e1069839SBorislav Petkov EVENT_PTR(el_start), 4999e1069839SBorislav Petkov EVENT_PTR(el_commit), 5000e1069839SBorislav Petkov EVENT_PTR(el_abort), 5001e1069839SBorislav Petkov EVENT_PTR(el_capacity), 5002e1069839SBorislav Petkov EVENT_PTR(el_conflict), 5003e1069839SBorislav Petkov EVENT_PTR(cycles_t), 5004e1069839SBorislav Petkov EVENT_PTR(cycles_ct), 5005e1069839SBorislav Petkov NULL 5006e1069839SBorislav Petkov }; 5007e1069839SBorislav Petkov 500860176089SKan Liang EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 500960176089SKan Liang EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 501060176089SKan Liang EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 501160176089SKan Liang EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 501260176089SKan Liang 501360176089SKan Liang static struct attribute *icl_events_attrs[] = { 501460176089SKan Liang EVENT_PTR(mem_ld_hsw), 501560176089SKan Liang EVENT_PTR(mem_st_hsw), 501660176089SKan Liang NULL, 501760176089SKan Liang }; 501860176089SKan Liang 501959a854e2SKan Liang static struct attribute *icl_td_events_attrs[] = { 502059a854e2SKan Liang EVENT_PTR(slots), 502159a854e2SKan Liang EVENT_PTR(td_retiring), 502259a854e2SKan Liang EVENT_PTR(td_bad_spec), 502359a854e2SKan Liang EVENT_PTR(td_fe_bound), 502459a854e2SKan Liang EVENT_PTR(td_be_bound), 502559a854e2SKan Liang NULL, 502659a854e2SKan Liang }; 502759a854e2SKan Liang 502860176089SKan Liang static struct attribute *icl_tsx_events_attrs[] = { 502960176089SKan Liang EVENT_PTR(tx_start), 503060176089SKan Liang EVENT_PTR(tx_abort), 503160176089SKan Liang EVENT_PTR(tx_commit), 503260176089SKan Liang EVENT_PTR(tx_capacity_read), 503360176089SKan Liang EVENT_PTR(tx_capacity_write), 503460176089SKan Liang EVENT_PTR(tx_conflict), 503560176089SKan Liang EVENT_PTR(el_start), 503660176089SKan Liang EVENT_PTR(el_abort), 503760176089SKan Liang EVENT_PTR(el_commit), 503860176089SKan Liang EVENT_PTR(el_capacity_read), 503960176089SKan Liang EVENT_PTR(el_capacity_write), 504060176089SKan Liang EVENT_PTR(el_conflict), 504160176089SKan Liang EVENT_PTR(cycles_t), 504260176089SKan Liang EVENT_PTR(cycles_ct), 504360176089SKan Liang NULL, 504460176089SKan Liang }; 504560176089SKan Liang 504661b985e3SKan Liang 504761b985e3SKan Liang EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 504861b985e3SKan Liang EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 504961b985e3SKan Liang 505061b985e3SKan Liang static struct attribute *spr_events_attrs[] = { 505161b985e3SKan Liang EVENT_PTR(mem_ld_hsw), 505261b985e3SKan Liang EVENT_PTR(mem_st_spr), 505361b985e3SKan Liang EVENT_PTR(mem_ld_aux), 505461b985e3SKan Liang NULL, 505561b985e3SKan Liang }; 505661b985e3SKan Liang 505761b985e3SKan Liang static struct attribute *spr_td_events_attrs[] = { 505861b985e3SKan Liang EVENT_PTR(slots), 505961b985e3SKan Liang EVENT_PTR(td_retiring), 506061b985e3SKan Liang EVENT_PTR(td_bad_spec), 506161b985e3SKan Liang EVENT_PTR(td_fe_bound), 506261b985e3SKan Liang EVENT_PTR(td_be_bound), 506361b985e3SKan Liang EVENT_PTR(td_heavy_ops), 506461b985e3SKan Liang EVENT_PTR(td_br_mispredict), 506561b985e3SKan Liang EVENT_PTR(td_fetch_lat), 506661b985e3SKan Liang EVENT_PTR(td_mem_bound), 506761b985e3SKan Liang NULL, 506861b985e3SKan Liang }; 506961b985e3SKan Liang 507061b985e3SKan Liang static struct attribute *spr_tsx_events_attrs[] = { 507161b985e3SKan Liang EVENT_PTR(tx_start), 507261b985e3SKan Liang EVENT_PTR(tx_abort), 507361b985e3SKan Liang EVENT_PTR(tx_commit), 507461b985e3SKan Liang EVENT_PTR(tx_capacity_read), 507561b985e3SKan Liang EVENT_PTR(tx_capacity_write), 507661b985e3SKan Liang EVENT_PTR(tx_conflict), 507761b985e3SKan Liang EVENT_PTR(cycles_t), 507861b985e3SKan Liang EVENT_PTR(cycles_ct), 507961b985e3SKan Liang NULL, 508061b985e3SKan Liang }; 508161b985e3SKan Liang 50826089327fSKan Liang static ssize_t freeze_on_smi_show(struct device *cdev, 50836089327fSKan Liang struct device_attribute *attr, 50846089327fSKan Liang char *buf) 50856089327fSKan Liang { 50866089327fSKan Liang return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 50876089327fSKan Liang } 50886089327fSKan Liang 50896089327fSKan Liang static DEFINE_MUTEX(freeze_on_smi_mutex); 50906089327fSKan Liang 50916089327fSKan Liang static ssize_t freeze_on_smi_store(struct device *cdev, 50926089327fSKan Liang struct device_attribute *attr, 50936089327fSKan Liang const char *buf, size_t count) 50946089327fSKan Liang { 50956089327fSKan Liang unsigned long val; 50966089327fSKan Liang ssize_t ret; 50976089327fSKan Liang 50986089327fSKan Liang ret = kstrtoul(buf, 0, &val); 50996089327fSKan Liang if (ret) 51006089327fSKan Liang return ret; 51016089327fSKan Liang 51026089327fSKan Liang if (val > 1) 51036089327fSKan Liang return -EINVAL; 51046089327fSKan Liang 51056089327fSKan Liang mutex_lock(&freeze_on_smi_mutex); 51066089327fSKan Liang 51076089327fSKan Liang if (x86_pmu.attr_freeze_on_smi == val) 51086089327fSKan Liang goto done; 51096089327fSKan Liang 51106089327fSKan Liang x86_pmu.attr_freeze_on_smi = val; 51116089327fSKan Liang 5112eda8a2c5SSebastian Andrzej Siewior cpus_read_lock(); 51136089327fSKan Liang on_each_cpu(flip_smm_bit, &val, 1); 5114eda8a2c5SSebastian Andrzej Siewior cpus_read_unlock(); 51156089327fSKan Liang done: 51166089327fSKan Liang mutex_unlock(&freeze_on_smi_mutex); 51176089327fSKan Liang 51186089327fSKan Liang return count; 51196089327fSKan Liang } 51206089327fSKan Liang 5121f447e4ebSStephane Eranian static void update_tfa_sched(void *ignored) 5122f447e4ebSStephane Eranian { 5123f447e4ebSStephane Eranian struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5124f447e4ebSStephane Eranian 5125f447e4ebSStephane Eranian /* 5126f447e4ebSStephane Eranian * check if PMC3 is used 5127f447e4ebSStephane Eranian * and if so force schedule out for all event types all contexts 5128f447e4ebSStephane Eranian */ 5129f447e4ebSStephane Eranian if (test_bit(3, cpuc->active_mask)) 513061e76d53SKan Liang perf_pmu_resched(x86_get_pmu(smp_processor_id())); 5131f447e4ebSStephane Eranian } 5132f447e4ebSStephane Eranian 5133f447e4ebSStephane Eranian static ssize_t show_sysctl_tfa(struct device *cdev, 5134f447e4ebSStephane Eranian struct device_attribute *attr, 5135f447e4ebSStephane Eranian char *buf) 5136f447e4ebSStephane Eranian { 5137f447e4ebSStephane Eranian return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 5138f447e4ebSStephane Eranian } 5139f447e4ebSStephane Eranian 5140f447e4ebSStephane Eranian static ssize_t set_sysctl_tfa(struct device *cdev, 5141f447e4ebSStephane Eranian struct device_attribute *attr, 5142f447e4ebSStephane Eranian const char *buf, size_t count) 5143f447e4ebSStephane Eranian { 5144f447e4ebSStephane Eranian bool val; 5145f447e4ebSStephane Eranian ssize_t ret; 5146f447e4ebSStephane Eranian 5147f447e4ebSStephane Eranian ret = kstrtobool(buf, &val); 5148f447e4ebSStephane Eranian if (ret) 5149f447e4ebSStephane Eranian return ret; 5150f447e4ebSStephane Eranian 5151f447e4ebSStephane Eranian /* no change */ 5152f447e4ebSStephane Eranian if (val == allow_tsx_force_abort) 5153f447e4ebSStephane Eranian return count; 5154f447e4ebSStephane Eranian 5155f447e4ebSStephane Eranian allow_tsx_force_abort = val; 5156f447e4ebSStephane Eranian 5157eda8a2c5SSebastian Andrzej Siewior cpus_read_lock(); 5158f447e4ebSStephane Eranian on_each_cpu(update_tfa_sched, NULL, 1); 5159eda8a2c5SSebastian Andrzej Siewior cpus_read_unlock(); 5160f447e4ebSStephane Eranian 5161f447e4ebSStephane Eranian return count; 5162f447e4ebSStephane Eranian } 5163f447e4ebSStephane Eranian 5164f447e4ebSStephane Eranian 51656089327fSKan Liang static DEVICE_ATTR_RW(freeze_on_smi); 51666089327fSKan Liang 5167b00233b5SAndi Kleen static ssize_t branches_show(struct device *cdev, 5168b00233b5SAndi Kleen struct device_attribute *attr, 5169b00233b5SAndi Kleen char *buf) 5170b00233b5SAndi Kleen { 5171b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 5172b00233b5SAndi Kleen } 5173b00233b5SAndi Kleen 5174b00233b5SAndi Kleen static DEVICE_ATTR_RO(branches); 5175b00233b5SAndi Kleen 5176b00233b5SAndi Kleen static struct attribute *lbr_attrs[] = { 5177b00233b5SAndi Kleen &dev_attr_branches.attr, 5178b00233b5SAndi Kleen NULL 5179b00233b5SAndi Kleen }; 5180b00233b5SAndi Kleen 5181b00233b5SAndi Kleen static char pmu_name_str[30]; 5182b00233b5SAndi Kleen 5183b00233b5SAndi Kleen static ssize_t pmu_name_show(struct device *cdev, 5184b00233b5SAndi Kleen struct device_attribute *attr, 5185b00233b5SAndi Kleen char *buf) 5186b00233b5SAndi Kleen { 5187b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 5188b00233b5SAndi Kleen } 5189b00233b5SAndi Kleen 5190b00233b5SAndi Kleen static DEVICE_ATTR_RO(pmu_name); 5191b00233b5SAndi Kleen 5192b00233b5SAndi Kleen static struct attribute *intel_pmu_caps_attrs[] = { 5193b00233b5SAndi Kleen &dev_attr_pmu_name.attr, 5194b00233b5SAndi Kleen NULL 5195b00233b5SAndi Kleen }; 5196b00233b5SAndi Kleen 5197f447e4ebSStephane Eranian static DEVICE_ATTR(allow_tsx_force_abort, 0644, 5198f447e4ebSStephane Eranian show_sysctl_tfa, 5199f447e4ebSStephane Eranian set_sysctl_tfa); 5200400816f6SPeter Zijlstra (Intel) 52016089327fSKan Liang static struct attribute *intel_pmu_attrs[] = { 52026089327fSKan Liang &dev_attr_freeze_on_smi.attr, 5203b7c9b392SJiri Olsa &dev_attr_allow_tsx_force_abort.attr, 52046089327fSKan Liang NULL, 52056089327fSKan Liang }; 52066089327fSKan Liang 5207baa0c833SJiri Olsa static umode_t 5208baa0c833SJiri Olsa tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5209d4ae5529SJiri Olsa { 5210baa0c833SJiri Olsa return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 5211d4ae5529SJiri Olsa } 5212d4ae5529SJiri Olsa 5213baa0c833SJiri Olsa static umode_t 5214baa0c833SJiri Olsa pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5215baa0c833SJiri Olsa { 5216baa0c833SJiri Olsa return x86_pmu.pebs ? attr->mode : 0; 5217d4ae5529SJiri Olsa } 5218d4ae5529SJiri Olsa 52191f157286SJiri Olsa static umode_t 52201f157286SJiri Olsa lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 52211f157286SJiri Olsa { 52221f157286SJiri Olsa return x86_pmu.lbr_nr ? attr->mode : 0; 52231f157286SJiri Olsa } 52241f157286SJiri Olsa 52253ea40ac7SJiri Olsa static umode_t 52263ea40ac7SJiri Olsa exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 52273ea40ac7SJiri Olsa { 52283ea40ac7SJiri Olsa return x86_pmu.version >= 2 ? attr->mode : 0; 52293ea40ac7SJiri Olsa } 52303ea40ac7SJiri Olsa 5231b7c9b392SJiri Olsa static umode_t 5232b7c9b392SJiri Olsa default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5233b7c9b392SJiri Olsa { 5234b7c9b392SJiri Olsa if (attr == &dev_attr_allow_tsx_force_abort.attr) 5235b7c9b392SJiri Olsa return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 5236b7c9b392SJiri Olsa 5237b7c9b392SJiri Olsa return attr->mode; 5238b7c9b392SJiri Olsa } 5239b7c9b392SJiri Olsa 5240baa0c833SJiri Olsa static struct attribute_group group_events_td = { 5241baa0c833SJiri Olsa .name = "events", 5242baa0c833SJiri Olsa }; 5243baa0c833SJiri Olsa 5244baa0c833SJiri Olsa static struct attribute_group group_events_mem = { 5245baa0c833SJiri Olsa .name = "events", 5246baa0c833SJiri Olsa .is_visible = pebs_is_visible, 5247baa0c833SJiri Olsa }; 5248baa0c833SJiri Olsa 5249baa0c833SJiri Olsa static struct attribute_group group_events_tsx = { 5250baa0c833SJiri Olsa .name = "events", 5251baa0c833SJiri Olsa .is_visible = tsx_is_visible, 5252baa0c833SJiri Olsa }; 5253baa0c833SJiri Olsa 52541f157286SJiri Olsa static struct attribute_group group_caps_gen = { 52551f157286SJiri Olsa .name = "caps", 52561f157286SJiri Olsa .attrs = intel_pmu_caps_attrs, 52571f157286SJiri Olsa }; 52581f157286SJiri Olsa 52591f157286SJiri Olsa static struct attribute_group group_caps_lbr = { 52601f157286SJiri Olsa .name = "caps", 52611f157286SJiri Olsa .attrs = lbr_attrs, 52621f157286SJiri Olsa .is_visible = lbr_is_visible, 52631f157286SJiri Olsa }; 52641f157286SJiri Olsa 52653ea40ac7SJiri Olsa static struct attribute_group group_format_extra = { 52663ea40ac7SJiri Olsa .name = "format", 52673ea40ac7SJiri Olsa .is_visible = exra_is_visible, 52683ea40ac7SJiri Olsa }; 52693ea40ac7SJiri Olsa 5270b6576880SJiri Olsa static struct attribute_group group_format_extra_skl = { 5271b6576880SJiri Olsa .name = "format", 5272b6576880SJiri Olsa .is_visible = exra_is_visible, 5273b6576880SJiri Olsa }; 5274b6576880SJiri Olsa 52756a9f4efeSJiri Olsa static struct attribute_group group_default = { 52766a9f4efeSJiri Olsa .attrs = intel_pmu_attrs, 5277b7c9b392SJiri Olsa .is_visible = default_is_visible, 52786a9f4efeSJiri Olsa }; 52796a9f4efeSJiri Olsa 5280baa0c833SJiri Olsa static const struct attribute_group *attr_update[] = { 5281baa0c833SJiri Olsa &group_events_td, 5282baa0c833SJiri Olsa &group_events_mem, 5283baa0c833SJiri Olsa &group_events_tsx, 52841f157286SJiri Olsa &group_caps_gen, 52851f157286SJiri Olsa &group_caps_lbr, 52863ea40ac7SJiri Olsa &group_format_extra, 5287b6576880SJiri Olsa &group_format_extra_skl, 52886a9f4efeSJiri Olsa &group_default, 5289baa0c833SJiri Olsa NULL, 5290baa0c833SJiri Olsa }; 5291baa0c833SJiri Olsa 5292f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 5293f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 5294f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 5295f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 5296f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 5297f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 5298f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 5299f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 5300f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 5301f83d2f91SKan Liang 5302f83d2f91SKan Liang static struct attribute *adl_hybrid_events_attrs[] = { 5303f83d2f91SKan Liang EVENT_PTR(slots_adl), 5304f83d2f91SKan Liang EVENT_PTR(td_retiring_adl), 5305f83d2f91SKan Liang EVENT_PTR(td_bad_spec_adl), 5306f83d2f91SKan Liang EVENT_PTR(td_fe_bound_adl), 5307f83d2f91SKan Liang EVENT_PTR(td_be_bound_adl), 5308f83d2f91SKan Liang EVENT_PTR(td_heavy_ops_adl), 5309f83d2f91SKan Liang EVENT_PTR(td_br_mis_adl), 5310f83d2f91SKan Liang EVENT_PTR(td_fetch_lat_adl), 5311f83d2f91SKan Liang EVENT_PTR(td_mem_bound_adl), 5312f83d2f91SKan Liang NULL, 5313f83d2f91SKan Liang }; 5314f83d2f91SKan Liang 5315f83d2f91SKan Liang /* Must be in IDX order */ 5316f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 5317f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 5318f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 5319f83d2f91SKan Liang 5320f83d2f91SKan Liang static struct attribute *adl_hybrid_mem_attrs[] = { 5321f83d2f91SKan Liang EVENT_PTR(mem_ld_adl), 5322f83d2f91SKan Liang EVENT_PTR(mem_st_adl), 5323f83d2f91SKan Liang EVENT_PTR(mem_ld_aux_adl), 5324f83d2f91SKan Liang NULL, 5325f83d2f91SKan Liang }; 5326f83d2f91SKan Liang 5327f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 5328f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 5329f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 5330f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 5331f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 5332f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 5333f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 5334f83d2f91SKan Liang EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 5335f83d2f91SKan Liang 5336f83d2f91SKan Liang static struct attribute *adl_hybrid_tsx_attrs[] = { 5337f83d2f91SKan Liang EVENT_PTR(tx_start_adl), 5338f83d2f91SKan Liang EVENT_PTR(tx_abort_adl), 5339f83d2f91SKan Liang EVENT_PTR(tx_commit_adl), 5340f83d2f91SKan Liang EVENT_PTR(tx_capacity_read_adl), 5341f83d2f91SKan Liang EVENT_PTR(tx_capacity_write_adl), 5342f83d2f91SKan Liang EVENT_PTR(tx_conflict_adl), 5343f83d2f91SKan Liang EVENT_PTR(cycles_t_adl), 5344f83d2f91SKan Liang EVENT_PTR(cycles_ct_adl), 5345f83d2f91SKan Liang NULL, 5346f83d2f91SKan Liang }; 5347f83d2f91SKan Liang 5348f83d2f91SKan Liang FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 5349f83d2f91SKan Liang FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 5350f83d2f91SKan Liang FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); 5351f83d2f91SKan Liang FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); 5352f83d2f91SKan Liang FORMAT_ATTR_HYBRID(frontend, hybrid_big); 5353f83d2f91SKan Liang 5354f83d2f91SKan Liang static struct attribute *adl_hybrid_extra_attr_rtm[] = { 5355f83d2f91SKan Liang FORMAT_HYBRID_PTR(in_tx), 5356f83d2f91SKan Liang FORMAT_HYBRID_PTR(in_tx_cp), 5357f83d2f91SKan Liang FORMAT_HYBRID_PTR(offcore_rsp), 5358f83d2f91SKan Liang FORMAT_HYBRID_PTR(ldlat), 5359f83d2f91SKan Liang FORMAT_HYBRID_PTR(frontend), 5360f83d2f91SKan Liang NULL, 5361f83d2f91SKan Liang }; 5362f83d2f91SKan Liang 5363f83d2f91SKan Liang static struct attribute *adl_hybrid_extra_attr[] = { 5364f83d2f91SKan Liang FORMAT_HYBRID_PTR(offcore_rsp), 5365f83d2f91SKan Liang FORMAT_HYBRID_PTR(ldlat), 5366f83d2f91SKan Liang FORMAT_HYBRID_PTR(frontend), 5367f83d2f91SKan Liang NULL, 5368f83d2f91SKan Liang }; 5369f83d2f91SKan Liang 537058ae30c2SKan Liang static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 537158ae30c2SKan Liang { 537258ae30c2SKan Liang struct device *dev = kobj_to_dev(kobj); 537358ae30c2SKan Liang struct x86_hybrid_pmu *pmu = 537458ae30c2SKan Liang container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 537558ae30c2SKan Liang struct perf_pmu_events_hybrid_attr *pmu_attr = 537658ae30c2SKan Liang container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 537758ae30c2SKan Liang 537858ae30c2SKan Liang return pmu->cpu_type & pmu_attr->pmu_type; 537958ae30c2SKan Liang } 538058ae30c2SKan Liang 538158ae30c2SKan Liang static umode_t hybrid_events_is_visible(struct kobject *kobj, 538258ae30c2SKan Liang struct attribute *attr, int i) 538358ae30c2SKan Liang { 538458ae30c2SKan Liang return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 538558ae30c2SKan Liang } 538658ae30c2SKan Liang 538758ae30c2SKan Liang static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 538858ae30c2SKan Liang { 538958ae30c2SKan Liang int cpu = cpumask_first(&pmu->supported_cpus); 539058ae30c2SKan Liang 539158ae30c2SKan Liang return (cpu >= nr_cpu_ids) ? -1 : cpu; 539258ae30c2SKan Liang } 539358ae30c2SKan Liang 539458ae30c2SKan Liang static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 539558ae30c2SKan Liang struct attribute *attr, int i) 539658ae30c2SKan Liang { 539758ae30c2SKan Liang struct device *dev = kobj_to_dev(kobj); 539858ae30c2SKan Liang struct x86_hybrid_pmu *pmu = 539958ae30c2SKan Liang container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 540058ae30c2SKan Liang int cpu = hybrid_find_supported_cpu(pmu); 540158ae30c2SKan Liang 540258ae30c2SKan Liang return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 540358ae30c2SKan Liang } 540458ae30c2SKan Liang 540558ae30c2SKan Liang static umode_t hybrid_format_is_visible(struct kobject *kobj, 540658ae30c2SKan Liang struct attribute *attr, int i) 540758ae30c2SKan Liang { 540858ae30c2SKan Liang struct device *dev = kobj_to_dev(kobj); 540958ae30c2SKan Liang struct x86_hybrid_pmu *pmu = 541058ae30c2SKan Liang container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 541158ae30c2SKan Liang struct perf_pmu_format_hybrid_attr *pmu_attr = 541258ae30c2SKan Liang container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 541358ae30c2SKan Liang int cpu = hybrid_find_supported_cpu(pmu); 541458ae30c2SKan Liang 541558ae30c2SKan Liang return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; 541658ae30c2SKan Liang } 541758ae30c2SKan Liang 541858ae30c2SKan Liang static struct attribute_group hybrid_group_events_td = { 541958ae30c2SKan Liang .name = "events", 542058ae30c2SKan Liang .is_visible = hybrid_events_is_visible, 542158ae30c2SKan Liang }; 542258ae30c2SKan Liang 542358ae30c2SKan Liang static struct attribute_group hybrid_group_events_mem = { 542458ae30c2SKan Liang .name = "events", 542558ae30c2SKan Liang .is_visible = hybrid_events_is_visible, 542658ae30c2SKan Liang }; 542758ae30c2SKan Liang 542858ae30c2SKan Liang static struct attribute_group hybrid_group_events_tsx = { 542958ae30c2SKan Liang .name = "events", 543058ae30c2SKan Liang .is_visible = hybrid_tsx_is_visible, 543158ae30c2SKan Liang }; 543258ae30c2SKan Liang 543358ae30c2SKan Liang static struct attribute_group hybrid_group_format_extra = { 543458ae30c2SKan Liang .name = "format", 543558ae30c2SKan Liang .is_visible = hybrid_format_is_visible, 543658ae30c2SKan Liang }; 543758ae30c2SKan Liang 543858ae30c2SKan Liang static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 543958ae30c2SKan Liang struct device_attribute *attr, 544058ae30c2SKan Liang char *buf) 544158ae30c2SKan Liang { 544258ae30c2SKan Liang struct x86_hybrid_pmu *pmu = 544358ae30c2SKan Liang container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 544458ae30c2SKan Liang 544558ae30c2SKan Liang return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 544658ae30c2SKan Liang } 544758ae30c2SKan Liang 544858ae30c2SKan Liang static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 544958ae30c2SKan Liang static struct attribute *intel_hybrid_cpus_attrs[] = { 545058ae30c2SKan Liang &dev_attr_cpus.attr, 545158ae30c2SKan Liang NULL, 545258ae30c2SKan Liang }; 545358ae30c2SKan Liang 545458ae30c2SKan Liang static struct attribute_group hybrid_group_cpus = { 545558ae30c2SKan Liang .attrs = intel_hybrid_cpus_attrs, 545658ae30c2SKan Liang }; 545758ae30c2SKan Liang 545858ae30c2SKan Liang static const struct attribute_group *hybrid_attr_update[] = { 545958ae30c2SKan Liang &hybrid_group_events_td, 546058ae30c2SKan Liang &hybrid_group_events_mem, 546158ae30c2SKan Liang &hybrid_group_events_tsx, 546258ae30c2SKan Liang &group_caps_gen, 546358ae30c2SKan Liang &group_caps_lbr, 546458ae30c2SKan Liang &hybrid_group_format_extra, 546558ae30c2SKan Liang &group_default, 546658ae30c2SKan Liang &hybrid_group_cpus, 546758ae30c2SKan Liang NULL, 546858ae30c2SKan Liang }; 546958ae30c2SKan Liang 5470baa0c833SJiri Olsa static struct attribute *empty_attrs; 5471baa0c833SJiri Olsa 5472b8c4d1a8SKan Liang static void intel_pmu_check_num_counters(int *num_counters, 5473b8c4d1a8SKan Liang int *num_counters_fixed, 5474b8c4d1a8SKan Liang u64 *intel_ctrl, u64 fixed_mask) 5475b8c4d1a8SKan Liang { 5476b8c4d1a8SKan Liang if (*num_counters > INTEL_PMC_MAX_GENERIC) { 5477b8c4d1a8SKan Liang WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5478b8c4d1a8SKan Liang *num_counters, INTEL_PMC_MAX_GENERIC); 5479b8c4d1a8SKan Liang *num_counters = INTEL_PMC_MAX_GENERIC; 5480b8c4d1a8SKan Liang } 5481b8c4d1a8SKan Liang *intel_ctrl = (1ULL << *num_counters) - 1; 5482b8c4d1a8SKan Liang 5483b8c4d1a8SKan Liang if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5484b8c4d1a8SKan Liang WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5485b8c4d1a8SKan Liang *num_counters_fixed, INTEL_PMC_MAX_FIXED); 5486b8c4d1a8SKan Liang *num_counters_fixed = INTEL_PMC_MAX_FIXED; 5487b8c4d1a8SKan Liang } 5488b8c4d1a8SKan Liang 5489b8c4d1a8SKan Liang *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; 5490b8c4d1a8SKan Liang } 5491b8c4d1a8SKan Liang 5492bc14fe1bSKan Liang static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5493bc14fe1bSKan Liang int num_counters, 5494bc14fe1bSKan Liang int num_counters_fixed, 5495bc14fe1bSKan Liang u64 intel_ctrl) 5496bc14fe1bSKan Liang { 5497bc14fe1bSKan Liang struct event_constraint *c; 5498bc14fe1bSKan Liang 5499bc14fe1bSKan Liang if (!event_constraints) 5500bc14fe1bSKan Liang return; 5501bc14fe1bSKan Liang 5502bc14fe1bSKan Liang /* 5503bc14fe1bSKan Liang * event on fixed counter2 (REF_CYCLES) only works on this 5504bc14fe1bSKan Liang * counter, so do not extend mask to generic counters 5505bc14fe1bSKan Liang */ 5506bc14fe1bSKan Liang for_each_event_constraint(c, event_constraints) { 5507bc14fe1bSKan Liang /* 5508bc14fe1bSKan Liang * Don't extend the topdown slots and metrics 5509bc14fe1bSKan Liang * events to the generic counters. 5510bc14fe1bSKan Liang */ 5511bc14fe1bSKan Liang if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5512bc14fe1bSKan Liang /* 5513bc14fe1bSKan Liang * Disable topdown slots and metrics events, 5514bc14fe1bSKan Liang * if slots event is not in CPUID. 5515bc14fe1bSKan Liang */ 5516bc14fe1bSKan Liang if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 5517bc14fe1bSKan Liang c->idxmsk64 = 0; 5518bc14fe1bSKan Liang c->weight = hweight64(c->idxmsk64); 5519bc14fe1bSKan Liang continue; 5520bc14fe1bSKan Liang } 5521bc14fe1bSKan Liang 5522bc14fe1bSKan Liang if (c->cmask == FIXED_EVENT_FLAGS) { 5523bc14fe1bSKan Liang /* Disabled fixed counters which are not in CPUID */ 5524bc14fe1bSKan Liang c->idxmsk64 &= intel_ctrl; 5525bc14fe1bSKan Liang 5526bc14fe1bSKan Liang if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) 5527bc14fe1bSKan Liang c->idxmsk64 |= (1ULL << num_counters) - 1; 5528bc14fe1bSKan Liang } 5529bc14fe1bSKan Liang c->idxmsk64 &= 5530bc14fe1bSKan Liang ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); 5531bc14fe1bSKan Liang c->weight = hweight64(c->idxmsk64); 5532bc14fe1bSKan Liang } 5533bc14fe1bSKan Liang } 5534bc14fe1bSKan Liang 553534d5b61fSKan Liang static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 553634d5b61fSKan Liang { 553734d5b61fSKan Liang struct extra_reg *er; 553834d5b61fSKan Liang 553934d5b61fSKan Liang /* 554034d5b61fSKan Liang * Access extra MSR may cause #GP under certain circumstances. 554134d5b61fSKan Liang * E.g. KVM doesn't support offcore event 554234d5b61fSKan Liang * Check all extra_regs here. 554334d5b61fSKan Liang */ 554434d5b61fSKan Liang if (!extra_regs) 554534d5b61fSKan Liang return; 554634d5b61fSKan Liang 554734d5b61fSKan Liang for (er = extra_regs; er->msr; er++) { 554834d5b61fSKan Liang er->extra_msr_access = check_msr(er->msr, 0x11UL); 554934d5b61fSKan Liang /* Disable LBR select mapping */ 555034d5b61fSKan Liang if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 555134d5b61fSKan Liang x86_pmu.lbr_sel_map = NULL; 555234d5b61fSKan Liang } 555334d5b61fSKan Liang } 555434d5b61fSKan Liang 5555d9977c43SKan Liang static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) 5556d9977c43SKan Liang { 5557d9977c43SKan Liang struct x86_hybrid_pmu *pmu; 5558d9977c43SKan Liang int i; 5559d9977c43SKan Liang 5560d9977c43SKan Liang for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5561d9977c43SKan Liang pmu = &x86_pmu.hybrid_pmu[i]; 5562d9977c43SKan Liang 5563d9977c43SKan Liang intel_pmu_check_num_counters(&pmu->num_counters, 5564d9977c43SKan Liang &pmu->num_counters_fixed, 5565d9977c43SKan Liang &pmu->intel_ctrl, 5566d9977c43SKan Liang fixed_mask); 5567d9977c43SKan Liang 5568d9977c43SKan Liang if (pmu->intel_cap.perf_metrics) { 5569d9977c43SKan Liang pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5570d9977c43SKan Liang pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; 5571d9977c43SKan Liang } 5572d9977c43SKan Liang 5573d9977c43SKan Liang if (pmu->intel_cap.pebs_output_pt_available) 5574d9977c43SKan Liang pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 5575d9977c43SKan Liang 5576d9977c43SKan Liang intel_pmu_check_event_constraints(pmu->event_constraints, 5577d9977c43SKan Liang pmu->num_counters, 5578d9977c43SKan Liang pmu->num_counters_fixed, 5579d9977c43SKan Liang pmu->intel_ctrl); 5580d9977c43SKan Liang 5581d9977c43SKan Liang intel_pmu_check_extra_regs(pmu->extra_regs); 5582d9977c43SKan Liang } 5583d9977c43SKan Liang } 5584d9977c43SKan Liang 5585e1069839SBorislav Petkov __init int intel_pmu_init(void) 5586e1069839SBorislav Petkov { 5587b6576880SJiri Olsa struct attribute **extra_skl_attr = &empty_attrs; 5588baa0c833SJiri Olsa struct attribute **extra_attr = &empty_attrs; 5589baa0c833SJiri Olsa struct attribute **td_attr = &empty_attrs; 5590baa0c833SJiri Olsa struct attribute **mem_attr = &empty_attrs; 5591baa0c833SJiri Olsa struct attribute **tsx_attr = &empty_attrs; 5592e1069839SBorislav Petkov union cpuid10_edx edx; 5593e1069839SBorislav Petkov union cpuid10_eax eax; 5594e1069839SBorislav Petkov union cpuid10_ebx ebx; 559532451614SKan Liang unsigned int fixed_mask; 5596faaeff98SKan Liang bool pmem = false; 5597e1069839SBorislav Petkov int version, i; 5598b00233b5SAndi Kleen char *name; 5599f83d2f91SKan Liang struct x86_hybrid_pmu *pmu; 5600e1069839SBorislav Petkov 5601e1069839SBorislav Petkov if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5602e1069839SBorislav Petkov switch (boot_cpu_data.x86) { 5603e1069839SBorislav Petkov case 0x6: 5604e1069839SBorislav Petkov return p6_pmu_init(); 5605e1069839SBorislav Petkov case 0xb: 5606e1069839SBorislav Petkov return knc_pmu_init(); 5607e1069839SBorislav Petkov case 0xf: 5608e1069839SBorislav Petkov return p4_pmu_init(); 5609e1069839SBorislav Petkov } 5610e1069839SBorislav Petkov return -ENODEV; 5611e1069839SBorislav Petkov } 5612e1069839SBorislav Petkov 5613e1069839SBorislav Petkov /* 5614e1069839SBorislav Petkov * Check whether the Architectural PerfMon supports 5615e1069839SBorislav Petkov * Branch Misses Retired hw_event or not. 5616e1069839SBorislav Petkov */ 561732451614SKan Liang cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 5618e1069839SBorislav Petkov if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5619e1069839SBorislav Petkov return -ENODEV; 5620e1069839SBorislav Petkov 5621e1069839SBorislav Petkov version = eax.split.version_id; 5622e1069839SBorislav Petkov if (version < 2) 5623e1069839SBorislav Petkov x86_pmu = core_pmu; 5624e1069839SBorislav Petkov else 5625e1069839SBorislav Petkov x86_pmu = intel_pmu; 5626e1069839SBorislav Petkov 5627e1069839SBorislav Petkov x86_pmu.version = version; 5628e1069839SBorislav Petkov x86_pmu.num_counters = eax.split.num_counters; 5629e1069839SBorislav Petkov x86_pmu.cntval_bits = eax.split.bit_width; 5630e1069839SBorislav Petkov x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5631e1069839SBorislav Petkov 5632e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 5633e1069839SBorislav Petkov x86_pmu.events_mask_len = eax.split.mask_length; 5634e1069839SBorislav Petkov 5635e1069839SBorislav Petkov x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5636e1069839SBorislav Petkov 5637e1069839SBorislav Petkov /* 5638e1069839SBorislav Petkov * Quirk: v2 perfmon does not report fixed-purpose events, so 5639f92b7604SImre Palik * assume at least 3 events, when not running in a hypervisor: 5640e1069839SBorislav Petkov */ 564132451614SKan Liang if (version > 1 && version < 5) { 5642f92b7604SImre Palik int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5643f92b7604SImre Palik 5644f92b7604SImre Palik x86_pmu.num_counters_fixed = 5645f92b7604SImre Palik max((int)edx.split.num_counters_fixed, assume); 564632451614SKan Liang 564732451614SKan Liang fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; 564832451614SKan Liang } else if (version >= 5) 564932451614SKan Liang x86_pmu.num_counters_fixed = fls(fixed_mask); 5650e1069839SBorislav Petkov 5651e1069839SBorislav Petkov if (boot_cpu_has(X86_FEATURE_PDCM)) { 5652e1069839SBorislav Petkov u64 capabilities; 5653e1069839SBorislav Petkov 5654e1069839SBorislav Petkov rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5655e1069839SBorislav Petkov x86_pmu.intel_cap.capabilities = capabilities; 5656e1069839SBorislav Petkov } 5657e1069839SBorislav Petkov 5658c301b1d8SKan Liang if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 56599f354a72SKan Liang x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5660c301b1d8SKan Liang x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5661c301b1d8SKan Liang } 56629f354a72SKan Liang 566347125db2SKan Liang if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 566447125db2SKan Liang intel_pmu_arch_lbr_init(); 566547125db2SKan Liang 5666e1069839SBorislav Petkov intel_ds_init(); 5667e1069839SBorislav Petkov 5668e1069839SBorislav Petkov x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5669e1069839SBorislav Petkov 5670cadbaa03SStephane Eranian if (version >= 5) { 5671cadbaa03SStephane Eranian x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5672cadbaa03SStephane Eranian if (x86_pmu.intel_cap.anythread_deprecated) 5673cadbaa03SStephane Eranian pr_cont(" AnyThread deprecated, "); 5674cadbaa03SStephane Eranian } 5675cadbaa03SStephane Eranian 5676e1069839SBorislav Petkov /* 5677e1069839SBorislav Petkov * Install the hw-cache-events table: 5678e1069839SBorislav Petkov */ 5679e1069839SBorislav Petkov switch (boot_cpu_data.x86_model) { 5680ef5f9f47SDave Hansen case INTEL_FAM6_CORE_YONAH: 5681e1069839SBorislav Petkov pr_cont("Core events, "); 5682b00233b5SAndi Kleen name = "core"; 5683e1069839SBorislav Petkov break; 5684e1069839SBorislav Petkov 5685ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM: 5686e1069839SBorislav Petkov x86_add_quirk(intel_clovertown_quirk); 5687df561f66SGustavo A. R. Silva fallthrough; 56882b0fc374SGustavo A. R. Silva 5689ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM_L: 5690ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_PENRYN: 5691ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_DUNNINGTON: 5692e1069839SBorislav Petkov memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5693e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5694e1069839SBorislav Petkov 5695e1069839SBorislav Petkov intel_pmu_lbr_init_core(); 5696e1069839SBorislav Petkov 5697e1069839SBorislav Petkov x86_pmu.event_constraints = intel_core2_event_constraints; 5698e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5699e1069839SBorislav Petkov pr_cont("Core2 events, "); 5700b00233b5SAndi Kleen name = "core2"; 5701e1069839SBorislav Petkov break; 5702e1069839SBorislav Petkov 5703ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM: 5704ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EP: 5705ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EX: 5706e1069839SBorislav Petkov memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5707e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5708e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5709e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5710e1069839SBorislav Petkov 5711e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 5712e1069839SBorislav Petkov 5713e1069839SBorislav Petkov x86_pmu.event_constraints = intel_nehalem_event_constraints; 5714e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5715e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5716e1069839SBorislav Petkov x86_pmu.extra_regs = intel_nehalem_extra_regs; 571744d3bbb6SJosh Hunt x86_pmu.limit_period = nhm_limit_period; 5718e1069839SBorislav Petkov 5719d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 5720e1069839SBorislav Petkov 5721e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 5722e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5723e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5724e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5725e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5726e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5727e1069839SBorislav Petkov 5728e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 5729e1069839SBorislav Petkov x86_add_quirk(intel_nehalem_quirk); 573095298355SAndi Kleen x86_pmu.pebs_no_tlb = 1; 5731a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5732e1069839SBorislav Petkov 5733e1069839SBorislav Petkov pr_cont("Nehalem events, "); 5734b00233b5SAndi Kleen name = "nehalem"; 5735e1069839SBorislav Petkov break; 5736e1069839SBorislav Petkov 5737f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL: 5738f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL_MID: 5739f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL: 5740f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_MID: 5741f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5742e1069839SBorislav Petkov memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5743e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5744e1069839SBorislav Petkov 5745e1069839SBorislav Petkov intel_pmu_lbr_init_atom(); 5746e1069839SBorislav Petkov 5747e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 5748e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5749e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5750e1069839SBorislav Petkov pr_cont("Atom events, "); 5751b00233b5SAndi Kleen name = "bonnell"; 5752e1069839SBorislav Petkov break; 5753e1069839SBorislav Petkov 5754f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT: 57555ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_D: 5756f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_MID: 5757ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_AIRMONT: 5758f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_AIRMONT_MID: 5759e1069839SBorislav Petkov memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5760e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5761e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5762e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5763e1069839SBorislav Petkov 5764f21d5adcSKan Liang intel_pmu_lbr_init_slm(); 5765e1069839SBorislav Petkov 5766e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 5767e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5768e1069839SBorislav Petkov x86_pmu.extra_regs = intel_slm_extra_regs; 5769e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5770baa0c833SJiri Olsa td_attr = slm_events_attrs; 5771a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5772e1069839SBorislav Petkov pr_cont("Silvermont events, "); 5773b00233b5SAndi Kleen name = "silvermont"; 5774e1069839SBorislav Petkov break; 5775e1069839SBorislav Petkov 5776ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_GOLDMONT: 57775ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_D: 57788b92c3a7SKan Liang memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 57798b92c3a7SKan Liang sizeof(hw_cache_event_ids)); 57808b92c3a7SKan Liang memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 57818b92c3a7SKan Liang sizeof(hw_cache_extra_regs)); 57828b92c3a7SKan Liang 57838b92c3a7SKan Liang intel_pmu_lbr_init_skl(); 57848b92c3a7SKan Liang 57858b92c3a7SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 57868b92c3a7SKan Liang x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 57878b92c3a7SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 57888b92c3a7SKan Liang /* 57898b92c3a7SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 57908b92c3a7SKan Liang * for precise cycles. 57918b92c3a7SKan Liang * :pp is identical to :ppp 57928b92c3a7SKan Liang */ 57938b92c3a7SKan Liang x86_pmu.pebs_aliases = NULL; 57948b92c3a7SKan Liang x86_pmu.pebs_prec_dist = true; 5795ccbebba4SAlexander Shishkin x86_pmu.lbr_pt_coexist = true; 57968b92c3a7SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5797baa0c833SJiri Olsa td_attr = glm_events_attrs; 5798a5df70c3SAndi Kleen extra_attr = slm_format_attr; 57998b92c3a7SKan Liang pr_cont("Goldmont events, "); 5800b00233b5SAndi Kleen name = "goldmont"; 58018b92c3a7SKan Liang break; 58028b92c3a7SKan Liang 5803f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5804dd0b06b5SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5805dd0b06b5SKan Liang sizeof(hw_cache_event_ids)); 5806dd0b06b5SKan Liang memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5807dd0b06b5SKan Liang sizeof(hw_cache_extra_regs)); 5808dd0b06b5SKan Liang 5809dd0b06b5SKan Liang intel_pmu_lbr_init_skl(); 5810dd0b06b5SKan Liang 5811dd0b06b5SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 5812dd0b06b5SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 5813dd0b06b5SKan Liang /* 5814dd0b06b5SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5815dd0b06b5SKan Liang * for precise cycles. 5816dd0b06b5SKan Liang */ 5817dd0b06b5SKan Liang x86_pmu.pebs_aliases = NULL; 5818dd0b06b5SKan Liang x86_pmu.pebs_prec_dist = true; 5819dd0b06b5SKan Liang x86_pmu.lbr_pt_coexist = true; 5820dd0b06b5SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5821a38b0ba1SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 5822dd0b06b5SKan Liang x86_pmu.get_event_constraints = glp_get_event_constraints; 5823baa0c833SJiri Olsa td_attr = glm_events_attrs; 5824dd0b06b5SKan Liang /* Goldmont Plus has 4-wide pipeline */ 5825dd0b06b5SKan Liang event_attr_td_total_slots_scale_glm.event_str = "4"; 5826a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5827dd0b06b5SKan Liang pr_cont("Goldmont plus events, "); 5828b00233b5SAndi Kleen name = "goldmont_plus"; 5829dd0b06b5SKan Liang break; 5830dd0b06b5SKan Liang 58315ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_TREMONT_D: 5832eda23b38SKan Liang case INTEL_FAM6_ATOM_TREMONT: 5833dbfd6388SKan Liang case INTEL_FAM6_ATOM_TREMONT_L: 58346daeb873SKan Liang x86_pmu.late_ack = true; 58356daeb873SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 58366daeb873SKan Liang sizeof(hw_cache_event_ids)); 58376daeb873SKan Liang memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 58386daeb873SKan Liang sizeof(hw_cache_extra_regs)); 58396daeb873SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 58406daeb873SKan Liang 58416daeb873SKan Liang intel_pmu_lbr_init_skl(); 58426daeb873SKan Liang 58436daeb873SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 58446daeb873SKan Liang x86_pmu.extra_regs = intel_tnt_extra_regs; 58456daeb873SKan Liang /* 58466daeb873SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 58476daeb873SKan Liang * for precise cycles. 58486daeb873SKan Liang */ 58496daeb873SKan Liang x86_pmu.pebs_aliases = NULL; 58506daeb873SKan Liang x86_pmu.pebs_prec_dist = true; 58516daeb873SKan Liang x86_pmu.lbr_pt_coexist = true; 58526daeb873SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 58536daeb873SKan Liang x86_pmu.get_event_constraints = tnt_get_event_constraints; 5854c2208046SKan Liang td_attr = tnt_events_attrs; 58556daeb873SKan Liang extra_attr = slm_format_attr; 58566daeb873SKan Liang pr_cont("Tremont events, "); 58576daeb873SKan Liang name = "Tremont"; 58586daeb873SKan Liang break; 58596daeb873SKan Liang 5860ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE: 5861ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EP: 5862ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EX: 5863e1069839SBorislav Petkov memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5864e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5865e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5866e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5867e1069839SBorislav Petkov 5868e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 5869e1069839SBorislav Petkov 5870e1069839SBorislav Petkov x86_pmu.event_constraints = intel_westmere_event_constraints; 5871e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5872e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5873e1069839SBorislav Petkov x86_pmu.extra_regs = intel_westmere_extra_regs; 5874e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5875e1069839SBorislav Petkov 5876d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 5877e1069839SBorislav Petkov 5878e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 5879e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5880e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5881e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5882e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5883e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5884e1069839SBorislav Petkov 5885e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 5886a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5887e1069839SBorislav Petkov pr_cont("Westmere events, "); 5888b00233b5SAndi Kleen name = "westmere"; 5889e1069839SBorislav Petkov break; 5890e1069839SBorislav Petkov 5891ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 5892ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 5893e1069839SBorislav Petkov x86_add_quirk(intel_sandybridge_quirk); 5894e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 5895e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5896e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5897e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5898e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5899e1069839SBorislav Petkov 5900e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 5901e1069839SBorislav Petkov 5902e1069839SBorislav Petkov x86_pmu.event_constraints = intel_snb_event_constraints; 5903e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5904e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5905ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5906e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5907e1069839SBorislav Petkov else 5908e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 5909e1069839SBorislav Petkov 5910e1069839SBorislav Petkov 5911e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5912e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5913e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5914e1069839SBorislav Petkov 5915baa0c833SJiri Olsa td_attr = snb_events_attrs; 5916d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 5917e1069839SBorislav Petkov 5918e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5919e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5920e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5921e1069839SBorislav Petkov /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5922e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5923e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5924e1069839SBorislav Petkov 5925a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5926a5df70c3SAndi Kleen 5927e1069839SBorislav Petkov pr_cont("SandyBridge events, "); 5928b00233b5SAndi Kleen name = "sandybridge"; 5929e1069839SBorislav Petkov break; 5930e1069839SBorislav Petkov 5931ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE: 5932ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE_X: 5933e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 5934e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5935e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5936e1069839SBorislav Petkov /* dTLB-load-misses on IVB is different than SNB */ 5937e1069839SBorislav Petkov hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5938e1069839SBorislav Petkov 5939e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5940e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5941e1069839SBorislav Petkov 5942e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 5943e1069839SBorislav Petkov 5944e1069839SBorislav Petkov x86_pmu.event_constraints = intel_ivb_event_constraints; 5945e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5946e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5947e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5948ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5949e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5950e1069839SBorislav Petkov else 5951e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 5952e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5953e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5954e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5955e1069839SBorislav Petkov 5956baa0c833SJiri Olsa td_attr = snb_events_attrs; 5957d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 5958e1069839SBorislav Petkov 5959e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5960e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5961e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5962e1069839SBorislav Petkov 5963a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5964a5df70c3SAndi Kleen 5965e1069839SBorislav Petkov pr_cont("IvyBridge events, "); 5966b00233b5SAndi Kleen name = "ivybridge"; 5967e1069839SBorislav Petkov break; 5968e1069839SBorislav Petkov 5969e1069839SBorislav Petkov 5970c66f78a6SPeter Zijlstra case INTEL_FAM6_HASWELL: 5971ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_X: 5972af239c44SPeter Zijlstra case INTEL_FAM6_HASWELL_L: 59735e741407SPeter Zijlstra case INTEL_FAM6_HASWELL_G: 5974e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 59759b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5976e1069839SBorislav Petkov x86_pmu.late_ack = true; 5977e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5978e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5979e1069839SBorislav Petkov 5980e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 5981e1069839SBorislav Petkov 5982e1069839SBorislav Petkov x86_pmu.event_constraints = intel_hsw_event_constraints; 5983e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5984e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5985e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5986e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5987e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5988e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5989e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5990e1069839SBorislav Petkov 5991e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5992e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5993e1069839SBorislav Petkov x86_pmu.lbr_double_abort = true; 5994a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5995a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5996baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5997d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5998d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5999e1069839SBorislav Petkov pr_cont("Haswell events, "); 6000b00233b5SAndi Kleen name = "haswell"; 6001e1069839SBorislav Petkov break; 6002e1069839SBorislav Petkov 6003c66f78a6SPeter Zijlstra case INTEL_FAM6_BROADWELL: 60045ebb34edSPeter Zijlstra case INTEL_FAM6_BROADWELL_D: 60055e741407SPeter Zijlstra case INTEL_FAM6_BROADWELL_G: 6006ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_X: 60079b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 6008e1069839SBorislav Petkov x86_pmu.late_ack = true; 6009e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6010e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6011e1069839SBorislav Petkov 6012e1069839SBorislav Petkov /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 6013e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 6014e1069839SBorislav Petkov BDW_L3_MISS|HSW_SNOOP_DRAM; 6015e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 6016e1069839SBorislav Petkov HSW_SNOOP_DRAM; 6017e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 6018e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6019e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 6020e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 6021e1069839SBorislav Petkov 6022e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 6023e1069839SBorislav Petkov 6024e1069839SBorislav Petkov x86_pmu.event_constraints = intel_bdw_event_constraints; 6025b3e62463SStephane Eranian x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 6026e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 6027e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 6028e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 6029e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 6030e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6031e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6032e1069839SBorislav Petkov 6033e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 6034e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 6035e1069839SBorislav Petkov x86_pmu.limit_period = bdw_limit_period; 6036a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6037a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 6038baa0c833SJiri Olsa td_attr = hsw_events_attrs; 6039d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 6040d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 6041e1069839SBorislav Petkov pr_cont("Broadwell events, "); 6042b00233b5SAndi Kleen name = "broadwell"; 6043e1069839SBorislav Petkov break; 6044e1069839SBorislav Petkov 6045ef5f9f47SDave Hansen case INTEL_FAM6_XEON_PHI_KNL: 6046608284bfSPiotr Luc case INTEL_FAM6_XEON_PHI_KNM: 6047e1069839SBorislav Petkov memcpy(hw_cache_event_ids, 6048e1069839SBorislav Petkov slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6049e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, 6050e1069839SBorislav Petkov knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6051e1069839SBorislav Petkov intel_pmu_lbr_init_knl(); 6052e1069839SBorislav Petkov 6053e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 6054e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 6055e1069839SBorislav Petkov x86_pmu.extra_regs = intel_knl_extra_regs; 6056e1069839SBorislav Petkov 6057e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 6058e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6059e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6060a5df70c3SAndi Kleen extra_attr = slm_format_attr; 6061608284bfSPiotr Luc pr_cont("Knights Landing/Mill events, "); 6062b00233b5SAndi Kleen name = "knights-landing"; 6063e1069839SBorislav Petkov break; 6064e1069839SBorislav Petkov 6065faaeff98SKan Liang case INTEL_FAM6_SKYLAKE_X: 6066faaeff98SKan Liang pmem = true; 6067df561f66SGustavo A. R. Silva fallthrough; 6068af239c44SPeter Zijlstra case INTEL_FAM6_SKYLAKE_L: 6069c66f78a6SPeter Zijlstra case INTEL_FAM6_SKYLAKE: 6070af239c44SPeter Zijlstra case INTEL_FAM6_KABYLAKE_L: 6071c66f78a6SPeter Zijlstra case INTEL_FAM6_KABYLAKE: 60729066288bSKan Liang case INTEL_FAM6_COMETLAKE_L: 60739066288bSKan Liang case INTEL_FAM6_COMETLAKE: 60749b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 6075e1069839SBorislav Petkov x86_pmu.late_ack = true; 6076e1069839SBorislav Petkov memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 6077e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 6078e1069839SBorislav Petkov intel_pmu_lbr_init_skl(); 6079e1069839SBorislav Petkov 6080a39fcae7SAndi Kleen /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 6081a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_noht = 6082a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1"; 6083a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_ht = 6084a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1,any=1"; 6085a39fcae7SAndi Kleen 6086e1069839SBorislav Petkov x86_pmu.event_constraints = intel_skl_event_constraints; 6087e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 6088e1069839SBorislav Petkov x86_pmu.extra_regs = intel_skl_extra_regs; 6089e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 6090e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 6091e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 6092e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6093e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6094e1069839SBorislav Petkov 6095e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 6096e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 6097a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6098a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 6099b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 6100baa0c833SJiri Olsa td_attr = hsw_events_attrs; 6101d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 6102d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 6103faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 6104400816f6SPeter Zijlstra (Intel) 6105ad3c2e17SPawan Gupta /* 6106ad3c2e17SPawan Gupta * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 6107ad3c2e17SPawan Gupta * TSX force abort hooks are not required on these systems. Only deploy 6108ad3c2e17SPawan Gupta * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 6109ad3c2e17SPawan Gupta */ 6110ad3c2e17SPawan Gupta if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 6111ad3c2e17SPawan Gupta !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 6112400816f6SPeter Zijlstra (Intel) x86_pmu.flags |= PMU_FL_TFA; 6113400816f6SPeter Zijlstra (Intel) x86_pmu.get_event_constraints = tfa_get_event_constraints; 6114400816f6SPeter Zijlstra (Intel) x86_pmu.enable_all = intel_tfa_pmu_enable_all; 6115400816f6SPeter Zijlstra (Intel) x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 6116400816f6SPeter Zijlstra (Intel) } 6117400816f6SPeter Zijlstra (Intel) 6118e1069839SBorislav Petkov pr_cont("Skylake events, "); 6119b00233b5SAndi Kleen name = "skylake"; 6120e1069839SBorislav Petkov break; 6121e1069839SBorislav Petkov 6122faaeff98SKan Liang case INTEL_FAM6_ICELAKE_X: 61235ebb34edSPeter Zijlstra case INTEL_FAM6_ICELAKE_D: 6124faaeff98SKan Liang pmem = true; 6125df561f66SGustavo A. R. Silva fallthrough; 6126af239c44SPeter Zijlstra case INTEL_FAM6_ICELAKE_L: 6127c66f78a6SPeter Zijlstra case INTEL_FAM6_ICELAKE: 612823645a76SKan Liang case INTEL_FAM6_TIGERLAKE_L: 612923645a76SKan Liang case INTEL_FAM6_TIGERLAKE: 6130b14d0db5SKan Liang case INTEL_FAM6_ROCKETLAKE: 613160176089SKan Liang x86_pmu.late_ack = true; 613260176089SKan Liang memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 613360176089SKan Liang memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 613460176089SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 613560176089SKan Liang intel_pmu_lbr_init_skl(); 613660176089SKan Liang 613760176089SKan Liang x86_pmu.event_constraints = intel_icl_event_constraints; 613860176089SKan Liang x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 613960176089SKan Liang x86_pmu.extra_regs = intel_icl_extra_regs; 614060176089SKan Liang x86_pmu.pebs_aliases = NULL; 614160176089SKan Liang x86_pmu.pebs_prec_dist = true; 614260176089SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 614360176089SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 614460176089SKan Liang 614560176089SKan Liang x86_pmu.hw_config = hsw_hw_config; 614660176089SKan Liang x86_pmu.get_event_constraints = icl_get_event_constraints; 614760176089SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 614860176089SKan Liang hsw_format_attr : nhm_format_attr; 6149b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 6150baa0c833SJiri Olsa mem_attr = icl_events_attrs; 615159a854e2SKan Liang td_attr = icl_td_events_attrs; 6152baa0c833SJiri Olsa tsx_attr = icl_tsx_events_attrs; 615346b72e1bSKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 615460176089SKan Liang x86_pmu.lbr_pt_coexist = true; 6155faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 61561ab5f235SKan Liang x86_pmu.num_topdown_events = 4; 615759a854e2SKan Liang x86_pmu.update_topdown_event = icl_update_topdown_event; 615859a854e2SKan Liang x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 615960176089SKan Liang pr_cont("Icelake events, "); 616060176089SKan Liang name = "icelake"; 616160176089SKan Liang break; 616260176089SKan Liang 616361b985e3SKan Liang case INTEL_FAM6_SAPPHIRERAPIDS_X: 616461b985e3SKan Liang pmem = true; 616561b985e3SKan Liang x86_pmu.late_ack = true; 616661b985e3SKan Liang memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 616761b985e3SKan Liang memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 616861b985e3SKan Liang 616961b985e3SKan Liang x86_pmu.event_constraints = intel_spr_event_constraints; 617061b985e3SKan Liang x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 617161b985e3SKan Liang x86_pmu.extra_regs = intel_spr_extra_regs; 617261b985e3SKan Liang x86_pmu.limit_period = spr_limit_period; 617361b985e3SKan Liang x86_pmu.pebs_aliases = NULL; 617461b985e3SKan Liang x86_pmu.pebs_prec_dist = true; 617561b985e3SKan Liang x86_pmu.pebs_block = true; 617661b985e3SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 617761b985e3SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 617861b985e3SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 617961b985e3SKan Liang x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 618061b985e3SKan Liang x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 618161b985e3SKan Liang 618261b985e3SKan Liang x86_pmu.hw_config = hsw_hw_config; 618361b985e3SKan Liang x86_pmu.get_event_constraints = spr_get_event_constraints; 618461b985e3SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 618561b985e3SKan Liang hsw_format_attr : nhm_format_attr; 618661b985e3SKan Liang extra_skl_attr = skl_format_attr; 618761b985e3SKan Liang mem_attr = spr_events_attrs; 618861b985e3SKan Liang td_attr = spr_td_events_attrs; 618961b985e3SKan Liang tsx_attr = spr_tsx_events_attrs; 619061b985e3SKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 619161b985e3SKan Liang x86_pmu.lbr_pt_coexist = true; 619261b985e3SKan Liang intel_pmu_pebs_data_source_skl(pmem); 619361b985e3SKan Liang x86_pmu.num_topdown_events = 8; 619461b985e3SKan Liang x86_pmu.update_topdown_event = icl_update_topdown_event; 619561b985e3SKan Liang x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 619661b985e3SKan Liang pr_cont("Sapphire Rapids events, "); 619761b985e3SKan Liang name = "sapphire_rapids"; 619861b985e3SKan Liang break; 619961b985e3SKan Liang 6200f83d2f91SKan Liang case INTEL_FAM6_ALDERLAKE: 6201f83d2f91SKan Liang case INTEL_FAM6_ALDERLAKE_L: 6202f83d2f91SKan Liang /* 6203f83d2f91SKan Liang * Alder Lake has 2 types of CPU, core and atom. 6204f83d2f91SKan Liang * 6205f83d2f91SKan Liang * Initialize the common PerfMon capabilities here. 6206f83d2f91SKan Liang */ 6207f83d2f91SKan Liang x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, 6208f83d2f91SKan Liang sizeof(struct x86_hybrid_pmu), 6209f83d2f91SKan Liang GFP_KERNEL); 6210f83d2f91SKan Liang if (!x86_pmu.hybrid_pmu) 6211f83d2f91SKan Liang return -ENOMEM; 6212f83d2f91SKan Liang static_branch_enable(&perf_is_hybrid); 6213f83d2f91SKan Liang x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; 6214f83d2f91SKan Liang 6215f83d2f91SKan Liang x86_pmu.pebs_aliases = NULL; 6216f83d2f91SKan Liang x86_pmu.pebs_prec_dist = true; 6217f83d2f91SKan Liang x86_pmu.pebs_block = true; 6218f83d2f91SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 6219f83d2f91SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 6220f83d2f91SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 6221f83d2f91SKan Liang x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 6222f83d2f91SKan Liang x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 6223f83d2f91SKan Liang x86_pmu.lbr_pt_coexist = true; 6224f83d2f91SKan Liang intel_pmu_pebs_data_source_skl(false); 6225f83d2f91SKan Liang x86_pmu.num_topdown_events = 8; 6226f83d2f91SKan Liang x86_pmu.update_topdown_event = adl_update_topdown_event; 6227f83d2f91SKan Liang x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; 6228f83d2f91SKan Liang 6229f83d2f91SKan Liang x86_pmu.filter_match = intel_pmu_filter_match; 6230f83d2f91SKan Liang x86_pmu.get_event_constraints = adl_get_event_constraints; 6231f83d2f91SKan Liang x86_pmu.hw_config = adl_hw_config; 6232f83d2f91SKan Liang x86_pmu.limit_period = spr_limit_period; 6233f83d2f91SKan Liang x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 6234f83d2f91SKan Liang /* 6235f83d2f91SKan Liang * The rtm_abort_event is used to check whether to enable GPRs 6236f83d2f91SKan Liang * for the RTM abort event. Atom doesn't have the RTM abort 6237f83d2f91SKan Liang * event. There is no harmful to set it in the common 6238f83d2f91SKan Liang * x86_pmu.rtm_abort_event. 6239f83d2f91SKan Liang */ 6240f83d2f91SKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 6241f83d2f91SKan Liang 6242f83d2f91SKan Liang td_attr = adl_hybrid_events_attrs; 6243f83d2f91SKan Liang mem_attr = adl_hybrid_mem_attrs; 6244f83d2f91SKan Liang tsx_attr = adl_hybrid_tsx_attrs; 6245f83d2f91SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 6246f83d2f91SKan Liang adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 6247f83d2f91SKan Liang 6248f83d2f91SKan Liang /* Initialize big core specific PerfMon capabilities.*/ 6249f83d2f91SKan Liang pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 6250f83d2f91SKan Liang pmu->name = "cpu_core"; 6251f83d2f91SKan Liang pmu->cpu_type = hybrid_big; 6252acade637SKan Liang pmu->late_ack = true; 6253ee72a94eSKan Liang if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 6254f83d2f91SKan Liang pmu->num_counters = x86_pmu.num_counters + 2; 6255f83d2f91SKan Liang pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; 6256ee72a94eSKan Liang } else { 6257ee72a94eSKan Liang pmu->num_counters = x86_pmu.num_counters; 6258ee72a94eSKan Liang pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6259ee72a94eSKan Liang } 62607fa981caSKan Liang 62617fa981caSKan Liang /* 62627fa981caSKan Liang * Quirk: For some Alder Lake machine, when all E-cores are disabled in 62637fa981caSKan Liang * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 62647fa981caSKan Liang * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 62657fa981caSKan Liang * mistakenly add extra counters for P-cores. Correct the number of 62667fa981caSKan Liang * counters here. 62677fa981caSKan Liang */ 62687fa981caSKan Liang if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) { 62697fa981caSKan Liang pmu->num_counters = x86_pmu.num_counters; 62707fa981caSKan Liang pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 62717fa981caSKan Liang } 62727fa981caSKan Liang 6273f83d2f91SKan Liang pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); 6274f83d2f91SKan Liang pmu->unconstrained = (struct event_constraint) 6275f83d2f91SKan Liang __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6276f83d2f91SKan Liang 0, pmu->num_counters, 0, 0); 6277f83d2f91SKan Liang pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6278f83d2f91SKan Liang pmu->intel_cap.perf_metrics = 1; 6279f83d2f91SKan Liang pmu->intel_cap.pebs_output_pt_available = 0; 6280f83d2f91SKan Liang 6281f83d2f91SKan Liang memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6282f83d2f91SKan Liang memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6283f83d2f91SKan Liang pmu->event_constraints = intel_spr_event_constraints; 6284f83d2f91SKan Liang pmu->pebs_constraints = intel_spr_pebs_event_constraints; 6285f83d2f91SKan Liang pmu->extra_regs = intel_spr_extra_regs; 6286f83d2f91SKan Liang 6287f83d2f91SKan Liang /* Initialize Atom core specific PerfMon capabilities.*/ 6288f83d2f91SKan Liang pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 6289f83d2f91SKan Liang pmu->name = "cpu_atom"; 6290f83d2f91SKan Liang pmu->cpu_type = hybrid_small; 6291acade637SKan Liang pmu->mid_ack = true; 6292f83d2f91SKan Liang pmu->num_counters = x86_pmu.num_counters; 6293f83d2f91SKan Liang pmu->num_counters_fixed = x86_pmu.num_counters_fixed; 6294f83d2f91SKan Liang pmu->max_pebs_events = x86_pmu.max_pebs_events; 6295f83d2f91SKan Liang pmu->unconstrained = (struct event_constraint) 6296f83d2f91SKan Liang __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, 6297f83d2f91SKan Liang 0, pmu->num_counters, 0, 0); 6298f83d2f91SKan Liang pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6299f83d2f91SKan Liang pmu->intel_cap.perf_metrics = 0; 6300f83d2f91SKan Liang pmu->intel_cap.pebs_output_pt_available = 1; 6301f83d2f91SKan Liang 6302f83d2f91SKan Liang memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); 6303f83d2f91SKan Liang memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); 6304f83d2f91SKan Liang pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 6305f83d2f91SKan Liang pmu->event_constraints = intel_slm_event_constraints; 6306f83d2f91SKan Liang pmu->pebs_constraints = intel_grt_pebs_event_constraints; 6307f83d2f91SKan Liang pmu->extra_regs = intel_grt_extra_regs; 6308f83d2f91SKan Liang pr_cont("Alderlake Hybrid events, "); 6309f83d2f91SKan Liang name = "alderlake_hybrid"; 6310f83d2f91SKan Liang break; 6311f83d2f91SKan Liang 6312e1069839SBorislav Petkov default: 6313e1069839SBorislav Petkov switch (x86_pmu.version) { 6314e1069839SBorislav Petkov case 1: 6315e1069839SBorislav Petkov x86_pmu.event_constraints = intel_v1_event_constraints; 6316e1069839SBorislav Petkov pr_cont("generic architected perfmon v1, "); 6317b00233b5SAndi Kleen name = "generic_arch_v1"; 6318e1069839SBorislav Petkov break; 6319*ee28855aSKan Liang case 2: 6320*ee28855aSKan Liang case 3: 6321*ee28855aSKan Liang case 4: 6322e1069839SBorislav Petkov /* 6323e1069839SBorislav Petkov * default constraints for v2 and up 6324e1069839SBorislav Petkov */ 6325e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 6326e1069839SBorislav Petkov pr_cont("generic architected perfmon, "); 6327b00233b5SAndi Kleen name = "generic_arch_v2+"; 6328e1069839SBorislav Petkov break; 6329*ee28855aSKan Liang default: 6330*ee28855aSKan Liang /* 6331*ee28855aSKan Liang * The default constraints for v5 and up can support up to 6332*ee28855aSKan Liang * 16 fixed counters. For the fixed counters 4 and later, 6333*ee28855aSKan Liang * the pseudo-encoding is applied. 6334*ee28855aSKan Liang * The constraints may be cut according to the CPUID enumeration 6335*ee28855aSKan Liang * by inserting the EVENT_CONSTRAINT_END. 6336*ee28855aSKan Liang */ 6337*ee28855aSKan Liang if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) 6338*ee28855aSKan Liang x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 6339*ee28855aSKan Liang intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1; 6340*ee28855aSKan Liang x86_pmu.event_constraints = intel_v5_gen_event_constraints; 6341*ee28855aSKan Liang pr_cont("generic architected perfmon, "); 6342*ee28855aSKan Liang name = "generic_arch_v5+"; 6343*ee28855aSKan Liang break; 6344e1069839SBorislav Petkov } 6345e1069839SBorislav Petkov } 6346e1069839SBorislav Petkov 63470e96f31eSJordan Borgner snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 6348b00233b5SAndi Kleen 634958ae30c2SKan Liang if (!is_hybrid()) { 6350baa0c833SJiri Olsa group_events_td.attrs = td_attr; 6351baa0c833SJiri Olsa group_events_mem.attrs = mem_attr; 6352baa0c833SJiri Olsa group_events_tsx.attrs = tsx_attr; 63533ea40ac7SJiri Olsa group_format_extra.attrs = extra_attr; 6354b6576880SJiri Olsa group_format_extra_skl.attrs = extra_skl_attr; 6355baa0c833SJiri Olsa 6356baa0c833SJiri Olsa x86_pmu.attr_update = attr_update; 635758ae30c2SKan Liang } else { 635858ae30c2SKan Liang hybrid_group_events_td.attrs = td_attr; 635958ae30c2SKan Liang hybrid_group_events_mem.attrs = mem_attr; 636058ae30c2SKan Liang hybrid_group_events_tsx.attrs = tsx_attr; 636158ae30c2SKan Liang hybrid_group_format_extra.attrs = extra_attr; 6362d4ae5529SJiri Olsa 636358ae30c2SKan Liang x86_pmu.attr_update = hybrid_attr_update; 6364e1069839SBorislav Petkov } 6365e1069839SBorislav Petkov 6366b8c4d1a8SKan Liang intel_pmu_check_num_counters(&x86_pmu.num_counters, 6367b8c4d1a8SKan Liang &x86_pmu.num_counters_fixed, 6368b8c4d1a8SKan Liang &x86_pmu.intel_ctrl, 6369b8c4d1a8SKan Liang (u64)fixed_mask); 6370e1069839SBorislav Petkov 6371cadbaa03SStephane Eranian /* AnyThread may be deprecated on arch perfmon v5 or later */ 6372cadbaa03SStephane Eranian if (x86_pmu.intel_cap.anythread_deprecated) 6373cadbaa03SStephane Eranian x86_pmu.format_attrs = intel_arch_formats_attr; 6374cadbaa03SStephane Eranian 6375bc14fe1bSKan Liang intel_pmu_check_event_constraints(x86_pmu.event_constraints, 6376bc14fe1bSKan Liang x86_pmu.num_counters, 6377bc14fe1bSKan Liang x86_pmu.num_counters_fixed, 6378bc14fe1bSKan Liang x86_pmu.intel_ctrl); 6379e1069839SBorislav Petkov /* 6380e1069839SBorislav Petkov * Access LBR MSR may cause #GP under certain circumstances. 6381e1069839SBorislav Petkov * E.g. KVM doesn't support LBR MSR 6382e1069839SBorislav Petkov * Check all LBT MSR here. 6383e1069839SBorislav Petkov * Disable LBR access if any LBR MSRs can not be accessed. 6384e1069839SBorislav Petkov */ 63853317c26aSLike Xu if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 6386e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 6387e1069839SBorislav Petkov for (i = 0; i < x86_pmu.lbr_nr; i++) { 6388e1069839SBorislav Petkov if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 6389e1069839SBorislav Petkov check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 6390e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 6391e1069839SBorislav Petkov } 6392e1069839SBorislav Petkov 6393c22ac2a3SSong Liu if (x86_pmu.lbr_nr) { 63941ac7fd81SPeter Zijlstra (Intel) intel_pmu_lbr_init(); 63951ac7fd81SPeter Zijlstra (Intel) 6396f09509b9SDavid Carrillo-Cisneros pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 6397b00233b5SAndi Kleen 6398c22ac2a3SSong Liu /* only support branch_stack snapshot for perfmon >= v2 */ 6399c22ac2a3SSong Liu if (x86_pmu.disable_all == intel_pmu_disable_all) { 6400c22ac2a3SSong Liu if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 6401c22ac2a3SSong Liu static_call_update(perf_snapshot_branch_stack, 6402c22ac2a3SSong Liu intel_pmu_snapshot_arch_branch_stack); 6403c22ac2a3SSong Liu } else { 6404c22ac2a3SSong Liu static_call_update(perf_snapshot_branch_stack, 6405c22ac2a3SSong Liu intel_pmu_snapshot_branch_stack); 6406c22ac2a3SSong Liu } 6407c22ac2a3SSong Liu } 6408c22ac2a3SSong Liu } 6409c22ac2a3SSong Liu 641034d5b61fSKan Liang intel_pmu_check_extra_regs(x86_pmu.extra_regs); 6411e1069839SBorislav Petkov 6412e1069839SBorislav Petkov /* Support full width counters using alternative MSR range */ 6413e1069839SBorislav Petkov if (x86_pmu.intel_cap.full_width_write) { 64147f612a7fSPeter Zijlstra (Intel) x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 6415e1069839SBorislav Petkov x86_pmu.perfctr = MSR_IA32_PMC0; 6416e1069839SBorislav Petkov pr_cont("full-width counters, "); 6417e1069839SBorislav Petkov } 6418e1069839SBorislav Petkov 6419d0946a88SKan Liang if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 642059a854e2SKan Liang x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 642159a854e2SKan Liang 6422d9977c43SKan Liang if (is_hybrid()) 6423d9977c43SKan Liang intel_pmu_check_hybrid_pmus((u64)fixed_mask); 6424d9977c43SKan Liang 64258b8ff8ccSAdrian Hunter intel_aux_output_init(); 64268b8ff8ccSAdrian Hunter 6427e1069839SBorislav Petkov return 0; 6428e1069839SBorislav Petkov } 6429e1069839SBorislav Petkov 6430e1069839SBorislav Petkov /* 6431e1069839SBorislav Petkov * HT bug: phase 2 init 6432e1069839SBorislav Petkov * Called once we have valid topology information to check 6433e1069839SBorislav Petkov * whether or not HT is enabled 6434e1069839SBorislav Petkov * If HT is off, then we disable the workaround 6435e1069839SBorislav Petkov */ 6436e1069839SBorislav Petkov static __init int fixup_ht_bug(void) 6437e1069839SBorislav Petkov { 6438030ba6cdSAndi Kleen int c; 6439e1069839SBorislav Petkov /* 6440e1069839SBorislav Petkov * problem not present on this CPU model, nothing to do 6441e1069839SBorislav Petkov */ 6442e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 6443e1069839SBorislav Petkov return 0; 6444e1069839SBorislav Petkov 6445030ba6cdSAndi Kleen if (topology_max_smt_threads() > 1) { 6446e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 6447e1069839SBorislav Petkov return 0; 6448e1069839SBorislav Petkov } 6449e1069839SBorislav Petkov 64502406e3b1SPeter Zijlstra cpus_read_lock(); 64512406e3b1SPeter Zijlstra 64522406e3b1SPeter Zijlstra hardlockup_detector_perf_stop(); 6453e1069839SBorislav Petkov 6454e1069839SBorislav Petkov x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 6455e1069839SBorislav Petkov 6456e1069839SBorislav Petkov x86_pmu.start_scheduling = NULL; 6457e1069839SBorislav Petkov x86_pmu.commit_scheduling = NULL; 6458e1069839SBorislav Petkov x86_pmu.stop_scheduling = NULL; 6459e1069839SBorislav Petkov 64602406e3b1SPeter Zijlstra hardlockup_detector_perf_restart(); 6461e1069839SBorislav Petkov 64621ba143a5SSebastian Andrzej Siewior for_each_online_cpu(c) 6463d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 6464e1069839SBorislav Petkov 64651ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 6466e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 6467e1069839SBorislav Petkov return 0; 6468e1069839SBorislav Petkov } 6469e1069839SBorislav Petkov subsys_initcall(fixup_ht_bug) 6470