1e1069839SBorislav Petkov /* 2e1069839SBorislav Petkov * Per core/cpu state 3e1069839SBorislav Petkov * 4e1069839SBorislav Petkov * Used to coordinate shared registers between HT threads or 5e1069839SBorislav Petkov * among events on a single PMU. 6e1069839SBorislav Petkov */ 7e1069839SBorislav Petkov 8e1069839SBorislav Petkov #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9e1069839SBorislav Petkov 10e1069839SBorislav Petkov #include <linux/stddef.h> 11e1069839SBorislav Petkov #include <linux/types.h> 12e1069839SBorislav Petkov #include <linux/init.h> 13e1069839SBorislav Petkov #include <linux/slab.h> 14e1069839SBorislav Petkov #include <linux/export.h> 15e1069839SBorislav Petkov #include <linux/nmi.h> 16e1069839SBorislav Petkov 17e1069839SBorislav Petkov #include <asm/cpufeature.h> 18e1069839SBorislav Petkov #include <asm/hardirq.h> 19ef5f9f47SDave Hansen #include <asm/intel-family.h> 20e1069839SBorislav Petkov #include <asm/apic.h> 219b545c04SAndi Kleen #include <asm/cpu_device_id.h> 22e1069839SBorislav Petkov 2327f6d22bSBorislav Petkov #include "../perf_event.h" 24e1069839SBorislav Petkov 25e1069839SBorislav Petkov /* 26e1069839SBorislav Petkov * Intel PerfMon, used on Core and later. 27e1069839SBorislav Petkov */ 28e1069839SBorislav Petkov static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 29e1069839SBorislav Petkov { 30e1069839SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 31e1069839SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 32e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 33e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 34e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 35e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 36e1069839SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 37e1069839SBorislav Petkov [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 38e1069839SBorislav Petkov }; 39e1069839SBorislav Petkov 40e1069839SBorislav Petkov static struct event_constraint intel_core_event_constraints[] __read_mostly = 41e1069839SBorislav Petkov { 42e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 43e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 44e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 45e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 46e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 47e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 48e1069839SBorislav Petkov EVENT_CONSTRAINT_END 49e1069839SBorislav Petkov }; 50e1069839SBorislav Petkov 51e1069839SBorislav Petkov static struct event_constraint intel_core2_event_constraints[] __read_mostly = 52e1069839SBorislav Petkov { 53e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 54e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 55e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 56e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 57e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 58e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 59e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 60e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 61e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 62e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 63e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 64e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 65e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 66e1069839SBorislav Petkov EVENT_CONSTRAINT_END 67e1069839SBorislav Petkov }; 68e1069839SBorislav Petkov 69e1069839SBorislav Petkov static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 70e1069839SBorislav Petkov { 71e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 72e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 73e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 74e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 75e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 76e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 77e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 78e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 79e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 80e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 81e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 82e1069839SBorislav Petkov EVENT_CONSTRAINT_END 83e1069839SBorislav Petkov }; 84e1069839SBorislav Petkov 85e1069839SBorislav Petkov static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 86e1069839SBorislav Petkov { 87e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 88e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 89e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 90e1069839SBorislav Petkov EVENT_EXTRA_END 91e1069839SBorislav Petkov }; 92e1069839SBorislav Petkov 93e1069839SBorislav Petkov static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 94e1069839SBorislav Petkov { 95e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 96e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 97e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 98e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 99e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 100e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 101e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 102e1069839SBorislav Petkov EVENT_CONSTRAINT_END 103e1069839SBorislav Petkov }; 104e1069839SBorislav Petkov 105e1069839SBorislav Petkov static struct event_constraint intel_snb_event_constraints[] __read_mostly = 106e1069839SBorislav Petkov { 107e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 108e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 109e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 110e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 111e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 112e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 113e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 114e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 115e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 116e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 117e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 118e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 119e1069839SBorislav Petkov 1209010ae4aSStephane Eranian /* 1219010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1229010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1239010ae4aSStephane Eranian */ 124e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 125e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 126e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 127e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 128e1069839SBorislav Petkov 129e1069839SBorislav Petkov EVENT_CONSTRAINT_END 130e1069839SBorislav Petkov }; 131e1069839SBorislav Petkov 132e1069839SBorislav Petkov static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 133e1069839SBorislav Petkov { 134e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 135e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 136e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 137e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 138e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 139e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 140e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 141e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 142e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 143e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 144e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 145e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 146e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 147e1069839SBorislav Petkov 1489010ae4aSStephane Eranian /* 1499010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1509010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1519010ae4aSStephane Eranian */ 152e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 153e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 154e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 155e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 156e1069839SBorislav Petkov 157e1069839SBorislav Petkov EVENT_CONSTRAINT_END 158e1069839SBorislav Petkov }; 159e1069839SBorislav Petkov 160e1069839SBorislav Petkov static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 161e1069839SBorislav Petkov { 162e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 163e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 164e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 165e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 166e1069839SBorislav Petkov EVENT_EXTRA_END 167e1069839SBorislav Petkov }; 168e1069839SBorislav Petkov 169e1069839SBorislav Petkov static struct event_constraint intel_v1_event_constraints[] __read_mostly = 170e1069839SBorislav Petkov { 171e1069839SBorislav Petkov EVENT_CONSTRAINT_END 172e1069839SBorislav Petkov }; 173e1069839SBorislav Petkov 174e1069839SBorislav Petkov static struct event_constraint intel_gen_event_constraints[] __read_mostly = 175e1069839SBorislav Petkov { 176e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 177e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 178e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 179e1069839SBorislav Petkov EVENT_CONSTRAINT_END 180e1069839SBorislav Petkov }; 181e1069839SBorislav Petkov 182e1069839SBorislav Petkov static struct event_constraint intel_slm_event_constraints[] __read_mostly = 183e1069839SBorislav Petkov { 184e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 185e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 186e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 187e1069839SBorislav Petkov EVENT_CONSTRAINT_END 188e1069839SBorislav Petkov }; 189e1069839SBorislav Petkov 19020f36278SLukasz Odzioba static struct event_constraint intel_skl_event_constraints[] = { 191e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 192e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 193e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 194e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1959010ae4aSStephane Eranian 1969010ae4aSStephane Eranian /* 1979010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 1989010ae4aSStephane Eranian */ 1999010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 2009010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 2019010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 2029010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 2039010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 2049010ae4aSStephane Eranian 205e1069839SBorislav Petkov EVENT_CONSTRAINT_END 206e1069839SBorislav Petkov }; 207e1069839SBorislav Petkov 208e1069839SBorislav Petkov static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 2099c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 2109c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 211e1069839SBorislav Petkov EVENT_EXTRA_END 212e1069839SBorislav Petkov }; 213e1069839SBorislav Petkov 214e1069839SBorislav Petkov static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 215e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 216e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 217e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 218e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 219e1069839SBorislav Petkov EVENT_EXTRA_END 220e1069839SBorislav Petkov }; 221e1069839SBorislav Petkov 222e1069839SBorislav Petkov static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 223e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 224e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 225e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 226e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 227e1069839SBorislav Petkov EVENT_EXTRA_END 228e1069839SBorislav Petkov }; 229e1069839SBorislav Petkov 230e1069839SBorislav Petkov static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 231e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 232e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 233e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 234e1069839SBorislav Petkov /* 235e1069839SBorislav Petkov * Note the low 8 bits eventsel code is not a continuous field, containing 236e1069839SBorislav Petkov * some #GPing bits. These are masked out. 237e1069839SBorislav Petkov */ 238e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 239e1069839SBorislav Petkov EVENT_EXTRA_END 240e1069839SBorislav Petkov }; 241e1069839SBorislav Petkov 242e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 243e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 244e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 245e1069839SBorislav Petkov 246d4ae5529SJiri Olsa static struct attribute *nhm_mem_events_attrs[] = { 247e1069839SBorislav Petkov EVENT_PTR(mem_ld_nhm), 248e1069839SBorislav Petkov NULL, 249e1069839SBorislav Petkov }; 250e1069839SBorislav Petkov 251a39fcae7SAndi Kleen /* 252a39fcae7SAndi Kleen * topdown events for Intel Core CPUs. 253a39fcae7SAndi Kleen * 254a39fcae7SAndi Kleen * The events are all in slots, which is a free slot in a 4 wide 255a39fcae7SAndi Kleen * pipeline. Some events are already reported in slots, for cycle 256a39fcae7SAndi Kleen * events we multiply by the pipeline width (4). 257a39fcae7SAndi Kleen * 258a39fcae7SAndi Kleen * With Hyper Threading on, topdown metrics are either summed or averaged 259a39fcae7SAndi Kleen * between the threads of a core: (count_t0 + count_t1). 260a39fcae7SAndi Kleen * 261a39fcae7SAndi Kleen * For the average case the metric is always scaled to pipeline width, 262a39fcae7SAndi Kleen * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 263a39fcae7SAndi Kleen */ 264a39fcae7SAndi Kleen 265a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 266a39fcae7SAndi Kleen "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 267a39fcae7SAndi Kleen "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 268a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 269a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 270a39fcae7SAndi Kleen "event=0xe,umask=0x1"); /* uops_issued.any */ 271a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 272a39fcae7SAndi Kleen "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 273a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 274a39fcae7SAndi Kleen "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 275a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 276a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 277a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 278a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 279a39fcae7SAndi Kleen "4", "2"); 280a39fcae7SAndi Kleen 28120f36278SLukasz Odzioba static struct attribute *snb_events_attrs[] = { 282a39fcae7SAndi Kleen EVENT_PTR(td_slots_issued), 283a39fcae7SAndi Kleen EVENT_PTR(td_slots_retired), 284a39fcae7SAndi Kleen EVENT_PTR(td_fetch_bubbles), 285a39fcae7SAndi Kleen EVENT_PTR(td_total_slots), 286a39fcae7SAndi Kleen EVENT_PTR(td_total_slots_scale), 287a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles), 288a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 289e1069839SBorislav Petkov NULL, 290e1069839SBorislav Petkov }; 291e1069839SBorislav Petkov 292d4ae5529SJiri Olsa static struct attribute *snb_mem_events_attrs[] = { 293d4ae5529SJiri Olsa EVENT_PTR(mem_ld_snb), 294d4ae5529SJiri Olsa EVENT_PTR(mem_st_snb), 295d4ae5529SJiri Olsa NULL, 296d4ae5529SJiri Olsa }; 297d4ae5529SJiri Olsa 298e1069839SBorislav Petkov static struct event_constraint intel_hsw_event_constraints[] = { 299e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 300e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 301e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 302e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 303e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 304e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 305e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 306e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 307e1069839SBorislav Petkov /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 308e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 309e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 310e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 311e1069839SBorislav Petkov 3129010ae4aSStephane Eranian /* 3139010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 3149010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 3159010ae4aSStephane Eranian */ 316e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 317e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 318e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 319e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 320e1069839SBorislav Petkov 321e1069839SBorislav Petkov EVENT_CONSTRAINT_END 322e1069839SBorislav Petkov }; 323e1069839SBorislav Petkov 32420f36278SLukasz Odzioba static struct event_constraint intel_bdw_event_constraints[] = { 325e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 326e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 327e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 328e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 329e1069839SBorislav Petkov INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 3309010ae4aSStephane Eranian /* 3319010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 3329010ae4aSStephane Eranian */ 3339010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 3349010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 3359010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 3369010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 337e1069839SBorislav Petkov EVENT_CONSTRAINT_END 338e1069839SBorislav Petkov }; 339e1069839SBorislav Petkov 340e1069839SBorislav Petkov static u64 intel_pmu_event_map(int hw_event) 341e1069839SBorislav Petkov { 342e1069839SBorislav Petkov return intel_perfmon_event_map[hw_event]; 343e1069839SBorislav Petkov } 344e1069839SBorislav Petkov 345e1069839SBorislav Petkov /* 346e1069839SBorislav Petkov * Notes on the events: 347e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 348e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 349e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 350e1069839SBorislav Petkov * - prefetches are not included in the counts. 351e1069839SBorislav Petkov * - icache miss does not include decoded icache 352e1069839SBorislav Petkov */ 353e1069839SBorislav Petkov 354e1069839SBorislav Petkov #define SKL_DEMAND_DATA_RD BIT_ULL(0) 355e1069839SBorislav Petkov #define SKL_DEMAND_RFO BIT_ULL(1) 356e1069839SBorislav Petkov #define SKL_ANY_RESPONSE BIT_ULL(16) 357e1069839SBorislav Petkov #define SKL_SUPPLIER_NONE BIT_ULL(17) 358e1069839SBorislav Petkov #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 359e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 360e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 361e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 362e1069839SBorislav Petkov #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 363e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 364e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 365e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 366e1069839SBorislav Petkov #define SKL_SPL_HIT BIT_ULL(30) 367e1069839SBorislav Petkov #define SKL_SNOOP_NONE BIT_ULL(31) 368e1069839SBorislav Petkov #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 369e1069839SBorislav Petkov #define SKL_SNOOP_MISS BIT_ULL(33) 370e1069839SBorislav Petkov #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 371e1069839SBorislav Petkov #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 372e1069839SBorislav Petkov #define SKL_SNOOP_HITM BIT_ULL(36) 373e1069839SBorislav Petkov #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 374e1069839SBorislav Petkov #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 375e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 376e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 377e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 378e1069839SBorislav Petkov #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 379e1069839SBorislav Petkov #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 380e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 381e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 382e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SPL_HIT) 383e1069839SBorislav Petkov #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 384e1069839SBorislav Petkov #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 385e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 386e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 387e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 388e1069839SBorislav Petkov 389e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_event_ids 390e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 391e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 392e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 393e1069839SBorislav Petkov { 394e1069839SBorislav Petkov [ C(L1D ) ] = { 395e1069839SBorislav Petkov [ C(OP_READ) ] = { 396e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 397e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 398e1069839SBorislav Petkov }, 399e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 400e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 401e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 402e1069839SBorislav Petkov }, 403e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 404e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 405e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 406e1069839SBorislav Petkov }, 407e1069839SBorislav Petkov }, 408e1069839SBorislav Petkov [ C(L1I ) ] = { 409e1069839SBorislav Petkov [ C(OP_READ) ] = { 410e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 411e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 412e1069839SBorislav Petkov }, 413e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 414e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 415e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 416e1069839SBorislav Petkov }, 417e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 418e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 419e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 420e1069839SBorislav Petkov }, 421e1069839SBorislav Petkov }, 422e1069839SBorislav Petkov [ C(LL ) ] = { 423e1069839SBorislav Petkov [ C(OP_READ) ] = { 424e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 425e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 426e1069839SBorislav Petkov }, 427e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 428e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 429e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 430e1069839SBorislav Petkov }, 431e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 432e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 433e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 434e1069839SBorislav Petkov }, 435e1069839SBorislav Petkov }, 436e1069839SBorislav Petkov [ C(DTLB) ] = { 437e1069839SBorislav Petkov [ C(OP_READ) ] = { 438e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 439fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 440e1069839SBorislav Petkov }, 441e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 442e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 443fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 444e1069839SBorislav Petkov }, 445e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 446e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 447e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 448e1069839SBorislav Petkov }, 449e1069839SBorislav Petkov }, 450e1069839SBorislav Petkov [ C(ITLB) ] = { 451e1069839SBorislav Petkov [ C(OP_READ) ] = { 452e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 453e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 454e1069839SBorislav Petkov }, 455e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 456e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 457e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 458e1069839SBorislav Petkov }, 459e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 460e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 461e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 462e1069839SBorislav Petkov }, 463e1069839SBorislav Petkov }, 464e1069839SBorislav Petkov [ C(BPU ) ] = { 465e1069839SBorislav Petkov [ C(OP_READ) ] = { 466e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 467e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 468e1069839SBorislav Petkov }, 469e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 470e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 471e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 472e1069839SBorislav Petkov }, 473e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 474e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 475e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 476e1069839SBorislav Petkov }, 477e1069839SBorislav Petkov }, 478e1069839SBorislav Petkov [ C(NODE) ] = { 479e1069839SBorislav Petkov [ C(OP_READ) ] = { 480e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 481e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 482e1069839SBorislav Petkov }, 483e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 484e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 485e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 486e1069839SBorislav Petkov }, 487e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 488e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 489e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 490e1069839SBorislav Petkov }, 491e1069839SBorislav Petkov }, 492e1069839SBorislav Petkov }; 493e1069839SBorislav Petkov 494e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_extra_regs 495e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 496e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 497e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 498e1069839SBorislav Petkov { 499e1069839SBorislav Petkov [ C(LL ) ] = { 500e1069839SBorislav Petkov [ C(OP_READ) ] = { 501e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 502e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 503e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 504e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 505e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 506e1069839SBorislav Petkov }, 507e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 508e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 509e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 510e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 511e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 512e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 513e1069839SBorislav Petkov }, 514e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 515e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 516e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 517e1069839SBorislav Petkov }, 518e1069839SBorislav Petkov }, 519e1069839SBorislav Petkov [ C(NODE) ] = { 520e1069839SBorislav Petkov [ C(OP_READ) ] = { 521e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 522e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 523e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 524e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 525e1069839SBorislav Petkov }, 526e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 527e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 528e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 529e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 530e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 531e1069839SBorislav Petkov }, 532e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 533e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 534e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 535e1069839SBorislav Petkov }, 536e1069839SBorislav Petkov }, 537e1069839SBorislav Petkov }; 538e1069839SBorislav Petkov 539e1069839SBorislav Petkov #define SNB_DMND_DATA_RD (1ULL << 0) 540e1069839SBorislav Petkov #define SNB_DMND_RFO (1ULL << 1) 541e1069839SBorislav Petkov #define SNB_DMND_IFETCH (1ULL << 2) 542e1069839SBorislav Petkov #define SNB_DMND_WB (1ULL << 3) 543e1069839SBorislav Petkov #define SNB_PF_DATA_RD (1ULL << 4) 544e1069839SBorislav Petkov #define SNB_PF_RFO (1ULL << 5) 545e1069839SBorislav Petkov #define SNB_PF_IFETCH (1ULL << 6) 546e1069839SBorislav Petkov #define SNB_LLC_DATA_RD (1ULL << 7) 547e1069839SBorislav Petkov #define SNB_LLC_RFO (1ULL << 8) 548e1069839SBorislav Petkov #define SNB_LLC_IFETCH (1ULL << 9) 549e1069839SBorislav Petkov #define SNB_BUS_LOCKS (1ULL << 10) 550e1069839SBorislav Petkov #define SNB_STRM_ST (1ULL << 11) 551e1069839SBorislav Petkov #define SNB_OTHER (1ULL << 15) 552e1069839SBorislav Petkov #define SNB_RESP_ANY (1ULL << 16) 553e1069839SBorislav Petkov #define SNB_NO_SUPP (1ULL << 17) 554e1069839SBorislav Petkov #define SNB_LLC_HITM (1ULL << 18) 555e1069839SBorislav Petkov #define SNB_LLC_HITE (1ULL << 19) 556e1069839SBorislav Petkov #define SNB_LLC_HITS (1ULL << 20) 557e1069839SBorislav Petkov #define SNB_LLC_HITF (1ULL << 21) 558e1069839SBorislav Petkov #define SNB_LOCAL (1ULL << 22) 559e1069839SBorislav Petkov #define SNB_REMOTE (0xffULL << 23) 560e1069839SBorislav Petkov #define SNB_SNP_NONE (1ULL << 31) 561e1069839SBorislav Petkov #define SNB_SNP_NOT_NEEDED (1ULL << 32) 562e1069839SBorislav Petkov #define SNB_SNP_MISS (1ULL << 33) 563e1069839SBorislav Petkov #define SNB_NO_FWD (1ULL << 34) 564e1069839SBorislav Petkov #define SNB_SNP_FWD (1ULL << 35) 565e1069839SBorislav Petkov #define SNB_HITM (1ULL << 36) 566e1069839SBorislav Petkov #define SNB_NON_DRAM (1ULL << 37) 567e1069839SBorislav Petkov 568e1069839SBorislav Petkov #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 569e1069839SBorislav Petkov #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 570e1069839SBorislav Petkov #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 571e1069839SBorislav Petkov 572e1069839SBorislav Petkov #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 573e1069839SBorislav Petkov SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 574e1069839SBorislav Petkov SNB_HITM) 575e1069839SBorislav Petkov 576e1069839SBorislav Petkov #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 577e1069839SBorislav Petkov #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 578e1069839SBorislav Petkov 579e1069839SBorislav Petkov #define SNB_L3_ACCESS SNB_RESP_ANY 580e1069839SBorislav Petkov #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 581e1069839SBorislav Petkov 582e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_extra_regs 583e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 584e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 585e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 586e1069839SBorislav Petkov { 587e1069839SBorislav Petkov [ C(LL ) ] = { 588e1069839SBorislav Petkov [ C(OP_READ) ] = { 589e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 590e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 591e1069839SBorislav Petkov }, 592e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 593e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 594e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 595e1069839SBorislav Petkov }, 596e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 597e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 598e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 599e1069839SBorislav Petkov }, 600e1069839SBorislav Petkov }, 601e1069839SBorislav Petkov [ C(NODE) ] = { 602e1069839SBorislav Petkov [ C(OP_READ) ] = { 603e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 604e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 605e1069839SBorislav Petkov }, 606e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 607e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 608e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 609e1069839SBorislav Petkov }, 610e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 611e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 612e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 613e1069839SBorislav Petkov }, 614e1069839SBorislav Petkov }, 615e1069839SBorislav Petkov }; 616e1069839SBorislav Petkov 617e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_event_ids 618e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 619e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 620e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 621e1069839SBorislav Petkov { 622e1069839SBorislav Petkov [ C(L1D) ] = { 623e1069839SBorislav Petkov [ C(OP_READ) ] = { 624e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 625e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 626e1069839SBorislav Petkov }, 627e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 628e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 629e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 630e1069839SBorislav Petkov }, 631e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 632e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 633e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 634e1069839SBorislav Petkov }, 635e1069839SBorislav Petkov }, 636e1069839SBorislav Petkov [ C(L1I ) ] = { 637e1069839SBorislav Petkov [ C(OP_READ) ] = { 638e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 639e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 640e1069839SBorislav Petkov }, 641e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 642e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 643e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 644e1069839SBorislav Petkov }, 645e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 646e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 647e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 648e1069839SBorislav Petkov }, 649e1069839SBorislav Petkov }, 650e1069839SBorislav Petkov [ C(LL ) ] = { 651e1069839SBorislav Petkov [ C(OP_READ) ] = { 652e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 653e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 654e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 655e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 656e1069839SBorislav Petkov }, 657e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 658e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 659e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 660e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 661e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 662e1069839SBorislav Petkov }, 663e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 664e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 665e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 666e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 667e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 668e1069839SBorislav Petkov }, 669e1069839SBorislav Petkov }, 670e1069839SBorislav Petkov [ C(DTLB) ] = { 671e1069839SBorislav Petkov [ C(OP_READ) ] = { 672e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 673e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 674e1069839SBorislav Petkov }, 675e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 676e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 677e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 678e1069839SBorislav Petkov }, 679e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 680e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 681e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 682e1069839SBorislav Petkov }, 683e1069839SBorislav Petkov }, 684e1069839SBorislav Petkov [ C(ITLB) ] = { 685e1069839SBorislav Petkov [ C(OP_READ) ] = { 686e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 687e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 688e1069839SBorislav Petkov }, 689e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 690e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 691e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 692e1069839SBorislav Petkov }, 693e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 694e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 695e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 696e1069839SBorislav Petkov }, 697e1069839SBorislav Petkov }, 698e1069839SBorislav Petkov [ C(BPU ) ] = { 699e1069839SBorislav Petkov [ C(OP_READ) ] = { 700e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 701e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 702e1069839SBorislav Petkov }, 703e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 704e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 705e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 706e1069839SBorislav Petkov }, 707e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 708e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 709e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 710e1069839SBorislav Petkov }, 711e1069839SBorislav Petkov }, 712e1069839SBorislav Petkov [ C(NODE) ] = { 713e1069839SBorislav Petkov [ C(OP_READ) ] = { 714e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 715e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 716e1069839SBorislav Petkov }, 717e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 718e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 719e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 720e1069839SBorislav Petkov }, 721e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 722e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 723e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 724e1069839SBorislav Petkov }, 725e1069839SBorislav Petkov }, 726e1069839SBorislav Petkov 727e1069839SBorislav Petkov }; 728e1069839SBorislav Petkov 729e1069839SBorislav Petkov /* 730e1069839SBorislav Petkov * Notes on the events: 731e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 732e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 733e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 734e1069839SBorislav Petkov * - prefetches are not included in the counts because they are not 735e1069839SBorislav Petkov * reliably counted. 736e1069839SBorislav Petkov */ 737e1069839SBorislav Petkov 738e1069839SBorislav Petkov #define HSW_DEMAND_DATA_RD BIT_ULL(0) 739e1069839SBorislav Petkov #define HSW_DEMAND_RFO BIT_ULL(1) 740e1069839SBorislav Petkov #define HSW_ANY_RESPONSE BIT_ULL(16) 741e1069839SBorislav Petkov #define HSW_SUPPLIER_NONE BIT_ULL(17) 742e1069839SBorislav Petkov #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 743e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 744e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 745e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 746e1069839SBorislav Petkov #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 747e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 748e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 749e1069839SBorislav Petkov #define HSW_SNOOP_NONE BIT_ULL(31) 750e1069839SBorislav Petkov #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 751e1069839SBorislav Petkov #define HSW_SNOOP_MISS BIT_ULL(33) 752e1069839SBorislav Petkov #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 753e1069839SBorislav Petkov #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 754e1069839SBorislav Petkov #define HSW_SNOOP_HITM BIT_ULL(36) 755e1069839SBorislav Petkov #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 756e1069839SBorislav Petkov #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 757e1069839SBorislav Petkov HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 758e1069839SBorislav Petkov HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 759e1069839SBorislav Petkov HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 760e1069839SBorislav Petkov #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 761e1069839SBorislav Petkov #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 762e1069839SBorislav Petkov #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 763e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 764e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 765e1069839SBorislav Petkov #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 766e1069839SBorislav Petkov 767e1069839SBorislav Petkov #define BDW_L3_MISS_LOCAL BIT(26) 768e1069839SBorislav Petkov #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 769e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 770e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 771e1069839SBorislav Petkov 772e1069839SBorislav Petkov 773e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_event_ids 774e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 775e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 776e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 777e1069839SBorislav Petkov { 778e1069839SBorislav Petkov [ C(L1D ) ] = { 779e1069839SBorislav Petkov [ C(OP_READ) ] = { 780e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 781e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 782e1069839SBorislav Petkov }, 783e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 784e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 785e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 786e1069839SBorislav Petkov }, 787e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 788e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 789e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 790e1069839SBorislav Petkov }, 791e1069839SBorislav Petkov }, 792e1069839SBorislav Petkov [ C(L1I ) ] = { 793e1069839SBorislav Petkov [ C(OP_READ) ] = { 794e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 795e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 796e1069839SBorislav Petkov }, 797e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 798e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 799e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 800e1069839SBorislav Petkov }, 801e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 802e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 803e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 804e1069839SBorislav Petkov }, 805e1069839SBorislav Petkov }, 806e1069839SBorislav Petkov [ C(LL ) ] = { 807e1069839SBorislav Petkov [ C(OP_READ) ] = { 808e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 809e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 810e1069839SBorislav Petkov }, 811e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 812e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 813e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 814e1069839SBorislav Petkov }, 815e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 816e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 817e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 818e1069839SBorislav Petkov }, 819e1069839SBorislav Petkov }, 820e1069839SBorislav Petkov [ C(DTLB) ] = { 821e1069839SBorislav Petkov [ C(OP_READ) ] = { 822e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 823e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 824e1069839SBorislav Petkov }, 825e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 826e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 827e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 828e1069839SBorislav Petkov }, 829e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 830e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 831e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 832e1069839SBorislav Petkov }, 833e1069839SBorislav Petkov }, 834e1069839SBorislav Petkov [ C(ITLB) ] = { 835e1069839SBorislav Petkov [ C(OP_READ) ] = { 836e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 837e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 838e1069839SBorislav Petkov }, 839e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 840e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 841e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 842e1069839SBorislav Petkov }, 843e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 844e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 845e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 846e1069839SBorislav Petkov }, 847e1069839SBorislav Petkov }, 848e1069839SBorislav Petkov [ C(BPU ) ] = { 849e1069839SBorislav Petkov [ C(OP_READ) ] = { 850e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 851e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 852e1069839SBorislav Petkov }, 853e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 854e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 855e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 856e1069839SBorislav Petkov }, 857e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 858e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 859e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 860e1069839SBorislav Petkov }, 861e1069839SBorislav Petkov }, 862e1069839SBorislav Petkov [ C(NODE) ] = { 863e1069839SBorislav Petkov [ C(OP_READ) ] = { 864e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 865e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 866e1069839SBorislav Petkov }, 867e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 868e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 869e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 870e1069839SBorislav Petkov }, 871e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 872e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 873e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 874e1069839SBorislav Petkov }, 875e1069839SBorislav Petkov }, 876e1069839SBorislav Petkov }; 877e1069839SBorislav Petkov 878e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_extra_regs 879e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 880e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 881e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 882e1069839SBorislav Petkov { 883e1069839SBorislav Petkov [ C(LL ) ] = { 884e1069839SBorislav Petkov [ C(OP_READ) ] = { 885e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 886e1069839SBorislav Petkov HSW_LLC_ACCESS, 887e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 888e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 889e1069839SBorislav Petkov }, 890e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 891e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 892e1069839SBorislav Petkov HSW_LLC_ACCESS, 893e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 894e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 895e1069839SBorislav Petkov }, 896e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 897e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 898e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 899e1069839SBorislav Petkov }, 900e1069839SBorislav Petkov }, 901e1069839SBorislav Petkov [ C(NODE) ] = { 902e1069839SBorislav Petkov [ C(OP_READ) ] = { 903e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 904e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 905e1069839SBorislav Petkov HSW_SNOOP_DRAM, 906e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 907e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 908e1069839SBorislav Petkov HSW_SNOOP_DRAM, 909e1069839SBorislav Petkov }, 910e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 911e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 912e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 913e1069839SBorislav Petkov HSW_SNOOP_DRAM, 914e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 915e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 916e1069839SBorislav Petkov HSW_SNOOP_DRAM, 917e1069839SBorislav Petkov }, 918e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 919e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 920e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 921e1069839SBorislav Petkov }, 922e1069839SBorislav Petkov }, 923e1069839SBorislav Petkov }; 924e1069839SBorislav Petkov 925e1069839SBorislav Petkov static __initconst const u64 westmere_hw_cache_event_ids 926e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 927e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 928e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 929e1069839SBorislav Petkov { 930e1069839SBorislav Petkov [ C(L1D) ] = { 931e1069839SBorislav Petkov [ C(OP_READ) ] = { 932e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 933e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 934e1069839SBorislav Petkov }, 935e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 936e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 937e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 938e1069839SBorislav Petkov }, 939e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 940e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 941e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 942e1069839SBorislav Petkov }, 943e1069839SBorislav Petkov }, 944e1069839SBorislav Petkov [ C(L1I ) ] = { 945e1069839SBorislav Petkov [ C(OP_READ) ] = { 946e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 947e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 948e1069839SBorislav Petkov }, 949e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 950e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 951e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 952e1069839SBorislav Petkov }, 953e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 954e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 955e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 956e1069839SBorislav Petkov }, 957e1069839SBorislav Petkov }, 958e1069839SBorislav Petkov [ C(LL ) ] = { 959e1069839SBorislav Petkov [ C(OP_READ) ] = { 960e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 961e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 962e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 963e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 964e1069839SBorislav Petkov }, 965e1069839SBorislav Petkov /* 966e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 967e1069839SBorislav Petkov * on RFO. 968e1069839SBorislav Petkov */ 969e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 970e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 971e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 972e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 973e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 974e1069839SBorislav Petkov }, 975e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 976e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 977e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 978e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 979e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 980e1069839SBorislav Petkov }, 981e1069839SBorislav Petkov }, 982e1069839SBorislav Petkov [ C(DTLB) ] = { 983e1069839SBorislav Petkov [ C(OP_READ) ] = { 984e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 985e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 986e1069839SBorislav Petkov }, 987e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 988e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 989e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 990e1069839SBorislav Petkov }, 991e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 992e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 993e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 994e1069839SBorislav Petkov }, 995e1069839SBorislav Petkov }, 996e1069839SBorislav Petkov [ C(ITLB) ] = { 997e1069839SBorislav Petkov [ C(OP_READ) ] = { 998e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 999e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1000e1069839SBorislav Petkov }, 1001e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1002e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1003e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1004e1069839SBorislav Petkov }, 1005e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1006e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1007e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1008e1069839SBorislav Petkov }, 1009e1069839SBorislav Petkov }, 1010e1069839SBorislav Petkov [ C(BPU ) ] = { 1011e1069839SBorislav Petkov [ C(OP_READ) ] = { 1012e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1013e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1014e1069839SBorislav Petkov }, 1015e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1016e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1017e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1018e1069839SBorislav Petkov }, 1019e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1020e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1021e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1022e1069839SBorislav Petkov }, 1023e1069839SBorislav Petkov }, 1024e1069839SBorislav Petkov [ C(NODE) ] = { 1025e1069839SBorislav Petkov [ C(OP_READ) ] = { 1026e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1027e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1028e1069839SBorislav Petkov }, 1029e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1030e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1031e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1032e1069839SBorislav Petkov }, 1033e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1034e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1035e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1036e1069839SBorislav Petkov }, 1037e1069839SBorislav Petkov }, 1038e1069839SBorislav Petkov }; 1039e1069839SBorislav Petkov 1040e1069839SBorislav Petkov /* 1041e1069839SBorislav Petkov * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1042e1069839SBorislav Petkov * See IA32 SDM Vol 3B 30.6.1.3 1043e1069839SBorislav Petkov */ 1044e1069839SBorislav Petkov 1045e1069839SBorislav Petkov #define NHM_DMND_DATA_RD (1 << 0) 1046e1069839SBorislav Petkov #define NHM_DMND_RFO (1 << 1) 1047e1069839SBorislav Petkov #define NHM_DMND_IFETCH (1 << 2) 1048e1069839SBorislav Petkov #define NHM_DMND_WB (1 << 3) 1049e1069839SBorislav Petkov #define NHM_PF_DATA_RD (1 << 4) 1050e1069839SBorislav Petkov #define NHM_PF_DATA_RFO (1 << 5) 1051e1069839SBorislav Petkov #define NHM_PF_IFETCH (1 << 6) 1052e1069839SBorislav Petkov #define NHM_OFFCORE_OTHER (1 << 7) 1053e1069839SBorislav Petkov #define NHM_UNCORE_HIT (1 << 8) 1054e1069839SBorislav Petkov #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1055e1069839SBorislav Petkov #define NHM_OTHER_CORE_HITM (1 << 10) 1056e1069839SBorislav Petkov /* reserved */ 1057e1069839SBorislav Petkov #define NHM_REMOTE_CACHE_FWD (1 << 12) 1058e1069839SBorislav Petkov #define NHM_REMOTE_DRAM (1 << 13) 1059e1069839SBorislav Petkov #define NHM_LOCAL_DRAM (1 << 14) 1060e1069839SBorislav Petkov #define NHM_NON_DRAM (1 << 15) 1061e1069839SBorislav Petkov 1062e1069839SBorislav Petkov #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1063e1069839SBorislav Petkov #define NHM_REMOTE (NHM_REMOTE_DRAM) 1064e1069839SBorislav Petkov 1065e1069839SBorislav Petkov #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1066e1069839SBorislav Petkov #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1067e1069839SBorislav Petkov #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1068e1069839SBorislav Petkov 1069e1069839SBorislav Petkov #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1070e1069839SBorislav Petkov #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1071e1069839SBorislav Petkov #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1072e1069839SBorislav Petkov 1073e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_extra_regs 1074e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1075e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1076e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1077e1069839SBorislav Petkov { 1078e1069839SBorislav Petkov [ C(LL ) ] = { 1079e1069839SBorislav Petkov [ C(OP_READ) ] = { 1080e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1081e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1082e1069839SBorislav Petkov }, 1083e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1084e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1085e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1086e1069839SBorislav Petkov }, 1087e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1088e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1089e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1090e1069839SBorislav Petkov }, 1091e1069839SBorislav Petkov }, 1092e1069839SBorislav Petkov [ C(NODE) ] = { 1093e1069839SBorislav Petkov [ C(OP_READ) ] = { 1094e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1095e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1096e1069839SBorislav Petkov }, 1097e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1098e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1099e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1100e1069839SBorislav Petkov }, 1101e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1102e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1103e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1104e1069839SBorislav Petkov }, 1105e1069839SBorislav Petkov }, 1106e1069839SBorislav Petkov }; 1107e1069839SBorislav Petkov 1108e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_event_ids 1109e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1110e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1111e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1112e1069839SBorislav Petkov { 1113e1069839SBorislav Petkov [ C(L1D) ] = { 1114e1069839SBorislav Petkov [ C(OP_READ) ] = { 1115e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1116e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1117e1069839SBorislav Petkov }, 1118e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1119e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1120e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1121e1069839SBorislav Petkov }, 1122e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1123e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1124e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1125e1069839SBorislav Petkov }, 1126e1069839SBorislav Petkov }, 1127e1069839SBorislav Petkov [ C(L1I ) ] = { 1128e1069839SBorislav Petkov [ C(OP_READ) ] = { 1129e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1130e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1131e1069839SBorislav Petkov }, 1132e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1133e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1134e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1135e1069839SBorislav Petkov }, 1136e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1137e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1138e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1139e1069839SBorislav Petkov }, 1140e1069839SBorislav Petkov }, 1141e1069839SBorislav Petkov [ C(LL ) ] = { 1142e1069839SBorislav Petkov [ C(OP_READ) ] = { 1143e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1144e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1145e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1146e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1147e1069839SBorislav Petkov }, 1148e1069839SBorislav Petkov /* 1149e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1150e1069839SBorislav Petkov * on RFO. 1151e1069839SBorislav Petkov */ 1152e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1153e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1154e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1155e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1156e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1157e1069839SBorislav Petkov }, 1158e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1159e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1160e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1161e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1162e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1163e1069839SBorislav Petkov }, 1164e1069839SBorislav Petkov }, 1165e1069839SBorislav Petkov [ C(DTLB) ] = { 1166e1069839SBorislav Petkov [ C(OP_READ) ] = { 1167e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1168e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1169e1069839SBorislav Petkov }, 1170e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1171e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1172e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1173e1069839SBorislav Petkov }, 1174e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1175e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1176e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1177e1069839SBorislav Petkov }, 1178e1069839SBorislav Petkov }, 1179e1069839SBorislav Petkov [ C(ITLB) ] = { 1180e1069839SBorislav Petkov [ C(OP_READ) ] = { 1181e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1182e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1183e1069839SBorislav Petkov }, 1184e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1185e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1186e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1187e1069839SBorislav Petkov }, 1188e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1189e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1190e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1191e1069839SBorislav Petkov }, 1192e1069839SBorislav Petkov }, 1193e1069839SBorislav Petkov [ C(BPU ) ] = { 1194e1069839SBorislav Petkov [ C(OP_READ) ] = { 1195e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1196e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1197e1069839SBorislav Petkov }, 1198e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1199e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1200e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1201e1069839SBorislav Petkov }, 1202e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1203e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1204e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1205e1069839SBorislav Petkov }, 1206e1069839SBorislav Petkov }, 1207e1069839SBorislav Petkov [ C(NODE) ] = { 1208e1069839SBorislav Petkov [ C(OP_READ) ] = { 1209e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1210e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1211e1069839SBorislav Petkov }, 1212e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1213e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1214e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1215e1069839SBorislav Petkov }, 1216e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1217e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1218e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1219e1069839SBorislav Petkov }, 1220e1069839SBorislav Petkov }, 1221e1069839SBorislav Petkov }; 1222e1069839SBorislav Petkov 1223e1069839SBorislav Petkov static __initconst const u64 core2_hw_cache_event_ids 1224e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1225e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1226e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1227e1069839SBorislav Petkov { 1228e1069839SBorislav Petkov [ C(L1D) ] = { 1229e1069839SBorislav Petkov [ C(OP_READ) ] = { 1230e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1231e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1232e1069839SBorislav Petkov }, 1233e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1234e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1235e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1236e1069839SBorislav Petkov }, 1237e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1238e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1239e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1240e1069839SBorislav Petkov }, 1241e1069839SBorislav Petkov }, 1242e1069839SBorislav Petkov [ C(L1I ) ] = { 1243e1069839SBorislav Petkov [ C(OP_READ) ] = { 1244e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1245e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1246e1069839SBorislav Petkov }, 1247e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1248e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1249e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1250e1069839SBorislav Petkov }, 1251e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1252e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1253e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1254e1069839SBorislav Petkov }, 1255e1069839SBorislav Petkov }, 1256e1069839SBorislav Petkov [ C(LL ) ] = { 1257e1069839SBorislav Petkov [ C(OP_READ) ] = { 1258e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1259e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1260e1069839SBorislav Petkov }, 1261e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1262e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1263e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1264e1069839SBorislav Petkov }, 1265e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1266e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1267e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1268e1069839SBorislav Petkov }, 1269e1069839SBorislav Petkov }, 1270e1069839SBorislav Petkov [ C(DTLB) ] = { 1271e1069839SBorislav Petkov [ C(OP_READ) ] = { 1272e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1273e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1274e1069839SBorislav Petkov }, 1275e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1276e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1277e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1278e1069839SBorislav Petkov }, 1279e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1280e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1281e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1282e1069839SBorislav Petkov }, 1283e1069839SBorislav Petkov }, 1284e1069839SBorislav Petkov [ C(ITLB) ] = { 1285e1069839SBorislav Petkov [ C(OP_READ) ] = { 1286e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1287e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1288e1069839SBorislav Petkov }, 1289e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1290e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1291e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1292e1069839SBorislav Petkov }, 1293e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1294e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1295e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1296e1069839SBorislav Petkov }, 1297e1069839SBorislav Petkov }, 1298e1069839SBorislav Petkov [ C(BPU ) ] = { 1299e1069839SBorislav Petkov [ C(OP_READ) ] = { 1300e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1301e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1302e1069839SBorislav Petkov }, 1303e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1304e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1305e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1306e1069839SBorislav Petkov }, 1307e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1308e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1309e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1310e1069839SBorislav Petkov }, 1311e1069839SBorislav Petkov }, 1312e1069839SBorislav Petkov }; 1313e1069839SBorislav Petkov 1314e1069839SBorislav Petkov static __initconst const u64 atom_hw_cache_event_ids 1315e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1316e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1317e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1318e1069839SBorislav Petkov { 1319e1069839SBorislav Petkov [ C(L1D) ] = { 1320e1069839SBorislav Petkov [ C(OP_READ) ] = { 1321e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1322e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1323e1069839SBorislav Petkov }, 1324e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1325e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1326e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1327e1069839SBorislav Petkov }, 1328e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1329e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1330e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1331e1069839SBorislav Petkov }, 1332e1069839SBorislav Petkov }, 1333e1069839SBorislav Petkov [ C(L1I ) ] = { 1334e1069839SBorislav Petkov [ C(OP_READ) ] = { 1335e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1336e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1337e1069839SBorislav Petkov }, 1338e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1339e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1340e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1341e1069839SBorislav Petkov }, 1342e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1343e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1344e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1345e1069839SBorislav Petkov }, 1346e1069839SBorislav Petkov }, 1347e1069839SBorislav Petkov [ C(LL ) ] = { 1348e1069839SBorislav Petkov [ C(OP_READ) ] = { 1349e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1350e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1351e1069839SBorislav Petkov }, 1352e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1353e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1354e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1355e1069839SBorislav Petkov }, 1356e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1357e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1358e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1359e1069839SBorislav Petkov }, 1360e1069839SBorislav Petkov }, 1361e1069839SBorislav Petkov [ C(DTLB) ] = { 1362e1069839SBorislav Petkov [ C(OP_READ) ] = { 1363e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1364e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1365e1069839SBorislav Petkov }, 1366e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1367e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1368e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1369e1069839SBorislav Petkov }, 1370e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1371e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1372e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1373e1069839SBorislav Petkov }, 1374e1069839SBorislav Petkov }, 1375e1069839SBorislav Petkov [ C(ITLB) ] = { 1376e1069839SBorislav Petkov [ C(OP_READ) ] = { 1377e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1378e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1379e1069839SBorislav Petkov }, 1380e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1381e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1382e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1383e1069839SBorislav Petkov }, 1384e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1385e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1386e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1387e1069839SBorislav Petkov }, 1388e1069839SBorislav Petkov }, 1389e1069839SBorislav Petkov [ C(BPU ) ] = { 1390e1069839SBorislav Petkov [ C(OP_READ) ] = { 1391e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1392e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1393e1069839SBorislav Petkov }, 1394e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1395e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1396e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1397e1069839SBorislav Petkov }, 1398e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1399e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1400e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1401e1069839SBorislav Petkov }, 1402e1069839SBorislav Petkov }, 1403e1069839SBorislav Petkov }; 1404e1069839SBorislav Petkov 1405eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1406eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1407eb12b8ecSAndi Kleen /* no_alloc_cycles.not_delivered */ 1408eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1409eb12b8ecSAndi Kleen "event=0xca,umask=0x50"); 1410eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1411eb12b8ecSAndi Kleen /* uops_retired.all */ 1412eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1413eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1414eb12b8ecSAndi Kleen /* uops_retired.all */ 1415eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1416eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1417eb12b8ecSAndi Kleen 1418eb12b8ecSAndi Kleen static struct attribute *slm_events_attrs[] = { 1419eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_slm), 1420eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_scale_slm), 1421eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_slm), 1422eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_scale_slm), 1423eb12b8ecSAndi Kleen EVENT_PTR(td_slots_issued_slm), 1424eb12b8ecSAndi Kleen EVENT_PTR(td_slots_retired_slm), 1425eb12b8ecSAndi Kleen NULL 1426eb12b8ecSAndi Kleen }; 1427eb12b8ecSAndi Kleen 1428e1069839SBorislav Petkov static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1429e1069839SBorislav Petkov { 1430e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1431e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1432e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1433e1069839SBorislav Petkov EVENT_EXTRA_END 1434e1069839SBorislav Petkov }; 1435e1069839SBorislav Petkov 1436e1069839SBorislav Petkov #define SLM_DMND_READ SNB_DMND_DATA_RD 1437e1069839SBorislav Petkov #define SLM_DMND_WRITE SNB_DMND_RFO 1438e1069839SBorislav Petkov #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1439e1069839SBorislav Petkov 1440e1069839SBorislav Petkov #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1441e1069839SBorislav Petkov #define SLM_LLC_ACCESS SNB_RESP_ANY 1442e1069839SBorislav Petkov #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1443e1069839SBorislav Petkov 1444e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_extra_regs 1445e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1446e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1447e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1448e1069839SBorislav Petkov { 1449e1069839SBorislav Petkov [ C(LL ) ] = { 1450e1069839SBorislav Petkov [ C(OP_READ) ] = { 1451e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1452e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1453e1069839SBorislav Petkov }, 1454e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1455e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1456e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1457e1069839SBorislav Petkov }, 1458e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1459e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1460e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1461e1069839SBorislav Petkov }, 1462e1069839SBorislav Petkov }, 1463e1069839SBorislav Petkov }; 1464e1069839SBorislav Petkov 1465e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_event_ids 1466e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1467e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1468e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1469e1069839SBorislav Petkov { 1470e1069839SBorislav Petkov [ C(L1D) ] = { 1471e1069839SBorislav Petkov [ C(OP_READ) ] = { 1472e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1473e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1474e1069839SBorislav Petkov }, 1475e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1476e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1477e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1478e1069839SBorislav Petkov }, 1479e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1480e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1481e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1482e1069839SBorislav Petkov }, 1483e1069839SBorislav Petkov }, 1484e1069839SBorislav Petkov [ C(L1I ) ] = { 1485e1069839SBorislav Petkov [ C(OP_READ) ] = { 1486e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1487e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1488e1069839SBorislav Petkov }, 1489e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1490e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1491e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1492e1069839SBorislav Petkov }, 1493e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1494e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1495e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1496e1069839SBorislav Petkov }, 1497e1069839SBorislav Petkov }, 1498e1069839SBorislav Petkov [ C(LL ) ] = { 1499e1069839SBorislav Petkov [ C(OP_READ) ] = { 1500e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1501e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1502e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1503e1069839SBorislav Petkov }, 1504e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1505e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1506e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1507e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1508e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1509e1069839SBorislav Petkov }, 1510e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1511e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1512e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1513e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1514e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1515e1069839SBorislav Petkov }, 1516e1069839SBorislav Petkov }, 1517e1069839SBorislav Petkov [ C(DTLB) ] = { 1518e1069839SBorislav Petkov [ C(OP_READ) ] = { 1519e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1520e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1521e1069839SBorislav Petkov }, 1522e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1523e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1524e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1525e1069839SBorislav Petkov }, 1526e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1527e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1528e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1529e1069839SBorislav Petkov }, 1530e1069839SBorislav Petkov }, 1531e1069839SBorislav Petkov [ C(ITLB) ] = { 1532e1069839SBorislav Petkov [ C(OP_READ) ] = { 1533e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1534e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1535e1069839SBorislav Petkov }, 1536e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1537e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1538e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1539e1069839SBorislav Petkov }, 1540e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1541e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1542e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1543e1069839SBorislav Petkov }, 1544e1069839SBorislav Petkov }, 1545e1069839SBorislav Petkov [ C(BPU ) ] = { 1546e1069839SBorislav Petkov [ C(OP_READ) ] = { 1547e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1548e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1549e1069839SBorislav Petkov }, 1550e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1551e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1552e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1553e1069839SBorislav Petkov }, 1554e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1555e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1556e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1557e1069839SBorislav Petkov }, 1558e1069839SBorislav Petkov }, 1559e1069839SBorislav Petkov }; 1560e1069839SBorislav Petkov 1561ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1562ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1563ed827adbSKan Liang /* UOPS_NOT_DELIVERED.ANY */ 1564ed827adbSKan Liang EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1565ed827adbSKan Liang /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1566ed827adbSKan Liang EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1567ed827adbSKan Liang /* UOPS_RETIRED.ANY */ 1568ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1569ed827adbSKan Liang /* UOPS_ISSUED.ANY */ 1570ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1571ed827adbSKan Liang 1572ed827adbSKan Liang static struct attribute *glm_events_attrs[] = { 1573ed827adbSKan Liang EVENT_PTR(td_total_slots_glm), 1574ed827adbSKan Liang EVENT_PTR(td_total_slots_scale_glm), 1575ed827adbSKan Liang EVENT_PTR(td_fetch_bubbles_glm), 1576ed827adbSKan Liang EVENT_PTR(td_recovery_bubbles_glm), 1577ed827adbSKan Liang EVENT_PTR(td_slots_issued_glm), 1578ed827adbSKan Liang EVENT_PTR(td_slots_retired_glm), 1579ed827adbSKan Liang NULL 1580ed827adbSKan Liang }; 1581ed827adbSKan Liang 15828b92c3a7SKan Liang static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 15838b92c3a7SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 15848b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 15858b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 15868b92c3a7SKan Liang EVENT_EXTRA_END 15878b92c3a7SKan Liang }; 15888b92c3a7SKan Liang 15898b92c3a7SKan Liang #define GLM_DEMAND_DATA_RD BIT_ULL(0) 15908b92c3a7SKan Liang #define GLM_DEMAND_RFO BIT_ULL(1) 15918b92c3a7SKan Liang #define GLM_ANY_RESPONSE BIT_ULL(16) 15928b92c3a7SKan Liang #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 15938b92c3a7SKan Liang #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 15948b92c3a7SKan Liang #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 15958b92c3a7SKan Liang #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 15968b92c3a7SKan Liang #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 15978b92c3a7SKan Liang #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 15988b92c3a7SKan Liang #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 15998b92c3a7SKan Liang 16008b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_event_ids 16018b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 16028b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 16038b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 16048b92c3a7SKan Liang [C(L1D)] = { 16058b92c3a7SKan Liang [C(OP_READ)] = { 16068b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16078b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16088b92c3a7SKan Liang }, 16098b92c3a7SKan Liang [C(OP_WRITE)] = { 16108b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16118b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16128b92c3a7SKan Liang }, 16138b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16148b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16158b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16168b92c3a7SKan Liang }, 16178b92c3a7SKan Liang }, 16188b92c3a7SKan Liang [C(L1I)] = { 16198b92c3a7SKan Liang [C(OP_READ)] = { 16208b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 16218b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 16228b92c3a7SKan Liang }, 16238b92c3a7SKan Liang [C(OP_WRITE)] = { 16248b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16258b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16268b92c3a7SKan Liang }, 16278b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16288b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16298b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16308b92c3a7SKan Liang }, 16318b92c3a7SKan Liang }, 16328b92c3a7SKan Liang [C(LL)] = { 16338b92c3a7SKan Liang [C(OP_READ)] = { 16348b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16358b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16368b92c3a7SKan Liang }, 16378b92c3a7SKan Liang [C(OP_WRITE)] = { 16388b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16398b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16408b92c3a7SKan Liang }, 16418b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16428b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16438b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16448b92c3a7SKan Liang }, 16458b92c3a7SKan Liang }, 16468b92c3a7SKan Liang [C(DTLB)] = { 16478b92c3a7SKan Liang [C(OP_READ)] = { 16488b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16498b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16508b92c3a7SKan Liang }, 16518b92c3a7SKan Liang [C(OP_WRITE)] = { 16528b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16538b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16548b92c3a7SKan Liang }, 16558b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16568b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16578b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16588b92c3a7SKan Liang }, 16598b92c3a7SKan Liang }, 16608b92c3a7SKan Liang [C(ITLB)] = { 16618b92c3a7SKan Liang [C(OP_READ)] = { 16628b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 16638b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 16648b92c3a7SKan Liang }, 16658b92c3a7SKan Liang [C(OP_WRITE)] = { 16668b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16678b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16688b92c3a7SKan Liang }, 16698b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16708b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16718b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16728b92c3a7SKan Liang }, 16738b92c3a7SKan Liang }, 16748b92c3a7SKan Liang [C(BPU)] = { 16758b92c3a7SKan Liang [C(OP_READ)] = { 16768b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 16778b92c3a7SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 16788b92c3a7SKan Liang }, 16798b92c3a7SKan Liang [C(OP_WRITE)] = { 16808b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16818b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16828b92c3a7SKan Liang }, 16838b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16848b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16858b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16868b92c3a7SKan Liang }, 16878b92c3a7SKan Liang }, 16888b92c3a7SKan Liang }; 16898b92c3a7SKan Liang 16908b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_extra_regs 16918b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 16928b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 16938b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 16948b92c3a7SKan Liang [C(LL)] = { 16958b92c3a7SKan Liang [C(OP_READ)] = { 16968b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 16978b92c3a7SKan Liang GLM_LLC_ACCESS, 16988b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 16998b92c3a7SKan Liang GLM_LLC_MISS, 17008b92c3a7SKan Liang }, 17018b92c3a7SKan Liang [C(OP_WRITE)] = { 17028b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 17038b92c3a7SKan Liang GLM_LLC_ACCESS, 17048b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 17058b92c3a7SKan Liang GLM_LLC_MISS, 17068b92c3a7SKan Liang }, 17078b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17088b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 17098b92c3a7SKan Liang GLM_LLC_ACCESS, 17108b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 17118b92c3a7SKan Liang GLM_LLC_MISS, 17128b92c3a7SKan Liang }, 17138b92c3a7SKan Liang }, 17148b92c3a7SKan Liang }; 17158b92c3a7SKan Liang 1716dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_event_ids 1717dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1718dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1719dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1720dd0b06b5SKan Liang [C(L1D)] = { 1721dd0b06b5SKan Liang [C(OP_READ)] = { 1722dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1723dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1724dd0b06b5SKan Liang }, 1725dd0b06b5SKan Liang [C(OP_WRITE)] = { 1726dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1727dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1728dd0b06b5SKan Liang }, 1729dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1730dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1731dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1732dd0b06b5SKan Liang }, 1733dd0b06b5SKan Liang }, 1734dd0b06b5SKan Liang [C(L1I)] = { 1735dd0b06b5SKan Liang [C(OP_READ)] = { 1736dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1737dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1738dd0b06b5SKan Liang }, 1739dd0b06b5SKan Liang [C(OP_WRITE)] = { 1740dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1741dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1742dd0b06b5SKan Liang }, 1743dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1744dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1745dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1746dd0b06b5SKan Liang }, 1747dd0b06b5SKan Liang }, 1748dd0b06b5SKan Liang [C(LL)] = { 1749dd0b06b5SKan Liang [C(OP_READ)] = { 1750dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1751dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1752dd0b06b5SKan Liang }, 1753dd0b06b5SKan Liang [C(OP_WRITE)] = { 1754dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1755dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1756dd0b06b5SKan Liang }, 1757dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1758dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1759dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1760dd0b06b5SKan Liang }, 1761dd0b06b5SKan Liang }, 1762dd0b06b5SKan Liang [C(DTLB)] = { 1763dd0b06b5SKan Liang [C(OP_READ)] = { 1764dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1765dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1766dd0b06b5SKan Liang }, 1767dd0b06b5SKan Liang [C(OP_WRITE)] = { 1768dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1769dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1770dd0b06b5SKan Liang }, 1771dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1772dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1773dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1774dd0b06b5SKan Liang }, 1775dd0b06b5SKan Liang }, 1776dd0b06b5SKan Liang [C(ITLB)] = { 1777dd0b06b5SKan Liang [C(OP_READ)] = { 1778dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1779dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1780dd0b06b5SKan Liang }, 1781dd0b06b5SKan Liang [C(OP_WRITE)] = { 1782dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1783dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1784dd0b06b5SKan Liang }, 1785dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1786dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1787dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1788dd0b06b5SKan Liang }, 1789dd0b06b5SKan Liang }, 1790dd0b06b5SKan Liang [C(BPU)] = { 1791dd0b06b5SKan Liang [C(OP_READ)] = { 1792dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1793dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1794dd0b06b5SKan Liang }, 1795dd0b06b5SKan Liang [C(OP_WRITE)] = { 1796dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1797dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1798dd0b06b5SKan Liang }, 1799dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1800dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1801dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1802dd0b06b5SKan Liang }, 1803dd0b06b5SKan Liang }, 1804dd0b06b5SKan Liang }; 1805dd0b06b5SKan Liang 1806dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_extra_regs 1807dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1808dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1809dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1810dd0b06b5SKan Liang [C(LL)] = { 1811dd0b06b5SKan Liang [C(OP_READ)] = { 1812dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1813dd0b06b5SKan Liang GLM_LLC_ACCESS, 1814dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 1815dd0b06b5SKan Liang GLM_LLC_MISS, 1816dd0b06b5SKan Liang }, 1817dd0b06b5SKan Liang [C(OP_WRITE)] = { 1818dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1819dd0b06b5SKan Liang GLM_LLC_ACCESS, 1820dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1821dd0b06b5SKan Liang GLM_LLC_MISS, 1822dd0b06b5SKan Liang }, 1823dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1824dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1825dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1826dd0b06b5SKan Liang }, 1827dd0b06b5SKan Liang }, 1828dd0b06b5SKan Liang }; 1829dd0b06b5SKan Liang 1830e1069839SBorislav Petkov #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1831e1069839SBorislav Petkov #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1832e1069839SBorislav Petkov #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1833e1069839SBorislav Petkov #define KNL_MCDRAM_FAR BIT_ULL(22) 1834e1069839SBorislav Petkov #define KNL_DDR_LOCAL BIT_ULL(23) 1835e1069839SBorislav Petkov #define KNL_DDR_FAR BIT_ULL(24) 1836e1069839SBorislav Petkov #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1837e1069839SBorislav Petkov KNL_DDR_LOCAL | KNL_DDR_FAR) 1838e1069839SBorislav Petkov #define KNL_L2_READ SLM_DMND_READ 1839e1069839SBorislav Petkov #define KNL_L2_WRITE SLM_DMND_WRITE 1840e1069839SBorislav Petkov #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1841e1069839SBorislav Petkov #define KNL_L2_ACCESS SLM_LLC_ACCESS 1842e1069839SBorislav Petkov #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1843e1069839SBorislav Petkov KNL_DRAM_ANY | SNB_SNP_ANY | \ 1844e1069839SBorislav Petkov SNB_NON_DRAM) 1845e1069839SBorislav Petkov 1846e1069839SBorislav Petkov static __initconst const u64 knl_hw_cache_extra_regs 1847e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1848e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1849e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1850e1069839SBorislav Petkov [C(LL)] = { 1851e1069839SBorislav Petkov [C(OP_READ)] = { 1852e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1853e1069839SBorislav Petkov [C(RESULT_MISS)] = 0, 1854e1069839SBorislav Petkov }, 1855e1069839SBorislav Petkov [C(OP_WRITE)] = { 1856e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1857e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1858e1069839SBorislav Petkov }, 1859e1069839SBorislav Petkov [C(OP_PREFETCH)] = { 1860e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1861e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1862e1069839SBorislav Petkov }, 1863e1069839SBorislav Petkov }, 1864e1069839SBorislav Petkov }; 1865e1069839SBorislav Petkov 1866e1069839SBorislav Petkov /* 1867c3d266c8SKan Liang * Used from PMIs where the LBRs are already disabled. 1868c3d266c8SKan Liang * 1869c3d266c8SKan Liang * This function could be called consecutively. It is required to remain in 1870c3d266c8SKan Liang * disabled state if called consecutively. 1871c3d266c8SKan Liang * 1872c3d266c8SKan Liang * During consecutive calls, the same disable value will be written to related 1873cecf6235SAlexander Shishkin * registers, so the PMU state remains unchanged. 1874cecf6235SAlexander Shishkin * 1875cecf6235SAlexander Shishkin * intel_bts events don't coexist with intel PMU's BTS events because of 1876cecf6235SAlexander Shishkin * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1877cecf6235SAlexander Shishkin * disabled around intel PMU's event batching etc, only inside the PMI handler. 1878e1069839SBorislav Petkov */ 1879e1069839SBorislav Petkov static void __intel_pmu_disable_all(void) 1880e1069839SBorislav Petkov { 1881e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1882e1069839SBorislav Petkov 1883e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1884e1069839SBorislav Petkov 1885e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1886e1069839SBorislav Petkov intel_pmu_disable_bts(); 1887e1069839SBorislav Petkov 1888e1069839SBorislav Petkov intel_pmu_pebs_disable_all(); 1889e1069839SBorislav Petkov } 1890e1069839SBorislav Petkov 1891e1069839SBorislav Petkov static void intel_pmu_disable_all(void) 1892e1069839SBorislav Petkov { 1893e1069839SBorislav Petkov __intel_pmu_disable_all(); 1894e1069839SBorislav Petkov intel_pmu_lbr_disable_all(); 1895e1069839SBorislav Petkov } 1896e1069839SBorislav Petkov 1897e1069839SBorislav Petkov static void __intel_pmu_enable_all(int added, bool pmi) 1898e1069839SBorislav Petkov { 1899e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1900e1069839SBorislav Petkov 1901e1069839SBorislav Petkov intel_pmu_pebs_enable_all(); 1902e1069839SBorislav Petkov intel_pmu_lbr_enable_all(pmi); 1903e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1904e1069839SBorislav Petkov x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1905e1069839SBorislav Petkov 1906e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1907e1069839SBorislav Petkov struct perf_event *event = 1908e1069839SBorislav Petkov cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1909e1069839SBorislav Petkov 1910e1069839SBorislav Petkov if (WARN_ON_ONCE(!event)) 1911e1069839SBorislav Petkov return; 1912e1069839SBorislav Petkov 1913e1069839SBorislav Petkov intel_pmu_enable_bts(event->hw.config); 1914cecf6235SAlexander Shishkin } 1915e1069839SBorislav Petkov } 1916e1069839SBorislav Petkov 1917e1069839SBorislav Petkov static void intel_pmu_enable_all(int added) 1918e1069839SBorislav Petkov { 1919e1069839SBorislav Petkov __intel_pmu_enable_all(added, false); 1920e1069839SBorislav Petkov } 1921e1069839SBorislav Petkov 1922e1069839SBorislav Petkov /* 1923e1069839SBorislav Petkov * Workaround for: 1924e1069839SBorislav Petkov * Intel Errata AAK100 (model 26) 1925e1069839SBorislav Petkov * Intel Errata AAP53 (model 30) 1926e1069839SBorislav Petkov * Intel Errata BD53 (model 44) 1927e1069839SBorislav Petkov * 1928e1069839SBorislav Petkov * The official story: 1929e1069839SBorislav Petkov * These chips need to be 'reset' when adding counters by programming the 1930e1069839SBorislav Petkov * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 1931e1069839SBorislav Petkov * in sequence on the same PMC or on different PMCs. 1932e1069839SBorislav Petkov * 1933e1069839SBorislav Petkov * In practise it appears some of these events do in fact count, and 1934a97673a1SIngo Molnar * we need to program all 4 events. 1935e1069839SBorislav Petkov */ 1936e1069839SBorislav Petkov static void intel_pmu_nhm_workaround(void) 1937e1069839SBorislav Petkov { 1938e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1939e1069839SBorislav Petkov static const unsigned long nhm_magic[4] = { 1940e1069839SBorislav Petkov 0x4300B5, 1941e1069839SBorislav Petkov 0x4300D2, 1942e1069839SBorislav Petkov 0x4300B1, 1943e1069839SBorislav Petkov 0x4300B1 1944e1069839SBorislav Petkov }; 1945e1069839SBorislav Petkov struct perf_event *event; 1946e1069839SBorislav Petkov int i; 1947e1069839SBorislav Petkov 1948e1069839SBorislav Petkov /* 1949e1069839SBorislav Petkov * The Errata requires below steps: 1950e1069839SBorislav Petkov * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 1951e1069839SBorislav Petkov * 2) Configure 4 PERFEVTSELx with the magic events and clear 1952e1069839SBorislav Petkov * the corresponding PMCx; 1953e1069839SBorislav Petkov * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 1954e1069839SBorislav Petkov * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 1955e1069839SBorislav Petkov * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 1956e1069839SBorislav Petkov */ 1957e1069839SBorislav Petkov 1958e1069839SBorislav Petkov /* 1959e1069839SBorislav Petkov * The real steps we choose are a little different from above. 1960e1069839SBorislav Petkov * A) To reduce MSR operations, we don't run step 1) as they 1961e1069839SBorislav Petkov * are already cleared before this function is called; 1962e1069839SBorislav Petkov * B) Call x86_perf_event_update to save PMCx before configuring 1963e1069839SBorislav Petkov * PERFEVTSELx with magic number; 1964e1069839SBorislav Petkov * C) With step 5), we do clear only when the PERFEVTSELx is 1965e1069839SBorislav Petkov * not used currently. 1966e1069839SBorislav Petkov * D) Call x86_perf_event_set_period to restore PMCx; 1967e1069839SBorislav Petkov */ 1968e1069839SBorislav Petkov 1969e1069839SBorislav Petkov /* We always operate 4 pairs of PERF Counters */ 1970e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 1971e1069839SBorislav Petkov event = cpuc->events[i]; 1972e1069839SBorislav Petkov if (event) 1973e1069839SBorislav Petkov x86_perf_event_update(event); 1974e1069839SBorislav Petkov } 1975e1069839SBorislav Petkov 1976e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 1977e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 1978e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 1979e1069839SBorislav Petkov } 1980e1069839SBorislav Petkov 1981e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 1982e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 1983e1069839SBorislav Petkov 1984e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 1985e1069839SBorislav Petkov event = cpuc->events[i]; 1986e1069839SBorislav Petkov 1987e1069839SBorislav Petkov if (event) { 1988e1069839SBorislav Petkov x86_perf_event_set_period(event); 1989e1069839SBorislav Petkov __x86_pmu_enable_event(&event->hw, 1990e1069839SBorislav Petkov ARCH_PERFMON_EVENTSEL_ENABLE); 1991e1069839SBorislav Petkov } else 1992e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 1993e1069839SBorislav Petkov } 1994e1069839SBorislav Petkov } 1995e1069839SBorislav Petkov 1996e1069839SBorislav Petkov static void intel_pmu_nhm_enable_all(int added) 1997e1069839SBorislav Petkov { 1998e1069839SBorislav Petkov if (added) 1999e1069839SBorislav Petkov intel_pmu_nhm_workaround(); 2000e1069839SBorislav Petkov intel_pmu_enable_all(added); 2001e1069839SBorislav Petkov } 2002e1069839SBorislav Petkov 2003af3bdb99SAndi Kleen static void enable_counter_freeze(void) 2004af3bdb99SAndi Kleen { 2005af3bdb99SAndi Kleen update_debugctlmsr(get_debugctlmsr() | 2006af3bdb99SAndi Kleen DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2007af3bdb99SAndi Kleen } 2008af3bdb99SAndi Kleen 2009af3bdb99SAndi Kleen static void disable_counter_freeze(void) 2010af3bdb99SAndi Kleen { 2011af3bdb99SAndi Kleen update_debugctlmsr(get_debugctlmsr() & 2012af3bdb99SAndi Kleen ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2013af3bdb99SAndi Kleen } 2014af3bdb99SAndi Kleen 2015e1069839SBorislav Petkov static inline u64 intel_pmu_get_status(void) 2016e1069839SBorislav Petkov { 2017e1069839SBorislav Petkov u64 status; 2018e1069839SBorislav Petkov 2019e1069839SBorislav Petkov rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2020e1069839SBorislav Petkov 2021e1069839SBorislav Petkov return status; 2022e1069839SBorislav Petkov } 2023e1069839SBorislav Petkov 2024e1069839SBorislav Petkov static inline void intel_pmu_ack_status(u64 ack) 2025e1069839SBorislav Petkov { 2026e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2027e1069839SBorislav Petkov } 2028e1069839SBorislav Petkov 2029e1069839SBorislav Petkov static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 2030e1069839SBorislav Petkov { 2031e1069839SBorislav Petkov int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2032e1069839SBorislav Petkov u64 ctrl_val, mask; 2033e1069839SBorislav Petkov 2034e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2035e1069839SBorislav Petkov 2036e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2037e1069839SBorislav Petkov ctrl_val &= ~mask; 2038e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2039e1069839SBorislav Petkov } 2040e1069839SBorislav Petkov 2041e1069839SBorislav Petkov static inline bool event_is_checkpointed(struct perf_event *event) 2042e1069839SBorislav Petkov { 2043e1069839SBorislav Petkov return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2044e1069839SBorislav Petkov } 2045e1069839SBorislav Petkov 2046e1069839SBorislav Petkov static void intel_pmu_disable_event(struct perf_event *event) 2047e1069839SBorislav Petkov { 2048e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2049e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2050e1069839SBorislav Petkov 2051e1069839SBorislav Petkov if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2052e1069839SBorislav Petkov intel_pmu_disable_bts(); 2053e1069839SBorislav Petkov intel_pmu_drain_bts_buffer(); 2054e1069839SBorislav Petkov return; 2055e1069839SBorislav Petkov } 2056e1069839SBorislav Petkov 2057e1069839SBorislav Petkov cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); 2058e1069839SBorislav Petkov cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); 2059e1069839SBorislav Petkov cpuc->intel_cp_status &= ~(1ull << hwc->idx); 2060e1069839SBorislav Petkov 20614f08b625SKan Liang if (unlikely(event->attr.precise_ip)) 20624f08b625SKan Liang intel_pmu_pebs_disable(event); 20634f08b625SKan Liang 2064e1069839SBorislav Petkov if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2065e1069839SBorislav Petkov intel_pmu_disable_fixed(hwc); 2066e1069839SBorislav Petkov return; 2067e1069839SBorislav Petkov } 2068e1069839SBorislav Petkov 2069e1069839SBorislav Petkov x86_pmu_disable_event(event); 2070e1069839SBorislav Petkov } 2071e1069839SBorislav Petkov 207268f7082fSPeter Zijlstra static void intel_pmu_del_event(struct perf_event *event) 207368f7082fSPeter Zijlstra { 207468f7082fSPeter Zijlstra if (needs_branch_stack(event)) 207568f7082fSPeter Zijlstra intel_pmu_lbr_del(event); 207668f7082fSPeter Zijlstra if (event->attr.precise_ip) 207768f7082fSPeter Zijlstra intel_pmu_pebs_del(event); 207868f7082fSPeter Zijlstra } 207968f7082fSPeter Zijlstra 2080ceb90d9eSKan Liang static void intel_pmu_read_event(struct perf_event *event) 2081ceb90d9eSKan Liang { 2082ceb90d9eSKan Liang if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2083ceb90d9eSKan Liang intel_pmu_auto_reload_read(event); 2084ceb90d9eSKan Liang else 2085ceb90d9eSKan Liang x86_perf_event_update(event); 2086ceb90d9eSKan Liang } 2087ceb90d9eSKan Liang 20884f08b625SKan Liang static void intel_pmu_enable_fixed(struct perf_event *event) 2089e1069839SBorislav Petkov { 20904f08b625SKan Liang struct hw_perf_event *hwc = &event->hw; 2091e1069839SBorislav Petkov int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 20924f08b625SKan Liang u64 ctrl_val, mask, bits = 0; 2093e1069839SBorislav Petkov 2094e1069839SBorislav Petkov /* 20954f08b625SKan Liang * Enable IRQ generation (0x8), if not PEBS, 2096e1069839SBorislav Petkov * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2097e1069839SBorislav Petkov * if requested: 2098e1069839SBorislav Petkov */ 20994f08b625SKan Liang if (!event->attr.precise_ip) 21004f08b625SKan Liang bits |= 0x8; 2101e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2102e1069839SBorislav Petkov bits |= 0x2; 2103e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2104e1069839SBorislav Petkov bits |= 0x1; 2105e1069839SBorislav Petkov 2106e1069839SBorislav Petkov /* 2107e1069839SBorislav Petkov * ANY bit is supported in v3 and up 2108e1069839SBorislav Petkov */ 2109e1069839SBorislav Petkov if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2110e1069839SBorislav Petkov bits |= 0x4; 2111e1069839SBorislav Petkov 2112e1069839SBorislav Petkov bits <<= (idx * 4); 2113e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2114e1069839SBorislav Petkov 2115e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2116e1069839SBorislav Petkov ctrl_val &= ~mask; 2117e1069839SBorislav Petkov ctrl_val |= bits; 2118e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2119e1069839SBorislav Petkov } 2120e1069839SBorislav Petkov 2121e1069839SBorislav Petkov static void intel_pmu_enable_event(struct perf_event *event) 2122e1069839SBorislav Petkov { 2123e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2124e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2125e1069839SBorislav Petkov 2126e1069839SBorislav Petkov if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2127e1069839SBorislav Petkov if (!__this_cpu_read(cpu_hw_events.enabled)) 2128e1069839SBorislav Petkov return; 2129e1069839SBorislav Petkov 2130e1069839SBorislav Petkov intel_pmu_enable_bts(hwc->config); 2131e1069839SBorislav Petkov return; 2132e1069839SBorislav Petkov } 2133e1069839SBorislav Petkov 2134e1069839SBorislav Petkov if (event->attr.exclude_host) 2135e1069839SBorislav Petkov cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); 2136e1069839SBorislav Petkov if (event->attr.exclude_guest) 2137e1069839SBorislav Petkov cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); 2138e1069839SBorislav Petkov 2139e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) 2140e1069839SBorislav Petkov cpuc->intel_cp_status |= (1ull << hwc->idx); 2141e1069839SBorislav Petkov 2142e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2143e1069839SBorislav Petkov intel_pmu_pebs_enable(event); 2144e1069839SBorislav Petkov 21454f08b625SKan Liang if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 21464f08b625SKan Liang intel_pmu_enable_fixed(event); 21474f08b625SKan Liang return; 21484f08b625SKan Liang } 21494f08b625SKan Liang 2150e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2151e1069839SBorislav Petkov } 2152e1069839SBorislav Petkov 215368f7082fSPeter Zijlstra static void intel_pmu_add_event(struct perf_event *event) 215468f7082fSPeter Zijlstra { 215568f7082fSPeter Zijlstra if (event->attr.precise_ip) 215668f7082fSPeter Zijlstra intel_pmu_pebs_add(event); 215768f7082fSPeter Zijlstra if (needs_branch_stack(event)) 215868f7082fSPeter Zijlstra intel_pmu_lbr_add(event); 215968f7082fSPeter Zijlstra } 216068f7082fSPeter Zijlstra 2161e1069839SBorislav Petkov /* 2162e1069839SBorislav Petkov * Save and restart an expired event. Called by NMI contexts, 2163e1069839SBorislav Petkov * so it has to be careful about preempting normal event ops: 2164e1069839SBorislav Petkov */ 2165e1069839SBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event) 2166e1069839SBorislav Petkov { 2167e1069839SBorislav Petkov x86_perf_event_update(event); 2168e1069839SBorislav Petkov /* 2169e1069839SBorislav Petkov * For a checkpointed counter always reset back to 0. This 2170e1069839SBorislav Petkov * avoids a situation where the counter overflows, aborts the 2171e1069839SBorislav Petkov * transaction and is then set back to shortly before the 2172e1069839SBorislav Petkov * overflow, and overflows and aborts again. 2173e1069839SBorislav Petkov */ 2174e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) { 2175e1069839SBorislav Petkov /* No race with NMIs because the counter should not be armed */ 2176e1069839SBorislav Petkov wrmsrl(event->hw.event_base, 0); 2177e1069839SBorislav Petkov local64_set(&event->hw.prev_count, 0); 2178e1069839SBorislav Petkov } 2179e1069839SBorislav Petkov return x86_perf_event_set_period(event); 2180e1069839SBorislav Petkov } 2181e1069839SBorislav Petkov 2182e1069839SBorislav Petkov static void intel_pmu_reset(void) 2183e1069839SBorislav Petkov { 2184e1069839SBorislav Petkov struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2185e1069839SBorislav Petkov unsigned long flags; 2186e1069839SBorislav Petkov int idx; 2187e1069839SBorislav Petkov 2188e1069839SBorislav Petkov if (!x86_pmu.num_counters) 2189e1069839SBorislav Petkov return; 2190e1069839SBorislav Petkov 2191e1069839SBorislav Petkov local_irq_save(flags); 2192e1069839SBorislav Petkov 2193e1069839SBorislav Petkov pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2194e1069839SBorislav Petkov 2195e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2196e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2197e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2198e1069839SBorislav Petkov } 2199e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2200e1069839SBorislav Petkov wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2201e1069839SBorislav Petkov 2202e1069839SBorislav Petkov if (ds) 2203e1069839SBorislav Petkov ds->bts_index = ds->bts_buffer_base; 2204e1069839SBorislav Petkov 2205e1069839SBorislav Petkov /* Ack all overflows and disable fixed counters */ 2206e1069839SBorislav Petkov if (x86_pmu.version >= 2) { 2207e1069839SBorislav Petkov intel_pmu_ack_status(intel_pmu_get_status()); 2208e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2209e1069839SBorislav Petkov } 2210e1069839SBorislav Petkov 2211e1069839SBorislav Petkov /* Reset LBRs and LBR freezing */ 2212e1069839SBorislav Petkov if (x86_pmu.lbr_nr) { 2213e1069839SBorislav Petkov update_debugctlmsr(get_debugctlmsr() & 2214e1069839SBorislav Petkov ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2215e1069839SBorislav Petkov } 2216e1069839SBorislav Petkov 2217e1069839SBorislav Petkov local_irq_restore(flags); 2218e1069839SBorislav Petkov } 2219e1069839SBorislav Petkov 2220ba12d20eSKan Liang static int handle_pmi_common(struct pt_regs *regs, u64 status) 2221e1069839SBorislav Petkov { 2222e1069839SBorislav Petkov struct perf_sample_data data; 2223ba12d20eSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2224ba12d20eSKan Liang int bit; 2225ba12d20eSKan Liang int handled = 0; 2226e1069839SBorislav Petkov 2227e1069839SBorislav Petkov inc_irq_stat(apic_perf_irqs); 2228e1069839SBorislav Petkov 2229e1069839SBorislav Petkov /* 2230e1069839SBorislav Petkov * Ignore a range of extra bits in status that do not indicate 2231e1069839SBorislav Petkov * overflow by themselves. 2232e1069839SBorislav Petkov */ 2233e1069839SBorislav Petkov status &= ~(GLOBAL_STATUS_COND_CHG | 2234e1069839SBorislav Petkov GLOBAL_STATUS_ASIF | 2235e1069839SBorislav Petkov GLOBAL_STATUS_LBRS_FROZEN); 2236e1069839SBorislav Petkov if (!status) 2237ba12d20eSKan Liang return 0; 2238daa864b8SStephane Eranian /* 2239daa864b8SStephane Eranian * In case multiple PEBS events are sampled at the same time, 2240daa864b8SStephane Eranian * it is possible to have GLOBAL_STATUS bit 62 set indicating 2241daa864b8SStephane Eranian * PEBS buffer overflow and also seeing at most 3 PEBS counters 2242daa864b8SStephane Eranian * having their bits set in the status register. This is a sign 2243daa864b8SStephane Eranian * that there was at least one PEBS record pending at the time 2244daa864b8SStephane Eranian * of the PMU interrupt. PEBS counters must only be processed 2245daa864b8SStephane Eranian * via the drain_pebs() calls and not via the regular sample 2246daa864b8SStephane Eranian * processing loop coming after that the function, otherwise 2247daa864b8SStephane Eranian * phony regular samples may be generated in the sampling buffer 2248daa864b8SStephane Eranian * not marked with the EXACT tag. Another possibility is to have 2249daa864b8SStephane Eranian * one PEBS event and at least one non-PEBS event whic hoverflows 2250daa864b8SStephane Eranian * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2251daa864b8SStephane Eranian * not be set, yet the overflow status bit for the PEBS counter will 2252daa864b8SStephane Eranian * be on Skylake. 2253daa864b8SStephane Eranian * 2254daa864b8SStephane Eranian * To avoid this problem, we systematically ignore the PEBS-enabled 2255daa864b8SStephane Eranian * counters from the GLOBAL_STATUS mask and we always process PEBS 2256daa864b8SStephane Eranian * events via drain_pebs(). 2257daa864b8SStephane Eranian */ 2258ec71a398SKan Liang if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2259ec71a398SKan Liang status &= ~cpuc->pebs_enabled; 2260ec71a398SKan Liang else 2261fd583ad1SKan Liang status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2262e1069839SBorislav Petkov 2263e1069839SBorislav Petkov /* 2264e1069839SBorislav Petkov * PEBS overflow sets bit 62 in the global status register 2265e1069839SBorislav Petkov */ 2266e1069839SBorislav Petkov if (__test_and_clear_bit(62, (unsigned long *)&status)) { 2267e1069839SBorislav Petkov handled++; 2268e1069839SBorislav Petkov x86_pmu.drain_pebs(regs); 22698077eca0SStephane Eranian status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2270e1069839SBorislav Petkov } 2271e1069839SBorislav Petkov 2272e1069839SBorislav Petkov /* 2273e1069839SBorislav Petkov * Intel PT 2274e1069839SBorislav Petkov */ 2275e1069839SBorislav Petkov if (__test_and_clear_bit(55, (unsigned long *)&status)) { 2276e1069839SBorislav Petkov handled++; 2277e1069839SBorislav Petkov intel_pt_interrupt(); 2278e1069839SBorislav Petkov } 2279e1069839SBorislav Petkov 2280e1069839SBorislav Petkov /* 2281e1069839SBorislav Petkov * Checkpointed counters can lead to 'spurious' PMIs because the 2282e1069839SBorislav Petkov * rollback caused by the PMI will have cleared the overflow status 2283e1069839SBorislav Petkov * bit. Therefore always force probe these counters. 2284e1069839SBorislav Petkov */ 2285e1069839SBorislav Petkov status |= cpuc->intel_cp_status; 2286e1069839SBorislav Petkov 2287e1069839SBorislav Petkov for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2288e1069839SBorislav Petkov struct perf_event *event = cpuc->events[bit]; 2289e1069839SBorislav Petkov 2290e1069839SBorislav Petkov handled++; 2291e1069839SBorislav Petkov 2292e1069839SBorislav Petkov if (!test_bit(bit, cpuc->active_mask)) 2293e1069839SBorislav Petkov continue; 2294e1069839SBorislav Petkov 2295e1069839SBorislav Petkov if (!intel_pmu_save_and_restart(event)) 2296e1069839SBorislav Petkov continue; 2297e1069839SBorislav Petkov 2298e1069839SBorislav Petkov perf_sample_data_init(&data, 0, event->hw.last_period); 2299e1069839SBorislav Petkov 2300e1069839SBorislav Petkov if (has_branch_stack(event)) 2301e1069839SBorislav Petkov data.br_stack = &cpuc->lbr_stack; 2302e1069839SBorislav Petkov 2303e1069839SBorislav Petkov if (perf_event_overflow(event, &data, regs)) 2304e1069839SBorislav Petkov x86_pmu_stop(event, 0); 2305e1069839SBorislav Petkov } 2306e1069839SBorislav Petkov 2307ba12d20eSKan Liang return handled; 2308ba12d20eSKan Liang } 2309ba12d20eSKan Liang 23102a5bf23dSPeter Zijlstra static bool disable_counter_freezing = true; 2311af3bdb99SAndi Kleen static int __init intel_perf_counter_freezing_setup(char *s) 2312af3bdb99SAndi Kleen { 23132a5bf23dSPeter Zijlstra bool res; 23142a5bf23dSPeter Zijlstra 23152a5bf23dSPeter Zijlstra if (kstrtobool(s, &res)) 23162a5bf23dSPeter Zijlstra return -EINVAL; 23172a5bf23dSPeter Zijlstra 23182a5bf23dSPeter Zijlstra disable_counter_freezing = !res; 2319af3bdb99SAndi Kleen return 1; 2320af3bdb99SAndi Kleen } 23212a5bf23dSPeter Zijlstra __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup); 2322af3bdb99SAndi Kleen 2323af3bdb99SAndi Kleen /* 2324af3bdb99SAndi Kleen * Simplified handler for Arch Perfmon v4: 2325af3bdb99SAndi Kleen * - We rely on counter freezing/unfreezing to enable/disable the PMU. 2326af3bdb99SAndi Kleen * This is done automatically on PMU ack. 2327af3bdb99SAndi Kleen * - Ack the PMU only after the APIC. 2328af3bdb99SAndi Kleen */ 2329af3bdb99SAndi Kleen 2330af3bdb99SAndi Kleen static int intel_pmu_handle_irq_v4(struct pt_regs *regs) 2331af3bdb99SAndi Kleen { 2332af3bdb99SAndi Kleen struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2333af3bdb99SAndi Kleen int handled = 0; 2334af3bdb99SAndi Kleen bool bts = false; 2335af3bdb99SAndi Kleen u64 status; 2336af3bdb99SAndi Kleen int pmu_enabled = cpuc->enabled; 2337af3bdb99SAndi Kleen int loops = 0; 2338af3bdb99SAndi Kleen 2339af3bdb99SAndi Kleen /* PMU has been disabled because of counter freezing */ 2340af3bdb99SAndi Kleen cpuc->enabled = 0; 2341af3bdb99SAndi Kleen if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2342af3bdb99SAndi Kleen bts = true; 2343af3bdb99SAndi Kleen intel_bts_disable_local(); 2344af3bdb99SAndi Kleen handled = intel_pmu_drain_bts_buffer(); 2345af3bdb99SAndi Kleen handled += intel_bts_interrupt(); 2346af3bdb99SAndi Kleen } 2347af3bdb99SAndi Kleen status = intel_pmu_get_status(); 2348af3bdb99SAndi Kleen if (!status) 2349af3bdb99SAndi Kleen goto done; 2350af3bdb99SAndi Kleen again: 2351af3bdb99SAndi Kleen intel_pmu_lbr_read(); 2352af3bdb99SAndi Kleen if (++loops > 100) { 2353af3bdb99SAndi Kleen static bool warned; 2354af3bdb99SAndi Kleen 2355af3bdb99SAndi Kleen if (!warned) { 2356af3bdb99SAndi Kleen WARN(1, "perfevents: irq loop stuck!\n"); 2357af3bdb99SAndi Kleen perf_event_print_debug(); 2358af3bdb99SAndi Kleen warned = true; 2359af3bdb99SAndi Kleen } 2360af3bdb99SAndi Kleen intel_pmu_reset(); 2361af3bdb99SAndi Kleen goto done; 2362af3bdb99SAndi Kleen } 2363af3bdb99SAndi Kleen 2364af3bdb99SAndi Kleen 2365af3bdb99SAndi Kleen handled += handle_pmi_common(regs, status); 2366af3bdb99SAndi Kleen done: 2367af3bdb99SAndi Kleen /* Ack the PMI in the APIC */ 2368af3bdb99SAndi Kleen apic_write(APIC_LVTPC, APIC_DM_NMI); 2369af3bdb99SAndi Kleen 2370af3bdb99SAndi Kleen /* 2371af3bdb99SAndi Kleen * The counters start counting immediately while ack the status. 2372af3bdb99SAndi Kleen * Make it as close as possible to IRET. This avoids bogus 2373af3bdb99SAndi Kleen * freezing on Skylake CPUs. 2374af3bdb99SAndi Kleen */ 2375af3bdb99SAndi Kleen if (status) { 2376af3bdb99SAndi Kleen intel_pmu_ack_status(status); 2377af3bdb99SAndi Kleen } else { 2378af3bdb99SAndi Kleen /* 2379af3bdb99SAndi Kleen * CPU may issues two PMIs very close to each other. 2380af3bdb99SAndi Kleen * When the PMI handler services the first one, the 2381af3bdb99SAndi Kleen * GLOBAL_STATUS is already updated to reflect both. 2382af3bdb99SAndi Kleen * When it IRETs, the second PMI is immediately 2383af3bdb99SAndi Kleen * handled and it sees clear status. At the meantime, 2384af3bdb99SAndi Kleen * there may be a third PMI, because the freezing bit 2385af3bdb99SAndi Kleen * isn't set since the ack in first PMI handlers. 2386af3bdb99SAndi Kleen * Double check if there is more work to be done. 2387af3bdb99SAndi Kleen */ 2388af3bdb99SAndi Kleen status = intel_pmu_get_status(); 2389af3bdb99SAndi Kleen if (status) 2390af3bdb99SAndi Kleen goto again; 2391af3bdb99SAndi Kleen } 2392af3bdb99SAndi Kleen 2393af3bdb99SAndi Kleen if (bts) 2394af3bdb99SAndi Kleen intel_bts_enable_local(); 2395af3bdb99SAndi Kleen cpuc->enabled = pmu_enabled; 2396af3bdb99SAndi Kleen return handled; 2397af3bdb99SAndi Kleen } 2398af3bdb99SAndi Kleen 2399ba12d20eSKan Liang /* 2400ba12d20eSKan Liang * This handler is triggered by the local APIC, so the APIC IRQ handling 2401ba12d20eSKan Liang * rules apply: 2402ba12d20eSKan Liang */ 2403ba12d20eSKan Liang static int intel_pmu_handle_irq(struct pt_regs *regs) 2404ba12d20eSKan Liang { 2405ba12d20eSKan Liang struct cpu_hw_events *cpuc; 2406ba12d20eSKan Liang int loops; 2407ba12d20eSKan Liang u64 status; 2408ba12d20eSKan Liang int handled; 2409ba12d20eSKan Liang int pmu_enabled; 2410ba12d20eSKan Liang 2411ba12d20eSKan Liang cpuc = this_cpu_ptr(&cpu_hw_events); 2412ba12d20eSKan Liang 2413ba12d20eSKan Liang /* 2414ba12d20eSKan Liang * Save the PMU state. 2415ba12d20eSKan Liang * It needs to be restored when leaving the handler. 2416ba12d20eSKan Liang */ 2417ba12d20eSKan Liang pmu_enabled = cpuc->enabled; 2418ba12d20eSKan Liang /* 2419ba12d20eSKan Liang * No known reason to not always do late ACK, 2420ba12d20eSKan Liang * but just in case do it opt-in. 2421ba12d20eSKan Liang */ 2422ba12d20eSKan Liang if (!x86_pmu.late_ack) 2423ba12d20eSKan Liang apic_write(APIC_LVTPC, APIC_DM_NMI); 2424ba12d20eSKan Liang intel_bts_disable_local(); 2425ba12d20eSKan Liang cpuc->enabled = 0; 2426ba12d20eSKan Liang __intel_pmu_disable_all(); 2427ba12d20eSKan Liang handled = intel_pmu_drain_bts_buffer(); 2428ba12d20eSKan Liang handled += intel_bts_interrupt(); 2429ba12d20eSKan Liang status = intel_pmu_get_status(); 2430ba12d20eSKan Liang if (!status) 2431ba12d20eSKan Liang goto done; 2432ba12d20eSKan Liang 2433ba12d20eSKan Liang loops = 0; 2434ba12d20eSKan Liang again: 2435ba12d20eSKan Liang intel_pmu_lbr_read(); 2436ba12d20eSKan Liang intel_pmu_ack_status(status); 2437ba12d20eSKan Liang if (++loops > 100) { 2438ba12d20eSKan Liang static bool warned; 2439ba12d20eSKan Liang 2440ba12d20eSKan Liang if (!warned) { 2441ba12d20eSKan Liang WARN(1, "perfevents: irq loop stuck!\n"); 2442ba12d20eSKan Liang perf_event_print_debug(); 2443ba12d20eSKan Liang warned = true; 2444ba12d20eSKan Liang } 2445ba12d20eSKan Liang intel_pmu_reset(); 2446ba12d20eSKan Liang goto done; 2447ba12d20eSKan Liang } 2448ba12d20eSKan Liang 2449ba12d20eSKan Liang handled += handle_pmi_common(regs, status); 2450ba12d20eSKan Liang 2451e1069839SBorislav Petkov /* 2452e1069839SBorislav Petkov * Repeat if there is more work to be done: 2453e1069839SBorislav Petkov */ 2454e1069839SBorislav Petkov status = intel_pmu_get_status(); 2455e1069839SBorislav Petkov if (status) 2456e1069839SBorislav Petkov goto again; 2457e1069839SBorislav Petkov 2458e1069839SBorislav Petkov done: 2459c3d266c8SKan Liang /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 246082d71ed0SKan Liang cpuc->enabled = pmu_enabled; 246182d71ed0SKan Liang if (pmu_enabled) 2462e1069839SBorislav Petkov __intel_pmu_enable_all(0, true); 2463cecf6235SAlexander Shishkin intel_bts_enable_local(); 2464c3d266c8SKan Liang 2465e1069839SBorislav Petkov /* 2466e1069839SBorislav Petkov * Only unmask the NMI after the overflow counters 2467e1069839SBorislav Petkov * have been reset. This avoids spurious NMIs on 2468e1069839SBorislav Petkov * Haswell CPUs. 2469e1069839SBorislav Petkov */ 2470e1069839SBorislav Petkov if (x86_pmu.late_ack) 2471e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 2472e1069839SBorislav Petkov return handled; 2473e1069839SBorislav Petkov } 2474e1069839SBorislav Petkov 2475e1069839SBorislav Petkov static struct event_constraint * 2476e1069839SBorislav Petkov intel_bts_constraints(struct perf_event *event) 2477e1069839SBorislav Petkov { 247867266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) 2479e1069839SBorislav Petkov return &bts_constraint; 2480e1069839SBorislav Petkov 2481e1069839SBorislav Petkov return NULL; 2482e1069839SBorislav Petkov } 2483e1069839SBorislav Petkov 2484e1069839SBorislav Petkov static int intel_alt_er(int idx, u64 config) 2485e1069839SBorislav Petkov { 2486e1069839SBorislav Petkov int alt_idx = idx; 2487e1069839SBorislav Petkov 2488e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2489e1069839SBorislav Petkov return idx; 2490e1069839SBorislav Petkov 2491e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) 2492e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_1; 2493e1069839SBorislav Petkov 2494e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_1) 2495e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_0; 2496e1069839SBorislav Petkov 2497e1069839SBorislav Petkov if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2498e1069839SBorislav Petkov return idx; 2499e1069839SBorislav Petkov 2500e1069839SBorislav Petkov return alt_idx; 2501e1069839SBorislav Petkov } 2502e1069839SBorislav Petkov 2503e1069839SBorislav Petkov static void intel_fixup_er(struct perf_event *event, int idx) 2504e1069839SBorislav Petkov { 2505e1069839SBorislav Petkov event->hw.extra_reg.idx = idx; 2506e1069839SBorislav Petkov 2507e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) { 2508e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2509e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2510e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2511e1069839SBorislav Petkov } else if (idx == EXTRA_REG_RSP_1) { 2512e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2513e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2514e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2515e1069839SBorislav Petkov } 2516e1069839SBorislav Petkov } 2517e1069839SBorislav Petkov 2518e1069839SBorislav Petkov /* 2519e1069839SBorislav Petkov * manage allocation of shared extra msr for certain events 2520e1069839SBorislav Petkov * 2521e1069839SBorislav Petkov * sharing can be: 2522e1069839SBorislav Petkov * per-cpu: to be shared between the various events on a single PMU 2523e1069839SBorislav Petkov * per-core: per-cpu + shared by HT threads 2524e1069839SBorislav Petkov */ 2525e1069839SBorislav Petkov static struct event_constraint * 2526e1069839SBorislav Petkov __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2527e1069839SBorislav Petkov struct perf_event *event, 2528e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2529e1069839SBorislav Petkov { 2530e1069839SBorislav Petkov struct event_constraint *c = &emptyconstraint; 2531e1069839SBorislav Petkov struct er_account *era; 2532e1069839SBorislav Petkov unsigned long flags; 2533e1069839SBorislav Petkov int idx = reg->idx; 2534e1069839SBorislav Petkov 2535e1069839SBorislav Petkov /* 2536e1069839SBorislav Petkov * reg->alloc can be set due to existing state, so for fake cpuc we 2537e1069839SBorislav Petkov * need to ignore this, otherwise we might fail to allocate proper fake 2538e1069839SBorislav Petkov * state for this extra reg constraint. Also see the comment below. 2539e1069839SBorislav Petkov */ 2540e1069839SBorislav Petkov if (reg->alloc && !cpuc->is_fake) 2541e1069839SBorislav Petkov return NULL; /* call x86_get_event_constraint() */ 2542e1069839SBorislav Petkov 2543e1069839SBorislav Petkov again: 2544e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[idx]; 2545e1069839SBorislav Petkov /* 2546e1069839SBorislav Petkov * we use spin_lock_irqsave() to avoid lockdep issues when 2547e1069839SBorislav Petkov * passing a fake cpuc 2548e1069839SBorislav Petkov */ 2549e1069839SBorislav Petkov raw_spin_lock_irqsave(&era->lock, flags); 2550e1069839SBorislav Petkov 2551e1069839SBorislav Petkov if (!atomic_read(&era->ref) || era->config == reg->config) { 2552e1069839SBorislav Petkov 2553e1069839SBorislav Petkov /* 2554e1069839SBorislav Petkov * If its a fake cpuc -- as per validate_{group,event}() we 2555e1069839SBorislav Petkov * shouldn't touch event state and we can avoid doing so 2556e1069839SBorislav Petkov * since both will only call get_event_constraints() once 2557e1069839SBorislav Petkov * on each event, this avoids the need for reg->alloc. 2558e1069839SBorislav Petkov * 2559e1069839SBorislav Petkov * Not doing the ER fixup will only result in era->reg being 2560e1069839SBorislav Petkov * wrong, but since we won't actually try and program hardware 2561e1069839SBorislav Petkov * this isn't a problem either. 2562e1069839SBorislav Petkov */ 2563e1069839SBorislav Petkov if (!cpuc->is_fake) { 2564e1069839SBorislav Petkov if (idx != reg->idx) 2565e1069839SBorislav Petkov intel_fixup_er(event, idx); 2566e1069839SBorislav Petkov 2567e1069839SBorislav Petkov /* 2568e1069839SBorislav Petkov * x86_schedule_events() can call get_event_constraints() 2569e1069839SBorislav Petkov * multiple times on events in the case of incremental 2570e1069839SBorislav Petkov * scheduling(). reg->alloc ensures we only do the ER 2571e1069839SBorislav Petkov * allocation once. 2572e1069839SBorislav Petkov */ 2573e1069839SBorislav Petkov reg->alloc = 1; 2574e1069839SBorislav Petkov } 2575e1069839SBorislav Petkov 2576e1069839SBorislav Petkov /* lock in msr value */ 2577e1069839SBorislav Petkov era->config = reg->config; 2578e1069839SBorislav Petkov era->reg = reg->reg; 2579e1069839SBorislav Petkov 2580e1069839SBorislav Petkov /* one more user */ 2581e1069839SBorislav Petkov atomic_inc(&era->ref); 2582e1069839SBorislav Petkov 2583e1069839SBorislav Petkov /* 2584e1069839SBorislav Petkov * need to call x86_get_event_constraint() 2585e1069839SBorislav Petkov * to check if associated event has constraints 2586e1069839SBorislav Petkov */ 2587e1069839SBorislav Petkov c = NULL; 2588e1069839SBorislav Petkov } else { 2589e1069839SBorislav Petkov idx = intel_alt_er(idx, reg->config); 2590e1069839SBorislav Petkov if (idx != reg->idx) { 2591e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2592e1069839SBorislav Petkov goto again; 2593e1069839SBorislav Petkov } 2594e1069839SBorislav Petkov } 2595e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2596e1069839SBorislav Petkov 2597e1069839SBorislav Petkov return c; 2598e1069839SBorislav Petkov } 2599e1069839SBorislav Petkov 2600e1069839SBorislav Petkov static void 2601e1069839SBorislav Petkov __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 2602e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2603e1069839SBorislav Petkov { 2604e1069839SBorislav Petkov struct er_account *era; 2605e1069839SBorislav Petkov 2606e1069839SBorislav Petkov /* 2607e1069839SBorislav Petkov * Only put constraint if extra reg was actually allocated. Also takes 2608e1069839SBorislav Petkov * care of event which do not use an extra shared reg. 2609e1069839SBorislav Petkov * 2610e1069839SBorislav Petkov * Also, if this is a fake cpuc we shouldn't touch any event state 2611e1069839SBorislav Petkov * (reg->alloc) and we don't care about leaving inconsistent cpuc state 2612e1069839SBorislav Petkov * either since it'll be thrown out. 2613e1069839SBorislav Petkov */ 2614e1069839SBorislav Petkov if (!reg->alloc || cpuc->is_fake) 2615e1069839SBorislav Petkov return; 2616e1069839SBorislav Petkov 2617e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[reg->idx]; 2618e1069839SBorislav Petkov 2619e1069839SBorislav Petkov /* one fewer user */ 2620e1069839SBorislav Petkov atomic_dec(&era->ref); 2621e1069839SBorislav Petkov 2622e1069839SBorislav Petkov /* allocate again next time */ 2623e1069839SBorislav Petkov reg->alloc = 0; 2624e1069839SBorislav Petkov } 2625e1069839SBorislav Petkov 2626e1069839SBorislav Petkov static struct event_constraint * 2627e1069839SBorislav Petkov intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 2628e1069839SBorislav Petkov struct perf_event *event) 2629e1069839SBorislav Petkov { 2630e1069839SBorislav Petkov struct event_constraint *c = NULL, *d; 2631e1069839SBorislav Petkov struct hw_perf_event_extra *xreg, *breg; 2632e1069839SBorislav Petkov 2633e1069839SBorislav Petkov xreg = &event->hw.extra_reg; 2634e1069839SBorislav Petkov if (xreg->idx != EXTRA_REG_NONE) { 2635e1069839SBorislav Petkov c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 2636e1069839SBorislav Petkov if (c == &emptyconstraint) 2637e1069839SBorislav Petkov return c; 2638e1069839SBorislav Petkov } 2639e1069839SBorislav Petkov breg = &event->hw.branch_reg; 2640e1069839SBorislav Petkov if (breg->idx != EXTRA_REG_NONE) { 2641e1069839SBorislav Petkov d = __intel_shared_reg_get_constraints(cpuc, event, breg); 2642e1069839SBorislav Petkov if (d == &emptyconstraint) { 2643e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, xreg); 2644e1069839SBorislav Petkov c = d; 2645e1069839SBorislav Petkov } 2646e1069839SBorislav Petkov } 2647e1069839SBorislav Petkov return c; 2648e1069839SBorislav Petkov } 2649e1069839SBorislav Petkov 2650e1069839SBorislav Petkov struct event_constraint * 2651e1069839SBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2652e1069839SBorislav Petkov struct perf_event *event) 2653e1069839SBorislav Petkov { 2654e1069839SBorislav Petkov struct event_constraint *c; 2655e1069839SBorislav Petkov 2656e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 2657e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 2658e1069839SBorislav Petkov if ((event->hw.config & c->cmask) == c->code) { 2659e1069839SBorislav Petkov event->hw.flags |= c->flags; 2660e1069839SBorislav Petkov return c; 2661e1069839SBorislav Petkov } 2662e1069839SBorislav Petkov } 2663e1069839SBorislav Petkov } 2664e1069839SBorislav Petkov 2665e1069839SBorislav Petkov return &unconstrained; 2666e1069839SBorislav Petkov } 2667e1069839SBorislav Petkov 2668e1069839SBorislav Petkov static struct event_constraint * 2669e1069839SBorislav Petkov __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2670e1069839SBorislav Petkov struct perf_event *event) 2671e1069839SBorislav Petkov { 2672e1069839SBorislav Petkov struct event_constraint *c; 2673e1069839SBorislav Petkov 2674e1069839SBorislav Petkov c = intel_bts_constraints(event); 2675e1069839SBorislav Petkov if (c) 2676e1069839SBorislav Petkov return c; 2677e1069839SBorislav Petkov 2678e1069839SBorislav Petkov c = intel_shared_regs_constraints(cpuc, event); 2679e1069839SBorislav Petkov if (c) 2680e1069839SBorislav Petkov return c; 2681e1069839SBorislav Petkov 2682e1069839SBorislav Petkov c = intel_pebs_constraints(event); 2683e1069839SBorislav Petkov if (c) 2684e1069839SBorislav Petkov return c; 2685e1069839SBorislav Petkov 2686e1069839SBorislav Petkov return x86_get_event_constraints(cpuc, idx, event); 2687e1069839SBorislav Petkov } 2688e1069839SBorislav Petkov 2689e1069839SBorislav Petkov static void 2690e1069839SBorislav Petkov intel_start_scheduling(struct cpu_hw_events *cpuc) 2691e1069839SBorislav Petkov { 2692e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2693e1069839SBorislav Petkov struct intel_excl_states *xl; 2694e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2695e1069839SBorislav Petkov 2696e1069839SBorislav Petkov /* 2697e1069839SBorislav Petkov * nothing needed if in group validation mode 2698e1069839SBorislav Petkov */ 2699e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2700e1069839SBorislav Petkov return; 2701e1069839SBorislav Petkov 2702e1069839SBorislav Petkov /* 2703e1069839SBorislav Petkov * no exclusion needed 2704e1069839SBorislav Petkov */ 2705e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2706e1069839SBorislav Petkov return; 2707e1069839SBorislav Petkov 2708e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2709e1069839SBorislav Petkov 2710e1069839SBorislav Petkov xl->sched_started = true; 2711e1069839SBorislav Petkov /* 2712e1069839SBorislav Petkov * lock shared state until we are done scheduling 2713e1069839SBorislav Petkov * in stop_event_scheduling() 2714e1069839SBorislav Petkov * makes scheduling appear as a transaction 2715e1069839SBorislav Petkov */ 2716e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 2717e1069839SBorislav Petkov } 2718e1069839SBorislav Petkov 2719e1069839SBorislav Petkov static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2720e1069839SBorislav Petkov { 2721e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2722e1069839SBorislav Petkov struct event_constraint *c = cpuc->event_constraint[idx]; 2723e1069839SBorislav Petkov struct intel_excl_states *xl; 2724e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2725e1069839SBorislav Petkov 2726e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2727e1069839SBorislav Petkov return; 2728e1069839SBorislav Petkov 2729e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2730e1069839SBorislav Petkov return; 2731e1069839SBorislav Petkov 2732e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 2733e1069839SBorislav Petkov return; 2734e1069839SBorislav Petkov 2735e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2736e1069839SBorislav Petkov 2737e1069839SBorislav Petkov lockdep_assert_held(&excl_cntrs->lock); 2738e1069839SBorislav Petkov 2739e1069839SBorislav Petkov if (c->flags & PERF_X86_EVENT_EXCL) 2740e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 2741e1069839SBorislav Petkov else 2742e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_SHARED; 2743e1069839SBorislav Petkov } 2744e1069839SBorislav Petkov 2745e1069839SBorislav Petkov static void 2746e1069839SBorislav Petkov intel_stop_scheduling(struct cpu_hw_events *cpuc) 2747e1069839SBorislav Petkov { 2748e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2749e1069839SBorislav Petkov struct intel_excl_states *xl; 2750e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2751e1069839SBorislav Petkov 2752e1069839SBorislav Petkov /* 2753e1069839SBorislav Petkov * nothing needed if in group validation mode 2754e1069839SBorislav Petkov */ 2755e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2756e1069839SBorislav Petkov return; 2757e1069839SBorislav Petkov /* 2758e1069839SBorislav Petkov * no exclusion needed 2759e1069839SBorislav Petkov */ 2760e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2761e1069839SBorislav Petkov return; 2762e1069839SBorislav Petkov 2763e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2764e1069839SBorislav Petkov 2765e1069839SBorislav Petkov xl->sched_started = false; 2766e1069839SBorislav Petkov /* 2767e1069839SBorislav Petkov * release shared state lock (acquired in intel_start_scheduling()) 2768e1069839SBorislav Petkov */ 2769e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 2770e1069839SBorislav Petkov } 2771e1069839SBorislav Petkov 2772e1069839SBorislav Petkov static struct event_constraint * 2773e1069839SBorislav Petkov intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 2774e1069839SBorislav Petkov int idx, struct event_constraint *c) 2775e1069839SBorislav Petkov { 2776e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2777e1069839SBorislav Petkov struct intel_excl_states *xlo; 2778e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2779e1069839SBorislav Petkov int is_excl, i; 2780e1069839SBorislav Petkov 2781e1069839SBorislav Petkov /* 2782e1069839SBorislav Petkov * validating a group does not require 2783e1069839SBorislav Petkov * enforcing cross-thread exclusion 2784e1069839SBorislav Petkov */ 2785e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2786e1069839SBorislav Petkov return c; 2787e1069839SBorislav Petkov 2788e1069839SBorislav Petkov /* 2789e1069839SBorislav Petkov * no exclusion needed 2790e1069839SBorislav Petkov */ 2791e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2792e1069839SBorislav Petkov return c; 2793e1069839SBorislav Petkov 2794e1069839SBorislav Petkov /* 2795e1069839SBorislav Petkov * because we modify the constraint, we need 2796e1069839SBorislav Petkov * to make a copy. Static constraints come 2797e1069839SBorislav Petkov * from static const tables. 2798e1069839SBorislav Petkov * 2799e1069839SBorislav Petkov * only needed when constraint has not yet 2800e1069839SBorislav Petkov * been cloned (marked dynamic) 2801e1069839SBorislav Petkov */ 2802e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 2803e1069839SBorislav Petkov struct event_constraint *cx; 2804e1069839SBorislav Petkov 2805e1069839SBorislav Petkov /* 2806e1069839SBorislav Petkov * grab pre-allocated constraint entry 2807e1069839SBorislav Petkov */ 2808e1069839SBorislav Petkov cx = &cpuc->constraint_list[idx]; 2809e1069839SBorislav Petkov 2810e1069839SBorislav Petkov /* 2811e1069839SBorislav Petkov * initialize dynamic constraint 2812e1069839SBorislav Petkov * with static constraint 2813e1069839SBorislav Petkov */ 2814e1069839SBorislav Petkov *cx = *c; 2815e1069839SBorislav Petkov 2816e1069839SBorislav Petkov /* 2817e1069839SBorislav Petkov * mark constraint as dynamic, so we 2818e1069839SBorislav Petkov * can free it later on 2819e1069839SBorislav Petkov */ 2820e1069839SBorislav Petkov cx->flags |= PERF_X86_EVENT_DYNAMIC; 2821e1069839SBorislav Petkov c = cx; 2822e1069839SBorislav Petkov } 2823e1069839SBorislav Petkov 2824e1069839SBorislav Petkov /* 2825e1069839SBorislav Petkov * From here on, the constraint is dynamic. 2826e1069839SBorislav Petkov * Either it was just allocated above, or it 2827e1069839SBorislav Petkov * was allocated during a earlier invocation 2828e1069839SBorislav Petkov * of this function 2829e1069839SBorislav Petkov */ 2830e1069839SBorislav Petkov 2831e1069839SBorislav Petkov /* 2832e1069839SBorislav Petkov * state of sibling HT 2833e1069839SBorislav Petkov */ 2834e1069839SBorislav Petkov xlo = &excl_cntrs->states[tid ^ 1]; 2835e1069839SBorislav Petkov 2836e1069839SBorislav Petkov /* 2837e1069839SBorislav Petkov * event requires exclusive counter access 2838e1069839SBorislav Petkov * across HT threads 2839e1069839SBorislav Petkov */ 2840e1069839SBorislav Petkov is_excl = c->flags & PERF_X86_EVENT_EXCL; 2841e1069839SBorislav Petkov if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 2842e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 2843e1069839SBorislav Petkov if (!cpuc->n_excl++) 2844e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 2845e1069839SBorislav Petkov } 2846e1069839SBorislav Petkov 2847e1069839SBorislav Petkov /* 2848e1069839SBorislav Petkov * Modify static constraint with current dynamic 2849e1069839SBorislav Petkov * state of thread 2850e1069839SBorislav Petkov * 2851e1069839SBorislav Petkov * EXCLUSIVE: sibling counter measuring exclusive event 2852e1069839SBorislav Petkov * SHARED : sibling counter measuring non-exclusive event 2853e1069839SBorislav Petkov * UNUSED : sibling counter unused 2854e1069839SBorislav Petkov */ 2855e1069839SBorislav Petkov for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 2856e1069839SBorislav Petkov /* 2857e1069839SBorislav Petkov * exclusive event in sibling counter 2858e1069839SBorislav Petkov * our corresponding counter cannot be used 2859e1069839SBorislav Petkov * regardless of our event 2860e1069839SBorislav Petkov */ 2861e1069839SBorislav Petkov if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) 2862e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 2863e1069839SBorislav Petkov /* 2864e1069839SBorislav Petkov * if measuring an exclusive event, sibling 2865e1069839SBorislav Petkov * measuring non-exclusive, then counter cannot 2866e1069839SBorislav Petkov * be used 2867e1069839SBorislav Petkov */ 2868e1069839SBorislav Petkov if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) 2869e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 2870e1069839SBorislav Petkov } 2871e1069839SBorislav Petkov 2872e1069839SBorislav Petkov /* 2873e1069839SBorislav Petkov * recompute actual bit weight for scheduling algorithm 2874e1069839SBorislav Petkov */ 2875e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 2876e1069839SBorislav Petkov 2877e1069839SBorislav Petkov /* 2878e1069839SBorislav Petkov * if we return an empty mask, then switch 2879e1069839SBorislav Petkov * back to static empty constraint to avoid 2880e1069839SBorislav Petkov * the cost of freeing later on 2881e1069839SBorislav Petkov */ 2882e1069839SBorislav Petkov if (c->weight == 0) 2883e1069839SBorislav Petkov c = &emptyconstraint; 2884e1069839SBorislav Petkov 2885e1069839SBorislav Petkov return c; 2886e1069839SBorislav Petkov } 2887e1069839SBorislav Petkov 2888e1069839SBorislav Petkov static struct event_constraint * 2889e1069839SBorislav Petkov intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2890e1069839SBorislav Petkov struct perf_event *event) 2891e1069839SBorislav Petkov { 2892e1069839SBorislav Petkov struct event_constraint *c1 = NULL; 2893e1069839SBorislav Petkov struct event_constraint *c2; 2894e1069839SBorislav Petkov 2895e1069839SBorislav Petkov if (idx >= 0) /* fake does < 0 */ 2896e1069839SBorislav Petkov c1 = cpuc->event_constraint[idx]; 2897e1069839SBorislav Petkov 2898e1069839SBorislav Petkov /* 2899e1069839SBorislav Petkov * first time only 2900e1069839SBorislav Petkov * - static constraint: no change across incremental scheduling calls 2901e1069839SBorislav Petkov * - dynamic constraint: handled by intel_get_excl_constraints() 2902e1069839SBorislav Petkov */ 2903e1069839SBorislav Petkov c2 = __intel_get_event_constraints(cpuc, idx, event); 2904e1069839SBorislav Petkov if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) { 2905e1069839SBorislav Petkov bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 2906e1069839SBorislav Petkov c1->weight = c2->weight; 2907e1069839SBorislav Petkov c2 = c1; 2908e1069839SBorislav Petkov } 2909e1069839SBorislav Petkov 2910e1069839SBorislav Petkov if (cpuc->excl_cntrs) 2911e1069839SBorislav Petkov return intel_get_excl_constraints(cpuc, event, idx, c2); 2912e1069839SBorislav Petkov 2913e1069839SBorislav Petkov return c2; 2914e1069839SBorislav Petkov } 2915e1069839SBorislav Petkov 2916e1069839SBorislav Petkov static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 2917e1069839SBorislav Petkov struct perf_event *event) 2918e1069839SBorislav Petkov { 2919e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2920e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2921e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2922e1069839SBorislav Petkov struct intel_excl_states *xl; 2923e1069839SBorislav Petkov 2924e1069839SBorislav Petkov /* 2925e1069839SBorislav Petkov * nothing needed if in group validation mode 2926e1069839SBorislav Petkov */ 2927e1069839SBorislav Petkov if (cpuc->is_fake) 2928e1069839SBorislav Petkov return; 2929e1069839SBorislav Petkov 2930e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2931e1069839SBorislav Petkov return; 2932e1069839SBorislav Petkov 2933e1069839SBorislav Petkov if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 2934e1069839SBorislav Petkov hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 2935e1069839SBorislav Petkov if (!--cpuc->n_excl) 2936e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 2937e1069839SBorislav Petkov } 2938e1069839SBorislav Petkov 2939e1069839SBorislav Petkov /* 2940e1069839SBorislav Petkov * If event was actually assigned, then mark the counter state as 2941e1069839SBorislav Petkov * unused now. 2942e1069839SBorislav Petkov */ 2943e1069839SBorislav Petkov if (hwc->idx >= 0) { 2944e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2945e1069839SBorislav Petkov 2946e1069839SBorislav Petkov /* 2947e1069839SBorislav Petkov * put_constraint may be called from x86_schedule_events() 2948e1069839SBorislav Petkov * which already has the lock held so here make locking 2949e1069839SBorislav Petkov * conditional. 2950e1069839SBorislav Petkov */ 2951e1069839SBorislav Petkov if (!xl->sched_started) 2952e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 2953e1069839SBorislav Petkov 2954e1069839SBorislav Petkov xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 2955e1069839SBorislav Petkov 2956e1069839SBorislav Petkov if (!xl->sched_started) 2957e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 2958e1069839SBorislav Petkov } 2959e1069839SBorislav Petkov } 2960e1069839SBorislav Petkov 2961e1069839SBorislav Petkov static void 2962e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 2963e1069839SBorislav Petkov struct perf_event *event) 2964e1069839SBorislav Petkov { 2965e1069839SBorislav Petkov struct hw_perf_event_extra *reg; 2966e1069839SBorislav Petkov 2967e1069839SBorislav Petkov reg = &event->hw.extra_reg; 2968e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 2969e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 2970e1069839SBorislav Petkov 2971e1069839SBorislav Petkov reg = &event->hw.branch_reg; 2972e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 2973e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 2974e1069839SBorislav Petkov } 2975e1069839SBorislav Petkov 2976e1069839SBorislav Petkov static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 2977e1069839SBorislav Petkov struct perf_event *event) 2978e1069839SBorislav Petkov { 2979e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(cpuc, event); 2980e1069839SBorislav Petkov 2981e1069839SBorislav Petkov /* 2982e1069839SBorislav Petkov * is PMU has exclusive counter restrictions, then 2983e1069839SBorislav Petkov * all events are subject to and must call the 2984e1069839SBorislav Petkov * put_excl_constraints() routine 2985e1069839SBorislav Petkov */ 2986e1069839SBorislav Petkov if (cpuc->excl_cntrs) 2987e1069839SBorislav Petkov intel_put_excl_constraints(cpuc, event); 2988e1069839SBorislav Petkov } 2989e1069839SBorislav Petkov 2990e1069839SBorislav Petkov static void intel_pebs_aliases_core2(struct perf_event *event) 2991e1069839SBorislav Petkov { 2992e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2993e1069839SBorislav Petkov /* 2994e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2995e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 2996e1069839SBorislav Petkov * 2997e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2998e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.ANY_P 2999e1069839SBorislav Petkov * (0x00c0), which is a PEBS capable event, to get the same 3000e1069839SBorislav Petkov * count. 3001e1069839SBorislav Petkov * 3002e1069839SBorislav Petkov * INST_RETIRED.ANY_P counts the number of cycles that retires 3003e1069839SBorislav Petkov * CNTMASK instructions. By setting CNTMASK to a value (16) 3004e1069839SBorislav Petkov * larger than the maximum number of instructions that can be 3005e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3006e1069839SBorislav Petkov * count all cycles that retire 16 or less instructions, which 3007e1069839SBorislav Petkov * is every cycle. 3008e1069839SBorislav Petkov * 3009e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3010e1069839SBorislav Petkov */ 3011e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3012e1069839SBorislav Petkov 3013e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3014e1069839SBorislav Petkov event->hw.config = alt_config; 3015e1069839SBorislav Petkov } 3016e1069839SBorislav Petkov } 3017e1069839SBorislav Petkov 3018e1069839SBorislav Petkov static void intel_pebs_aliases_snb(struct perf_event *event) 3019e1069839SBorislav Petkov { 3020e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3021e1069839SBorislav Petkov /* 3022e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3023e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3024e1069839SBorislav Petkov * 3025e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3026e1069839SBorislav Petkov * PEBS capable. However we can use UOPS_RETIRED.ALL 3027e1069839SBorislav Petkov * (0x01c2), which is a PEBS capable event, to get the same 3028e1069839SBorislav Petkov * count. 3029e1069839SBorislav Petkov * 3030e1069839SBorislav Petkov * UOPS_RETIRED.ALL counts the number of cycles that retires 3031e1069839SBorislav Petkov * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3032e1069839SBorislav Petkov * larger than the maximum number of micro-ops that can be 3033e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3034e1069839SBorislav Petkov * count all cycles that retire 16 or less micro-ops, which 3035e1069839SBorislav Petkov * is every cycle. 3036e1069839SBorislav Petkov * 3037e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3038e1069839SBorislav Petkov */ 3039e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3040e1069839SBorislav Petkov 3041e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3042e1069839SBorislav Petkov event->hw.config = alt_config; 3043e1069839SBorislav Petkov } 3044e1069839SBorislav Petkov } 3045e1069839SBorislav Petkov 3046e1069839SBorislav Petkov static void intel_pebs_aliases_precdist(struct perf_event *event) 3047e1069839SBorislav Petkov { 3048e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3049e1069839SBorislav Petkov /* 3050e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3051e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3052e1069839SBorislav Petkov * 3053e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3054e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3055e1069839SBorislav Petkov * (0x01c0), which is a PEBS capable event, to get the same 3056e1069839SBorislav Petkov * count. 3057e1069839SBorislav Petkov * 3058e1069839SBorislav Petkov * The PREC_DIST event has special support to minimize sample 3059e1069839SBorislav Petkov * shadowing effects. One drawback is that it can be 3060e1069839SBorislav Petkov * only programmed on counter 1, but that seems like an 3061e1069839SBorislav Petkov * acceptable trade off. 3062e1069839SBorislav Petkov */ 3063e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3064e1069839SBorislav Petkov 3065e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3066e1069839SBorislav Petkov event->hw.config = alt_config; 3067e1069839SBorislav Petkov } 3068e1069839SBorislav Petkov } 3069e1069839SBorislav Petkov 3070e1069839SBorislav Petkov static void intel_pebs_aliases_ivb(struct perf_event *event) 3071e1069839SBorislav Petkov { 3072e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3073e1069839SBorislav Petkov return intel_pebs_aliases_snb(event); 3074e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3075e1069839SBorislav Petkov } 3076e1069839SBorislav Petkov 3077e1069839SBorislav Petkov static void intel_pebs_aliases_skl(struct perf_event *event) 3078e1069839SBorislav Petkov { 3079e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3080e1069839SBorislav Petkov return intel_pebs_aliases_core2(event); 3081e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3082e1069839SBorislav Petkov } 3083e1069839SBorislav Petkov 3084174afc3eSKan Liang static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3085e1069839SBorislav Petkov { 3086174afc3eSKan Liang unsigned long flags = x86_pmu.large_pebs_flags; 3087e1069839SBorislav Petkov 3088e1069839SBorislav Petkov if (event->attr.use_clockid) 3089e1069839SBorislav Petkov flags &= ~PERF_SAMPLE_TIME; 3090a47ba4d7SAndi Kleen if (!event->attr.exclude_kernel) 3091a47ba4d7SAndi Kleen flags &= ~PERF_SAMPLE_REGS_USER; 3092a47ba4d7SAndi Kleen if (event->attr.sample_regs_user & ~PEBS_REGS) 3093a47ba4d7SAndi Kleen flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3094e1069839SBorislav Petkov return flags; 3095e1069839SBorislav Petkov } 3096e1069839SBorislav Petkov 3097ed6101bbSJiri Olsa static int intel_pmu_bts_config(struct perf_event *event) 3098ed6101bbSJiri Olsa { 3099ed6101bbSJiri Olsa struct perf_event_attr *attr = &event->attr; 3100ed6101bbSJiri Olsa 310167266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) { 3102ed6101bbSJiri Olsa /* BTS is not supported by this architecture. */ 3103ed6101bbSJiri Olsa if (!x86_pmu.bts_active) 3104ed6101bbSJiri Olsa return -EOPNOTSUPP; 3105ed6101bbSJiri Olsa 3106ed6101bbSJiri Olsa /* BTS is currently only allowed for user-mode. */ 3107ed6101bbSJiri Olsa if (!attr->exclude_kernel) 3108ed6101bbSJiri Olsa return -EOPNOTSUPP; 3109ed6101bbSJiri Olsa 3110472de49fSJiri Olsa /* BTS is not allowed for precise events. */ 3111472de49fSJiri Olsa if (attr->precise_ip) 3112472de49fSJiri Olsa return -EOPNOTSUPP; 3113472de49fSJiri Olsa 3114ed6101bbSJiri Olsa /* disallow bts if conflicting events are present */ 3115ed6101bbSJiri Olsa if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3116ed6101bbSJiri Olsa return -EBUSY; 3117ed6101bbSJiri Olsa 3118ed6101bbSJiri Olsa event->destroy = hw_perf_lbr_event_destroy; 3119ed6101bbSJiri Olsa } 3120ed6101bbSJiri Olsa 3121ed6101bbSJiri Olsa return 0; 3122ed6101bbSJiri Olsa } 3123ed6101bbSJiri Olsa 3124ed6101bbSJiri Olsa static int core_pmu_hw_config(struct perf_event *event) 3125ed6101bbSJiri Olsa { 3126ed6101bbSJiri Olsa int ret = x86_pmu_hw_config(event); 3127ed6101bbSJiri Olsa 3128ed6101bbSJiri Olsa if (ret) 3129ed6101bbSJiri Olsa return ret; 3130ed6101bbSJiri Olsa 3131ed6101bbSJiri Olsa return intel_pmu_bts_config(event); 3132ed6101bbSJiri Olsa } 3133ed6101bbSJiri Olsa 3134e1069839SBorislav Petkov static int intel_pmu_hw_config(struct perf_event *event) 3135e1069839SBorislav Petkov { 3136e1069839SBorislav Petkov int ret = x86_pmu_hw_config(event); 3137e1069839SBorislav Petkov 3138e1069839SBorislav Petkov if (ret) 3139e1069839SBorislav Petkov return ret; 3140e1069839SBorislav Petkov 3141ed6101bbSJiri Olsa ret = intel_pmu_bts_config(event); 3142ed6101bbSJiri Olsa if (ret) 3143ed6101bbSJiri Olsa return ret; 3144ed6101bbSJiri Olsa 3145e1069839SBorislav Petkov if (event->attr.precise_ip) { 3146e1069839SBorislav Petkov if (!event->attr.freq) { 3147e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3148e1069839SBorislav Petkov if (!(event->attr.sample_type & 3149174afc3eSKan Liang ~intel_pmu_large_pebs_flags(event))) 3150174afc3eSKan Liang event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3151e1069839SBorislav Petkov } 3152e1069839SBorislav Petkov if (x86_pmu.pebs_aliases) 3153e1069839SBorislav Petkov x86_pmu.pebs_aliases(event); 31546cbc304fSPeter Zijlstra 31556cbc304fSPeter Zijlstra if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 31566cbc304fSPeter Zijlstra event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3157e1069839SBorislav Petkov } 3158e1069839SBorislav Petkov 3159e1069839SBorislav Petkov if (needs_branch_stack(event)) { 3160e1069839SBorislav Petkov ret = intel_pmu_setup_lbr_filter(event); 3161e1069839SBorislav Petkov if (ret) 3162e1069839SBorislav Petkov return ret; 3163e1069839SBorislav Petkov 3164e1069839SBorislav Petkov /* 3165e1069839SBorislav Petkov * BTS is set up earlier in this path, so don't account twice 3166e1069839SBorislav Petkov */ 316767266c10SJiri Olsa if (!unlikely(intel_pmu_has_bts(event))) { 3168e1069839SBorislav Petkov /* disallow lbr if conflicting events are present */ 3169e1069839SBorislav Petkov if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3170e1069839SBorislav Petkov return -EBUSY; 3171e1069839SBorislav Petkov 3172e1069839SBorislav Petkov event->destroy = hw_perf_lbr_event_destroy; 3173e1069839SBorislav Petkov } 3174e1069839SBorislav Petkov } 3175e1069839SBorislav Petkov 3176e1069839SBorislav Petkov if (event->attr.type != PERF_TYPE_RAW) 3177e1069839SBorislav Petkov return 0; 3178e1069839SBorislav Petkov 3179e1069839SBorislav Petkov if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3180e1069839SBorislav Petkov return 0; 3181e1069839SBorislav Petkov 3182e1069839SBorislav Petkov if (x86_pmu.version < 3) 3183e1069839SBorislav Petkov return -EINVAL; 3184e1069839SBorislav Petkov 3185e1069839SBorislav Petkov if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) 3186e1069839SBorislav Petkov return -EACCES; 3187e1069839SBorislav Petkov 3188e1069839SBorislav Petkov event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3189e1069839SBorislav Petkov 3190e1069839SBorislav Petkov return 0; 3191e1069839SBorislav Petkov } 3192e1069839SBorislav Petkov 3193e1069839SBorislav Petkov struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3194e1069839SBorislav Petkov { 3195e1069839SBorislav Petkov if (x86_pmu.guest_get_msrs) 3196e1069839SBorislav Petkov return x86_pmu.guest_get_msrs(nr); 3197e1069839SBorislav Petkov *nr = 0; 3198e1069839SBorislav Petkov return NULL; 3199e1069839SBorislav Petkov } 3200e1069839SBorislav Petkov EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3201e1069839SBorislav Petkov 3202e1069839SBorislav Petkov static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3203e1069839SBorislav Petkov { 3204e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3205e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3206e1069839SBorislav Petkov 3207e1069839SBorislav Petkov arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3208e1069839SBorislav Petkov arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3209e1069839SBorislav Petkov arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 32109b545c04SAndi Kleen if (x86_pmu.flags & PMU_FL_PEBS_ALL) 32119b545c04SAndi Kleen arr[0].guest &= ~cpuc->pebs_enabled; 32129b545c04SAndi Kleen else 32139b545c04SAndi Kleen arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 32149b545c04SAndi Kleen *nr = 1; 32159b545c04SAndi Kleen 32169b545c04SAndi Kleen if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3217e1069839SBorislav Petkov /* 32189b545c04SAndi Kleen * If PMU counter has PEBS enabled it is not enough to 32199b545c04SAndi Kleen * disable counter on a guest entry since PEBS memory 32209b545c04SAndi Kleen * write can overshoot guest entry and corrupt guest 32219b545c04SAndi Kleen * memory. Disabling PEBS solves the problem. 32229b545c04SAndi Kleen * 32239b545c04SAndi Kleen * Don't do this if the CPU already enforces it. 3224e1069839SBorislav Petkov */ 3225e1069839SBorislav Petkov arr[1].msr = MSR_IA32_PEBS_ENABLE; 3226e1069839SBorislav Petkov arr[1].host = cpuc->pebs_enabled; 3227e1069839SBorislav Petkov arr[1].guest = 0; 3228e1069839SBorislav Petkov *nr = 2; 32299b545c04SAndi Kleen } 32309b545c04SAndi Kleen 3231e1069839SBorislav Petkov return arr; 3232e1069839SBorislav Petkov } 3233e1069839SBorislav Petkov 3234e1069839SBorislav Petkov static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3235e1069839SBorislav Petkov { 3236e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3237e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3238e1069839SBorislav Petkov int idx; 3239e1069839SBorislav Petkov 3240e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3241e1069839SBorislav Petkov struct perf_event *event = cpuc->events[idx]; 3242e1069839SBorislav Petkov 3243e1069839SBorislav Petkov arr[idx].msr = x86_pmu_config_addr(idx); 3244e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 0; 3245e1069839SBorislav Petkov 3246e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) 3247e1069839SBorislav Petkov continue; 3248e1069839SBorislav Petkov 3249e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 3250e1069839SBorislav Petkov event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3251e1069839SBorislav Petkov 3252e1069839SBorislav Petkov if (event->attr.exclude_host) 3253e1069839SBorislav Petkov arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3254e1069839SBorislav Petkov else if (event->attr.exclude_guest) 3255e1069839SBorislav Petkov arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3256e1069839SBorislav Petkov } 3257e1069839SBorislav Petkov 3258e1069839SBorislav Petkov *nr = x86_pmu.num_counters; 3259e1069839SBorislav Petkov return arr; 3260e1069839SBorislav Petkov } 3261e1069839SBorislav Petkov 3262e1069839SBorislav Petkov static void core_pmu_enable_event(struct perf_event *event) 3263e1069839SBorislav Petkov { 3264e1069839SBorislav Petkov if (!event->attr.exclude_host) 3265e1069839SBorislav Petkov x86_pmu_enable_event(event); 3266e1069839SBorislav Petkov } 3267e1069839SBorislav Petkov 3268e1069839SBorislav Petkov static void core_pmu_enable_all(int added) 3269e1069839SBorislav Petkov { 3270e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3271e1069839SBorislav Petkov int idx; 3272e1069839SBorislav Petkov 3273e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3274e1069839SBorislav Petkov struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3275e1069839SBorislav Petkov 3276e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask) || 3277e1069839SBorislav Petkov cpuc->events[idx]->attr.exclude_host) 3278e1069839SBorislav Petkov continue; 3279e1069839SBorislav Petkov 3280e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3281e1069839SBorislav Petkov } 3282e1069839SBorislav Petkov } 3283e1069839SBorislav Petkov 3284e1069839SBorislav Petkov static int hsw_hw_config(struct perf_event *event) 3285e1069839SBorislav Petkov { 3286e1069839SBorislav Petkov int ret = intel_pmu_hw_config(event); 3287e1069839SBorislav Petkov 3288e1069839SBorislav Petkov if (ret) 3289e1069839SBorislav Petkov return ret; 3290e1069839SBorislav Petkov if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3291e1069839SBorislav Petkov return 0; 3292e1069839SBorislav Petkov event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3293e1069839SBorislav Petkov 3294e1069839SBorislav Petkov /* 3295e1069839SBorislav Petkov * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3296e1069839SBorislav Petkov * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3297e1069839SBorislav Petkov * this combination. 3298e1069839SBorislav Petkov */ 3299e1069839SBorislav Petkov if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3300e1069839SBorislav Petkov ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3301e1069839SBorislav Petkov event->attr.precise_ip > 0)) 3302e1069839SBorislav Petkov return -EOPNOTSUPP; 3303e1069839SBorislav Petkov 3304e1069839SBorislav Petkov if (event_is_checkpointed(event)) { 3305e1069839SBorislav Petkov /* 3306e1069839SBorislav Petkov * Sampling of checkpointed events can cause situations where 3307e1069839SBorislav Petkov * the CPU constantly aborts because of a overflow, which is 3308e1069839SBorislav Petkov * then checkpointed back and ignored. Forbid checkpointing 3309e1069839SBorislav Petkov * for sampling. 3310e1069839SBorislav Petkov * 3311e1069839SBorislav Petkov * But still allow a long sampling period, so that perf stat 3312e1069839SBorislav Petkov * from KVM works. 3313e1069839SBorislav Petkov */ 3314e1069839SBorislav Petkov if (event->attr.sample_period > 0 && 3315e1069839SBorislav Petkov event->attr.sample_period < 0x7fffffff) 3316e1069839SBorislav Petkov return -EOPNOTSUPP; 3317e1069839SBorislav Petkov } 3318e1069839SBorislav Petkov return 0; 3319e1069839SBorislav Petkov } 3320e1069839SBorislav Petkov 3321dd0b06b5SKan Liang static struct event_constraint counter0_constraint = 3322dd0b06b5SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3323dd0b06b5SKan Liang 3324e1069839SBorislav Petkov static struct event_constraint counter2_constraint = 3325e1069839SBorislav Petkov EVENT_CONSTRAINT(0, 0x4, 0); 3326e1069839SBorislav Petkov 3327e1069839SBorislav Petkov static struct event_constraint * 3328e1069839SBorislav Petkov hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3329e1069839SBorislav Petkov struct perf_event *event) 3330e1069839SBorislav Petkov { 3331e1069839SBorislav Petkov struct event_constraint *c; 3332e1069839SBorislav Petkov 3333e1069839SBorislav Petkov c = intel_get_event_constraints(cpuc, idx, event); 3334e1069839SBorislav Petkov 3335e1069839SBorislav Petkov /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3336e1069839SBorislav Petkov if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3337e1069839SBorislav Petkov if (c->idxmsk64 & (1U << 2)) 3338e1069839SBorislav Petkov return &counter2_constraint; 3339e1069839SBorislav Petkov return &emptyconstraint; 3340e1069839SBorislav Petkov } 3341e1069839SBorislav Petkov 3342e1069839SBorislav Petkov return c; 3343e1069839SBorislav Petkov } 3344e1069839SBorislav Petkov 3345dd0b06b5SKan Liang static struct event_constraint * 3346dd0b06b5SKan Liang glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3347dd0b06b5SKan Liang struct perf_event *event) 3348dd0b06b5SKan Liang { 3349dd0b06b5SKan Liang struct event_constraint *c; 3350dd0b06b5SKan Liang 3351dd0b06b5SKan Liang /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3352dd0b06b5SKan Liang if (event->attr.precise_ip == 3) 3353dd0b06b5SKan Liang return &counter0_constraint; 3354dd0b06b5SKan Liang 3355dd0b06b5SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 3356dd0b06b5SKan Liang 3357dd0b06b5SKan Liang return c; 3358dd0b06b5SKan Liang } 3359dd0b06b5SKan Liang 3360e1069839SBorislav Petkov /* 3361e1069839SBorislav Petkov * Broadwell: 3362e1069839SBorislav Petkov * 3363e1069839SBorislav Petkov * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3364e1069839SBorislav Petkov * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3365e1069839SBorislav Petkov * the two to enforce a minimum period of 128 (the smallest value that has bits 3366e1069839SBorislav Petkov * 0-5 cleared and >= 100). 3367e1069839SBorislav Petkov * 3368e1069839SBorislav Petkov * Because of how the code in x86_perf_event_set_period() works, the truncation 3369e1069839SBorislav Petkov * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3370e1069839SBorislav Petkov * to make up for the 'lost' events due to carrying the 'error' in period_left. 3371e1069839SBorislav Petkov * 3372e1069839SBorislav Petkov * Therefore the effective (average) period matches the requested period, 3373e1069839SBorislav Petkov * despite coarser hardware granularity. 3374e1069839SBorislav Petkov */ 3375f605cfcaSKan Liang static u64 bdw_limit_period(struct perf_event *event, u64 left) 3376e1069839SBorislav Petkov { 3377e1069839SBorislav Petkov if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3378e1069839SBorislav Petkov X86_CONFIG(.event=0xc0, .umask=0x01)) { 3379e1069839SBorislav Petkov if (left < 128) 3380e1069839SBorislav Petkov left = 128; 3381e5ea9b54SDan Carpenter left &= ~0x3fULL; 3382e1069839SBorislav Petkov } 3383e1069839SBorislav Petkov return left; 3384e1069839SBorislav Petkov } 3385e1069839SBorislav Petkov 3386e1069839SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 3387e1069839SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 3388e1069839SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 3389e1069839SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 3390e1069839SBorislav Petkov PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3391e1069839SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 3392e1069839SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3393e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx, "config:32"); 3394e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3395e1069839SBorislav Petkov 3396e1069839SBorislav Petkov static struct attribute *intel_arch_formats_attr[] = { 3397e1069839SBorislav Petkov &format_attr_event.attr, 3398e1069839SBorislav Petkov &format_attr_umask.attr, 3399e1069839SBorislav Petkov &format_attr_edge.attr, 3400e1069839SBorislav Petkov &format_attr_pc.attr, 3401e1069839SBorislav Petkov &format_attr_inv.attr, 3402e1069839SBorislav Petkov &format_attr_cmask.attr, 3403e1069839SBorislav Petkov NULL, 3404e1069839SBorislav Petkov }; 3405e1069839SBorislav Petkov 3406e1069839SBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config) 3407e1069839SBorislav Petkov { 3408e1069839SBorislav Petkov u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3409e1069839SBorislav Petkov 3410e1069839SBorislav Petkov return x86_event_sysfs_show(page, config, event); 3411e1069839SBorislav Petkov } 3412e1069839SBorislav Petkov 3413e1069839SBorislav Petkov struct intel_shared_regs *allocate_shared_regs(int cpu) 3414e1069839SBorislav Petkov { 3415e1069839SBorislav Petkov struct intel_shared_regs *regs; 3416e1069839SBorislav Petkov int i; 3417e1069839SBorislav Petkov 3418e1069839SBorislav Petkov regs = kzalloc_node(sizeof(struct intel_shared_regs), 3419e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3420e1069839SBorislav Petkov if (regs) { 3421e1069839SBorislav Petkov /* 3422e1069839SBorislav Petkov * initialize the locks to keep lockdep happy 3423e1069839SBorislav Petkov */ 3424e1069839SBorislav Petkov for (i = 0; i < EXTRA_REG_MAX; i++) 3425e1069839SBorislav Petkov raw_spin_lock_init(®s->regs[i].lock); 3426e1069839SBorislav Petkov 3427e1069839SBorislav Petkov regs->core_id = -1; 3428e1069839SBorislav Petkov } 3429e1069839SBorislav Petkov return regs; 3430e1069839SBorislav Petkov } 3431e1069839SBorislav Petkov 3432e1069839SBorislav Petkov static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3433e1069839SBorislav Petkov { 3434e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3435e1069839SBorislav Petkov 3436e1069839SBorislav Petkov c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3437e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3438e1069839SBorislav Petkov if (c) { 3439e1069839SBorislav Petkov raw_spin_lock_init(&c->lock); 3440e1069839SBorislav Petkov c->core_id = -1; 3441e1069839SBorislav Petkov } 3442e1069839SBorislav Petkov return c; 3443e1069839SBorislav Petkov } 3444e1069839SBorislav Petkov 3445e1069839SBorislav Petkov static int intel_pmu_cpu_prepare(int cpu) 3446e1069839SBorislav Petkov { 3447e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3448e1069839SBorislav Petkov 3449e1069839SBorislav Petkov if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 3450e1069839SBorislav Petkov cpuc->shared_regs = allocate_shared_regs(cpu); 3451e1069839SBorislav Petkov if (!cpuc->shared_regs) 3452e1069839SBorislav Petkov goto err; 3453e1069839SBorislav Petkov } 3454e1069839SBorislav Petkov 3455e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3456e1069839SBorislav Petkov size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 3457e1069839SBorislav Petkov 3458e1069839SBorislav Petkov cpuc->constraint_list = kzalloc(sz, GFP_KERNEL); 3459e1069839SBorislav Petkov if (!cpuc->constraint_list) 3460e1069839SBorislav Petkov goto err_shared_regs; 3461e1069839SBorislav Petkov 3462e1069839SBorislav Petkov cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 3463e1069839SBorislav Petkov if (!cpuc->excl_cntrs) 3464e1069839SBorislav Petkov goto err_constraint_list; 3465e1069839SBorislav Petkov 3466e1069839SBorislav Petkov cpuc->excl_thread_id = 0; 3467e1069839SBorislav Petkov } 3468e1069839SBorislav Petkov 346995ca792cSThomas Gleixner return 0; 3470e1069839SBorislav Petkov 3471e1069839SBorislav Petkov err_constraint_list: 3472e1069839SBorislav Petkov kfree(cpuc->constraint_list); 3473e1069839SBorislav Petkov cpuc->constraint_list = NULL; 3474e1069839SBorislav Petkov 3475e1069839SBorislav Petkov err_shared_regs: 3476e1069839SBorislav Petkov kfree(cpuc->shared_regs); 3477e1069839SBorislav Petkov cpuc->shared_regs = NULL; 3478e1069839SBorislav Petkov 3479e1069839SBorislav Petkov err: 348095ca792cSThomas Gleixner return -ENOMEM; 3481e1069839SBorislav Petkov } 3482e1069839SBorislav Petkov 34836089327fSKan Liang static void flip_smm_bit(void *data) 34846089327fSKan Liang { 34856089327fSKan Liang unsigned long set = *(unsigned long *)data; 34866089327fSKan Liang 34876089327fSKan Liang if (set > 0) { 34886089327fSKan Liang msr_set_bit(MSR_IA32_DEBUGCTLMSR, 34896089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 34906089327fSKan Liang } else { 34916089327fSKan Liang msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 34926089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 34936089327fSKan Liang } 34946089327fSKan Liang } 34956089327fSKan Liang 3496e1069839SBorislav Petkov static void intel_pmu_cpu_starting(int cpu) 3497e1069839SBorislav Petkov { 3498e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3499e1069839SBorislav Petkov int core_id = topology_core_id(cpu); 3500e1069839SBorislav Petkov int i; 3501e1069839SBorislav Petkov 3502e1069839SBorislav Petkov init_debug_store_on_cpu(cpu); 3503e1069839SBorislav Petkov /* 3504e1069839SBorislav Petkov * Deal with CPUs that don't clear their LBRs on power-up. 3505e1069839SBorislav Petkov */ 3506e1069839SBorislav Petkov intel_pmu_lbr_reset(); 3507e1069839SBorislav Petkov 3508e1069839SBorislav Petkov cpuc->lbr_sel = NULL; 3509e1069839SBorislav Petkov 35104e949e9bSKan Liang if (x86_pmu.version > 1) 35116089327fSKan Liang flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 35126089327fSKan Liang 3513af3bdb99SAndi Kleen if (x86_pmu.counter_freezing) 3514af3bdb99SAndi Kleen enable_counter_freeze(); 3515af3bdb99SAndi Kleen 3516e1069839SBorislav Petkov if (!cpuc->shared_regs) 3517e1069839SBorislav Petkov return; 3518e1069839SBorislav Petkov 3519e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 3520e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3521e1069839SBorislav Petkov struct intel_shared_regs *pc; 3522e1069839SBorislav Petkov 3523e1069839SBorislav Petkov pc = per_cpu(cpu_hw_events, i).shared_regs; 3524e1069839SBorislav Petkov if (pc && pc->core_id == core_id) { 3525e1069839SBorislav Petkov cpuc->kfree_on_online[0] = cpuc->shared_regs; 3526e1069839SBorislav Petkov cpuc->shared_regs = pc; 3527e1069839SBorislav Petkov break; 3528e1069839SBorislav Petkov } 3529e1069839SBorislav Petkov } 3530e1069839SBorislav Petkov cpuc->shared_regs->core_id = core_id; 3531e1069839SBorislav Petkov cpuc->shared_regs->refcnt++; 3532e1069839SBorislav Petkov } 3533e1069839SBorislav Petkov 3534e1069839SBorislav Petkov if (x86_pmu.lbr_sel_map) 3535e1069839SBorislav Petkov cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 3536e1069839SBorislav Petkov 3537e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3538e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 35394e71de79SZhou Chengming struct cpu_hw_events *sibling; 3540e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3541e1069839SBorislav Petkov 35424e71de79SZhou Chengming sibling = &per_cpu(cpu_hw_events, i); 35434e71de79SZhou Chengming c = sibling->excl_cntrs; 3544e1069839SBorislav Petkov if (c && c->core_id == core_id) { 3545e1069839SBorislav Petkov cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 3546e1069839SBorislav Petkov cpuc->excl_cntrs = c; 35474e71de79SZhou Chengming if (!sibling->excl_thread_id) 3548e1069839SBorislav Petkov cpuc->excl_thread_id = 1; 3549e1069839SBorislav Petkov break; 3550e1069839SBorislav Petkov } 3551e1069839SBorislav Petkov } 3552e1069839SBorislav Petkov cpuc->excl_cntrs->core_id = core_id; 3553e1069839SBorislav Petkov cpuc->excl_cntrs->refcnt++; 3554e1069839SBorislav Petkov } 3555e1069839SBorislav Petkov } 3556e1069839SBorislav Petkov 3557e1069839SBorislav Petkov static void free_excl_cntrs(int cpu) 3558e1069839SBorislav Petkov { 3559e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3560e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3561e1069839SBorislav Petkov 3562e1069839SBorislav Petkov c = cpuc->excl_cntrs; 3563e1069839SBorislav Petkov if (c) { 3564e1069839SBorislav Petkov if (c->core_id == -1 || --c->refcnt == 0) 3565e1069839SBorislav Petkov kfree(c); 3566e1069839SBorislav Petkov cpuc->excl_cntrs = NULL; 3567e1069839SBorislav Petkov kfree(cpuc->constraint_list); 3568e1069839SBorislav Petkov cpuc->constraint_list = NULL; 3569e1069839SBorislav Petkov } 3570e1069839SBorislav Petkov } 3571e1069839SBorislav Petkov 3572e1069839SBorislav Petkov static void intel_pmu_cpu_dying(int cpu) 3573e1069839SBorislav Petkov { 3574602cae04SPeter Zijlstra fini_debug_store_on_cpu(cpu); 3575602cae04SPeter Zijlstra 3576602cae04SPeter Zijlstra if (x86_pmu.counter_freezing) 3577602cae04SPeter Zijlstra disable_counter_freeze(); 3578602cae04SPeter Zijlstra } 3579602cae04SPeter Zijlstra 3580602cae04SPeter Zijlstra static void intel_pmu_cpu_dead(int cpu) 3581602cae04SPeter Zijlstra { 3582e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3583e1069839SBorislav Petkov struct intel_shared_regs *pc; 3584e1069839SBorislav Petkov 3585e1069839SBorislav Petkov pc = cpuc->shared_regs; 3586e1069839SBorislav Petkov if (pc) { 3587e1069839SBorislav Petkov if (pc->core_id == -1 || --pc->refcnt == 0) 3588e1069839SBorislav Petkov kfree(pc); 3589e1069839SBorislav Petkov cpuc->shared_regs = NULL; 3590e1069839SBorislav Petkov } 3591e1069839SBorislav Petkov 3592e1069839SBorislav Petkov free_excl_cntrs(cpu); 3593e1069839SBorislav Petkov } 3594e1069839SBorislav Petkov 3595e1069839SBorislav Petkov static void intel_pmu_sched_task(struct perf_event_context *ctx, 3596e1069839SBorislav Petkov bool sched_in) 3597e1069839SBorislav Petkov { 3598e1069839SBorislav Petkov intel_pmu_pebs_sched_task(ctx, sched_in); 3599e1069839SBorislav Petkov intel_pmu_lbr_sched_task(ctx, sched_in); 3600e1069839SBorislav Petkov } 3601e1069839SBorislav Petkov 3602e1069839SBorislav Petkov PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 3603e1069839SBorislav Petkov 3604e1069839SBorislav Petkov PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 3605e1069839SBorislav Petkov 3606e1069839SBorislav Petkov PMU_FORMAT_ATTR(frontend, "config1:0-23"); 3607e1069839SBorislav Petkov 3608e1069839SBorislav Petkov static struct attribute *intel_arch3_formats_attr[] = { 3609e1069839SBorislav Petkov &format_attr_event.attr, 3610e1069839SBorislav Petkov &format_attr_umask.attr, 3611e1069839SBorislav Petkov &format_attr_edge.attr, 3612e1069839SBorislav Petkov &format_attr_pc.attr, 3613e1069839SBorislav Petkov &format_attr_any.attr, 3614e1069839SBorislav Petkov &format_attr_inv.attr, 3615e1069839SBorislav Petkov &format_attr_cmask.attr, 3616a5df70c3SAndi Kleen NULL, 3617a5df70c3SAndi Kleen }; 3618a5df70c3SAndi Kleen 3619a5df70c3SAndi Kleen static struct attribute *hsw_format_attr[] = { 3620e1069839SBorislav Petkov &format_attr_in_tx.attr, 3621e1069839SBorislav Petkov &format_attr_in_tx_cp.attr, 3622a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3623a5df70c3SAndi Kleen &format_attr_ldlat.attr, 3624a5df70c3SAndi Kleen NULL 3625a5df70c3SAndi Kleen }; 3626e1069839SBorislav Petkov 3627a5df70c3SAndi Kleen static struct attribute *nhm_format_attr[] = { 3628a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3629a5df70c3SAndi Kleen &format_attr_ldlat.attr, 3630a5df70c3SAndi Kleen NULL 3631a5df70c3SAndi Kleen }; 3632a5df70c3SAndi Kleen 3633a5df70c3SAndi Kleen static struct attribute *slm_format_attr[] = { 3634a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3635a5df70c3SAndi Kleen NULL 3636e1069839SBorislav Petkov }; 3637e1069839SBorislav Petkov 3638e1069839SBorislav Petkov static struct attribute *skl_format_attr[] = { 3639e1069839SBorislav Petkov &format_attr_frontend.attr, 3640e1069839SBorislav Petkov NULL, 3641e1069839SBorislav Petkov }; 3642e1069839SBorislav Petkov 3643e1069839SBorislav Petkov static __initconst const struct x86_pmu core_pmu = { 3644e1069839SBorislav Petkov .name = "core", 3645e1069839SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 3646e1069839SBorislav Petkov .disable_all = x86_pmu_disable_all, 3647e1069839SBorislav Petkov .enable_all = core_pmu_enable_all, 3648e1069839SBorislav Petkov .enable = core_pmu_enable_event, 3649e1069839SBorislav Petkov .disable = x86_pmu_disable_event, 3650ed6101bbSJiri Olsa .hw_config = core_pmu_hw_config, 3651e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 3652e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3653e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3654e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 3655e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3656e1069839SBorislav Petkov .apic = 1, 3657174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 3658e1069839SBorislav Petkov 3659e1069839SBorislav Petkov /* 3660e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32-bit width, 3661e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 3662e1069839SBorislav Petkov * the generic event period: 3663e1069839SBorislav Petkov */ 3664e1069839SBorislav Petkov .max_period = (1ULL<<31) - 1, 3665e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 3666e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 3667e1069839SBorislav Petkov .event_constraints = intel_core_event_constraints, 3668e1069839SBorislav Petkov .guest_get_msrs = core_guest_get_msrs, 3669e1069839SBorislav Petkov .format_attrs = intel_arch_formats_attr, 3670e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 3671e1069839SBorislav Petkov 3672e1069839SBorislav Petkov /* 3673e1069839SBorislav Petkov * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 3674e1069839SBorislav Petkov * together with PMU version 1 and thus be using core_pmu with 3675e1069839SBorislav Petkov * shared_regs. We need following callbacks here to allocate 3676e1069839SBorislav Petkov * it properly. 3677e1069839SBorislav Petkov */ 3678e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 3679e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 3680e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 3681602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 3682e1069839SBorislav Petkov }; 3683e1069839SBorislav Petkov 36844e949e9bSKan Liang static struct attribute *intel_pmu_attrs[]; 36854e949e9bSKan Liang 3686e1069839SBorislav Petkov static __initconst const struct x86_pmu intel_pmu = { 3687e1069839SBorislav Petkov .name = "Intel", 3688e1069839SBorislav Petkov .handle_irq = intel_pmu_handle_irq, 3689e1069839SBorislav Petkov .disable_all = intel_pmu_disable_all, 3690e1069839SBorislav Petkov .enable_all = intel_pmu_enable_all, 3691e1069839SBorislav Petkov .enable = intel_pmu_enable_event, 3692e1069839SBorislav Petkov .disable = intel_pmu_disable_event, 369368f7082fSPeter Zijlstra .add = intel_pmu_add_event, 369468f7082fSPeter Zijlstra .del = intel_pmu_del_event, 3695ceb90d9eSKan Liang .read = intel_pmu_read_event, 3696e1069839SBorislav Petkov .hw_config = intel_pmu_hw_config, 3697e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 3698e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3699e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3700e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 3701e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3702e1069839SBorislav Petkov .apic = 1, 3703174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 3704e1069839SBorislav Petkov /* 3705e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32 bit width, 3706e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 3707e1069839SBorislav Petkov * the generic event period: 3708e1069839SBorislav Petkov */ 3709e1069839SBorislav Petkov .max_period = (1ULL << 31) - 1, 3710e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 3711e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 3712e1069839SBorislav Petkov .pebs_aliases = intel_pebs_aliases_core2, 3713e1069839SBorislav Petkov 3714e1069839SBorislav Petkov .format_attrs = intel_arch3_formats_attr, 3715e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 3716e1069839SBorislav Petkov 37174e949e9bSKan Liang .attrs = intel_pmu_attrs, 37184e949e9bSKan Liang 3719e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 3720e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 3721e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 3722602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 3723602cae04SPeter Zijlstra 3724e1069839SBorislav Petkov .guest_get_msrs = intel_guest_get_msrs, 3725e1069839SBorislav Petkov .sched_task = intel_pmu_sched_task, 3726e1069839SBorislav Petkov }; 3727e1069839SBorislav Petkov 3728e1069839SBorislav Petkov static __init void intel_clovertown_quirk(void) 3729e1069839SBorislav Petkov { 3730e1069839SBorislav Petkov /* 3731e1069839SBorislav Petkov * PEBS is unreliable due to: 3732e1069839SBorislav Petkov * 3733e1069839SBorislav Petkov * AJ67 - PEBS may experience CPL leaks 3734e1069839SBorislav Petkov * AJ68 - PEBS PMI may be delayed by one event 3735e1069839SBorislav Petkov * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 3736e1069839SBorislav Petkov * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 3737e1069839SBorislav Petkov * 3738e1069839SBorislav Petkov * AJ67 could be worked around by restricting the OS/USR flags. 3739e1069839SBorislav Petkov * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 3740e1069839SBorislav Petkov * 3741e1069839SBorislav Petkov * AJ106 could possibly be worked around by not allowing LBR 3742e1069839SBorislav Petkov * usage from PEBS, including the fixup. 3743e1069839SBorislav Petkov * AJ68 could possibly be worked around by always programming 3744e1069839SBorislav Petkov * a pebs_event_reset[0] value and coping with the lost events. 3745e1069839SBorislav Petkov * 3746e1069839SBorislav Petkov * But taken together it might just make sense to not enable PEBS on 3747e1069839SBorislav Petkov * these chips. 3748e1069839SBorislav Petkov */ 3749e1069839SBorislav Petkov pr_warn("PEBS disabled due to CPU errata\n"); 3750e1069839SBorislav Petkov x86_pmu.pebs = 0; 3751e1069839SBorislav Petkov x86_pmu.pebs_constraints = NULL; 3752e1069839SBorislav Petkov } 3753e1069839SBorislav Petkov 37549b545c04SAndi Kleen static const struct x86_cpu_desc isolation_ucodes[] = { 37559b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_CORE, 3, 0x0000001f), 37569b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_ULT, 1, 0x0000001e), 37579b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_GT3E, 1, 0x00000015), 37589b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 37599b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 37609b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_CORE, 4, 0x00000023), 37619b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_GT3E, 1, 0x00000014), 37629b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 2, 0x00000010), 37639b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 3, 0x07000009), 37649b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 4, 0x0f000009), 37659b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D, 5, 0x0e000002), 37669b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014), 37679b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 37689b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 37699b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_MOBILE, 3, 0x0000007c), 37709b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_DESKTOP, 3, 0x0000007c), 37719b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 9, 0x0000004e), 37729b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 9, 0x0000004e), 37739b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 10, 0x0000004e), 37749b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 11, 0x0000004e), 37759b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_MOBILE, 12, 0x0000004e), 37769b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 10, 0x0000004e), 37779b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 11, 0x0000004e), 37789b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 12, 0x0000004e), 37799b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_DESKTOP, 13, 0x0000004e), 37809b545c04SAndi Kleen {} 37819b545c04SAndi Kleen }; 37829b545c04SAndi Kleen 37839b545c04SAndi Kleen static void intel_check_pebs_isolation(void) 37849b545c04SAndi Kleen { 37859b545c04SAndi Kleen x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 37869b545c04SAndi Kleen } 37879b545c04SAndi Kleen 37889b545c04SAndi Kleen static __init void intel_pebs_isolation_quirk(void) 37899b545c04SAndi Kleen { 37909b545c04SAndi Kleen WARN_ON_ONCE(x86_pmu.check_microcode); 37919b545c04SAndi Kleen x86_pmu.check_microcode = intel_check_pebs_isolation; 37929b545c04SAndi Kleen intel_check_pebs_isolation(); 37939b545c04SAndi Kleen } 37949b545c04SAndi Kleen 3795a96fff8dSKan Liang static const struct x86_cpu_desc pebs_ucodes[] = { 3796a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 3797a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 3798a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 3799a96fff8dSKan Liang {} 3800a96fff8dSKan Liang }; 3801a96fff8dSKan Liang 3802a96fff8dSKan Liang static bool intel_snb_pebs_broken(void) 3803e1069839SBorislav Petkov { 3804a96fff8dSKan Liang return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 3805e1069839SBorislav Petkov } 3806e1069839SBorislav Petkov 3807e1069839SBorislav Petkov static void intel_snb_check_microcode(void) 3808e1069839SBorislav Petkov { 3809a96fff8dSKan Liang if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 3810e1069839SBorislav Petkov return; 3811e1069839SBorislav Petkov 3812e1069839SBorislav Petkov /* 3813e1069839SBorislav Petkov * Serialized by the microcode lock.. 3814e1069839SBorislav Petkov */ 3815e1069839SBorislav Petkov if (x86_pmu.pebs_broken) { 3816e1069839SBorislav Petkov pr_info("PEBS enabled due to microcode update\n"); 3817e1069839SBorislav Petkov x86_pmu.pebs_broken = 0; 3818e1069839SBorislav Petkov } else { 3819e1069839SBorislav Petkov pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 3820e1069839SBorislav Petkov x86_pmu.pebs_broken = 1; 3821e1069839SBorislav Petkov } 3822e1069839SBorislav Petkov } 3823e1069839SBorislav Petkov 382419fc9dddSDavid Carrillo-Cisneros static bool is_lbr_from(unsigned long msr) 382519fc9dddSDavid Carrillo-Cisneros { 382619fc9dddSDavid Carrillo-Cisneros unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 382719fc9dddSDavid Carrillo-Cisneros 382819fc9dddSDavid Carrillo-Cisneros return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 382919fc9dddSDavid Carrillo-Cisneros } 383019fc9dddSDavid Carrillo-Cisneros 3831e1069839SBorislav Petkov /* 3832e1069839SBorislav Petkov * Under certain circumstances, access certain MSR may cause #GP. 3833e1069839SBorislav Petkov * The function tests if the input MSR can be safely accessed. 3834e1069839SBorislav Petkov */ 3835e1069839SBorislav Petkov static bool check_msr(unsigned long msr, u64 mask) 3836e1069839SBorislav Petkov { 3837e1069839SBorislav Petkov u64 val_old, val_new, val_tmp; 3838e1069839SBorislav Petkov 3839e1069839SBorislav Petkov /* 3840e1069839SBorislav Petkov * Read the current value, change it and read it back to see if it 3841e1069839SBorislav Petkov * matches, this is needed to detect certain hardware emulators 3842e1069839SBorislav Petkov * (qemu/kvm) that don't trap on the MSR access and always return 0s. 3843e1069839SBorislav Petkov */ 3844e1069839SBorislav Petkov if (rdmsrl_safe(msr, &val_old)) 3845e1069839SBorislav Petkov return false; 3846e1069839SBorislav Petkov 3847e1069839SBorislav Petkov /* 3848e1069839SBorislav Petkov * Only change the bits which can be updated by wrmsrl. 3849e1069839SBorislav Petkov */ 3850e1069839SBorislav Petkov val_tmp = val_old ^ mask; 385119fc9dddSDavid Carrillo-Cisneros 385219fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 385319fc9dddSDavid Carrillo-Cisneros val_tmp = lbr_from_signext_quirk_wr(val_tmp); 385419fc9dddSDavid Carrillo-Cisneros 3855e1069839SBorislav Petkov if (wrmsrl_safe(msr, val_tmp) || 3856e1069839SBorislav Petkov rdmsrl_safe(msr, &val_new)) 3857e1069839SBorislav Petkov return false; 3858e1069839SBorislav Petkov 385919fc9dddSDavid Carrillo-Cisneros /* 386019fc9dddSDavid Carrillo-Cisneros * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 386119fc9dddSDavid Carrillo-Cisneros * should equal rdmsrl()'s even with the quirk. 386219fc9dddSDavid Carrillo-Cisneros */ 3863e1069839SBorislav Petkov if (val_new != val_tmp) 3864e1069839SBorislav Petkov return false; 3865e1069839SBorislav Petkov 386619fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 386719fc9dddSDavid Carrillo-Cisneros val_old = lbr_from_signext_quirk_wr(val_old); 386819fc9dddSDavid Carrillo-Cisneros 3869e1069839SBorislav Petkov /* Here it's sure that the MSR can be safely accessed. 3870e1069839SBorislav Petkov * Restore the old value and return. 3871e1069839SBorislav Petkov */ 3872e1069839SBorislav Petkov wrmsrl(msr, val_old); 3873e1069839SBorislav Petkov 3874e1069839SBorislav Petkov return true; 3875e1069839SBorislav Petkov } 3876e1069839SBorislav Petkov 3877e1069839SBorislav Petkov static __init void intel_sandybridge_quirk(void) 3878e1069839SBorislav Petkov { 3879e1069839SBorislav Petkov x86_pmu.check_microcode = intel_snb_check_microcode; 38801ba143a5SSebastian Andrzej Siewior cpus_read_lock(); 3881e1069839SBorislav Petkov intel_snb_check_microcode(); 38821ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 3883e1069839SBorislav Petkov } 3884e1069839SBorislav Petkov 3885e1069839SBorislav Petkov static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 3886e1069839SBorislav Petkov { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 3887e1069839SBorislav Petkov { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 3888e1069839SBorislav Petkov { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 3889e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 3890e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 3891e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 3892e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 3893e1069839SBorislav Petkov }; 3894e1069839SBorislav Petkov 3895e1069839SBorislav Petkov static __init void intel_arch_events_quirk(void) 3896e1069839SBorislav Petkov { 3897e1069839SBorislav Petkov int bit; 3898e1069839SBorislav Petkov 3899e1069839SBorislav Petkov /* disable event that reported as not presend by cpuid */ 3900e1069839SBorislav Petkov for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 3901e1069839SBorislav Petkov intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 3902e1069839SBorislav Petkov pr_warn("CPUID marked event: \'%s\' unavailable\n", 3903e1069839SBorislav Petkov intel_arch_events_map[bit].name); 3904e1069839SBorislav Petkov } 3905e1069839SBorislav Petkov } 3906e1069839SBorislav Petkov 3907e1069839SBorislav Petkov static __init void intel_nehalem_quirk(void) 3908e1069839SBorislav Petkov { 3909e1069839SBorislav Petkov union cpuid10_ebx ebx; 3910e1069839SBorislav Petkov 3911e1069839SBorislav Petkov ebx.full = x86_pmu.events_maskl; 3912e1069839SBorislav Petkov if (ebx.split.no_branch_misses_retired) { 3913e1069839SBorislav Petkov /* 3914e1069839SBorislav Petkov * Erratum AAJ80 detected, we work it around by using 3915e1069839SBorislav Petkov * the BR_MISP_EXEC.ANY event. This will over-count 3916e1069839SBorislav Petkov * branch-misses, but it's still much better than the 3917e1069839SBorislav Petkov * architectural event which is often completely bogus: 3918e1069839SBorislav Petkov */ 3919e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 3920e1069839SBorislav Petkov ebx.split.no_branch_misses_retired = 0; 3921e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 3922e1069839SBorislav Petkov pr_info("CPU erratum AAJ80 worked around\n"); 3923e1069839SBorislav Petkov } 3924e1069839SBorislav Petkov } 3925e1069839SBorislav Petkov 3926bef9f271SKan Liang static const struct x86_cpu_desc counter_freezing_ucodes[] = { 3927bef9f271SKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028), 3928bef9f271SKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006), 3929bef9f271SKan Liang {} 3930bef9f271SKan Liang }; 3931bef9f271SKan Liang 3932bef9f271SKan Liang static bool intel_counter_freezing_broken(void) 39337c5314b8SKan Liang { 3934bef9f271SKan Liang return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes); 39357c5314b8SKan Liang } 39367c5314b8SKan Liang 3937bef9f271SKan Liang static __init void intel_counter_freezing_quirk(void) 39387c5314b8SKan Liang { 39397c5314b8SKan Liang /* Check if it's already disabled */ 39407c5314b8SKan Liang if (disable_counter_freezing) 39417c5314b8SKan Liang return; 39427c5314b8SKan Liang 39437c5314b8SKan Liang /* 39447c5314b8SKan Liang * If the system starts with the wrong ucode, leave the 39457c5314b8SKan Liang * counter-freezing feature permanently disabled. 39467c5314b8SKan Liang */ 3947bef9f271SKan Liang if (intel_counter_freezing_broken()) { 39487c5314b8SKan Liang pr_info("PMU counter freezing disabled due to CPU errata," 39497c5314b8SKan Liang "please upgrade microcode\n"); 39507c5314b8SKan Liang x86_pmu.counter_freezing = false; 39517c5314b8SKan Liang x86_pmu.handle_irq = intel_pmu_handle_irq; 39527c5314b8SKan Liang } 39537c5314b8SKan Liang } 39547c5314b8SKan Liang 3955e1069839SBorislav Petkov /* 3956e1069839SBorislav Petkov * enable software workaround for errata: 3957e1069839SBorislav Petkov * SNB: BJ122 3958e1069839SBorislav Petkov * IVB: BV98 3959e1069839SBorislav Petkov * HSW: HSD29 3960e1069839SBorislav Petkov * 3961e1069839SBorislav Petkov * Only needed when HT is enabled. However detecting 3962e1069839SBorislav Petkov * if HT is enabled is difficult (model specific). So instead, 3963e1069839SBorislav Petkov * we enable the workaround in the early boot, and verify if 3964e1069839SBorislav Petkov * it is needed in a later initcall phase once we have valid 3965e1069839SBorislav Petkov * topology information to check if HT is actually enabled 3966e1069839SBorislav Petkov */ 3967e1069839SBorislav Petkov static __init void intel_ht_bug(void) 3968e1069839SBorislav Petkov { 3969e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 3970e1069839SBorislav Petkov 3971e1069839SBorislav Petkov x86_pmu.start_scheduling = intel_start_scheduling; 3972e1069839SBorislav Petkov x86_pmu.commit_scheduling = intel_commit_scheduling; 3973e1069839SBorislav Petkov x86_pmu.stop_scheduling = intel_stop_scheduling; 3974e1069839SBorislav Petkov } 3975e1069839SBorislav Petkov 3976e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 3977e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 3978e1069839SBorislav Petkov 3979e1069839SBorislav Petkov /* Haswell special events */ 3980e1069839SBorislav Petkov EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 3981e1069839SBorislav Petkov EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 3982e1069839SBorislav Petkov EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 3983e1069839SBorislav Petkov EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 3984e1069839SBorislav Petkov EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 3985e1069839SBorislav Petkov EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 3986e1069839SBorislav Petkov EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 3987e1069839SBorislav Petkov EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 3988e1069839SBorislav Petkov EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 3989e1069839SBorislav Petkov EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 3990e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 3991e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 3992e1069839SBorislav Petkov 3993e1069839SBorislav Petkov static struct attribute *hsw_events_attrs[] = { 399458ba4d5aSAndi Kleen EVENT_PTR(td_slots_issued), 399558ba4d5aSAndi Kleen EVENT_PTR(td_slots_retired), 399658ba4d5aSAndi Kleen EVENT_PTR(td_fetch_bubbles), 399758ba4d5aSAndi Kleen EVENT_PTR(td_total_slots), 399858ba4d5aSAndi Kleen EVENT_PTR(td_total_slots_scale), 399958ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles), 400058ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 400158ba4d5aSAndi Kleen NULL 400258ba4d5aSAndi Kleen }; 400358ba4d5aSAndi Kleen 4004d4ae5529SJiri Olsa static struct attribute *hsw_mem_events_attrs[] = { 4005d4ae5529SJiri Olsa EVENT_PTR(mem_ld_hsw), 4006d4ae5529SJiri Olsa EVENT_PTR(mem_st_hsw), 4007d4ae5529SJiri Olsa NULL, 4008d4ae5529SJiri Olsa }; 4009d4ae5529SJiri Olsa 401058ba4d5aSAndi Kleen static struct attribute *hsw_tsx_events_attrs[] = { 4011e1069839SBorislav Petkov EVENT_PTR(tx_start), 4012e1069839SBorislav Petkov EVENT_PTR(tx_commit), 4013e1069839SBorislav Petkov EVENT_PTR(tx_abort), 4014e1069839SBorislav Petkov EVENT_PTR(tx_capacity), 4015e1069839SBorislav Petkov EVENT_PTR(tx_conflict), 4016e1069839SBorislav Petkov EVENT_PTR(el_start), 4017e1069839SBorislav Petkov EVENT_PTR(el_commit), 4018e1069839SBorislav Petkov EVENT_PTR(el_abort), 4019e1069839SBorislav Petkov EVENT_PTR(el_capacity), 4020e1069839SBorislav Petkov EVENT_PTR(el_conflict), 4021e1069839SBorislav Petkov EVENT_PTR(cycles_t), 4022e1069839SBorislav Petkov EVENT_PTR(cycles_ct), 4023e1069839SBorislav Petkov NULL 4024e1069839SBorislav Petkov }; 4025e1069839SBorislav Petkov 40266089327fSKan Liang static ssize_t freeze_on_smi_show(struct device *cdev, 40276089327fSKan Liang struct device_attribute *attr, 40286089327fSKan Liang char *buf) 40296089327fSKan Liang { 40306089327fSKan Liang return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 40316089327fSKan Liang } 40326089327fSKan Liang 40336089327fSKan Liang static DEFINE_MUTEX(freeze_on_smi_mutex); 40346089327fSKan Liang 40356089327fSKan Liang static ssize_t freeze_on_smi_store(struct device *cdev, 40366089327fSKan Liang struct device_attribute *attr, 40376089327fSKan Liang const char *buf, size_t count) 40386089327fSKan Liang { 40396089327fSKan Liang unsigned long val; 40406089327fSKan Liang ssize_t ret; 40416089327fSKan Liang 40426089327fSKan Liang ret = kstrtoul(buf, 0, &val); 40436089327fSKan Liang if (ret) 40446089327fSKan Liang return ret; 40456089327fSKan Liang 40466089327fSKan Liang if (val > 1) 40476089327fSKan Liang return -EINVAL; 40486089327fSKan Liang 40496089327fSKan Liang mutex_lock(&freeze_on_smi_mutex); 40506089327fSKan Liang 40516089327fSKan Liang if (x86_pmu.attr_freeze_on_smi == val) 40526089327fSKan Liang goto done; 40536089327fSKan Liang 40546089327fSKan Liang x86_pmu.attr_freeze_on_smi = val; 40556089327fSKan Liang 40566089327fSKan Liang get_online_cpus(); 40576089327fSKan Liang on_each_cpu(flip_smm_bit, &val, 1); 40586089327fSKan Liang put_online_cpus(); 40596089327fSKan Liang done: 40606089327fSKan Liang mutex_unlock(&freeze_on_smi_mutex); 40616089327fSKan Liang 40626089327fSKan Liang return count; 40636089327fSKan Liang } 40646089327fSKan Liang 40656089327fSKan Liang static DEVICE_ATTR_RW(freeze_on_smi); 40666089327fSKan Liang 4067b00233b5SAndi Kleen static ssize_t branches_show(struct device *cdev, 4068b00233b5SAndi Kleen struct device_attribute *attr, 4069b00233b5SAndi Kleen char *buf) 4070b00233b5SAndi Kleen { 4071b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4072b00233b5SAndi Kleen } 4073b00233b5SAndi Kleen 4074b00233b5SAndi Kleen static DEVICE_ATTR_RO(branches); 4075b00233b5SAndi Kleen 4076b00233b5SAndi Kleen static struct attribute *lbr_attrs[] = { 4077b00233b5SAndi Kleen &dev_attr_branches.attr, 4078b00233b5SAndi Kleen NULL 4079b00233b5SAndi Kleen }; 4080b00233b5SAndi Kleen 4081b00233b5SAndi Kleen static char pmu_name_str[30]; 4082b00233b5SAndi Kleen 4083b00233b5SAndi Kleen static ssize_t pmu_name_show(struct device *cdev, 4084b00233b5SAndi Kleen struct device_attribute *attr, 4085b00233b5SAndi Kleen char *buf) 4086b00233b5SAndi Kleen { 4087b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4088b00233b5SAndi Kleen } 4089b00233b5SAndi Kleen 4090b00233b5SAndi Kleen static DEVICE_ATTR_RO(pmu_name); 4091b00233b5SAndi Kleen 4092b00233b5SAndi Kleen static struct attribute *intel_pmu_caps_attrs[] = { 4093b00233b5SAndi Kleen &dev_attr_pmu_name.attr, 4094b00233b5SAndi Kleen NULL 4095b00233b5SAndi Kleen }; 4096b00233b5SAndi Kleen 40976089327fSKan Liang static struct attribute *intel_pmu_attrs[] = { 40986089327fSKan Liang &dev_attr_freeze_on_smi.attr, 40996089327fSKan Liang NULL, 41006089327fSKan Liang }; 41016089327fSKan Liang 4102d4ae5529SJiri Olsa static __init struct attribute ** 4103d4ae5529SJiri Olsa get_events_attrs(struct attribute **base, 4104d4ae5529SJiri Olsa struct attribute **mem, 4105d4ae5529SJiri Olsa struct attribute **tsx) 4106d4ae5529SJiri Olsa { 4107d4ae5529SJiri Olsa struct attribute **attrs = base; 4108d4ae5529SJiri Olsa struct attribute **old; 4109d4ae5529SJiri Olsa 4110d4ae5529SJiri Olsa if (mem && x86_pmu.pebs) 4111d4ae5529SJiri Olsa attrs = merge_attr(attrs, mem); 4112d4ae5529SJiri Olsa 4113d4ae5529SJiri Olsa if (tsx && boot_cpu_has(X86_FEATURE_RTM)) { 4114d4ae5529SJiri Olsa old = attrs; 4115d4ae5529SJiri Olsa attrs = merge_attr(attrs, tsx); 4116d4ae5529SJiri Olsa if (old != base) 4117d4ae5529SJiri Olsa kfree(old); 4118d4ae5529SJiri Olsa } 4119d4ae5529SJiri Olsa 4120d4ae5529SJiri Olsa return attrs; 4121d4ae5529SJiri Olsa } 4122d4ae5529SJiri Olsa 4123e1069839SBorislav Petkov __init int intel_pmu_init(void) 4124e1069839SBorislav Petkov { 41257ad1437dSThomas Gleixner struct attribute **extra_attr = NULL; 4126d4ae5529SJiri Olsa struct attribute **mem_attr = NULL; 4127d4ae5529SJiri Olsa struct attribute **tsx_attr = NULL; 41287ad1437dSThomas Gleixner struct attribute **to_free = NULL; 4129e1069839SBorislav Petkov union cpuid10_edx edx; 4130e1069839SBorislav Petkov union cpuid10_eax eax; 4131e1069839SBorislav Petkov union cpuid10_ebx ebx; 4132e1069839SBorislav Petkov struct event_constraint *c; 4133e1069839SBorislav Petkov unsigned int unused; 4134e1069839SBorislav Petkov struct extra_reg *er; 4135e1069839SBorislav Petkov int version, i; 4136b00233b5SAndi Kleen char *name; 4137e1069839SBorislav Petkov 4138e1069839SBorislav Petkov if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4139e1069839SBorislav Petkov switch (boot_cpu_data.x86) { 4140e1069839SBorislav Petkov case 0x6: 4141e1069839SBorislav Petkov return p6_pmu_init(); 4142e1069839SBorislav Petkov case 0xb: 4143e1069839SBorislav Petkov return knc_pmu_init(); 4144e1069839SBorislav Petkov case 0xf: 4145e1069839SBorislav Petkov return p4_pmu_init(); 4146e1069839SBorislav Petkov } 4147e1069839SBorislav Petkov return -ENODEV; 4148e1069839SBorislav Petkov } 4149e1069839SBorislav Petkov 4150e1069839SBorislav Petkov /* 4151e1069839SBorislav Petkov * Check whether the Architectural PerfMon supports 4152e1069839SBorislav Petkov * Branch Misses Retired hw_event or not. 4153e1069839SBorislav Petkov */ 4154e1069839SBorislav Petkov cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4155e1069839SBorislav Petkov if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4156e1069839SBorislav Petkov return -ENODEV; 4157e1069839SBorislav Petkov 4158e1069839SBorislav Petkov version = eax.split.version_id; 4159e1069839SBorislav Petkov if (version < 2) 4160e1069839SBorislav Petkov x86_pmu = core_pmu; 4161e1069839SBorislav Petkov else 4162e1069839SBorislav Petkov x86_pmu = intel_pmu; 4163e1069839SBorislav Petkov 4164e1069839SBorislav Petkov x86_pmu.version = version; 4165e1069839SBorislav Petkov x86_pmu.num_counters = eax.split.num_counters; 4166e1069839SBorislav Petkov x86_pmu.cntval_bits = eax.split.bit_width; 4167e1069839SBorislav Petkov x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4168e1069839SBorislav Petkov 4169e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4170e1069839SBorislav Petkov x86_pmu.events_mask_len = eax.split.mask_length; 4171e1069839SBorislav Petkov 4172e1069839SBorislav Petkov x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4173e1069839SBorislav Petkov 4174e1069839SBorislav Petkov /* 4175e1069839SBorislav Petkov * Quirk: v2 perfmon does not report fixed-purpose events, so 4176f92b7604SImre Palik * assume at least 3 events, when not running in a hypervisor: 4177e1069839SBorislav Petkov */ 4178f92b7604SImre Palik if (version > 1) { 4179f92b7604SImre Palik int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4180f92b7604SImre Palik 4181f92b7604SImre Palik x86_pmu.num_counters_fixed = 4182f92b7604SImre Palik max((int)edx.split.num_counters_fixed, assume); 4183f92b7604SImre Palik } 4184e1069839SBorislav Petkov 4185af3bdb99SAndi Kleen if (version >= 4) 4186af3bdb99SAndi Kleen x86_pmu.counter_freezing = !disable_counter_freezing; 4187af3bdb99SAndi Kleen 4188e1069839SBorislav Petkov if (boot_cpu_has(X86_FEATURE_PDCM)) { 4189e1069839SBorislav Petkov u64 capabilities; 4190e1069839SBorislav Petkov 4191e1069839SBorislav Petkov rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4192e1069839SBorislav Petkov x86_pmu.intel_cap.capabilities = capabilities; 4193e1069839SBorislav Petkov } 4194e1069839SBorislav Petkov 4195e1069839SBorislav Petkov intel_ds_init(); 4196e1069839SBorislav Petkov 4197e1069839SBorislav Petkov x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 4198e1069839SBorislav Petkov 4199e1069839SBorislav Petkov /* 4200e1069839SBorislav Petkov * Install the hw-cache-events table: 4201e1069839SBorislav Petkov */ 4202e1069839SBorislav Petkov switch (boot_cpu_data.x86_model) { 4203ef5f9f47SDave Hansen case INTEL_FAM6_CORE_YONAH: 4204e1069839SBorislav Petkov pr_cont("Core events, "); 4205b00233b5SAndi Kleen name = "core"; 4206e1069839SBorislav Petkov break; 4207e1069839SBorislav Petkov 4208ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM: 4209e1069839SBorislav Petkov x86_add_quirk(intel_clovertown_quirk); 4210ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM_L: 4211ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_PENRYN: 4212ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_DUNNINGTON: 4213e1069839SBorislav Petkov memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 4214e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4215e1069839SBorislav Petkov 4216e1069839SBorislav Petkov intel_pmu_lbr_init_core(); 4217e1069839SBorislav Petkov 4218e1069839SBorislav Petkov x86_pmu.event_constraints = intel_core2_event_constraints; 4219e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 4220e1069839SBorislav Petkov pr_cont("Core2 events, "); 4221b00233b5SAndi Kleen name = "core2"; 4222e1069839SBorislav Petkov break; 4223e1069839SBorislav Petkov 4224ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM: 4225ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EP: 4226ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EX: 4227e1069839SBorislav Petkov memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 4228e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4229e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4230e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4231e1069839SBorislav Petkov 4232e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 4233e1069839SBorislav Petkov 4234e1069839SBorislav Petkov x86_pmu.event_constraints = intel_nehalem_event_constraints; 4235e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 4236e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4237e1069839SBorislav Petkov x86_pmu.extra_regs = intel_nehalem_extra_regs; 4238e1069839SBorislav Petkov 4239d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 4240e1069839SBorislav Petkov 4241e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 4242e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4243e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4244e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4245e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4246e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4247e1069839SBorislav Petkov 4248e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 4249e1069839SBorislav Petkov x86_add_quirk(intel_nehalem_quirk); 425095298355SAndi Kleen x86_pmu.pebs_no_tlb = 1; 4251a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4252e1069839SBorislav Petkov 4253e1069839SBorislav Petkov pr_cont("Nehalem events, "); 4254b00233b5SAndi Kleen name = "nehalem"; 4255e1069839SBorislav Petkov break; 4256e1069839SBorislav Petkov 4257f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL: 4258f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL_MID: 4259f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL: 4260f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_MID: 4261f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_TABLET: 4262e1069839SBorislav Petkov memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 4263e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4264e1069839SBorislav Petkov 4265e1069839SBorislav Petkov intel_pmu_lbr_init_atom(); 4266e1069839SBorislav Petkov 4267e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 4268e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 4269e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 4270e1069839SBorislav Petkov pr_cont("Atom events, "); 4271b00233b5SAndi Kleen name = "bonnell"; 4272e1069839SBorislav Petkov break; 4273e1069839SBorislav Petkov 4274f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT: 4275f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_X: 4276f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_MID: 4277ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_AIRMONT: 4278f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_AIRMONT_MID: 4279e1069839SBorislav Petkov memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 4280e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4281e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 4282e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4283e1069839SBorislav Petkov 4284f21d5adcSKan Liang intel_pmu_lbr_init_slm(); 4285e1069839SBorislav Petkov 4286e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 4287e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4288e1069839SBorislav Petkov x86_pmu.extra_regs = intel_slm_extra_regs; 4289e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4290eb12b8ecSAndi Kleen x86_pmu.cpu_events = slm_events_attrs; 4291a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4292e1069839SBorislav Petkov pr_cont("Silvermont events, "); 4293b00233b5SAndi Kleen name = "silvermont"; 4294e1069839SBorislav Petkov break; 4295e1069839SBorislav Petkov 4296ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_GOLDMONT: 4297f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_X: 42988b92c3a7SKan Liang memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 42998b92c3a7SKan Liang sizeof(hw_cache_event_ids)); 43008b92c3a7SKan Liang memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 43018b92c3a7SKan Liang sizeof(hw_cache_extra_regs)); 43028b92c3a7SKan Liang 43038b92c3a7SKan Liang intel_pmu_lbr_init_skl(); 43048b92c3a7SKan Liang 43058b92c3a7SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 43068b92c3a7SKan Liang x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 43078b92c3a7SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 43088b92c3a7SKan Liang /* 43098b92c3a7SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 43108b92c3a7SKan Liang * for precise cycles. 43118b92c3a7SKan Liang * :pp is identical to :ppp 43128b92c3a7SKan Liang */ 43138b92c3a7SKan Liang x86_pmu.pebs_aliases = NULL; 43148b92c3a7SKan Liang x86_pmu.pebs_prec_dist = true; 4315ccbebba4SAlexander Shishkin x86_pmu.lbr_pt_coexist = true; 43168b92c3a7SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4317ed827adbSKan Liang x86_pmu.cpu_events = glm_events_attrs; 4318a5df70c3SAndi Kleen extra_attr = slm_format_attr; 43198b92c3a7SKan Liang pr_cont("Goldmont events, "); 4320b00233b5SAndi Kleen name = "goldmont"; 43218b92c3a7SKan Liang break; 43228b92c3a7SKan Liang 4323f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4324bef9f271SKan Liang x86_add_quirk(intel_counter_freezing_quirk); 4325dd0b06b5SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4326dd0b06b5SKan Liang sizeof(hw_cache_event_ids)); 4327dd0b06b5SKan Liang memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 4328dd0b06b5SKan Liang sizeof(hw_cache_extra_regs)); 4329dd0b06b5SKan Liang 4330dd0b06b5SKan Liang intel_pmu_lbr_init_skl(); 4331dd0b06b5SKan Liang 4332dd0b06b5SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 4333dd0b06b5SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 4334dd0b06b5SKan Liang /* 4335dd0b06b5SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4336dd0b06b5SKan Liang * for precise cycles. 4337dd0b06b5SKan Liang */ 4338dd0b06b5SKan Liang x86_pmu.pebs_aliases = NULL; 4339dd0b06b5SKan Liang x86_pmu.pebs_prec_dist = true; 4340dd0b06b5SKan Liang x86_pmu.lbr_pt_coexist = true; 4341dd0b06b5SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4342a38b0ba1SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 4343dd0b06b5SKan Liang x86_pmu.get_event_constraints = glp_get_event_constraints; 4344dd0b06b5SKan Liang x86_pmu.cpu_events = glm_events_attrs; 4345dd0b06b5SKan Liang /* Goldmont Plus has 4-wide pipeline */ 4346dd0b06b5SKan Liang event_attr_td_total_slots_scale_glm.event_str = "4"; 4347a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4348dd0b06b5SKan Liang pr_cont("Goldmont plus events, "); 4349b00233b5SAndi Kleen name = "goldmont_plus"; 4350dd0b06b5SKan Liang break; 4351dd0b06b5SKan Liang 4352ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE: 4353ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EP: 4354ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EX: 4355e1069839SBorislav Petkov memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 4356e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4357e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4358e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4359e1069839SBorislav Petkov 4360e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 4361e1069839SBorislav Petkov 4362e1069839SBorislav Petkov x86_pmu.event_constraints = intel_westmere_event_constraints; 4363e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4364e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 4365e1069839SBorislav Petkov x86_pmu.extra_regs = intel_westmere_extra_regs; 4366e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4367e1069839SBorislav Petkov 4368d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 4369e1069839SBorislav Petkov 4370e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 4371e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4372e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4373e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4374e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4375e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4376e1069839SBorislav Petkov 4377e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 4378a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4379e1069839SBorislav Petkov pr_cont("Westmere events, "); 4380b00233b5SAndi Kleen name = "westmere"; 4381e1069839SBorislav Petkov break; 4382e1069839SBorislav Petkov 4383ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 4384ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 4385e1069839SBorislav Petkov x86_add_quirk(intel_sandybridge_quirk); 4386e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4387e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4388e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4389e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4390e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4391e1069839SBorislav Petkov 4392e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 4393e1069839SBorislav Petkov 4394e1069839SBorislav Petkov x86_pmu.event_constraints = intel_snb_event_constraints; 4395e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 4396e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 4397ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 4398e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4399e1069839SBorislav Petkov else 4400e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 4401e1069839SBorislav Petkov 4402e1069839SBorislav Petkov 4403e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4404e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4405e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4406e1069839SBorislav Petkov 4407e1069839SBorislav Petkov x86_pmu.cpu_events = snb_events_attrs; 4408d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 4409e1069839SBorislav Petkov 4410e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4411e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4412e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4413e1069839SBorislav Petkov /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 4414e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4415e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 4416e1069839SBorislav Petkov 4417a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4418a5df70c3SAndi Kleen 4419e1069839SBorislav Petkov pr_cont("SandyBridge events, "); 4420b00233b5SAndi Kleen name = "sandybridge"; 4421e1069839SBorislav Petkov break; 4422e1069839SBorislav Petkov 4423ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE: 4424ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE_X: 4425e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4426e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4427e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4428e1069839SBorislav Petkov /* dTLB-load-misses on IVB is different than SNB */ 4429e1069839SBorislav Petkov hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 4430e1069839SBorislav Petkov 4431e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4432e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4433e1069839SBorislav Petkov 4434e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 4435e1069839SBorislav Petkov 4436e1069839SBorislav Petkov x86_pmu.event_constraints = intel_ivb_event_constraints; 4437e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 4438e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4439e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4440ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 4441e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4442e1069839SBorislav Petkov else 4443e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 4444e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4445e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4446e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4447e1069839SBorislav Petkov 4448e1069839SBorislav Petkov x86_pmu.cpu_events = snb_events_attrs; 4449d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 4450e1069839SBorislav Petkov 4451e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4452e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4453e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4454e1069839SBorislav Petkov 4455a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4456a5df70c3SAndi Kleen 4457e1069839SBorislav Petkov pr_cont("IvyBridge events, "); 4458b00233b5SAndi Kleen name = "ivybridge"; 4459e1069839SBorislav Petkov break; 4460e1069839SBorislav Petkov 4461e1069839SBorislav Petkov 4462ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_CORE: 4463ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_X: 4464ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_ULT: 4465ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_GT3E: 4466e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 44679b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 4468e1069839SBorislav Petkov x86_pmu.late_ack = true; 4469e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4470e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4471e1069839SBorislav Petkov 4472e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 4473e1069839SBorislav Petkov 4474e1069839SBorislav Petkov x86_pmu.event_constraints = intel_hsw_event_constraints; 4475e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 4476e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4477e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4478e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4479e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4480e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4481e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4482e1069839SBorislav Petkov 4483e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4484e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 4485d4ae5529SJiri Olsa x86_pmu.cpu_events = hsw_events_attrs; 4486e1069839SBorislav Petkov x86_pmu.lbr_double_abort = true; 4487a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4488a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4489d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 4490d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 4491e1069839SBorislav Petkov pr_cont("Haswell events, "); 4492b00233b5SAndi Kleen name = "haswell"; 4493e1069839SBorislav Petkov break; 4494e1069839SBorislav Petkov 4495ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_CORE: 4496ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_XEON_D: 4497ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_GT3E: 4498ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_X: 44999b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 4500e1069839SBorislav Petkov x86_pmu.late_ack = true; 4501e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4502e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4503e1069839SBorislav Petkov 4504e1069839SBorislav Petkov /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 4505e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 4506e1069839SBorislav Petkov BDW_L3_MISS|HSW_SNOOP_DRAM; 4507e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 4508e1069839SBorislav Petkov HSW_SNOOP_DRAM; 4509e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 4510e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4511e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 4512e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4513e1069839SBorislav Petkov 4514e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 4515e1069839SBorislav Petkov 4516e1069839SBorislav Petkov x86_pmu.event_constraints = intel_bdw_event_constraints; 4517b3e62463SStephane Eranian x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 4518e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4519e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4520e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4521e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4522e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4523e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4524e1069839SBorislav Petkov 4525e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4526e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 4527d4ae5529SJiri Olsa x86_pmu.cpu_events = hsw_events_attrs; 4528e1069839SBorislav Petkov x86_pmu.limit_period = bdw_limit_period; 4529a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4530a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4531d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 4532d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 4533e1069839SBorislav Petkov pr_cont("Broadwell events, "); 4534b00233b5SAndi Kleen name = "broadwell"; 4535e1069839SBorislav Petkov break; 4536e1069839SBorislav Petkov 4537ef5f9f47SDave Hansen case INTEL_FAM6_XEON_PHI_KNL: 4538608284bfSPiotr Luc case INTEL_FAM6_XEON_PHI_KNM: 4539e1069839SBorislav Petkov memcpy(hw_cache_event_ids, 4540e1069839SBorislav Petkov slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4541e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, 4542e1069839SBorislav Petkov knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4543e1069839SBorislav Petkov intel_pmu_lbr_init_knl(); 4544e1069839SBorislav Petkov 4545e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 4546e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4547e1069839SBorislav Petkov x86_pmu.extra_regs = intel_knl_extra_regs; 4548e1069839SBorislav Petkov 4549e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4550e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4551e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4552a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4553608284bfSPiotr Luc pr_cont("Knights Landing/Mill events, "); 4554b00233b5SAndi Kleen name = "knights-landing"; 4555e1069839SBorislav Petkov break; 4556e1069839SBorislav Petkov 4557ef5f9f47SDave Hansen case INTEL_FAM6_SKYLAKE_MOBILE: 4558ef5f9f47SDave Hansen case INTEL_FAM6_SKYLAKE_DESKTOP: 4559ef5f9f47SDave Hansen case INTEL_FAM6_SKYLAKE_X: 4560ef5f9f47SDave Hansen case INTEL_FAM6_KABYLAKE_MOBILE: 4561ef5f9f47SDave Hansen case INTEL_FAM6_KABYLAKE_DESKTOP: 45629b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 4563e1069839SBorislav Petkov x86_pmu.late_ack = true; 4564e1069839SBorislav Petkov memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4565e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4566e1069839SBorislav Petkov intel_pmu_lbr_init_skl(); 4567e1069839SBorislav Petkov 4568a39fcae7SAndi Kleen /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 4569a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_noht = 4570a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1"; 4571a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_ht = 4572a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1,any=1"; 4573a39fcae7SAndi Kleen 4574e1069839SBorislav Petkov x86_pmu.event_constraints = intel_skl_event_constraints; 4575e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 4576e1069839SBorislav Petkov x86_pmu.extra_regs = intel_skl_extra_regs; 4577e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 4578e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4579e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4580e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4581e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4582e1069839SBorislav Petkov 4583e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4584e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 4585a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4586a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4587a5df70c3SAndi Kleen extra_attr = merge_attr(extra_attr, skl_format_attr); 45887ad1437dSThomas Gleixner to_free = extra_attr; 4589d4ae5529SJiri Olsa x86_pmu.cpu_events = hsw_events_attrs; 4590d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 4591d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 45926ae5fa61SAndi Kleen intel_pmu_pebs_data_source_skl( 45936ae5fa61SAndi Kleen boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X); 4594e1069839SBorislav Petkov pr_cont("Skylake events, "); 4595b00233b5SAndi Kleen name = "skylake"; 4596e1069839SBorislav Petkov break; 4597e1069839SBorislav Petkov 4598e1069839SBorislav Petkov default: 4599e1069839SBorislav Petkov switch (x86_pmu.version) { 4600e1069839SBorislav Petkov case 1: 4601e1069839SBorislav Petkov x86_pmu.event_constraints = intel_v1_event_constraints; 4602e1069839SBorislav Petkov pr_cont("generic architected perfmon v1, "); 4603b00233b5SAndi Kleen name = "generic_arch_v1"; 4604e1069839SBorislav Petkov break; 4605e1069839SBorislav Petkov default: 4606e1069839SBorislav Petkov /* 4607e1069839SBorislav Petkov * default constraints for v2 and up 4608e1069839SBorislav Petkov */ 4609e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 4610e1069839SBorislav Petkov pr_cont("generic architected perfmon, "); 4611b00233b5SAndi Kleen name = "generic_arch_v2+"; 4612e1069839SBorislav Petkov break; 4613e1069839SBorislav Petkov } 4614e1069839SBorislav Petkov } 4615e1069839SBorislav Petkov 46160e96f31eSJordan Borgner snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 4617b00233b5SAndi Kleen 4618a5df70c3SAndi Kleen if (version >= 2 && extra_attr) { 4619a5df70c3SAndi Kleen x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, 4620a5df70c3SAndi Kleen extra_attr); 4621a5df70c3SAndi Kleen WARN_ON(!x86_pmu.format_attrs); 4622a5df70c3SAndi Kleen } 4623a5df70c3SAndi Kleen 4624d4ae5529SJiri Olsa x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events, 4625d4ae5529SJiri Olsa mem_attr, tsx_attr); 4626d4ae5529SJiri Olsa 4627e1069839SBorislav Petkov if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 4628e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 4629e1069839SBorislav Petkov x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 4630e1069839SBorislav Petkov x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 4631e1069839SBorislav Petkov } 4632ad5013d5SColin King x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 4633e1069839SBorislav Petkov 4634e1069839SBorislav Petkov if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 4635e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 4636e1069839SBorislav Petkov x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 4637e1069839SBorislav Petkov x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 4638e1069839SBorislav Petkov } 4639e1069839SBorislav Petkov 4640e1069839SBorislav Petkov x86_pmu.intel_ctrl |= 4641e1069839SBorislav Petkov ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 4642e1069839SBorislav Petkov 4643e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 4644e1069839SBorislav Petkov /* 4645e1069839SBorislav Petkov * event on fixed counter2 (REF_CYCLES) only works on this 4646e1069839SBorislav Petkov * counter, so do not extend mask to generic counters 4647e1069839SBorislav Petkov */ 4648e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 4649e1069839SBorislav Petkov if (c->cmask == FIXED_EVENT_FLAGS 4650e1069839SBorislav Petkov && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 4651e1069839SBorislav Petkov c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 4652e1069839SBorislav Petkov } 4653e1069839SBorislav Petkov c->idxmsk64 &= 46546d6f2833SAndrey Ryabinin ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 4655e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 4656e1069839SBorislav Petkov } 4657e1069839SBorislav Petkov } 4658e1069839SBorislav Petkov 4659e1069839SBorislav Petkov /* 4660e1069839SBorislav Petkov * Access LBR MSR may cause #GP under certain circumstances. 4661e1069839SBorislav Petkov * E.g. KVM doesn't support LBR MSR 4662e1069839SBorislav Petkov * Check all LBT MSR here. 4663e1069839SBorislav Petkov * Disable LBR access if any LBR MSRs can not be accessed. 4664e1069839SBorislav Petkov */ 4665e1069839SBorislav Petkov if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 4666e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 4667e1069839SBorislav Petkov for (i = 0; i < x86_pmu.lbr_nr; i++) { 4668e1069839SBorislav Petkov if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 4669e1069839SBorislav Petkov check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 4670e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 4671e1069839SBorislav Petkov } 4672e1069839SBorislav Petkov 4673b00233b5SAndi Kleen x86_pmu.caps_attrs = intel_pmu_caps_attrs; 4674b00233b5SAndi Kleen 4675b00233b5SAndi Kleen if (x86_pmu.lbr_nr) { 4676b00233b5SAndi Kleen x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs); 4677f09509b9SDavid Carrillo-Cisneros pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 4678b00233b5SAndi Kleen } 4679b00233b5SAndi Kleen 4680e1069839SBorislav Petkov /* 4681e1069839SBorislav Petkov * Access extra MSR may cause #GP under certain circumstances. 4682e1069839SBorislav Petkov * E.g. KVM doesn't support offcore event 4683e1069839SBorislav Petkov * Check all extra_regs here. 4684e1069839SBorislav Petkov */ 4685e1069839SBorislav Petkov if (x86_pmu.extra_regs) { 4686e1069839SBorislav Petkov for (er = x86_pmu.extra_regs; er->msr; er++) { 4687e1069839SBorislav Petkov er->extra_msr_access = check_msr(er->msr, 0x11UL); 4688e1069839SBorislav Petkov /* Disable LBR select mapping */ 4689e1069839SBorislav Petkov if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 4690e1069839SBorislav Petkov x86_pmu.lbr_sel_map = NULL; 4691e1069839SBorislav Petkov } 4692e1069839SBorislav Petkov } 4693e1069839SBorislav Petkov 4694e1069839SBorislav Petkov /* Support full width counters using alternative MSR range */ 4695e1069839SBorislav Petkov if (x86_pmu.intel_cap.full_width_write) { 46967f612a7fSPeter Zijlstra (Intel) x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 4697e1069839SBorislav Petkov x86_pmu.perfctr = MSR_IA32_PMC0; 4698e1069839SBorislav Petkov pr_cont("full-width counters, "); 4699e1069839SBorislav Petkov } 4700e1069839SBorislav Petkov 4701af3bdb99SAndi Kleen /* 4702af3bdb99SAndi Kleen * For arch perfmon 4 use counter freezing to avoid 4703af3bdb99SAndi Kleen * several MSR accesses in the PMI. 4704af3bdb99SAndi Kleen */ 4705af3bdb99SAndi Kleen if (x86_pmu.counter_freezing) 4706af3bdb99SAndi Kleen x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 4707af3bdb99SAndi Kleen 47087ad1437dSThomas Gleixner kfree(to_free); 4709e1069839SBorislav Petkov return 0; 4710e1069839SBorislav Petkov } 4711e1069839SBorislav Petkov 4712e1069839SBorislav Petkov /* 4713e1069839SBorislav Petkov * HT bug: phase 2 init 4714e1069839SBorislav Petkov * Called once we have valid topology information to check 4715e1069839SBorislav Petkov * whether or not HT is enabled 4716e1069839SBorislav Petkov * If HT is off, then we disable the workaround 4717e1069839SBorislav Petkov */ 4718e1069839SBorislav Petkov static __init int fixup_ht_bug(void) 4719e1069839SBorislav Petkov { 4720030ba6cdSAndi Kleen int c; 4721e1069839SBorislav Petkov /* 4722e1069839SBorislav Petkov * problem not present on this CPU model, nothing to do 4723e1069839SBorislav Petkov */ 4724e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 4725e1069839SBorislav Petkov return 0; 4726e1069839SBorislav Petkov 4727030ba6cdSAndi Kleen if (topology_max_smt_threads() > 1) { 4728e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 4729e1069839SBorislav Petkov return 0; 4730e1069839SBorislav Petkov } 4731e1069839SBorislav Petkov 47322406e3b1SPeter Zijlstra cpus_read_lock(); 47332406e3b1SPeter Zijlstra 47342406e3b1SPeter Zijlstra hardlockup_detector_perf_stop(); 4735e1069839SBorislav Petkov 4736e1069839SBorislav Petkov x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 4737e1069839SBorislav Petkov 4738e1069839SBorislav Petkov x86_pmu.start_scheduling = NULL; 4739e1069839SBorislav Petkov x86_pmu.commit_scheduling = NULL; 4740e1069839SBorislav Petkov x86_pmu.stop_scheduling = NULL; 4741e1069839SBorislav Petkov 47422406e3b1SPeter Zijlstra hardlockup_detector_perf_restart(); 4743e1069839SBorislav Petkov 47441ba143a5SSebastian Andrzej Siewior for_each_online_cpu(c) 4745e1069839SBorislav Petkov free_excl_cntrs(c); 4746e1069839SBorislav Petkov 47471ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 4748e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 4749e1069839SBorislav Petkov return 0; 4750e1069839SBorislav Petkov } 4751e1069839SBorislav Petkov subsys_initcall(fixup_ht_bug) 4752