1e1069839SBorislav Petkov /* 2e1069839SBorislav Petkov * Per core/cpu state 3e1069839SBorislav Petkov * 4e1069839SBorislav Petkov * Used to coordinate shared registers between HT threads or 5e1069839SBorislav Petkov * among events on a single PMU. 6e1069839SBorislav Petkov */ 7e1069839SBorislav Petkov 8e1069839SBorislav Petkov #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9e1069839SBorislav Petkov 10e1069839SBorislav Petkov #include <linux/stddef.h> 11e1069839SBorislav Petkov #include <linux/types.h> 12e1069839SBorislav Petkov #include <linux/init.h> 13e1069839SBorislav Petkov #include <linux/slab.h> 14e1069839SBorislav Petkov #include <linux/export.h> 15e1069839SBorislav Petkov #include <linux/nmi.h> 16e1069839SBorislav Petkov 17e1069839SBorislav Petkov #include <asm/cpufeature.h> 18e1069839SBorislav Petkov #include <asm/hardirq.h> 19ef5f9f47SDave Hansen #include <asm/intel-family.h> 20e1069839SBorislav Petkov #include <asm/apic.h> 21e1069839SBorislav Petkov 2227f6d22bSBorislav Petkov #include "../perf_event.h" 23e1069839SBorislav Petkov 24e1069839SBorislav Petkov /* 25e1069839SBorislav Petkov * Intel PerfMon, used on Core and later. 26e1069839SBorislav Petkov */ 27e1069839SBorislav Petkov static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 28e1069839SBorislav Petkov { 29e1069839SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 30e1069839SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 31e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 32e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 33e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 34e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 35e1069839SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 36e1069839SBorislav Petkov [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 37e1069839SBorislav Petkov }; 38e1069839SBorislav Petkov 39e1069839SBorislav Petkov static struct event_constraint intel_core_event_constraints[] __read_mostly = 40e1069839SBorislav Petkov { 41e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 42e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 43e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 44e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 45e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 46e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 47e1069839SBorislav Petkov EVENT_CONSTRAINT_END 48e1069839SBorislav Petkov }; 49e1069839SBorislav Petkov 50e1069839SBorislav Petkov static struct event_constraint intel_core2_event_constraints[] __read_mostly = 51e1069839SBorislav Petkov { 52e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 53e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 54e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 55e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 56e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 57e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 58e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 59e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 60e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 61e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 62e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 63e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 64e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 65e1069839SBorislav Petkov EVENT_CONSTRAINT_END 66e1069839SBorislav Petkov }; 67e1069839SBorislav Petkov 68e1069839SBorislav Petkov static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 69e1069839SBorislav Petkov { 70e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 71e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 72e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 73e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 74e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 75e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 76e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 77e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 78e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 79e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 80e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 81e1069839SBorislav Petkov EVENT_CONSTRAINT_END 82e1069839SBorislav Petkov }; 83e1069839SBorislav Petkov 84e1069839SBorislav Petkov static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 85e1069839SBorislav Petkov { 86e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 87e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 88e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 89e1069839SBorislav Petkov EVENT_EXTRA_END 90e1069839SBorislav Petkov }; 91e1069839SBorislav Petkov 92e1069839SBorislav Petkov static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 93e1069839SBorislav Petkov { 94e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 95e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 96e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 97e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 98e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 99e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 100e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 101e1069839SBorislav Petkov EVENT_CONSTRAINT_END 102e1069839SBorislav Petkov }; 103e1069839SBorislav Petkov 104e1069839SBorislav Petkov static struct event_constraint intel_snb_event_constraints[] __read_mostly = 105e1069839SBorislav Petkov { 106e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 107e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 108e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 109e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 110e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 111e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 112e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 113e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 114e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 115e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 116e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 117e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 118e1069839SBorislav Petkov 1199010ae4aSStephane Eranian /* 1209010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1219010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1229010ae4aSStephane Eranian */ 123e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 124e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 125e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 126e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 127e1069839SBorislav Petkov 128e1069839SBorislav Petkov EVENT_CONSTRAINT_END 129e1069839SBorislav Petkov }; 130e1069839SBorislav Petkov 131e1069839SBorislav Petkov static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 132e1069839SBorislav Petkov { 133e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 134e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 135e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 136e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 137e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 138e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 139e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 140e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 141e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 142e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 143e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 144e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 145e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 146e1069839SBorislav Petkov 1479010ae4aSStephane Eranian /* 1489010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1499010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1509010ae4aSStephane Eranian */ 151e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 152e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 153e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 154e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 155e1069839SBorislav Petkov 156e1069839SBorislav Petkov EVENT_CONSTRAINT_END 157e1069839SBorislav Petkov }; 158e1069839SBorislav Petkov 159e1069839SBorislav Petkov static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 160e1069839SBorislav Petkov { 161e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 162e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 163e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 164e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 165e1069839SBorislav Petkov EVENT_EXTRA_END 166e1069839SBorislav Petkov }; 167e1069839SBorislav Petkov 168e1069839SBorislav Petkov static struct event_constraint intel_v1_event_constraints[] __read_mostly = 169e1069839SBorislav Petkov { 170e1069839SBorislav Petkov EVENT_CONSTRAINT_END 171e1069839SBorislav Petkov }; 172e1069839SBorislav Petkov 173e1069839SBorislav Petkov static struct event_constraint intel_gen_event_constraints[] __read_mostly = 174e1069839SBorislav Petkov { 175e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 176e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 177e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 178e1069839SBorislav Petkov EVENT_CONSTRAINT_END 179e1069839SBorislav Petkov }; 180e1069839SBorislav Petkov 181e1069839SBorislav Petkov static struct event_constraint intel_slm_event_constraints[] __read_mostly = 182e1069839SBorislav Petkov { 183e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 184e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 185e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 186e1069839SBorislav Petkov EVENT_CONSTRAINT_END 187e1069839SBorislav Petkov }; 188e1069839SBorislav Petkov 18920f36278SLukasz Odzioba static struct event_constraint intel_skl_event_constraints[] = { 190e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 191e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 192e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 193e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1949010ae4aSStephane Eranian 1959010ae4aSStephane Eranian /* 1969010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 1979010ae4aSStephane Eranian */ 1989010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 1999010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 2009010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 2019010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 2029010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 2039010ae4aSStephane Eranian 204e1069839SBorislav Petkov EVENT_CONSTRAINT_END 205e1069839SBorislav Petkov }; 206e1069839SBorislav Petkov 207e1069839SBorislav Petkov static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 2089c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 2099c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 210e1069839SBorislav Petkov EVENT_EXTRA_END 211e1069839SBorislav Petkov }; 212e1069839SBorislav Petkov 213e1069839SBorislav Petkov static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 214e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 215e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 216e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 217e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 218e1069839SBorislav Petkov EVENT_EXTRA_END 219e1069839SBorislav Petkov }; 220e1069839SBorislav Petkov 221e1069839SBorislav Petkov static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 222e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 223e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 224e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 225e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 226e1069839SBorislav Petkov EVENT_EXTRA_END 227e1069839SBorislav Petkov }; 228e1069839SBorislav Petkov 229e1069839SBorislav Petkov static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 230e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 231e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 232e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 233e1069839SBorislav Petkov /* 234e1069839SBorislav Petkov * Note the low 8 bits eventsel code is not a continuous field, containing 235e1069839SBorislav Petkov * some #GPing bits. These are masked out. 236e1069839SBorislav Petkov */ 237e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 238e1069839SBorislav Petkov EVENT_EXTRA_END 239e1069839SBorislav Petkov }; 240e1069839SBorislav Petkov 241e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 242e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 243e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 244e1069839SBorislav Petkov 24520f36278SLukasz Odzioba static struct attribute *nhm_events_attrs[] = { 246e1069839SBorislav Petkov EVENT_PTR(mem_ld_nhm), 247e1069839SBorislav Petkov NULL, 248e1069839SBorislav Petkov }; 249e1069839SBorislav Petkov 250a39fcae7SAndi Kleen /* 251a39fcae7SAndi Kleen * topdown events for Intel Core CPUs. 252a39fcae7SAndi Kleen * 253a39fcae7SAndi Kleen * The events are all in slots, which is a free slot in a 4 wide 254a39fcae7SAndi Kleen * pipeline. Some events are already reported in slots, for cycle 255a39fcae7SAndi Kleen * events we multiply by the pipeline width (4). 256a39fcae7SAndi Kleen * 257a39fcae7SAndi Kleen * With Hyper Threading on, topdown metrics are either summed or averaged 258a39fcae7SAndi Kleen * between the threads of a core: (count_t0 + count_t1). 259a39fcae7SAndi Kleen * 260a39fcae7SAndi Kleen * For the average case the metric is always scaled to pipeline width, 261a39fcae7SAndi Kleen * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 262a39fcae7SAndi Kleen */ 263a39fcae7SAndi Kleen 264a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 265a39fcae7SAndi Kleen "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 266a39fcae7SAndi Kleen "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 267a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 268a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 269a39fcae7SAndi Kleen "event=0xe,umask=0x1"); /* uops_issued.any */ 270a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 271a39fcae7SAndi Kleen "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 272a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 273a39fcae7SAndi Kleen "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 274a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 275a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 276a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 277a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 278a39fcae7SAndi Kleen "4", "2"); 279a39fcae7SAndi Kleen 28020f36278SLukasz Odzioba static struct attribute *snb_events_attrs[] = { 281e1069839SBorislav Petkov EVENT_PTR(mem_ld_snb), 282e1069839SBorislav Petkov EVENT_PTR(mem_st_snb), 283a39fcae7SAndi Kleen EVENT_PTR(td_slots_issued), 284a39fcae7SAndi Kleen EVENT_PTR(td_slots_retired), 285a39fcae7SAndi Kleen EVENT_PTR(td_fetch_bubbles), 286a39fcae7SAndi Kleen EVENT_PTR(td_total_slots), 287a39fcae7SAndi Kleen EVENT_PTR(td_total_slots_scale), 288a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles), 289a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 290e1069839SBorislav Petkov NULL, 291e1069839SBorislav Petkov }; 292e1069839SBorislav Petkov 293e1069839SBorislav Petkov static struct event_constraint intel_hsw_event_constraints[] = { 294e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 295e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 296e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 297e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 298e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 299e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 300e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 301e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 302e1069839SBorislav Petkov /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 303e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 304e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 305e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 306e1069839SBorislav Petkov 3079010ae4aSStephane Eranian /* 3089010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 3099010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 3109010ae4aSStephane Eranian */ 311e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 312e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 313e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 314e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 315e1069839SBorislav Petkov 316e1069839SBorislav Petkov EVENT_CONSTRAINT_END 317e1069839SBorislav Petkov }; 318e1069839SBorislav Petkov 31920f36278SLukasz Odzioba static struct event_constraint intel_bdw_event_constraints[] = { 320e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 321e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 322e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 323e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 324e1069839SBorislav Petkov INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 3259010ae4aSStephane Eranian /* 3269010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 3279010ae4aSStephane Eranian */ 3289010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 3299010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 3309010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 3319010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 332e1069839SBorislav Petkov EVENT_CONSTRAINT_END 333e1069839SBorislav Petkov }; 334e1069839SBorislav Petkov 335e1069839SBorislav Petkov static u64 intel_pmu_event_map(int hw_event) 336e1069839SBorislav Petkov { 337e1069839SBorislav Petkov return intel_perfmon_event_map[hw_event]; 338e1069839SBorislav Petkov } 339e1069839SBorislav Petkov 340e1069839SBorislav Petkov /* 341e1069839SBorislav Petkov * Notes on the events: 342e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 343e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 344e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 345e1069839SBorislav Petkov * - prefetches are not included in the counts. 346e1069839SBorislav Petkov * - icache miss does not include decoded icache 347e1069839SBorislav Petkov */ 348e1069839SBorislav Petkov 349e1069839SBorislav Petkov #define SKL_DEMAND_DATA_RD BIT_ULL(0) 350e1069839SBorislav Petkov #define SKL_DEMAND_RFO BIT_ULL(1) 351e1069839SBorislav Petkov #define SKL_ANY_RESPONSE BIT_ULL(16) 352e1069839SBorislav Petkov #define SKL_SUPPLIER_NONE BIT_ULL(17) 353e1069839SBorislav Petkov #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 354e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 355e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 356e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 357e1069839SBorislav Petkov #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 358e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 359e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 360e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 361e1069839SBorislav Petkov #define SKL_SPL_HIT BIT_ULL(30) 362e1069839SBorislav Petkov #define SKL_SNOOP_NONE BIT_ULL(31) 363e1069839SBorislav Petkov #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 364e1069839SBorislav Petkov #define SKL_SNOOP_MISS BIT_ULL(33) 365e1069839SBorislav Petkov #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 366e1069839SBorislav Petkov #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 367e1069839SBorislav Petkov #define SKL_SNOOP_HITM BIT_ULL(36) 368e1069839SBorislav Petkov #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 369e1069839SBorislav Petkov #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 370e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 371e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 372e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 373e1069839SBorislav Petkov #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 374e1069839SBorislav Petkov #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 375e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 376e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 377e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SPL_HIT) 378e1069839SBorislav Petkov #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 379e1069839SBorislav Petkov #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 380e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 381e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 382e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 383e1069839SBorislav Petkov 384e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_event_ids 385e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 386e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 387e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 388e1069839SBorislav Petkov { 389e1069839SBorislav Petkov [ C(L1D ) ] = { 390e1069839SBorislav Petkov [ C(OP_READ) ] = { 391e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 392e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 393e1069839SBorislav Petkov }, 394e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 395e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 396e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 397e1069839SBorislav Petkov }, 398e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 399e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 400e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 401e1069839SBorislav Petkov }, 402e1069839SBorislav Petkov }, 403e1069839SBorislav Petkov [ C(L1I ) ] = { 404e1069839SBorislav Petkov [ C(OP_READ) ] = { 405e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 406e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 407e1069839SBorislav Petkov }, 408e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 409e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 410e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 411e1069839SBorislav Petkov }, 412e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 413e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 414e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 415e1069839SBorislav Petkov }, 416e1069839SBorislav Petkov }, 417e1069839SBorislav Petkov [ C(LL ) ] = { 418e1069839SBorislav Petkov [ C(OP_READ) ] = { 419e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 420e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 421e1069839SBorislav Petkov }, 422e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 423e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 424e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 425e1069839SBorislav Petkov }, 426e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 427e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 428e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 429e1069839SBorislav Petkov }, 430e1069839SBorislav Petkov }, 431e1069839SBorislav Petkov [ C(DTLB) ] = { 432e1069839SBorislav Petkov [ C(OP_READ) ] = { 433e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 434fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 435e1069839SBorislav Petkov }, 436e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 437e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 438fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 439e1069839SBorislav Petkov }, 440e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 441e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 442e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 443e1069839SBorislav Petkov }, 444e1069839SBorislav Petkov }, 445e1069839SBorislav Petkov [ C(ITLB) ] = { 446e1069839SBorislav Petkov [ C(OP_READ) ] = { 447e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 448e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 449e1069839SBorislav Petkov }, 450e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 451e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 452e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 453e1069839SBorislav Petkov }, 454e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 455e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 456e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 457e1069839SBorislav Petkov }, 458e1069839SBorislav Petkov }, 459e1069839SBorislav Petkov [ C(BPU ) ] = { 460e1069839SBorislav Petkov [ C(OP_READ) ] = { 461e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 462e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 463e1069839SBorislav Petkov }, 464e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 465e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 466e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 467e1069839SBorislav Petkov }, 468e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 469e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 470e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 471e1069839SBorislav Petkov }, 472e1069839SBorislav Petkov }, 473e1069839SBorislav Petkov [ C(NODE) ] = { 474e1069839SBorislav Petkov [ C(OP_READ) ] = { 475e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 476e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 477e1069839SBorislav Petkov }, 478e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 479e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 480e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 481e1069839SBorislav Petkov }, 482e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 483e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 484e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 485e1069839SBorislav Petkov }, 486e1069839SBorislav Petkov }, 487e1069839SBorislav Petkov }; 488e1069839SBorislav Petkov 489e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_extra_regs 490e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 491e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 492e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 493e1069839SBorislav Petkov { 494e1069839SBorislav Petkov [ C(LL ) ] = { 495e1069839SBorislav Petkov [ C(OP_READ) ] = { 496e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 497e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 498e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 499e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 500e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 501e1069839SBorislav Petkov }, 502e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 503e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 504e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 505e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 506e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 507e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 508e1069839SBorislav Petkov }, 509e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 510e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 511e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 512e1069839SBorislav Petkov }, 513e1069839SBorislav Petkov }, 514e1069839SBorislav Petkov [ C(NODE) ] = { 515e1069839SBorislav Petkov [ C(OP_READ) ] = { 516e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 517e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 518e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 519e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 520e1069839SBorislav Petkov }, 521e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 522e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 523e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 524e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 525e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 526e1069839SBorislav Petkov }, 527e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 528e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 529e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 530e1069839SBorislav Petkov }, 531e1069839SBorislav Petkov }, 532e1069839SBorislav Petkov }; 533e1069839SBorislav Petkov 534e1069839SBorislav Petkov #define SNB_DMND_DATA_RD (1ULL << 0) 535e1069839SBorislav Petkov #define SNB_DMND_RFO (1ULL << 1) 536e1069839SBorislav Petkov #define SNB_DMND_IFETCH (1ULL << 2) 537e1069839SBorislav Petkov #define SNB_DMND_WB (1ULL << 3) 538e1069839SBorislav Petkov #define SNB_PF_DATA_RD (1ULL << 4) 539e1069839SBorislav Petkov #define SNB_PF_RFO (1ULL << 5) 540e1069839SBorislav Petkov #define SNB_PF_IFETCH (1ULL << 6) 541e1069839SBorislav Petkov #define SNB_LLC_DATA_RD (1ULL << 7) 542e1069839SBorislav Petkov #define SNB_LLC_RFO (1ULL << 8) 543e1069839SBorislav Petkov #define SNB_LLC_IFETCH (1ULL << 9) 544e1069839SBorislav Petkov #define SNB_BUS_LOCKS (1ULL << 10) 545e1069839SBorislav Petkov #define SNB_STRM_ST (1ULL << 11) 546e1069839SBorislav Petkov #define SNB_OTHER (1ULL << 15) 547e1069839SBorislav Petkov #define SNB_RESP_ANY (1ULL << 16) 548e1069839SBorislav Petkov #define SNB_NO_SUPP (1ULL << 17) 549e1069839SBorislav Petkov #define SNB_LLC_HITM (1ULL << 18) 550e1069839SBorislav Petkov #define SNB_LLC_HITE (1ULL << 19) 551e1069839SBorislav Petkov #define SNB_LLC_HITS (1ULL << 20) 552e1069839SBorislav Petkov #define SNB_LLC_HITF (1ULL << 21) 553e1069839SBorislav Petkov #define SNB_LOCAL (1ULL << 22) 554e1069839SBorislav Petkov #define SNB_REMOTE (0xffULL << 23) 555e1069839SBorislav Petkov #define SNB_SNP_NONE (1ULL << 31) 556e1069839SBorislav Petkov #define SNB_SNP_NOT_NEEDED (1ULL << 32) 557e1069839SBorislav Petkov #define SNB_SNP_MISS (1ULL << 33) 558e1069839SBorislav Petkov #define SNB_NO_FWD (1ULL << 34) 559e1069839SBorislav Petkov #define SNB_SNP_FWD (1ULL << 35) 560e1069839SBorislav Petkov #define SNB_HITM (1ULL << 36) 561e1069839SBorislav Petkov #define SNB_NON_DRAM (1ULL << 37) 562e1069839SBorislav Petkov 563e1069839SBorislav Petkov #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 564e1069839SBorislav Petkov #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 565e1069839SBorislav Petkov #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 566e1069839SBorislav Petkov 567e1069839SBorislav Petkov #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 568e1069839SBorislav Petkov SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 569e1069839SBorislav Petkov SNB_HITM) 570e1069839SBorislav Petkov 571e1069839SBorislav Petkov #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 572e1069839SBorislav Petkov #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 573e1069839SBorislav Petkov 574e1069839SBorislav Petkov #define SNB_L3_ACCESS SNB_RESP_ANY 575e1069839SBorislav Petkov #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 576e1069839SBorislav Petkov 577e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_extra_regs 578e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 579e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 580e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 581e1069839SBorislav Petkov { 582e1069839SBorislav Petkov [ C(LL ) ] = { 583e1069839SBorislav Petkov [ C(OP_READ) ] = { 584e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 585e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 586e1069839SBorislav Petkov }, 587e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 588e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 589e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 590e1069839SBorislav Petkov }, 591e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 592e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 593e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 594e1069839SBorislav Petkov }, 595e1069839SBorislav Petkov }, 596e1069839SBorislav Petkov [ C(NODE) ] = { 597e1069839SBorislav Petkov [ C(OP_READ) ] = { 598e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 599e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 600e1069839SBorislav Petkov }, 601e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 602e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 603e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 604e1069839SBorislav Petkov }, 605e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 606e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 607e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 608e1069839SBorislav Petkov }, 609e1069839SBorislav Petkov }, 610e1069839SBorislav Petkov }; 611e1069839SBorislav Petkov 612e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_event_ids 613e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 614e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 615e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 616e1069839SBorislav Petkov { 617e1069839SBorislav Petkov [ C(L1D) ] = { 618e1069839SBorislav Petkov [ C(OP_READ) ] = { 619e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 620e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 621e1069839SBorislav Petkov }, 622e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 623e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 624e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 625e1069839SBorislav Petkov }, 626e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 627e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 628e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 629e1069839SBorislav Petkov }, 630e1069839SBorislav Petkov }, 631e1069839SBorislav Petkov [ C(L1I ) ] = { 632e1069839SBorislav Petkov [ C(OP_READ) ] = { 633e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 634e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 635e1069839SBorislav Petkov }, 636e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 637e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 638e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 639e1069839SBorislav Petkov }, 640e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 641e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 642e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 643e1069839SBorislav Petkov }, 644e1069839SBorislav Petkov }, 645e1069839SBorislav Petkov [ C(LL ) ] = { 646e1069839SBorislav Petkov [ C(OP_READ) ] = { 647e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 648e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 649e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 650e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 651e1069839SBorislav Petkov }, 652e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 653e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 654e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 655e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 656e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 657e1069839SBorislav Petkov }, 658e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 659e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 660e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 661e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 662e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 663e1069839SBorislav Petkov }, 664e1069839SBorislav Petkov }, 665e1069839SBorislav Petkov [ C(DTLB) ] = { 666e1069839SBorislav Petkov [ C(OP_READ) ] = { 667e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 668e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 669e1069839SBorislav Petkov }, 670e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 671e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 672e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 673e1069839SBorislav Petkov }, 674e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 675e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 676e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 677e1069839SBorislav Petkov }, 678e1069839SBorislav Petkov }, 679e1069839SBorislav Petkov [ C(ITLB) ] = { 680e1069839SBorislav Petkov [ C(OP_READ) ] = { 681e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 682e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 683e1069839SBorislav Petkov }, 684e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 685e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 686e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 687e1069839SBorislav Petkov }, 688e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 689e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 690e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 691e1069839SBorislav Petkov }, 692e1069839SBorislav Petkov }, 693e1069839SBorislav Petkov [ C(BPU ) ] = { 694e1069839SBorislav Petkov [ C(OP_READ) ] = { 695e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 696e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 697e1069839SBorislav Petkov }, 698e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 699e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 700e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 701e1069839SBorislav Petkov }, 702e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 703e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 704e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 705e1069839SBorislav Petkov }, 706e1069839SBorislav Petkov }, 707e1069839SBorislav Petkov [ C(NODE) ] = { 708e1069839SBorislav Petkov [ C(OP_READ) ] = { 709e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 710e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 711e1069839SBorislav Petkov }, 712e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 713e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 714e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 715e1069839SBorislav Petkov }, 716e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 717e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 718e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 719e1069839SBorislav Petkov }, 720e1069839SBorislav Petkov }, 721e1069839SBorislav Petkov 722e1069839SBorislav Petkov }; 723e1069839SBorislav Petkov 724e1069839SBorislav Petkov /* 725e1069839SBorislav Petkov * Notes on the events: 726e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 727e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 728e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 729e1069839SBorislav Petkov * - prefetches are not included in the counts because they are not 730e1069839SBorislav Petkov * reliably counted. 731e1069839SBorislav Petkov */ 732e1069839SBorislav Petkov 733e1069839SBorislav Petkov #define HSW_DEMAND_DATA_RD BIT_ULL(0) 734e1069839SBorislav Petkov #define HSW_DEMAND_RFO BIT_ULL(1) 735e1069839SBorislav Petkov #define HSW_ANY_RESPONSE BIT_ULL(16) 736e1069839SBorislav Petkov #define HSW_SUPPLIER_NONE BIT_ULL(17) 737e1069839SBorislav Petkov #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 738e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 739e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 740e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 741e1069839SBorislav Petkov #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 742e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 743e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 744e1069839SBorislav Petkov #define HSW_SNOOP_NONE BIT_ULL(31) 745e1069839SBorislav Petkov #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 746e1069839SBorislav Petkov #define HSW_SNOOP_MISS BIT_ULL(33) 747e1069839SBorislav Petkov #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 748e1069839SBorislav Petkov #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 749e1069839SBorislav Petkov #define HSW_SNOOP_HITM BIT_ULL(36) 750e1069839SBorislav Petkov #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 751e1069839SBorislav Petkov #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 752e1069839SBorislav Petkov HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 753e1069839SBorislav Petkov HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 754e1069839SBorislav Petkov HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 755e1069839SBorislav Petkov #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 756e1069839SBorislav Petkov #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 757e1069839SBorislav Petkov #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 758e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 759e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 760e1069839SBorislav Petkov #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 761e1069839SBorislav Petkov 762e1069839SBorislav Petkov #define BDW_L3_MISS_LOCAL BIT(26) 763e1069839SBorislav Petkov #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 764e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 765e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 766e1069839SBorislav Petkov 767e1069839SBorislav Petkov 768e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_event_ids 769e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 770e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 771e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 772e1069839SBorislav Petkov { 773e1069839SBorislav Petkov [ C(L1D ) ] = { 774e1069839SBorislav Petkov [ C(OP_READ) ] = { 775e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 776e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 777e1069839SBorislav Petkov }, 778e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 779e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 780e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 781e1069839SBorislav Petkov }, 782e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 783e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 784e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 785e1069839SBorislav Petkov }, 786e1069839SBorislav Petkov }, 787e1069839SBorislav Petkov [ C(L1I ) ] = { 788e1069839SBorislav Petkov [ C(OP_READ) ] = { 789e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 790e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 791e1069839SBorislav Petkov }, 792e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 793e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 794e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 795e1069839SBorislav Petkov }, 796e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 797e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 798e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 799e1069839SBorislav Petkov }, 800e1069839SBorislav Petkov }, 801e1069839SBorislav Petkov [ C(LL ) ] = { 802e1069839SBorislav Petkov [ C(OP_READ) ] = { 803e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 804e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 805e1069839SBorislav Petkov }, 806e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 807e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 808e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 809e1069839SBorislav Petkov }, 810e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 811e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 812e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 813e1069839SBorislav Petkov }, 814e1069839SBorislav Petkov }, 815e1069839SBorislav Petkov [ C(DTLB) ] = { 816e1069839SBorislav Petkov [ C(OP_READ) ] = { 817e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 818e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 819e1069839SBorislav Petkov }, 820e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 821e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 822e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 823e1069839SBorislav Petkov }, 824e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 825e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 826e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 827e1069839SBorislav Petkov }, 828e1069839SBorislav Petkov }, 829e1069839SBorislav Petkov [ C(ITLB) ] = { 830e1069839SBorislav Petkov [ C(OP_READ) ] = { 831e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 832e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 833e1069839SBorislav Petkov }, 834e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 835e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 836e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 837e1069839SBorislav Petkov }, 838e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 839e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 840e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 841e1069839SBorislav Petkov }, 842e1069839SBorislav Petkov }, 843e1069839SBorislav Petkov [ C(BPU ) ] = { 844e1069839SBorislav Petkov [ C(OP_READ) ] = { 845e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 846e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 847e1069839SBorislav Petkov }, 848e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 849e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 850e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 851e1069839SBorislav Petkov }, 852e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 853e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 854e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 855e1069839SBorislav Petkov }, 856e1069839SBorislav Petkov }, 857e1069839SBorislav Petkov [ C(NODE) ] = { 858e1069839SBorislav Petkov [ C(OP_READ) ] = { 859e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 860e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 861e1069839SBorislav Petkov }, 862e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 863e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 864e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 865e1069839SBorislav Petkov }, 866e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 867e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 868e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 869e1069839SBorislav Petkov }, 870e1069839SBorislav Petkov }, 871e1069839SBorislav Petkov }; 872e1069839SBorislav Petkov 873e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_extra_regs 874e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 875e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 876e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 877e1069839SBorislav Petkov { 878e1069839SBorislav Petkov [ C(LL ) ] = { 879e1069839SBorislav Petkov [ C(OP_READ) ] = { 880e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 881e1069839SBorislav Petkov HSW_LLC_ACCESS, 882e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 883e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 884e1069839SBorislav Petkov }, 885e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 886e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 887e1069839SBorislav Petkov HSW_LLC_ACCESS, 888e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 889e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 890e1069839SBorislav Petkov }, 891e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 892e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 893e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 894e1069839SBorislav Petkov }, 895e1069839SBorislav Petkov }, 896e1069839SBorislav Petkov [ C(NODE) ] = { 897e1069839SBorislav Petkov [ C(OP_READ) ] = { 898e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 899e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 900e1069839SBorislav Petkov HSW_SNOOP_DRAM, 901e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 902e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 903e1069839SBorislav Petkov HSW_SNOOP_DRAM, 904e1069839SBorislav Petkov }, 905e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 906e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 907e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 908e1069839SBorislav Petkov HSW_SNOOP_DRAM, 909e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 910e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 911e1069839SBorislav Petkov HSW_SNOOP_DRAM, 912e1069839SBorislav Petkov }, 913e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 914e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 915e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 916e1069839SBorislav Petkov }, 917e1069839SBorislav Petkov }, 918e1069839SBorislav Petkov }; 919e1069839SBorislav Petkov 920e1069839SBorislav Petkov static __initconst const u64 westmere_hw_cache_event_ids 921e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 922e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 923e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 924e1069839SBorislav Petkov { 925e1069839SBorislav Petkov [ C(L1D) ] = { 926e1069839SBorislav Petkov [ C(OP_READ) ] = { 927e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 928e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 929e1069839SBorislav Petkov }, 930e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 931e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 932e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 933e1069839SBorislav Petkov }, 934e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 935e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 936e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 937e1069839SBorislav Petkov }, 938e1069839SBorislav Petkov }, 939e1069839SBorislav Petkov [ C(L1I ) ] = { 940e1069839SBorislav Petkov [ C(OP_READ) ] = { 941e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 942e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 943e1069839SBorislav Petkov }, 944e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 945e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 946e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 947e1069839SBorislav Petkov }, 948e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 949e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 950e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 951e1069839SBorislav Petkov }, 952e1069839SBorislav Petkov }, 953e1069839SBorislav Petkov [ C(LL ) ] = { 954e1069839SBorislav Petkov [ C(OP_READ) ] = { 955e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 956e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 957e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 958e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 959e1069839SBorislav Petkov }, 960e1069839SBorislav Petkov /* 961e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 962e1069839SBorislav Petkov * on RFO. 963e1069839SBorislav Petkov */ 964e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 965e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 966e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 967e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 968e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 969e1069839SBorislav Petkov }, 970e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 971e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 972e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 973e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 974e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 975e1069839SBorislav Petkov }, 976e1069839SBorislav Petkov }, 977e1069839SBorislav Petkov [ C(DTLB) ] = { 978e1069839SBorislav Petkov [ C(OP_READ) ] = { 979e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 980e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 981e1069839SBorislav Petkov }, 982e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 983e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 984e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 985e1069839SBorislav Petkov }, 986e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 987e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 988e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 989e1069839SBorislav Petkov }, 990e1069839SBorislav Petkov }, 991e1069839SBorislav Petkov [ C(ITLB) ] = { 992e1069839SBorislav Petkov [ C(OP_READ) ] = { 993e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 994e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 995e1069839SBorislav Petkov }, 996e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 997e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 998e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 999e1069839SBorislav Petkov }, 1000e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1001e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1002e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1003e1069839SBorislav Petkov }, 1004e1069839SBorislav Petkov }, 1005e1069839SBorislav Petkov [ C(BPU ) ] = { 1006e1069839SBorislav Petkov [ C(OP_READ) ] = { 1007e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1008e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1009e1069839SBorislav Petkov }, 1010e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1011e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1012e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1013e1069839SBorislav Petkov }, 1014e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1015e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1016e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1017e1069839SBorislav Petkov }, 1018e1069839SBorislav Petkov }, 1019e1069839SBorislav Petkov [ C(NODE) ] = { 1020e1069839SBorislav Petkov [ C(OP_READ) ] = { 1021e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1022e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1023e1069839SBorislav Petkov }, 1024e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1025e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1026e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1027e1069839SBorislav Petkov }, 1028e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1029e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1030e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1031e1069839SBorislav Petkov }, 1032e1069839SBorislav Petkov }, 1033e1069839SBorislav Petkov }; 1034e1069839SBorislav Petkov 1035e1069839SBorislav Petkov /* 1036e1069839SBorislav Petkov * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1037e1069839SBorislav Petkov * See IA32 SDM Vol 3B 30.6.1.3 1038e1069839SBorislav Petkov */ 1039e1069839SBorislav Petkov 1040e1069839SBorislav Petkov #define NHM_DMND_DATA_RD (1 << 0) 1041e1069839SBorislav Petkov #define NHM_DMND_RFO (1 << 1) 1042e1069839SBorislav Petkov #define NHM_DMND_IFETCH (1 << 2) 1043e1069839SBorislav Petkov #define NHM_DMND_WB (1 << 3) 1044e1069839SBorislav Petkov #define NHM_PF_DATA_RD (1 << 4) 1045e1069839SBorislav Petkov #define NHM_PF_DATA_RFO (1 << 5) 1046e1069839SBorislav Petkov #define NHM_PF_IFETCH (1 << 6) 1047e1069839SBorislav Petkov #define NHM_OFFCORE_OTHER (1 << 7) 1048e1069839SBorislav Petkov #define NHM_UNCORE_HIT (1 << 8) 1049e1069839SBorislav Petkov #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1050e1069839SBorislav Petkov #define NHM_OTHER_CORE_HITM (1 << 10) 1051e1069839SBorislav Petkov /* reserved */ 1052e1069839SBorislav Petkov #define NHM_REMOTE_CACHE_FWD (1 << 12) 1053e1069839SBorislav Petkov #define NHM_REMOTE_DRAM (1 << 13) 1054e1069839SBorislav Petkov #define NHM_LOCAL_DRAM (1 << 14) 1055e1069839SBorislav Petkov #define NHM_NON_DRAM (1 << 15) 1056e1069839SBorislav Petkov 1057e1069839SBorislav Petkov #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1058e1069839SBorislav Petkov #define NHM_REMOTE (NHM_REMOTE_DRAM) 1059e1069839SBorislav Petkov 1060e1069839SBorislav Petkov #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1061e1069839SBorislav Petkov #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1062e1069839SBorislav Petkov #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1063e1069839SBorislav Petkov 1064e1069839SBorislav Petkov #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1065e1069839SBorislav Petkov #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1066e1069839SBorislav Petkov #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1067e1069839SBorislav Petkov 1068e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_extra_regs 1069e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1070e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1071e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1072e1069839SBorislav Petkov { 1073e1069839SBorislav Petkov [ C(LL ) ] = { 1074e1069839SBorislav Petkov [ C(OP_READ) ] = { 1075e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1076e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1077e1069839SBorislav Petkov }, 1078e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1079e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1080e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1081e1069839SBorislav Petkov }, 1082e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1083e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1084e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1085e1069839SBorislav Petkov }, 1086e1069839SBorislav Petkov }, 1087e1069839SBorislav Petkov [ C(NODE) ] = { 1088e1069839SBorislav Petkov [ C(OP_READ) ] = { 1089e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1090e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1091e1069839SBorislav Petkov }, 1092e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1093e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1094e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1095e1069839SBorislav Petkov }, 1096e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1097e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1098e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1099e1069839SBorislav Petkov }, 1100e1069839SBorislav Petkov }, 1101e1069839SBorislav Petkov }; 1102e1069839SBorislav Petkov 1103e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_event_ids 1104e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1105e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1106e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1107e1069839SBorislav Petkov { 1108e1069839SBorislav Petkov [ C(L1D) ] = { 1109e1069839SBorislav Petkov [ C(OP_READ) ] = { 1110e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1111e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1112e1069839SBorislav Petkov }, 1113e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1114e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1115e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1116e1069839SBorislav Petkov }, 1117e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1118e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1119e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1120e1069839SBorislav Petkov }, 1121e1069839SBorislav Petkov }, 1122e1069839SBorislav Petkov [ C(L1I ) ] = { 1123e1069839SBorislav Petkov [ C(OP_READ) ] = { 1124e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1125e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1126e1069839SBorislav Petkov }, 1127e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1128e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1129e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1130e1069839SBorislav Petkov }, 1131e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1132e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1133e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1134e1069839SBorislav Petkov }, 1135e1069839SBorislav Petkov }, 1136e1069839SBorislav Petkov [ C(LL ) ] = { 1137e1069839SBorislav Petkov [ C(OP_READ) ] = { 1138e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1139e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1140e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1141e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1142e1069839SBorislav Petkov }, 1143e1069839SBorislav Petkov /* 1144e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1145e1069839SBorislav Petkov * on RFO. 1146e1069839SBorislav Petkov */ 1147e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1148e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1149e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1150e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1151e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1152e1069839SBorislav Petkov }, 1153e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1154e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1155e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1156e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1157e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1158e1069839SBorislav Petkov }, 1159e1069839SBorislav Petkov }, 1160e1069839SBorislav Petkov [ C(DTLB) ] = { 1161e1069839SBorislav Petkov [ C(OP_READ) ] = { 1162e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1163e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1164e1069839SBorislav Petkov }, 1165e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1166e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1167e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1168e1069839SBorislav Petkov }, 1169e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1170e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1171e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1172e1069839SBorislav Petkov }, 1173e1069839SBorislav Petkov }, 1174e1069839SBorislav Petkov [ C(ITLB) ] = { 1175e1069839SBorislav Petkov [ C(OP_READ) ] = { 1176e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1177e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1178e1069839SBorislav Petkov }, 1179e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1180e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1181e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1182e1069839SBorislav Petkov }, 1183e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1184e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1185e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1186e1069839SBorislav Petkov }, 1187e1069839SBorislav Petkov }, 1188e1069839SBorislav Petkov [ C(BPU ) ] = { 1189e1069839SBorislav Petkov [ C(OP_READ) ] = { 1190e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1191e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1192e1069839SBorislav Petkov }, 1193e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1194e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1195e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1196e1069839SBorislav Petkov }, 1197e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1198e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1199e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1200e1069839SBorislav Petkov }, 1201e1069839SBorislav Petkov }, 1202e1069839SBorislav Petkov [ C(NODE) ] = { 1203e1069839SBorislav Petkov [ C(OP_READ) ] = { 1204e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1205e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1206e1069839SBorislav Petkov }, 1207e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1208e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1209e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1210e1069839SBorislav Petkov }, 1211e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1212e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1213e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1214e1069839SBorislav Petkov }, 1215e1069839SBorislav Petkov }, 1216e1069839SBorislav Petkov }; 1217e1069839SBorislav Petkov 1218e1069839SBorislav Petkov static __initconst const u64 core2_hw_cache_event_ids 1219e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1220e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1221e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1222e1069839SBorislav Petkov { 1223e1069839SBorislav Petkov [ C(L1D) ] = { 1224e1069839SBorislav Petkov [ C(OP_READ) ] = { 1225e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1226e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1227e1069839SBorislav Petkov }, 1228e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1229e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1230e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1231e1069839SBorislav Petkov }, 1232e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1233e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1234e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1235e1069839SBorislav Petkov }, 1236e1069839SBorislav Petkov }, 1237e1069839SBorislav Petkov [ C(L1I ) ] = { 1238e1069839SBorislav Petkov [ C(OP_READ) ] = { 1239e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1240e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1241e1069839SBorislav Petkov }, 1242e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1243e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1244e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1245e1069839SBorislav Petkov }, 1246e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1247e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1248e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1249e1069839SBorislav Petkov }, 1250e1069839SBorislav Petkov }, 1251e1069839SBorislav Petkov [ C(LL ) ] = { 1252e1069839SBorislav Petkov [ C(OP_READ) ] = { 1253e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1254e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1255e1069839SBorislav Petkov }, 1256e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1257e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1258e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1259e1069839SBorislav Petkov }, 1260e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1261e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1262e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1263e1069839SBorislav Petkov }, 1264e1069839SBorislav Petkov }, 1265e1069839SBorislav Petkov [ C(DTLB) ] = { 1266e1069839SBorislav Petkov [ C(OP_READ) ] = { 1267e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1268e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1269e1069839SBorislav Petkov }, 1270e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1271e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1272e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1273e1069839SBorislav Petkov }, 1274e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1275e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1276e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1277e1069839SBorislav Petkov }, 1278e1069839SBorislav Petkov }, 1279e1069839SBorislav Petkov [ C(ITLB) ] = { 1280e1069839SBorislav Petkov [ C(OP_READ) ] = { 1281e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1282e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1283e1069839SBorislav Petkov }, 1284e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1285e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1286e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1287e1069839SBorislav Petkov }, 1288e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1289e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1290e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1291e1069839SBorislav Petkov }, 1292e1069839SBorislav Petkov }, 1293e1069839SBorislav Petkov [ C(BPU ) ] = { 1294e1069839SBorislav Petkov [ C(OP_READ) ] = { 1295e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1296e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1297e1069839SBorislav Petkov }, 1298e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1299e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1300e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1301e1069839SBorislav Petkov }, 1302e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1303e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1304e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1305e1069839SBorislav Petkov }, 1306e1069839SBorislav Petkov }, 1307e1069839SBorislav Petkov }; 1308e1069839SBorislav Petkov 1309e1069839SBorislav Petkov static __initconst const u64 atom_hw_cache_event_ids 1310e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1311e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1312e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1313e1069839SBorislav Petkov { 1314e1069839SBorislav Petkov [ C(L1D) ] = { 1315e1069839SBorislav Petkov [ C(OP_READ) ] = { 1316e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1317e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1318e1069839SBorislav Petkov }, 1319e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1320e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1321e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1322e1069839SBorislav Petkov }, 1323e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1324e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1325e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1326e1069839SBorislav Petkov }, 1327e1069839SBorislav Petkov }, 1328e1069839SBorislav Petkov [ C(L1I ) ] = { 1329e1069839SBorislav Petkov [ C(OP_READ) ] = { 1330e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1331e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1332e1069839SBorislav Petkov }, 1333e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1334e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1335e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1336e1069839SBorislav Petkov }, 1337e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1338e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1339e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1340e1069839SBorislav Petkov }, 1341e1069839SBorislav Petkov }, 1342e1069839SBorislav Petkov [ C(LL ) ] = { 1343e1069839SBorislav Petkov [ C(OP_READ) ] = { 1344e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1345e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1346e1069839SBorislav Petkov }, 1347e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1348e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1349e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1350e1069839SBorislav Petkov }, 1351e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1352e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1353e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1354e1069839SBorislav Petkov }, 1355e1069839SBorislav Petkov }, 1356e1069839SBorislav Petkov [ C(DTLB) ] = { 1357e1069839SBorislav Petkov [ C(OP_READ) ] = { 1358e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1359e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1360e1069839SBorislav Petkov }, 1361e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1362e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1363e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1364e1069839SBorislav Petkov }, 1365e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1366e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1367e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1368e1069839SBorislav Petkov }, 1369e1069839SBorislav Petkov }, 1370e1069839SBorislav Petkov [ C(ITLB) ] = { 1371e1069839SBorislav Petkov [ C(OP_READ) ] = { 1372e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1373e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1374e1069839SBorislav Petkov }, 1375e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1376e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1377e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1378e1069839SBorislav Petkov }, 1379e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1380e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1381e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1382e1069839SBorislav Petkov }, 1383e1069839SBorislav Petkov }, 1384e1069839SBorislav Petkov [ C(BPU ) ] = { 1385e1069839SBorislav Petkov [ C(OP_READ) ] = { 1386e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1387e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1388e1069839SBorislav Petkov }, 1389e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1390e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1391e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1392e1069839SBorislav Petkov }, 1393e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1394e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1395e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1396e1069839SBorislav Petkov }, 1397e1069839SBorislav Petkov }, 1398e1069839SBorislav Petkov }; 1399e1069839SBorislav Petkov 1400eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1401eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1402eb12b8ecSAndi Kleen /* no_alloc_cycles.not_delivered */ 1403eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1404eb12b8ecSAndi Kleen "event=0xca,umask=0x50"); 1405eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1406eb12b8ecSAndi Kleen /* uops_retired.all */ 1407eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1408eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1409eb12b8ecSAndi Kleen /* uops_retired.all */ 1410eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1411eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1412eb12b8ecSAndi Kleen 1413eb12b8ecSAndi Kleen static struct attribute *slm_events_attrs[] = { 1414eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_slm), 1415eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_scale_slm), 1416eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_slm), 1417eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_scale_slm), 1418eb12b8ecSAndi Kleen EVENT_PTR(td_slots_issued_slm), 1419eb12b8ecSAndi Kleen EVENT_PTR(td_slots_retired_slm), 1420eb12b8ecSAndi Kleen NULL 1421eb12b8ecSAndi Kleen }; 1422eb12b8ecSAndi Kleen 1423e1069839SBorislav Petkov static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1424e1069839SBorislav Petkov { 1425e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1426e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1427e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1428e1069839SBorislav Petkov EVENT_EXTRA_END 1429e1069839SBorislav Petkov }; 1430e1069839SBorislav Petkov 1431e1069839SBorislav Petkov #define SLM_DMND_READ SNB_DMND_DATA_RD 1432e1069839SBorislav Petkov #define SLM_DMND_WRITE SNB_DMND_RFO 1433e1069839SBorislav Petkov #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1434e1069839SBorislav Petkov 1435e1069839SBorislav Petkov #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1436e1069839SBorislav Petkov #define SLM_LLC_ACCESS SNB_RESP_ANY 1437e1069839SBorislav Petkov #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1438e1069839SBorislav Petkov 1439e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_extra_regs 1440e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1441e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1442e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1443e1069839SBorislav Petkov { 1444e1069839SBorislav Petkov [ C(LL ) ] = { 1445e1069839SBorislav Petkov [ C(OP_READ) ] = { 1446e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1447e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1448e1069839SBorislav Petkov }, 1449e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1450e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1451e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1452e1069839SBorislav Petkov }, 1453e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1454e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1455e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1456e1069839SBorislav Petkov }, 1457e1069839SBorislav Petkov }, 1458e1069839SBorislav Petkov }; 1459e1069839SBorislav Petkov 1460e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_event_ids 1461e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1462e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1463e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1464e1069839SBorislav Petkov { 1465e1069839SBorislav Petkov [ C(L1D) ] = { 1466e1069839SBorislav Petkov [ C(OP_READ) ] = { 1467e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1468e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1469e1069839SBorislav Petkov }, 1470e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1471e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1472e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1473e1069839SBorislav Petkov }, 1474e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1475e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1476e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1477e1069839SBorislav Petkov }, 1478e1069839SBorislav Petkov }, 1479e1069839SBorislav Petkov [ C(L1I ) ] = { 1480e1069839SBorislav Petkov [ C(OP_READ) ] = { 1481e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1482e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1483e1069839SBorislav Petkov }, 1484e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1485e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1486e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1487e1069839SBorislav Petkov }, 1488e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1489e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1490e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1491e1069839SBorislav Petkov }, 1492e1069839SBorislav Petkov }, 1493e1069839SBorislav Petkov [ C(LL ) ] = { 1494e1069839SBorislav Petkov [ C(OP_READ) ] = { 1495e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1496e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1497e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1498e1069839SBorislav Petkov }, 1499e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1500e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1501e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1502e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1503e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1504e1069839SBorislav Petkov }, 1505e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1506e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1507e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1508e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1509e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1510e1069839SBorislav Petkov }, 1511e1069839SBorislav Petkov }, 1512e1069839SBorislav Petkov [ C(DTLB) ] = { 1513e1069839SBorislav Petkov [ C(OP_READ) ] = { 1514e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1515e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1516e1069839SBorislav Petkov }, 1517e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1518e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1519e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1520e1069839SBorislav Petkov }, 1521e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1522e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1523e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1524e1069839SBorislav Petkov }, 1525e1069839SBorislav Petkov }, 1526e1069839SBorislav Petkov [ C(ITLB) ] = { 1527e1069839SBorislav Petkov [ C(OP_READ) ] = { 1528e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1529e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1530e1069839SBorislav Petkov }, 1531e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1532e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1533e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1534e1069839SBorislav Petkov }, 1535e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1536e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1537e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1538e1069839SBorislav Petkov }, 1539e1069839SBorislav Petkov }, 1540e1069839SBorislav Petkov [ C(BPU ) ] = { 1541e1069839SBorislav Petkov [ C(OP_READ) ] = { 1542e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1543e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1544e1069839SBorislav Petkov }, 1545e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1546e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1547e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1548e1069839SBorislav Petkov }, 1549e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1550e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1551e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1552e1069839SBorislav Petkov }, 1553e1069839SBorislav Petkov }, 1554e1069839SBorislav Petkov }; 1555e1069839SBorislav Petkov 1556ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1557ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1558ed827adbSKan Liang /* UOPS_NOT_DELIVERED.ANY */ 1559ed827adbSKan Liang EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1560ed827adbSKan Liang /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1561ed827adbSKan Liang EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1562ed827adbSKan Liang /* UOPS_RETIRED.ANY */ 1563ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1564ed827adbSKan Liang /* UOPS_ISSUED.ANY */ 1565ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1566ed827adbSKan Liang 1567ed827adbSKan Liang static struct attribute *glm_events_attrs[] = { 1568ed827adbSKan Liang EVENT_PTR(td_total_slots_glm), 1569ed827adbSKan Liang EVENT_PTR(td_total_slots_scale_glm), 1570ed827adbSKan Liang EVENT_PTR(td_fetch_bubbles_glm), 1571ed827adbSKan Liang EVENT_PTR(td_recovery_bubbles_glm), 1572ed827adbSKan Liang EVENT_PTR(td_slots_issued_glm), 1573ed827adbSKan Liang EVENT_PTR(td_slots_retired_glm), 1574ed827adbSKan Liang NULL 1575ed827adbSKan Liang }; 1576ed827adbSKan Liang 15778b92c3a7SKan Liang static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 15788b92c3a7SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 15798b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 15808b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 15818b92c3a7SKan Liang EVENT_EXTRA_END 15828b92c3a7SKan Liang }; 15838b92c3a7SKan Liang 15848b92c3a7SKan Liang #define GLM_DEMAND_DATA_RD BIT_ULL(0) 15858b92c3a7SKan Liang #define GLM_DEMAND_RFO BIT_ULL(1) 15868b92c3a7SKan Liang #define GLM_ANY_RESPONSE BIT_ULL(16) 15878b92c3a7SKan Liang #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 15888b92c3a7SKan Liang #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 15898b92c3a7SKan Liang #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 15908b92c3a7SKan Liang #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 15918b92c3a7SKan Liang #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 15928b92c3a7SKan Liang #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 15938b92c3a7SKan Liang #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 15948b92c3a7SKan Liang 15958b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_event_ids 15968b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 15978b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 15988b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 15998b92c3a7SKan Liang [C(L1D)] = { 16008b92c3a7SKan Liang [C(OP_READ)] = { 16018b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16028b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16038b92c3a7SKan Liang }, 16048b92c3a7SKan Liang [C(OP_WRITE)] = { 16058b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16068b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16078b92c3a7SKan Liang }, 16088b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16098b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16108b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16118b92c3a7SKan Liang }, 16128b92c3a7SKan Liang }, 16138b92c3a7SKan Liang [C(L1I)] = { 16148b92c3a7SKan Liang [C(OP_READ)] = { 16158b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 16168b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 16178b92c3a7SKan Liang }, 16188b92c3a7SKan Liang [C(OP_WRITE)] = { 16198b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16208b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16218b92c3a7SKan Liang }, 16228b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16238b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16248b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16258b92c3a7SKan Liang }, 16268b92c3a7SKan Liang }, 16278b92c3a7SKan Liang [C(LL)] = { 16288b92c3a7SKan Liang [C(OP_READ)] = { 16298b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16308b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16318b92c3a7SKan Liang }, 16328b92c3a7SKan Liang [C(OP_WRITE)] = { 16338b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16348b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16358b92c3a7SKan Liang }, 16368b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16378b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16388b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16398b92c3a7SKan Liang }, 16408b92c3a7SKan Liang }, 16418b92c3a7SKan Liang [C(DTLB)] = { 16428b92c3a7SKan Liang [C(OP_READ)] = { 16438b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16448b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16458b92c3a7SKan Liang }, 16468b92c3a7SKan Liang [C(OP_WRITE)] = { 16478b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16488b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16498b92c3a7SKan Liang }, 16508b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16518b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16528b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16538b92c3a7SKan Liang }, 16548b92c3a7SKan Liang }, 16558b92c3a7SKan Liang [C(ITLB)] = { 16568b92c3a7SKan Liang [C(OP_READ)] = { 16578b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 16588b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 16598b92c3a7SKan Liang }, 16608b92c3a7SKan Liang [C(OP_WRITE)] = { 16618b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16628b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16638b92c3a7SKan Liang }, 16648b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16658b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16668b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16678b92c3a7SKan Liang }, 16688b92c3a7SKan Liang }, 16698b92c3a7SKan Liang [C(BPU)] = { 16708b92c3a7SKan Liang [C(OP_READ)] = { 16718b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 16728b92c3a7SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 16738b92c3a7SKan Liang }, 16748b92c3a7SKan Liang [C(OP_WRITE)] = { 16758b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16768b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16778b92c3a7SKan Liang }, 16788b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16798b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16808b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16818b92c3a7SKan Liang }, 16828b92c3a7SKan Liang }, 16838b92c3a7SKan Liang }; 16848b92c3a7SKan Liang 16858b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_extra_regs 16868b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 16878b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 16888b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 16898b92c3a7SKan Liang [C(LL)] = { 16908b92c3a7SKan Liang [C(OP_READ)] = { 16918b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 16928b92c3a7SKan Liang GLM_LLC_ACCESS, 16938b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 16948b92c3a7SKan Liang GLM_LLC_MISS, 16958b92c3a7SKan Liang }, 16968b92c3a7SKan Liang [C(OP_WRITE)] = { 16978b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 16988b92c3a7SKan Liang GLM_LLC_ACCESS, 16998b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 17008b92c3a7SKan Liang GLM_LLC_MISS, 17018b92c3a7SKan Liang }, 17028b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17038b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 17048b92c3a7SKan Liang GLM_LLC_ACCESS, 17058b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 17068b92c3a7SKan Liang GLM_LLC_MISS, 17078b92c3a7SKan Liang }, 17088b92c3a7SKan Liang }, 17098b92c3a7SKan Liang }; 17108b92c3a7SKan Liang 1711dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_event_ids 1712dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1713dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1714dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1715dd0b06b5SKan Liang [C(L1D)] = { 1716dd0b06b5SKan Liang [C(OP_READ)] = { 1717dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1718dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1719dd0b06b5SKan Liang }, 1720dd0b06b5SKan Liang [C(OP_WRITE)] = { 1721dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1722dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1723dd0b06b5SKan Liang }, 1724dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1725dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1726dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1727dd0b06b5SKan Liang }, 1728dd0b06b5SKan Liang }, 1729dd0b06b5SKan Liang [C(L1I)] = { 1730dd0b06b5SKan Liang [C(OP_READ)] = { 1731dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1732dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1733dd0b06b5SKan Liang }, 1734dd0b06b5SKan Liang [C(OP_WRITE)] = { 1735dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1736dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1737dd0b06b5SKan Liang }, 1738dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1739dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1740dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1741dd0b06b5SKan Liang }, 1742dd0b06b5SKan Liang }, 1743dd0b06b5SKan Liang [C(LL)] = { 1744dd0b06b5SKan Liang [C(OP_READ)] = { 1745dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1746dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1747dd0b06b5SKan Liang }, 1748dd0b06b5SKan Liang [C(OP_WRITE)] = { 1749dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1750dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1751dd0b06b5SKan Liang }, 1752dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1753dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1754dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1755dd0b06b5SKan Liang }, 1756dd0b06b5SKan Liang }, 1757dd0b06b5SKan Liang [C(DTLB)] = { 1758dd0b06b5SKan Liang [C(OP_READ)] = { 1759dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1760dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1761dd0b06b5SKan Liang }, 1762dd0b06b5SKan Liang [C(OP_WRITE)] = { 1763dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1764dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1765dd0b06b5SKan Liang }, 1766dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1767dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1768dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1769dd0b06b5SKan Liang }, 1770dd0b06b5SKan Liang }, 1771dd0b06b5SKan Liang [C(ITLB)] = { 1772dd0b06b5SKan Liang [C(OP_READ)] = { 1773dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1774dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1775dd0b06b5SKan Liang }, 1776dd0b06b5SKan Liang [C(OP_WRITE)] = { 1777dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1778dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1779dd0b06b5SKan Liang }, 1780dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1781dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1782dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1783dd0b06b5SKan Liang }, 1784dd0b06b5SKan Liang }, 1785dd0b06b5SKan Liang [C(BPU)] = { 1786dd0b06b5SKan Liang [C(OP_READ)] = { 1787dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1788dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1789dd0b06b5SKan Liang }, 1790dd0b06b5SKan Liang [C(OP_WRITE)] = { 1791dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1792dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1793dd0b06b5SKan Liang }, 1794dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1795dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1796dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1797dd0b06b5SKan Liang }, 1798dd0b06b5SKan Liang }, 1799dd0b06b5SKan Liang }; 1800dd0b06b5SKan Liang 1801dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_extra_regs 1802dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1803dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1804dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1805dd0b06b5SKan Liang [C(LL)] = { 1806dd0b06b5SKan Liang [C(OP_READ)] = { 1807dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1808dd0b06b5SKan Liang GLM_LLC_ACCESS, 1809dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 1810dd0b06b5SKan Liang GLM_LLC_MISS, 1811dd0b06b5SKan Liang }, 1812dd0b06b5SKan Liang [C(OP_WRITE)] = { 1813dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1814dd0b06b5SKan Liang GLM_LLC_ACCESS, 1815dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1816dd0b06b5SKan Liang GLM_LLC_MISS, 1817dd0b06b5SKan Liang }, 1818dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1819dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1820dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1821dd0b06b5SKan Liang }, 1822dd0b06b5SKan Liang }, 1823dd0b06b5SKan Liang }; 1824dd0b06b5SKan Liang 1825e1069839SBorislav Petkov #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1826e1069839SBorislav Petkov #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1827e1069839SBorislav Petkov #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1828e1069839SBorislav Petkov #define KNL_MCDRAM_FAR BIT_ULL(22) 1829e1069839SBorislav Petkov #define KNL_DDR_LOCAL BIT_ULL(23) 1830e1069839SBorislav Petkov #define KNL_DDR_FAR BIT_ULL(24) 1831e1069839SBorislav Petkov #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1832e1069839SBorislav Petkov KNL_DDR_LOCAL | KNL_DDR_FAR) 1833e1069839SBorislav Petkov #define KNL_L2_READ SLM_DMND_READ 1834e1069839SBorislav Petkov #define KNL_L2_WRITE SLM_DMND_WRITE 1835e1069839SBorislav Petkov #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1836e1069839SBorislav Petkov #define KNL_L2_ACCESS SLM_LLC_ACCESS 1837e1069839SBorislav Petkov #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1838e1069839SBorislav Petkov KNL_DRAM_ANY | SNB_SNP_ANY | \ 1839e1069839SBorislav Petkov SNB_NON_DRAM) 1840e1069839SBorislav Petkov 1841e1069839SBorislav Petkov static __initconst const u64 knl_hw_cache_extra_regs 1842e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1843e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1844e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1845e1069839SBorislav Petkov [C(LL)] = { 1846e1069839SBorislav Petkov [C(OP_READ)] = { 1847e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1848e1069839SBorislav Petkov [C(RESULT_MISS)] = 0, 1849e1069839SBorislav Petkov }, 1850e1069839SBorislav Petkov [C(OP_WRITE)] = { 1851e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1852e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1853e1069839SBorislav Petkov }, 1854e1069839SBorislav Petkov [C(OP_PREFETCH)] = { 1855e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1856e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1857e1069839SBorislav Petkov }, 1858e1069839SBorislav Petkov }, 1859e1069839SBorislav Petkov }; 1860e1069839SBorislav Petkov 1861e1069839SBorislav Petkov /* 1862c3d266c8SKan Liang * Used from PMIs where the LBRs are already disabled. 1863c3d266c8SKan Liang * 1864c3d266c8SKan Liang * This function could be called consecutively. It is required to remain in 1865c3d266c8SKan Liang * disabled state if called consecutively. 1866c3d266c8SKan Liang * 1867c3d266c8SKan Liang * During consecutive calls, the same disable value will be written to related 1868cecf6235SAlexander Shishkin * registers, so the PMU state remains unchanged. 1869cecf6235SAlexander Shishkin * 1870cecf6235SAlexander Shishkin * intel_bts events don't coexist with intel PMU's BTS events because of 1871cecf6235SAlexander Shishkin * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1872cecf6235SAlexander Shishkin * disabled around intel PMU's event batching etc, only inside the PMI handler. 1873e1069839SBorislav Petkov */ 1874e1069839SBorislav Petkov static void __intel_pmu_disable_all(void) 1875e1069839SBorislav Petkov { 1876e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1877e1069839SBorislav Petkov 1878e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1879e1069839SBorislav Petkov 1880e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1881e1069839SBorislav Petkov intel_pmu_disable_bts(); 1882e1069839SBorislav Petkov 1883e1069839SBorislav Petkov intel_pmu_pebs_disable_all(); 1884e1069839SBorislav Petkov } 1885e1069839SBorislav Petkov 1886e1069839SBorislav Petkov static void intel_pmu_disable_all(void) 1887e1069839SBorislav Petkov { 1888e1069839SBorislav Petkov __intel_pmu_disable_all(); 1889e1069839SBorislav Petkov intel_pmu_lbr_disable_all(); 1890e1069839SBorislav Petkov } 1891e1069839SBorislav Petkov 1892e1069839SBorislav Petkov static void __intel_pmu_enable_all(int added, bool pmi) 1893e1069839SBorislav Petkov { 1894e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1895e1069839SBorislav Petkov 1896e1069839SBorislav Petkov intel_pmu_pebs_enable_all(); 1897e1069839SBorislav Petkov intel_pmu_lbr_enable_all(pmi); 1898e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1899e1069839SBorislav Petkov x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1900e1069839SBorislav Petkov 1901e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1902e1069839SBorislav Petkov struct perf_event *event = 1903e1069839SBorislav Petkov cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1904e1069839SBorislav Petkov 1905e1069839SBorislav Petkov if (WARN_ON_ONCE(!event)) 1906e1069839SBorislav Petkov return; 1907e1069839SBorislav Petkov 1908e1069839SBorislav Petkov intel_pmu_enable_bts(event->hw.config); 1909cecf6235SAlexander Shishkin } 1910e1069839SBorislav Petkov } 1911e1069839SBorislav Petkov 1912e1069839SBorislav Petkov static void intel_pmu_enable_all(int added) 1913e1069839SBorislav Petkov { 1914e1069839SBorislav Petkov __intel_pmu_enable_all(added, false); 1915e1069839SBorislav Petkov } 1916e1069839SBorislav Petkov 1917e1069839SBorislav Petkov /* 1918e1069839SBorislav Petkov * Workaround for: 1919e1069839SBorislav Petkov * Intel Errata AAK100 (model 26) 1920e1069839SBorislav Petkov * Intel Errata AAP53 (model 30) 1921e1069839SBorislav Petkov * Intel Errata BD53 (model 44) 1922e1069839SBorislav Petkov * 1923e1069839SBorislav Petkov * The official story: 1924e1069839SBorislav Petkov * These chips need to be 'reset' when adding counters by programming the 1925e1069839SBorislav Petkov * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 1926e1069839SBorislav Petkov * in sequence on the same PMC or on different PMCs. 1927e1069839SBorislav Petkov * 1928e1069839SBorislav Petkov * In practise it appears some of these events do in fact count, and 1929e1069839SBorislav Petkov * we need to programm all 4 events. 1930e1069839SBorislav Petkov */ 1931e1069839SBorislav Petkov static void intel_pmu_nhm_workaround(void) 1932e1069839SBorislav Petkov { 1933e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1934e1069839SBorislav Petkov static const unsigned long nhm_magic[4] = { 1935e1069839SBorislav Petkov 0x4300B5, 1936e1069839SBorislav Petkov 0x4300D2, 1937e1069839SBorislav Petkov 0x4300B1, 1938e1069839SBorislav Petkov 0x4300B1 1939e1069839SBorislav Petkov }; 1940e1069839SBorislav Petkov struct perf_event *event; 1941e1069839SBorislav Petkov int i; 1942e1069839SBorislav Petkov 1943e1069839SBorislav Petkov /* 1944e1069839SBorislav Petkov * The Errata requires below steps: 1945e1069839SBorislav Petkov * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 1946e1069839SBorislav Petkov * 2) Configure 4 PERFEVTSELx with the magic events and clear 1947e1069839SBorislav Petkov * the corresponding PMCx; 1948e1069839SBorislav Petkov * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 1949e1069839SBorislav Petkov * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 1950e1069839SBorislav Petkov * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 1951e1069839SBorislav Petkov */ 1952e1069839SBorislav Petkov 1953e1069839SBorislav Petkov /* 1954e1069839SBorislav Petkov * The real steps we choose are a little different from above. 1955e1069839SBorislav Petkov * A) To reduce MSR operations, we don't run step 1) as they 1956e1069839SBorislav Petkov * are already cleared before this function is called; 1957e1069839SBorislav Petkov * B) Call x86_perf_event_update to save PMCx before configuring 1958e1069839SBorislav Petkov * PERFEVTSELx with magic number; 1959e1069839SBorislav Petkov * C) With step 5), we do clear only when the PERFEVTSELx is 1960e1069839SBorislav Petkov * not used currently. 1961e1069839SBorislav Petkov * D) Call x86_perf_event_set_period to restore PMCx; 1962e1069839SBorislav Petkov */ 1963e1069839SBorislav Petkov 1964e1069839SBorislav Petkov /* We always operate 4 pairs of PERF Counters */ 1965e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 1966e1069839SBorislav Petkov event = cpuc->events[i]; 1967e1069839SBorislav Petkov if (event) 1968e1069839SBorislav Petkov x86_perf_event_update(event); 1969e1069839SBorislav Petkov } 1970e1069839SBorislav Petkov 1971e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 1972e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 1973e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 1974e1069839SBorislav Petkov } 1975e1069839SBorislav Petkov 1976e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 1977e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 1978e1069839SBorislav Petkov 1979e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 1980e1069839SBorislav Petkov event = cpuc->events[i]; 1981e1069839SBorislav Petkov 1982e1069839SBorislav Petkov if (event) { 1983e1069839SBorislav Petkov x86_perf_event_set_period(event); 1984e1069839SBorislav Petkov __x86_pmu_enable_event(&event->hw, 1985e1069839SBorislav Petkov ARCH_PERFMON_EVENTSEL_ENABLE); 1986e1069839SBorislav Petkov } else 1987e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 1988e1069839SBorislav Petkov } 1989e1069839SBorislav Petkov } 1990e1069839SBorislav Petkov 1991e1069839SBorislav Petkov static void intel_pmu_nhm_enable_all(int added) 1992e1069839SBorislav Petkov { 1993e1069839SBorislav Petkov if (added) 1994e1069839SBorislav Petkov intel_pmu_nhm_workaround(); 1995e1069839SBorislav Petkov intel_pmu_enable_all(added); 1996e1069839SBorislav Petkov } 1997e1069839SBorislav Petkov 1998e1069839SBorislav Petkov static inline u64 intel_pmu_get_status(void) 1999e1069839SBorislav Petkov { 2000e1069839SBorislav Petkov u64 status; 2001e1069839SBorislav Petkov 2002e1069839SBorislav Petkov rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2003e1069839SBorislav Petkov 2004e1069839SBorislav Petkov return status; 2005e1069839SBorislav Petkov } 2006e1069839SBorislav Petkov 2007e1069839SBorislav Petkov static inline void intel_pmu_ack_status(u64 ack) 2008e1069839SBorislav Petkov { 2009e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2010e1069839SBorislav Petkov } 2011e1069839SBorislav Petkov 2012e1069839SBorislav Petkov static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 2013e1069839SBorislav Petkov { 2014e1069839SBorislav Petkov int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2015e1069839SBorislav Petkov u64 ctrl_val, mask; 2016e1069839SBorislav Petkov 2017e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2018e1069839SBorislav Petkov 2019e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2020e1069839SBorislav Petkov ctrl_val &= ~mask; 2021e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2022e1069839SBorislav Petkov } 2023e1069839SBorislav Petkov 2024e1069839SBorislav Petkov static inline bool event_is_checkpointed(struct perf_event *event) 2025e1069839SBorislav Petkov { 2026e1069839SBorislav Petkov return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2027e1069839SBorislav Petkov } 2028e1069839SBorislav Petkov 2029e1069839SBorislav Petkov static void intel_pmu_disable_event(struct perf_event *event) 2030e1069839SBorislav Petkov { 2031e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2032e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2033e1069839SBorislav Petkov 2034e1069839SBorislav Petkov if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2035e1069839SBorislav Petkov intel_pmu_disable_bts(); 2036e1069839SBorislav Petkov intel_pmu_drain_bts_buffer(); 2037e1069839SBorislav Petkov return; 2038e1069839SBorislav Petkov } 2039e1069839SBorislav Petkov 2040e1069839SBorislav Petkov cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); 2041e1069839SBorislav Petkov cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); 2042e1069839SBorislav Petkov cpuc->intel_cp_status &= ~(1ull << hwc->idx); 2043e1069839SBorislav Petkov 2044e1069839SBorislav Petkov if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2045e1069839SBorislav Petkov intel_pmu_disable_fixed(hwc); 2046e1069839SBorislav Petkov return; 2047e1069839SBorislav Petkov } 2048e1069839SBorislav Petkov 2049e1069839SBorislav Petkov x86_pmu_disable_event(event); 2050e1069839SBorislav Petkov 2051e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2052e1069839SBorislav Petkov intel_pmu_pebs_disable(event); 2053e1069839SBorislav Petkov } 2054e1069839SBorislav Petkov 205568f7082fSPeter Zijlstra static void intel_pmu_del_event(struct perf_event *event) 205668f7082fSPeter Zijlstra { 205768f7082fSPeter Zijlstra if (needs_branch_stack(event)) 205868f7082fSPeter Zijlstra intel_pmu_lbr_del(event); 205968f7082fSPeter Zijlstra if (event->attr.precise_ip) 206068f7082fSPeter Zijlstra intel_pmu_pebs_del(event); 206168f7082fSPeter Zijlstra } 206268f7082fSPeter Zijlstra 2063e1069839SBorislav Petkov static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) 2064e1069839SBorislav Petkov { 2065e1069839SBorislav Petkov int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2066e1069839SBorislav Petkov u64 ctrl_val, bits, mask; 2067e1069839SBorislav Petkov 2068e1069839SBorislav Petkov /* 2069e1069839SBorislav Petkov * Enable IRQ generation (0x8), 2070e1069839SBorislav Petkov * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2071e1069839SBorislav Petkov * if requested: 2072e1069839SBorislav Petkov */ 2073e1069839SBorislav Petkov bits = 0x8ULL; 2074e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2075e1069839SBorislav Petkov bits |= 0x2; 2076e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2077e1069839SBorislav Petkov bits |= 0x1; 2078e1069839SBorislav Petkov 2079e1069839SBorislav Petkov /* 2080e1069839SBorislav Petkov * ANY bit is supported in v3 and up 2081e1069839SBorislav Petkov */ 2082e1069839SBorislav Petkov if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2083e1069839SBorislav Petkov bits |= 0x4; 2084e1069839SBorislav Petkov 2085e1069839SBorislav Petkov bits <<= (idx * 4); 2086e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2087e1069839SBorislav Petkov 2088e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2089e1069839SBorislav Petkov ctrl_val &= ~mask; 2090e1069839SBorislav Petkov ctrl_val |= bits; 2091e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2092e1069839SBorislav Petkov } 2093e1069839SBorislav Petkov 2094e1069839SBorislav Petkov static void intel_pmu_enable_event(struct perf_event *event) 2095e1069839SBorislav Petkov { 2096e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2097e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2098e1069839SBorislav Petkov 2099e1069839SBorislav Petkov if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2100e1069839SBorislav Petkov if (!__this_cpu_read(cpu_hw_events.enabled)) 2101e1069839SBorislav Petkov return; 2102e1069839SBorislav Petkov 2103e1069839SBorislav Petkov intel_pmu_enable_bts(hwc->config); 2104e1069839SBorislav Petkov return; 2105e1069839SBorislav Petkov } 2106e1069839SBorislav Petkov 2107e1069839SBorislav Petkov if (event->attr.exclude_host) 2108e1069839SBorislav Petkov cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); 2109e1069839SBorislav Petkov if (event->attr.exclude_guest) 2110e1069839SBorislav Petkov cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); 2111e1069839SBorislav Petkov 2112e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) 2113e1069839SBorislav Petkov cpuc->intel_cp_status |= (1ull << hwc->idx); 2114e1069839SBorislav Petkov 2115e1069839SBorislav Petkov if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 2116e1069839SBorislav Petkov intel_pmu_enable_fixed(hwc); 2117e1069839SBorislav Petkov return; 2118e1069839SBorislav Petkov } 2119e1069839SBorislav Petkov 2120e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2121e1069839SBorislav Petkov intel_pmu_pebs_enable(event); 2122e1069839SBorislav Petkov 2123e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2124e1069839SBorislav Petkov } 2125e1069839SBorislav Petkov 212668f7082fSPeter Zijlstra static void intel_pmu_add_event(struct perf_event *event) 212768f7082fSPeter Zijlstra { 212868f7082fSPeter Zijlstra if (event->attr.precise_ip) 212968f7082fSPeter Zijlstra intel_pmu_pebs_add(event); 213068f7082fSPeter Zijlstra if (needs_branch_stack(event)) 213168f7082fSPeter Zijlstra intel_pmu_lbr_add(event); 213268f7082fSPeter Zijlstra } 213368f7082fSPeter Zijlstra 2134e1069839SBorislav Petkov /* 2135e1069839SBorislav Petkov * Save and restart an expired event. Called by NMI contexts, 2136e1069839SBorislav Petkov * so it has to be careful about preempting normal event ops: 2137e1069839SBorislav Petkov */ 2138e1069839SBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event) 2139e1069839SBorislav Petkov { 2140e1069839SBorislav Petkov x86_perf_event_update(event); 2141e1069839SBorislav Petkov /* 2142e1069839SBorislav Petkov * For a checkpointed counter always reset back to 0. This 2143e1069839SBorislav Petkov * avoids a situation where the counter overflows, aborts the 2144e1069839SBorislav Petkov * transaction and is then set back to shortly before the 2145e1069839SBorislav Petkov * overflow, and overflows and aborts again. 2146e1069839SBorislav Petkov */ 2147e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) { 2148e1069839SBorislav Petkov /* No race with NMIs because the counter should not be armed */ 2149e1069839SBorislav Petkov wrmsrl(event->hw.event_base, 0); 2150e1069839SBorislav Petkov local64_set(&event->hw.prev_count, 0); 2151e1069839SBorislav Petkov } 2152e1069839SBorislav Petkov return x86_perf_event_set_period(event); 2153e1069839SBorislav Petkov } 2154e1069839SBorislav Petkov 2155e1069839SBorislav Petkov static void intel_pmu_reset(void) 2156e1069839SBorislav Petkov { 2157e1069839SBorislav Petkov struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2158e1069839SBorislav Petkov unsigned long flags; 2159e1069839SBorislav Petkov int idx; 2160e1069839SBorislav Petkov 2161e1069839SBorislav Petkov if (!x86_pmu.num_counters) 2162e1069839SBorislav Petkov return; 2163e1069839SBorislav Petkov 2164e1069839SBorislav Petkov local_irq_save(flags); 2165e1069839SBorislav Petkov 2166e1069839SBorislav Petkov pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2167e1069839SBorislav Petkov 2168e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2169e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2170e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2171e1069839SBorislav Petkov } 2172e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2173e1069839SBorislav Petkov wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2174e1069839SBorislav Petkov 2175e1069839SBorislav Petkov if (ds) 2176e1069839SBorislav Petkov ds->bts_index = ds->bts_buffer_base; 2177e1069839SBorislav Petkov 2178e1069839SBorislav Petkov /* Ack all overflows and disable fixed counters */ 2179e1069839SBorislav Petkov if (x86_pmu.version >= 2) { 2180e1069839SBorislav Petkov intel_pmu_ack_status(intel_pmu_get_status()); 2181e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2182e1069839SBorislav Petkov } 2183e1069839SBorislav Petkov 2184e1069839SBorislav Petkov /* Reset LBRs and LBR freezing */ 2185e1069839SBorislav Petkov if (x86_pmu.lbr_nr) { 2186e1069839SBorislav Petkov update_debugctlmsr(get_debugctlmsr() & 2187e1069839SBorislav Petkov ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2188e1069839SBorislav Petkov } 2189e1069839SBorislav Petkov 2190e1069839SBorislav Petkov local_irq_restore(flags); 2191e1069839SBorislav Petkov } 2192e1069839SBorislav Petkov 2193e1069839SBorislav Petkov /* 2194e1069839SBorislav Petkov * This handler is triggered by the local APIC, so the APIC IRQ handling 2195e1069839SBorislav Petkov * rules apply: 2196e1069839SBorislav Petkov */ 2197e1069839SBorislav Petkov static int intel_pmu_handle_irq(struct pt_regs *regs) 2198e1069839SBorislav Petkov { 2199e1069839SBorislav Petkov struct perf_sample_data data; 2200e1069839SBorislav Petkov struct cpu_hw_events *cpuc; 2201e1069839SBorislav Petkov int bit, loops; 2202e1069839SBorislav Petkov u64 status; 2203e1069839SBorislav Petkov int handled; 2204e1069839SBorislav Petkov 2205e1069839SBorislav Petkov cpuc = this_cpu_ptr(&cpu_hw_events); 2206e1069839SBorislav Petkov 2207e1069839SBorislav Petkov /* 2208e1069839SBorislav Petkov * No known reason to not always do late ACK, 2209e1069839SBorislav Petkov * but just in case do it opt-in. 2210e1069839SBorislav Petkov */ 2211e1069839SBorislav Petkov if (!x86_pmu.late_ack) 2212e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 2213cecf6235SAlexander Shishkin intel_bts_disable_local(); 2214e1069839SBorislav Petkov __intel_pmu_disable_all(); 2215e1069839SBorislav Petkov handled = intel_pmu_drain_bts_buffer(); 2216e1069839SBorislav Petkov handled += intel_bts_interrupt(); 2217e1069839SBorislav Petkov status = intel_pmu_get_status(); 2218e1069839SBorislav Petkov if (!status) 2219e1069839SBorislav Petkov goto done; 2220e1069839SBorislav Petkov 2221e1069839SBorislav Petkov loops = 0; 2222e1069839SBorislav Petkov again: 2223e1069839SBorislav Petkov intel_pmu_lbr_read(); 2224e1069839SBorislav Petkov intel_pmu_ack_status(status); 2225e1069839SBorislav Petkov if (++loops > 100) { 2226e1069839SBorislav Petkov static bool warned = false; 2227e1069839SBorislav Petkov if (!warned) { 2228e1069839SBorislav Petkov WARN(1, "perfevents: irq loop stuck!\n"); 2229e1069839SBorislav Petkov perf_event_print_debug(); 2230e1069839SBorislav Petkov warned = true; 2231e1069839SBorislav Petkov } 2232e1069839SBorislav Petkov intel_pmu_reset(); 2233e1069839SBorislav Petkov goto done; 2234e1069839SBorislav Petkov } 2235e1069839SBorislav Petkov 2236e1069839SBorislav Petkov inc_irq_stat(apic_perf_irqs); 2237e1069839SBorislav Petkov 2238e1069839SBorislav Petkov 2239e1069839SBorislav Petkov /* 2240e1069839SBorislav Petkov * Ignore a range of extra bits in status that do not indicate 2241e1069839SBorislav Petkov * overflow by themselves. 2242e1069839SBorislav Petkov */ 2243e1069839SBorislav Petkov status &= ~(GLOBAL_STATUS_COND_CHG | 2244e1069839SBorislav Petkov GLOBAL_STATUS_ASIF | 2245e1069839SBorislav Petkov GLOBAL_STATUS_LBRS_FROZEN); 2246e1069839SBorislav Petkov if (!status) 2247e1069839SBorislav Petkov goto done; 2248daa864b8SStephane Eranian /* 2249daa864b8SStephane Eranian * In case multiple PEBS events are sampled at the same time, 2250daa864b8SStephane Eranian * it is possible to have GLOBAL_STATUS bit 62 set indicating 2251daa864b8SStephane Eranian * PEBS buffer overflow and also seeing at most 3 PEBS counters 2252daa864b8SStephane Eranian * having their bits set in the status register. This is a sign 2253daa864b8SStephane Eranian * that there was at least one PEBS record pending at the time 2254daa864b8SStephane Eranian * of the PMU interrupt. PEBS counters must only be processed 2255daa864b8SStephane Eranian * via the drain_pebs() calls and not via the regular sample 2256daa864b8SStephane Eranian * processing loop coming after that the function, otherwise 2257daa864b8SStephane Eranian * phony regular samples may be generated in the sampling buffer 2258daa864b8SStephane Eranian * not marked with the EXACT tag. Another possibility is to have 2259daa864b8SStephane Eranian * one PEBS event and at least one non-PEBS event whic hoverflows 2260daa864b8SStephane Eranian * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2261daa864b8SStephane Eranian * not be set, yet the overflow status bit for the PEBS counter will 2262daa864b8SStephane Eranian * be on Skylake. 2263daa864b8SStephane Eranian * 2264daa864b8SStephane Eranian * To avoid this problem, we systematically ignore the PEBS-enabled 2265daa864b8SStephane Eranian * counters from the GLOBAL_STATUS mask and we always process PEBS 2266daa864b8SStephane Eranian * events via drain_pebs(). 2267daa864b8SStephane Eranian */ 2268fd583ad1SKan Liang status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2269e1069839SBorislav Petkov 2270e1069839SBorislav Petkov /* 2271e1069839SBorislav Petkov * PEBS overflow sets bit 62 in the global status register 2272e1069839SBorislav Petkov */ 2273e1069839SBorislav Petkov if (__test_and_clear_bit(62, (unsigned long *)&status)) { 2274e1069839SBorislav Petkov handled++; 2275e1069839SBorislav Petkov x86_pmu.drain_pebs(regs); 22768077eca0SStephane Eranian status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2277e1069839SBorislav Petkov } 2278e1069839SBorislav Petkov 2279e1069839SBorislav Petkov /* 2280e1069839SBorislav Petkov * Intel PT 2281e1069839SBorislav Petkov */ 2282e1069839SBorislav Petkov if (__test_and_clear_bit(55, (unsigned long *)&status)) { 2283e1069839SBorislav Petkov handled++; 2284e1069839SBorislav Petkov intel_pt_interrupt(); 2285e1069839SBorislav Petkov } 2286e1069839SBorislav Petkov 2287e1069839SBorislav Petkov /* 2288e1069839SBorislav Petkov * Checkpointed counters can lead to 'spurious' PMIs because the 2289e1069839SBorislav Petkov * rollback caused by the PMI will have cleared the overflow status 2290e1069839SBorislav Petkov * bit. Therefore always force probe these counters. 2291e1069839SBorislav Petkov */ 2292e1069839SBorislav Petkov status |= cpuc->intel_cp_status; 2293e1069839SBorislav Petkov 2294e1069839SBorislav Petkov for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2295e1069839SBorislav Petkov struct perf_event *event = cpuc->events[bit]; 2296e1069839SBorislav Petkov 2297e1069839SBorislav Petkov handled++; 2298e1069839SBorislav Petkov 2299e1069839SBorislav Petkov if (!test_bit(bit, cpuc->active_mask)) 2300e1069839SBorislav Petkov continue; 2301e1069839SBorislav Petkov 2302e1069839SBorislav Petkov if (!intel_pmu_save_and_restart(event)) 2303e1069839SBorislav Petkov continue; 2304e1069839SBorislav Petkov 2305e1069839SBorislav Petkov perf_sample_data_init(&data, 0, event->hw.last_period); 2306e1069839SBorislav Petkov 2307e1069839SBorislav Petkov if (has_branch_stack(event)) 2308e1069839SBorislav Petkov data.br_stack = &cpuc->lbr_stack; 2309e1069839SBorislav Petkov 2310e1069839SBorislav Petkov if (perf_event_overflow(event, &data, regs)) 2311e1069839SBorislav Petkov x86_pmu_stop(event, 0); 2312e1069839SBorislav Petkov } 2313e1069839SBorislav Petkov 2314e1069839SBorislav Petkov /* 2315e1069839SBorislav Petkov * Repeat if there is more work to be done: 2316e1069839SBorislav Petkov */ 2317e1069839SBorislav Petkov status = intel_pmu_get_status(); 2318e1069839SBorislav Petkov if (status) 2319e1069839SBorislav Petkov goto again; 2320e1069839SBorislav Petkov 2321e1069839SBorislav Petkov done: 2322c3d266c8SKan Liang /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 2323c3d266c8SKan Liang if (cpuc->enabled) 2324e1069839SBorislav Petkov __intel_pmu_enable_all(0, true); 2325cecf6235SAlexander Shishkin intel_bts_enable_local(); 2326c3d266c8SKan Liang 2327e1069839SBorislav Petkov /* 2328e1069839SBorislav Petkov * Only unmask the NMI after the overflow counters 2329e1069839SBorislav Petkov * have been reset. This avoids spurious NMIs on 2330e1069839SBorislav Petkov * Haswell CPUs. 2331e1069839SBorislav Petkov */ 2332e1069839SBorislav Petkov if (x86_pmu.late_ack) 2333e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 2334e1069839SBorislav Petkov return handled; 2335e1069839SBorislav Petkov } 2336e1069839SBorislav Petkov 2337e1069839SBorislav Petkov static struct event_constraint * 2338e1069839SBorislav Petkov intel_bts_constraints(struct perf_event *event) 2339e1069839SBorislav Petkov { 2340e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2341e1069839SBorislav Petkov unsigned int hw_event, bts_event; 2342e1069839SBorislav Petkov 2343e1069839SBorislav Petkov if (event->attr.freq) 2344e1069839SBorislav Petkov return NULL; 2345e1069839SBorislav Petkov 2346e1069839SBorislav Petkov hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 2347e1069839SBorislav Petkov bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 2348e1069839SBorislav Petkov 2349e1069839SBorislav Petkov if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) 2350e1069839SBorislav Petkov return &bts_constraint; 2351e1069839SBorislav Petkov 2352e1069839SBorislav Petkov return NULL; 2353e1069839SBorislav Petkov } 2354e1069839SBorislav Petkov 2355e1069839SBorislav Petkov static int intel_alt_er(int idx, u64 config) 2356e1069839SBorislav Petkov { 2357e1069839SBorislav Petkov int alt_idx = idx; 2358e1069839SBorislav Petkov 2359e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2360e1069839SBorislav Petkov return idx; 2361e1069839SBorislav Petkov 2362e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) 2363e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_1; 2364e1069839SBorislav Petkov 2365e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_1) 2366e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_0; 2367e1069839SBorislav Petkov 2368e1069839SBorislav Petkov if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2369e1069839SBorislav Petkov return idx; 2370e1069839SBorislav Petkov 2371e1069839SBorislav Petkov return alt_idx; 2372e1069839SBorislav Petkov } 2373e1069839SBorislav Petkov 2374e1069839SBorislav Petkov static void intel_fixup_er(struct perf_event *event, int idx) 2375e1069839SBorislav Petkov { 2376e1069839SBorislav Petkov event->hw.extra_reg.idx = idx; 2377e1069839SBorislav Petkov 2378e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) { 2379e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2380e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2381e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2382e1069839SBorislav Petkov } else if (idx == EXTRA_REG_RSP_1) { 2383e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2384e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2385e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2386e1069839SBorislav Petkov } 2387e1069839SBorislav Petkov } 2388e1069839SBorislav Petkov 2389e1069839SBorislav Petkov /* 2390e1069839SBorislav Petkov * manage allocation of shared extra msr for certain events 2391e1069839SBorislav Petkov * 2392e1069839SBorislav Petkov * sharing can be: 2393e1069839SBorislav Petkov * per-cpu: to be shared between the various events on a single PMU 2394e1069839SBorislav Petkov * per-core: per-cpu + shared by HT threads 2395e1069839SBorislav Petkov */ 2396e1069839SBorislav Petkov static struct event_constraint * 2397e1069839SBorislav Petkov __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2398e1069839SBorislav Petkov struct perf_event *event, 2399e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2400e1069839SBorislav Petkov { 2401e1069839SBorislav Petkov struct event_constraint *c = &emptyconstraint; 2402e1069839SBorislav Petkov struct er_account *era; 2403e1069839SBorislav Petkov unsigned long flags; 2404e1069839SBorislav Petkov int idx = reg->idx; 2405e1069839SBorislav Petkov 2406e1069839SBorislav Petkov /* 2407e1069839SBorislav Petkov * reg->alloc can be set due to existing state, so for fake cpuc we 2408e1069839SBorislav Petkov * need to ignore this, otherwise we might fail to allocate proper fake 2409e1069839SBorislav Petkov * state for this extra reg constraint. Also see the comment below. 2410e1069839SBorislav Petkov */ 2411e1069839SBorislav Petkov if (reg->alloc && !cpuc->is_fake) 2412e1069839SBorislav Petkov return NULL; /* call x86_get_event_constraint() */ 2413e1069839SBorislav Petkov 2414e1069839SBorislav Petkov again: 2415e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[idx]; 2416e1069839SBorislav Petkov /* 2417e1069839SBorislav Petkov * we use spin_lock_irqsave() to avoid lockdep issues when 2418e1069839SBorislav Petkov * passing a fake cpuc 2419e1069839SBorislav Petkov */ 2420e1069839SBorislav Petkov raw_spin_lock_irqsave(&era->lock, flags); 2421e1069839SBorislav Petkov 2422e1069839SBorislav Petkov if (!atomic_read(&era->ref) || era->config == reg->config) { 2423e1069839SBorislav Petkov 2424e1069839SBorislav Petkov /* 2425e1069839SBorislav Petkov * If its a fake cpuc -- as per validate_{group,event}() we 2426e1069839SBorislav Petkov * shouldn't touch event state and we can avoid doing so 2427e1069839SBorislav Petkov * since both will only call get_event_constraints() once 2428e1069839SBorislav Petkov * on each event, this avoids the need for reg->alloc. 2429e1069839SBorislav Petkov * 2430e1069839SBorislav Petkov * Not doing the ER fixup will only result in era->reg being 2431e1069839SBorislav Petkov * wrong, but since we won't actually try and program hardware 2432e1069839SBorislav Petkov * this isn't a problem either. 2433e1069839SBorislav Petkov */ 2434e1069839SBorislav Petkov if (!cpuc->is_fake) { 2435e1069839SBorislav Petkov if (idx != reg->idx) 2436e1069839SBorislav Petkov intel_fixup_er(event, idx); 2437e1069839SBorislav Petkov 2438e1069839SBorislav Petkov /* 2439e1069839SBorislav Petkov * x86_schedule_events() can call get_event_constraints() 2440e1069839SBorislav Petkov * multiple times on events in the case of incremental 2441e1069839SBorislav Petkov * scheduling(). reg->alloc ensures we only do the ER 2442e1069839SBorislav Petkov * allocation once. 2443e1069839SBorislav Petkov */ 2444e1069839SBorislav Petkov reg->alloc = 1; 2445e1069839SBorislav Petkov } 2446e1069839SBorislav Petkov 2447e1069839SBorislav Petkov /* lock in msr value */ 2448e1069839SBorislav Petkov era->config = reg->config; 2449e1069839SBorislav Petkov era->reg = reg->reg; 2450e1069839SBorislav Petkov 2451e1069839SBorislav Petkov /* one more user */ 2452e1069839SBorislav Petkov atomic_inc(&era->ref); 2453e1069839SBorislav Petkov 2454e1069839SBorislav Petkov /* 2455e1069839SBorislav Petkov * need to call x86_get_event_constraint() 2456e1069839SBorislav Petkov * to check if associated event has constraints 2457e1069839SBorislav Petkov */ 2458e1069839SBorislav Petkov c = NULL; 2459e1069839SBorislav Petkov } else { 2460e1069839SBorislav Petkov idx = intel_alt_er(idx, reg->config); 2461e1069839SBorislav Petkov if (idx != reg->idx) { 2462e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2463e1069839SBorislav Petkov goto again; 2464e1069839SBorislav Petkov } 2465e1069839SBorislav Petkov } 2466e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2467e1069839SBorislav Petkov 2468e1069839SBorislav Petkov return c; 2469e1069839SBorislav Petkov } 2470e1069839SBorislav Petkov 2471e1069839SBorislav Petkov static void 2472e1069839SBorislav Petkov __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 2473e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2474e1069839SBorislav Petkov { 2475e1069839SBorislav Petkov struct er_account *era; 2476e1069839SBorislav Petkov 2477e1069839SBorislav Petkov /* 2478e1069839SBorislav Petkov * Only put constraint if extra reg was actually allocated. Also takes 2479e1069839SBorislav Petkov * care of event which do not use an extra shared reg. 2480e1069839SBorislav Petkov * 2481e1069839SBorislav Petkov * Also, if this is a fake cpuc we shouldn't touch any event state 2482e1069839SBorislav Petkov * (reg->alloc) and we don't care about leaving inconsistent cpuc state 2483e1069839SBorislav Petkov * either since it'll be thrown out. 2484e1069839SBorislav Petkov */ 2485e1069839SBorislav Petkov if (!reg->alloc || cpuc->is_fake) 2486e1069839SBorislav Petkov return; 2487e1069839SBorislav Petkov 2488e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[reg->idx]; 2489e1069839SBorislav Petkov 2490e1069839SBorislav Petkov /* one fewer user */ 2491e1069839SBorislav Petkov atomic_dec(&era->ref); 2492e1069839SBorislav Petkov 2493e1069839SBorislav Petkov /* allocate again next time */ 2494e1069839SBorislav Petkov reg->alloc = 0; 2495e1069839SBorislav Petkov } 2496e1069839SBorislav Petkov 2497e1069839SBorislav Petkov static struct event_constraint * 2498e1069839SBorislav Petkov intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 2499e1069839SBorislav Petkov struct perf_event *event) 2500e1069839SBorislav Petkov { 2501e1069839SBorislav Petkov struct event_constraint *c = NULL, *d; 2502e1069839SBorislav Petkov struct hw_perf_event_extra *xreg, *breg; 2503e1069839SBorislav Petkov 2504e1069839SBorislav Petkov xreg = &event->hw.extra_reg; 2505e1069839SBorislav Petkov if (xreg->idx != EXTRA_REG_NONE) { 2506e1069839SBorislav Petkov c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 2507e1069839SBorislav Petkov if (c == &emptyconstraint) 2508e1069839SBorislav Petkov return c; 2509e1069839SBorislav Petkov } 2510e1069839SBorislav Petkov breg = &event->hw.branch_reg; 2511e1069839SBorislav Petkov if (breg->idx != EXTRA_REG_NONE) { 2512e1069839SBorislav Petkov d = __intel_shared_reg_get_constraints(cpuc, event, breg); 2513e1069839SBorislav Petkov if (d == &emptyconstraint) { 2514e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, xreg); 2515e1069839SBorislav Petkov c = d; 2516e1069839SBorislav Petkov } 2517e1069839SBorislav Petkov } 2518e1069839SBorislav Petkov return c; 2519e1069839SBorislav Petkov } 2520e1069839SBorislav Petkov 2521e1069839SBorislav Petkov struct event_constraint * 2522e1069839SBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2523e1069839SBorislav Petkov struct perf_event *event) 2524e1069839SBorislav Petkov { 2525e1069839SBorislav Petkov struct event_constraint *c; 2526e1069839SBorislav Petkov 2527e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 2528e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 2529e1069839SBorislav Petkov if ((event->hw.config & c->cmask) == c->code) { 2530e1069839SBorislav Petkov event->hw.flags |= c->flags; 2531e1069839SBorislav Petkov return c; 2532e1069839SBorislav Petkov } 2533e1069839SBorislav Petkov } 2534e1069839SBorislav Petkov } 2535e1069839SBorislav Petkov 2536e1069839SBorislav Petkov return &unconstrained; 2537e1069839SBorislav Petkov } 2538e1069839SBorislav Petkov 2539e1069839SBorislav Petkov static struct event_constraint * 2540e1069839SBorislav Petkov __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2541e1069839SBorislav Petkov struct perf_event *event) 2542e1069839SBorislav Petkov { 2543e1069839SBorislav Petkov struct event_constraint *c; 2544e1069839SBorislav Petkov 2545e1069839SBorislav Petkov c = intel_bts_constraints(event); 2546e1069839SBorislav Petkov if (c) 2547e1069839SBorislav Petkov return c; 2548e1069839SBorislav Petkov 2549e1069839SBorislav Petkov c = intel_shared_regs_constraints(cpuc, event); 2550e1069839SBorislav Petkov if (c) 2551e1069839SBorislav Petkov return c; 2552e1069839SBorislav Petkov 2553e1069839SBorislav Petkov c = intel_pebs_constraints(event); 2554e1069839SBorislav Petkov if (c) 2555e1069839SBorislav Petkov return c; 2556e1069839SBorislav Petkov 2557e1069839SBorislav Petkov return x86_get_event_constraints(cpuc, idx, event); 2558e1069839SBorislav Petkov } 2559e1069839SBorislav Petkov 2560e1069839SBorislav Petkov static void 2561e1069839SBorislav Petkov intel_start_scheduling(struct cpu_hw_events *cpuc) 2562e1069839SBorislav Petkov { 2563e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2564e1069839SBorislav Petkov struct intel_excl_states *xl; 2565e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2566e1069839SBorislav Petkov 2567e1069839SBorislav Petkov /* 2568e1069839SBorislav Petkov * nothing needed if in group validation mode 2569e1069839SBorislav Petkov */ 2570e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2571e1069839SBorislav Petkov return; 2572e1069839SBorislav Petkov 2573e1069839SBorislav Petkov /* 2574e1069839SBorislav Petkov * no exclusion needed 2575e1069839SBorislav Petkov */ 2576e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2577e1069839SBorislav Petkov return; 2578e1069839SBorislav Petkov 2579e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2580e1069839SBorislav Petkov 2581e1069839SBorislav Petkov xl->sched_started = true; 2582e1069839SBorislav Petkov /* 2583e1069839SBorislav Petkov * lock shared state until we are done scheduling 2584e1069839SBorislav Petkov * in stop_event_scheduling() 2585e1069839SBorislav Petkov * makes scheduling appear as a transaction 2586e1069839SBorislav Petkov */ 2587e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 2588e1069839SBorislav Petkov } 2589e1069839SBorislav Petkov 2590e1069839SBorislav Petkov static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2591e1069839SBorislav Petkov { 2592e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2593e1069839SBorislav Petkov struct event_constraint *c = cpuc->event_constraint[idx]; 2594e1069839SBorislav Petkov struct intel_excl_states *xl; 2595e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2596e1069839SBorislav Petkov 2597e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2598e1069839SBorislav Petkov return; 2599e1069839SBorislav Petkov 2600e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2601e1069839SBorislav Petkov return; 2602e1069839SBorislav Petkov 2603e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 2604e1069839SBorislav Petkov return; 2605e1069839SBorislav Petkov 2606e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2607e1069839SBorislav Petkov 2608e1069839SBorislav Petkov lockdep_assert_held(&excl_cntrs->lock); 2609e1069839SBorislav Petkov 2610e1069839SBorislav Petkov if (c->flags & PERF_X86_EVENT_EXCL) 2611e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 2612e1069839SBorislav Petkov else 2613e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_SHARED; 2614e1069839SBorislav Petkov } 2615e1069839SBorislav Petkov 2616e1069839SBorislav Petkov static void 2617e1069839SBorislav Petkov intel_stop_scheduling(struct cpu_hw_events *cpuc) 2618e1069839SBorislav Petkov { 2619e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2620e1069839SBorislav Petkov struct intel_excl_states *xl; 2621e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2622e1069839SBorislav Petkov 2623e1069839SBorislav Petkov /* 2624e1069839SBorislav Petkov * nothing needed if in group validation mode 2625e1069839SBorislav Petkov */ 2626e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2627e1069839SBorislav Petkov return; 2628e1069839SBorislav Petkov /* 2629e1069839SBorislav Petkov * no exclusion needed 2630e1069839SBorislav Petkov */ 2631e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2632e1069839SBorislav Petkov return; 2633e1069839SBorislav Petkov 2634e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2635e1069839SBorislav Petkov 2636e1069839SBorislav Petkov xl->sched_started = false; 2637e1069839SBorislav Petkov /* 2638e1069839SBorislav Petkov * release shared state lock (acquired in intel_start_scheduling()) 2639e1069839SBorislav Petkov */ 2640e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 2641e1069839SBorislav Petkov } 2642e1069839SBorislav Petkov 2643e1069839SBorislav Petkov static struct event_constraint * 2644e1069839SBorislav Petkov intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 2645e1069839SBorislav Petkov int idx, struct event_constraint *c) 2646e1069839SBorislav Petkov { 2647e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2648e1069839SBorislav Petkov struct intel_excl_states *xlo; 2649e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2650e1069839SBorislav Petkov int is_excl, i; 2651e1069839SBorislav Petkov 2652e1069839SBorislav Petkov /* 2653e1069839SBorislav Petkov * validating a group does not require 2654e1069839SBorislav Petkov * enforcing cross-thread exclusion 2655e1069839SBorislav Petkov */ 2656e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2657e1069839SBorislav Petkov return c; 2658e1069839SBorislav Petkov 2659e1069839SBorislav Petkov /* 2660e1069839SBorislav Petkov * no exclusion needed 2661e1069839SBorislav Petkov */ 2662e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2663e1069839SBorislav Petkov return c; 2664e1069839SBorislav Petkov 2665e1069839SBorislav Petkov /* 2666e1069839SBorislav Petkov * because we modify the constraint, we need 2667e1069839SBorislav Petkov * to make a copy. Static constraints come 2668e1069839SBorislav Petkov * from static const tables. 2669e1069839SBorislav Petkov * 2670e1069839SBorislav Petkov * only needed when constraint has not yet 2671e1069839SBorislav Petkov * been cloned (marked dynamic) 2672e1069839SBorislav Petkov */ 2673e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 2674e1069839SBorislav Petkov struct event_constraint *cx; 2675e1069839SBorislav Petkov 2676e1069839SBorislav Petkov /* 2677e1069839SBorislav Petkov * grab pre-allocated constraint entry 2678e1069839SBorislav Petkov */ 2679e1069839SBorislav Petkov cx = &cpuc->constraint_list[idx]; 2680e1069839SBorislav Petkov 2681e1069839SBorislav Petkov /* 2682e1069839SBorislav Petkov * initialize dynamic constraint 2683e1069839SBorislav Petkov * with static constraint 2684e1069839SBorislav Petkov */ 2685e1069839SBorislav Petkov *cx = *c; 2686e1069839SBorislav Petkov 2687e1069839SBorislav Petkov /* 2688e1069839SBorislav Petkov * mark constraint as dynamic, so we 2689e1069839SBorislav Petkov * can free it later on 2690e1069839SBorislav Petkov */ 2691e1069839SBorislav Petkov cx->flags |= PERF_X86_EVENT_DYNAMIC; 2692e1069839SBorislav Petkov c = cx; 2693e1069839SBorislav Petkov } 2694e1069839SBorislav Petkov 2695e1069839SBorislav Petkov /* 2696e1069839SBorislav Petkov * From here on, the constraint is dynamic. 2697e1069839SBorislav Petkov * Either it was just allocated above, or it 2698e1069839SBorislav Petkov * was allocated during a earlier invocation 2699e1069839SBorislav Petkov * of this function 2700e1069839SBorislav Petkov */ 2701e1069839SBorislav Petkov 2702e1069839SBorislav Petkov /* 2703e1069839SBorislav Petkov * state of sibling HT 2704e1069839SBorislav Petkov */ 2705e1069839SBorislav Petkov xlo = &excl_cntrs->states[tid ^ 1]; 2706e1069839SBorislav Petkov 2707e1069839SBorislav Petkov /* 2708e1069839SBorislav Petkov * event requires exclusive counter access 2709e1069839SBorislav Petkov * across HT threads 2710e1069839SBorislav Petkov */ 2711e1069839SBorislav Petkov is_excl = c->flags & PERF_X86_EVENT_EXCL; 2712e1069839SBorislav Petkov if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 2713e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 2714e1069839SBorislav Petkov if (!cpuc->n_excl++) 2715e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 2716e1069839SBorislav Petkov } 2717e1069839SBorislav Petkov 2718e1069839SBorislav Petkov /* 2719e1069839SBorislav Petkov * Modify static constraint with current dynamic 2720e1069839SBorislav Petkov * state of thread 2721e1069839SBorislav Petkov * 2722e1069839SBorislav Petkov * EXCLUSIVE: sibling counter measuring exclusive event 2723e1069839SBorislav Petkov * SHARED : sibling counter measuring non-exclusive event 2724e1069839SBorislav Petkov * UNUSED : sibling counter unused 2725e1069839SBorislav Petkov */ 2726e1069839SBorislav Petkov for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 2727e1069839SBorislav Petkov /* 2728e1069839SBorislav Petkov * exclusive event in sibling counter 2729e1069839SBorislav Petkov * our corresponding counter cannot be used 2730e1069839SBorislav Petkov * regardless of our event 2731e1069839SBorislav Petkov */ 2732e1069839SBorislav Petkov if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) 2733e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 2734e1069839SBorislav Petkov /* 2735e1069839SBorislav Petkov * if measuring an exclusive event, sibling 2736e1069839SBorislav Petkov * measuring non-exclusive, then counter cannot 2737e1069839SBorislav Petkov * be used 2738e1069839SBorislav Petkov */ 2739e1069839SBorislav Petkov if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) 2740e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 2741e1069839SBorislav Petkov } 2742e1069839SBorislav Petkov 2743e1069839SBorislav Petkov /* 2744e1069839SBorislav Petkov * recompute actual bit weight for scheduling algorithm 2745e1069839SBorislav Petkov */ 2746e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 2747e1069839SBorislav Petkov 2748e1069839SBorislav Petkov /* 2749e1069839SBorislav Petkov * if we return an empty mask, then switch 2750e1069839SBorislav Petkov * back to static empty constraint to avoid 2751e1069839SBorislav Petkov * the cost of freeing later on 2752e1069839SBorislav Petkov */ 2753e1069839SBorislav Petkov if (c->weight == 0) 2754e1069839SBorislav Petkov c = &emptyconstraint; 2755e1069839SBorislav Petkov 2756e1069839SBorislav Petkov return c; 2757e1069839SBorislav Petkov } 2758e1069839SBorislav Petkov 2759e1069839SBorislav Petkov static struct event_constraint * 2760e1069839SBorislav Petkov intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2761e1069839SBorislav Petkov struct perf_event *event) 2762e1069839SBorislav Petkov { 2763e1069839SBorislav Petkov struct event_constraint *c1 = NULL; 2764e1069839SBorislav Petkov struct event_constraint *c2; 2765e1069839SBorislav Petkov 2766e1069839SBorislav Petkov if (idx >= 0) /* fake does < 0 */ 2767e1069839SBorislav Petkov c1 = cpuc->event_constraint[idx]; 2768e1069839SBorislav Petkov 2769e1069839SBorislav Petkov /* 2770e1069839SBorislav Petkov * first time only 2771e1069839SBorislav Petkov * - static constraint: no change across incremental scheduling calls 2772e1069839SBorislav Petkov * - dynamic constraint: handled by intel_get_excl_constraints() 2773e1069839SBorislav Petkov */ 2774e1069839SBorislav Petkov c2 = __intel_get_event_constraints(cpuc, idx, event); 2775e1069839SBorislav Petkov if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) { 2776e1069839SBorislav Petkov bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 2777e1069839SBorislav Petkov c1->weight = c2->weight; 2778e1069839SBorislav Petkov c2 = c1; 2779e1069839SBorislav Petkov } 2780e1069839SBorislav Petkov 2781e1069839SBorislav Petkov if (cpuc->excl_cntrs) 2782e1069839SBorislav Petkov return intel_get_excl_constraints(cpuc, event, idx, c2); 2783e1069839SBorislav Petkov 2784e1069839SBorislav Petkov return c2; 2785e1069839SBorislav Petkov } 2786e1069839SBorislav Petkov 2787e1069839SBorislav Petkov static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 2788e1069839SBorislav Petkov struct perf_event *event) 2789e1069839SBorislav Petkov { 2790e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2791e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2792e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2793e1069839SBorislav Petkov struct intel_excl_states *xl; 2794e1069839SBorislav Petkov 2795e1069839SBorislav Petkov /* 2796e1069839SBorislav Petkov * nothing needed if in group validation mode 2797e1069839SBorislav Petkov */ 2798e1069839SBorislav Petkov if (cpuc->is_fake) 2799e1069839SBorislav Petkov return; 2800e1069839SBorislav Petkov 2801e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2802e1069839SBorislav Petkov return; 2803e1069839SBorislav Petkov 2804e1069839SBorislav Petkov if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 2805e1069839SBorislav Petkov hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 2806e1069839SBorislav Petkov if (!--cpuc->n_excl) 2807e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 2808e1069839SBorislav Petkov } 2809e1069839SBorislav Petkov 2810e1069839SBorislav Petkov /* 2811e1069839SBorislav Petkov * If event was actually assigned, then mark the counter state as 2812e1069839SBorislav Petkov * unused now. 2813e1069839SBorislav Petkov */ 2814e1069839SBorislav Petkov if (hwc->idx >= 0) { 2815e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2816e1069839SBorislav Petkov 2817e1069839SBorislav Petkov /* 2818e1069839SBorislav Petkov * put_constraint may be called from x86_schedule_events() 2819e1069839SBorislav Petkov * which already has the lock held so here make locking 2820e1069839SBorislav Petkov * conditional. 2821e1069839SBorislav Petkov */ 2822e1069839SBorislav Petkov if (!xl->sched_started) 2823e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 2824e1069839SBorislav Petkov 2825e1069839SBorislav Petkov xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 2826e1069839SBorislav Petkov 2827e1069839SBorislav Petkov if (!xl->sched_started) 2828e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 2829e1069839SBorislav Petkov } 2830e1069839SBorislav Petkov } 2831e1069839SBorislav Petkov 2832e1069839SBorislav Petkov static void 2833e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 2834e1069839SBorislav Petkov struct perf_event *event) 2835e1069839SBorislav Petkov { 2836e1069839SBorislav Petkov struct hw_perf_event_extra *reg; 2837e1069839SBorislav Petkov 2838e1069839SBorislav Petkov reg = &event->hw.extra_reg; 2839e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 2840e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 2841e1069839SBorislav Petkov 2842e1069839SBorislav Petkov reg = &event->hw.branch_reg; 2843e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 2844e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 2845e1069839SBorislav Petkov } 2846e1069839SBorislav Petkov 2847e1069839SBorislav Petkov static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 2848e1069839SBorislav Petkov struct perf_event *event) 2849e1069839SBorislav Petkov { 2850e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(cpuc, event); 2851e1069839SBorislav Petkov 2852e1069839SBorislav Petkov /* 2853e1069839SBorislav Petkov * is PMU has exclusive counter restrictions, then 2854e1069839SBorislav Petkov * all events are subject to and must call the 2855e1069839SBorislav Petkov * put_excl_constraints() routine 2856e1069839SBorislav Petkov */ 2857e1069839SBorislav Petkov if (cpuc->excl_cntrs) 2858e1069839SBorislav Petkov intel_put_excl_constraints(cpuc, event); 2859e1069839SBorislav Petkov } 2860e1069839SBorislav Petkov 2861e1069839SBorislav Petkov static void intel_pebs_aliases_core2(struct perf_event *event) 2862e1069839SBorislav Petkov { 2863e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2864e1069839SBorislav Petkov /* 2865e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2866e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 2867e1069839SBorislav Petkov * 2868e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2869e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.ANY_P 2870e1069839SBorislav Petkov * (0x00c0), which is a PEBS capable event, to get the same 2871e1069839SBorislav Petkov * count. 2872e1069839SBorislav Petkov * 2873e1069839SBorislav Petkov * INST_RETIRED.ANY_P counts the number of cycles that retires 2874e1069839SBorislav Petkov * CNTMASK instructions. By setting CNTMASK to a value (16) 2875e1069839SBorislav Petkov * larger than the maximum number of instructions that can be 2876e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 2877e1069839SBorislav Petkov * count all cycles that retire 16 or less instructions, which 2878e1069839SBorislav Petkov * is every cycle. 2879e1069839SBorislav Petkov * 2880e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 2881e1069839SBorislav Petkov */ 2882e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 2883e1069839SBorislav Petkov 2884e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 2885e1069839SBorislav Petkov event->hw.config = alt_config; 2886e1069839SBorislav Petkov } 2887e1069839SBorislav Petkov } 2888e1069839SBorislav Petkov 2889e1069839SBorislav Petkov static void intel_pebs_aliases_snb(struct perf_event *event) 2890e1069839SBorislav Petkov { 2891e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2892e1069839SBorislav Petkov /* 2893e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2894e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 2895e1069839SBorislav Petkov * 2896e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2897e1069839SBorislav Petkov * PEBS capable. However we can use UOPS_RETIRED.ALL 2898e1069839SBorislav Petkov * (0x01c2), which is a PEBS capable event, to get the same 2899e1069839SBorislav Petkov * count. 2900e1069839SBorislav Petkov * 2901e1069839SBorislav Petkov * UOPS_RETIRED.ALL counts the number of cycles that retires 2902e1069839SBorislav Petkov * CNTMASK micro-ops. By setting CNTMASK to a value (16) 2903e1069839SBorislav Petkov * larger than the maximum number of micro-ops that can be 2904e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 2905e1069839SBorislav Petkov * count all cycles that retire 16 or less micro-ops, which 2906e1069839SBorislav Petkov * is every cycle. 2907e1069839SBorislav Petkov * 2908e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 2909e1069839SBorislav Petkov */ 2910e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 2911e1069839SBorislav Petkov 2912e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 2913e1069839SBorislav Petkov event->hw.config = alt_config; 2914e1069839SBorislav Petkov } 2915e1069839SBorislav Petkov } 2916e1069839SBorislav Petkov 2917e1069839SBorislav Petkov static void intel_pebs_aliases_precdist(struct perf_event *event) 2918e1069839SBorislav Petkov { 2919e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 2920e1069839SBorislav Petkov /* 2921e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 2922e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 2923e1069839SBorislav Petkov * 2924e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 2925e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.PREC_DIST 2926e1069839SBorislav Petkov * (0x01c0), which is a PEBS capable event, to get the same 2927e1069839SBorislav Petkov * count. 2928e1069839SBorislav Petkov * 2929e1069839SBorislav Petkov * The PREC_DIST event has special support to minimize sample 2930e1069839SBorislav Petkov * shadowing effects. One drawback is that it can be 2931e1069839SBorislav Petkov * only programmed on counter 1, but that seems like an 2932e1069839SBorislav Petkov * acceptable trade off. 2933e1069839SBorislav Petkov */ 2934e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 2935e1069839SBorislav Petkov 2936e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 2937e1069839SBorislav Petkov event->hw.config = alt_config; 2938e1069839SBorislav Petkov } 2939e1069839SBorislav Petkov } 2940e1069839SBorislav Petkov 2941e1069839SBorislav Petkov static void intel_pebs_aliases_ivb(struct perf_event *event) 2942e1069839SBorislav Petkov { 2943e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 2944e1069839SBorislav Petkov return intel_pebs_aliases_snb(event); 2945e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 2946e1069839SBorislav Petkov } 2947e1069839SBorislav Petkov 2948e1069839SBorislav Petkov static void intel_pebs_aliases_skl(struct perf_event *event) 2949e1069839SBorislav Petkov { 2950e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 2951e1069839SBorislav Petkov return intel_pebs_aliases_core2(event); 2952e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 2953e1069839SBorislav Petkov } 2954e1069839SBorislav Petkov 2955e1069839SBorislav Petkov static unsigned long intel_pmu_free_running_flags(struct perf_event *event) 2956e1069839SBorislav Petkov { 2957e1069839SBorislav Petkov unsigned long flags = x86_pmu.free_running_flags; 2958e1069839SBorislav Petkov 2959e1069839SBorislav Petkov if (event->attr.use_clockid) 2960e1069839SBorislav Petkov flags &= ~PERF_SAMPLE_TIME; 2961a47ba4d7SAndi Kleen if (!event->attr.exclude_kernel) 2962a47ba4d7SAndi Kleen flags &= ~PERF_SAMPLE_REGS_USER; 2963a47ba4d7SAndi Kleen if (event->attr.sample_regs_user & ~PEBS_REGS) 2964a47ba4d7SAndi Kleen flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 2965e1069839SBorislav Petkov return flags; 2966e1069839SBorislav Petkov } 2967e1069839SBorislav Petkov 2968e1069839SBorislav Petkov static int intel_pmu_hw_config(struct perf_event *event) 2969e1069839SBorislav Petkov { 2970e1069839SBorislav Petkov int ret = x86_pmu_hw_config(event); 2971e1069839SBorislav Petkov 2972e1069839SBorislav Petkov if (ret) 2973e1069839SBorislav Petkov return ret; 2974e1069839SBorislav Petkov 2975e1069839SBorislav Petkov if (event->attr.precise_ip) { 2976e1069839SBorislav Petkov if (!event->attr.freq) { 2977e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 2978e1069839SBorislav Petkov if (!(event->attr.sample_type & 2979e1069839SBorislav Petkov ~intel_pmu_free_running_flags(event))) 2980e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_FREERUNNING; 2981e1069839SBorislav Petkov } 2982e1069839SBorislav Petkov if (x86_pmu.pebs_aliases) 2983e1069839SBorislav Petkov x86_pmu.pebs_aliases(event); 2984e1069839SBorislav Petkov } 2985e1069839SBorislav Petkov 2986e1069839SBorislav Petkov if (needs_branch_stack(event)) { 2987e1069839SBorislav Petkov ret = intel_pmu_setup_lbr_filter(event); 2988e1069839SBorislav Petkov if (ret) 2989e1069839SBorislav Petkov return ret; 2990e1069839SBorislav Petkov 2991e1069839SBorislav Petkov /* 2992e1069839SBorislav Petkov * BTS is set up earlier in this path, so don't account twice 2993e1069839SBorislav Petkov */ 2994e1069839SBorislav Petkov if (!intel_pmu_has_bts(event)) { 2995e1069839SBorislav Petkov /* disallow lbr if conflicting events are present */ 2996e1069839SBorislav Petkov if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 2997e1069839SBorislav Petkov return -EBUSY; 2998e1069839SBorislav Petkov 2999e1069839SBorislav Petkov event->destroy = hw_perf_lbr_event_destroy; 3000e1069839SBorislav Petkov } 3001e1069839SBorislav Petkov } 3002e1069839SBorislav Petkov 3003e1069839SBorislav Petkov if (event->attr.type != PERF_TYPE_RAW) 3004e1069839SBorislav Petkov return 0; 3005e1069839SBorislav Petkov 3006e1069839SBorislav Petkov if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3007e1069839SBorislav Petkov return 0; 3008e1069839SBorislav Petkov 3009e1069839SBorislav Petkov if (x86_pmu.version < 3) 3010e1069839SBorislav Petkov return -EINVAL; 3011e1069839SBorislav Petkov 3012e1069839SBorislav Petkov if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) 3013e1069839SBorislav Petkov return -EACCES; 3014e1069839SBorislav Petkov 3015e1069839SBorislav Petkov event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3016e1069839SBorislav Petkov 3017e1069839SBorislav Petkov return 0; 3018e1069839SBorislav Petkov } 3019e1069839SBorislav Petkov 3020e1069839SBorislav Petkov struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3021e1069839SBorislav Petkov { 3022e1069839SBorislav Petkov if (x86_pmu.guest_get_msrs) 3023e1069839SBorislav Petkov return x86_pmu.guest_get_msrs(nr); 3024e1069839SBorislav Petkov *nr = 0; 3025e1069839SBorislav Petkov return NULL; 3026e1069839SBorislav Petkov } 3027e1069839SBorislav Petkov EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3028e1069839SBorislav Petkov 3029e1069839SBorislav Petkov static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3030e1069839SBorislav Petkov { 3031e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3032e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3033e1069839SBorislav Petkov 3034e1069839SBorislav Petkov arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3035e1069839SBorislav Petkov arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3036e1069839SBorislav Petkov arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3037e1069839SBorislav Petkov /* 3038e1069839SBorislav Petkov * If PMU counter has PEBS enabled it is not enough to disable counter 3039e1069839SBorislav Petkov * on a guest entry since PEBS memory write can overshoot guest entry 3040e1069839SBorislav Petkov * and corrupt guest memory. Disabling PEBS solves the problem. 3041e1069839SBorislav Petkov */ 3042e1069839SBorislav Petkov arr[1].msr = MSR_IA32_PEBS_ENABLE; 3043e1069839SBorislav Petkov arr[1].host = cpuc->pebs_enabled; 3044e1069839SBorislav Petkov arr[1].guest = 0; 3045e1069839SBorislav Petkov 3046e1069839SBorislav Petkov *nr = 2; 3047e1069839SBorislav Petkov return arr; 3048e1069839SBorislav Petkov } 3049e1069839SBorislav Petkov 3050e1069839SBorislav Petkov static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3051e1069839SBorislav Petkov { 3052e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3053e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3054e1069839SBorislav Petkov int idx; 3055e1069839SBorislav Petkov 3056e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3057e1069839SBorislav Petkov struct perf_event *event = cpuc->events[idx]; 3058e1069839SBorislav Petkov 3059e1069839SBorislav Petkov arr[idx].msr = x86_pmu_config_addr(idx); 3060e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 0; 3061e1069839SBorislav Petkov 3062e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) 3063e1069839SBorislav Petkov continue; 3064e1069839SBorislav Petkov 3065e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 3066e1069839SBorislav Petkov event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3067e1069839SBorislav Petkov 3068e1069839SBorislav Petkov if (event->attr.exclude_host) 3069e1069839SBorislav Petkov arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3070e1069839SBorislav Petkov else if (event->attr.exclude_guest) 3071e1069839SBorislav Petkov arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3072e1069839SBorislav Petkov } 3073e1069839SBorislav Petkov 3074e1069839SBorislav Petkov *nr = x86_pmu.num_counters; 3075e1069839SBorislav Petkov return arr; 3076e1069839SBorislav Petkov } 3077e1069839SBorislav Petkov 3078e1069839SBorislav Petkov static void core_pmu_enable_event(struct perf_event *event) 3079e1069839SBorislav Petkov { 3080e1069839SBorislav Petkov if (!event->attr.exclude_host) 3081e1069839SBorislav Petkov x86_pmu_enable_event(event); 3082e1069839SBorislav Petkov } 3083e1069839SBorislav Petkov 3084e1069839SBorislav Petkov static void core_pmu_enable_all(int added) 3085e1069839SBorislav Petkov { 3086e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3087e1069839SBorislav Petkov int idx; 3088e1069839SBorislav Petkov 3089e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3090e1069839SBorislav Petkov struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3091e1069839SBorislav Petkov 3092e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask) || 3093e1069839SBorislav Petkov cpuc->events[idx]->attr.exclude_host) 3094e1069839SBorislav Petkov continue; 3095e1069839SBorislav Petkov 3096e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3097e1069839SBorislav Petkov } 3098e1069839SBorislav Petkov } 3099e1069839SBorislav Petkov 3100e1069839SBorislav Petkov static int hsw_hw_config(struct perf_event *event) 3101e1069839SBorislav Petkov { 3102e1069839SBorislav Petkov int ret = intel_pmu_hw_config(event); 3103e1069839SBorislav Petkov 3104e1069839SBorislav Petkov if (ret) 3105e1069839SBorislav Petkov return ret; 3106e1069839SBorislav Petkov if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3107e1069839SBorislav Petkov return 0; 3108e1069839SBorislav Petkov event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3109e1069839SBorislav Petkov 3110e1069839SBorislav Petkov /* 3111e1069839SBorislav Petkov * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3112e1069839SBorislav Petkov * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3113e1069839SBorislav Petkov * this combination. 3114e1069839SBorislav Petkov */ 3115e1069839SBorislav Petkov if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3116e1069839SBorislav Petkov ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3117e1069839SBorislav Petkov event->attr.precise_ip > 0)) 3118e1069839SBorislav Petkov return -EOPNOTSUPP; 3119e1069839SBorislav Petkov 3120e1069839SBorislav Petkov if (event_is_checkpointed(event)) { 3121e1069839SBorislav Petkov /* 3122e1069839SBorislav Petkov * Sampling of checkpointed events can cause situations where 3123e1069839SBorislav Petkov * the CPU constantly aborts because of a overflow, which is 3124e1069839SBorislav Petkov * then checkpointed back and ignored. Forbid checkpointing 3125e1069839SBorislav Petkov * for sampling. 3126e1069839SBorislav Petkov * 3127e1069839SBorislav Petkov * But still allow a long sampling period, so that perf stat 3128e1069839SBorislav Petkov * from KVM works. 3129e1069839SBorislav Petkov */ 3130e1069839SBorislav Petkov if (event->attr.sample_period > 0 && 3131e1069839SBorislav Petkov event->attr.sample_period < 0x7fffffff) 3132e1069839SBorislav Petkov return -EOPNOTSUPP; 3133e1069839SBorislav Petkov } 3134e1069839SBorislav Petkov return 0; 3135e1069839SBorislav Petkov } 3136e1069839SBorislav Petkov 3137dd0b06b5SKan Liang static struct event_constraint counter0_constraint = 3138dd0b06b5SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3139dd0b06b5SKan Liang 3140e1069839SBorislav Petkov static struct event_constraint counter2_constraint = 3141e1069839SBorislav Petkov EVENT_CONSTRAINT(0, 0x4, 0); 3142e1069839SBorislav Petkov 3143e1069839SBorislav Petkov static struct event_constraint * 3144e1069839SBorislav Petkov hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3145e1069839SBorislav Petkov struct perf_event *event) 3146e1069839SBorislav Petkov { 3147e1069839SBorislav Petkov struct event_constraint *c; 3148e1069839SBorislav Petkov 3149e1069839SBorislav Petkov c = intel_get_event_constraints(cpuc, idx, event); 3150e1069839SBorislav Petkov 3151e1069839SBorislav Petkov /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3152e1069839SBorislav Petkov if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3153e1069839SBorislav Petkov if (c->idxmsk64 & (1U << 2)) 3154e1069839SBorislav Petkov return &counter2_constraint; 3155e1069839SBorislav Petkov return &emptyconstraint; 3156e1069839SBorislav Petkov } 3157e1069839SBorislav Petkov 3158e1069839SBorislav Petkov return c; 3159e1069839SBorislav Petkov } 3160e1069839SBorislav Petkov 3161dd0b06b5SKan Liang static struct event_constraint * 3162dd0b06b5SKan Liang glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3163dd0b06b5SKan Liang struct perf_event *event) 3164dd0b06b5SKan Liang { 3165dd0b06b5SKan Liang struct event_constraint *c; 3166dd0b06b5SKan Liang 3167dd0b06b5SKan Liang /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3168dd0b06b5SKan Liang if (event->attr.precise_ip == 3) 3169dd0b06b5SKan Liang return &counter0_constraint; 3170dd0b06b5SKan Liang 3171dd0b06b5SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 3172dd0b06b5SKan Liang 3173dd0b06b5SKan Liang return c; 3174dd0b06b5SKan Liang } 3175dd0b06b5SKan Liang 3176e1069839SBorislav Petkov /* 3177e1069839SBorislav Petkov * Broadwell: 3178e1069839SBorislav Petkov * 3179e1069839SBorislav Petkov * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3180e1069839SBorislav Petkov * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3181e1069839SBorislav Petkov * the two to enforce a minimum period of 128 (the smallest value that has bits 3182e1069839SBorislav Petkov * 0-5 cleared and >= 100). 3183e1069839SBorislav Petkov * 3184e1069839SBorislav Petkov * Because of how the code in x86_perf_event_set_period() works, the truncation 3185e1069839SBorislav Petkov * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3186e1069839SBorislav Petkov * to make up for the 'lost' events due to carrying the 'error' in period_left. 3187e1069839SBorislav Petkov * 3188e1069839SBorislav Petkov * Therefore the effective (average) period matches the requested period, 3189e1069839SBorislav Petkov * despite coarser hardware granularity. 3190e1069839SBorislav Petkov */ 3191e1069839SBorislav Petkov static unsigned bdw_limit_period(struct perf_event *event, unsigned left) 3192e1069839SBorislav Petkov { 3193e1069839SBorislav Petkov if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3194e1069839SBorislav Petkov X86_CONFIG(.event=0xc0, .umask=0x01)) { 3195e1069839SBorislav Petkov if (left < 128) 3196e1069839SBorislav Petkov left = 128; 3197e1069839SBorislav Petkov left &= ~0x3fu; 3198e1069839SBorislav Petkov } 3199e1069839SBorislav Petkov return left; 3200e1069839SBorislav Petkov } 3201e1069839SBorislav Petkov 3202e1069839SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 3203e1069839SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 3204e1069839SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 3205e1069839SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 3206e1069839SBorislav Petkov PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3207e1069839SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 3208e1069839SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3209e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx, "config:32"); 3210e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3211e1069839SBorislav Petkov 3212e1069839SBorislav Petkov static struct attribute *intel_arch_formats_attr[] = { 3213e1069839SBorislav Petkov &format_attr_event.attr, 3214e1069839SBorislav Petkov &format_attr_umask.attr, 3215e1069839SBorislav Petkov &format_attr_edge.attr, 3216e1069839SBorislav Petkov &format_attr_pc.attr, 3217e1069839SBorislav Petkov &format_attr_inv.attr, 3218e1069839SBorislav Petkov &format_attr_cmask.attr, 3219e1069839SBorislav Petkov NULL, 3220e1069839SBorislav Petkov }; 3221e1069839SBorislav Petkov 3222e1069839SBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config) 3223e1069839SBorislav Petkov { 3224e1069839SBorislav Petkov u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3225e1069839SBorislav Petkov 3226e1069839SBorislav Petkov return x86_event_sysfs_show(page, config, event); 3227e1069839SBorislav Petkov } 3228e1069839SBorislav Petkov 3229e1069839SBorislav Petkov struct intel_shared_regs *allocate_shared_regs(int cpu) 3230e1069839SBorislav Petkov { 3231e1069839SBorislav Petkov struct intel_shared_regs *regs; 3232e1069839SBorislav Petkov int i; 3233e1069839SBorislav Petkov 3234e1069839SBorislav Petkov regs = kzalloc_node(sizeof(struct intel_shared_regs), 3235e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3236e1069839SBorislav Petkov if (regs) { 3237e1069839SBorislav Petkov /* 3238e1069839SBorislav Petkov * initialize the locks to keep lockdep happy 3239e1069839SBorislav Petkov */ 3240e1069839SBorislav Petkov for (i = 0; i < EXTRA_REG_MAX; i++) 3241e1069839SBorislav Petkov raw_spin_lock_init(®s->regs[i].lock); 3242e1069839SBorislav Petkov 3243e1069839SBorislav Petkov regs->core_id = -1; 3244e1069839SBorislav Petkov } 3245e1069839SBorislav Petkov return regs; 3246e1069839SBorislav Petkov } 3247e1069839SBorislav Petkov 3248e1069839SBorislav Petkov static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3249e1069839SBorislav Petkov { 3250e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3251e1069839SBorislav Petkov 3252e1069839SBorislav Petkov c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3253e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3254e1069839SBorislav Petkov if (c) { 3255e1069839SBorislav Petkov raw_spin_lock_init(&c->lock); 3256e1069839SBorislav Petkov c->core_id = -1; 3257e1069839SBorislav Petkov } 3258e1069839SBorislav Petkov return c; 3259e1069839SBorislav Petkov } 3260e1069839SBorislav Petkov 3261e1069839SBorislav Petkov static int intel_pmu_cpu_prepare(int cpu) 3262e1069839SBorislav Petkov { 3263e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3264e1069839SBorislav Petkov 3265e1069839SBorislav Petkov if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 3266e1069839SBorislav Petkov cpuc->shared_regs = allocate_shared_regs(cpu); 3267e1069839SBorislav Petkov if (!cpuc->shared_regs) 3268e1069839SBorislav Petkov goto err; 3269e1069839SBorislav Petkov } 3270e1069839SBorislav Petkov 3271e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3272e1069839SBorislav Petkov size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 3273e1069839SBorislav Petkov 3274e1069839SBorislav Petkov cpuc->constraint_list = kzalloc(sz, GFP_KERNEL); 3275e1069839SBorislav Petkov if (!cpuc->constraint_list) 3276e1069839SBorislav Petkov goto err_shared_regs; 3277e1069839SBorislav Petkov 3278e1069839SBorislav Petkov cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 3279e1069839SBorislav Petkov if (!cpuc->excl_cntrs) 3280e1069839SBorislav Petkov goto err_constraint_list; 3281e1069839SBorislav Petkov 3282e1069839SBorislav Petkov cpuc->excl_thread_id = 0; 3283e1069839SBorislav Petkov } 3284e1069839SBorislav Petkov 328595ca792cSThomas Gleixner return 0; 3286e1069839SBorislav Petkov 3287e1069839SBorislav Petkov err_constraint_list: 3288e1069839SBorislav Petkov kfree(cpuc->constraint_list); 3289e1069839SBorislav Petkov cpuc->constraint_list = NULL; 3290e1069839SBorislav Petkov 3291e1069839SBorislav Petkov err_shared_regs: 3292e1069839SBorislav Petkov kfree(cpuc->shared_regs); 3293e1069839SBorislav Petkov cpuc->shared_regs = NULL; 3294e1069839SBorislav Petkov 3295e1069839SBorislav Petkov err: 329695ca792cSThomas Gleixner return -ENOMEM; 3297e1069839SBorislav Petkov } 3298e1069839SBorislav Petkov 32996089327fSKan Liang static void flip_smm_bit(void *data) 33006089327fSKan Liang { 33016089327fSKan Liang unsigned long set = *(unsigned long *)data; 33026089327fSKan Liang 33036089327fSKan Liang if (set > 0) { 33046089327fSKan Liang msr_set_bit(MSR_IA32_DEBUGCTLMSR, 33056089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 33066089327fSKan Liang } else { 33076089327fSKan Liang msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 33086089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 33096089327fSKan Liang } 33106089327fSKan Liang } 33116089327fSKan Liang 3312e1069839SBorislav Petkov static void intel_pmu_cpu_starting(int cpu) 3313e1069839SBorislav Petkov { 3314e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3315e1069839SBorislav Petkov int core_id = topology_core_id(cpu); 3316e1069839SBorislav Petkov int i; 3317e1069839SBorislav Petkov 3318e1069839SBorislav Petkov init_debug_store_on_cpu(cpu); 3319e1069839SBorislav Petkov /* 3320e1069839SBorislav Petkov * Deal with CPUs that don't clear their LBRs on power-up. 3321e1069839SBorislav Petkov */ 3322e1069839SBorislav Petkov intel_pmu_lbr_reset(); 3323e1069839SBorislav Petkov 3324e1069839SBorislav Petkov cpuc->lbr_sel = NULL; 3325e1069839SBorislav Petkov 33266089327fSKan Liang flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 33276089327fSKan Liang 3328e1069839SBorislav Petkov if (!cpuc->shared_regs) 3329e1069839SBorislav Petkov return; 3330e1069839SBorislav Petkov 3331e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 3332e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3333e1069839SBorislav Petkov struct intel_shared_regs *pc; 3334e1069839SBorislav Petkov 3335e1069839SBorislav Petkov pc = per_cpu(cpu_hw_events, i).shared_regs; 3336e1069839SBorislav Petkov if (pc && pc->core_id == core_id) { 3337e1069839SBorislav Petkov cpuc->kfree_on_online[0] = cpuc->shared_regs; 3338e1069839SBorislav Petkov cpuc->shared_regs = pc; 3339e1069839SBorislav Petkov break; 3340e1069839SBorislav Petkov } 3341e1069839SBorislav Petkov } 3342e1069839SBorislav Petkov cpuc->shared_regs->core_id = core_id; 3343e1069839SBorislav Petkov cpuc->shared_regs->refcnt++; 3344e1069839SBorislav Petkov } 3345e1069839SBorislav Petkov 3346e1069839SBorislav Petkov if (x86_pmu.lbr_sel_map) 3347e1069839SBorislav Petkov cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 3348e1069839SBorislav Petkov 3349e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3350e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 33514e71de79SZhou Chengming struct cpu_hw_events *sibling; 3352e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3353e1069839SBorislav Petkov 33544e71de79SZhou Chengming sibling = &per_cpu(cpu_hw_events, i); 33554e71de79SZhou Chengming c = sibling->excl_cntrs; 3356e1069839SBorislav Petkov if (c && c->core_id == core_id) { 3357e1069839SBorislav Petkov cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 3358e1069839SBorislav Petkov cpuc->excl_cntrs = c; 33594e71de79SZhou Chengming if (!sibling->excl_thread_id) 3360e1069839SBorislav Petkov cpuc->excl_thread_id = 1; 3361e1069839SBorislav Petkov break; 3362e1069839SBorislav Petkov } 3363e1069839SBorislav Petkov } 3364e1069839SBorislav Petkov cpuc->excl_cntrs->core_id = core_id; 3365e1069839SBorislav Petkov cpuc->excl_cntrs->refcnt++; 3366e1069839SBorislav Petkov } 3367e1069839SBorislav Petkov } 3368e1069839SBorislav Petkov 3369e1069839SBorislav Petkov static void free_excl_cntrs(int cpu) 3370e1069839SBorislav Petkov { 3371e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3372e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3373e1069839SBorislav Petkov 3374e1069839SBorislav Petkov c = cpuc->excl_cntrs; 3375e1069839SBorislav Petkov if (c) { 3376e1069839SBorislav Petkov if (c->core_id == -1 || --c->refcnt == 0) 3377e1069839SBorislav Petkov kfree(c); 3378e1069839SBorislav Petkov cpuc->excl_cntrs = NULL; 3379e1069839SBorislav Petkov kfree(cpuc->constraint_list); 3380e1069839SBorislav Petkov cpuc->constraint_list = NULL; 3381e1069839SBorislav Petkov } 3382e1069839SBorislav Petkov } 3383e1069839SBorislav Petkov 3384e1069839SBorislav Petkov static void intel_pmu_cpu_dying(int cpu) 3385e1069839SBorislav Petkov { 3386e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3387e1069839SBorislav Petkov struct intel_shared_regs *pc; 3388e1069839SBorislav Petkov 3389e1069839SBorislav Petkov pc = cpuc->shared_regs; 3390e1069839SBorislav Petkov if (pc) { 3391e1069839SBorislav Petkov if (pc->core_id == -1 || --pc->refcnt == 0) 3392e1069839SBorislav Petkov kfree(pc); 3393e1069839SBorislav Petkov cpuc->shared_regs = NULL; 3394e1069839SBorislav Petkov } 3395e1069839SBorislav Petkov 3396e1069839SBorislav Petkov free_excl_cntrs(cpu); 3397e1069839SBorislav Petkov 3398e1069839SBorislav Petkov fini_debug_store_on_cpu(cpu); 3399e1069839SBorislav Petkov } 3400e1069839SBorislav Petkov 3401e1069839SBorislav Petkov static void intel_pmu_sched_task(struct perf_event_context *ctx, 3402e1069839SBorislav Petkov bool sched_in) 3403e1069839SBorislav Petkov { 3404e1069839SBorislav Petkov intel_pmu_pebs_sched_task(ctx, sched_in); 3405e1069839SBorislav Petkov intel_pmu_lbr_sched_task(ctx, sched_in); 3406e1069839SBorislav Petkov } 3407e1069839SBorislav Petkov 3408e1069839SBorislav Petkov PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 3409e1069839SBorislav Petkov 3410e1069839SBorislav Petkov PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 3411e1069839SBorislav Petkov 3412e1069839SBorislav Petkov PMU_FORMAT_ATTR(frontend, "config1:0-23"); 3413e1069839SBorislav Petkov 3414e1069839SBorislav Petkov static struct attribute *intel_arch3_formats_attr[] = { 3415e1069839SBorislav Petkov &format_attr_event.attr, 3416e1069839SBorislav Petkov &format_attr_umask.attr, 3417e1069839SBorislav Petkov &format_attr_edge.attr, 3418e1069839SBorislav Petkov &format_attr_pc.attr, 3419e1069839SBorislav Petkov &format_attr_any.attr, 3420e1069839SBorislav Petkov &format_attr_inv.attr, 3421e1069839SBorislav Petkov &format_attr_cmask.attr, 3422a5df70c3SAndi Kleen NULL, 3423a5df70c3SAndi Kleen }; 3424a5df70c3SAndi Kleen 3425a5df70c3SAndi Kleen static struct attribute *hsw_format_attr[] = { 3426e1069839SBorislav Petkov &format_attr_in_tx.attr, 3427e1069839SBorislav Petkov &format_attr_in_tx_cp.attr, 3428a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3429a5df70c3SAndi Kleen &format_attr_ldlat.attr, 3430a5df70c3SAndi Kleen NULL 3431a5df70c3SAndi Kleen }; 3432e1069839SBorislav Petkov 3433a5df70c3SAndi Kleen static struct attribute *nhm_format_attr[] = { 3434a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3435a5df70c3SAndi Kleen &format_attr_ldlat.attr, 3436a5df70c3SAndi Kleen NULL 3437a5df70c3SAndi Kleen }; 3438a5df70c3SAndi Kleen 3439a5df70c3SAndi Kleen static struct attribute *slm_format_attr[] = { 3440a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3441a5df70c3SAndi Kleen NULL 3442e1069839SBorislav Petkov }; 3443e1069839SBorislav Petkov 3444e1069839SBorislav Petkov static struct attribute *skl_format_attr[] = { 3445e1069839SBorislav Petkov &format_attr_frontend.attr, 3446e1069839SBorislav Petkov NULL, 3447e1069839SBorislav Petkov }; 3448e1069839SBorislav Petkov 3449e1069839SBorislav Petkov static __initconst const struct x86_pmu core_pmu = { 3450e1069839SBorislav Petkov .name = "core", 3451e1069839SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 3452e1069839SBorislav Petkov .disable_all = x86_pmu_disable_all, 3453e1069839SBorislav Petkov .enable_all = core_pmu_enable_all, 3454e1069839SBorislav Petkov .enable = core_pmu_enable_event, 3455e1069839SBorislav Petkov .disable = x86_pmu_disable_event, 3456e1069839SBorislav Petkov .hw_config = x86_pmu_hw_config, 3457e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 3458e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3459e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3460e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 3461e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3462e1069839SBorislav Petkov .apic = 1, 3463e1069839SBorislav Petkov .free_running_flags = PEBS_FREERUNNING_FLAGS, 3464e1069839SBorislav Petkov 3465e1069839SBorislav Petkov /* 3466e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32-bit width, 3467e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 3468e1069839SBorislav Petkov * the generic event period: 3469e1069839SBorislav Petkov */ 3470e1069839SBorislav Petkov .max_period = (1ULL<<31) - 1, 3471e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 3472e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 3473e1069839SBorislav Petkov .event_constraints = intel_core_event_constraints, 3474e1069839SBorislav Petkov .guest_get_msrs = core_guest_get_msrs, 3475e1069839SBorislav Petkov .format_attrs = intel_arch_formats_attr, 3476e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 3477e1069839SBorislav Petkov 3478e1069839SBorislav Petkov /* 3479e1069839SBorislav Petkov * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 3480e1069839SBorislav Petkov * together with PMU version 1 and thus be using core_pmu with 3481e1069839SBorislav Petkov * shared_regs. We need following callbacks here to allocate 3482e1069839SBorislav Petkov * it properly. 3483e1069839SBorislav Petkov */ 3484e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 3485e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 3486e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 3487e1069839SBorislav Petkov }; 3488e1069839SBorislav Petkov 3489e1069839SBorislav Petkov static __initconst const struct x86_pmu intel_pmu = { 3490e1069839SBorislav Petkov .name = "Intel", 3491e1069839SBorislav Petkov .handle_irq = intel_pmu_handle_irq, 3492e1069839SBorislav Petkov .disable_all = intel_pmu_disable_all, 3493e1069839SBorislav Petkov .enable_all = intel_pmu_enable_all, 3494e1069839SBorislav Petkov .enable = intel_pmu_enable_event, 3495e1069839SBorislav Petkov .disable = intel_pmu_disable_event, 349668f7082fSPeter Zijlstra .add = intel_pmu_add_event, 349768f7082fSPeter Zijlstra .del = intel_pmu_del_event, 3498e1069839SBorislav Petkov .hw_config = intel_pmu_hw_config, 3499e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 3500e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3501e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3502e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 3503e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3504e1069839SBorislav Petkov .apic = 1, 3505e1069839SBorislav Petkov .free_running_flags = PEBS_FREERUNNING_FLAGS, 3506e1069839SBorislav Petkov /* 3507e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32 bit width, 3508e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 3509e1069839SBorislav Petkov * the generic event period: 3510e1069839SBorislav Petkov */ 3511e1069839SBorislav Petkov .max_period = (1ULL << 31) - 1, 3512e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 3513e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 3514e1069839SBorislav Petkov .pebs_aliases = intel_pebs_aliases_core2, 3515e1069839SBorislav Petkov 3516e1069839SBorislav Petkov .format_attrs = intel_arch3_formats_attr, 3517e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 3518e1069839SBorislav Petkov 3519e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 3520e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 3521e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 3522e1069839SBorislav Petkov .guest_get_msrs = intel_guest_get_msrs, 3523e1069839SBorislav Petkov .sched_task = intel_pmu_sched_task, 3524e1069839SBorislav Petkov }; 3525e1069839SBorislav Petkov 3526e1069839SBorislav Petkov static __init void intel_clovertown_quirk(void) 3527e1069839SBorislav Petkov { 3528e1069839SBorislav Petkov /* 3529e1069839SBorislav Petkov * PEBS is unreliable due to: 3530e1069839SBorislav Petkov * 3531e1069839SBorislav Petkov * AJ67 - PEBS may experience CPL leaks 3532e1069839SBorislav Petkov * AJ68 - PEBS PMI may be delayed by one event 3533e1069839SBorislav Petkov * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 3534e1069839SBorislav Petkov * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 3535e1069839SBorislav Petkov * 3536e1069839SBorislav Petkov * AJ67 could be worked around by restricting the OS/USR flags. 3537e1069839SBorislav Petkov * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 3538e1069839SBorislav Petkov * 3539e1069839SBorislav Petkov * AJ106 could possibly be worked around by not allowing LBR 3540e1069839SBorislav Petkov * usage from PEBS, including the fixup. 3541e1069839SBorislav Petkov * AJ68 could possibly be worked around by always programming 3542e1069839SBorislav Petkov * a pebs_event_reset[0] value and coping with the lost events. 3543e1069839SBorislav Petkov * 3544e1069839SBorislav Petkov * But taken together it might just make sense to not enable PEBS on 3545e1069839SBorislav Petkov * these chips. 3546e1069839SBorislav Petkov */ 3547e1069839SBorislav Petkov pr_warn("PEBS disabled due to CPU errata\n"); 3548e1069839SBorislav Petkov x86_pmu.pebs = 0; 3549e1069839SBorislav Petkov x86_pmu.pebs_constraints = NULL; 3550e1069839SBorislav Petkov } 3551e1069839SBorislav Petkov 3552e1069839SBorislav Petkov static int intel_snb_pebs_broken(int cpu) 3553e1069839SBorislav Petkov { 3554e1069839SBorislav Petkov u32 rev = UINT_MAX; /* default to broken for unknown models */ 3555e1069839SBorislav Petkov 3556e1069839SBorislav Petkov switch (cpu_data(cpu).x86_model) { 3557ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 3558e1069839SBorislav Petkov rev = 0x28; 3559e1069839SBorislav Petkov break; 3560e1069839SBorislav Petkov 3561ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 3562e1069839SBorislav Petkov switch (cpu_data(cpu).x86_mask) { 3563e1069839SBorislav Petkov case 6: rev = 0x618; break; 3564e1069839SBorislav Petkov case 7: rev = 0x70c; break; 3565e1069839SBorislav Petkov } 3566e1069839SBorislav Petkov } 3567e1069839SBorislav Petkov 3568e1069839SBorislav Petkov return (cpu_data(cpu).microcode < rev); 3569e1069839SBorislav Petkov } 3570e1069839SBorislav Petkov 3571e1069839SBorislav Petkov static void intel_snb_check_microcode(void) 3572e1069839SBorislav Petkov { 3573e1069839SBorislav Petkov int pebs_broken = 0; 3574e1069839SBorislav Petkov int cpu; 3575e1069839SBorislav Petkov 3576e1069839SBorislav Petkov for_each_online_cpu(cpu) { 3577e1069839SBorislav Petkov if ((pebs_broken = intel_snb_pebs_broken(cpu))) 3578e1069839SBorislav Petkov break; 3579e1069839SBorislav Petkov } 3580e1069839SBorislav Petkov 3581e1069839SBorislav Petkov if (pebs_broken == x86_pmu.pebs_broken) 3582e1069839SBorislav Petkov return; 3583e1069839SBorislav Petkov 3584e1069839SBorislav Petkov /* 3585e1069839SBorislav Petkov * Serialized by the microcode lock.. 3586e1069839SBorislav Petkov */ 3587e1069839SBorislav Petkov if (x86_pmu.pebs_broken) { 3588e1069839SBorislav Petkov pr_info("PEBS enabled due to microcode update\n"); 3589e1069839SBorislav Petkov x86_pmu.pebs_broken = 0; 3590e1069839SBorislav Petkov } else { 3591e1069839SBorislav Petkov pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 3592e1069839SBorislav Petkov x86_pmu.pebs_broken = 1; 3593e1069839SBorislav Petkov } 3594e1069839SBorislav Petkov } 3595e1069839SBorislav Petkov 359619fc9dddSDavid Carrillo-Cisneros static bool is_lbr_from(unsigned long msr) 359719fc9dddSDavid Carrillo-Cisneros { 359819fc9dddSDavid Carrillo-Cisneros unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 359919fc9dddSDavid Carrillo-Cisneros 360019fc9dddSDavid Carrillo-Cisneros return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 360119fc9dddSDavid Carrillo-Cisneros } 360219fc9dddSDavid Carrillo-Cisneros 3603e1069839SBorislav Petkov /* 3604e1069839SBorislav Petkov * Under certain circumstances, access certain MSR may cause #GP. 3605e1069839SBorislav Petkov * The function tests if the input MSR can be safely accessed. 3606e1069839SBorislav Petkov */ 3607e1069839SBorislav Petkov static bool check_msr(unsigned long msr, u64 mask) 3608e1069839SBorislav Petkov { 3609e1069839SBorislav Petkov u64 val_old, val_new, val_tmp; 3610e1069839SBorislav Petkov 3611e1069839SBorislav Petkov /* 3612e1069839SBorislav Petkov * Read the current value, change it and read it back to see if it 3613e1069839SBorislav Petkov * matches, this is needed to detect certain hardware emulators 3614e1069839SBorislav Petkov * (qemu/kvm) that don't trap on the MSR access and always return 0s. 3615e1069839SBorislav Petkov */ 3616e1069839SBorislav Petkov if (rdmsrl_safe(msr, &val_old)) 3617e1069839SBorislav Petkov return false; 3618e1069839SBorislav Petkov 3619e1069839SBorislav Petkov /* 3620e1069839SBorislav Petkov * Only change the bits which can be updated by wrmsrl. 3621e1069839SBorislav Petkov */ 3622e1069839SBorislav Petkov val_tmp = val_old ^ mask; 362319fc9dddSDavid Carrillo-Cisneros 362419fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 362519fc9dddSDavid Carrillo-Cisneros val_tmp = lbr_from_signext_quirk_wr(val_tmp); 362619fc9dddSDavid Carrillo-Cisneros 3627e1069839SBorislav Petkov if (wrmsrl_safe(msr, val_tmp) || 3628e1069839SBorislav Petkov rdmsrl_safe(msr, &val_new)) 3629e1069839SBorislav Petkov return false; 3630e1069839SBorislav Petkov 363119fc9dddSDavid Carrillo-Cisneros /* 363219fc9dddSDavid Carrillo-Cisneros * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 363319fc9dddSDavid Carrillo-Cisneros * should equal rdmsrl()'s even with the quirk. 363419fc9dddSDavid Carrillo-Cisneros */ 3635e1069839SBorislav Petkov if (val_new != val_tmp) 3636e1069839SBorislav Petkov return false; 3637e1069839SBorislav Petkov 363819fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 363919fc9dddSDavid Carrillo-Cisneros val_old = lbr_from_signext_quirk_wr(val_old); 364019fc9dddSDavid Carrillo-Cisneros 3641e1069839SBorislav Petkov /* Here it's sure that the MSR can be safely accessed. 3642e1069839SBorislav Petkov * Restore the old value and return. 3643e1069839SBorislav Petkov */ 3644e1069839SBorislav Petkov wrmsrl(msr, val_old); 3645e1069839SBorislav Petkov 3646e1069839SBorislav Petkov return true; 3647e1069839SBorislav Petkov } 3648e1069839SBorislav Petkov 3649e1069839SBorislav Petkov static __init void intel_sandybridge_quirk(void) 3650e1069839SBorislav Petkov { 3651e1069839SBorislav Petkov x86_pmu.check_microcode = intel_snb_check_microcode; 36521ba143a5SSebastian Andrzej Siewior cpus_read_lock(); 3653e1069839SBorislav Petkov intel_snb_check_microcode(); 36541ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 3655e1069839SBorislav Petkov } 3656e1069839SBorislav Petkov 3657e1069839SBorislav Petkov static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 3658e1069839SBorislav Petkov { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 3659e1069839SBorislav Petkov { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 3660e1069839SBorislav Petkov { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 3661e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 3662e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 3663e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 3664e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 3665e1069839SBorislav Petkov }; 3666e1069839SBorislav Petkov 3667e1069839SBorislav Petkov static __init void intel_arch_events_quirk(void) 3668e1069839SBorislav Petkov { 3669e1069839SBorislav Petkov int bit; 3670e1069839SBorislav Petkov 3671e1069839SBorislav Petkov /* disable event that reported as not presend by cpuid */ 3672e1069839SBorislav Petkov for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 3673e1069839SBorislav Petkov intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 3674e1069839SBorislav Petkov pr_warn("CPUID marked event: \'%s\' unavailable\n", 3675e1069839SBorislav Petkov intel_arch_events_map[bit].name); 3676e1069839SBorislav Petkov } 3677e1069839SBorislav Petkov } 3678e1069839SBorislav Petkov 3679e1069839SBorislav Petkov static __init void intel_nehalem_quirk(void) 3680e1069839SBorislav Petkov { 3681e1069839SBorislav Petkov union cpuid10_ebx ebx; 3682e1069839SBorislav Petkov 3683e1069839SBorislav Petkov ebx.full = x86_pmu.events_maskl; 3684e1069839SBorislav Petkov if (ebx.split.no_branch_misses_retired) { 3685e1069839SBorislav Petkov /* 3686e1069839SBorislav Petkov * Erratum AAJ80 detected, we work it around by using 3687e1069839SBorislav Petkov * the BR_MISP_EXEC.ANY event. This will over-count 3688e1069839SBorislav Petkov * branch-misses, but it's still much better than the 3689e1069839SBorislav Petkov * architectural event which is often completely bogus: 3690e1069839SBorislav Petkov */ 3691e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 3692e1069839SBorislav Petkov ebx.split.no_branch_misses_retired = 0; 3693e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 3694e1069839SBorislav Petkov pr_info("CPU erratum AAJ80 worked around\n"); 3695e1069839SBorislav Petkov } 3696e1069839SBorislav Petkov } 3697e1069839SBorislav Petkov 3698e1069839SBorislav Petkov /* 3699e1069839SBorislav Petkov * enable software workaround for errata: 3700e1069839SBorislav Petkov * SNB: BJ122 3701e1069839SBorislav Petkov * IVB: BV98 3702e1069839SBorislav Petkov * HSW: HSD29 3703e1069839SBorislav Petkov * 3704e1069839SBorislav Petkov * Only needed when HT is enabled. However detecting 3705e1069839SBorislav Petkov * if HT is enabled is difficult (model specific). So instead, 3706e1069839SBorislav Petkov * we enable the workaround in the early boot, and verify if 3707e1069839SBorislav Petkov * it is needed in a later initcall phase once we have valid 3708e1069839SBorislav Petkov * topology information to check if HT is actually enabled 3709e1069839SBorislav Petkov */ 3710e1069839SBorislav Petkov static __init void intel_ht_bug(void) 3711e1069839SBorislav Petkov { 3712e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 3713e1069839SBorislav Petkov 3714e1069839SBorislav Petkov x86_pmu.start_scheduling = intel_start_scheduling; 3715e1069839SBorislav Petkov x86_pmu.commit_scheduling = intel_commit_scheduling; 3716e1069839SBorislav Petkov x86_pmu.stop_scheduling = intel_stop_scheduling; 3717e1069839SBorislav Petkov } 3718e1069839SBorislav Petkov 3719e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 3720e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 3721e1069839SBorislav Petkov 3722e1069839SBorislav Petkov /* Haswell special events */ 3723e1069839SBorislav Petkov EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 3724e1069839SBorislav Petkov EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 3725e1069839SBorislav Petkov EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 3726e1069839SBorislav Petkov EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 3727e1069839SBorislav Petkov EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 3728e1069839SBorislav Petkov EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 3729e1069839SBorislav Petkov EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 3730e1069839SBorislav Petkov EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 3731e1069839SBorislav Petkov EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 3732e1069839SBorislav Petkov EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 3733e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 3734e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 3735e1069839SBorislav Petkov 3736e1069839SBorislav Petkov static struct attribute *hsw_events_attrs[] = { 373758ba4d5aSAndi Kleen EVENT_PTR(mem_ld_hsw), 373858ba4d5aSAndi Kleen EVENT_PTR(mem_st_hsw), 373958ba4d5aSAndi Kleen EVENT_PTR(td_slots_issued), 374058ba4d5aSAndi Kleen EVENT_PTR(td_slots_retired), 374158ba4d5aSAndi Kleen EVENT_PTR(td_fetch_bubbles), 374258ba4d5aSAndi Kleen EVENT_PTR(td_total_slots), 374358ba4d5aSAndi Kleen EVENT_PTR(td_total_slots_scale), 374458ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles), 374558ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 374658ba4d5aSAndi Kleen NULL 374758ba4d5aSAndi Kleen }; 374858ba4d5aSAndi Kleen 374958ba4d5aSAndi Kleen static struct attribute *hsw_tsx_events_attrs[] = { 3750e1069839SBorislav Petkov EVENT_PTR(tx_start), 3751e1069839SBorislav Petkov EVENT_PTR(tx_commit), 3752e1069839SBorislav Petkov EVENT_PTR(tx_abort), 3753e1069839SBorislav Petkov EVENT_PTR(tx_capacity), 3754e1069839SBorislav Petkov EVENT_PTR(tx_conflict), 3755e1069839SBorislav Petkov EVENT_PTR(el_start), 3756e1069839SBorislav Petkov EVENT_PTR(el_commit), 3757e1069839SBorislav Petkov EVENT_PTR(el_abort), 3758e1069839SBorislav Petkov EVENT_PTR(el_capacity), 3759e1069839SBorislav Petkov EVENT_PTR(el_conflict), 3760e1069839SBorislav Petkov EVENT_PTR(cycles_t), 3761e1069839SBorislav Petkov EVENT_PTR(cycles_ct), 3762e1069839SBorislav Petkov NULL 3763e1069839SBorislav Petkov }; 3764e1069839SBorislav Petkov 376558ba4d5aSAndi Kleen static __init struct attribute **get_hsw_events_attrs(void) 376658ba4d5aSAndi Kleen { 376758ba4d5aSAndi Kleen return boot_cpu_has(X86_FEATURE_RTM) ? 376858ba4d5aSAndi Kleen merge_attr(hsw_events_attrs, hsw_tsx_events_attrs) : 376958ba4d5aSAndi Kleen hsw_events_attrs; 377058ba4d5aSAndi Kleen } 377158ba4d5aSAndi Kleen 37726089327fSKan Liang static ssize_t freeze_on_smi_show(struct device *cdev, 37736089327fSKan Liang struct device_attribute *attr, 37746089327fSKan Liang char *buf) 37756089327fSKan Liang { 37766089327fSKan Liang return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 37776089327fSKan Liang } 37786089327fSKan Liang 37796089327fSKan Liang static DEFINE_MUTEX(freeze_on_smi_mutex); 37806089327fSKan Liang 37816089327fSKan Liang static ssize_t freeze_on_smi_store(struct device *cdev, 37826089327fSKan Liang struct device_attribute *attr, 37836089327fSKan Liang const char *buf, size_t count) 37846089327fSKan Liang { 37856089327fSKan Liang unsigned long val; 37866089327fSKan Liang ssize_t ret; 37876089327fSKan Liang 37886089327fSKan Liang ret = kstrtoul(buf, 0, &val); 37896089327fSKan Liang if (ret) 37906089327fSKan Liang return ret; 37916089327fSKan Liang 37926089327fSKan Liang if (val > 1) 37936089327fSKan Liang return -EINVAL; 37946089327fSKan Liang 37956089327fSKan Liang mutex_lock(&freeze_on_smi_mutex); 37966089327fSKan Liang 37976089327fSKan Liang if (x86_pmu.attr_freeze_on_smi == val) 37986089327fSKan Liang goto done; 37996089327fSKan Liang 38006089327fSKan Liang x86_pmu.attr_freeze_on_smi = val; 38016089327fSKan Liang 38026089327fSKan Liang get_online_cpus(); 38036089327fSKan Liang on_each_cpu(flip_smm_bit, &val, 1); 38046089327fSKan Liang put_online_cpus(); 38056089327fSKan Liang done: 38066089327fSKan Liang mutex_unlock(&freeze_on_smi_mutex); 38076089327fSKan Liang 38086089327fSKan Liang return count; 38096089327fSKan Liang } 38106089327fSKan Liang 38116089327fSKan Liang static DEVICE_ATTR_RW(freeze_on_smi); 38126089327fSKan Liang 3813b00233b5SAndi Kleen static ssize_t branches_show(struct device *cdev, 3814b00233b5SAndi Kleen struct device_attribute *attr, 3815b00233b5SAndi Kleen char *buf) 3816b00233b5SAndi Kleen { 3817b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 3818b00233b5SAndi Kleen } 3819b00233b5SAndi Kleen 3820b00233b5SAndi Kleen static DEVICE_ATTR_RO(branches); 3821b00233b5SAndi Kleen 3822b00233b5SAndi Kleen static struct attribute *lbr_attrs[] = { 3823b00233b5SAndi Kleen &dev_attr_branches.attr, 3824b00233b5SAndi Kleen NULL 3825b00233b5SAndi Kleen }; 3826b00233b5SAndi Kleen 3827b00233b5SAndi Kleen static char pmu_name_str[30]; 3828b00233b5SAndi Kleen 3829b00233b5SAndi Kleen static ssize_t pmu_name_show(struct device *cdev, 3830b00233b5SAndi Kleen struct device_attribute *attr, 3831b00233b5SAndi Kleen char *buf) 3832b00233b5SAndi Kleen { 3833b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 3834b00233b5SAndi Kleen } 3835b00233b5SAndi Kleen 3836b00233b5SAndi Kleen static DEVICE_ATTR_RO(pmu_name); 3837b00233b5SAndi Kleen 3838b00233b5SAndi Kleen static struct attribute *intel_pmu_caps_attrs[] = { 3839b00233b5SAndi Kleen &dev_attr_pmu_name.attr, 3840b00233b5SAndi Kleen NULL 3841b00233b5SAndi Kleen }; 3842b00233b5SAndi Kleen 38436089327fSKan Liang static struct attribute *intel_pmu_attrs[] = { 38446089327fSKan Liang &dev_attr_freeze_on_smi.attr, 38456089327fSKan Liang NULL, 38466089327fSKan Liang }; 38476089327fSKan Liang 3848e1069839SBorislav Petkov __init int intel_pmu_init(void) 3849e1069839SBorislav Petkov { 38507ad1437dSThomas Gleixner struct attribute **extra_attr = NULL; 38517ad1437dSThomas Gleixner struct attribute **to_free = NULL; 3852e1069839SBorislav Petkov union cpuid10_edx edx; 3853e1069839SBorislav Petkov union cpuid10_eax eax; 3854e1069839SBorislav Petkov union cpuid10_ebx ebx; 3855e1069839SBorislav Petkov struct event_constraint *c; 3856e1069839SBorislav Petkov unsigned int unused; 3857e1069839SBorislav Petkov struct extra_reg *er; 3858e1069839SBorislav Petkov int version, i; 3859b00233b5SAndi Kleen char *name; 3860e1069839SBorislav Petkov 3861e1069839SBorislav Petkov if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 3862e1069839SBorislav Petkov switch (boot_cpu_data.x86) { 3863e1069839SBorislav Petkov case 0x6: 3864e1069839SBorislav Petkov return p6_pmu_init(); 3865e1069839SBorislav Petkov case 0xb: 3866e1069839SBorislav Petkov return knc_pmu_init(); 3867e1069839SBorislav Petkov case 0xf: 3868e1069839SBorislav Petkov return p4_pmu_init(); 3869e1069839SBorislav Petkov } 3870e1069839SBorislav Petkov return -ENODEV; 3871e1069839SBorislav Petkov } 3872e1069839SBorislav Petkov 3873e1069839SBorislav Petkov /* 3874e1069839SBorislav Petkov * Check whether the Architectural PerfMon supports 3875e1069839SBorislav Petkov * Branch Misses Retired hw_event or not. 3876e1069839SBorislav Petkov */ 3877e1069839SBorislav Petkov cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 3878e1069839SBorislav Petkov if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 3879e1069839SBorislav Petkov return -ENODEV; 3880e1069839SBorislav Petkov 3881e1069839SBorislav Petkov version = eax.split.version_id; 3882e1069839SBorislav Petkov if (version < 2) 3883e1069839SBorislav Petkov x86_pmu = core_pmu; 3884e1069839SBorislav Petkov else 3885e1069839SBorislav Petkov x86_pmu = intel_pmu; 3886e1069839SBorislav Petkov 3887e1069839SBorislav Petkov x86_pmu.version = version; 3888e1069839SBorislav Petkov x86_pmu.num_counters = eax.split.num_counters; 3889e1069839SBorislav Petkov x86_pmu.cntval_bits = eax.split.bit_width; 3890e1069839SBorislav Petkov x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 3891e1069839SBorislav Petkov 3892e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 3893e1069839SBorislav Petkov x86_pmu.events_mask_len = eax.split.mask_length; 3894e1069839SBorislav Petkov 3895e1069839SBorislav Petkov x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 3896e1069839SBorislav Petkov 38976089327fSKan Liang 38986089327fSKan Liang x86_pmu.attrs = intel_pmu_attrs; 3899e1069839SBorislav Petkov /* 3900e1069839SBorislav Petkov * Quirk: v2 perfmon does not report fixed-purpose events, so 3901f92b7604SImre Palik * assume at least 3 events, when not running in a hypervisor: 3902e1069839SBorislav Petkov */ 3903f92b7604SImre Palik if (version > 1) { 3904f92b7604SImre Palik int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 3905f92b7604SImre Palik 3906f92b7604SImre Palik x86_pmu.num_counters_fixed = 3907f92b7604SImre Palik max((int)edx.split.num_counters_fixed, assume); 3908f92b7604SImre Palik } 3909e1069839SBorislav Petkov 3910e1069839SBorislav Petkov if (boot_cpu_has(X86_FEATURE_PDCM)) { 3911e1069839SBorislav Petkov u64 capabilities; 3912e1069839SBorislav Petkov 3913e1069839SBorislav Petkov rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 3914e1069839SBorislav Petkov x86_pmu.intel_cap.capabilities = capabilities; 3915e1069839SBorislav Petkov } 3916e1069839SBorislav Petkov 3917e1069839SBorislav Petkov intel_ds_init(); 3918e1069839SBorislav Petkov 3919e1069839SBorislav Petkov x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 3920e1069839SBorislav Petkov 3921e1069839SBorislav Petkov /* 3922e1069839SBorislav Petkov * Install the hw-cache-events table: 3923e1069839SBorislav Petkov */ 3924e1069839SBorislav Petkov switch (boot_cpu_data.x86_model) { 3925ef5f9f47SDave Hansen case INTEL_FAM6_CORE_YONAH: 3926e1069839SBorislav Petkov pr_cont("Core events, "); 3927b00233b5SAndi Kleen name = "core"; 3928e1069839SBorislav Petkov break; 3929e1069839SBorislav Petkov 3930ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM: 3931e1069839SBorislav Petkov x86_add_quirk(intel_clovertown_quirk); 3932ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM_L: 3933ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_PENRYN: 3934ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_DUNNINGTON: 3935e1069839SBorislav Petkov memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 3936e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 3937e1069839SBorislav Petkov 3938e1069839SBorislav Petkov intel_pmu_lbr_init_core(); 3939e1069839SBorislav Petkov 3940e1069839SBorislav Petkov x86_pmu.event_constraints = intel_core2_event_constraints; 3941e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 3942e1069839SBorislav Petkov pr_cont("Core2 events, "); 3943b00233b5SAndi Kleen name = "core2"; 3944e1069839SBorislav Petkov break; 3945e1069839SBorislav Petkov 3946ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM: 3947ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EP: 3948ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EX: 3949e1069839SBorislav Petkov memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 3950e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 3951e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 3952e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 3953e1069839SBorislav Petkov 3954e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 3955e1069839SBorislav Petkov 3956e1069839SBorislav Petkov x86_pmu.event_constraints = intel_nehalem_event_constraints; 3957e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 3958e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 3959e1069839SBorislav Petkov x86_pmu.extra_regs = intel_nehalem_extra_regs; 3960e1069839SBorislav Petkov 3961e1069839SBorislav Petkov x86_pmu.cpu_events = nhm_events_attrs; 3962e1069839SBorislav Petkov 3963e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 3964e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 3965e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 3966e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 3967e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 3968e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 3969e1069839SBorislav Petkov 3970e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 3971e1069839SBorislav Petkov x86_add_quirk(intel_nehalem_quirk); 397295298355SAndi Kleen x86_pmu.pebs_no_tlb = 1; 3973a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 3974e1069839SBorislav Petkov 3975e1069839SBorislav Petkov pr_cont("Nehalem events, "); 3976b00233b5SAndi Kleen name = "nehalem"; 3977e1069839SBorislav Petkov break; 3978e1069839SBorislav Petkov 3979ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_PINEVIEW: 3980ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_LINCROFT: 3981ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_PENWELL: 3982ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_CLOVERVIEW: 3983ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_CEDARVIEW: 3984e1069839SBorislav Petkov memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 3985e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 3986e1069839SBorislav Petkov 3987e1069839SBorislav Petkov intel_pmu_lbr_init_atom(); 3988e1069839SBorislav Petkov 3989e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 3990e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 3991e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 3992e1069839SBorislav Petkov pr_cont("Atom events, "); 3993b00233b5SAndi Kleen name = "bonnell"; 3994e1069839SBorislav Petkov break; 3995e1069839SBorislav Petkov 3996ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_SILVERMONT1: 3997ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_SILVERMONT2: 3998ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_AIRMONT: 3999e1069839SBorislav Petkov memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 4000e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4001e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 4002e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4003e1069839SBorislav Petkov 4004f21d5adcSKan Liang intel_pmu_lbr_init_slm(); 4005e1069839SBorislav Petkov 4006e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 4007e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4008e1069839SBorislav Petkov x86_pmu.extra_regs = intel_slm_extra_regs; 4009e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4010eb12b8ecSAndi Kleen x86_pmu.cpu_events = slm_events_attrs; 4011a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4012e1069839SBorislav Petkov pr_cont("Silvermont events, "); 4013b00233b5SAndi Kleen name = "silvermont"; 4014e1069839SBorislav Petkov break; 4015e1069839SBorislav Petkov 4016ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_GOLDMONT: 4017ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_DENVERTON: 40188b92c3a7SKan Liang memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 40198b92c3a7SKan Liang sizeof(hw_cache_event_ids)); 40208b92c3a7SKan Liang memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 40218b92c3a7SKan Liang sizeof(hw_cache_extra_regs)); 40228b92c3a7SKan Liang 40238b92c3a7SKan Liang intel_pmu_lbr_init_skl(); 40248b92c3a7SKan Liang 40258b92c3a7SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 40268b92c3a7SKan Liang x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 40278b92c3a7SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 40288b92c3a7SKan Liang /* 40298b92c3a7SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 40308b92c3a7SKan Liang * for precise cycles. 40318b92c3a7SKan Liang * :pp is identical to :ppp 40328b92c3a7SKan Liang */ 40338b92c3a7SKan Liang x86_pmu.pebs_aliases = NULL; 40348b92c3a7SKan Liang x86_pmu.pebs_prec_dist = true; 4035ccbebba4SAlexander Shishkin x86_pmu.lbr_pt_coexist = true; 40368b92c3a7SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4037ed827adbSKan Liang x86_pmu.cpu_events = glm_events_attrs; 4038a5df70c3SAndi Kleen extra_attr = slm_format_attr; 40398b92c3a7SKan Liang pr_cont("Goldmont events, "); 4040b00233b5SAndi Kleen name = "goldmont"; 40418b92c3a7SKan Liang break; 40428b92c3a7SKan Liang 4043dd0b06b5SKan Liang case INTEL_FAM6_ATOM_GEMINI_LAKE: 4044dd0b06b5SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4045dd0b06b5SKan Liang sizeof(hw_cache_event_ids)); 4046dd0b06b5SKan Liang memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 4047dd0b06b5SKan Liang sizeof(hw_cache_extra_regs)); 4048dd0b06b5SKan Liang 4049dd0b06b5SKan Liang intel_pmu_lbr_init_skl(); 4050dd0b06b5SKan Liang 4051dd0b06b5SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 4052dd0b06b5SKan Liang x86_pmu.pebs_constraints = intel_glp_pebs_event_constraints; 4053dd0b06b5SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 4054dd0b06b5SKan Liang /* 4055dd0b06b5SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4056dd0b06b5SKan Liang * for precise cycles. 4057dd0b06b5SKan Liang */ 4058dd0b06b5SKan Liang x86_pmu.pebs_aliases = NULL; 4059dd0b06b5SKan Liang x86_pmu.pebs_prec_dist = true; 4060dd0b06b5SKan Liang x86_pmu.lbr_pt_coexist = true; 4061dd0b06b5SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4062dd0b06b5SKan Liang x86_pmu.get_event_constraints = glp_get_event_constraints; 4063dd0b06b5SKan Liang x86_pmu.cpu_events = glm_events_attrs; 4064dd0b06b5SKan Liang /* Goldmont Plus has 4-wide pipeline */ 4065dd0b06b5SKan Liang event_attr_td_total_slots_scale_glm.event_str = "4"; 4066a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4067dd0b06b5SKan Liang pr_cont("Goldmont plus events, "); 4068b00233b5SAndi Kleen name = "goldmont_plus"; 4069dd0b06b5SKan Liang break; 4070dd0b06b5SKan Liang 4071ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE: 4072ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EP: 4073ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EX: 4074e1069839SBorislav Petkov memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 4075e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4076e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4077e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4078e1069839SBorislav Petkov 4079e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 4080e1069839SBorislav Petkov 4081e1069839SBorislav Petkov x86_pmu.event_constraints = intel_westmere_event_constraints; 4082e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4083e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 4084e1069839SBorislav Petkov x86_pmu.extra_regs = intel_westmere_extra_regs; 4085e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4086e1069839SBorislav Petkov 4087e1069839SBorislav Petkov x86_pmu.cpu_events = nhm_events_attrs; 4088e1069839SBorislav Petkov 4089e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 4090e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4091e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4092e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4093e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4094e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4095e1069839SBorislav Petkov 4096e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 4097a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4098e1069839SBorislav Petkov pr_cont("Westmere events, "); 4099b00233b5SAndi Kleen name = "westmere"; 4100e1069839SBorislav Petkov break; 4101e1069839SBorislav Petkov 4102ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 4103ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 4104e1069839SBorislav Petkov x86_add_quirk(intel_sandybridge_quirk); 4105e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4106e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4107e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4108e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4109e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4110e1069839SBorislav Petkov 4111e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 4112e1069839SBorislav Petkov 4113e1069839SBorislav Petkov x86_pmu.event_constraints = intel_snb_event_constraints; 4114e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 4115e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 4116ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 4117e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4118e1069839SBorislav Petkov else 4119e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 4120e1069839SBorislav Petkov 4121e1069839SBorislav Petkov 4122e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4123e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4124e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4125e1069839SBorislav Petkov 4126e1069839SBorislav Petkov x86_pmu.cpu_events = snb_events_attrs; 4127e1069839SBorislav Petkov 4128e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4129e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4130e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4131e1069839SBorislav Petkov /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 4132e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4133e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 4134e1069839SBorislav Petkov 4135a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4136a5df70c3SAndi Kleen 4137e1069839SBorislav Petkov pr_cont("SandyBridge events, "); 4138b00233b5SAndi Kleen name = "sandybridge"; 4139e1069839SBorislav Petkov break; 4140e1069839SBorislav Petkov 4141ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE: 4142ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE_X: 4143e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4144e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4145e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4146e1069839SBorislav Petkov /* dTLB-load-misses on IVB is different than SNB */ 4147e1069839SBorislav Petkov hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 4148e1069839SBorislav Petkov 4149e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4150e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4151e1069839SBorislav Petkov 4152e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 4153e1069839SBorislav Petkov 4154e1069839SBorislav Petkov x86_pmu.event_constraints = intel_ivb_event_constraints; 4155e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 4156e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4157e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4158ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 4159e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4160e1069839SBorislav Petkov else 4161e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 4162e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4163e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4164e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4165e1069839SBorislav Petkov 4166e1069839SBorislav Petkov x86_pmu.cpu_events = snb_events_attrs; 4167e1069839SBorislav Petkov 4168e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4169e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4170e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4171e1069839SBorislav Petkov 4172a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4173a5df70c3SAndi Kleen 4174e1069839SBorislav Petkov pr_cont("IvyBridge events, "); 4175b00233b5SAndi Kleen name = "ivybridge"; 4176e1069839SBorislav Petkov break; 4177e1069839SBorislav Petkov 4178e1069839SBorislav Petkov 4179ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_CORE: 4180ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_X: 4181ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_ULT: 4182ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_GT3E: 4183e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4184e1069839SBorislav Petkov x86_pmu.late_ack = true; 4185e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4186e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4187e1069839SBorislav Petkov 4188e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 4189e1069839SBorislav Petkov 4190e1069839SBorislav Petkov x86_pmu.event_constraints = intel_hsw_event_constraints; 4191e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 4192e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4193e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4194e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4195e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4196e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4197e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4198e1069839SBorislav Petkov 4199e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4200e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 420158ba4d5aSAndi Kleen x86_pmu.cpu_events = get_hsw_events_attrs(); 4202e1069839SBorislav Petkov x86_pmu.lbr_double_abort = true; 4203a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4204a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4205e1069839SBorislav Petkov pr_cont("Haswell events, "); 4206b00233b5SAndi Kleen name = "haswell"; 4207e1069839SBorislav Petkov break; 4208e1069839SBorislav Petkov 4209ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_CORE: 4210ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_XEON_D: 4211ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_GT3E: 4212ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_X: 4213e1069839SBorislav Petkov x86_pmu.late_ack = true; 4214e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4215e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4216e1069839SBorislav Petkov 4217e1069839SBorislav Petkov /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 4218e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 4219e1069839SBorislav Petkov BDW_L3_MISS|HSW_SNOOP_DRAM; 4220e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 4221e1069839SBorislav Petkov HSW_SNOOP_DRAM; 4222e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 4223e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4224e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 4225e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4226e1069839SBorislav Petkov 4227e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 4228e1069839SBorislav Petkov 4229e1069839SBorislav Petkov x86_pmu.event_constraints = intel_bdw_event_constraints; 4230b3e62463SStephane Eranian x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 4231e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4232e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4233e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4234e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4235e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4236e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4237e1069839SBorislav Petkov 4238e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4239e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 424058ba4d5aSAndi Kleen x86_pmu.cpu_events = get_hsw_events_attrs(); 4241e1069839SBorislav Petkov x86_pmu.limit_period = bdw_limit_period; 4242a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4243a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4244e1069839SBorislav Petkov pr_cont("Broadwell events, "); 4245b00233b5SAndi Kleen name = "broadwell"; 4246e1069839SBorislav Petkov break; 4247e1069839SBorislav Petkov 4248ef5f9f47SDave Hansen case INTEL_FAM6_XEON_PHI_KNL: 4249608284bfSPiotr Luc case INTEL_FAM6_XEON_PHI_KNM: 4250e1069839SBorislav Petkov memcpy(hw_cache_event_ids, 4251e1069839SBorislav Petkov slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4252e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, 4253e1069839SBorislav Petkov knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4254e1069839SBorislav Petkov intel_pmu_lbr_init_knl(); 4255e1069839SBorislav Petkov 4256e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 4257e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4258e1069839SBorislav Petkov x86_pmu.extra_regs = intel_knl_extra_regs; 4259e1069839SBorislav Petkov 4260e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4261e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4262e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4263a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4264608284bfSPiotr Luc pr_cont("Knights Landing/Mill events, "); 4265b00233b5SAndi Kleen name = "knights-landing"; 4266e1069839SBorislav Petkov break; 4267e1069839SBorislav Petkov 4268ef5f9f47SDave Hansen case INTEL_FAM6_SKYLAKE_MOBILE: 4269ef5f9f47SDave Hansen case INTEL_FAM6_SKYLAKE_DESKTOP: 4270ef5f9f47SDave Hansen case INTEL_FAM6_SKYLAKE_X: 4271ef5f9f47SDave Hansen case INTEL_FAM6_KABYLAKE_MOBILE: 4272ef5f9f47SDave Hansen case INTEL_FAM6_KABYLAKE_DESKTOP: 4273e1069839SBorislav Petkov x86_pmu.late_ack = true; 4274e1069839SBorislav Petkov memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4275e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4276e1069839SBorislav Petkov intel_pmu_lbr_init_skl(); 4277e1069839SBorislav Petkov 4278a39fcae7SAndi Kleen /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 4279a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_noht = 4280a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1"; 4281a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_ht = 4282a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1,any=1"; 4283a39fcae7SAndi Kleen 4284e1069839SBorislav Petkov x86_pmu.event_constraints = intel_skl_event_constraints; 4285e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 4286e1069839SBorislav Petkov x86_pmu.extra_regs = intel_skl_extra_regs; 4287e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 4288e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4289e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4290e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4291e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4292e1069839SBorislav Petkov 4293e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4294e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 4295a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4296a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4297a5df70c3SAndi Kleen extra_attr = merge_attr(extra_attr, skl_format_attr); 42987ad1437dSThomas Gleixner to_free = extra_attr; 429958ba4d5aSAndi Kleen x86_pmu.cpu_events = get_hsw_events_attrs(); 43006ae5fa61SAndi Kleen intel_pmu_pebs_data_source_skl( 43016ae5fa61SAndi Kleen boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X); 4302e1069839SBorislav Petkov pr_cont("Skylake events, "); 4303b00233b5SAndi Kleen name = "skylake"; 4304e1069839SBorislav Petkov break; 4305e1069839SBorislav Petkov 4306e1069839SBorislav Petkov default: 4307e1069839SBorislav Petkov switch (x86_pmu.version) { 4308e1069839SBorislav Petkov case 1: 4309e1069839SBorislav Petkov x86_pmu.event_constraints = intel_v1_event_constraints; 4310e1069839SBorislav Petkov pr_cont("generic architected perfmon v1, "); 4311b00233b5SAndi Kleen name = "generic_arch_v1"; 4312e1069839SBorislav Petkov break; 4313e1069839SBorislav Petkov default: 4314e1069839SBorislav Petkov /* 4315e1069839SBorislav Petkov * default constraints for v2 and up 4316e1069839SBorislav Petkov */ 4317e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 4318e1069839SBorislav Petkov pr_cont("generic architected perfmon, "); 4319b00233b5SAndi Kleen name = "generic_arch_v2+"; 4320e1069839SBorislav Petkov break; 4321e1069839SBorislav Petkov } 4322e1069839SBorislav Petkov } 4323e1069839SBorislav Petkov 4324b00233b5SAndi Kleen snprintf(pmu_name_str, sizeof pmu_name_str, "%s", name); 4325b00233b5SAndi Kleen 4326a5df70c3SAndi Kleen if (version >= 2 && extra_attr) { 4327a5df70c3SAndi Kleen x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, 4328a5df70c3SAndi Kleen extra_attr); 4329a5df70c3SAndi Kleen WARN_ON(!x86_pmu.format_attrs); 4330a5df70c3SAndi Kleen } 4331a5df70c3SAndi Kleen 4332e1069839SBorislav Petkov if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 4333e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 4334e1069839SBorislav Petkov x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 4335e1069839SBorislav Petkov x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 4336e1069839SBorislav Petkov } 4337ad5013d5SColin King x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 4338e1069839SBorislav Petkov 4339e1069839SBorislav Petkov if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 4340e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 4341e1069839SBorislav Petkov x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 4342e1069839SBorislav Petkov x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 4343e1069839SBorislav Petkov } 4344e1069839SBorislav Petkov 4345e1069839SBorislav Petkov x86_pmu.intel_ctrl |= 4346e1069839SBorislav Petkov ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 4347e1069839SBorislav Petkov 4348e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 4349e1069839SBorislav Petkov /* 4350e1069839SBorislav Petkov * event on fixed counter2 (REF_CYCLES) only works on this 4351e1069839SBorislav Petkov * counter, so do not extend mask to generic counters 4352e1069839SBorislav Petkov */ 4353e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 4354e1069839SBorislav Petkov if (c->cmask == FIXED_EVENT_FLAGS 4355e1069839SBorislav Petkov && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 4356e1069839SBorislav Petkov c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 4357e1069839SBorislav Petkov } 4358e1069839SBorislav Petkov c->idxmsk64 &= 43596d6f2833SAndrey Ryabinin ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 4360e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 4361e1069839SBorislav Petkov } 4362e1069839SBorislav Petkov } 4363e1069839SBorislav Petkov 4364e1069839SBorislav Petkov /* 4365e1069839SBorislav Petkov * Access LBR MSR may cause #GP under certain circumstances. 4366e1069839SBorislav Petkov * E.g. KVM doesn't support LBR MSR 4367e1069839SBorislav Petkov * Check all LBT MSR here. 4368e1069839SBorislav Petkov * Disable LBR access if any LBR MSRs can not be accessed. 4369e1069839SBorislav Petkov */ 4370e1069839SBorislav Petkov if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 4371e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 4372e1069839SBorislav Petkov for (i = 0; i < x86_pmu.lbr_nr; i++) { 4373e1069839SBorislav Petkov if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 4374e1069839SBorislav Petkov check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 4375e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 4376e1069839SBorislav Petkov } 4377e1069839SBorislav Petkov 4378b00233b5SAndi Kleen x86_pmu.caps_attrs = intel_pmu_caps_attrs; 4379b00233b5SAndi Kleen 4380b00233b5SAndi Kleen if (x86_pmu.lbr_nr) { 4381b00233b5SAndi Kleen x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs); 4382f09509b9SDavid Carrillo-Cisneros pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 4383b00233b5SAndi Kleen } 4384b00233b5SAndi Kleen 4385e1069839SBorislav Petkov /* 4386e1069839SBorislav Petkov * Access extra MSR may cause #GP under certain circumstances. 4387e1069839SBorislav Petkov * E.g. KVM doesn't support offcore event 4388e1069839SBorislav Petkov * Check all extra_regs here. 4389e1069839SBorislav Petkov */ 4390e1069839SBorislav Petkov if (x86_pmu.extra_regs) { 4391e1069839SBorislav Petkov for (er = x86_pmu.extra_regs; er->msr; er++) { 4392e1069839SBorislav Petkov er->extra_msr_access = check_msr(er->msr, 0x11UL); 4393e1069839SBorislav Petkov /* Disable LBR select mapping */ 4394e1069839SBorislav Petkov if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 4395e1069839SBorislav Petkov x86_pmu.lbr_sel_map = NULL; 4396e1069839SBorislav Petkov } 4397e1069839SBorislav Petkov } 4398e1069839SBorislav Petkov 4399e1069839SBorislav Petkov /* Support full width counters using alternative MSR range */ 4400e1069839SBorislav Petkov if (x86_pmu.intel_cap.full_width_write) { 44017f612a7fSPeter Zijlstra (Intel) x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 4402e1069839SBorislav Petkov x86_pmu.perfctr = MSR_IA32_PMC0; 4403e1069839SBorislav Petkov pr_cont("full-width counters, "); 4404e1069839SBorislav Petkov } 4405e1069839SBorislav Petkov 44067ad1437dSThomas Gleixner kfree(to_free); 4407e1069839SBorislav Petkov return 0; 4408e1069839SBorislav Petkov } 4409e1069839SBorislav Petkov 4410e1069839SBorislav Petkov /* 4411e1069839SBorislav Petkov * HT bug: phase 2 init 4412e1069839SBorislav Petkov * Called once we have valid topology information to check 4413e1069839SBorislav Petkov * whether or not HT is enabled 4414e1069839SBorislav Petkov * If HT is off, then we disable the workaround 4415e1069839SBorislav Petkov */ 4416e1069839SBorislav Petkov static __init int fixup_ht_bug(void) 4417e1069839SBorislav Petkov { 4418030ba6cdSAndi Kleen int c; 4419e1069839SBorislav Petkov /* 4420e1069839SBorislav Petkov * problem not present on this CPU model, nothing to do 4421e1069839SBorislav Petkov */ 4422e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 4423e1069839SBorislav Petkov return 0; 4424e1069839SBorislav Petkov 4425030ba6cdSAndi Kleen if (topology_max_smt_threads() > 1) { 4426e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 4427e1069839SBorislav Petkov return 0; 4428e1069839SBorislav Petkov } 4429e1069839SBorislav Petkov 44302406e3b1SPeter Zijlstra cpus_read_lock(); 44312406e3b1SPeter Zijlstra 44322406e3b1SPeter Zijlstra hardlockup_detector_perf_stop(); 4433e1069839SBorislav Petkov 4434e1069839SBorislav Petkov x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 4435e1069839SBorislav Petkov 4436e1069839SBorislav Petkov x86_pmu.start_scheduling = NULL; 4437e1069839SBorislav Petkov x86_pmu.commit_scheduling = NULL; 4438e1069839SBorislav Petkov x86_pmu.stop_scheduling = NULL; 4439e1069839SBorislav Petkov 44402406e3b1SPeter Zijlstra hardlockup_detector_perf_restart(); 4441e1069839SBorislav Petkov 44421ba143a5SSebastian Andrzej Siewior for_each_online_cpu(c) 4443e1069839SBorislav Petkov free_excl_cntrs(c); 4444e1069839SBorislav Petkov 44451ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 4446e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 4447e1069839SBorislav Petkov return 0; 4448e1069839SBorislav Petkov } 4449e1069839SBorislav Petkov subsys_initcall(fixup_ht_bug) 4450