1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1069839SBorislav Petkov /* 3e1069839SBorislav Petkov * Per core/cpu state 4e1069839SBorislav Petkov * 5e1069839SBorislav Petkov * Used to coordinate shared registers between HT threads or 6e1069839SBorislav Petkov * among events on a single PMU. 7e1069839SBorislav Petkov */ 8e1069839SBorislav Petkov 9e1069839SBorislav Petkov #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10e1069839SBorislav Petkov 11e1069839SBorislav Petkov #include <linux/stddef.h> 12e1069839SBorislav Petkov #include <linux/types.h> 13e1069839SBorislav Petkov #include <linux/init.h> 14e1069839SBorislav Petkov #include <linux/slab.h> 15e1069839SBorislav Petkov #include <linux/export.h> 16e1069839SBorislav Petkov #include <linux/nmi.h> 17e1069839SBorislav Petkov 18e1069839SBorislav Petkov #include <asm/cpufeature.h> 19e1069839SBorislav Petkov #include <asm/hardirq.h> 20ef5f9f47SDave Hansen #include <asm/intel-family.h> 2142880f72SAlexander Shishkin #include <asm/intel_pt.h> 22e1069839SBorislav Petkov #include <asm/apic.h> 239b545c04SAndi Kleen #include <asm/cpu_device_id.h> 24e1069839SBorislav Petkov 2527f6d22bSBorislav Petkov #include "../perf_event.h" 26e1069839SBorislav Petkov 27e1069839SBorislav Petkov /* 28e1069839SBorislav Petkov * Intel PerfMon, used on Core and later. 29e1069839SBorislav Petkov */ 30e1069839SBorislav Petkov static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31e1069839SBorislav Petkov { 32e1069839SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33e1069839SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38e1069839SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39e1069839SBorislav Petkov [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40e1069839SBorislav Petkov }; 41e1069839SBorislav Petkov 42e1069839SBorislav Petkov static struct event_constraint intel_core_event_constraints[] __read_mostly = 43e1069839SBorislav Petkov { 44e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50e1069839SBorislav Petkov EVENT_CONSTRAINT_END 51e1069839SBorislav Petkov }; 52e1069839SBorislav Petkov 53e1069839SBorislav Petkov static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54e1069839SBorislav Petkov { 55e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68e1069839SBorislav Petkov EVENT_CONSTRAINT_END 69e1069839SBorislav Petkov }; 70e1069839SBorislav Petkov 71e1069839SBorislav Petkov static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72e1069839SBorislav Petkov { 73e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84e1069839SBorislav Petkov EVENT_CONSTRAINT_END 85e1069839SBorislav Petkov }; 86e1069839SBorislav Petkov 87e1069839SBorislav Petkov static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88e1069839SBorislav Petkov { 89e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92e1069839SBorislav Petkov EVENT_EXTRA_END 93e1069839SBorislav Petkov }; 94e1069839SBorislav Petkov 95e1069839SBorislav Petkov static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96e1069839SBorislav Petkov { 97e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104e1069839SBorislav Petkov EVENT_CONSTRAINT_END 105e1069839SBorislav Petkov }; 106e1069839SBorislav Petkov 107e1069839SBorislav Petkov static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108e1069839SBorislav Petkov { 109e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121e1069839SBorislav Petkov 1229010ae4aSStephane Eranian /* 1239010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1249010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1259010ae4aSStephane Eranian */ 126e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130e1069839SBorislav Petkov 131e1069839SBorislav Petkov EVENT_CONSTRAINT_END 132e1069839SBorislav Petkov }; 133e1069839SBorislav Petkov 134e1069839SBorislav Petkov static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135e1069839SBorislav Petkov { 136e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 141e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149e1069839SBorislav Petkov 1509010ae4aSStephane Eranian /* 1519010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1529010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1539010ae4aSStephane Eranian */ 154e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158e1069839SBorislav Petkov 159e1069839SBorislav Petkov EVENT_CONSTRAINT_END 160e1069839SBorislav Petkov }; 161e1069839SBorislav Petkov 162e1069839SBorislav Petkov static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163e1069839SBorislav Petkov { 164e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168e1069839SBorislav Petkov EVENT_EXTRA_END 169e1069839SBorislav Petkov }; 170e1069839SBorislav Petkov 171e1069839SBorislav Petkov static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172e1069839SBorislav Petkov { 173e1069839SBorislav Petkov EVENT_CONSTRAINT_END 174e1069839SBorislav Petkov }; 175e1069839SBorislav Petkov 176e1069839SBorislav Petkov static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177e1069839SBorislav Petkov { 178e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181e1069839SBorislav Petkov EVENT_CONSTRAINT_END 182e1069839SBorislav Petkov }; 183e1069839SBorislav Petkov 184e1069839SBorislav Petkov static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185e1069839SBorislav Petkov { 186e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189e1069839SBorislav Petkov EVENT_CONSTRAINT_END 190e1069839SBorislav Petkov }; 191e1069839SBorislav Petkov 19220f36278SLukasz Odzioba static struct event_constraint intel_skl_event_constraints[] = { 193e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1979010ae4aSStephane Eranian 1989010ae4aSStephane Eranian /* 1999010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 2009010ae4aSStephane Eranian */ 2019010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 2029010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 2039010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 2049010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 2059010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 2069010ae4aSStephane Eranian 207e1069839SBorislav Petkov EVENT_CONSTRAINT_END 208e1069839SBorislav Petkov }; 209e1069839SBorislav Petkov 210e1069839SBorislav Petkov static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 2119c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 2129c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213e1069839SBorislav Petkov EVENT_EXTRA_END 214e1069839SBorislav Petkov }; 215e1069839SBorislav Petkov 216e1069839SBorislav Petkov static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221e1069839SBorislav Petkov EVENT_EXTRA_END 222e1069839SBorislav Petkov }; 223e1069839SBorislav Petkov 224e1069839SBorislav Petkov static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229e1069839SBorislav Petkov EVENT_EXTRA_END 230e1069839SBorislav Petkov }; 231e1069839SBorislav Petkov 232e1069839SBorislav Petkov static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236e1069839SBorislav Petkov /* 237e1069839SBorislav Petkov * Note the low 8 bits eventsel code is not a continuous field, containing 238e1069839SBorislav Petkov * some #GPing bits. These are masked out. 239e1069839SBorislav Petkov */ 240e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241e1069839SBorislav Petkov EVENT_EXTRA_END 242e1069839SBorislav Petkov }; 243e1069839SBorislav Petkov 24460176089SKan Liang static struct event_constraint intel_icl_event_constraints[] = { 24560176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 24660176089SKan Liang INTEL_UEVENT_CONSTRAINT(0x1c0, 0), /* INST_RETIRED.PREC_DIST */ 24760176089SKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 24860176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 24960176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 25060176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 25160176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 25260176089SKan Liang INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 25360176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 25460176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 25560176089SKan Liang INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 25660176089SKan Liang INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 25760176089SKan Liang INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 25860176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 25960176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 26060176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 26160176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 26260176089SKan Liang EVENT_CONSTRAINT_END 26360176089SKan Liang }; 26460176089SKan Liang 26560176089SKan Liang static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 2663b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 2673b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 26860176089SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 26960176089SKan Liang INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 27060176089SKan Liang EVENT_EXTRA_END 27160176089SKan Liang }; 27260176089SKan Liang 273e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 274e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 275e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 276e1069839SBorislav Petkov 277d4ae5529SJiri Olsa static struct attribute *nhm_mem_events_attrs[] = { 278e1069839SBorislav Petkov EVENT_PTR(mem_ld_nhm), 279e1069839SBorislav Petkov NULL, 280e1069839SBorislav Petkov }; 281e1069839SBorislav Petkov 282a39fcae7SAndi Kleen /* 283a39fcae7SAndi Kleen * topdown events for Intel Core CPUs. 284a39fcae7SAndi Kleen * 285a39fcae7SAndi Kleen * The events are all in slots, which is a free slot in a 4 wide 286a39fcae7SAndi Kleen * pipeline. Some events are already reported in slots, for cycle 287a39fcae7SAndi Kleen * events we multiply by the pipeline width (4). 288a39fcae7SAndi Kleen * 289a39fcae7SAndi Kleen * With Hyper Threading on, topdown metrics are either summed or averaged 290a39fcae7SAndi Kleen * between the threads of a core: (count_t0 + count_t1). 291a39fcae7SAndi Kleen * 292a39fcae7SAndi Kleen * For the average case the metric is always scaled to pipeline width, 293a39fcae7SAndi Kleen * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 294a39fcae7SAndi Kleen */ 295a39fcae7SAndi Kleen 296a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 297a39fcae7SAndi Kleen "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 298a39fcae7SAndi Kleen "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 299a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 300a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 301a39fcae7SAndi Kleen "event=0xe,umask=0x1"); /* uops_issued.any */ 302a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 303a39fcae7SAndi Kleen "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 304a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 305a39fcae7SAndi Kleen "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 306a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 307a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 308a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 309a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 310a39fcae7SAndi Kleen "4", "2"); 311a39fcae7SAndi Kleen 31220f36278SLukasz Odzioba static struct attribute *snb_events_attrs[] = { 313a39fcae7SAndi Kleen EVENT_PTR(td_slots_issued), 314a39fcae7SAndi Kleen EVENT_PTR(td_slots_retired), 315a39fcae7SAndi Kleen EVENT_PTR(td_fetch_bubbles), 316a39fcae7SAndi Kleen EVENT_PTR(td_total_slots), 317a39fcae7SAndi Kleen EVENT_PTR(td_total_slots_scale), 318a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles), 319a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 320e1069839SBorislav Petkov NULL, 321e1069839SBorislav Petkov }; 322e1069839SBorislav Petkov 323d4ae5529SJiri Olsa static struct attribute *snb_mem_events_attrs[] = { 324d4ae5529SJiri Olsa EVENT_PTR(mem_ld_snb), 325d4ae5529SJiri Olsa EVENT_PTR(mem_st_snb), 326d4ae5529SJiri Olsa NULL, 327d4ae5529SJiri Olsa }; 328d4ae5529SJiri Olsa 329e1069839SBorislav Petkov static struct event_constraint intel_hsw_event_constraints[] = { 330e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 331e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 332e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 333e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 334e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 335e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 336e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 337e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 338e1069839SBorislav Petkov /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 339e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 340e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 341e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 342e1069839SBorislav Petkov 3439010ae4aSStephane Eranian /* 3449010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 3459010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 3469010ae4aSStephane Eranian */ 347e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 348e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 349e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 350e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 351e1069839SBorislav Petkov 352e1069839SBorislav Petkov EVENT_CONSTRAINT_END 353e1069839SBorislav Petkov }; 354e1069839SBorislav Petkov 35520f36278SLukasz Odzioba static struct event_constraint intel_bdw_event_constraints[] = { 356e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 357e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 358e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 359e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 360e1069839SBorislav Petkov INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 3619010ae4aSStephane Eranian /* 3629010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 3639010ae4aSStephane Eranian */ 3649010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 3659010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 3669010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 3679010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 368e1069839SBorislav Petkov EVENT_CONSTRAINT_END 369e1069839SBorislav Petkov }; 370e1069839SBorislav Petkov 371e1069839SBorislav Petkov static u64 intel_pmu_event_map(int hw_event) 372e1069839SBorislav Petkov { 373e1069839SBorislav Petkov return intel_perfmon_event_map[hw_event]; 374e1069839SBorislav Petkov } 375e1069839SBorislav Petkov 376e1069839SBorislav Petkov /* 377e1069839SBorislav Petkov * Notes on the events: 378e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 379e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 380e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 381e1069839SBorislav Petkov * - prefetches are not included in the counts. 382e1069839SBorislav Petkov * - icache miss does not include decoded icache 383e1069839SBorislav Petkov */ 384e1069839SBorislav Petkov 385e1069839SBorislav Petkov #define SKL_DEMAND_DATA_RD BIT_ULL(0) 386e1069839SBorislav Petkov #define SKL_DEMAND_RFO BIT_ULL(1) 387e1069839SBorislav Petkov #define SKL_ANY_RESPONSE BIT_ULL(16) 388e1069839SBorislav Petkov #define SKL_SUPPLIER_NONE BIT_ULL(17) 389e1069839SBorislav Petkov #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 390e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 391e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 392e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 393e1069839SBorislav Petkov #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 394e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 395e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 396e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 397e1069839SBorislav Petkov #define SKL_SPL_HIT BIT_ULL(30) 398e1069839SBorislav Petkov #define SKL_SNOOP_NONE BIT_ULL(31) 399e1069839SBorislav Petkov #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 400e1069839SBorislav Petkov #define SKL_SNOOP_MISS BIT_ULL(33) 401e1069839SBorislav Petkov #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 402e1069839SBorislav Petkov #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 403e1069839SBorislav Petkov #define SKL_SNOOP_HITM BIT_ULL(36) 404e1069839SBorislav Petkov #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 405e1069839SBorislav Petkov #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 406e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 407e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 408e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 409e1069839SBorislav Petkov #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 410e1069839SBorislav Petkov #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 411e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 412e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 413e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SPL_HIT) 414e1069839SBorislav Petkov #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 415e1069839SBorislav Petkov #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 416e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 417e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 418e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 419e1069839SBorislav Petkov 420e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_event_ids 421e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 422e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 423e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 424e1069839SBorislav Petkov { 425e1069839SBorislav Petkov [ C(L1D ) ] = { 426e1069839SBorislav Petkov [ C(OP_READ) ] = { 427e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 428e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 429e1069839SBorislav Petkov }, 430e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 431e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 432e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 433e1069839SBorislav Petkov }, 434e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 435e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 436e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 437e1069839SBorislav Petkov }, 438e1069839SBorislav Petkov }, 439e1069839SBorislav Petkov [ C(L1I ) ] = { 440e1069839SBorislav Petkov [ C(OP_READ) ] = { 441e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 442e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 443e1069839SBorislav Petkov }, 444e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 445e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 446e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 447e1069839SBorislav Petkov }, 448e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 449e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 450e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 451e1069839SBorislav Petkov }, 452e1069839SBorislav Petkov }, 453e1069839SBorislav Petkov [ C(LL ) ] = { 454e1069839SBorislav Petkov [ C(OP_READ) ] = { 455e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 456e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 457e1069839SBorislav Petkov }, 458e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 459e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 460e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 461e1069839SBorislav Petkov }, 462e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 463e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 464e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 465e1069839SBorislav Petkov }, 466e1069839SBorislav Petkov }, 467e1069839SBorislav Petkov [ C(DTLB) ] = { 468e1069839SBorislav Petkov [ C(OP_READ) ] = { 469e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 470fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 471e1069839SBorislav Petkov }, 472e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 473e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 474fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 475e1069839SBorislav Petkov }, 476e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 477e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 478e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 479e1069839SBorislav Petkov }, 480e1069839SBorislav Petkov }, 481e1069839SBorislav Petkov [ C(ITLB) ] = { 482e1069839SBorislav Petkov [ C(OP_READ) ] = { 483e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 484e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 485e1069839SBorislav Petkov }, 486e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 487e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 488e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 489e1069839SBorislav Petkov }, 490e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 491e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 492e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 493e1069839SBorislav Petkov }, 494e1069839SBorislav Petkov }, 495e1069839SBorislav Petkov [ C(BPU ) ] = { 496e1069839SBorislav Petkov [ C(OP_READ) ] = { 497e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 498e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 499e1069839SBorislav Petkov }, 500e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 501e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 502e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 503e1069839SBorislav Petkov }, 504e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 505e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 506e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 507e1069839SBorislav Petkov }, 508e1069839SBorislav Petkov }, 509e1069839SBorislav Petkov [ C(NODE) ] = { 510e1069839SBorislav Petkov [ C(OP_READ) ] = { 511e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 512e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 513e1069839SBorislav Petkov }, 514e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 515e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 516e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 517e1069839SBorislav Petkov }, 518e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 519e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 520e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 521e1069839SBorislav Petkov }, 522e1069839SBorislav Petkov }, 523e1069839SBorislav Petkov }; 524e1069839SBorislav Petkov 525e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_extra_regs 526e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 527e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 528e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 529e1069839SBorislav Petkov { 530e1069839SBorislav Petkov [ C(LL ) ] = { 531e1069839SBorislav Petkov [ C(OP_READ) ] = { 532e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 533e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 534e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 535e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 536e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 537e1069839SBorislav Petkov }, 538e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 539e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 540e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 541e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 542e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 543e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 544e1069839SBorislav Petkov }, 545e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 546e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 547e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 548e1069839SBorislav Petkov }, 549e1069839SBorislav Petkov }, 550e1069839SBorislav Petkov [ C(NODE) ] = { 551e1069839SBorislav Petkov [ C(OP_READ) ] = { 552e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 553e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 554e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 555e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 556e1069839SBorislav Petkov }, 557e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 558e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 559e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 560e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 561e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 562e1069839SBorislav Petkov }, 563e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 564e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 565e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 566e1069839SBorislav Petkov }, 567e1069839SBorislav Petkov }, 568e1069839SBorislav Petkov }; 569e1069839SBorislav Petkov 570e1069839SBorislav Petkov #define SNB_DMND_DATA_RD (1ULL << 0) 571e1069839SBorislav Petkov #define SNB_DMND_RFO (1ULL << 1) 572e1069839SBorislav Petkov #define SNB_DMND_IFETCH (1ULL << 2) 573e1069839SBorislav Petkov #define SNB_DMND_WB (1ULL << 3) 574e1069839SBorislav Petkov #define SNB_PF_DATA_RD (1ULL << 4) 575e1069839SBorislav Petkov #define SNB_PF_RFO (1ULL << 5) 576e1069839SBorislav Petkov #define SNB_PF_IFETCH (1ULL << 6) 577e1069839SBorislav Petkov #define SNB_LLC_DATA_RD (1ULL << 7) 578e1069839SBorislav Petkov #define SNB_LLC_RFO (1ULL << 8) 579e1069839SBorislav Petkov #define SNB_LLC_IFETCH (1ULL << 9) 580e1069839SBorislav Petkov #define SNB_BUS_LOCKS (1ULL << 10) 581e1069839SBorislav Petkov #define SNB_STRM_ST (1ULL << 11) 582e1069839SBorislav Petkov #define SNB_OTHER (1ULL << 15) 583e1069839SBorislav Petkov #define SNB_RESP_ANY (1ULL << 16) 584e1069839SBorislav Petkov #define SNB_NO_SUPP (1ULL << 17) 585e1069839SBorislav Petkov #define SNB_LLC_HITM (1ULL << 18) 586e1069839SBorislav Petkov #define SNB_LLC_HITE (1ULL << 19) 587e1069839SBorislav Petkov #define SNB_LLC_HITS (1ULL << 20) 588e1069839SBorislav Petkov #define SNB_LLC_HITF (1ULL << 21) 589e1069839SBorislav Petkov #define SNB_LOCAL (1ULL << 22) 590e1069839SBorislav Petkov #define SNB_REMOTE (0xffULL << 23) 591e1069839SBorislav Petkov #define SNB_SNP_NONE (1ULL << 31) 592e1069839SBorislav Petkov #define SNB_SNP_NOT_NEEDED (1ULL << 32) 593e1069839SBorislav Petkov #define SNB_SNP_MISS (1ULL << 33) 594e1069839SBorislav Petkov #define SNB_NO_FWD (1ULL << 34) 595e1069839SBorislav Petkov #define SNB_SNP_FWD (1ULL << 35) 596e1069839SBorislav Petkov #define SNB_HITM (1ULL << 36) 597e1069839SBorislav Petkov #define SNB_NON_DRAM (1ULL << 37) 598e1069839SBorislav Petkov 599e1069839SBorislav Petkov #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 600e1069839SBorislav Petkov #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 601e1069839SBorislav Petkov #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 602e1069839SBorislav Petkov 603e1069839SBorislav Petkov #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 604e1069839SBorislav Petkov SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 605e1069839SBorislav Petkov SNB_HITM) 606e1069839SBorislav Petkov 607e1069839SBorislav Petkov #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 608e1069839SBorislav Petkov #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 609e1069839SBorislav Petkov 610e1069839SBorislav Petkov #define SNB_L3_ACCESS SNB_RESP_ANY 611e1069839SBorislav Petkov #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 612e1069839SBorislav Petkov 613e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_extra_regs 614e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 615e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 616e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 617e1069839SBorislav Petkov { 618e1069839SBorislav Petkov [ C(LL ) ] = { 619e1069839SBorislav Petkov [ C(OP_READ) ] = { 620e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 621e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 622e1069839SBorislav Petkov }, 623e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 624e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 625e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 626e1069839SBorislav Petkov }, 627e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 628e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 629e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 630e1069839SBorislav Petkov }, 631e1069839SBorislav Petkov }, 632e1069839SBorislav Petkov [ C(NODE) ] = { 633e1069839SBorislav Petkov [ C(OP_READ) ] = { 634e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 635e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 636e1069839SBorislav Petkov }, 637e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 638e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 639e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 640e1069839SBorislav Petkov }, 641e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 642e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 643e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 644e1069839SBorislav Petkov }, 645e1069839SBorislav Petkov }, 646e1069839SBorislav Petkov }; 647e1069839SBorislav Petkov 648e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_event_ids 649e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 650e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 651e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 652e1069839SBorislav Petkov { 653e1069839SBorislav Petkov [ C(L1D) ] = { 654e1069839SBorislav Petkov [ C(OP_READ) ] = { 655e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 656e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 657e1069839SBorislav Petkov }, 658e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 659e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 660e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 661e1069839SBorislav Petkov }, 662e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 663e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 664e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 665e1069839SBorislav Petkov }, 666e1069839SBorislav Petkov }, 667e1069839SBorislav Petkov [ C(L1I ) ] = { 668e1069839SBorislav Petkov [ C(OP_READ) ] = { 669e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 670e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 671e1069839SBorislav Petkov }, 672e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 673e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 674e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 675e1069839SBorislav Petkov }, 676e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 677e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 678e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 679e1069839SBorislav Petkov }, 680e1069839SBorislav Petkov }, 681e1069839SBorislav Petkov [ C(LL ) ] = { 682e1069839SBorislav Petkov [ C(OP_READ) ] = { 683e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 684e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 685e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 686e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 687e1069839SBorislav Petkov }, 688e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 689e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 690e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 691e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 692e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 693e1069839SBorislav Petkov }, 694e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 695e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 696e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 697e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 698e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 699e1069839SBorislav Petkov }, 700e1069839SBorislav Petkov }, 701e1069839SBorislav Petkov [ C(DTLB) ] = { 702e1069839SBorislav Petkov [ C(OP_READ) ] = { 703e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 704e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 705e1069839SBorislav Petkov }, 706e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 707e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 708e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 709e1069839SBorislav Petkov }, 710e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 711e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 712e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 713e1069839SBorislav Petkov }, 714e1069839SBorislav Petkov }, 715e1069839SBorislav Petkov [ C(ITLB) ] = { 716e1069839SBorislav Petkov [ C(OP_READ) ] = { 717e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 718e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 719e1069839SBorislav Petkov }, 720e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 721e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 722e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 723e1069839SBorislav Petkov }, 724e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 725e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 726e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 727e1069839SBorislav Petkov }, 728e1069839SBorislav Petkov }, 729e1069839SBorislav Petkov [ C(BPU ) ] = { 730e1069839SBorislav Petkov [ C(OP_READ) ] = { 731e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 732e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 733e1069839SBorislav Petkov }, 734e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 735e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 736e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 737e1069839SBorislav Petkov }, 738e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 739e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 740e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 741e1069839SBorislav Petkov }, 742e1069839SBorislav Petkov }, 743e1069839SBorislav Petkov [ C(NODE) ] = { 744e1069839SBorislav Petkov [ C(OP_READ) ] = { 745e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 746e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 747e1069839SBorislav Petkov }, 748e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 749e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 750e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 751e1069839SBorislav Petkov }, 752e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 753e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 754e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 755e1069839SBorislav Petkov }, 756e1069839SBorislav Petkov }, 757e1069839SBorislav Petkov 758e1069839SBorislav Petkov }; 759e1069839SBorislav Petkov 760e1069839SBorislav Petkov /* 761e1069839SBorislav Petkov * Notes on the events: 762e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 763e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 764e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 765e1069839SBorislav Petkov * - prefetches are not included in the counts because they are not 766e1069839SBorislav Petkov * reliably counted. 767e1069839SBorislav Petkov */ 768e1069839SBorislav Petkov 769e1069839SBorislav Petkov #define HSW_DEMAND_DATA_RD BIT_ULL(0) 770e1069839SBorislav Petkov #define HSW_DEMAND_RFO BIT_ULL(1) 771e1069839SBorislav Petkov #define HSW_ANY_RESPONSE BIT_ULL(16) 772e1069839SBorislav Petkov #define HSW_SUPPLIER_NONE BIT_ULL(17) 773e1069839SBorislav Petkov #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 774e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 775e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 776e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 777e1069839SBorislav Petkov #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 778e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 779e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 780e1069839SBorislav Petkov #define HSW_SNOOP_NONE BIT_ULL(31) 781e1069839SBorislav Petkov #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 782e1069839SBorislav Petkov #define HSW_SNOOP_MISS BIT_ULL(33) 783e1069839SBorislav Petkov #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 784e1069839SBorislav Petkov #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 785e1069839SBorislav Petkov #define HSW_SNOOP_HITM BIT_ULL(36) 786e1069839SBorislav Petkov #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 787e1069839SBorislav Petkov #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 788e1069839SBorislav Petkov HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 789e1069839SBorislav Petkov HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 790e1069839SBorislav Petkov HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 791e1069839SBorislav Petkov #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 792e1069839SBorislav Petkov #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 793e1069839SBorislav Petkov #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 794e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 795e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 796e1069839SBorislav Petkov #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 797e1069839SBorislav Petkov 798e1069839SBorislav Petkov #define BDW_L3_MISS_LOCAL BIT(26) 799e1069839SBorislav Petkov #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 800e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 801e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 802e1069839SBorislav Petkov 803e1069839SBorislav Petkov 804e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_event_ids 805e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 806e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 807e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 808e1069839SBorislav Petkov { 809e1069839SBorislav Petkov [ C(L1D ) ] = { 810e1069839SBorislav Petkov [ C(OP_READ) ] = { 811e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 812e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 813e1069839SBorislav Petkov }, 814e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 815e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 816e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 817e1069839SBorislav Petkov }, 818e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 819e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 820e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 821e1069839SBorislav Petkov }, 822e1069839SBorislav Petkov }, 823e1069839SBorislav Petkov [ C(L1I ) ] = { 824e1069839SBorislav Petkov [ C(OP_READ) ] = { 825e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 826e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 827e1069839SBorislav Petkov }, 828e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 829e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 830e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 831e1069839SBorislav Petkov }, 832e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 833e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 834e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 835e1069839SBorislav Petkov }, 836e1069839SBorislav Petkov }, 837e1069839SBorislav Petkov [ C(LL ) ] = { 838e1069839SBorislav Petkov [ C(OP_READ) ] = { 839e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 840e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 841e1069839SBorislav Petkov }, 842e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 843e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 844e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 845e1069839SBorislav Petkov }, 846e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 847e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 848e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 849e1069839SBorislav Petkov }, 850e1069839SBorislav Petkov }, 851e1069839SBorislav Petkov [ C(DTLB) ] = { 852e1069839SBorislav Petkov [ C(OP_READ) ] = { 853e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 854e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 855e1069839SBorislav Petkov }, 856e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 857e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 858e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 859e1069839SBorislav Petkov }, 860e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 861e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 862e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 863e1069839SBorislav Petkov }, 864e1069839SBorislav Petkov }, 865e1069839SBorislav Petkov [ C(ITLB) ] = { 866e1069839SBorislav Petkov [ C(OP_READ) ] = { 867e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 868e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 869e1069839SBorislav Petkov }, 870e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 871e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 872e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 873e1069839SBorislav Petkov }, 874e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 875e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 876e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 877e1069839SBorislav Petkov }, 878e1069839SBorislav Petkov }, 879e1069839SBorislav Petkov [ C(BPU ) ] = { 880e1069839SBorislav Petkov [ C(OP_READ) ] = { 881e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 882e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 883e1069839SBorislav Petkov }, 884e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 885e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 886e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 887e1069839SBorislav Petkov }, 888e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 889e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 890e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 891e1069839SBorislav Petkov }, 892e1069839SBorislav Petkov }, 893e1069839SBorislav Petkov [ C(NODE) ] = { 894e1069839SBorislav Petkov [ C(OP_READ) ] = { 895e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 896e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 897e1069839SBorislav Petkov }, 898e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 899e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 900e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 901e1069839SBorislav Petkov }, 902e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 903e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 904e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 905e1069839SBorislav Petkov }, 906e1069839SBorislav Petkov }, 907e1069839SBorislav Petkov }; 908e1069839SBorislav Petkov 909e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_extra_regs 910e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 911e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 912e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 913e1069839SBorislav Petkov { 914e1069839SBorislav Petkov [ C(LL ) ] = { 915e1069839SBorislav Petkov [ C(OP_READ) ] = { 916e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 917e1069839SBorislav Petkov HSW_LLC_ACCESS, 918e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 919e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 920e1069839SBorislav Petkov }, 921e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 922e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 923e1069839SBorislav Petkov HSW_LLC_ACCESS, 924e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 925e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 926e1069839SBorislav Petkov }, 927e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 928e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 929e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 930e1069839SBorislav Petkov }, 931e1069839SBorislav Petkov }, 932e1069839SBorislav Petkov [ C(NODE) ] = { 933e1069839SBorislav Petkov [ C(OP_READ) ] = { 934e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 935e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 936e1069839SBorislav Petkov HSW_SNOOP_DRAM, 937e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 938e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 939e1069839SBorislav Petkov HSW_SNOOP_DRAM, 940e1069839SBorislav Petkov }, 941e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 942e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 943e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 944e1069839SBorislav Petkov HSW_SNOOP_DRAM, 945e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 946e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 947e1069839SBorislav Petkov HSW_SNOOP_DRAM, 948e1069839SBorislav Petkov }, 949e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 950e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 951e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 952e1069839SBorislav Petkov }, 953e1069839SBorislav Petkov }, 954e1069839SBorislav Petkov }; 955e1069839SBorislav Petkov 956e1069839SBorislav Petkov static __initconst const u64 westmere_hw_cache_event_ids 957e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 958e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 959e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 960e1069839SBorislav Petkov { 961e1069839SBorislav Petkov [ C(L1D) ] = { 962e1069839SBorislav Petkov [ C(OP_READ) ] = { 963e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 964e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 965e1069839SBorislav Petkov }, 966e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 967e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 968e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 969e1069839SBorislav Petkov }, 970e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 971e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 972e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 973e1069839SBorislav Petkov }, 974e1069839SBorislav Petkov }, 975e1069839SBorislav Petkov [ C(L1I ) ] = { 976e1069839SBorislav Petkov [ C(OP_READ) ] = { 977e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 978e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 979e1069839SBorislav Petkov }, 980e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 981e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 982e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 983e1069839SBorislav Petkov }, 984e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 985e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 986e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 987e1069839SBorislav Petkov }, 988e1069839SBorislav Petkov }, 989e1069839SBorislav Petkov [ C(LL ) ] = { 990e1069839SBorislav Petkov [ C(OP_READ) ] = { 991e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 992e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 993e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 994e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 995e1069839SBorislav Petkov }, 996e1069839SBorislav Petkov /* 997e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 998e1069839SBorislav Petkov * on RFO. 999e1069839SBorislav Petkov */ 1000e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1001e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1002e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1003e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1004e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1005e1069839SBorislav Petkov }, 1006e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1007e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1008e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1009e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1010e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1011e1069839SBorislav Petkov }, 1012e1069839SBorislav Petkov }, 1013e1069839SBorislav Petkov [ C(DTLB) ] = { 1014e1069839SBorislav Petkov [ C(OP_READ) ] = { 1015e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1016e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1017e1069839SBorislav Petkov }, 1018e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1019e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1020e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1021e1069839SBorislav Petkov }, 1022e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1023e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1024e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1025e1069839SBorislav Petkov }, 1026e1069839SBorislav Petkov }, 1027e1069839SBorislav Petkov [ C(ITLB) ] = { 1028e1069839SBorislav Petkov [ C(OP_READ) ] = { 1029e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1030e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1031e1069839SBorislav Petkov }, 1032e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1033e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1034e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1035e1069839SBorislav Petkov }, 1036e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1037e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1038e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1039e1069839SBorislav Petkov }, 1040e1069839SBorislav Petkov }, 1041e1069839SBorislav Petkov [ C(BPU ) ] = { 1042e1069839SBorislav Petkov [ C(OP_READ) ] = { 1043e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1044e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1045e1069839SBorislav Petkov }, 1046e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1047e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1048e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1049e1069839SBorislav Petkov }, 1050e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1051e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1052e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1053e1069839SBorislav Petkov }, 1054e1069839SBorislav Petkov }, 1055e1069839SBorislav Petkov [ C(NODE) ] = { 1056e1069839SBorislav Petkov [ C(OP_READ) ] = { 1057e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1058e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1059e1069839SBorislav Petkov }, 1060e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1061e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1062e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1063e1069839SBorislav Petkov }, 1064e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1065e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1066e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1067e1069839SBorislav Petkov }, 1068e1069839SBorislav Petkov }, 1069e1069839SBorislav Petkov }; 1070e1069839SBorislav Petkov 1071e1069839SBorislav Petkov /* 1072e1069839SBorislav Petkov * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1073e1069839SBorislav Petkov * See IA32 SDM Vol 3B 30.6.1.3 1074e1069839SBorislav Petkov */ 1075e1069839SBorislav Petkov 1076e1069839SBorislav Petkov #define NHM_DMND_DATA_RD (1 << 0) 1077e1069839SBorislav Petkov #define NHM_DMND_RFO (1 << 1) 1078e1069839SBorislav Petkov #define NHM_DMND_IFETCH (1 << 2) 1079e1069839SBorislav Petkov #define NHM_DMND_WB (1 << 3) 1080e1069839SBorislav Petkov #define NHM_PF_DATA_RD (1 << 4) 1081e1069839SBorislav Petkov #define NHM_PF_DATA_RFO (1 << 5) 1082e1069839SBorislav Petkov #define NHM_PF_IFETCH (1 << 6) 1083e1069839SBorislav Petkov #define NHM_OFFCORE_OTHER (1 << 7) 1084e1069839SBorislav Petkov #define NHM_UNCORE_HIT (1 << 8) 1085e1069839SBorislav Petkov #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1086e1069839SBorislav Petkov #define NHM_OTHER_CORE_HITM (1 << 10) 1087e1069839SBorislav Petkov /* reserved */ 1088e1069839SBorislav Petkov #define NHM_REMOTE_CACHE_FWD (1 << 12) 1089e1069839SBorislav Petkov #define NHM_REMOTE_DRAM (1 << 13) 1090e1069839SBorislav Petkov #define NHM_LOCAL_DRAM (1 << 14) 1091e1069839SBorislav Petkov #define NHM_NON_DRAM (1 << 15) 1092e1069839SBorislav Petkov 1093e1069839SBorislav Petkov #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1094e1069839SBorislav Petkov #define NHM_REMOTE (NHM_REMOTE_DRAM) 1095e1069839SBorislav Petkov 1096e1069839SBorislav Petkov #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1097e1069839SBorislav Petkov #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1098e1069839SBorislav Petkov #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1099e1069839SBorislav Petkov 1100e1069839SBorislav Petkov #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1101e1069839SBorislav Petkov #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1102e1069839SBorislav Petkov #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1103e1069839SBorislav Petkov 1104e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_extra_regs 1105e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1106e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1107e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1108e1069839SBorislav Petkov { 1109e1069839SBorislav Petkov [ C(LL ) ] = { 1110e1069839SBorislav Petkov [ C(OP_READ) ] = { 1111e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1112e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1113e1069839SBorislav Petkov }, 1114e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1115e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1116e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1117e1069839SBorislav Petkov }, 1118e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1119e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1120e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1121e1069839SBorislav Petkov }, 1122e1069839SBorislav Petkov }, 1123e1069839SBorislav Petkov [ C(NODE) ] = { 1124e1069839SBorislav Petkov [ C(OP_READ) ] = { 1125e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1126e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1127e1069839SBorislav Petkov }, 1128e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1129e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1130e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1131e1069839SBorislav Petkov }, 1132e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1133e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1134e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1135e1069839SBorislav Petkov }, 1136e1069839SBorislav Petkov }, 1137e1069839SBorislav Petkov }; 1138e1069839SBorislav Petkov 1139e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_event_ids 1140e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1141e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1142e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1143e1069839SBorislav Petkov { 1144e1069839SBorislav Petkov [ C(L1D) ] = { 1145e1069839SBorislav Petkov [ C(OP_READ) ] = { 1146e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1147e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1148e1069839SBorislav Petkov }, 1149e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1150e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1151e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1152e1069839SBorislav Petkov }, 1153e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1154e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1155e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1156e1069839SBorislav Petkov }, 1157e1069839SBorislav Petkov }, 1158e1069839SBorislav Petkov [ C(L1I ) ] = { 1159e1069839SBorislav Petkov [ C(OP_READ) ] = { 1160e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1161e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1162e1069839SBorislav Petkov }, 1163e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1164e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1165e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1166e1069839SBorislav Petkov }, 1167e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1168e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1169e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1170e1069839SBorislav Petkov }, 1171e1069839SBorislav Petkov }, 1172e1069839SBorislav Petkov [ C(LL ) ] = { 1173e1069839SBorislav Petkov [ C(OP_READ) ] = { 1174e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1175e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1176e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1177e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1178e1069839SBorislav Petkov }, 1179e1069839SBorislav Petkov /* 1180e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1181e1069839SBorislav Petkov * on RFO. 1182e1069839SBorislav Petkov */ 1183e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1184e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1185e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1186e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1187e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1188e1069839SBorislav Petkov }, 1189e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1190e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1191e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1192e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1193e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1194e1069839SBorislav Petkov }, 1195e1069839SBorislav Petkov }, 1196e1069839SBorislav Petkov [ C(DTLB) ] = { 1197e1069839SBorislav Petkov [ C(OP_READ) ] = { 1198e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1199e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1200e1069839SBorislav Petkov }, 1201e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1202e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1203e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1204e1069839SBorislav Petkov }, 1205e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1206e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1207e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1208e1069839SBorislav Petkov }, 1209e1069839SBorislav Petkov }, 1210e1069839SBorislav Petkov [ C(ITLB) ] = { 1211e1069839SBorislav Petkov [ C(OP_READ) ] = { 1212e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1213e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1214e1069839SBorislav Petkov }, 1215e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1216e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1217e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1218e1069839SBorislav Petkov }, 1219e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1220e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1221e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1222e1069839SBorislav Petkov }, 1223e1069839SBorislav Petkov }, 1224e1069839SBorislav Petkov [ C(BPU ) ] = { 1225e1069839SBorislav Petkov [ C(OP_READ) ] = { 1226e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1227e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1228e1069839SBorislav Petkov }, 1229e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1230e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1231e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1232e1069839SBorislav Petkov }, 1233e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1234e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1235e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1236e1069839SBorislav Petkov }, 1237e1069839SBorislav Petkov }, 1238e1069839SBorislav Petkov [ C(NODE) ] = { 1239e1069839SBorislav Petkov [ C(OP_READ) ] = { 1240e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1241e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1242e1069839SBorislav Petkov }, 1243e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1244e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1245e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1246e1069839SBorislav Petkov }, 1247e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1248e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1249e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1250e1069839SBorislav Petkov }, 1251e1069839SBorislav Petkov }, 1252e1069839SBorislav Petkov }; 1253e1069839SBorislav Petkov 1254e1069839SBorislav Petkov static __initconst const u64 core2_hw_cache_event_ids 1255e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1256e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1257e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1258e1069839SBorislav Petkov { 1259e1069839SBorislav Petkov [ C(L1D) ] = { 1260e1069839SBorislav Petkov [ C(OP_READ) ] = { 1261e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1262e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1263e1069839SBorislav Petkov }, 1264e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1265e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1266e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1267e1069839SBorislav Petkov }, 1268e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1269e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1270e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1271e1069839SBorislav Petkov }, 1272e1069839SBorislav Petkov }, 1273e1069839SBorislav Petkov [ C(L1I ) ] = { 1274e1069839SBorislav Petkov [ C(OP_READ) ] = { 1275e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1276e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1277e1069839SBorislav Petkov }, 1278e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1279e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1280e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1281e1069839SBorislav Petkov }, 1282e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1283e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1284e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1285e1069839SBorislav Petkov }, 1286e1069839SBorislav Petkov }, 1287e1069839SBorislav Petkov [ C(LL ) ] = { 1288e1069839SBorislav Petkov [ C(OP_READ) ] = { 1289e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1290e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1291e1069839SBorislav Petkov }, 1292e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1293e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1294e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1295e1069839SBorislav Petkov }, 1296e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1297e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1298e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1299e1069839SBorislav Petkov }, 1300e1069839SBorislav Petkov }, 1301e1069839SBorislav Petkov [ C(DTLB) ] = { 1302e1069839SBorislav Petkov [ C(OP_READ) ] = { 1303e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1304e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1305e1069839SBorislav Petkov }, 1306e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1307e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1308e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1309e1069839SBorislav Petkov }, 1310e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1311e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1312e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1313e1069839SBorislav Petkov }, 1314e1069839SBorislav Petkov }, 1315e1069839SBorislav Petkov [ C(ITLB) ] = { 1316e1069839SBorislav Petkov [ C(OP_READ) ] = { 1317e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1318e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1319e1069839SBorislav Petkov }, 1320e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1321e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1322e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1323e1069839SBorislav Petkov }, 1324e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1325e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1326e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1327e1069839SBorislav Petkov }, 1328e1069839SBorislav Petkov }, 1329e1069839SBorislav Petkov [ C(BPU ) ] = { 1330e1069839SBorislav Petkov [ C(OP_READ) ] = { 1331e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1332e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1333e1069839SBorislav Petkov }, 1334e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1335e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1336e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1337e1069839SBorislav Petkov }, 1338e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1339e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1340e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1341e1069839SBorislav Petkov }, 1342e1069839SBorislav Petkov }, 1343e1069839SBorislav Petkov }; 1344e1069839SBorislav Petkov 1345e1069839SBorislav Petkov static __initconst const u64 atom_hw_cache_event_ids 1346e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1347e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1348e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1349e1069839SBorislav Petkov { 1350e1069839SBorislav Petkov [ C(L1D) ] = { 1351e1069839SBorislav Petkov [ C(OP_READ) ] = { 1352e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1353e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1354e1069839SBorislav Petkov }, 1355e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1356e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1357e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1358e1069839SBorislav Petkov }, 1359e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1360e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1361e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1362e1069839SBorislav Petkov }, 1363e1069839SBorislav Petkov }, 1364e1069839SBorislav Petkov [ C(L1I ) ] = { 1365e1069839SBorislav Petkov [ C(OP_READ) ] = { 1366e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1367e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1368e1069839SBorislav Petkov }, 1369e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1370e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1371e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1372e1069839SBorislav Petkov }, 1373e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1374e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1375e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1376e1069839SBorislav Petkov }, 1377e1069839SBorislav Petkov }, 1378e1069839SBorislav Petkov [ C(LL ) ] = { 1379e1069839SBorislav Petkov [ C(OP_READ) ] = { 1380e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1381e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1382e1069839SBorislav Petkov }, 1383e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1384e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1385e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1386e1069839SBorislav Petkov }, 1387e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1388e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1389e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1390e1069839SBorislav Petkov }, 1391e1069839SBorislav Petkov }, 1392e1069839SBorislav Petkov [ C(DTLB) ] = { 1393e1069839SBorislav Petkov [ C(OP_READ) ] = { 1394e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1395e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1396e1069839SBorislav Petkov }, 1397e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1398e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1399e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1400e1069839SBorislav Petkov }, 1401e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1402e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1403e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1404e1069839SBorislav Petkov }, 1405e1069839SBorislav Petkov }, 1406e1069839SBorislav Petkov [ C(ITLB) ] = { 1407e1069839SBorislav Petkov [ C(OP_READ) ] = { 1408e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1409e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1410e1069839SBorislav Petkov }, 1411e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1412e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1413e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1414e1069839SBorislav Petkov }, 1415e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1416e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1417e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1418e1069839SBorislav Petkov }, 1419e1069839SBorislav Petkov }, 1420e1069839SBorislav Petkov [ C(BPU ) ] = { 1421e1069839SBorislav Petkov [ C(OP_READ) ] = { 1422e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1423e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1424e1069839SBorislav Petkov }, 1425e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1426e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1427e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1428e1069839SBorislav Petkov }, 1429e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1430e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1431e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1432e1069839SBorislav Petkov }, 1433e1069839SBorislav Petkov }, 1434e1069839SBorislav Petkov }; 1435e1069839SBorislav Petkov 1436eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1437eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1438eb12b8ecSAndi Kleen /* no_alloc_cycles.not_delivered */ 1439eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1440eb12b8ecSAndi Kleen "event=0xca,umask=0x50"); 1441eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1442eb12b8ecSAndi Kleen /* uops_retired.all */ 1443eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1444eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1445eb12b8ecSAndi Kleen /* uops_retired.all */ 1446eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1447eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1448eb12b8ecSAndi Kleen 1449eb12b8ecSAndi Kleen static struct attribute *slm_events_attrs[] = { 1450eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_slm), 1451eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_scale_slm), 1452eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_slm), 1453eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_scale_slm), 1454eb12b8ecSAndi Kleen EVENT_PTR(td_slots_issued_slm), 1455eb12b8ecSAndi Kleen EVENT_PTR(td_slots_retired_slm), 1456eb12b8ecSAndi Kleen NULL 1457eb12b8ecSAndi Kleen }; 1458eb12b8ecSAndi Kleen 1459e1069839SBorislav Petkov static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1460e1069839SBorislav Petkov { 1461e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1462e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1463e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1464e1069839SBorislav Petkov EVENT_EXTRA_END 1465e1069839SBorislav Petkov }; 1466e1069839SBorislav Petkov 1467e1069839SBorislav Petkov #define SLM_DMND_READ SNB_DMND_DATA_RD 1468e1069839SBorislav Petkov #define SLM_DMND_WRITE SNB_DMND_RFO 1469e1069839SBorislav Petkov #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1470e1069839SBorislav Petkov 1471e1069839SBorislav Petkov #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1472e1069839SBorislav Petkov #define SLM_LLC_ACCESS SNB_RESP_ANY 1473e1069839SBorislav Petkov #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1474e1069839SBorislav Petkov 1475e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_extra_regs 1476e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1477e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1478e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1479e1069839SBorislav Petkov { 1480e1069839SBorislav Petkov [ C(LL ) ] = { 1481e1069839SBorislav Petkov [ C(OP_READ) ] = { 1482e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1483e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1484e1069839SBorislav Petkov }, 1485e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1486e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1487e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1488e1069839SBorislav Petkov }, 1489e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1490e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1491e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1492e1069839SBorislav Petkov }, 1493e1069839SBorislav Petkov }, 1494e1069839SBorislav Petkov }; 1495e1069839SBorislav Petkov 1496e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_event_ids 1497e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1498e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1499e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1500e1069839SBorislav Petkov { 1501e1069839SBorislav Petkov [ C(L1D) ] = { 1502e1069839SBorislav Petkov [ C(OP_READ) ] = { 1503e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1504e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1505e1069839SBorislav Petkov }, 1506e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1507e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1508e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1509e1069839SBorislav Petkov }, 1510e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1511e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1512e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1513e1069839SBorislav Petkov }, 1514e1069839SBorislav Petkov }, 1515e1069839SBorislav Petkov [ C(L1I ) ] = { 1516e1069839SBorislav Petkov [ C(OP_READ) ] = { 1517e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1518e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1519e1069839SBorislav Petkov }, 1520e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1521e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1522e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1523e1069839SBorislav Petkov }, 1524e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1525e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1526e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1527e1069839SBorislav Petkov }, 1528e1069839SBorislav Petkov }, 1529e1069839SBorislav Petkov [ C(LL ) ] = { 1530e1069839SBorislav Petkov [ C(OP_READ) ] = { 1531e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1532e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1533e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1534e1069839SBorislav Petkov }, 1535e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1536e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1537e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1538e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1539e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1540e1069839SBorislav Petkov }, 1541e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1542e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1543e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1544e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1545e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1546e1069839SBorislav Petkov }, 1547e1069839SBorislav Petkov }, 1548e1069839SBorislav Petkov [ C(DTLB) ] = { 1549e1069839SBorislav Petkov [ C(OP_READ) ] = { 1550e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1551e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1552e1069839SBorislav Petkov }, 1553e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1554e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1555e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1556e1069839SBorislav Petkov }, 1557e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1558e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1559e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1560e1069839SBorislav Petkov }, 1561e1069839SBorislav Petkov }, 1562e1069839SBorislav Petkov [ C(ITLB) ] = { 1563e1069839SBorislav Petkov [ C(OP_READ) ] = { 1564e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1565e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1566e1069839SBorislav Petkov }, 1567e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1568e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1569e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1570e1069839SBorislav Petkov }, 1571e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1572e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1573e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1574e1069839SBorislav Petkov }, 1575e1069839SBorislav Petkov }, 1576e1069839SBorislav Petkov [ C(BPU ) ] = { 1577e1069839SBorislav Petkov [ C(OP_READ) ] = { 1578e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1579e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1580e1069839SBorislav Petkov }, 1581e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1582e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1583e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1584e1069839SBorislav Petkov }, 1585e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1586e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1587e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1588e1069839SBorislav Petkov }, 1589e1069839SBorislav Petkov }, 1590e1069839SBorislav Petkov }; 1591e1069839SBorislav Petkov 1592ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1593ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1594ed827adbSKan Liang /* UOPS_NOT_DELIVERED.ANY */ 1595ed827adbSKan Liang EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1596ed827adbSKan Liang /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1597ed827adbSKan Liang EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1598ed827adbSKan Liang /* UOPS_RETIRED.ANY */ 1599ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1600ed827adbSKan Liang /* UOPS_ISSUED.ANY */ 1601ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1602ed827adbSKan Liang 1603ed827adbSKan Liang static struct attribute *glm_events_attrs[] = { 1604ed827adbSKan Liang EVENT_PTR(td_total_slots_glm), 1605ed827adbSKan Liang EVENT_PTR(td_total_slots_scale_glm), 1606ed827adbSKan Liang EVENT_PTR(td_fetch_bubbles_glm), 1607ed827adbSKan Liang EVENT_PTR(td_recovery_bubbles_glm), 1608ed827adbSKan Liang EVENT_PTR(td_slots_issued_glm), 1609ed827adbSKan Liang EVENT_PTR(td_slots_retired_glm), 1610ed827adbSKan Liang NULL 1611ed827adbSKan Liang }; 1612ed827adbSKan Liang 16138b92c3a7SKan Liang static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 16148b92c3a7SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 16158b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 16168b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 16178b92c3a7SKan Liang EVENT_EXTRA_END 16188b92c3a7SKan Liang }; 16198b92c3a7SKan Liang 16208b92c3a7SKan Liang #define GLM_DEMAND_DATA_RD BIT_ULL(0) 16218b92c3a7SKan Liang #define GLM_DEMAND_RFO BIT_ULL(1) 16228b92c3a7SKan Liang #define GLM_ANY_RESPONSE BIT_ULL(16) 16238b92c3a7SKan Liang #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 16248b92c3a7SKan Liang #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 16258b92c3a7SKan Liang #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 16268b92c3a7SKan Liang #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 16278b92c3a7SKan Liang #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 16288b92c3a7SKan Liang #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 16298b92c3a7SKan Liang #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 16308b92c3a7SKan Liang 16318b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_event_ids 16328b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 16338b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 16348b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 16358b92c3a7SKan Liang [C(L1D)] = { 16368b92c3a7SKan Liang [C(OP_READ)] = { 16378b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16388b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16398b92c3a7SKan Liang }, 16408b92c3a7SKan Liang [C(OP_WRITE)] = { 16418b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16428b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16438b92c3a7SKan Liang }, 16448b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16458b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16468b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16478b92c3a7SKan Liang }, 16488b92c3a7SKan Liang }, 16498b92c3a7SKan Liang [C(L1I)] = { 16508b92c3a7SKan Liang [C(OP_READ)] = { 16518b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 16528b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 16538b92c3a7SKan Liang }, 16548b92c3a7SKan Liang [C(OP_WRITE)] = { 16558b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16568b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16578b92c3a7SKan Liang }, 16588b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16598b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16608b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16618b92c3a7SKan Liang }, 16628b92c3a7SKan Liang }, 16638b92c3a7SKan Liang [C(LL)] = { 16648b92c3a7SKan Liang [C(OP_READ)] = { 16658b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16668b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16678b92c3a7SKan Liang }, 16688b92c3a7SKan Liang [C(OP_WRITE)] = { 16698b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16708b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16718b92c3a7SKan Liang }, 16728b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16738b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16748b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16758b92c3a7SKan Liang }, 16768b92c3a7SKan Liang }, 16778b92c3a7SKan Liang [C(DTLB)] = { 16788b92c3a7SKan Liang [C(OP_READ)] = { 16798b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16808b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16818b92c3a7SKan Liang }, 16828b92c3a7SKan Liang [C(OP_WRITE)] = { 16838b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16848b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16858b92c3a7SKan Liang }, 16868b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16878b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16888b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16898b92c3a7SKan Liang }, 16908b92c3a7SKan Liang }, 16918b92c3a7SKan Liang [C(ITLB)] = { 16928b92c3a7SKan Liang [C(OP_READ)] = { 16938b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 16948b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 16958b92c3a7SKan Liang }, 16968b92c3a7SKan Liang [C(OP_WRITE)] = { 16978b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16988b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16998b92c3a7SKan Liang }, 17008b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17018b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17028b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17038b92c3a7SKan Liang }, 17048b92c3a7SKan Liang }, 17058b92c3a7SKan Liang [C(BPU)] = { 17068b92c3a7SKan Liang [C(OP_READ)] = { 17078b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 17088b92c3a7SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 17098b92c3a7SKan Liang }, 17108b92c3a7SKan Liang [C(OP_WRITE)] = { 17118b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17128b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17138b92c3a7SKan Liang }, 17148b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17158b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17168b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17178b92c3a7SKan Liang }, 17188b92c3a7SKan Liang }, 17198b92c3a7SKan Liang }; 17208b92c3a7SKan Liang 17218b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_extra_regs 17228b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 17238b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 17248b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 17258b92c3a7SKan Liang [C(LL)] = { 17268b92c3a7SKan Liang [C(OP_READ)] = { 17278b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 17288b92c3a7SKan Liang GLM_LLC_ACCESS, 17298b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 17308b92c3a7SKan Liang GLM_LLC_MISS, 17318b92c3a7SKan Liang }, 17328b92c3a7SKan Liang [C(OP_WRITE)] = { 17338b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 17348b92c3a7SKan Liang GLM_LLC_ACCESS, 17358b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 17368b92c3a7SKan Liang GLM_LLC_MISS, 17378b92c3a7SKan Liang }, 17388b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17398b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 17408b92c3a7SKan Liang GLM_LLC_ACCESS, 17418b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 17428b92c3a7SKan Liang GLM_LLC_MISS, 17438b92c3a7SKan Liang }, 17448b92c3a7SKan Liang }, 17458b92c3a7SKan Liang }; 17468b92c3a7SKan Liang 1747dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_event_ids 1748dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1749dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1750dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1751dd0b06b5SKan Liang [C(L1D)] = { 1752dd0b06b5SKan Liang [C(OP_READ)] = { 1753dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1754dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1755dd0b06b5SKan Liang }, 1756dd0b06b5SKan Liang [C(OP_WRITE)] = { 1757dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1758dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1759dd0b06b5SKan Liang }, 1760dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1761dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1762dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1763dd0b06b5SKan Liang }, 1764dd0b06b5SKan Liang }, 1765dd0b06b5SKan Liang [C(L1I)] = { 1766dd0b06b5SKan Liang [C(OP_READ)] = { 1767dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1768dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1769dd0b06b5SKan Liang }, 1770dd0b06b5SKan Liang [C(OP_WRITE)] = { 1771dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1772dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1773dd0b06b5SKan Liang }, 1774dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1775dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1776dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1777dd0b06b5SKan Liang }, 1778dd0b06b5SKan Liang }, 1779dd0b06b5SKan Liang [C(LL)] = { 1780dd0b06b5SKan Liang [C(OP_READ)] = { 1781dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1782dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1783dd0b06b5SKan Liang }, 1784dd0b06b5SKan Liang [C(OP_WRITE)] = { 1785dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1786dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1787dd0b06b5SKan Liang }, 1788dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1789dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1790dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1791dd0b06b5SKan Liang }, 1792dd0b06b5SKan Liang }, 1793dd0b06b5SKan Liang [C(DTLB)] = { 1794dd0b06b5SKan Liang [C(OP_READ)] = { 1795dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1796dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1797dd0b06b5SKan Liang }, 1798dd0b06b5SKan Liang [C(OP_WRITE)] = { 1799dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1800dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1801dd0b06b5SKan Liang }, 1802dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1803dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1804dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1805dd0b06b5SKan Liang }, 1806dd0b06b5SKan Liang }, 1807dd0b06b5SKan Liang [C(ITLB)] = { 1808dd0b06b5SKan Liang [C(OP_READ)] = { 1809dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1810dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1811dd0b06b5SKan Liang }, 1812dd0b06b5SKan Liang [C(OP_WRITE)] = { 1813dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1814dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1815dd0b06b5SKan Liang }, 1816dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1817dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1818dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1819dd0b06b5SKan Liang }, 1820dd0b06b5SKan Liang }, 1821dd0b06b5SKan Liang [C(BPU)] = { 1822dd0b06b5SKan Liang [C(OP_READ)] = { 1823dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1824dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1825dd0b06b5SKan Liang }, 1826dd0b06b5SKan Liang [C(OP_WRITE)] = { 1827dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1828dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1829dd0b06b5SKan Liang }, 1830dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1831dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1832dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1833dd0b06b5SKan Liang }, 1834dd0b06b5SKan Liang }, 1835dd0b06b5SKan Liang }; 1836dd0b06b5SKan Liang 1837dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_extra_regs 1838dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1839dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1840dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1841dd0b06b5SKan Liang [C(LL)] = { 1842dd0b06b5SKan Liang [C(OP_READ)] = { 1843dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1844dd0b06b5SKan Liang GLM_LLC_ACCESS, 1845dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 1846dd0b06b5SKan Liang GLM_LLC_MISS, 1847dd0b06b5SKan Liang }, 1848dd0b06b5SKan Liang [C(OP_WRITE)] = { 1849dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1850dd0b06b5SKan Liang GLM_LLC_ACCESS, 1851dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1852dd0b06b5SKan Liang GLM_LLC_MISS, 1853dd0b06b5SKan Liang }, 1854dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1855dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1856dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1857dd0b06b5SKan Liang }, 1858dd0b06b5SKan Liang }, 1859dd0b06b5SKan Liang }; 1860dd0b06b5SKan Liang 18616daeb873SKan Liang #define TNT_LOCAL_DRAM BIT_ULL(26) 18626daeb873SKan Liang #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 18636daeb873SKan Liang #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 18646daeb873SKan Liang #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 18656daeb873SKan Liang #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 18666daeb873SKan Liang SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 18676daeb873SKan Liang #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 18686daeb873SKan Liang 18696daeb873SKan Liang static __initconst const u64 tnt_hw_cache_extra_regs 18706daeb873SKan Liang [PERF_COUNT_HW_CACHE_MAX] 18716daeb873SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 18726daeb873SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 18736daeb873SKan Liang [C(LL)] = { 18746daeb873SKan Liang [C(OP_READ)] = { 18756daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 18766daeb873SKan Liang TNT_LLC_ACCESS, 18776daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_READ| 18786daeb873SKan Liang TNT_LLC_MISS, 18796daeb873SKan Liang }, 18806daeb873SKan Liang [C(OP_WRITE)] = { 18816daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 18826daeb873SKan Liang TNT_LLC_ACCESS, 18836daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 18846daeb873SKan Liang TNT_LLC_MISS, 18856daeb873SKan Liang }, 18866daeb873SKan Liang [C(OP_PREFETCH)] = { 18876daeb873SKan Liang [C(RESULT_ACCESS)] = 0x0, 18886daeb873SKan Liang [C(RESULT_MISS)] = 0x0, 18896daeb873SKan Liang }, 18906daeb873SKan Liang }, 18916daeb873SKan Liang }; 18926daeb873SKan Liang 18936daeb873SKan Liang static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 18946daeb873SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 18956daeb873SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0), 18966daeb873SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1), 18976daeb873SKan Liang EVENT_EXTRA_END 18986daeb873SKan Liang }; 18996daeb873SKan Liang 1900e1069839SBorislav Petkov #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1901e1069839SBorislav Petkov #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1902e1069839SBorislav Petkov #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1903e1069839SBorislav Petkov #define KNL_MCDRAM_FAR BIT_ULL(22) 1904e1069839SBorislav Petkov #define KNL_DDR_LOCAL BIT_ULL(23) 1905e1069839SBorislav Petkov #define KNL_DDR_FAR BIT_ULL(24) 1906e1069839SBorislav Petkov #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1907e1069839SBorislav Petkov KNL_DDR_LOCAL | KNL_DDR_FAR) 1908e1069839SBorislav Petkov #define KNL_L2_READ SLM_DMND_READ 1909e1069839SBorislav Petkov #define KNL_L2_WRITE SLM_DMND_WRITE 1910e1069839SBorislav Petkov #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1911e1069839SBorislav Petkov #define KNL_L2_ACCESS SLM_LLC_ACCESS 1912e1069839SBorislav Petkov #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1913e1069839SBorislav Petkov KNL_DRAM_ANY | SNB_SNP_ANY | \ 1914e1069839SBorislav Petkov SNB_NON_DRAM) 1915e1069839SBorislav Petkov 1916e1069839SBorislav Petkov static __initconst const u64 knl_hw_cache_extra_regs 1917e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1918e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1919e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1920e1069839SBorislav Petkov [C(LL)] = { 1921e1069839SBorislav Petkov [C(OP_READ)] = { 1922e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1923e1069839SBorislav Petkov [C(RESULT_MISS)] = 0, 1924e1069839SBorislav Petkov }, 1925e1069839SBorislav Petkov [C(OP_WRITE)] = { 1926e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1927e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1928e1069839SBorislav Petkov }, 1929e1069839SBorislav Petkov [C(OP_PREFETCH)] = { 1930e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1931e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1932e1069839SBorislav Petkov }, 1933e1069839SBorislav Petkov }, 1934e1069839SBorislav Petkov }; 1935e1069839SBorislav Petkov 1936e1069839SBorislav Petkov /* 1937c3d266c8SKan Liang * Used from PMIs where the LBRs are already disabled. 1938c3d266c8SKan Liang * 1939c3d266c8SKan Liang * This function could be called consecutively. It is required to remain in 1940c3d266c8SKan Liang * disabled state if called consecutively. 1941c3d266c8SKan Liang * 1942c3d266c8SKan Liang * During consecutive calls, the same disable value will be written to related 1943cecf6235SAlexander Shishkin * registers, so the PMU state remains unchanged. 1944cecf6235SAlexander Shishkin * 1945cecf6235SAlexander Shishkin * intel_bts events don't coexist with intel PMU's BTS events because of 1946cecf6235SAlexander Shishkin * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1947cecf6235SAlexander Shishkin * disabled around intel PMU's event batching etc, only inside the PMI handler. 1948e1069839SBorislav Petkov */ 1949e1069839SBorislav Petkov static void __intel_pmu_disable_all(void) 1950e1069839SBorislav Petkov { 1951e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1952e1069839SBorislav Petkov 1953e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1954e1069839SBorislav Petkov 1955e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1956e1069839SBorislav Petkov intel_pmu_disable_bts(); 1957e1069839SBorislav Petkov 1958e1069839SBorislav Petkov intel_pmu_pebs_disable_all(); 1959e1069839SBorislav Petkov } 1960e1069839SBorislav Petkov 1961e1069839SBorislav Petkov static void intel_pmu_disable_all(void) 1962e1069839SBorislav Petkov { 1963e1069839SBorislav Petkov __intel_pmu_disable_all(); 1964e1069839SBorislav Petkov intel_pmu_lbr_disable_all(); 1965e1069839SBorislav Petkov } 1966e1069839SBorislav Petkov 1967e1069839SBorislav Petkov static void __intel_pmu_enable_all(int added, bool pmi) 1968e1069839SBorislav Petkov { 1969e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1970e1069839SBorislav Petkov 1971e1069839SBorislav Petkov intel_pmu_pebs_enable_all(); 1972e1069839SBorislav Petkov intel_pmu_lbr_enable_all(pmi); 1973e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1974e1069839SBorislav Petkov x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1975e1069839SBorislav Petkov 1976e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1977e1069839SBorislav Petkov struct perf_event *event = 1978e1069839SBorislav Petkov cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1979e1069839SBorislav Petkov 1980e1069839SBorislav Petkov if (WARN_ON_ONCE(!event)) 1981e1069839SBorislav Petkov return; 1982e1069839SBorislav Petkov 1983e1069839SBorislav Petkov intel_pmu_enable_bts(event->hw.config); 1984cecf6235SAlexander Shishkin } 1985e1069839SBorislav Petkov } 1986e1069839SBorislav Petkov 1987e1069839SBorislav Petkov static void intel_pmu_enable_all(int added) 1988e1069839SBorislav Petkov { 1989e1069839SBorislav Petkov __intel_pmu_enable_all(added, false); 1990e1069839SBorislav Petkov } 1991e1069839SBorislav Petkov 1992e1069839SBorislav Petkov /* 1993e1069839SBorislav Petkov * Workaround for: 1994e1069839SBorislav Petkov * Intel Errata AAK100 (model 26) 1995e1069839SBorislav Petkov * Intel Errata AAP53 (model 30) 1996e1069839SBorislav Petkov * Intel Errata BD53 (model 44) 1997e1069839SBorislav Petkov * 1998e1069839SBorislav Petkov * The official story: 1999e1069839SBorislav Petkov * These chips need to be 'reset' when adding counters by programming the 2000e1069839SBorislav Petkov * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2001e1069839SBorislav Petkov * in sequence on the same PMC or on different PMCs. 2002e1069839SBorislav Petkov * 2003e1069839SBorislav Petkov * In practise it appears some of these events do in fact count, and 2004a97673a1SIngo Molnar * we need to program all 4 events. 2005e1069839SBorislav Petkov */ 2006e1069839SBorislav Petkov static void intel_pmu_nhm_workaround(void) 2007e1069839SBorislav Petkov { 2008e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2009e1069839SBorislav Petkov static const unsigned long nhm_magic[4] = { 2010e1069839SBorislav Petkov 0x4300B5, 2011e1069839SBorislav Petkov 0x4300D2, 2012e1069839SBorislav Petkov 0x4300B1, 2013e1069839SBorislav Petkov 0x4300B1 2014e1069839SBorislav Petkov }; 2015e1069839SBorislav Petkov struct perf_event *event; 2016e1069839SBorislav Petkov int i; 2017e1069839SBorislav Petkov 2018e1069839SBorislav Petkov /* 2019e1069839SBorislav Petkov * The Errata requires below steps: 2020e1069839SBorislav Petkov * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2021e1069839SBorislav Petkov * 2) Configure 4 PERFEVTSELx with the magic events and clear 2022e1069839SBorislav Petkov * the corresponding PMCx; 2023e1069839SBorislav Petkov * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2024e1069839SBorislav Petkov * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2025e1069839SBorislav Petkov * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2026e1069839SBorislav Petkov */ 2027e1069839SBorislav Petkov 2028e1069839SBorislav Petkov /* 2029e1069839SBorislav Petkov * The real steps we choose are a little different from above. 2030e1069839SBorislav Petkov * A) To reduce MSR operations, we don't run step 1) as they 2031e1069839SBorislav Petkov * are already cleared before this function is called; 2032e1069839SBorislav Petkov * B) Call x86_perf_event_update to save PMCx before configuring 2033e1069839SBorislav Petkov * PERFEVTSELx with magic number; 2034e1069839SBorislav Petkov * C) With step 5), we do clear only when the PERFEVTSELx is 2035e1069839SBorislav Petkov * not used currently. 2036e1069839SBorislav Petkov * D) Call x86_perf_event_set_period to restore PMCx; 2037e1069839SBorislav Petkov */ 2038e1069839SBorislav Petkov 2039e1069839SBorislav Petkov /* We always operate 4 pairs of PERF Counters */ 2040e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2041e1069839SBorislav Petkov event = cpuc->events[i]; 2042e1069839SBorislav Petkov if (event) 2043e1069839SBorislav Petkov x86_perf_event_update(event); 2044e1069839SBorislav Petkov } 2045e1069839SBorislav Petkov 2046e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2047e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2048e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2049e1069839SBorislav Petkov } 2050e1069839SBorislav Petkov 2051e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2052e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2053e1069839SBorislav Petkov 2054e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2055e1069839SBorislav Petkov event = cpuc->events[i]; 2056e1069839SBorislav Petkov 2057e1069839SBorislav Petkov if (event) { 2058e1069839SBorislav Petkov x86_perf_event_set_period(event); 2059e1069839SBorislav Petkov __x86_pmu_enable_event(&event->hw, 2060e1069839SBorislav Petkov ARCH_PERFMON_EVENTSEL_ENABLE); 2061e1069839SBorislav Petkov } else 2062e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2063e1069839SBorislav Petkov } 2064e1069839SBorislav Petkov } 2065e1069839SBorislav Petkov 2066e1069839SBorislav Petkov static void intel_pmu_nhm_enable_all(int added) 2067e1069839SBorislav Petkov { 2068e1069839SBorislav Petkov if (added) 2069e1069839SBorislav Petkov intel_pmu_nhm_workaround(); 2070e1069839SBorislav Petkov intel_pmu_enable_all(added); 2071e1069839SBorislav Petkov } 2072e1069839SBorislav Petkov 2073400816f6SPeter Zijlstra (Intel) static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2074400816f6SPeter Zijlstra (Intel) { 2075400816f6SPeter Zijlstra (Intel) u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2076400816f6SPeter Zijlstra (Intel) 2077400816f6SPeter Zijlstra (Intel) if (cpuc->tfa_shadow != val) { 2078400816f6SPeter Zijlstra (Intel) cpuc->tfa_shadow = val; 2079400816f6SPeter Zijlstra (Intel) wrmsrl(MSR_TSX_FORCE_ABORT, val); 2080400816f6SPeter Zijlstra (Intel) } 2081400816f6SPeter Zijlstra (Intel) } 2082400816f6SPeter Zijlstra (Intel) 2083400816f6SPeter Zijlstra (Intel) static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2084400816f6SPeter Zijlstra (Intel) { 2085400816f6SPeter Zijlstra (Intel) /* 2086400816f6SPeter Zijlstra (Intel) * We're going to use PMC3, make sure TFA is set before we touch it. 2087400816f6SPeter Zijlstra (Intel) */ 20881a81542aSPeter Zijlstra if (cntr == 3) 2089400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, true); 2090400816f6SPeter Zijlstra (Intel) } 2091400816f6SPeter Zijlstra (Intel) 2092400816f6SPeter Zijlstra (Intel) static void intel_tfa_pmu_enable_all(int added) 2093400816f6SPeter Zijlstra (Intel) { 2094400816f6SPeter Zijlstra (Intel) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2095400816f6SPeter Zijlstra (Intel) 2096400816f6SPeter Zijlstra (Intel) /* 2097400816f6SPeter Zijlstra (Intel) * If we find PMC3 is no longer used when we enable the PMU, we can 2098400816f6SPeter Zijlstra (Intel) * clear TFA. 2099400816f6SPeter Zijlstra (Intel) */ 2100400816f6SPeter Zijlstra (Intel) if (!test_bit(3, cpuc->active_mask)) 2101400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, false); 2102400816f6SPeter Zijlstra (Intel) 2103400816f6SPeter Zijlstra (Intel) intel_pmu_enable_all(added); 2104400816f6SPeter Zijlstra (Intel) } 2105400816f6SPeter Zijlstra (Intel) 2106af3bdb99SAndi Kleen static void enable_counter_freeze(void) 2107af3bdb99SAndi Kleen { 2108af3bdb99SAndi Kleen update_debugctlmsr(get_debugctlmsr() | 2109af3bdb99SAndi Kleen DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2110af3bdb99SAndi Kleen } 2111af3bdb99SAndi Kleen 2112af3bdb99SAndi Kleen static void disable_counter_freeze(void) 2113af3bdb99SAndi Kleen { 2114af3bdb99SAndi Kleen update_debugctlmsr(get_debugctlmsr() & 2115af3bdb99SAndi Kleen ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2116af3bdb99SAndi Kleen } 2117af3bdb99SAndi Kleen 2118e1069839SBorislav Petkov static inline u64 intel_pmu_get_status(void) 2119e1069839SBorislav Petkov { 2120e1069839SBorislav Petkov u64 status; 2121e1069839SBorislav Petkov 2122e1069839SBorislav Petkov rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2123e1069839SBorislav Petkov 2124e1069839SBorislav Petkov return status; 2125e1069839SBorislav Petkov } 2126e1069839SBorislav Petkov 2127e1069839SBorislav Petkov static inline void intel_pmu_ack_status(u64 ack) 2128e1069839SBorislav Petkov { 2129e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2130e1069839SBorislav Petkov } 2131e1069839SBorislav Petkov 2132e1069839SBorislav Petkov static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 2133e1069839SBorislav Petkov { 2134e1069839SBorislav Petkov int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 2135e1069839SBorislav Petkov u64 ctrl_val, mask; 2136e1069839SBorislav Petkov 2137e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2138e1069839SBorislav Petkov 2139e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2140e1069839SBorislav Petkov ctrl_val &= ~mask; 2141e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2142e1069839SBorislav Petkov } 2143e1069839SBorislav Petkov 2144e1069839SBorislav Petkov static inline bool event_is_checkpointed(struct perf_event *event) 2145e1069839SBorislav Petkov { 2146e1069839SBorislav Petkov return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2147e1069839SBorislav Petkov } 2148e1069839SBorislav Petkov 2149e1069839SBorislav Petkov static void intel_pmu_disable_event(struct perf_event *event) 2150e1069839SBorislav Petkov { 2151e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2152e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2153e1069839SBorislav Petkov 2154e1069839SBorislav Petkov if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2155e1069839SBorislav Petkov intel_pmu_disable_bts(); 2156e1069839SBorislav Petkov intel_pmu_drain_bts_buffer(); 2157e1069839SBorislav Petkov return; 2158e1069839SBorislav Petkov } 2159e1069839SBorislav Petkov 2160e1069839SBorislav Petkov cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); 2161e1069839SBorislav Petkov cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); 2162e1069839SBorislav Petkov cpuc->intel_cp_status &= ~(1ull << hwc->idx); 2163e1069839SBorislav Petkov 2164e4557c1aSKan Liang if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) 2165e1069839SBorislav Petkov intel_pmu_disable_fixed(hwc); 2166e4557c1aSKan Liang else 2167e1069839SBorislav Petkov x86_pmu_disable_event(event); 21686f55967aSJiri Olsa 21696f55967aSJiri Olsa /* 21706f55967aSJiri Olsa * Needs to be called after x86_pmu_disable_event, 21716f55967aSJiri Olsa * so we don't trigger the event without PEBS bit set. 21726f55967aSJiri Olsa */ 21736f55967aSJiri Olsa if (unlikely(event->attr.precise_ip)) 21746f55967aSJiri Olsa intel_pmu_pebs_disable(event); 2175e1069839SBorislav Petkov } 2176e1069839SBorislav Petkov 217768f7082fSPeter Zijlstra static void intel_pmu_del_event(struct perf_event *event) 217868f7082fSPeter Zijlstra { 217968f7082fSPeter Zijlstra if (needs_branch_stack(event)) 218068f7082fSPeter Zijlstra intel_pmu_lbr_del(event); 218168f7082fSPeter Zijlstra if (event->attr.precise_ip) 218268f7082fSPeter Zijlstra intel_pmu_pebs_del(event); 218368f7082fSPeter Zijlstra } 218468f7082fSPeter Zijlstra 2185ceb90d9eSKan Liang static void intel_pmu_read_event(struct perf_event *event) 2186ceb90d9eSKan Liang { 2187ceb90d9eSKan Liang if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2188ceb90d9eSKan Liang intel_pmu_auto_reload_read(event); 2189ceb90d9eSKan Liang else 2190ceb90d9eSKan Liang x86_perf_event_update(event); 2191ceb90d9eSKan Liang } 2192ceb90d9eSKan Liang 21934f08b625SKan Liang static void intel_pmu_enable_fixed(struct perf_event *event) 2194e1069839SBorislav Petkov { 21954f08b625SKan Liang struct hw_perf_event *hwc = &event->hw; 2196e1069839SBorislav Petkov int idx = hwc->idx - INTEL_PMC_IDX_FIXED; 21974f08b625SKan Liang u64 ctrl_val, mask, bits = 0; 2198e1069839SBorislav Petkov 2199e1069839SBorislav Petkov /* 22004f08b625SKan Liang * Enable IRQ generation (0x8), if not PEBS, 2201e1069839SBorislav Petkov * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2202e1069839SBorislav Petkov * if requested: 2203e1069839SBorislav Petkov */ 22044f08b625SKan Liang if (!event->attr.precise_ip) 22054f08b625SKan Liang bits |= 0x8; 2206e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2207e1069839SBorislav Petkov bits |= 0x2; 2208e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2209e1069839SBorislav Petkov bits |= 0x1; 2210e1069839SBorislav Petkov 2211e1069839SBorislav Petkov /* 2212e1069839SBorislav Petkov * ANY bit is supported in v3 and up 2213e1069839SBorislav Petkov */ 2214e1069839SBorislav Petkov if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2215e1069839SBorislav Petkov bits |= 0x4; 2216e1069839SBorislav Petkov 2217e1069839SBorislav Petkov bits <<= (idx * 4); 2218e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2219e1069839SBorislav Petkov 2220c22497f5SKan Liang if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2221c22497f5SKan Liang bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2222c22497f5SKan Liang mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2223c22497f5SKan Liang } 2224c22497f5SKan Liang 2225e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2226e1069839SBorislav Petkov ctrl_val &= ~mask; 2227e1069839SBorislav Petkov ctrl_val |= bits; 2228e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2229e1069839SBorislav Petkov } 2230e1069839SBorislav Petkov 2231e1069839SBorislav Petkov static void intel_pmu_enable_event(struct perf_event *event) 2232e1069839SBorislav Petkov { 2233e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2234e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2235e1069839SBorislav Petkov 2236e1069839SBorislav Petkov if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { 2237e1069839SBorislav Petkov if (!__this_cpu_read(cpu_hw_events.enabled)) 2238e1069839SBorislav Petkov return; 2239e1069839SBorislav Petkov 2240e1069839SBorislav Petkov intel_pmu_enable_bts(hwc->config); 2241e1069839SBorislav Petkov return; 2242e1069839SBorislav Petkov } 2243e1069839SBorislav Petkov 2244e1069839SBorislav Petkov if (event->attr.exclude_host) 2245e1069839SBorislav Petkov cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); 2246e1069839SBorislav Petkov if (event->attr.exclude_guest) 2247e1069839SBorislav Petkov cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); 2248e1069839SBorislav Petkov 2249e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) 2250e1069839SBorislav Petkov cpuc->intel_cp_status |= (1ull << hwc->idx); 2251e1069839SBorislav Petkov 2252e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2253e1069839SBorislav Petkov intel_pmu_pebs_enable(event); 2254e1069839SBorislav Petkov 22554f08b625SKan Liang if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { 22564f08b625SKan Liang intel_pmu_enable_fixed(event); 22574f08b625SKan Liang return; 22584f08b625SKan Liang } 22594f08b625SKan Liang 2260e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2261e1069839SBorislav Petkov } 2262e1069839SBorislav Petkov 226368f7082fSPeter Zijlstra static void intel_pmu_add_event(struct perf_event *event) 226468f7082fSPeter Zijlstra { 226568f7082fSPeter Zijlstra if (event->attr.precise_ip) 226668f7082fSPeter Zijlstra intel_pmu_pebs_add(event); 226768f7082fSPeter Zijlstra if (needs_branch_stack(event)) 226868f7082fSPeter Zijlstra intel_pmu_lbr_add(event); 226968f7082fSPeter Zijlstra } 227068f7082fSPeter Zijlstra 2271e1069839SBorislav Petkov /* 2272e1069839SBorislav Petkov * Save and restart an expired event. Called by NMI contexts, 2273e1069839SBorislav Petkov * so it has to be careful about preempting normal event ops: 2274e1069839SBorislav Petkov */ 2275e1069839SBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event) 2276e1069839SBorislav Petkov { 2277e1069839SBorislav Petkov x86_perf_event_update(event); 2278e1069839SBorislav Petkov /* 2279e1069839SBorislav Petkov * For a checkpointed counter always reset back to 0. This 2280e1069839SBorislav Petkov * avoids a situation where the counter overflows, aborts the 2281e1069839SBorislav Petkov * transaction and is then set back to shortly before the 2282e1069839SBorislav Petkov * overflow, and overflows and aborts again. 2283e1069839SBorislav Petkov */ 2284e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) { 2285e1069839SBorislav Petkov /* No race with NMIs because the counter should not be armed */ 2286e1069839SBorislav Petkov wrmsrl(event->hw.event_base, 0); 2287e1069839SBorislav Petkov local64_set(&event->hw.prev_count, 0); 2288e1069839SBorislav Petkov } 2289e1069839SBorislav Petkov return x86_perf_event_set_period(event); 2290e1069839SBorislav Petkov } 2291e1069839SBorislav Petkov 2292e1069839SBorislav Petkov static void intel_pmu_reset(void) 2293e1069839SBorislav Petkov { 2294e1069839SBorislav Petkov struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2295e1069839SBorislav Petkov unsigned long flags; 2296e1069839SBorislav Petkov int idx; 2297e1069839SBorislav Petkov 2298e1069839SBorislav Petkov if (!x86_pmu.num_counters) 2299e1069839SBorislav Petkov return; 2300e1069839SBorislav Petkov 2301e1069839SBorislav Petkov local_irq_save(flags); 2302e1069839SBorislav Petkov 2303e1069839SBorislav Petkov pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2304e1069839SBorislav Petkov 2305e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2306e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2307e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2308e1069839SBorislav Petkov } 2309e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2310e1069839SBorislav Petkov wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2311e1069839SBorislav Petkov 2312e1069839SBorislav Petkov if (ds) 2313e1069839SBorislav Petkov ds->bts_index = ds->bts_buffer_base; 2314e1069839SBorislav Petkov 2315e1069839SBorislav Petkov /* Ack all overflows and disable fixed counters */ 2316e1069839SBorislav Petkov if (x86_pmu.version >= 2) { 2317e1069839SBorislav Petkov intel_pmu_ack_status(intel_pmu_get_status()); 2318e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2319e1069839SBorislav Petkov } 2320e1069839SBorislav Petkov 2321e1069839SBorislav Petkov /* Reset LBRs and LBR freezing */ 2322e1069839SBorislav Petkov if (x86_pmu.lbr_nr) { 2323e1069839SBorislav Petkov update_debugctlmsr(get_debugctlmsr() & 2324e1069839SBorislav Petkov ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2325e1069839SBorislav Petkov } 2326e1069839SBorislav Petkov 2327e1069839SBorislav Petkov local_irq_restore(flags); 2328e1069839SBorislav Petkov } 2329e1069839SBorislav Petkov 2330ba12d20eSKan Liang static int handle_pmi_common(struct pt_regs *regs, u64 status) 2331e1069839SBorislav Petkov { 2332e1069839SBorislav Petkov struct perf_sample_data data; 2333ba12d20eSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2334ba12d20eSKan Liang int bit; 2335ba12d20eSKan Liang int handled = 0; 2336e1069839SBorislav Petkov 2337e1069839SBorislav Petkov inc_irq_stat(apic_perf_irqs); 2338e1069839SBorislav Petkov 2339e1069839SBorislav Petkov /* 2340e1069839SBorislav Petkov * Ignore a range of extra bits in status that do not indicate 2341e1069839SBorislav Petkov * overflow by themselves. 2342e1069839SBorislav Petkov */ 2343e1069839SBorislav Petkov status &= ~(GLOBAL_STATUS_COND_CHG | 2344e1069839SBorislav Petkov GLOBAL_STATUS_ASIF | 2345e1069839SBorislav Petkov GLOBAL_STATUS_LBRS_FROZEN); 2346e1069839SBorislav Petkov if (!status) 2347ba12d20eSKan Liang return 0; 2348daa864b8SStephane Eranian /* 2349daa864b8SStephane Eranian * In case multiple PEBS events are sampled at the same time, 2350daa864b8SStephane Eranian * it is possible to have GLOBAL_STATUS bit 62 set indicating 2351daa864b8SStephane Eranian * PEBS buffer overflow and also seeing at most 3 PEBS counters 2352daa864b8SStephane Eranian * having their bits set in the status register. This is a sign 2353daa864b8SStephane Eranian * that there was at least one PEBS record pending at the time 2354daa864b8SStephane Eranian * of the PMU interrupt. PEBS counters must only be processed 2355daa864b8SStephane Eranian * via the drain_pebs() calls and not via the regular sample 2356daa864b8SStephane Eranian * processing loop coming after that the function, otherwise 2357daa864b8SStephane Eranian * phony regular samples may be generated in the sampling buffer 2358daa864b8SStephane Eranian * not marked with the EXACT tag. Another possibility is to have 2359daa864b8SStephane Eranian * one PEBS event and at least one non-PEBS event whic hoverflows 2360daa864b8SStephane Eranian * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2361daa864b8SStephane Eranian * not be set, yet the overflow status bit for the PEBS counter will 2362daa864b8SStephane Eranian * be on Skylake. 2363daa864b8SStephane Eranian * 2364daa864b8SStephane Eranian * To avoid this problem, we systematically ignore the PEBS-enabled 2365daa864b8SStephane Eranian * counters from the GLOBAL_STATUS mask and we always process PEBS 2366daa864b8SStephane Eranian * events via drain_pebs(). 2367daa864b8SStephane Eranian */ 2368ec71a398SKan Liang if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2369ec71a398SKan Liang status &= ~cpuc->pebs_enabled; 2370ec71a398SKan Liang else 2371fd583ad1SKan Liang status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2372e1069839SBorislav Petkov 2373e1069839SBorislav Petkov /* 2374e1069839SBorislav Petkov * PEBS overflow sets bit 62 in the global status register 2375e1069839SBorislav Petkov */ 2376e1069839SBorislav Petkov if (__test_and_clear_bit(62, (unsigned long *)&status)) { 2377e1069839SBorislav Petkov handled++; 2378e1069839SBorislav Petkov x86_pmu.drain_pebs(regs); 23798077eca0SStephane Eranian status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2380e1069839SBorislav Petkov } 2381e1069839SBorislav Petkov 2382e1069839SBorislav Petkov /* 2383e1069839SBorislav Petkov * Intel PT 2384e1069839SBorislav Petkov */ 2385e1069839SBorislav Petkov if (__test_and_clear_bit(55, (unsigned long *)&status)) { 2386e1069839SBorislav Petkov handled++; 23878479e04eSLuwei Kang if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 23888479e04eSLuwei Kang perf_guest_cbs->handle_intel_pt_intr)) 23898479e04eSLuwei Kang perf_guest_cbs->handle_intel_pt_intr(); 23908479e04eSLuwei Kang else 2391e1069839SBorislav Petkov intel_pt_interrupt(); 2392e1069839SBorislav Petkov } 2393e1069839SBorislav Petkov 2394e1069839SBorislav Petkov /* 2395e1069839SBorislav Petkov * Checkpointed counters can lead to 'spurious' PMIs because the 2396e1069839SBorislav Petkov * rollback caused by the PMI will have cleared the overflow status 2397e1069839SBorislav Petkov * bit. Therefore always force probe these counters. 2398e1069839SBorislav Petkov */ 2399e1069839SBorislav Petkov status |= cpuc->intel_cp_status; 2400e1069839SBorislav Petkov 2401e1069839SBorislav Petkov for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2402e1069839SBorislav Petkov struct perf_event *event = cpuc->events[bit]; 2403e1069839SBorislav Petkov 2404e1069839SBorislav Petkov handled++; 2405e1069839SBorislav Petkov 2406e1069839SBorislav Petkov if (!test_bit(bit, cpuc->active_mask)) 2407e1069839SBorislav Petkov continue; 2408e1069839SBorislav Petkov 2409e1069839SBorislav Petkov if (!intel_pmu_save_and_restart(event)) 2410e1069839SBorislav Petkov continue; 2411e1069839SBorislav Petkov 2412e1069839SBorislav Petkov perf_sample_data_init(&data, 0, event->hw.last_period); 2413e1069839SBorislav Petkov 2414e1069839SBorislav Petkov if (has_branch_stack(event)) 2415e1069839SBorislav Petkov data.br_stack = &cpuc->lbr_stack; 2416e1069839SBorislav Petkov 2417e1069839SBorislav Petkov if (perf_event_overflow(event, &data, regs)) 2418e1069839SBorislav Petkov x86_pmu_stop(event, 0); 2419e1069839SBorislav Petkov } 2420e1069839SBorislav Petkov 2421ba12d20eSKan Liang return handled; 2422ba12d20eSKan Liang } 2423ba12d20eSKan Liang 24242a5bf23dSPeter Zijlstra static bool disable_counter_freezing = true; 2425af3bdb99SAndi Kleen static int __init intel_perf_counter_freezing_setup(char *s) 2426af3bdb99SAndi Kleen { 24272a5bf23dSPeter Zijlstra bool res; 24282a5bf23dSPeter Zijlstra 24292a5bf23dSPeter Zijlstra if (kstrtobool(s, &res)) 24302a5bf23dSPeter Zijlstra return -EINVAL; 24312a5bf23dSPeter Zijlstra 24322a5bf23dSPeter Zijlstra disable_counter_freezing = !res; 2433af3bdb99SAndi Kleen return 1; 2434af3bdb99SAndi Kleen } 24352a5bf23dSPeter Zijlstra __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup); 2436af3bdb99SAndi Kleen 2437af3bdb99SAndi Kleen /* 2438af3bdb99SAndi Kleen * Simplified handler for Arch Perfmon v4: 2439af3bdb99SAndi Kleen * - We rely on counter freezing/unfreezing to enable/disable the PMU. 2440af3bdb99SAndi Kleen * This is done automatically on PMU ack. 2441af3bdb99SAndi Kleen * - Ack the PMU only after the APIC. 2442af3bdb99SAndi Kleen */ 2443af3bdb99SAndi Kleen 2444af3bdb99SAndi Kleen static int intel_pmu_handle_irq_v4(struct pt_regs *regs) 2445af3bdb99SAndi Kleen { 2446af3bdb99SAndi Kleen struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2447af3bdb99SAndi Kleen int handled = 0; 2448af3bdb99SAndi Kleen bool bts = false; 2449af3bdb99SAndi Kleen u64 status; 2450af3bdb99SAndi Kleen int pmu_enabled = cpuc->enabled; 2451af3bdb99SAndi Kleen int loops = 0; 2452af3bdb99SAndi Kleen 2453af3bdb99SAndi Kleen /* PMU has been disabled because of counter freezing */ 2454af3bdb99SAndi Kleen cpuc->enabled = 0; 2455af3bdb99SAndi Kleen if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2456af3bdb99SAndi Kleen bts = true; 2457af3bdb99SAndi Kleen intel_bts_disable_local(); 2458af3bdb99SAndi Kleen handled = intel_pmu_drain_bts_buffer(); 2459af3bdb99SAndi Kleen handled += intel_bts_interrupt(); 2460af3bdb99SAndi Kleen } 2461af3bdb99SAndi Kleen status = intel_pmu_get_status(); 2462af3bdb99SAndi Kleen if (!status) 2463af3bdb99SAndi Kleen goto done; 2464af3bdb99SAndi Kleen again: 2465af3bdb99SAndi Kleen intel_pmu_lbr_read(); 2466af3bdb99SAndi Kleen if (++loops > 100) { 2467af3bdb99SAndi Kleen static bool warned; 2468af3bdb99SAndi Kleen 2469af3bdb99SAndi Kleen if (!warned) { 2470af3bdb99SAndi Kleen WARN(1, "perfevents: irq loop stuck!\n"); 2471af3bdb99SAndi Kleen perf_event_print_debug(); 2472af3bdb99SAndi Kleen warned = true; 2473af3bdb99SAndi Kleen } 2474af3bdb99SAndi Kleen intel_pmu_reset(); 2475af3bdb99SAndi Kleen goto done; 2476af3bdb99SAndi Kleen } 2477af3bdb99SAndi Kleen 2478af3bdb99SAndi Kleen 2479af3bdb99SAndi Kleen handled += handle_pmi_common(regs, status); 2480af3bdb99SAndi Kleen done: 2481af3bdb99SAndi Kleen /* Ack the PMI in the APIC */ 2482af3bdb99SAndi Kleen apic_write(APIC_LVTPC, APIC_DM_NMI); 2483af3bdb99SAndi Kleen 2484af3bdb99SAndi Kleen /* 2485af3bdb99SAndi Kleen * The counters start counting immediately while ack the status. 2486af3bdb99SAndi Kleen * Make it as close as possible to IRET. This avoids bogus 2487af3bdb99SAndi Kleen * freezing on Skylake CPUs. 2488af3bdb99SAndi Kleen */ 2489af3bdb99SAndi Kleen if (status) { 2490af3bdb99SAndi Kleen intel_pmu_ack_status(status); 2491af3bdb99SAndi Kleen } else { 2492af3bdb99SAndi Kleen /* 2493af3bdb99SAndi Kleen * CPU may issues two PMIs very close to each other. 2494af3bdb99SAndi Kleen * When the PMI handler services the first one, the 2495af3bdb99SAndi Kleen * GLOBAL_STATUS is already updated to reflect both. 2496af3bdb99SAndi Kleen * When it IRETs, the second PMI is immediately 2497af3bdb99SAndi Kleen * handled and it sees clear status. At the meantime, 2498af3bdb99SAndi Kleen * there may be a third PMI, because the freezing bit 2499af3bdb99SAndi Kleen * isn't set since the ack in first PMI handlers. 2500af3bdb99SAndi Kleen * Double check if there is more work to be done. 2501af3bdb99SAndi Kleen */ 2502af3bdb99SAndi Kleen status = intel_pmu_get_status(); 2503af3bdb99SAndi Kleen if (status) 2504af3bdb99SAndi Kleen goto again; 2505af3bdb99SAndi Kleen } 2506af3bdb99SAndi Kleen 2507af3bdb99SAndi Kleen if (bts) 2508af3bdb99SAndi Kleen intel_bts_enable_local(); 2509af3bdb99SAndi Kleen cpuc->enabled = pmu_enabled; 2510af3bdb99SAndi Kleen return handled; 2511af3bdb99SAndi Kleen } 2512af3bdb99SAndi Kleen 2513ba12d20eSKan Liang /* 2514ba12d20eSKan Liang * This handler is triggered by the local APIC, so the APIC IRQ handling 2515ba12d20eSKan Liang * rules apply: 2516ba12d20eSKan Liang */ 2517ba12d20eSKan Liang static int intel_pmu_handle_irq(struct pt_regs *regs) 2518ba12d20eSKan Liang { 2519ba12d20eSKan Liang struct cpu_hw_events *cpuc; 2520ba12d20eSKan Liang int loops; 2521ba12d20eSKan Liang u64 status; 2522ba12d20eSKan Liang int handled; 2523ba12d20eSKan Liang int pmu_enabled; 2524ba12d20eSKan Liang 2525ba12d20eSKan Liang cpuc = this_cpu_ptr(&cpu_hw_events); 2526ba12d20eSKan Liang 2527ba12d20eSKan Liang /* 2528ba12d20eSKan Liang * Save the PMU state. 2529ba12d20eSKan Liang * It needs to be restored when leaving the handler. 2530ba12d20eSKan Liang */ 2531ba12d20eSKan Liang pmu_enabled = cpuc->enabled; 2532ba12d20eSKan Liang /* 2533ba12d20eSKan Liang * No known reason to not always do late ACK, 2534ba12d20eSKan Liang * but just in case do it opt-in. 2535ba12d20eSKan Liang */ 2536ba12d20eSKan Liang if (!x86_pmu.late_ack) 2537ba12d20eSKan Liang apic_write(APIC_LVTPC, APIC_DM_NMI); 2538ba12d20eSKan Liang intel_bts_disable_local(); 2539ba12d20eSKan Liang cpuc->enabled = 0; 2540ba12d20eSKan Liang __intel_pmu_disable_all(); 2541ba12d20eSKan Liang handled = intel_pmu_drain_bts_buffer(); 2542ba12d20eSKan Liang handled += intel_bts_interrupt(); 2543ba12d20eSKan Liang status = intel_pmu_get_status(); 2544ba12d20eSKan Liang if (!status) 2545ba12d20eSKan Liang goto done; 2546ba12d20eSKan Liang 2547ba12d20eSKan Liang loops = 0; 2548ba12d20eSKan Liang again: 2549ba12d20eSKan Liang intel_pmu_lbr_read(); 2550ba12d20eSKan Liang intel_pmu_ack_status(status); 2551ba12d20eSKan Liang if (++loops > 100) { 2552ba12d20eSKan Liang static bool warned; 2553ba12d20eSKan Liang 2554ba12d20eSKan Liang if (!warned) { 2555ba12d20eSKan Liang WARN(1, "perfevents: irq loop stuck!\n"); 2556ba12d20eSKan Liang perf_event_print_debug(); 2557ba12d20eSKan Liang warned = true; 2558ba12d20eSKan Liang } 2559ba12d20eSKan Liang intel_pmu_reset(); 2560ba12d20eSKan Liang goto done; 2561ba12d20eSKan Liang } 2562ba12d20eSKan Liang 2563ba12d20eSKan Liang handled += handle_pmi_common(regs, status); 2564ba12d20eSKan Liang 2565e1069839SBorislav Petkov /* 2566e1069839SBorislav Petkov * Repeat if there is more work to be done: 2567e1069839SBorislav Petkov */ 2568e1069839SBorislav Petkov status = intel_pmu_get_status(); 2569e1069839SBorislav Petkov if (status) 2570e1069839SBorislav Petkov goto again; 2571e1069839SBorislav Petkov 2572e1069839SBorislav Petkov done: 2573c3d266c8SKan Liang /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 257482d71ed0SKan Liang cpuc->enabled = pmu_enabled; 257582d71ed0SKan Liang if (pmu_enabled) 2576e1069839SBorislav Petkov __intel_pmu_enable_all(0, true); 2577cecf6235SAlexander Shishkin intel_bts_enable_local(); 2578c3d266c8SKan Liang 2579e1069839SBorislav Petkov /* 2580e1069839SBorislav Petkov * Only unmask the NMI after the overflow counters 2581e1069839SBorislav Petkov * have been reset. This avoids spurious NMIs on 2582e1069839SBorislav Petkov * Haswell CPUs. 2583e1069839SBorislav Petkov */ 2584e1069839SBorislav Petkov if (x86_pmu.late_ack) 2585e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 2586e1069839SBorislav Petkov return handled; 2587e1069839SBorislav Petkov } 2588e1069839SBorislav Petkov 2589e1069839SBorislav Petkov static struct event_constraint * 2590e1069839SBorislav Petkov intel_bts_constraints(struct perf_event *event) 2591e1069839SBorislav Petkov { 259267266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) 2593e1069839SBorislav Petkov return &bts_constraint; 2594e1069839SBorislav Petkov 2595e1069839SBorislav Petkov return NULL; 2596e1069839SBorislav Petkov } 2597e1069839SBorislav Petkov 2598e1069839SBorislav Petkov static int intel_alt_er(int idx, u64 config) 2599e1069839SBorislav Petkov { 2600e1069839SBorislav Petkov int alt_idx = idx; 2601e1069839SBorislav Petkov 2602e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2603e1069839SBorislav Petkov return idx; 2604e1069839SBorislav Petkov 2605e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) 2606e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_1; 2607e1069839SBorislav Petkov 2608e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_1) 2609e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_0; 2610e1069839SBorislav Petkov 2611e1069839SBorislav Petkov if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2612e1069839SBorislav Petkov return idx; 2613e1069839SBorislav Petkov 2614e1069839SBorislav Petkov return alt_idx; 2615e1069839SBorislav Petkov } 2616e1069839SBorislav Petkov 2617e1069839SBorislav Petkov static void intel_fixup_er(struct perf_event *event, int idx) 2618e1069839SBorislav Petkov { 2619e1069839SBorislav Petkov event->hw.extra_reg.idx = idx; 2620e1069839SBorislav Petkov 2621e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) { 2622e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2623e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2624e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2625e1069839SBorislav Petkov } else if (idx == EXTRA_REG_RSP_1) { 2626e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2627e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2628e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2629e1069839SBorislav Petkov } 2630e1069839SBorislav Petkov } 2631e1069839SBorislav Petkov 2632e1069839SBorislav Petkov /* 2633e1069839SBorislav Petkov * manage allocation of shared extra msr for certain events 2634e1069839SBorislav Petkov * 2635e1069839SBorislav Petkov * sharing can be: 2636e1069839SBorislav Petkov * per-cpu: to be shared between the various events on a single PMU 2637e1069839SBorislav Petkov * per-core: per-cpu + shared by HT threads 2638e1069839SBorislav Petkov */ 2639e1069839SBorislav Petkov static struct event_constraint * 2640e1069839SBorislav Petkov __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2641e1069839SBorislav Petkov struct perf_event *event, 2642e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2643e1069839SBorislav Petkov { 2644e1069839SBorislav Petkov struct event_constraint *c = &emptyconstraint; 2645e1069839SBorislav Petkov struct er_account *era; 2646e1069839SBorislav Petkov unsigned long flags; 2647e1069839SBorislav Petkov int idx = reg->idx; 2648e1069839SBorislav Petkov 2649e1069839SBorislav Petkov /* 2650e1069839SBorislav Petkov * reg->alloc can be set due to existing state, so for fake cpuc we 2651e1069839SBorislav Petkov * need to ignore this, otherwise we might fail to allocate proper fake 2652e1069839SBorislav Petkov * state for this extra reg constraint. Also see the comment below. 2653e1069839SBorislav Petkov */ 2654e1069839SBorislav Petkov if (reg->alloc && !cpuc->is_fake) 2655e1069839SBorislav Petkov return NULL; /* call x86_get_event_constraint() */ 2656e1069839SBorislav Petkov 2657e1069839SBorislav Petkov again: 2658e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[idx]; 2659e1069839SBorislav Petkov /* 2660e1069839SBorislav Petkov * we use spin_lock_irqsave() to avoid lockdep issues when 2661e1069839SBorislav Petkov * passing a fake cpuc 2662e1069839SBorislav Petkov */ 2663e1069839SBorislav Petkov raw_spin_lock_irqsave(&era->lock, flags); 2664e1069839SBorislav Petkov 2665e1069839SBorislav Petkov if (!atomic_read(&era->ref) || era->config == reg->config) { 2666e1069839SBorislav Petkov 2667e1069839SBorislav Petkov /* 2668e1069839SBorislav Petkov * If its a fake cpuc -- as per validate_{group,event}() we 2669e1069839SBorislav Petkov * shouldn't touch event state and we can avoid doing so 2670e1069839SBorislav Petkov * since both will only call get_event_constraints() once 2671e1069839SBorislav Petkov * on each event, this avoids the need for reg->alloc. 2672e1069839SBorislav Petkov * 2673e1069839SBorislav Petkov * Not doing the ER fixup will only result in era->reg being 2674e1069839SBorislav Petkov * wrong, but since we won't actually try and program hardware 2675e1069839SBorislav Petkov * this isn't a problem either. 2676e1069839SBorislav Petkov */ 2677e1069839SBorislav Petkov if (!cpuc->is_fake) { 2678e1069839SBorislav Petkov if (idx != reg->idx) 2679e1069839SBorislav Petkov intel_fixup_er(event, idx); 2680e1069839SBorislav Petkov 2681e1069839SBorislav Petkov /* 2682e1069839SBorislav Petkov * x86_schedule_events() can call get_event_constraints() 2683e1069839SBorislav Petkov * multiple times on events in the case of incremental 2684e1069839SBorislav Petkov * scheduling(). reg->alloc ensures we only do the ER 2685e1069839SBorislav Petkov * allocation once. 2686e1069839SBorislav Petkov */ 2687e1069839SBorislav Petkov reg->alloc = 1; 2688e1069839SBorislav Petkov } 2689e1069839SBorislav Petkov 2690e1069839SBorislav Petkov /* lock in msr value */ 2691e1069839SBorislav Petkov era->config = reg->config; 2692e1069839SBorislav Petkov era->reg = reg->reg; 2693e1069839SBorislav Petkov 2694e1069839SBorislav Petkov /* one more user */ 2695e1069839SBorislav Petkov atomic_inc(&era->ref); 2696e1069839SBorislav Petkov 2697e1069839SBorislav Petkov /* 2698e1069839SBorislav Petkov * need to call x86_get_event_constraint() 2699e1069839SBorislav Petkov * to check if associated event has constraints 2700e1069839SBorislav Petkov */ 2701e1069839SBorislav Petkov c = NULL; 2702e1069839SBorislav Petkov } else { 2703e1069839SBorislav Petkov idx = intel_alt_er(idx, reg->config); 2704e1069839SBorislav Petkov if (idx != reg->idx) { 2705e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2706e1069839SBorislav Petkov goto again; 2707e1069839SBorislav Petkov } 2708e1069839SBorislav Petkov } 2709e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2710e1069839SBorislav Petkov 2711e1069839SBorislav Petkov return c; 2712e1069839SBorislav Petkov } 2713e1069839SBorislav Petkov 2714e1069839SBorislav Petkov static void 2715e1069839SBorislav Petkov __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 2716e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2717e1069839SBorislav Petkov { 2718e1069839SBorislav Petkov struct er_account *era; 2719e1069839SBorislav Petkov 2720e1069839SBorislav Petkov /* 2721e1069839SBorislav Petkov * Only put constraint if extra reg was actually allocated. Also takes 2722e1069839SBorislav Petkov * care of event which do not use an extra shared reg. 2723e1069839SBorislav Petkov * 2724e1069839SBorislav Petkov * Also, if this is a fake cpuc we shouldn't touch any event state 2725e1069839SBorislav Petkov * (reg->alloc) and we don't care about leaving inconsistent cpuc state 2726e1069839SBorislav Petkov * either since it'll be thrown out. 2727e1069839SBorislav Petkov */ 2728e1069839SBorislav Petkov if (!reg->alloc || cpuc->is_fake) 2729e1069839SBorislav Petkov return; 2730e1069839SBorislav Petkov 2731e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[reg->idx]; 2732e1069839SBorislav Petkov 2733e1069839SBorislav Petkov /* one fewer user */ 2734e1069839SBorislav Petkov atomic_dec(&era->ref); 2735e1069839SBorislav Petkov 2736e1069839SBorislav Petkov /* allocate again next time */ 2737e1069839SBorislav Petkov reg->alloc = 0; 2738e1069839SBorislav Petkov } 2739e1069839SBorislav Petkov 2740e1069839SBorislav Petkov static struct event_constraint * 2741e1069839SBorislav Petkov intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 2742e1069839SBorislav Petkov struct perf_event *event) 2743e1069839SBorislav Petkov { 2744e1069839SBorislav Petkov struct event_constraint *c = NULL, *d; 2745e1069839SBorislav Petkov struct hw_perf_event_extra *xreg, *breg; 2746e1069839SBorislav Petkov 2747e1069839SBorislav Petkov xreg = &event->hw.extra_reg; 2748e1069839SBorislav Petkov if (xreg->idx != EXTRA_REG_NONE) { 2749e1069839SBorislav Petkov c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 2750e1069839SBorislav Petkov if (c == &emptyconstraint) 2751e1069839SBorislav Petkov return c; 2752e1069839SBorislav Petkov } 2753e1069839SBorislav Petkov breg = &event->hw.branch_reg; 2754e1069839SBorislav Petkov if (breg->idx != EXTRA_REG_NONE) { 2755e1069839SBorislav Petkov d = __intel_shared_reg_get_constraints(cpuc, event, breg); 2756e1069839SBorislav Petkov if (d == &emptyconstraint) { 2757e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, xreg); 2758e1069839SBorislav Petkov c = d; 2759e1069839SBorislav Petkov } 2760e1069839SBorislav Petkov } 2761e1069839SBorislav Petkov return c; 2762e1069839SBorislav Petkov } 2763e1069839SBorislav Petkov 2764e1069839SBorislav Petkov struct event_constraint * 2765e1069839SBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2766e1069839SBorislav Petkov struct perf_event *event) 2767e1069839SBorislav Petkov { 2768e1069839SBorislav Petkov struct event_constraint *c; 2769e1069839SBorislav Petkov 2770e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 2771e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 277263b79f6eSPeter Zijlstra if (constraint_match(c, event->hw.config)) { 2773e1069839SBorislav Petkov event->hw.flags |= c->flags; 2774e1069839SBorislav Petkov return c; 2775e1069839SBorislav Petkov } 2776e1069839SBorislav Petkov } 2777e1069839SBorislav Petkov } 2778e1069839SBorislav Petkov 2779e1069839SBorislav Petkov return &unconstrained; 2780e1069839SBorislav Petkov } 2781e1069839SBorislav Petkov 2782e1069839SBorislav Petkov static struct event_constraint * 2783e1069839SBorislav Petkov __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 2784e1069839SBorislav Petkov struct perf_event *event) 2785e1069839SBorislav Petkov { 2786e1069839SBorislav Petkov struct event_constraint *c; 2787e1069839SBorislav Petkov 2788e1069839SBorislav Petkov c = intel_bts_constraints(event); 2789e1069839SBorislav Petkov if (c) 2790e1069839SBorislav Petkov return c; 2791e1069839SBorislav Petkov 2792e1069839SBorislav Petkov c = intel_shared_regs_constraints(cpuc, event); 2793e1069839SBorislav Petkov if (c) 2794e1069839SBorislav Petkov return c; 2795e1069839SBorislav Petkov 2796e1069839SBorislav Petkov c = intel_pebs_constraints(event); 2797e1069839SBorislav Petkov if (c) 2798e1069839SBorislav Petkov return c; 2799e1069839SBorislav Petkov 2800e1069839SBorislav Petkov return x86_get_event_constraints(cpuc, idx, event); 2801e1069839SBorislav Petkov } 2802e1069839SBorislav Petkov 2803e1069839SBorislav Petkov static void 2804e1069839SBorislav Petkov intel_start_scheduling(struct cpu_hw_events *cpuc) 2805e1069839SBorislav Petkov { 2806e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2807e1069839SBorislav Petkov struct intel_excl_states *xl; 2808e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2809e1069839SBorislav Petkov 2810e1069839SBorislav Petkov /* 2811e1069839SBorislav Petkov * nothing needed if in group validation mode 2812e1069839SBorislav Petkov */ 2813e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2814e1069839SBorislav Petkov return; 2815e1069839SBorislav Petkov 2816e1069839SBorislav Petkov /* 2817e1069839SBorislav Petkov * no exclusion needed 2818e1069839SBorislav Petkov */ 2819e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2820e1069839SBorislav Petkov return; 2821e1069839SBorislav Petkov 2822e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2823e1069839SBorislav Petkov 2824e1069839SBorislav Petkov xl->sched_started = true; 2825e1069839SBorislav Petkov /* 2826e1069839SBorislav Petkov * lock shared state until we are done scheduling 2827e1069839SBorislav Petkov * in stop_event_scheduling() 2828e1069839SBorislav Petkov * makes scheduling appear as a transaction 2829e1069839SBorislav Petkov */ 2830e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 2831e1069839SBorislav Petkov } 2832e1069839SBorislav Petkov 2833e1069839SBorislav Petkov static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2834e1069839SBorislav Petkov { 2835e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2836e1069839SBorislav Petkov struct event_constraint *c = cpuc->event_constraint[idx]; 2837e1069839SBorislav Petkov struct intel_excl_states *xl; 2838e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2839e1069839SBorislav Petkov 2840e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2841e1069839SBorislav Petkov return; 2842e1069839SBorislav Petkov 2843e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2844e1069839SBorislav Petkov return; 2845e1069839SBorislav Petkov 2846e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 2847e1069839SBorislav Petkov return; 2848e1069839SBorislav Petkov 2849e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2850e1069839SBorislav Petkov 2851e1069839SBorislav Petkov lockdep_assert_held(&excl_cntrs->lock); 2852e1069839SBorislav Petkov 2853e1069839SBorislav Petkov if (c->flags & PERF_X86_EVENT_EXCL) 2854e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 2855e1069839SBorislav Petkov else 2856e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_SHARED; 2857e1069839SBorislav Petkov } 2858e1069839SBorislav Petkov 2859e1069839SBorislav Petkov static void 2860e1069839SBorislav Petkov intel_stop_scheduling(struct cpu_hw_events *cpuc) 2861e1069839SBorislav Petkov { 2862e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2863e1069839SBorislav Petkov struct intel_excl_states *xl; 2864e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2865e1069839SBorislav Petkov 2866e1069839SBorislav Petkov /* 2867e1069839SBorislav Petkov * nothing needed if in group validation mode 2868e1069839SBorislav Petkov */ 2869e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2870e1069839SBorislav Petkov return; 2871e1069839SBorislav Petkov /* 2872e1069839SBorislav Petkov * no exclusion needed 2873e1069839SBorislav Petkov */ 2874e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2875e1069839SBorislav Petkov return; 2876e1069839SBorislav Petkov 2877e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 2878e1069839SBorislav Petkov 2879e1069839SBorislav Petkov xl->sched_started = false; 2880e1069839SBorislav Petkov /* 2881e1069839SBorislav Petkov * release shared state lock (acquired in intel_start_scheduling()) 2882e1069839SBorislav Petkov */ 2883e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 2884e1069839SBorislav Petkov } 2885e1069839SBorislav Petkov 2886e1069839SBorislav Petkov static struct event_constraint * 288711f8b2d6SPeter Zijlstra (Intel) dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 288811f8b2d6SPeter Zijlstra (Intel) { 288911f8b2d6SPeter Zijlstra (Intel) WARN_ON_ONCE(!cpuc->constraint_list); 289011f8b2d6SPeter Zijlstra (Intel) 289111f8b2d6SPeter Zijlstra (Intel) if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 289211f8b2d6SPeter Zijlstra (Intel) struct event_constraint *cx; 289311f8b2d6SPeter Zijlstra (Intel) 289411f8b2d6SPeter Zijlstra (Intel) /* 289511f8b2d6SPeter Zijlstra (Intel) * grab pre-allocated constraint entry 289611f8b2d6SPeter Zijlstra (Intel) */ 289711f8b2d6SPeter Zijlstra (Intel) cx = &cpuc->constraint_list[idx]; 289811f8b2d6SPeter Zijlstra (Intel) 289911f8b2d6SPeter Zijlstra (Intel) /* 290011f8b2d6SPeter Zijlstra (Intel) * initialize dynamic constraint 290111f8b2d6SPeter Zijlstra (Intel) * with static constraint 290211f8b2d6SPeter Zijlstra (Intel) */ 290311f8b2d6SPeter Zijlstra (Intel) *cx = *c; 290411f8b2d6SPeter Zijlstra (Intel) 290511f8b2d6SPeter Zijlstra (Intel) /* 290611f8b2d6SPeter Zijlstra (Intel) * mark constraint as dynamic 290711f8b2d6SPeter Zijlstra (Intel) */ 290811f8b2d6SPeter Zijlstra (Intel) cx->flags |= PERF_X86_EVENT_DYNAMIC; 290911f8b2d6SPeter Zijlstra (Intel) c = cx; 291011f8b2d6SPeter Zijlstra (Intel) } 291111f8b2d6SPeter Zijlstra (Intel) 291211f8b2d6SPeter Zijlstra (Intel) return c; 291311f8b2d6SPeter Zijlstra (Intel) } 291411f8b2d6SPeter Zijlstra (Intel) 291511f8b2d6SPeter Zijlstra (Intel) static struct event_constraint * 2916e1069839SBorislav Petkov intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 2917e1069839SBorislav Petkov int idx, struct event_constraint *c) 2918e1069839SBorislav Petkov { 2919e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 2920e1069839SBorislav Petkov struct intel_excl_states *xlo; 2921e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 2922c090cb70SPeter Zijlstra int is_excl, i, w; 2923e1069839SBorislav Petkov 2924e1069839SBorislav Petkov /* 2925e1069839SBorislav Petkov * validating a group does not require 2926e1069839SBorislav Petkov * enforcing cross-thread exclusion 2927e1069839SBorislav Petkov */ 2928e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 2929e1069839SBorislav Petkov return c; 2930e1069839SBorislav Petkov 2931e1069839SBorislav Petkov /* 2932e1069839SBorislav Petkov * no exclusion needed 2933e1069839SBorislav Petkov */ 2934e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 2935e1069839SBorislav Petkov return c; 2936e1069839SBorislav Petkov 2937e1069839SBorislav Petkov /* 2938e1069839SBorislav Petkov * because we modify the constraint, we need 2939e1069839SBorislav Petkov * to make a copy. Static constraints come 2940e1069839SBorislav Petkov * from static const tables. 2941e1069839SBorislav Petkov * 2942e1069839SBorislav Petkov * only needed when constraint has not yet 2943e1069839SBorislav Petkov * been cloned (marked dynamic) 2944e1069839SBorislav Petkov */ 294511f8b2d6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 2946e1069839SBorislav Petkov 2947e1069839SBorislav Petkov /* 2948e1069839SBorislav Petkov * From here on, the constraint is dynamic. 2949e1069839SBorislav Petkov * Either it was just allocated above, or it 2950e1069839SBorislav Petkov * was allocated during a earlier invocation 2951e1069839SBorislav Petkov * of this function 2952e1069839SBorislav Petkov */ 2953e1069839SBorislav Petkov 2954e1069839SBorislav Petkov /* 2955e1069839SBorislav Petkov * state of sibling HT 2956e1069839SBorislav Petkov */ 2957e1069839SBorislav Petkov xlo = &excl_cntrs->states[tid ^ 1]; 2958e1069839SBorislav Petkov 2959e1069839SBorislav Petkov /* 2960e1069839SBorislav Petkov * event requires exclusive counter access 2961e1069839SBorislav Petkov * across HT threads 2962e1069839SBorislav Petkov */ 2963e1069839SBorislav Petkov is_excl = c->flags & PERF_X86_EVENT_EXCL; 2964e1069839SBorislav Petkov if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 2965e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 2966e1069839SBorislav Petkov if (!cpuc->n_excl++) 2967e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 2968e1069839SBorislav Petkov } 2969e1069839SBorislav Petkov 2970e1069839SBorislav Petkov /* 2971e1069839SBorislav Petkov * Modify static constraint with current dynamic 2972e1069839SBorislav Petkov * state of thread 2973e1069839SBorislav Petkov * 2974e1069839SBorislav Petkov * EXCLUSIVE: sibling counter measuring exclusive event 2975e1069839SBorislav Petkov * SHARED : sibling counter measuring non-exclusive event 2976e1069839SBorislav Petkov * UNUSED : sibling counter unused 2977e1069839SBorislav Petkov */ 2978c090cb70SPeter Zijlstra w = c->weight; 2979e1069839SBorislav Petkov for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 2980e1069839SBorislav Petkov /* 2981e1069839SBorislav Petkov * exclusive event in sibling counter 2982e1069839SBorislav Petkov * our corresponding counter cannot be used 2983e1069839SBorislav Petkov * regardless of our event 2984e1069839SBorislav Petkov */ 2985c090cb70SPeter Zijlstra if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 2986e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 2987c090cb70SPeter Zijlstra w--; 2988c090cb70SPeter Zijlstra continue; 2989c090cb70SPeter Zijlstra } 2990e1069839SBorislav Petkov /* 2991e1069839SBorislav Petkov * if measuring an exclusive event, sibling 2992e1069839SBorislav Petkov * measuring non-exclusive, then counter cannot 2993e1069839SBorislav Petkov * be used 2994e1069839SBorislav Petkov */ 2995c090cb70SPeter Zijlstra if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 2996e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 2997c090cb70SPeter Zijlstra w--; 2998c090cb70SPeter Zijlstra continue; 2999e1069839SBorislav Petkov } 3000c090cb70SPeter Zijlstra } 3001e1069839SBorislav Petkov 3002e1069839SBorislav Petkov /* 3003e1069839SBorislav Petkov * if we return an empty mask, then switch 3004e1069839SBorislav Petkov * back to static empty constraint to avoid 3005e1069839SBorislav Petkov * the cost of freeing later on 3006e1069839SBorislav Petkov */ 3007c090cb70SPeter Zijlstra if (!w) 3008e1069839SBorislav Petkov c = &emptyconstraint; 3009e1069839SBorislav Petkov 3010c090cb70SPeter Zijlstra c->weight = w; 3011c090cb70SPeter Zijlstra 3012e1069839SBorislav Petkov return c; 3013e1069839SBorislav Petkov } 3014e1069839SBorislav Petkov 3015e1069839SBorislav Petkov static struct event_constraint * 3016e1069839SBorislav Petkov intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3017e1069839SBorislav Petkov struct perf_event *event) 3018e1069839SBorislav Petkov { 301921d65555SPeter Zijlstra struct event_constraint *c1, *c2; 3020e1069839SBorislav Petkov 3021e1069839SBorislav Petkov c1 = cpuc->event_constraint[idx]; 3022e1069839SBorislav Petkov 3023e1069839SBorislav Petkov /* 3024e1069839SBorislav Petkov * first time only 3025e1069839SBorislav Petkov * - static constraint: no change across incremental scheduling calls 3026e1069839SBorislav Petkov * - dynamic constraint: handled by intel_get_excl_constraints() 3027e1069839SBorislav Petkov */ 3028e1069839SBorislav Petkov c2 = __intel_get_event_constraints(cpuc, idx, event); 3029109717deSPeter Zijlstra if (c1) { 3030109717deSPeter Zijlstra WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3031e1069839SBorislav Petkov bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3032e1069839SBorislav Petkov c1->weight = c2->weight; 3033e1069839SBorislav Petkov c2 = c1; 3034e1069839SBorislav Petkov } 3035e1069839SBorislav Petkov 3036e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3037e1069839SBorislav Petkov return intel_get_excl_constraints(cpuc, event, idx, c2); 3038e1069839SBorislav Petkov 3039e1069839SBorislav Petkov return c2; 3040e1069839SBorislav Petkov } 3041e1069839SBorislav Petkov 3042e1069839SBorislav Petkov static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3043e1069839SBorislav Petkov struct perf_event *event) 3044e1069839SBorislav Petkov { 3045e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 3046e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3047e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3048e1069839SBorislav Petkov struct intel_excl_states *xl; 3049e1069839SBorislav Petkov 3050e1069839SBorislav Petkov /* 3051e1069839SBorislav Petkov * nothing needed if in group validation mode 3052e1069839SBorislav Petkov */ 3053e1069839SBorislav Petkov if (cpuc->is_fake) 3054e1069839SBorislav Petkov return; 3055e1069839SBorislav Petkov 3056e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3057e1069839SBorislav Petkov return; 3058e1069839SBorislav Petkov 3059e1069839SBorislav Petkov if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3060e1069839SBorislav Petkov hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3061e1069839SBorislav Petkov if (!--cpuc->n_excl) 3062e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3063e1069839SBorislav Petkov } 3064e1069839SBorislav Petkov 3065e1069839SBorislav Petkov /* 3066e1069839SBorislav Petkov * If event was actually assigned, then mark the counter state as 3067e1069839SBorislav Petkov * unused now. 3068e1069839SBorislav Petkov */ 3069e1069839SBorislav Petkov if (hwc->idx >= 0) { 3070e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3071e1069839SBorislav Petkov 3072e1069839SBorislav Petkov /* 3073e1069839SBorislav Petkov * put_constraint may be called from x86_schedule_events() 3074e1069839SBorislav Petkov * which already has the lock held so here make locking 3075e1069839SBorislav Petkov * conditional. 3076e1069839SBorislav Petkov */ 3077e1069839SBorislav Petkov if (!xl->sched_started) 3078e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3079e1069839SBorislav Petkov 3080e1069839SBorislav Petkov xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3081e1069839SBorislav Petkov 3082e1069839SBorislav Petkov if (!xl->sched_started) 3083e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3084e1069839SBorislav Petkov } 3085e1069839SBorislav Petkov } 3086e1069839SBorislav Petkov 3087e1069839SBorislav Petkov static void 3088e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3089e1069839SBorislav Petkov struct perf_event *event) 3090e1069839SBorislav Petkov { 3091e1069839SBorislav Petkov struct hw_perf_event_extra *reg; 3092e1069839SBorislav Petkov 3093e1069839SBorislav Petkov reg = &event->hw.extra_reg; 3094e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3095e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3096e1069839SBorislav Petkov 3097e1069839SBorislav Petkov reg = &event->hw.branch_reg; 3098e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3099e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3100e1069839SBorislav Petkov } 3101e1069839SBorislav Petkov 3102e1069839SBorislav Petkov static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3103e1069839SBorislav Petkov struct perf_event *event) 3104e1069839SBorislav Petkov { 3105e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(cpuc, event); 3106e1069839SBorislav Petkov 3107e1069839SBorislav Petkov /* 3108e1069839SBorislav Petkov * is PMU has exclusive counter restrictions, then 3109e1069839SBorislav Petkov * all events are subject to and must call the 3110e1069839SBorislav Petkov * put_excl_constraints() routine 3111e1069839SBorislav Petkov */ 3112e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3113e1069839SBorislav Petkov intel_put_excl_constraints(cpuc, event); 3114e1069839SBorislav Petkov } 3115e1069839SBorislav Petkov 3116e1069839SBorislav Petkov static void intel_pebs_aliases_core2(struct perf_event *event) 3117e1069839SBorislav Petkov { 3118e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3119e1069839SBorislav Petkov /* 3120e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3121e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3122e1069839SBorislav Petkov * 3123e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3124e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.ANY_P 3125e1069839SBorislav Petkov * (0x00c0), which is a PEBS capable event, to get the same 3126e1069839SBorislav Petkov * count. 3127e1069839SBorislav Petkov * 3128e1069839SBorislav Petkov * INST_RETIRED.ANY_P counts the number of cycles that retires 3129e1069839SBorislav Petkov * CNTMASK instructions. By setting CNTMASK to a value (16) 3130e1069839SBorislav Petkov * larger than the maximum number of instructions that can be 3131e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3132e1069839SBorislav Petkov * count all cycles that retire 16 or less instructions, which 3133e1069839SBorislav Petkov * is every cycle. 3134e1069839SBorislav Petkov * 3135e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3136e1069839SBorislav Petkov */ 3137e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3138e1069839SBorislav Petkov 3139e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3140e1069839SBorislav Petkov event->hw.config = alt_config; 3141e1069839SBorislav Petkov } 3142e1069839SBorislav Petkov } 3143e1069839SBorislav Petkov 3144e1069839SBorislav Petkov static void intel_pebs_aliases_snb(struct perf_event *event) 3145e1069839SBorislav Petkov { 3146e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3147e1069839SBorislav Petkov /* 3148e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3149e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3150e1069839SBorislav Petkov * 3151e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3152e1069839SBorislav Petkov * PEBS capable. However we can use UOPS_RETIRED.ALL 3153e1069839SBorislav Petkov * (0x01c2), which is a PEBS capable event, to get the same 3154e1069839SBorislav Petkov * count. 3155e1069839SBorislav Petkov * 3156e1069839SBorislav Petkov * UOPS_RETIRED.ALL counts the number of cycles that retires 3157e1069839SBorislav Petkov * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3158e1069839SBorislav Petkov * larger than the maximum number of micro-ops that can be 3159e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3160e1069839SBorislav Petkov * count all cycles that retire 16 or less micro-ops, which 3161e1069839SBorislav Petkov * is every cycle. 3162e1069839SBorislav Petkov * 3163e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3164e1069839SBorislav Petkov */ 3165e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3166e1069839SBorislav Petkov 3167e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3168e1069839SBorislav Petkov event->hw.config = alt_config; 3169e1069839SBorislav Petkov } 3170e1069839SBorislav Petkov } 3171e1069839SBorislav Petkov 3172e1069839SBorislav Petkov static void intel_pebs_aliases_precdist(struct perf_event *event) 3173e1069839SBorislav Petkov { 3174e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3175e1069839SBorislav Petkov /* 3176e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3177e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3178e1069839SBorislav Petkov * 3179e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3180e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3181e1069839SBorislav Petkov * (0x01c0), which is a PEBS capable event, to get the same 3182e1069839SBorislav Petkov * count. 3183e1069839SBorislav Petkov * 3184e1069839SBorislav Petkov * The PREC_DIST event has special support to minimize sample 3185e1069839SBorislav Petkov * shadowing effects. One drawback is that it can be 3186e1069839SBorislav Petkov * only programmed on counter 1, but that seems like an 3187e1069839SBorislav Petkov * acceptable trade off. 3188e1069839SBorislav Petkov */ 3189e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3190e1069839SBorislav Petkov 3191e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3192e1069839SBorislav Petkov event->hw.config = alt_config; 3193e1069839SBorislav Petkov } 3194e1069839SBorislav Petkov } 3195e1069839SBorislav Petkov 3196e1069839SBorislav Petkov static void intel_pebs_aliases_ivb(struct perf_event *event) 3197e1069839SBorislav Petkov { 3198e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3199e1069839SBorislav Petkov return intel_pebs_aliases_snb(event); 3200e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3201e1069839SBorislav Petkov } 3202e1069839SBorislav Petkov 3203e1069839SBorislav Petkov static void intel_pebs_aliases_skl(struct perf_event *event) 3204e1069839SBorislav Petkov { 3205e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3206e1069839SBorislav Petkov return intel_pebs_aliases_core2(event); 3207e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3208e1069839SBorislav Petkov } 3209e1069839SBorislav Petkov 3210174afc3eSKan Liang static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3211e1069839SBorislav Petkov { 3212174afc3eSKan Liang unsigned long flags = x86_pmu.large_pebs_flags; 3213e1069839SBorislav Petkov 3214e1069839SBorislav Petkov if (event->attr.use_clockid) 3215e1069839SBorislav Petkov flags &= ~PERF_SAMPLE_TIME; 3216a47ba4d7SAndi Kleen if (!event->attr.exclude_kernel) 3217a47ba4d7SAndi Kleen flags &= ~PERF_SAMPLE_REGS_USER; 32189d5dcc93SKan Liang if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3219a47ba4d7SAndi Kleen flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3220e1069839SBorislav Petkov return flags; 3221e1069839SBorislav Petkov } 3222e1069839SBorislav Petkov 3223ed6101bbSJiri Olsa static int intel_pmu_bts_config(struct perf_event *event) 3224ed6101bbSJiri Olsa { 3225ed6101bbSJiri Olsa struct perf_event_attr *attr = &event->attr; 3226ed6101bbSJiri Olsa 322767266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) { 3228ed6101bbSJiri Olsa /* BTS is not supported by this architecture. */ 3229ed6101bbSJiri Olsa if (!x86_pmu.bts_active) 3230ed6101bbSJiri Olsa return -EOPNOTSUPP; 3231ed6101bbSJiri Olsa 3232ed6101bbSJiri Olsa /* BTS is currently only allowed for user-mode. */ 3233ed6101bbSJiri Olsa if (!attr->exclude_kernel) 3234ed6101bbSJiri Olsa return -EOPNOTSUPP; 3235ed6101bbSJiri Olsa 3236472de49fSJiri Olsa /* BTS is not allowed for precise events. */ 3237472de49fSJiri Olsa if (attr->precise_ip) 3238472de49fSJiri Olsa return -EOPNOTSUPP; 3239472de49fSJiri Olsa 3240ed6101bbSJiri Olsa /* disallow bts if conflicting events are present */ 3241ed6101bbSJiri Olsa if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3242ed6101bbSJiri Olsa return -EBUSY; 3243ed6101bbSJiri Olsa 3244ed6101bbSJiri Olsa event->destroy = hw_perf_lbr_event_destroy; 3245ed6101bbSJiri Olsa } 3246ed6101bbSJiri Olsa 3247ed6101bbSJiri Olsa return 0; 3248ed6101bbSJiri Olsa } 3249ed6101bbSJiri Olsa 3250ed6101bbSJiri Olsa static int core_pmu_hw_config(struct perf_event *event) 3251ed6101bbSJiri Olsa { 3252ed6101bbSJiri Olsa int ret = x86_pmu_hw_config(event); 3253ed6101bbSJiri Olsa 3254ed6101bbSJiri Olsa if (ret) 3255ed6101bbSJiri Olsa return ret; 3256ed6101bbSJiri Olsa 3257ed6101bbSJiri Olsa return intel_pmu_bts_config(event); 3258ed6101bbSJiri Olsa } 3259ed6101bbSJiri Olsa 3260e1069839SBorislav Petkov static int intel_pmu_hw_config(struct perf_event *event) 3261e1069839SBorislav Petkov { 3262e1069839SBorislav Petkov int ret = x86_pmu_hw_config(event); 3263e1069839SBorislav Petkov 3264e1069839SBorislav Petkov if (ret) 3265e1069839SBorislav Petkov return ret; 3266e1069839SBorislav Petkov 3267ed6101bbSJiri Olsa ret = intel_pmu_bts_config(event); 3268ed6101bbSJiri Olsa if (ret) 3269ed6101bbSJiri Olsa return ret; 3270ed6101bbSJiri Olsa 3271e1069839SBorislav Petkov if (event->attr.precise_ip) { 3272c7a28657SStephane Eranian if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3273e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3274e1069839SBorislav Petkov if (!(event->attr.sample_type & 3275174afc3eSKan Liang ~intel_pmu_large_pebs_flags(event))) 3276174afc3eSKan Liang event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3277e1069839SBorislav Petkov } 3278e1069839SBorislav Petkov if (x86_pmu.pebs_aliases) 3279e1069839SBorislav Petkov x86_pmu.pebs_aliases(event); 32806cbc304fSPeter Zijlstra 32816cbc304fSPeter Zijlstra if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 32826cbc304fSPeter Zijlstra event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3283e1069839SBorislav Petkov } 3284e1069839SBorislav Petkov 3285e1069839SBorislav Petkov if (needs_branch_stack(event)) { 3286e1069839SBorislav Petkov ret = intel_pmu_setup_lbr_filter(event); 3287e1069839SBorislav Petkov if (ret) 3288e1069839SBorislav Petkov return ret; 3289e1069839SBorislav Petkov 3290e1069839SBorislav Petkov /* 3291e1069839SBorislav Petkov * BTS is set up earlier in this path, so don't account twice 3292e1069839SBorislav Petkov */ 329367266c10SJiri Olsa if (!unlikely(intel_pmu_has_bts(event))) { 3294e1069839SBorislav Petkov /* disallow lbr if conflicting events are present */ 3295e1069839SBorislav Petkov if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3296e1069839SBorislav Petkov return -EBUSY; 3297e1069839SBorislav Petkov 3298e1069839SBorislav Petkov event->destroy = hw_perf_lbr_event_destroy; 3299e1069839SBorislav Petkov } 3300e1069839SBorislav Petkov } 3301e1069839SBorislav Petkov 330242880f72SAlexander Shishkin if (event->attr.aux_output) { 330342880f72SAlexander Shishkin if (!event->attr.precise_ip) 330442880f72SAlexander Shishkin return -EINVAL; 330542880f72SAlexander Shishkin 330642880f72SAlexander Shishkin event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 330742880f72SAlexander Shishkin } 330842880f72SAlexander Shishkin 3309e1069839SBorislav Petkov if (event->attr.type != PERF_TYPE_RAW) 3310e1069839SBorislav Petkov return 0; 3311e1069839SBorislav Petkov 3312e1069839SBorislav Petkov if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3313e1069839SBorislav Petkov return 0; 3314e1069839SBorislav Petkov 3315e1069839SBorislav Petkov if (x86_pmu.version < 3) 3316e1069839SBorislav Petkov return -EINVAL; 3317e1069839SBorislav Petkov 3318e1069839SBorislav Petkov if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) 3319e1069839SBorislav Petkov return -EACCES; 3320e1069839SBorislav Petkov 3321e1069839SBorislav Petkov event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3322e1069839SBorislav Petkov 3323e1069839SBorislav Petkov return 0; 3324e1069839SBorislav Petkov } 3325e1069839SBorislav Petkov 332674c504a6SAndrea Arcangeli #ifdef CONFIG_RETPOLINE 332774c504a6SAndrea Arcangeli static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr); 332874c504a6SAndrea Arcangeli static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr); 332974c504a6SAndrea Arcangeli #endif 333074c504a6SAndrea Arcangeli 3331e1069839SBorislav Petkov struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3332e1069839SBorislav Petkov { 333374c504a6SAndrea Arcangeli #ifdef CONFIG_RETPOLINE 333474c504a6SAndrea Arcangeli if (x86_pmu.guest_get_msrs == intel_guest_get_msrs) 333574c504a6SAndrea Arcangeli return intel_guest_get_msrs(nr); 333674c504a6SAndrea Arcangeli else if (x86_pmu.guest_get_msrs == core_guest_get_msrs) 333774c504a6SAndrea Arcangeli return core_guest_get_msrs(nr); 333874c504a6SAndrea Arcangeli #endif 3339e1069839SBorislav Petkov if (x86_pmu.guest_get_msrs) 3340e1069839SBorislav Petkov return x86_pmu.guest_get_msrs(nr); 3341e1069839SBorislav Petkov *nr = 0; 3342e1069839SBorislav Petkov return NULL; 3343e1069839SBorislav Petkov } 3344e1069839SBorislav Petkov EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3345e1069839SBorislav Petkov 3346e1069839SBorislav Petkov static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3347e1069839SBorislav Petkov { 3348e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3349e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3350e1069839SBorislav Petkov 3351e1069839SBorislav Petkov arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3352e1069839SBorislav Petkov arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3353e1069839SBorislav Petkov arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 33549b545c04SAndi Kleen if (x86_pmu.flags & PMU_FL_PEBS_ALL) 33559b545c04SAndi Kleen arr[0].guest &= ~cpuc->pebs_enabled; 33569b545c04SAndi Kleen else 33579b545c04SAndi Kleen arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 33589b545c04SAndi Kleen *nr = 1; 33599b545c04SAndi Kleen 33609b545c04SAndi Kleen if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3361e1069839SBorislav Petkov /* 33629b545c04SAndi Kleen * If PMU counter has PEBS enabled it is not enough to 33639b545c04SAndi Kleen * disable counter on a guest entry since PEBS memory 33649b545c04SAndi Kleen * write can overshoot guest entry and corrupt guest 33659b545c04SAndi Kleen * memory. Disabling PEBS solves the problem. 33669b545c04SAndi Kleen * 33679b545c04SAndi Kleen * Don't do this if the CPU already enforces it. 3368e1069839SBorislav Petkov */ 3369e1069839SBorislav Petkov arr[1].msr = MSR_IA32_PEBS_ENABLE; 3370e1069839SBorislav Petkov arr[1].host = cpuc->pebs_enabled; 3371e1069839SBorislav Petkov arr[1].guest = 0; 3372e1069839SBorislav Petkov *nr = 2; 33739b545c04SAndi Kleen } 33749b545c04SAndi Kleen 3375e1069839SBorislav Petkov return arr; 3376e1069839SBorislav Petkov } 3377e1069839SBorislav Petkov 3378e1069839SBorislav Petkov static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3379e1069839SBorislav Petkov { 3380e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3381e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3382e1069839SBorislav Petkov int idx; 3383e1069839SBorislav Petkov 3384e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3385e1069839SBorislav Petkov struct perf_event *event = cpuc->events[idx]; 3386e1069839SBorislav Petkov 3387e1069839SBorislav Petkov arr[idx].msr = x86_pmu_config_addr(idx); 3388e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 0; 3389e1069839SBorislav Petkov 3390e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) 3391e1069839SBorislav Petkov continue; 3392e1069839SBorislav Petkov 3393e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 3394e1069839SBorislav Petkov event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3395e1069839SBorislav Petkov 3396e1069839SBorislav Petkov if (event->attr.exclude_host) 3397e1069839SBorislav Petkov arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3398e1069839SBorislav Petkov else if (event->attr.exclude_guest) 3399e1069839SBorislav Petkov arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3400e1069839SBorislav Petkov } 3401e1069839SBorislav Petkov 3402e1069839SBorislav Petkov *nr = x86_pmu.num_counters; 3403e1069839SBorislav Petkov return arr; 3404e1069839SBorislav Petkov } 3405e1069839SBorislav Petkov 3406e1069839SBorislav Petkov static void core_pmu_enable_event(struct perf_event *event) 3407e1069839SBorislav Petkov { 3408e1069839SBorislav Petkov if (!event->attr.exclude_host) 3409e1069839SBorislav Petkov x86_pmu_enable_event(event); 3410e1069839SBorislav Petkov } 3411e1069839SBorislav Petkov 3412e1069839SBorislav Petkov static void core_pmu_enable_all(int added) 3413e1069839SBorislav Petkov { 3414e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3415e1069839SBorislav Petkov int idx; 3416e1069839SBorislav Petkov 3417e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3418e1069839SBorislav Petkov struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3419e1069839SBorislav Petkov 3420e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask) || 3421e1069839SBorislav Petkov cpuc->events[idx]->attr.exclude_host) 3422e1069839SBorislav Petkov continue; 3423e1069839SBorislav Petkov 3424e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3425e1069839SBorislav Petkov } 3426e1069839SBorislav Petkov } 3427e1069839SBorislav Petkov 3428e1069839SBorislav Petkov static int hsw_hw_config(struct perf_event *event) 3429e1069839SBorislav Petkov { 3430e1069839SBorislav Petkov int ret = intel_pmu_hw_config(event); 3431e1069839SBorislav Petkov 3432e1069839SBorislav Petkov if (ret) 3433e1069839SBorislav Petkov return ret; 3434e1069839SBorislav Petkov if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3435e1069839SBorislav Petkov return 0; 3436e1069839SBorislav Petkov event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3437e1069839SBorislav Petkov 3438e1069839SBorislav Petkov /* 3439e1069839SBorislav Petkov * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3440e1069839SBorislav Petkov * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3441e1069839SBorislav Petkov * this combination. 3442e1069839SBorislav Petkov */ 3443e1069839SBorislav Petkov if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3444e1069839SBorislav Petkov ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3445e1069839SBorislav Petkov event->attr.precise_ip > 0)) 3446e1069839SBorislav Petkov return -EOPNOTSUPP; 3447e1069839SBorislav Petkov 3448e1069839SBorislav Petkov if (event_is_checkpointed(event)) { 3449e1069839SBorislav Petkov /* 3450e1069839SBorislav Petkov * Sampling of checkpointed events can cause situations where 3451e1069839SBorislav Petkov * the CPU constantly aborts because of a overflow, which is 3452e1069839SBorislav Petkov * then checkpointed back and ignored. Forbid checkpointing 3453e1069839SBorislav Petkov * for sampling. 3454e1069839SBorislav Petkov * 3455e1069839SBorislav Petkov * But still allow a long sampling period, so that perf stat 3456e1069839SBorislav Petkov * from KVM works. 3457e1069839SBorislav Petkov */ 3458e1069839SBorislav Petkov if (event->attr.sample_period > 0 && 3459e1069839SBorislav Petkov event->attr.sample_period < 0x7fffffff) 3460e1069839SBorislav Petkov return -EOPNOTSUPP; 3461e1069839SBorislav Petkov } 3462e1069839SBorislav Petkov return 0; 3463e1069839SBorislav Petkov } 3464e1069839SBorislav Petkov 3465dd0b06b5SKan Liang static struct event_constraint counter0_constraint = 3466dd0b06b5SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3467dd0b06b5SKan Liang 3468e1069839SBorislav Petkov static struct event_constraint counter2_constraint = 3469e1069839SBorislav Petkov EVENT_CONSTRAINT(0, 0x4, 0); 3470e1069839SBorislav Petkov 347160176089SKan Liang static struct event_constraint fixed0_constraint = 347260176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0); 347360176089SKan Liang 34746daeb873SKan Liang static struct event_constraint fixed0_counter0_constraint = 34756daeb873SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 34766daeb873SKan Liang 3477e1069839SBorislav Petkov static struct event_constraint * 3478e1069839SBorislav Petkov hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3479e1069839SBorislav Petkov struct perf_event *event) 3480e1069839SBorislav Petkov { 3481e1069839SBorislav Petkov struct event_constraint *c; 3482e1069839SBorislav Petkov 3483e1069839SBorislav Petkov c = intel_get_event_constraints(cpuc, idx, event); 3484e1069839SBorislav Petkov 3485e1069839SBorislav Petkov /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3486e1069839SBorislav Petkov if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3487e1069839SBorislav Petkov if (c->idxmsk64 & (1U << 2)) 3488e1069839SBorislav Petkov return &counter2_constraint; 3489e1069839SBorislav Petkov return &emptyconstraint; 3490e1069839SBorislav Petkov } 3491e1069839SBorislav Petkov 3492e1069839SBorislav Petkov return c; 3493e1069839SBorislav Petkov } 3494e1069839SBorislav Petkov 3495dd0b06b5SKan Liang static struct event_constraint * 349660176089SKan Liang icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 349760176089SKan Liang struct perf_event *event) 349860176089SKan Liang { 349960176089SKan Liang /* 350060176089SKan Liang * Fixed counter 0 has less skid. 350160176089SKan Liang * Force instruction:ppp in Fixed counter 0 350260176089SKan Liang */ 350360176089SKan Liang if ((event->attr.precise_ip == 3) && 350460176089SKan Liang constraint_match(&fixed0_constraint, event->hw.config)) 350560176089SKan Liang return &fixed0_constraint; 350660176089SKan Liang 350760176089SKan Liang return hsw_get_event_constraints(cpuc, idx, event); 350860176089SKan Liang } 350960176089SKan Liang 351060176089SKan Liang static struct event_constraint * 3511dd0b06b5SKan Liang glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3512dd0b06b5SKan Liang struct perf_event *event) 3513dd0b06b5SKan Liang { 3514dd0b06b5SKan Liang struct event_constraint *c; 3515dd0b06b5SKan Liang 3516dd0b06b5SKan Liang /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3517dd0b06b5SKan Liang if (event->attr.precise_ip == 3) 3518dd0b06b5SKan Liang return &counter0_constraint; 3519dd0b06b5SKan Liang 3520dd0b06b5SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 3521dd0b06b5SKan Liang 3522dd0b06b5SKan Liang return c; 3523dd0b06b5SKan Liang } 3524dd0b06b5SKan Liang 35256daeb873SKan Liang static struct event_constraint * 35266daeb873SKan Liang tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 35276daeb873SKan Liang struct perf_event *event) 35286daeb873SKan Liang { 35296daeb873SKan Liang struct event_constraint *c; 35306daeb873SKan Liang 35316daeb873SKan Liang /* 35326daeb873SKan Liang * :ppp means to do reduced skid PEBS, 35336daeb873SKan Liang * which is available on PMC0 and fixed counter 0. 35346daeb873SKan Liang */ 35356daeb873SKan Liang if (event->attr.precise_ip == 3) { 35366daeb873SKan Liang /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 35376daeb873SKan Liang if (constraint_match(&fixed0_constraint, event->hw.config)) 35386daeb873SKan Liang return &fixed0_counter0_constraint; 35396daeb873SKan Liang 35406daeb873SKan Liang return &counter0_constraint; 35416daeb873SKan Liang } 35426daeb873SKan Liang 35436daeb873SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 35446daeb873SKan Liang 35456daeb873SKan Liang return c; 35466daeb873SKan Liang } 35476daeb873SKan Liang 3548400816f6SPeter Zijlstra (Intel) static bool allow_tsx_force_abort = true; 3549400816f6SPeter Zijlstra (Intel) 3550400816f6SPeter Zijlstra (Intel) static struct event_constraint * 3551400816f6SPeter Zijlstra (Intel) tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3552400816f6SPeter Zijlstra (Intel) struct perf_event *event) 3553400816f6SPeter Zijlstra (Intel) { 3554400816f6SPeter Zijlstra (Intel) struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 3555400816f6SPeter Zijlstra (Intel) 3556400816f6SPeter Zijlstra (Intel) /* 3557400816f6SPeter Zijlstra (Intel) * Without TFA we must not use PMC3. 3558400816f6SPeter Zijlstra (Intel) */ 355921d65555SPeter Zijlstra if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 3560400816f6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 3561400816f6SPeter Zijlstra (Intel) c->idxmsk64 &= ~(1ULL << 3); 3562400816f6SPeter Zijlstra (Intel) c->weight--; 3563400816f6SPeter Zijlstra (Intel) } 3564400816f6SPeter Zijlstra (Intel) 3565400816f6SPeter Zijlstra (Intel) return c; 3566400816f6SPeter Zijlstra (Intel) } 3567400816f6SPeter Zijlstra (Intel) 3568e1069839SBorislav Petkov /* 3569e1069839SBorislav Petkov * Broadwell: 3570e1069839SBorislav Petkov * 3571e1069839SBorislav Petkov * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3572e1069839SBorislav Petkov * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3573e1069839SBorislav Petkov * the two to enforce a minimum period of 128 (the smallest value that has bits 3574e1069839SBorislav Petkov * 0-5 cleared and >= 100). 3575e1069839SBorislav Petkov * 3576e1069839SBorislav Petkov * Because of how the code in x86_perf_event_set_period() works, the truncation 3577e1069839SBorislav Petkov * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3578e1069839SBorislav Petkov * to make up for the 'lost' events due to carrying the 'error' in period_left. 3579e1069839SBorislav Petkov * 3580e1069839SBorislav Petkov * Therefore the effective (average) period matches the requested period, 3581e1069839SBorislav Petkov * despite coarser hardware granularity. 3582e1069839SBorislav Petkov */ 3583f605cfcaSKan Liang static u64 bdw_limit_period(struct perf_event *event, u64 left) 3584e1069839SBorislav Petkov { 3585e1069839SBorislav Petkov if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3586e1069839SBorislav Petkov X86_CONFIG(.event=0xc0, .umask=0x01)) { 3587e1069839SBorislav Petkov if (left < 128) 3588e1069839SBorislav Petkov left = 128; 3589e5ea9b54SDan Carpenter left &= ~0x3fULL; 3590e1069839SBorislav Petkov } 3591e1069839SBorislav Petkov return left; 3592e1069839SBorislav Petkov } 3593e1069839SBorislav Petkov 359444d3bbb6SJosh Hunt static u64 nhm_limit_period(struct perf_event *event, u64 left) 359544d3bbb6SJosh Hunt { 359644d3bbb6SJosh Hunt return max(left, 32ULL); 359744d3bbb6SJosh Hunt } 359844d3bbb6SJosh Hunt 3599e1069839SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 3600e1069839SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 3601e1069839SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 3602e1069839SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 3603e1069839SBorislav Petkov PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3604e1069839SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 3605e1069839SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3606e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx, "config:32"); 3607e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3608e1069839SBorislav Petkov 3609e1069839SBorislav Petkov static struct attribute *intel_arch_formats_attr[] = { 3610e1069839SBorislav Petkov &format_attr_event.attr, 3611e1069839SBorislav Petkov &format_attr_umask.attr, 3612e1069839SBorislav Petkov &format_attr_edge.attr, 3613e1069839SBorislav Petkov &format_attr_pc.attr, 3614e1069839SBorislav Petkov &format_attr_inv.attr, 3615e1069839SBorislav Petkov &format_attr_cmask.attr, 3616e1069839SBorislav Petkov NULL, 3617e1069839SBorislav Petkov }; 3618e1069839SBorislav Petkov 3619e1069839SBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config) 3620e1069839SBorislav Petkov { 3621e1069839SBorislav Petkov u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3622e1069839SBorislav Petkov 3623e1069839SBorislav Petkov return x86_event_sysfs_show(page, config, event); 3624e1069839SBorislav Petkov } 3625e1069839SBorislav Petkov 3626d01b1f96SPeter Zijlstra (Intel) static struct intel_shared_regs *allocate_shared_regs(int cpu) 3627e1069839SBorislav Petkov { 3628e1069839SBorislav Petkov struct intel_shared_regs *regs; 3629e1069839SBorislav Petkov int i; 3630e1069839SBorislav Petkov 3631e1069839SBorislav Petkov regs = kzalloc_node(sizeof(struct intel_shared_regs), 3632e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3633e1069839SBorislav Petkov if (regs) { 3634e1069839SBorislav Petkov /* 3635e1069839SBorislav Petkov * initialize the locks to keep lockdep happy 3636e1069839SBorislav Petkov */ 3637e1069839SBorislav Petkov for (i = 0; i < EXTRA_REG_MAX; i++) 3638e1069839SBorislav Petkov raw_spin_lock_init(®s->regs[i].lock); 3639e1069839SBorislav Petkov 3640e1069839SBorislav Petkov regs->core_id = -1; 3641e1069839SBorislav Petkov } 3642e1069839SBorislav Petkov return regs; 3643e1069839SBorislav Petkov } 3644e1069839SBorislav Petkov 3645e1069839SBorislav Petkov static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3646e1069839SBorislav Petkov { 3647e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3648e1069839SBorislav Petkov 3649e1069839SBorislav Petkov c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3650e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3651e1069839SBorislav Petkov if (c) { 3652e1069839SBorislav Petkov raw_spin_lock_init(&c->lock); 3653e1069839SBorislav Petkov c->core_id = -1; 3654e1069839SBorislav Petkov } 3655e1069839SBorislav Petkov return c; 3656e1069839SBorislav Petkov } 3657e1069839SBorislav Petkov 3658e1069839SBorislav Petkov 3659d01b1f96SPeter Zijlstra (Intel) int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 3660d01b1f96SPeter Zijlstra (Intel) { 3661c22497f5SKan Liang cpuc->pebs_record_size = x86_pmu.pebs_record_size; 3662c22497f5SKan Liang 3663e1069839SBorislav Petkov if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 3664e1069839SBorislav Petkov cpuc->shared_regs = allocate_shared_regs(cpu); 3665e1069839SBorislav Petkov if (!cpuc->shared_regs) 3666e1069839SBorislav Petkov goto err; 3667e1069839SBorislav Petkov } 3668e1069839SBorislav Petkov 3669400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 3670e1069839SBorislav Petkov size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 3671e1069839SBorislav Petkov 3672d01b1f96SPeter Zijlstra (Intel) cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 3673e1069839SBorislav Petkov if (!cpuc->constraint_list) 3674e1069839SBorislav Petkov goto err_shared_regs; 3675400816f6SPeter Zijlstra (Intel) } 3676e1069839SBorislav Petkov 3677400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3678e1069839SBorislav Petkov cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 3679e1069839SBorislav Petkov if (!cpuc->excl_cntrs) 3680e1069839SBorislav Petkov goto err_constraint_list; 3681e1069839SBorislav Petkov 3682e1069839SBorislav Petkov cpuc->excl_thread_id = 0; 3683e1069839SBorislav Petkov } 3684e1069839SBorislav Petkov 368595ca792cSThomas Gleixner return 0; 3686e1069839SBorislav Petkov 3687e1069839SBorislav Petkov err_constraint_list: 3688e1069839SBorislav Petkov kfree(cpuc->constraint_list); 3689e1069839SBorislav Petkov cpuc->constraint_list = NULL; 3690e1069839SBorislav Petkov 3691e1069839SBorislav Petkov err_shared_regs: 3692e1069839SBorislav Petkov kfree(cpuc->shared_regs); 3693e1069839SBorislav Petkov cpuc->shared_regs = NULL; 3694e1069839SBorislav Petkov 3695e1069839SBorislav Petkov err: 369695ca792cSThomas Gleixner return -ENOMEM; 3697e1069839SBorislav Petkov } 3698e1069839SBorislav Petkov 3699d01b1f96SPeter Zijlstra (Intel) static int intel_pmu_cpu_prepare(int cpu) 3700d01b1f96SPeter Zijlstra (Intel) { 3701d01b1f96SPeter Zijlstra (Intel) return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 3702d01b1f96SPeter Zijlstra (Intel) } 3703d01b1f96SPeter Zijlstra (Intel) 37046089327fSKan Liang static void flip_smm_bit(void *data) 37056089327fSKan Liang { 37066089327fSKan Liang unsigned long set = *(unsigned long *)data; 37076089327fSKan Liang 37086089327fSKan Liang if (set > 0) { 37096089327fSKan Liang msr_set_bit(MSR_IA32_DEBUGCTLMSR, 37106089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 37116089327fSKan Liang } else { 37126089327fSKan Liang msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 37136089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 37146089327fSKan Liang } 37156089327fSKan Liang } 37166089327fSKan Liang 3717e1069839SBorislav Petkov static void intel_pmu_cpu_starting(int cpu) 3718e1069839SBorislav Petkov { 3719e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 3720e1069839SBorislav Petkov int core_id = topology_core_id(cpu); 3721e1069839SBorislav Petkov int i; 3722e1069839SBorislav Petkov 3723e1069839SBorislav Petkov init_debug_store_on_cpu(cpu); 3724e1069839SBorislav Petkov /* 3725e1069839SBorislav Petkov * Deal with CPUs that don't clear their LBRs on power-up. 3726e1069839SBorislav Petkov */ 3727e1069839SBorislav Petkov intel_pmu_lbr_reset(); 3728e1069839SBorislav Petkov 3729e1069839SBorislav Petkov cpuc->lbr_sel = NULL; 3730e1069839SBorislav Petkov 3731d7262457SPeter Zijlstra if (x86_pmu.flags & PMU_FL_TFA) { 3732d7262457SPeter Zijlstra WARN_ON_ONCE(cpuc->tfa_shadow); 3733d7262457SPeter Zijlstra cpuc->tfa_shadow = ~0ULL; 3734d7262457SPeter Zijlstra intel_set_tfa(cpuc, false); 3735d7262457SPeter Zijlstra } 3736d7262457SPeter Zijlstra 37374e949e9bSKan Liang if (x86_pmu.version > 1) 37386089327fSKan Liang flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 37396089327fSKan Liang 3740af3bdb99SAndi Kleen if (x86_pmu.counter_freezing) 3741af3bdb99SAndi Kleen enable_counter_freeze(); 3742af3bdb99SAndi Kleen 3743e1069839SBorislav Petkov if (!cpuc->shared_regs) 3744e1069839SBorislav Petkov return; 3745e1069839SBorislav Petkov 3746e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 3747e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 3748e1069839SBorislav Petkov struct intel_shared_regs *pc; 3749e1069839SBorislav Petkov 3750e1069839SBorislav Petkov pc = per_cpu(cpu_hw_events, i).shared_regs; 3751e1069839SBorislav Petkov if (pc && pc->core_id == core_id) { 3752e1069839SBorislav Petkov cpuc->kfree_on_online[0] = cpuc->shared_regs; 3753e1069839SBorislav Petkov cpuc->shared_regs = pc; 3754e1069839SBorislav Petkov break; 3755e1069839SBorislav Petkov } 3756e1069839SBorislav Petkov } 3757e1069839SBorislav Petkov cpuc->shared_regs->core_id = core_id; 3758e1069839SBorislav Petkov cpuc->shared_regs->refcnt++; 3759e1069839SBorislav Petkov } 3760e1069839SBorislav Petkov 3761e1069839SBorislav Petkov if (x86_pmu.lbr_sel_map) 3762e1069839SBorislav Petkov cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 3763e1069839SBorislav Petkov 3764e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 3765e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 37664e71de79SZhou Chengming struct cpu_hw_events *sibling; 3767e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3768e1069839SBorislav Petkov 37694e71de79SZhou Chengming sibling = &per_cpu(cpu_hw_events, i); 37704e71de79SZhou Chengming c = sibling->excl_cntrs; 3771e1069839SBorislav Petkov if (c && c->core_id == core_id) { 3772e1069839SBorislav Petkov cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 3773e1069839SBorislav Petkov cpuc->excl_cntrs = c; 37744e71de79SZhou Chengming if (!sibling->excl_thread_id) 3775e1069839SBorislav Petkov cpuc->excl_thread_id = 1; 3776e1069839SBorislav Petkov break; 3777e1069839SBorislav Petkov } 3778e1069839SBorislav Petkov } 3779e1069839SBorislav Petkov cpuc->excl_cntrs->core_id = core_id; 3780e1069839SBorislav Petkov cpuc->excl_cntrs->refcnt++; 3781e1069839SBorislav Petkov } 3782e1069839SBorislav Petkov } 3783e1069839SBorislav Petkov 3784d01b1f96SPeter Zijlstra (Intel) static void free_excl_cntrs(struct cpu_hw_events *cpuc) 3785e1069839SBorislav Petkov { 3786e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3787e1069839SBorislav Petkov 3788e1069839SBorislav Petkov c = cpuc->excl_cntrs; 3789e1069839SBorislav Petkov if (c) { 3790e1069839SBorislav Petkov if (c->core_id == -1 || --c->refcnt == 0) 3791e1069839SBorislav Petkov kfree(c); 3792e1069839SBorislav Petkov cpuc->excl_cntrs = NULL; 3793400816f6SPeter Zijlstra (Intel) } 3794400816f6SPeter Zijlstra (Intel) 3795e1069839SBorislav Petkov kfree(cpuc->constraint_list); 3796e1069839SBorislav Petkov cpuc->constraint_list = NULL; 3797e1069839SBorislav Petkov } 3798e1069839SBorislav Petkov 3799e1069839SBorislav Petkov static void intel_pmu_cpu_dying(int cpu) 3800e1069839SBorislav Petkov { 3801602cae04SPeter Zijlstra fini_debug_store_on_cpu(cpu); 3802602cae04SPeter Zijlstra 3803602cae04SPeter Zijlstra if (x86_pmu.counter_freezing) 3804602cae04SPeter Zijlstra disable_counter_freeze(); 3805602cae04SPeter Zijlstra } 3806602cae04SPeter Zijlstra 3807d01b1f96SPeter Zijlstra (Intel) void intel_cpuc_finish(struct cpu_hw_events *cpuc) 3808602cae04SPeter Zijlstra { 3809e1069839SBorislav Petkov struct intel_shared_regs *pc; 3810e1069839SBorislav Petkov 3811e1069839SBorislav Petkov pc = cpuc->shared_regs; 3812e1069839SBorislav Petkov if (pc) { 3813e1069839SBorislav Petkov if (pc->core_id == -1 || --pc->refcnt == 0) 3814e1069839SBorislav Petkov kfree(pc); 3815e1069839SBorislav Petkov cpuc->shared_regs = NULL; 3816e1069839SBorislav Petkov } 3817e1069839SBorislav Petkov 3818d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(cpuc); 3819d01b1f96SPeter Zijlstra (Intel) } 3820d01b1f96SPeter Zijlstra (Intel) 3821d01b1f96SPeter Zijlstra (Intel) static void intel_pmu_cpu_dead(int cpu) 3822d01b1f96SPeter Zijlstra (Intel) { 3823d01b1f96SPeter Zijlstra (Intel) intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu)); 3824e1069839SBorislav Petkov } 3825e1069839SBorislav Petkov 3826e1069839SBorislav Petkov static void intel_pmu_sched_task(struct perf_event_context *ctx, 3827e1069839SBorislav Petkov bool sched_in) 3828e1069839SBorislav Petkov { 3829e1069839SBorislav Petkov intel_pmu_pebs_sched_task(ctx, sched_in); 3830e1069839SBorislav Petkov intel_pmu_lbr_sched_task(ctx, sched_in); 3831e1069839SBorislav Petkov } 3832e1069839SBorislav Petkov 383381ec3f3cSJiri Olsa static int intel_pmu_check_period(struct perf_event *event, u64 value) 383481ec3f3cSJiri Olsa { 383581ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 383681ec3f3cSJiri Olsa } 383781ec3f3cSJiri Olsa 383842880f72SAlexander Shishkin static int intel_pmu_aux_output_match(struct perf_event *event) 383942880f72SAlexander Shishkin { 384042880f72SAlexander Shishkin if (!x86_pmu.intel_cap.pebs_output_pt_available) 384142880f72SAlexander Shishkin return 0; 384242880f72SAlexander Shishkin 384342880f72SAlexander Shishkin return is_intel_pt_event(event); 384442880f72SAlexander Shishkin } 384542880f72SAlexander Shishkin 3846e1069839SBorislav Petkov PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 3847e1069839SBorislav Petkov 3848e1069839SBorislav Petkov PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 3849e1069839SBorislav Petkov 3850e1069839SBorislav Petkov PMU_FORMAT_ATTR(frontend, "config1:0-23"); 3851e1069839SBorislav Petkov 3852e1069839SBorislav Petkov static struct attribute *intel_arch3_formats_attr[] = { 3853e1069839SBorislav Petkov &format_attr_event.attr, 3854e1069839SBorislav Petkov &format_attr_umask.attr, 3855e1069839SBorislav Petkov &format_attr_edge.attr, 3856e1069839SBorislav Petkov &format_attr_pc.attr, 3857e1069839SBorislav Petkov &format_attr_any.attr, 3858e1069839SBorislav Petkov &format_attr_inv.attr, 3859e1069839SBorislav Petkov &format_attr_cmask.attr, 3860a5df70c3SAndi Kleen NULL, 3861a5df70c3SAndi Kleen }; 3862a5df70c3SAndi Kleen 3863a5df70c3SAndi Kleen static struct attribute *hsw_format_attr[] = { 3864e1069839SBorislav Petkov &format_attr_in_tx.attr, 3865e1069839SBorislav Petkov &format_attr_in_tx_cp.attr, 3866a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3867a5df70c3SAndi Kleen &format_attr_ldlat.attr, 3868a5df70c3SAndi Kleen NULL 3869a5df70c3SAndi Kleen }; 3870e1069839SBorislav Petkov 3871a5df70c3SAndi Kleen static struct attribute *nhm_format_attr[] = { 3872a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3873a5df70c3SAndi Kleen &format_attr_ldlat.attr, 3874a5df70c3SAndi Kleen NULL 3875a5df70c3SAndi Kleen }; 3876a5df70c3SAndi Kleen 3877a5df70c3SAndi Kleen static struct attribute *slm_format_attr[] = { 3878a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 3879a5df70c3SAndi Kleen NULL 3880e1069839SBorislav Petkov }; 3881e1069839SBorislav Petkov 3882e1069839SBorislav Petkov static struct attribute *skl_format_attr[] = { 3883e1069839SBorislav Petkov &format_attr_frontend.attr, 3884e1069839SBorislav Petkov NULL, 3885e1069839SBorislav Petkov }; 3886e1069839SBorislav Petkov 3887e1069839SBorislav Petkov static __initconst const struct x86_pmu core_pmu = { 3888e1069839SBorislav Petkov .name = "core", 3889e1069839SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 3890e1069839SBorislav Petkov .disable_all = x86_pmu_disable_all, 3891e1069839SBorislav Petkov .enable_all = core_pmu_enable_all, 3892e1069839SBorislav Petkov .enable = core_pmu_enable_event, 3893e1069839SBorislav Petkov .disable = x86_pmu_disable_event, 3894ed6101bbSJiri Olsa .hw_config = core_pmu_hw_config, 3895e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 3896e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3897e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3898e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 3899e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3900e1069839SBorislav Petkov .apic = 1, 3901174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 3902e1069839SBorislav Petkov 3903e1069839SBorislav Petkov /* 3904e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32-bit width, 3905e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 3906e1069839SBorislav Petkov * the generic event period: 3907e1069839SBorislav Petkov */ 3908e1069839SBorislav Petkov .max_period = (1ULL<<31) - 1, 3909e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 3910e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 3911e1069839SBorislav Petkov .event_constraints = intel_core_event_constraints, 3912e1069839SBorislav Petkov .guest_get_msrs = core_guest_get_msrs, 3913e1069839SBorislav Petkov .format_attrs = intel_arch_formats_attr, 3914e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 3915e1069839SBorislav Petkov 3916e1069839SBorislav Petkov /* 3917e1069839SBorislav Petkov * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 3918e1069839SBorislav Petkov * together with PMU version 1 and thus be using core_pmu with 3919e1069839SBorislav Petkov * shared_regs. We need following callbacks here to allocate 3920e1069839SBorislav Petkov * it properly. 3921e1069839SBorislav Petkov */ 3922e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 3923e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 3924e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 3925602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 392681ec3f3cSJiri Olsa 392781ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 3928e1069839SBorislav Petkov }; 3929e1069839SBorislav Petkov 3930e1069839SBorislav Petkov static __initconst const struct x86_pmu intel_pmu = { 3931e1069839SBorislav Petkov .name = "Intel", 3932e1069839SBorislav Petkov .handle_irq = intel_pmu_handle_irq, 3933e1069839SBorislav Petkov .disable_all = intel_pmu_disable_all, 3934e1069839SBorislav Petkov .enable_all = intel_pmu_enable_all, 3935e1069839SBorislav Petkov .enable = intel_pmu_enable_event, 3936e1069839SBorislav Petkov .disable = intel_pmu_disable_event, 393768f7082fSPeter Zijlstra .add = intel_pmu_add_event, 393868f7082fSPeter Zijlstra .del = intel_pmu_del_event, 3939ceb90d9eSKan Liang .read = intel_pmu_read_event, 3940e1069839SBorislav Petkov .hw_config = intel_pmu_hw_config, 3941e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 3942e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 3943e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 3944e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 3945e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3946e1069839SBorislav Petkov .apic = 1, 3947174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 3948e1069839SBorislav Petkov /* 3949e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32 bit width, 3950e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 3951e1069839SBorislav Petkov * the generic event period: 3952e1069839SBorislav Petkov */ 3953e1069839SBorislav Petkov .max_period = (1ULL << 31) - 1, 3954e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 3955e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 3956e1069839SBorislav Petkov .pebs_aliases = intel_pebs_aliases_core2, 3957e1069839SBorislav Petkov 3958e1069839SBorislav Petkov .format_attrs = intel_arch3_formats_attr, 3959e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 3960e1069839SBorislav Petkov 3961e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 3962e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 3963e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 3964602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 3965602cae04SPeter Zijlstra 3966e1069839SBorislav Petkov .guest_get_msrs = intel_guest_get_msrs, 3967e1069839SBorislav Petkov .sched_task = intel_pmu_sched_task, 396881ec3f3cSJiri Olsa 396981ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 397042880f72SAlexander Shishkin 397142880f72SAlexander Shishkin .aux_output_match = intel_pmu_aux_output_match, 3972e1069839SBorislav Petkov }; 3973e1069839SBorislav Petkov 3974e1069839SBorislav Petkov static __init void intel_clovertown_quirk(void) 3975e1069839SBorislav Petkov { 3976e1069839SBorislav Petkov /* 3977e1069839SBorislav Petkov * PEBS is unreliable due to: 3978e1069839SBorislav Petkov * 3979e1069839SBorislav Petkov * AJ67 - PEBS may experience CPL leaks 3980e1069839SBorislav Petkov * AJ68 - PEBS PMI may be delayed by one event 3981e1069839SBorislav Petkov * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 3982e1069839SBorislav Petkov * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 3983e1069839SBorislav Petkov * 3984e1069839SBorislav Petkov * AJ67 could be worked around by restricting the OS/USR flags. 3985e1069839SBorislav Petkov * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 3986e1069839SBorislav Petkov * 3987e1069839SBorislav Petkov * AJ106 could possibly be worked around by not allowing LBR 3988e1069839SBorislav Petkov * usage from PEBS, including the fixup. 3989e1069839SBorislav Petkov * AJ68 could possibly be worked around by always programming 3990e1069839SBorislav Petkov * a pebs_event_reset[0] value and coping with the lost events. 3991e1069839SBorislav Petkov * 3992e1069839SBorislav Petkov * But taken together it might just make sense to not enable PEBS on 3993e1069839SBorislav Petkov * these chips. 3994e1069839SBorislav Petkov */ 3995e1069839SBorislav Petkov pr_warn("PEBS disabled due to CPU errata\n"); 3996e1069839SBorislav Petkov x86_pmu.pebs = 0; 3997e1069839SBorislav Petkov x86_pmu.pebs_constraints = NULL; 3998e1069839SBorislav Petkov } 3999e1069839SBorislav Petkov 40009b545c04SAndi Kleen static const struct x86_cpu_desc isolation_ucodes[] = { 4001c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4002af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 40035e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 40049b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 40059b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4006c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 40075e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 40085ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 40095ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 40105ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 40115ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 40129b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014), 40139b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 40149b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4015af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4016c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4017c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4018af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4019af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4020af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4021af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4022c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4023c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4024c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4025c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 40269b545c04SAndi Kleen {} 40279b545c04SAndi Kleen }; 40289b545c04SAndi Kleen 40299b545c04SAndi Kleen static void intel_check_pebs_isolation(void) 40309b545c04SAndi Kleen { 40319b545c04SAndi Kleen x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 40329b545c04SAndi Kleen } 40339b545c04SAndi Kleen 40349b545c04SAndi Kleen static __init void intel_pebs_isolation_quirk(void) 40359b545c04SAndi Kleen { 40369b545c04SAndi Kleen WARN_ON_ONCE(x86_pmu.check_microcode); 40379b545c04SAndi Kleen x86_pmu.check_microcode = intel_check_pebs_isolation; 40389b545c04SAndi Kleen intel_check_pebs_isolation(); 40399b545c04SAndi Kleen } 40409b545c04SAndi Kleen 4041a96fff8dSKan Liang static const struct x86_cpu_desc pebs_ucodes[] = { 4042a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4043a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4044a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4045a96fff8dSKan Liang {} 4046a96fff8dSKan Liang }; 4047a96fff8dSKan Liang 4048a96fff8dSKan Liang static bool intel_snb_pebs_broken(void) 4049e1069839SBorislav Petkov { 4050a96fff8dSKan Liang return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4051e1069839SBorislav Petkov } 4052e1069839SBorislav Petkov 4053e1069839SBorislav Petkov static void intel_snb_check_microcode(void) 4054e1069839SBorislav Petkov { 4055a96fff8dSKan Liang if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4056e1069839SBorislav Petkov return; 4057e1069839SBorislav Petkov 4058e1069839SBorislav Petkov /* 4059e1069839SBorislav Petkov * Serialized by the microcode lock.. 4060e1069839SBorislav Petkov */ 4061e1069839SBorislav Petkov if (x86_pmu.pebs_broken) { 4062e1069839SBorislav Petkov pr_info("PEBS enabled due to microcode update\n"); 4063e1069839SBorislav Petkov x86_pmu.pebs_broken = 0; 4064e1069839SBorislav Petkov } else { 4065e1069839SBorislav Petkov pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4066e1069839SBorislav Petkov x86_pmu.pebs_broken = 1; 4067e1069839SBorislav Petkov } 4068e1069839SBorislav Petkov } 4069e1069839SBorislav Petkov 407019fc9dddSDavid Carrillo-Cisneros static bool is_lbr_from(unsigned long msr) 407119fc9dddSDavid Carrillo-Cisneros { 407219fc9dddSDavid Carrillo-Cisneros unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 407319fc9dddSDavid Carrillo-Cisneros 407419fc9dddSDavid Carrillo-Cisneros return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 407519fc9dddSDavid Carrillo-Cisneros } 407619fc9dddSDavid Carrillo-Cisneros 4077e1069839SBorislav Petkov /* 4078e1069839SBorislav Petkov * Under certain circumstances, access certain MSR may cause #GP. 4079e1069839SBorislav Petkov * The function tests if the input MSR can be safely accessed. 4080e1069839SBorislav Petkov */ 4081e1069839SBorislav Petkov static bool check_msr(unsigned long msr, u64 mask) 4082e1069839SBorislav Petkov { 4083e1069839SBorislav Petkov u64 val_old, val_new, val_tmp; 4084e1069839SBorislav Petkov 4085e1069839SBorislav Petkov /* 4086d0e1a507SJiri Olsa * Disable the check for real HW, so we don't 4087d0e1a507SJiri Olsa * mess with potentionaly enabled registers: 4088d0e1a507SJiri Olsa */ 40895ea3f6fbSZhenzhong Duan if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4090d0e1a507SJiri Olsa return true; 4091d0e1a507SJiri Olsa 4092d0e1a507SJiri Olsa /* 4093e1069839SBorislav Petkov * Read the current value, change it and read it back to see if it 4094e1069839SBorislav Petkov * matches, this is needed to detect certain hardware emulators 4095e1069839SBorislav Petkov * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4096e1069839SBorislav Petkov */ 4097e1069839SBorislav Petkov if (rdmsrl_safe(msr, &val_old)) 4098e1069839SBorislav Petkov return false; 4099e1069839SBorislav Petkov 4100e1069839SBorislav Petkov /* 4101e1069839SBorislav Petkov * Only change the bits which can be updated by wrmsrl. 4102e1069839SBorislav Petkov */ 4103e1069839SBorislav Petkov val_tmp = val_old ^ mask; 410419fc9dddSDavid Carrillo-Cisneros 410519fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 410619fc9dddSDavid Carrillo-Cisneros val_tmp = lbr_from_signext_quirk_wr(val_tmp); 410719fc9dddSDavid Carrillo-Cisneros 4108e1069839SBorislav Petkov if (wrmsrl_safe(msr, val_tmp) || 4109e1069839SBorislav Petkov rdmsrl_safe(msr, &val_new)) 4110e1069839SBorislav Petkov return false; 4111e1069839SBorislav Petkov 411219fc9dddSDavid Carrillo-Cisneros /* 411319fc9dddSDavid Carrillo-Cisneros * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 411419fc9dddSDavid Carrillo-Cisneros * should equal rdmsrl()'s even with the quirk. 411519fc9dddSDavid Carrillo-Cisneros */ 4116e1069839SBorislav Petkov if (val_new != val_tmp) 4117e1069839SBorislav Petkov return false; 4118e1069839SBorislav Petkov 411919fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 412019fc9dddSDavid Carrillo-Cisneros val_old = lbr_from_signext_quirk_wr(val_old); 412119fc9dddSDavid Carrillo-Cisneros 4122e1069839SBorislav Petkov /* Here it's sure that the MSR can be safely accessed. 4123e1069839SBorislav Petkov * Restore the old value and return. 4124e1069839SBorislav Petkov */ 4125e1069839SBorislav Petkov wrmsrl(msr, val_old); 4126e1069839SBorislav Petkov 4127e1069839SBorislav Petkov return true; 4128e1069839SBorislav Petkov } 4129e1069839SBorislav Petkov 4130e1069839SBorislav Petkov static __init void intel_sandybridge_quirk(void) 4131e1069839SBorislav Petkov { 4132e1069839SBorislav Petkov x86_pmu.check_microcode = intel_snb_check_microcode; 41331ba143a5SSebastian Andrzej Siewior cpus_read_lock(); 4134e1069839SBorislav Petkov intel_snb_check_microcode(); 41351ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 4136e1069839SBorislav Petkov } 4137e1069839SBorislav Petkov 4138e1069839SBorislav Petkov static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4139e1069839SBorislav Petkov { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4140e1069839SBorislav Petkov { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4141e1069839SBorislav Petkov { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4142e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4143e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4144e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4145e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4146e1069839SBorislav Petkov }; 4147e1069839SBorislav Petkov 4148e1069839SBorislav Petkov static __init void intel_arch_events_quirk(void) 4149e1069839SBorislav Petkov { 4150e1069839SBorislav Petkov int bit; 4151e1069839SBorislav Petkov 4152e1069839SBorislav Petkov /* disable event that reported as not presend by cpuid */ 4153e1069839SBorislav Petkov for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4154e1069839SBorislav Petkov intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4155e1069839SBorislav Petkov pr_warn("CPUID marked event: \'%s\' unavailable\n", 4156e1069839SBorislav Petkov intel_arch_events_map[bit].name); 4157e1069839SBorislav Petkov } 4158e1069839SBorislav Petkov } 4159e1069839SBorislav Petkov 4160e1069839SBorislav Petkov static __init void intel_nehalem_quirk(void) 4161e1069839SBorislav Petkov { 4162e1069839SBorislav Petkov union cpuid10_ebx ebx; 4163e1069839SBorislav Petkov 4164e1069839SBorislav Petkov ebx.full = x86_pmu.events_maskl; 4165e1069839SBorislav Petkov if (ebx.split.no_branch_misses_retired) { 4166e1069839SBorislav Petkov /* 4167e1069839SBorislav Petkov * Erratum AAJ80 detected, we work it around by using 4168e1069839SBorislav Petkov * the BR_MISP_EXEC.ANY event. This will over-count 4169e1069839SBorislav Petkov * branch-misses, but it's still much better than the 4170e1069839SBorislav Petkov * architectural event which is often completely bogus: 4171e1069839SBorislav Petkov */ 4172e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4173e1069839SBorislav Petkov ebx.split.no_branch_misses_retired = 0; 4174e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4175e1069839SBorislav Petkov pr_info("CPU erratum AAJ80 worked around\n"); 4176e1069839SBorislav Petkov } 4177e1069839SBorislav Petkov } 4178e1069839SBorislav Petkov 4179bef9f271SKan Liang static const struct x86_cpu_desc counter_freezing_ucodes[] = { 4180af63147cSKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e), 4181af63147cSKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e), 4182af63147cSKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008), 41835ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028), 4184bef9f271SKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028), 4185bef9f271SKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006), 4186bef9f271SKan Liang {} 4187bef9f271SKan Liang }; 4188bef9f271SKan Liang 4189bef9f271SKan Liang static bool intel_counter_freezing_broken(void) 41907c5314b8SKan Liang { 4191bef9f271SKan Liang return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes); 41927c5314b8SKan Liang } 41937c5314b8SKan Liang 4194bef9f271SKan Liang static __init void intel_counter_freezing_quirk(void) 41957c5314b8SKan Liang { 41967c5314b8SKan Liang /* Check if it's already disabled */ 41977c5314b8SKan Liang if (disable_counter_freezing) 41987c5314b8SKan Liang return; 41997c5314b8SKan Liang 42007c5314b8SKan Liang /* 42017c5314b8SKan Liang * If the system starts with the wrong ucode, leave the 42027c5314b8SKan Liang * counter-freezing feature permanently disabled. 42037c5314b8SKan Liang */ 4204bef9f271SKan Liang if (intel_counter_freezing_broken()) { 42057c5314b8SKan Liang pr_info("PMU counter freezing disabled due to CPU errata," 42067c5314b8SKan Liang "please upgrade microcode\n"); 42077c5314b8SKan Liang x86_pmu.counter_freezing = false; 42087c5314b8SKan Liang x86_pmu.handle_irq = intel_pmu_handle_irq; 42097c5314b8SKan Liang } 42107c5314b8SKan Liang } 42117c5314b8SKan Liang 4212e1069839SBorislav Petkov /* 4213e1069839SBorislav Petkov * enable software workaround for errata: 4214e1069839SBorislav Petkov * SNB: BJ122 4215e1069839SBorislav Petkov * IVB: BV98 4216e1069839SBorislav Petkov * HSW: HSD29 4217e1069839SBorislav Petkov * 4218e1069839SBorislav Petkov * Only needed when HT is enabled. However detecting 4219e1069839SBorislav Petkov * if HT is enabled is difficult (model specific). So instead, 4220e1069839SBorislav Petkov * we enable the workaround in the early boot, and verify if 4221e1069839SBorislav Petkov * it is needed in a later initcall phase once we have valid 4222e1069839SBorislav Petkov * topology information to check if HT is actually enabled 4223e1069839SBorislav Petkov */ 4224e1069839SBorislav Petkov static __init void intel_ht_bug(void) 4225e1069839SBorislav Petkov { 4226e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4227e1069839SBorislav Petkov 4228e1069839SBorislav Petkov x86_pmu.start_scheduling = intel_start_scheduling; 4229e1069839SBorislav Petkov x86_pmu.commit_scheduling = intel_commit_scheduling; 4230e1069839SBorislav Petkov x86_pmu.stop_scheduling = intel_stop_scheduling; 4231e1069839SBorislav Petkov } 4232e1069839SBorislav Petkov 4233e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4234e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4235e1069839SBorislav Petkov 4236e1069839SBorislav Petkov /* Haswell special events */ 4237e1069839SBorislav Petkov EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4238e1069839SBorislav Petkov EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4239e1069839SBorislav Petkov EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4240e1069839SBorislav Petkov EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4241e1069839SBorislav Petkov EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4242e1069839SBorislav Petkov EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4243e1069839SBorislav Petkov EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4244e1069839SBorislav Petkov EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4245e1069839SBorislav Petkov EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4246e1069839SBorislav Petkov EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4247e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4248e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4249e1069839SBorislav Petkov 4250e1069839SBorislav Petkov static struct attribute *hsw_events_attrs[] = { 425158ba4d5aSAndi Kleen EVENT_PTR(td_slots_issued), 425258ba4d5aSAndi Kleen EVENT_PTR(td_slots_retired), 425358ba4d5aSAndi Kleen EVENT_PTR(td_fetch_bubbles), 425458ba4d5aSAndi Kleen EVENT_PTR(td_total_slots), 425558ba4d5aSAndi Kleen EVENT_PTR(td_total_slots_scale), 425658ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles), 425758ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 425858ba4d5aSAndi Kleen NULL 425958ba4d5aSAndi Kleen }; 426058ba4d5aSAndi Kleen 4261d4ae5529SJiri Olsa static struct attribute *hsw_mem_events_attrs[] = { 4262d4ae5529SJiri Olsa EVENT_PTR(mem_ld_hsw), 4263d4ae5529SJiri Olsa EVENT_PTR(mem_st_hsw), 4264d4ae5529SJiri Olsa NULL, 4265d4ae5529SJiri Olsa }; 4266d4ae5529SJiri Olsa 426758ba4d5aSAndi Kleen static struct attribute *hsw_tsx_events_attrs[] = { 4268e1069839SBorislav Petkov EVENT_PTR(tx_start), 4269e1069839SBorislav Petkov EVENT_PTR(tx_commit), 4270e1069839SBorislav Petkov EVENT_PTR(tx_abort), 4271e1069839SBorislav Petkov EVENT_PTR(tx_capacity), 4272e1069839SBorislav Petkov EVENT_PTR(tx_conflict), 4273e1069839SBorislav Petkov EVENT_PTR(el_start), 4274e1069839SBorislav Petkov EVENT_PTR(el_commit), 4275e1069839SBorislav Petkov EVENT_PTR(el_abort), 4276e1069839SBorislav Petkov EVENT_PTR(el_capacity), 4277e1069839SBorislav Petkov EVENT_PTR(el_conflict), 4278e1069839SBorislav Petkov EVENT_PTR(cycles_t), 4279e1069839SBorislav Petkov EVENT_PTR(cycles_ct), 4280e1069839SBorislav Petkov NULL 4281e1069839SBorislav Petkov }; 4282e1069839SBorislav Petkov 428360176089SKan Liang EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 428460176089SKan Liang EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 428560176089SKan Liang EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 428660176089SKan Liang EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 428760176089SKan Liang 428860176089SKan Liang static struct attribute *icl_events_attrs[] = { 428960176089SKan Liang EVENT_PTR(mem_ld_hsw), 429060176089SKan Liang EVENT_PTR(mem_st_hsw), 429160176089SKan Liang NULL, 429260176089SKan Liang }; 429360176089SKan Liang 429460176089SKan Liang static struct attribute *icl_tsx_events_attrs[] = { 429560176089SKan Liang EVENT_PTR(tx_start), 429660176089SKan Liang EVENT_PTR(tx_abort), 429760176089SKan Liang EVENT_PTR(tx_commit), 429860176089SKan Liang EVENT_PTR(tx_capacity_read), 429960176089SKan Liang EVENT_PTR(tx_capacity_write), 430060176089SKan Liang EVENT_PTR(tx_conflict), 430160176089SKan Liang EVENT_PTR(el_start), 430260176089SKan Liang EVENT_PTR(el_abort), 430360176089SKan Liang EVENT_PTR(el_commit), 430460176089SKan Liang EVENT_PTR(el_capacity_read), 430560176089SKan Liang EVENT_PTR(el_capacity_write), 430660176089SKan Liang EVENT_PTR(el_conflict), 430760176089SKan Liang EVENT_PTR(cycles_t), 430860176089SKan Liang EVENT_PTR(cycles_ct), 430960176089SKan Liang NULL, 431060176089SKan Liang }; 431160176089SKan Liang 43126089327fSKan Liang static ssize_t freeze_on_smi_show(struct device *cdev, 43136089327fSKan Liang struct device_attribute *attr, 43146089327fSKan Liang char *buf) 43156089327fSKan Liang { 43166089327fSKan Liang return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 43176089327fSKan Liang } 43186089327fSKan Liang 43196089327fSKan Liang static DEFINE_MUTEX(freeze_on_smi_mutex); 43206089327fSKan Liang 43216089327fSKan Liang static ssize_t freeze_on_smi_store(struct device *cdev, 43226089327fSKan Liang struct device_attribute *attr, 43236089327fSKan Liang const char *buf, size_t count) 43246089327fSKan Liang { 43256089327fSKan Liang unsigned long val; 43266089327fSKan Liang ssize_t ret; 43276089327fSKan Liang 43286089327fSKan Liang ret = kstrtoul(buf, 0, &val); 43296089327fSKan Liang if (ret) 43306089327fSKan Liang return ret; 43316089327fSKan Liang 43326089327fSKan Liang if (val > 1) 43336089327fSKan Liang return -EINVAL; 43346089327fSKan Liang 43356089327fSKan Liang mutex_lock(&freeze_on_smi_mutex); 43366089327fSKan Liang 43376089327fSKan Liang if (x86_pmu.attr_freeze_on_smi == val) 43386089327fSKan Liang goto done; 43396089327fSKan Liang 43406089327fSKan Liang x86_pmu.attr_freeze_on_smi = val; 43416089327fSKan Liang 43426089327fSKan Liang get_online_cpus(); 43436089327fSKan Liang on_each_cpu(flip_smm_bit, &val, 1); 43446089327fSKan Liang put_online_cpus(); 43456089327fSKan Liang done: 43466089327fSKan Liang mutex_unlock(&freeze_on_smi_mutex); 43476089327fSKan Liang 43486089327fSKan Liang return count; 43496089327fSKan Liang } 43506089327fSKan Liang 4351f447e4ebSStephane Eranian static void update_tfa_sched(void *ignored) 4352f447e4ebSStephane Eranian { 4353f447e4ebSStephane Eranian struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4354f447e4ebSStephane Eranian 4355f447e4ebSStephane Eranian /* 4356f447e4ebSStephane Eranian * check if PMC3 is used 4357f447e4ebSStephane Eranian * and if so force schedule out for all event types all contexts 4358f447e4ebSStephane Eranian */ 4359f447e4ebSStephane Eranian if (test_bit(3, cpuc->active_mask)) 4360f447e4ebSStephane Eranian perf_pmu_resched(x86_get_pmu()); 4361f447e4ebSStephane Eranian } 4362f447e4ebSStephane Eranian 4363f447e4ebSStephane Eranian static ssize_t show_sysctl_tfa(struct device *cdev, 4364f447e4ebSStephane Eranian struct device_attribute *attr, 4365f447e4ebSStephane Eranian char *buf) 4366f447e4ebSStephane Eranian { 4367f447e4ebSStephane Eranian return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 4368f447e4ebSStephane Eranian } 4369f447e4ebSStephane Eranian 4370f447e4ebSStephane Eranian static ssize_t set_sysctl_tfa(struct device *cdev, 4371f447e4ebSStephane Eranian struct device_attribute *attr, 4372f447e4ebSStephane Eranian const char *buf, size_t count) 4373f447e4ebSStephane Eranian { 4374f447e4ebSStephane Eranian bool val; 4375f447e4ebSStephane Eranian ssize_t ret; 4376f447e4ebSStephane Eranian 4377f447e4ebSStephane Eranian ret = kstrtobool(buf, &val); 4378f447e4ebSStephane Eranian if (ret) 4379f447e4ebSStephane Eranian return ret; 4380f447e4ebSStephane Eranian 4381f447e4ebSStephane Eranian /* no change */ 4382f447e4ebSStephane Eranian if (val == allow_tsx_force_abort) 4383f447e4ebSStephane Eranian return count; 4384f447e4ebSStephane Eranian 4385f447e4ebSStephane Eranian allow_tsx_force_abort = val; 4386f447e4ebSStephane Eranian 4387f447e4ebSStephane Eranian get_online_cpus(); 4388f447e4ebSStephane Eranian on_each_cpu(update_tfa_sched, NULL, 1); 4389f447e4ebSStephane Eranian put_online_cpus(); 4390f447e4ebSStephane Eranian 4391f447e4ebSStephane Eranian return count; 4392f447e4ebSStephane Eranian } 4393f447e4ebSStephane Eranian 4394f447e4ebSStephane Eranian 43956089327fSKan Liang static DEVICE_ATTR_RW(freeze_on_smi); 43966089327fSKan Liang 4397b00233b5SAndi Kleen static ssize_t branches_show(struct device *cdev, 4398b00233b5SAndi Kleen struct device_attribute *attr, 4399b00233b5SAndi Kleen char *buf) 4400b00233b5SAndi Kleen { 4401b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4402b00233b5SAndi Kleen } 4403b00233b5SAndi Kleen 4404b00233b5SAndi Kleen static DEVICE_ATTR_RO(branches); 4405b00233b5SAndi Kleen 4406b00233b5SAndi Kleen static struct attribute *lbr_attrs[] = { 4407b00233b5SAndi Kleen &dev_attr_branches.attr, 4408b00233b5SAndi Kleen NULL 4409b00233b5SAndi Kleen }; 4410b00233b5SAndi Kleen 4411b00233b5SAndi Kleen static char pmu_name_str[30]; 4412b00233b5SAndi Kleen 4413b00233b5SAndi Kleen static ssize_t pmu_name_show(struct device *cdev, 4414b00233b5SAndi Kleen struct device_attribute *attr, 4415b00233b5SAndi Kleen char *buf) 4416b00233b5SAndi Kleen { 4417b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4418b00233b5SAndi Kleen } 4419b00233b5SAndi Kleen 4420b00233b5SAndi Kleen static DEVICE_ATTR_RO(pmu_name); 4421b00233b5SAndi Kleen 4422b00233b5SAndi Kleen static struct attribute *intel_pmu_caps_attrs[] = { 4423b00233b5SAndi Kleen &dev_attr_pmu_name.attr, 4424b00233b5SAndi Kleen NULL 4425b00233b5SAndi Kleen }; 4426b00233b5SAndi Kleen 4427f447e4ebSStephane Eranian static DEVICE_ATTR(allow_tsx_force_abort, 0644, 4428f447e4ebSStephane Eranian show_sysctl_tfa, 4429f447e4ebSStephane Eranian set_sysctl_tfa); 4430400816f6SPeter Zijlstra (Intel) 44316089327fSKan Liang static struct attribute *intel_pmu_attrs[] = { 44326089327fSKan Liang &dev_attr_freeze_on_smi.attr, 4433b7c9b392SJiri Olsa &dev_attr_allow_tsx_force_abort.attr, 44346089327fSKan Liang NULL, 44356089327fSKan Liang }; 44366089327fSKan Liang 4437baa0c833SJiri Olsa static umode_t 4438baa0c833SJiri Olsa tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4439d4ae5529SJiri Olsa { 4440baa0c833SJiri Olsa return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 4441d4ae5529SJiri Olsa } 4442d4ae5529SJiri Olsa 4443baa0c833SJiri Olsa static umode_t 4444baa0c833SJiri Olsa pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4445baa0c833SJiri Olsa { 4446baa0c833SJiri Olsa return x86_pmu.pebs ? attr->mode : 0; 4447d4ae5529SJiri Olsa } 4448d4ae5529SJiri Olsa 44491f157286SJiri Olsa static umode_t 44501f157286SJiri Olsa lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 44511f157286SJiri Olsa { 44521f157286SJiri Olsa return x86_pmu.lbr_nr ? attr->mode : 0; 44531f157286SJiri Olsa } 44541f157286SJiri Olsa 44553ea40ac7SJiri Olsa static umode_t 44563ea40ac7SJiri Olsa exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 44573ea40ac7SJiri Olsa { 44583ea40ac7SJiri Olsa return x86_pmu.version >= 2 ? attr->mode : 0; 44593ea40ac7SJiri Olsa } 44603ea40ac7SJiri Olsa 4461b7c9b392SJiri Olsa static umode_t 4462b7c9b392SJiri Olsa default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4463b7c9b392SJiri Olsa { 4464b7c9b392SJiri Olsa if (attr == &dev_attr_allow_tsx_force_abort.attr) 4465b7c9b392SJiri Olsa return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 4466b7c9b392SJiri Olsa 4467b7c9b392SJiri Olsa return attr->mode; 4468b7c9b392SJiri Olsa } 4469b7c9b392SJiri Olsa 4470baa0c833SJiri Olsa static struct attribute_group group_events_td = { 4471baa0c833SJiri Olsa .name = "events", 4472baa0c833SJiri Olsa }; 4473baa0c833SJiri Olsa 4474baa0c833SJiri Olsa static struct attribute_group group_events_mem = { 4475baa0c833SJiri Olsa .name = "events", 4476baa0c833SJiri Olsa .is_visible = pebs_is_visible, 4477baa0c833SJiri Olsa }; 4478baa0c833SJiri Olsa 4479baa0c833SJiri Olsa static struct attribute_group group_events_tsx = { 4480baa0c833SJiri Olsa .name = "events", 4481baa0c833SJiri Olsa .is_visible = tsx_is_visible, 4482baa0c833SJiri Olsa }; 4483baa0c833SJiri Olsa 44841f157286SJiri Olsa static struct attribute_group group_caps_gen = { 44851f157286SJiri Olsa .name = "caps", 44861f157286SJiri Olsa .attrs = intel_pmu_caps_attrs, 44871f157286SJiri Olsa }; 44881f157286SJiri Olsa 44891f157286SJiri Olsa static struct attribute_group group_caps_lbr = { 44901f157286SJiri Olsa .name = "caps", 44911f157286SJiri Olsa .attrs = lbr_attrs, 44921f157286SJiri Olsa .is_visible = lbr_is_visible, 44931f157286SJiri Olsa }; 44941f157286SJiri Olsa 44953ea40ac7SJiri Olsa static struct attribute_group group_format_extra = { 44963ea40ac7SJiri Olsa .name = "format", 44973ea40ac7SJiri Olsa .is_visible = exra_is_visible, 44983ea40ac7SJiri Olsa }; 44993ea40ac7SJiri Olsa 4500b6576880SJiri Olsa static struct attribute_group group_format_extra_skl = { 4501b6576880SJiri Olsa .name = "format", 4502b6576880SJiri Olsa .is_visible = exra_is_visible, 4503b6576880SJiri Olsa }; 4504b6576880SJiri Olsa 45056a9f4efeSJiri Olsa static struct attribute_group group_default = { 45066a9f4efeSJiri Olsa .attrs = intel_pmu_attrs, 4507b7c9b392SJiri Olsa .is_visible = default_is_visible, 45086a9f4efeSJiri Olsa }; 45096a9f4efeSJiri Olsa 4510baa0c833SJiri Olsa static const struct attribute_group *attr_update[] = { 4511baa0c833SJiri Olsa &group_events_td, 4512baa0c833SJiri Olsa &group_events_mem, 4513baa0c833SJiri Olsa &group_events_tsx, 45141f157286SJiri Olsa &group_caps_gen, 45151f157286SJiri Olsa &group_caps_lbr, 45163ea40ac7SJiri Olsa &group_format_extra, 4517b6576880SJiri Olsa &group_format_extra_skl, 45186a9f4efeSJiri Olsa &group_default, 4519baa0c833SJiri Olsa NULL, 4520baa0c833SJiri Olsa }; 4521baa0c833SJiri Olsa 4522baa0c833SJiri Olsa static struct attribute *empty_attrs; 4523baa0c833SJiri Olsa 4524e1069839SBorislav Petkov __init int intel_pmu_init(void) 4525e1069839SBorislav Petkov { 4526b6576880SJiri Olsa struct attribute **extra_skl_attr = &empty_attrs; 4527baa0c833SJiri Olsa struct attribute **extra_attr = &empty_attrs; 4528baa0c833SJiri Olsa struct attribute **td_attr = &empty_attrs; 4529baa0c833SJiri Olsa struct attribute **mem_attr = &empty_attrs; 4530baa0c833SJiri Olsa struct attribute **tsx_attr = &empty_attrs; 4531e1069839SBorislav Petkov union cpuid10_edx edx; 4532e1069839SBorislav Petkov union cpuid10_eax eax; 4533e1069839SBorislav Petkov union cpuid10_ebx ebx; 4534e1069839SBorislav Petkov struct event_constraint *c; 4535e1069839SBorislav Petkov unsigned int unused; 4536e1069839SBorislav Petkov struct extra_reg *er; 4537faaeff98SKan Liang bool pmem = false; 4538e1069839SBorislav Petkov int version, i; 4539b00233b5SAndi Kleen char *name; 4540e1069839SBorislav Petkov 4541e1069839SBorislav Petkov if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4542e1069839SBorislav Petkov switch (boot_cpu_data.x86) { 4543e1069839SBorislav Petkov case 0x6: 4544e1069839SBorislav Petkov return p6_pmu_init(); 4545e1069839SBorislav Petkov case 0xb: 4546e1069839SBorislav Petkov return knc_pmu_init(); 4547e1069839SBorislav Petkov case 0xf: 4548e1069839SBorislav Petkov return p4_pmu_init(); 4549e1069839SBorislav Petkov } 4550e1069839SBorislav Petkov return -ENODEV; 4551e1069839SBorislav Petkov } 4552e1069839SBorislav Petkov 4553e1069839SBorislav Petkov /* 4554e1069839SBorislav Petkov * Check whether the Architectural PerfMon supports 4555e1069839SBorislav Petkov * Branch Misses Retired hw_event or not. 4556e1069839SBorislav Petkov */ 4557e1069839SBorislav Petkov cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4558e1069839SBorislav Petkov if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4559e1069839SBorislav Petkov return -ENODEV; 4560e1069839SBorislav Petkov 4561e1069839SBorislav Petkov version = eax.split.version_id; 4562e1069839SBorislav Petkov if (version < 2) 4563e1069839SBorislav Petkov x86_pmu = core_pmu; 4564e1069839SBorislav Petkov else 4565e1069839SBorislav Petkov x86_pmu = intel_pmu; 4566e1069839SBorislav Petkov 4567e1069839SBorislav Petkov x86_pmu.version = version; 4568e1069839SBorislav Petkov x86_pmu.num_counters = eax.split.num_counters; 4569e1069839SBorislav Petkov x86_pmu.cntval_bits = eax.split.bit_width; 4570e1069839SBorislav Petkov x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4571e1069839SBorislav Petkov 4572e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4573e1069839SBorislav Petkov x86_pmu.events_mask_len = eax.split.mask_length; 4574e1069839SBorislav Petkov 4575e1069839SBorislav Petkov x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4576e1069839SBorislav Petkov 4577e1069839SBorislav Petkov /* 4578e1069839SBorislav Petkov * Quirk: v2 perfmon does not report fixed-purpose events, so 4579f92b7604SImre Palik * assume at least 3 events, when not running in a hypervisor: 4580e1069839SBorislav Petkov */ 4581f92b7604SImre Palik if (version > 1) { 4582f92b7604SImre Palik int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4583f92b7604SImre Palik 4584f92b7604SImre Palik x86_pmu.num_counters_fixed = 4585f92b7604SImre Palik max((int)edx.split.num_counters_fixed, assume); 4586f92b7604SImre Palik } 4587e1069839SBorislav Petkov 4588af3bdb99SAndi Kleen if (version >= 4) 4589af3bdb99SAndi Kleen x86_pmu.counter_freezing = !disable_counter_freezing; 4590af3bdb99SAndi Kleen 4591e1069839SBorislav Petkov if (boot_cpu_has(X86_FEATURE_PDCM)) { 4592e1069839SBorislav Petkov u64 capabilities; 4593e1069839SBorislav Petkov 4594e1069839SBorislav Petkov rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4595e1069839SBorislav Petkov x86_pmu.intel_cap.capabilities = capabilities; 4596e1069839SBorislav Petkov } 4597e1069839SBorislav Petkov 4598e1069839SBorislav Petkov intel_ds_init(); 4599e1069839SBorislav Petkov 4600e1069839SBorislav Petkov x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 4601e1069839SBorislav Petkov 4602e1069839SBorislav Petkov /* 4603e1069839SBorislav Petkov * Install the hw-cache-events table: 4604e1069839SBorislav Petkov */ 4605e1069839SBorislav Petkov switch (boot_cpu_data.x86_model) { 4606ef5f9f47SDave Hansen case INTEL_FAM6_CORE_YONAH: 4607e1069839SBorislav Petkov pr_cont("Core events, "); 4608b00233b5SAndi Kleen name = "core"; 4609e1069839SBorislav Petkov break; 4610e1069839SBorislav Petkov 4611ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM: 4612e1069839SBorislav Petkov x86_add_quirk(intel_clovertown_quirk); 46132b0fc374SGustavo A. R. Silva /* fall through */ 46142b0fc374SGustavo A. R. Silva 4615ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM_L: 4616ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_PENRYN: 4617ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_DUNNINGTON: 4618e1069839SBorislav Petkov memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 4619e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4620e1069839SBorislav Petkov 4621e1069839SBorislav Petkov intel_pmu_lbr_init_core(); 4622e1069839SBorislav Petkov 4623e1069839SBorislav Petkov x86_pmu.event_constraints = intel_core2_event_constraints; 4624e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 4625e1069839SBorislav Petkov pr_cont("Core2 events, "); 4626b00233b5SAndi Kleen name = "core2"; 4627e1069839SBorislav Petkov break; 4628e1069839SBorislav Petkov 4629ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM: 4630ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EP: 4631ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EX: 4632e1069839SBorislav Petkov memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 4633e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4634e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4635e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4636e1069839SBorislav Petkov 4637e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 4638e1069839SBorislav Petkov 4639e1069839SBorislav Petkov x86_pmu.event_constraints = intel_nehalem_event_constraints; 4640e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 4641e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4642e1069839SBorislav Petkov x86_pmu.extra_regs = intel_nehalem_extra_regs; 464344d3bbb6SJosh Hunt x86_pmu.limit_period = nhm_limit_period; 4644e1069839SBorislav Petkov 4645d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 4646e1069839SBorislav Petkov 4647e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 4648e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4649e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4650e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4651e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4652e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4653e1069839SBorislav Petkov 4654e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 4655e1069839SBorislav Petkov x86_add_quirk(intel_nehalem_quirk); 465695298355SAndi Kleen x86_pmu.pebs_no_tlb = 1; 4657a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4658e1069839SBorislav Petkov 4659e1069839SBorislav Petkov pr_cont("Nehalem events, "); 4660b00233b5SAndi Kleen name = "nehalem"; 4661e1069839SBorislav Petkov break; 4662e1069839SBorislav Petkov 4663f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL: 4664f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL_MID: 4665f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL: 4666f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_MID: 4667f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_TABLET: 4668e1069839SBorislav Petkov memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 4669e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4670e1069839SBorislav Petkov 4671e1069839SBorislav Petkov intel_pmu_lbr_init_atom(); 4672e1069839SBorislav Petkov 4673e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 4674e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 4675e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 4676e1069839SBorislav Petkov pr_cont("Atom events, "); 4677b00233b5SAndi Kleen name = "bonnell"; 4678e1069839SBorislav Petkov break; 4679e1069839SBorislav Petkov 4680f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT: 46815ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_D: 4682f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_MID: 4683ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_AIRMONT: 4684f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_AIRMONT_MID: 4685e1069839SBorislav Petkov memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 4686e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4687e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 4688e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4689e1069839SBorislav Petkov 4690f21d5adcSKan Liang intel_pmu_lbr_init_slm(); 4691e1069839SBorislav Petkov 4692e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 4693e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4694e1069839SBorislav Petkov x86_pmu.extra_regs = intel_slm_extra_regs; 4695e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4696baa0c833SJiri Olsa td_attr = slm_events_attrs; 4697a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4698e1069839SBorislav Petkov pr_cont("Silvermont events, "); 4699b00233b5SAndi Kleen name = "silvermont"; 4700e1069839SBorislav Petkov break; 4701e1069839SBorislav Petkov 4702ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_GOLDMONT: 47035ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_D: 4704af63147cSKan Liang x86_add_quirk(intel_counter_freezing_quirk); 47058b92c3a7SKan Liang memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 47068b92c3a7SKan Liang sizeof(hw_cache_event_ids)); 47078b92c3a7SKan Liang memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 47088b92c3a7SKan Liang sizeof(hw_cache_extra_regs)); 47098b92c3a7SKan Liang 47108b92c3a7SKan Liang intel_pmu_lbr_init_skl(); 47118b92c3a7SKan Liang 47128b92c3a7SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 47138b92c3a7SKan Liang x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 47148b92c3a7SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 47158b92c3a7SKan Liang /* 47168b92c3a7SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 47178b92c3a7SKan Liang * for precise cycles. 47188b92c3a7SKan Liang * :pp is identical to :ppp 47198b92c3a7SKan Liang */ 47208b92c3a7SKan Liang x86_pmu.pebs_aliases = NULL; 47218b92c3a7SKan Liang x86_pmu.pebs_prec_dist = true; 4722ccbebba4SAlexander Shishkin x86_pmu.lbr_pt_coexist = true; 47238b92c3a7SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4724baa0c833SJiri Olsa td_attr = glm_events_attrs; 4725a5df70c3SAndi Kleen extra_attr = slm_format_attr; 47268b92c3a7SKan Liang pr_cont("Goldmont events, "); 4727b00233b5SAndi Kleen name = "goldmont"; 47288b92c3a7SKan Liang break; 47298b92c3a7SKan Liang 4730f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4731bef9f271SKan Liang x86_add_quirk(intel_counter_freezing_quirk); 4732dd0b06b5SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 4733dd0b06b5SKan Liang sizeof(hw_cache_event_ids)); 4734dd0b06b5SKan Liang memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 4735dd0b06b5SKan Liang sizeof(hw_cache_extra_regs)); 4736dd0b06b5SKan Liang 4737dd0b06b5SKan Liang intel_pmu_lbr_init_skl(); 4738dd0b06b5SKan Liang 4739dd0b06b5SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 4740dd0b06b5SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 4741dd0b06b5SKan Liang /* 4742dd0b06b5SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 4743dd0b06b5SKan Liang * for precise cycles. 4744dd0b06b5SKan Liang */ 4745dd0b06b5SKan Liang x86_pmu.pebs_aliases = NULL; 4746dd0b06b5SKan Liang x86_pmu.pebs_prec_dist = true; 4747dd0b06b5SKan Liang x86_pmu.lbr_pt_coexist = true; 4748dd0b06b5SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4749a38b0ba1SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 4750dd0b06b5SKan Liang x86_pmu.get_event_constraints = glp_get_event_constraints; 4751baa0c833SJiri Olsa td_attr = glm_events_attrs; 4752dd0b06b5SKan Liang /* Goldmont Plus has 4-wide pipeline */ 4753dd0b06b5SKan Liang event_attr_td_total_slots_scale_glm.event_str = "4"; 4754a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4755dd0b06b5SKan Liang pr_cont("Goldmont plus events, "); 4756b00233b5SAndi Kleen name = "goldmont_plus"; 4757dd0b06b5SKan Liang break; 4758dd0b06b5SKan Liang 47595ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_TREMONT_D: 47606daeb873SKan Liang x86_pmu.late_ack = true; 47616daeb873SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 47626daeb873SKan Liang sizeof(hw_cache_event_ids)); 47636daeb873SKan Liang memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 47646daeb873SKan Liang sizeof(hw_cache_extra_regs)); 47656daeb873SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 47666daeb873SKan Liang 47676daeb873SKan Liang intel_pmu_lbr_init_skl(); 47686daeb873SKan Liang 47696daeb873SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 47706daeb873SKan Liang x86_pmu.extra_regs = intel_tnt_extra_regs; 47716daeb873SKan Liang /* 47726daeb873SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 47736daeb873SKan Liang * for precise cycles. 47746daeb873SKan Liang */ 47756daeb873SKan Liang x86_pmu.pebs_aliases = NULL; 47766daeb873SKan Liang x86_pmu.pebs_prec_dist = true; 47776daeb873SKan Liang x86_pmu.lbr_pt_coexist = true; 47786daeb873SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 47796daeb873SKan Liang x86_pmu.get_event_constraints = tnt_get_event_constraints; 47806daeb873SKan Liang extra_attr = slm_format_attr; 47816daeb873SKan Liang pr_cont("Tremont events, "); 47826daeb873SKan Liang name = "Tremont"; 47836daeb873SKan Liang break; 47846daeb873SKan Liang 4785ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE: 4786ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EP: 4787ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EX: 4788e1069839SBorislav Petkov memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 4789e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4790e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 4791e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4792e1069839SBorislav Petkov 4793e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 4794e1069839SBorislav Petkov 4795e1069839SBorislav Petkov x86_pmu.event_constraints = intel_westmere_event_constraints; 4796e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 4797e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 4798e1069839SBorislav Petkov x86_pmu.extra_regs = intel_westmere_extra_regs; 4799e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4800e1069839SBorislav Petkov 4801d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 4802e1069839SBorislav Petkov 4803e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 4804e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4805e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4806e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 4807e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4808e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 4809e1069839SBorislav Petkov 4810e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 4811a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4812e1069839SBorislav Petkov pr_cont("Westmere events, "); 4813b00233b5SAndi Kleen name = "westmere"; 4814e1069839SBorislav Petkov break; 4815e1069839SBorislav Petkov 4816ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 4817ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 4818e1069839SBorislav Petkov x86_add_quirk(intel_sandybridge_quirk); 4819e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4820e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4821e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4822e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4823e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4824e1069839SBorislav Petkov 4825e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 4826e1069839SBorislav Petkov 4827e1069839SBorislav Petkov x86_pmu.event_constraints = intel_snb_event_constraints; 4828e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 4829e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 4830ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 4831e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4832e1069839SBorislav Petkov else 4833e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 4834e1069839SBorislav Petkov 4835e1069839SBorislav Petkov 4836e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4837e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4838e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4839e1069839SBorislav Petkov 4840baa0c833SJiri Olsa td_attr = snb_events_attrs; 4841d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 4842e1069839SBorislav Petkov 4843e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4844e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4845e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4846e1069839SBorislav Petkov /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 4847e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 4848e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 4849e1069839SBorislav Petkov 4850a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4851a5df70c3SAndi Kleen 4852e1069839SBorislav Petkov pr_cont("SandyBridge events, "); 4853b00233b5SAndi Kleen name = "sandybridge"; 4854e1069839SBorislav Petkov break; 4855e1069839SBorislav Petkov 4856ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE: 4857ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE_X: 4858e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 4859e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 4860e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 4861e1069839SBorislav Petkov /* dTLB-load-misses on IVB is different than SNB */ 4862e1069839SBorislav Petkov hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 4863e1069839SBorislav Petkov 4864e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 4865e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 4866e1069839SBorislav Petkov 4867e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 4868e1069839SBorislav Petkov 4869e1069839SBorislav Petkov x86_pmu.event_constraints = intel_ivb_event_constraints; 4870e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 4871e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4872e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4873ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 4874e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4875e1069839SBorislav Petkov else 4876e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 4877e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4878e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4879e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4880e1069839SBorislav Petkov 4881baa0c833SJiri Olsa td_attr = snb_events_attrs; 4882d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 4883e1069839SBorislav Petkov 4884e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 4885e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 4886e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 4887e1069839SBorislav Petkov 4888a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 4889a5df70c3SAndi Kleen 4890e1069839SBorislav Petkov pr_cont("IvyBridge events, "); 4891b00233b5SAndi Kleen name = "ivybridge"; 4892e1069839SBorislav Petkov break; 4893e1069839SBorislav Petkov 4894e1069839SBorislav Petkov 4895c66f78a6SPeter Zijlstra case INTEL_FAM6_HASWELL: 4896ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_X: 4897af239c44SPeter Zijlstra case INTEL_FAM6_HASWELL_L: 48985e741407SPeter Zijlstra case INTEL_FAM6_HASWELL_G: 4899e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 49009b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 4901e1069839SBorislav Petkov x86_pmu.late_ack = true; 4902e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4903e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4904e1069839SBorislav Petkov 4905e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 4906e1069839SBorislav Petkov 4907e1069839SBorislav Petkov x86_pmu.event_constraints = intel_hsw_event_constraints; 4908e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 4909e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4910e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4911e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4912e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4913e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4914e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4915e1069839SBorislav Petkov 4916e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4917e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 4918e1069839SBorislav Petkov x86_pmu.lbr_double_abort = true; 4919a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4920a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4921baa0c833SJiri Olsa td_attr = hsw_events_attrs; 4922d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 4923d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 4924e1069839SBorislav Petkov pr_cont("Haswell events, "); 4925b00233b5SAndi Kleen name = "haswell"; 4926e1069839SBorislav Petkov break; 4927e1069839SBorislav Petkov 4928c66f78a6SPeter Zijlstra case INTEL_FAM6_BROADWELL: 49295ebb34edSPeter Zijlstra case INTEL_FAM6_BROADWELL_D: 49305e741407SPeter Zijlstra case INTEL_FAM6_BROADWELL_G: 4931ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_X: 49329b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 4933e1069839SBorislav Petkov x86_pmu.late_ack = true; 4934e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4935e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4936e1069839SBorislav Petkov 4937e1069839SBorislav Petkov /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 4938e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 4939e1069839SBorislav Petkov BDW_L3_MISS|HSW_SNOOP_DRAM; 4940e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 4941e1069839SBorislav Petkov HSW_SNOOP_DRAM; 4942e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 4943e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4944e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 4945e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 4946e1069839SBorislav Petkov 4947e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 4948e1069839SBorislav Petkov 4949e1069839SBorislav Petkov x86_pmu.event_constraints = intel_bdw_event_constraints; 4950b3e62463SStephane Eranian x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 4951e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 4952e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 4953e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 4954e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4955e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4956e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4957e1069839SBorislav Petkov 4958e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 4959e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 4960e1069839SBorislav Petkov x86_pmu.limit_period = bdw_limit_period; 4961a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 4962a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 4963baa0c833SJiri Olsa td_attr = hsw_events_attrs; 4964d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 4965d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 4966e1069839SBorislav Petkov pr_cont("Broadwell events, "); 4967b00233b5SAndi Kleen name = "broadwell"; 4968e1069839SBorislav Petkov break; 4969e1069839SBorislav Petkov 4970ef5f9f47SDave Hansen case INTEL_FAM6_XEON_PHI_KNL: 4971608284bfSPiotr Luc case INTEL_FAM6_XEON_PHI_KNM: 4972e1069839SBorislav Petkov memcpy(hw_cache_event_ids, 4973e1069839SBorislav Petkov slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 4974e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, 4975e1069839SBorislav Petkov knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 4976e1069839SBorislav Petkov intel_pmu_lbr_init_knl(); 4977e1069839SBorislav Petkov 4978e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 4979e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 4980e1069839SBorislav Petkov x86_pmu.extra_regs = intel_knl_extra_regs; 4981e1069839SBorislav Petkov 4982e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 4983e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 4984e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 4985a5df70c3SAndi Kleen extra_attr = slm_format_attr; 4986608284bfSPiotr Luc pr_cont("Knights Landing/Mill events, "); 4987b00233b5SAndi Kleen name = "knights-landing"; 4988e1069839SBorislav Petkov break; 4989e1069839SBorislav Petkov 4990faaeff98SKan Liang case INTEL_FAM6_SKYLAKE_X: 4991faaeff98SKan Liang pmem = true; 4992289a2d22SGustavo A. R. Silva /* fall through */ 4993af239c44SPeter Zijlstra case INTEL_FAM6_SKYLAKE_L: 4994c66f78a6SPeter Zijlstra case INTEL_FAM6_SKYLAKE: 4995af239c44SPeter Zijlstra case INTEL_FAM6_KABYLAKE_L: 4996c66f78a6SPeter Zijlstra case INTEL_FAM6_KABYLAKE: 49979066288bSKan Liang case INTEL_FAM6_COMETLAKE_L: 49989066288bSKan Liang case INTEL_FAM6_COMETLAKE: 49999b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5000e1069839SBorislav Petkov x86_pmu.late_ack = true; 5001e1069839SBorislav Petkov memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5002e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5003e1069839SBorislav Petkov intel_pmu_lbr_init_skl(); 5004e1069839SBorislav Petkov 5005a39fcae7SAndi Kleen /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 5006a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_noht = 5007a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1"; 5008a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_ht = 5009a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1,any=1"; 5010a39fcae7SAndi Kleen 5011e1069839SBorislav Petkov x86_pmu.event_constraints = intel_skl_event_constraints; 5012e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 5013e1069839SBorislav Petkov x86_pmu.extra_regs = intel_skl_extra_regs; 5014e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 5015e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5016e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5017e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5018e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5019e1069839SBorislav Petkov 5020e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5021e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5022a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5023a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5024b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 5025baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5026d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5027d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5028faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 5029400816f6SPeter Zijlstra (Intel) 5030400816f6SPeter Zijlstra (Intel) if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 5031400816f6SPeter Zijlstra (Intel) x86_pmu.flags |= PMU_FL_TFA; 5032400816f6SPeter Zijlstra (Intel) x86_pmu.get_event_constraints = tfa_get_event_constraints; 5033400816f6SPeter Zijlstra (Intel) x86_pmu.enable_all = intel_tfa_pmu_enable_all; 5034400816f6SPeter Zijlstra (Intel) x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 5035400816f6SPeter Zijlstra (Intel) } 5036400816f6SPeter Zijlstra (Intel) 5037e1069839SBorislav Petkov pr_cont("Skylake events, "); 5038b00233b5SAndi Kleen name = "skylake"; 5039e1069839SBorislav Petkov break; 5040e1069839SBorislav Petkov 5041faaeff98SKan Liang case INTEL_FAM6_ICELAKE_X: 50425ebb34edSPeter Zijlstra case INTEL_FAM6_ICELAKE_D: 5043faaeff98SKan Liang pmem = true; 5044289a2d22SGustavo A. R. Silva /* fall through */ 5045af239c44SPeter Zijlstra case INTEL_FAM6_ICELAKE_L: 5046c66f78a6SPeter Zijlstra case INTEL_FAM6_ICELAKE: 504723645a76SKan Liang case INTEL_FAM6_TIGERLAKE_L: 504823645a76SKan Liang case INTEL_FAM6_TIGERLAKE: 504960176089SKan Liang x86_pmu.late_ack = true; 505060176089SKan Liang memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 505160176089SKan Liang memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 505260176089SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 505360176089SKan Liang intel_pmu_lbr_init_skl(); 505460176089SKan Liang 505560176089SKan Liang x86_pmu.event_constraints = intel_icl_event_constraints; 505660176089SKan Liang x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 505760176089SKan Liang x86_pmu.extra_regs = intel_icl_extra_regs; 505860176089SKan Liang x86_pmu.pebs_aliases = NULL; 505960176089SKan Liang x86_pmu.pebs_prec_dist = true; 506060176089SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 506160176089SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 506260176089SKan Liang 506360176089SKan Liang x86_pmu.hw_config = hsw_hw_config; 506460176089SKan Liang x86_pmu.get_event_constraints = icl_get_event_constraints; 506560176089SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 506660176089SKan Liang hsw_format_attr : nhm_format_attr; 5067b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 5068baa0c833SJiri Olsa mem_attr = icl_events_attrs; 5069baa0c833SJiri Olsa tsx_attr = icl_tsx_events_attrs; 507060176089SKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02); 507160176089SKan Liang x86_pmu.lbr_pt_coexist = true; 5072faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 507360176089SKan Liang pr_cont("Icelake events, "); 507460176089SKan Liang name = "icelake"; 507560176089SKan Liang break; 507660176089SKan Liang 5077e1069839SBorislav Petkov default: 5078e1069839SBorislav Petkov switch (x86_pmu.version) { 5079e1069839SBorislav Petkov case 1: 5080e1069839SBorislav Petkov x86_pmu.event_constraints = intel_v1_event_constraints; 5081e1069839SBorislav Petkov pr_cont("generic architected perfmon v1, "); 5082b00233b5SAndi Kleen name = "generic_arch_v1"; 5083e1069839SBorislav Petkov break; 5084e1069839SBorislav Petkov default: 5085e1069839SBorislav Petkov /* 5086e1069839SBorislav Petkov * default constraints for v2 and up 5087e1069839SBorislav Petkov */ 5088e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 5089e1069839SBorislav Petkov pr_cont("generic architected perfmon, "); 5090b00233b5SAndi Kleen name = "generic_arch_v2+"; 5091e1069839SBorislav Petkov break; 5092e1069839SBorislav Petkov } 5093e1069839SBorislav Petkov } 5094e1069839SBorislav Petkov 50950e96f31eSJordan Borgner snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 5096b00233b5SAndi Kleen 5097a5df70c3SAndi Kleen 5098baa0c833SJiri Olsa group_events_td.attrs = td_attr; 5099baa0c833SJiri Olsa group_events_mem.attrs = mem_attr; 5100baa0c833SJiri Olsa group_events_tsx.attrs = tsx_attr; 51013ea40ac7SJiri Olsa group_format_extra.attrs = extra_attr; 5102b6576880SJiri Olsa group_format_extra_skl.attrs = extra_skl_attr; 5103baa0c833SJiri Olsa 5104baa0c833SJiri Olsa x86_pmu.attr_update = attr_update; 5105d4ae5529SJiri Olsa 5106e1069839SBorislav Petkov if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 5107e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5108e1069839SBorislav Petkov x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 5109e1069839SBorislav Petkov x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 5110e1069839SBorislav Petkov } 5111ad5013d5SColin King x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 5112e1069839SBorislav Petkov 5113e1069839SBorislav Petkov if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5114e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5115e1069839SBorislav Petkov x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 5116e1069839SBorislav Petkov x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 5117e1069839SBorislav Petkov } 5118e1069839SBorislav Petkov 5119e1069839SBorislav Petkov x86_pmu.intel_ctrl |= 5120e1069839SBorislav Petkov ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 5121e1069839SBorislav Petkov 5122e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 5123e1069839SBorislav Petkov /* 5124e1069839SBorislav Petkov * event on fixed counter2 (REF_CYCLES) only works on this 5125e1069839SBorislav Petkov * counter, so do not extend mask to generic counters 5126e1069839SBorislav Petkov */ 5127e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 5128e1069839SBorislav Petkov if (c->cmask == FIXED_EVENT_FLAGS 5129e1069839SBorislav Petkov && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 5130e1069839SBorislav Petkov c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 5131e1069839SBorislav Petkov } 5132e1069839SBorislav Petkov c->idxmsk64 &= 51336d6f2833SAndrey Ryabinin ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 5134e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 5135e1069839SBorislav Petkov } 5136e1069839SBorislav Petkov } 5137e1069839SBorislav Petkov 5138e1069839SBorislav Petkov /* 5139e1069839SBorislav Petkov * Access LBR MSR may cause #GP under certain circumstances. 5140e1069839SBorislav Petkov * E.g. KVM doesn't support LBR MSR 5141e1069839SBorislav Petkov * Check all LBT MSR here. 5142e1069839SBorislav Petkov * Disable LBR access if any LBR MSRs can not be accessed. 5143e1069839SBorislav Petkov */ 5144e1069839SBorislav Petkov if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 5145e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 5146e1069839SBorislav Petkov for (i = 0; i < x86_pmu.lbr_nr; i++) { 5147e1069839SBorislav Petkov if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 5148e1069839SBorislav Petkov check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 5149e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 5150e1069839SBorislav Petkov } 5151e1069839SBorislav Petkov 51521f157286SJiri Olsa if (x86_pmu.lbr_nr) 5153f09509b9SDavid Carrillo-Cisneros pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 5154b00233b5SAndi Kleen 5155e1069839SBorislav Petkov /* 5156e1069839SBorislav Petkov * Access extra MSR may cause #GP under certain circumstances. 5157e1069839SBorislav Petkov * E.g. KVM doesn't support offcore event 5158e1069839SBorislav Petkov * Check all extra_regs here. 5159e1069839SBorislav Petkov */ 5160e1069839SBorislav Petkov if (x86_pmu.extra_regs) { 5161e1069839SBorislav Petkov for (er = x86_pmu.extra_regs; er->msr; er++) { 5162e1069839SBorislav Petkov er->extra_msr_access = check_msr(er->msr, 0x11UL); 5163e1069839SBorislav Petkov /* Disable LBR select mapping */ 5164e1069839SBorislav Petkov if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5165e1069839SBorislav Petkov x86_pmu.lbr_sel_map = NULL; 5166e1069839SBorislav Petkov } 5167e1069839SBorislav Petkov } 5168e1069839SBorislav Petkov 5169e1069839SBorislav Petkov /* Support full width counters using alternative MSR range */ 5170e1069839SBorislav Petkov if (x86_pmu.intel_cap.full_width_write) { 51717f612a7fSPeter Zijlstra (Intel) x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 5172e1069839SBorislav Petkov x86_pmu.perfctr = MSR_IA32_PMC0; 5173e1069839SBorislav Petkov pr_cont("full-width counters, "); 5174e1069839SBorislav Petkov } 5175e1069839SBorislav Petkov 5176af3bdb99SAndi Kleen /* 5177af3bdb99SAndi Kleen * For arch perfmon 4 use counter freezing to avoid 5178af3bdb99SAndi Kleen * several MSR accesses in the PMI. 5179af3bdb99SAndi Kleen */ 5180af3bdb99SAndi Kleen if (x86_pmu.counter_freezing) 5181af3bdb99SAndi Kleen x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 5182af3bdb99SAndi Kleen 5183e1069839SBorislav Petkov return 0; 5184e1069839SBorislav Petkov } 5185e1069839SBorislav Petkov 5186e1069839SBorislav Petkov /* 5187e1069839SBorislav Petkov * HT bug: phase 2 init 5188e1069839SBorislav Petkov * Called once we have valid topology information to check 5189e1069839SBorislav Petkov * whether or not HT is enabled 5190e1069839SBorislav Petkov * If HT is off, then we disable the workaround 5191e1069839SBorislav Petkov */ 5192e1069839SBorislav Petkov static __init int fixup_ht_bug(void) 5193e1069839SBorislav Petkov { 5194030ba6cdSAndi Kleen int c; 5195e1069839SBorislav Petkov /* 5196e1069839SBorislav Petkov * problem not present on this CPU model, nothing to do 5197e1069839SBorislav Petkov */ 5198e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 5199e1069839SBorislav Petkov return 0; 5200e1069839SBorislav Petkov 5201030ba6cdSAndi Kleen if (topology_max_smt_threads() > 1) { 5202e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 5203e1069839SBorislav Petkov return 0; 5204e1069839SBorislav Petkov } 5205e1069839SBorislav Petkov 52062406e3b1SPeter Zijlstra cpus_read_lock(); 52072406e3b1SPeter Zijlstra 52082406e3b1SPeter Zijlstra hardlockup_detector_perf_stop(); 5209e1069839SBorislav Petkov 5210e1069839SBorislav Petkov x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 5211e1069839SBorislav Petkov 5212e1069839SBorislav Petkov x86_pmu.start_scheduling = NULL; 5213e1069839SBorislav Petkov x86_pmu.commit_scheduling = NULL; 5214e1069839SBorislav Petkov x86_pmu.stop_scheduling = NULL; 5215e1069839SBorislav Petkov 52162406e3b1SPeter Zijlstra hardlockup_detector_perf_restart(); 5217e1069839SBorislav Petkov 52181ba143a5SSebastian Andrzej Siewior for_each_online_cpu(c) 5219d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 5220e1069839SBorislav Petkov 52211ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 5222e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 5223e1069839SBorislav Petkov return 0; 5224e1069839SBorislav Petkov } 5225e1069839SBorislav Petkov subsys_initcall(fixup_ht_bug) 5226