1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1069839SBorislav Petkov /* 3e1069839SBorislav Petkov * Per core/cpu state 4e1069839SBorislav Petkov * 5e1069839SBorislav Petkov * Used to coordinate shared registers between HT threads or 6e1069839SBorislav Petkov * among events on a single PMU. 7e1069839SBorislav Petkov */ 8e1069839SBorislav Petkov 9e1069839SBorislav Petkov #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10e1069839SBorislav Petkov 11e1069839SBorislav Petkov #include <linux/stddef.h> 12e1069839SBorislav Petkov #include <linux/types.h> 13e1069839SBorislav Petkov #include <linux/init.h> 14e1069839SBorislav Petkov #include <linux/slab.h> 15e1069839SBorislav Petkov #include <linux/export.h> 16e1069839SBorislav Petkov #include <linux/nmi.h> 17e1069839SBorislav Petkov 18e1069839SBorislav Petkov #include <asm/cpufeature.h> 19e1069839SBorislav Petkov #include <asm/hardirq.h> 20ef5f9f47SDave Hansen #include <asm/intel-family.h> 2142880f72SAlexander Shishkin #include <asm/intel_pt.h> 22e1069839SBorislav Petkov #include <asm/apic.h> 239b545c04SAndi Kleen #include <asm/cpu_device_id.h> 24e1069839SBorislav Petkov 2527f6d22bSBorislav Petkov #include "../perf_event.h" 26e1069839SBorislav Petkov 27e1069839SBorislav Petkov /* 28e1069839SBorislav Petkov * Intel PerfMon, used on Core and later. 29e1069839SBorislav Petkov */ 30e1069839SBorislav Petkov static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31e1069839SBorislav Petkov { 32e1069839SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33e1069839SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38e1069839SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39e1069839SBorislav Petkov [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40e1069839SBorislav Petkov }; 41e1069839SBorislav Petkov 42e1069839SBorislav Petkov static struct event_constraint intel_core_event_constraints[] __read_mostly = 43e1069839SBorislav Petkov { 44e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50e1069839SBorislav Petkov EVENT_CONSTRAINT_END 51e1069839SBorislav Petkov }; 52e1069839SBorislav Petkov 53e1069839SBorislav Petkov static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54e1069839SBorislav Petkov { 55e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68e1069839SBorislav Petkov EVENT_CONSTRAINT_END 69e1069839SBorislav Petkov }; 70e1069839SBorislav Petkov 71e1069839SBorislav Petkov static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72e1069839SBorislav Petkov { 73e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84e1069839SBorislav Petkov EVENT_CONSTRAINT_END 85e1069839SBorislav Petkov }; 86e1069839SBorislav Petkov 87e1069839SBorislav Petkov static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88e1069839SBorislav Petkov { 89e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92e1069839SBorislav Petkov EVENT_EXTRA_END 93e1069839SBorislav Petkov }; 94e1069839SBorislav Petkov 95e1069839SBorislav Petkov static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96e1069839SBorislav Petkov { 97e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104e1069839SBorislav Petkov EVENT_CONSTRAINT_END 105e1069839SBorislav Petkov }; 106e1069839SBorislav Petkov 107e1069839SBorislav Petkov static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108e1069839SBorislav Petkov { 109e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121e1069839SBorislav Petkov 1229010ae4aSStephane Eranian /* 1239010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1249010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1259010ae4aSStephane Eranian */ 126e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130e1069839SBorislav Petkov 131e1069839SBorislav Petkov EVENT_CONSTRAINT_END 132e1069839SBorislav Petkov }; 133e1069839SBorislav Petkov 134e1069839SBorislav Petkov static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135e1069839SBorislav Petkov { 136e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 141e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149e1069839SBorislav Petkov 1509010ae4aSStephane Eranian /* 1519010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1529010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1539010ae4aSStephane Eranian */ 154e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158e1069839SBorislav Petkov 159e1069839SBorislav Petkov EVENT_CONSTRAINT_END 160e1069839SBorislav Petkov }; 161e1069839SBorislav Petkov 162e1069839SBorislav Petkov static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163e1069839SBorislav Petkov { 164e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168e1069839SBorislav Petkov EVENT_EXTRA_END 169e1069839SBorislav Petkov }; 170e1069839SBorislav Petkov 171e1069839SBorislav Petkov static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172e1069839SBorislav Petkov { 173e1069839SBorislav Petkov EVENT_CONSTRAINT_END 174e1069839SBorislav Petkov }; 175e1069839SBorislav Petkov 176e1069839SBorislav Petkov static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177e1069839SBorislav Petkov { 178e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181e1069839SBorislav Petkov EVENT_CONSTRAINT_END 182e1069839SBorislav Petkov }; 183e1069839SBorislav Petkov 184e1069839SBorislav Petkov static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185e1069839SBorislav Petkov { 186e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189e1069839SBorislav Petkov EVENT_CONSTRAINT_END 190e1069839SBorislav Petkov }; 191e1069839SBorislav Petkov 19220f36278SLukasz Odzioba static struct event_constraint intel_skl_event_constraints[] = { 193e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1979010ae4aSStephane Eranian 1989010ae4aSStephane Eranian /* 1999010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 2009010ae4aSStephane Eranian */ 2019010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 2029010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 2039010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 2049010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 2059010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 2069010ae4aSStephane Eranian 207e1069839SBorislav Petkov EVENT_CONSTRAINT_END 208e1069839SBorislav Petkov }; 209e1069839SBorislav Petkov 210e1069839SBorislav Petkov static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 2119c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 2129c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213e1069839SBorislav Petkov EVENT_EXTRA_END 214e1069839SBorislav Petkov }; 215e1069839SBorislav Petkov 216e1069839SBorislav Petkov static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221e1069839SBorislav Petkov EVENT_EXTRA_END 222e1069839SBorislav Petkov }; 223e1069839SBorislav Petkov 224e1069839SBorislav Petkov static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229e1069839SBorislav Petkov EVENT_EXTRA_END 230e1069839SBorislav Petkov }; 231e1069839SBorislav Petkov 232e1069839SBorislav Petkov static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236e1069839SBorislav Petkov /* 237e1069839SBorislav Petkov * Note the low 8 bits eventsel code is not a continuous field, containing 238e1069839SBorislav Petkov * some #GPing bits. These are masked out. 239e1069839SBorislav Petkov */ 240e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241e1069839SBorislav Petkov EVENT_EXTRA_END 242e1069839SBorislav Petkov }; 243e1069839SBorislav Petkov 24460176089SKan Liang static struct event_constraint intel_icl_event_constraints[] = { 24560176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246010cb002SKan Liang FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */ 24760176089SKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 24860176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 24960176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 25059a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 25159a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 25259a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 25359a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 25460176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 25560176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 25660176089SKan Liang INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 25760176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 25860176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 25960176089SKan Liang INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 260306e3e91SKan Liang INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 261306e3e91SKan Liang INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 26260176089SKan Liang INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 26360176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 26460176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 26560176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 26660176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 26760176089SKan Liang EVENT_CONSTRAINT_END 26860176089SKan Liang }; 26960176089SKan Liang 27060176089SKan Liang static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 2713b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 2723b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 27360176089SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 27460176089SKan Liang INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 27560176089SKan Liang EVENT_EXTRA_END 27660176089SKan Liang }; 27760176089SKan Liang 278*61b985e3SKan Liang static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 279*61b985e3SKan Liang INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 280*61b985e3SKan Liang INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 281*61b985e3SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 282*61b985e3SKan Liang INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 283*61b985e3SKan Liang EVENT_EXTRA_END 284*61b985e3SKan Liang }; 285*61b985e3SKan Liang 286*61b985e3SKan Liang static struct event_constraint intel_spr_event_constraints[] = { 287*61b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 288*61b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */ 289*61b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 290*61b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 291*61b985e3SKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 292*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 293*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 294*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 295*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 296*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 297*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 298*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 299*61b985e3SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 300*61b985e3SKan Liang 301*61b985e3SKan Liang INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 302*61b985e3SKan Liang INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 303*61b985e3SKan Liang /* 304*61b985e3SKan Liang * Generally event codes < 0x90 are restricted to counters 0-3. 305*61b985e3SKan Liang * The 0x2E and 0x3C are exception, which has no restriction. 306*61b985e3SKan Liang */ 307*61b985e3SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 308*61b985e3SKan Liang 309*61b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 310*61b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 311*61b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 312*61b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 313*61b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 314*61b985e3SKan Liang INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 315*61b985e3SKan Liang INTEL_EVENT_CONSTRAINT(0xce, 0x1), 316*61b985e3SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 317*61b985e3SKan Liang /* 318*61b985e3SKan Liang * Generally event codes >= 0x90 are likely to have no restrictions. 319*61b985e3SKan Liang * The exception are defined as above. 320*61b985e3SKan Liang */ 321*61b985e3SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 322*61b985e3SKan Liang 323*61b985e3SKan Liang EVENT_CONSTRAINT_END 324*61b985e3SKan Liang }; 325*61b985e3SKan Liang 326*61b985e3SKan Liang 327e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 328e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 329e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 330e1069839SBorislav Petkov 331d4ae5529SJiri Olsa static struct attribute *nhm_mem_events_attrs[] = { 332e1069839SBorislav Petkov EVENT_PTR(mem_ld_nhm), 333e1069839SBorislav Petkov NULL, 334e1069839SBorislav Petkov }; 335e1069839SBorislav Petkov 336a39fcae7SAndi Kleen /* 337a39fcae7SAndi Kleen * topdown events for Intel Core CPUs. 338a39fcae7SAndi Kleen * 339a39fcae7SAndi Kleen * The events are all in slots, which is a free slot in a 4 wide 340a39fcae7SAndi Kleen * pipeline. Some events are already reported in slots, for cycle 341a39fcae7SAndi Kleen * events we multiply by the pipeline width (4). 342a39fcae7SAndi Kleen * 343a39fcae7SAndi Kleen * With Hyper Threading on, topdown metrics are either summed or averaged 344a39fcae7SAndi Kleen * between the threads of a core: (count_t0 + count_t1). 345a39fcae7SAndi Kleen * 346a39fcae7SAndi Kleen * For the average case the metric is always scaled to pipeline width, 347a39fcae7SAndi Kleen * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 348a39fcae7SAndi Kleen */ 349a39fcae7SAndi Kleen 350a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 351a39fcae7SAndi Kleen "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 352a39fcae7SAndi Kleen "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 353a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 354a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 355a39fcae7SAndi Kleen "event=0xe,umask=0x1"); /* uops_issued.any */ 356a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 357a39fcae7SAndi Kleen "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 358a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 359a39fcae7SAndi Kleen "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 360a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 361a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 362a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 363a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 364a39fcae7SAndi Kleen "4", "2"); 365a39fcae7SAndi Kleen 36659a854e2SKan Liang EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 36759a854e2SKan Liang EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 36859a854e2SKan Liang EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 36959a854e2SKan Liang EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 37059a854e2SKan Liang EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 371*61b985e3SKan Liang EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 372*61b985e3SKan Liang EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 373*61b985e3SKan Liang EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 374*61b985e3SKan Liang EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 37559a854e2SKan Liang 37620f36278SLukasz Odzioba static struct attribute *snb_events_attrs[] = { 377a39fcae7SAndi Kleen EVENT_PTR(td_slots_issued), 378a39fcae7SAndi Kleen EVENT_PTR(td_slots_retired), 379a39fcae7SAndi Kleen EVENT_PTR(td_fetch_bubbles), 380a39fcae7SAndi Kleen EVENT_PTR(td_total_slots), 381a39fcae7SAndi Kleen EVENT_PTR(td_total_slots_scale), 382a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles), 383a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 384e1069839SBorislav Petkov NULL, 385e1069839SBorislav Petkov }; 386e1069839SBorislav Petkov 387d4ae5529SJiri Olsa static struct attribute *snb_mem_events_attrs[] = { 388d4ae5529SJiri Olsa EVENT_PTR(mem_ld_snb), 389d4ae5529SJiri Olsa EVENT_PTR(mem_st_snb), 390d4ae5529SJiri Olsa NULL, 391d4ae5529SJiri Olsa }; 392d4ae5529SJiri Olsa 393e1069839SBorislav Petkov static struct event_constraint intel_hsw_event_constraints[] = { 394e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 395e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 396e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 397e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 398e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 399e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 400e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 401e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 402e1069839SBorislav Petkov /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 403e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 404e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 405e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 406e1069839SBorislav Petkov 4079010ae4aSStephane Eranian /* 4089010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 4099010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 4109010ae4aSStephane Eranian */ 411e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 412e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 413e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 414e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 415e1069839SBorislav Petkov 416e1069839SBorislav Petkov EVENT_CONSTRAINT_END 417e1069839SBorislav Petkov }; 418e1069839SBorislav Petkov 41920f36278SLukasz Odzioba static struct event_constraint intel_bdw_event_constraints[] = { 420e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 421e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 422e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 423e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 424e1069839SBorislav Petkov INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 4259010ae4aSStephane Eranian /* 4269010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 4279010ae4aSStephane Eranian */ 4289010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 4299010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 4309010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 4319010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 432e1069839SBorislav Petkov EVENT_CONSTRAINT_END 433e1069839SBorislav Petkov }; 434e1069839SBorislav Petkov 435e1069839SBorislav Petkov static u64 intel_pmu_event_map(int hw_event) 436e1069839SBorislav Petkov { 437e1069839SBorislav Petkov return intel_perfmon_event_map[hw_event]; 438e1069839SBorislav Petkov } 439e1069839SBorislav Petkov 440*61b985e3SKan Liang static __initconst const u64 spr_hw_cache_event_ids 441*61b985e3SKan Liang [PERF_COUNT_HW_CACHE_MAX] 442*61b985e3SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 443*61b985e3SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = 444*61b985e3SKan Liang { 445*61b985e3SKan Liang [ C(L1D ) ] = { 446*61b985e3SKan Liang [ C(OP_READ) ] = { 447*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x81d0, 448*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe124, 449*61b985e3SKan Liang }, 450*61b985e3SKan Liang [ C(OP_WRITE) ] = { 451*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x82d0, 452*61b985e3SKan Liang }, 453*61b985e3SKan Liang }, 454*61b985e3SKan Liang [ C(L1I ) ] = { 455*61b985e3SKan Liang [ C(OP_READ) ] = { 456*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe424, 457*61b985e3SKan Liang }, 458*61b985e3SKan Liang [ C(OP_WRITE) ] = { 459*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 460*61b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 461*61b985e3SKan Liang }, 462*61b985e3SKan Liang }, 463*61b985e3SKan Liang [ C(LL ) ] = { 464*61b985e3SKan Liang [ C(OP_READ) ] = { 465*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x12a, 466*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x12a, 467*61b985e3SKan Liang }, 468*61b985e3SKan Liang [ C(OP_WRITE) ] = { 469*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x12a, 470*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x12a, 471*61b985e3SKan Liang }, 472*61b985e3SKan Liang }, 473*61b985e3SKan Liang [ C(DTLB) ] = { 474*61b985e3SKan Liang [ C(OP_READ) ] = { 475*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x81d0, 476*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe12, 477*61b985e3SKan Liang }, 478*61b985e3SKan Liang [ C(OP_WRITE) ] = { 479*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x82d0, 480*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe13, 481*61b985e3SKan Liang }, 482*61b985e3SKan Liang }, 483*61b985e3SKan Liang [ C(ITLB) ] = { 484*61b985e3SKan Liang [ C(OP_READ) ] = { 485*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 486*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0xe11, 487*61b985e3SKan Liang }, 488*61b985e3SKan Liang [ C(OP_WRITE) ] = { 489*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 490*61b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 491*61b985e3SKan Liang }, 492*61b985e3SKan Liang [ C(OP_PREFETCH) ] = { 493*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 494*61b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 495*61b985e3SKan Liang }, 496*61b985e3SKan Liang }, 497*61b985e3SKan Liang [ C(BPU ) ] = { 498*61b985e3SKan Liang [ C(OP_READ) ] = { 499*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x4c4, 500*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x4c5, 501*61b985e3SKan Liang }, 502*61b985e3SKan Liang [ C(OP_WRITE) ] = { 503*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 504*61b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 505*61b985e3SKan Liang }, 506*61b985e3SKan Liang [ C(OP_PREFETCH) ] = { 507*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = -1, 508*61b985e3SKan Liang [ C(RESULT_MISS) ] = -1, 509*61b985e3SKan Liang }, 510*61b985e3SKan Liang }, 511*61b985e3SKan Liang [ C(NODE) ] = { 512*61b985e3SKan Liang [ C(OP_READ) ] = { 513*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x12a, 514*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x12a, 515*61b985e3SKan Liang }, 516*61b985e3SKan Liang }, 517*61b985e3SKan Liang }; 518*61b985e3SKan Liang 519*61b985e3SKan Liang static __initconst const u64 spr_hw_cache_extra_regs 520*61b985e3SKan Liang [PERF_COUNT_HW_CACHE_MAX] 521*61b985e3SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 522*61b985e3SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = 523*61b985e3SKan Liang { 524*61b985e3SKan Liang [ C(LL ) ] = { 525*61b985e3SKan Liang [ C(OP_READ) ] = { 526*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x10001, 527*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x3fbfc00001, 528*61b985e3SKan Liang }, 529*61b985e3SKan Liang [ C(OP_WRITE) ] = { 530*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 531*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x3f3fc00002, 532*61b985e3SKan Liang }, 533*61b985e3SKan Liang }, 534*61b985e3SKan Liang [ C(NODE) ] = { 535*61b985e3SKan Liang [ C(OP_READ) ] = { 536*61b985e3SKan Liang [ C(RESULT_ACCESS) ] = 0x10c000001, 537*61b985e3SKan Liang [ C(RESULT_MISS) ] = 0x3fb3000001, 538*61b985e3SKan Liang }, 539*61b985e3SKan Liang }, 540*61b985e3SKan Liang }; 541*61b985e3SKan Liang 542e1069839SBorislav Petkov /* 543e1069839SBorislav Petkov * Notes on the events: 544e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 545e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 546e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 547e1069839SBorislav Petkov * - prefetches are not included in the counts. 548e1069839SBorislav Petkov * - icache miss does not include decoded icache 549e1069839SBorislav Petkov */ 550e1069839SBorislav Petkov 551e1069839SBorislav Petkov #define SKL_DEMAND_DATA_RD BIT_ULL(0) 552e1069839SBorislav Petkov #define SKL_DEMAND_RFO BIT_ULL(1) 553e1069839SBorislav Petkov #define SKL_ANY_RESPONSE BIT_ULL(16) 554e1069839SBorislav Petkov #define SKL_SUPPLIER_NONE BIT_ULL(17) 555e1069839SBorislav Petkov #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 556e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 557e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 558e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 559e1069839SBorislav Petkov #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 560e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 561e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 562e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 563e1069839SBorislav Petkov #define SKL_SPL_HIT BIT_ULL(30) 564e1069839SBorislav Petkov #define SKL_SNOOP_NONE BIT_ULL(31) 565e1069839SBorislav Petkov #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 566e1069839SBorislav Petkov #define SKL_SNOOP_MISS BIT_ULL(33) 567e1069839SBorislav Petkov #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 568e1069839SBorislav Petkov #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 569e1069839SBorislav Petkov #define SKL_SNOOP_HITM BIT_ULL(36) 570e1069839SBorislav Petkov #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 571e1069839SBorislav Petkov #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 572e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 573e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 574e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 575e1069839SBorislav Petkov #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 576e1069839SBorislav Petkov #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 577e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 578e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 579e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SPL_HIT) 580e1069839SBorislav Petkov #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 581e1069839SBorislav Petkov #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 582e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 583e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 584e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 585e1069839SBorislav Petkov 586e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_event_ids 587e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 588e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 589e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 590e1069839SBorislav Petkov { 591e1069839SBorislav Petkov [ C(L1D ) ] = { 592e1069839SBorislav Petkov [ C(OP_READ) ] = { 593e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 594e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 595e1069839SBorislav Petkov }, 596e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 597e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 598e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 599e1069839SBorislav Petkov }, 600e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 601e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 602e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 603e1069839SBorislav Petkov }, 604e1069839SBorislav Petkov }, 605e1069839SBorislav Petkov [ C(L1I ) ] = { 606e1069839SBorislav Petkov [ C(OP_READ) ] = { 607e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 608e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 609e1069839SBorislav Petkov }, 610e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 611e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 612e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 613e1069839SBorislav Petkov }, 614e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 615e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 616e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 617e1069839SBorislav Petkov }, 618e1069839SBorislav Petkov }, 619e1069839SBorislav Petkov [ C(LL ) ] = { 620e1069839SBorislav Petkov [ C(OP_READ) ] = { 621e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 622e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 623e1069839SBorislav Petkov }, 624e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 625e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 626e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 627e1069839SBorislav Petkov }, 628e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 629e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 630e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 631e1069839SBorislav Petkov }, 632e1069839SBorislav Petkov }, 633e1069839SBorislav Petkov [ C(DTLB) ] = { 634e1069839SBorislav Petkov [ C(OP_READ) ] = { 635e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 636fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 637e1069839SBorislav Petkov }, 638e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 639e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 640fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 641e1069839SBorislav Petkov }, 642e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 643e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 644e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 645e1069839SBorislav Petkov }, 646e1069839SBorislav Petkov }, 647e1069839SBorislav Petkov [ C(ITLB) ] = { 648e1069839SBorislav Petkov [ C(OP_READ) ] = { 649e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 650e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 651e1069839SBorislav Petkov }, 652e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 653e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 654e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 655e1069839SBorislav Petkov }, 656e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 657e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 658e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 659e1069839SBorislav Petkov }, 660e1069839SBorislav Petkov }, 661e1069839SBorislav Petkov [ C(BPU ) ] = { 662e1069839SBorislav Petkov [ C(OP_READ) ] = { 663e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 664e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 665e1069839SBorislav Petkov }, 666e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 667e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 668e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 669e1069839SBorislav Petkov }, 670e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 671e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 672e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 673e1069839SBorislav Petkov }, 674e1069839SBorislav Petkov }, 675e1069839SBorislav Petkov [ C(NODE) ] = { 676e1069839SBorislav Petkov [ C(OP_READ) ] = { 677e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 678e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 679e1069839SBorislav Petkov }, 680e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 681e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 682e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 683e1069839SBorislav Petkov }, 684e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 685e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 686e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 687e1069839SBorislav Petkov }, 688e1069839SBorislav Petkov }, 689e1069839SBorislav Petkov }; 690e1069839SBorislav Petkov 691e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_extra_regs 692e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 693e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 694e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 695e1069839SBorislav Petkov { 696e1069839SBorislav Petkov [ C(LL ) ] = { 697e1069839SBorislav Petkov [ C(OP_READ) ] = { 698e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 699e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 700e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 701e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 702e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 703e1069839SBorislav Petkov }, 704e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 705e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 706e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 707e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 708e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 709e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 710e1069839SBorislav Petkov }, 711e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 712e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 713e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 714e1069839SBorislav Petkov }, 715e1069839SBorislav Petkov }, 716e1069839SBorislav Petkov [ C(NODE) ] = { 717e1069839SBorislav Petkov [ C(OP_READ) ] = { 718e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 719e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 720e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 721e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 722e1069839SBorislav Petkov }, 723e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 724e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 725e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 726e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 727e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 728e1069839SBorislav Petkov }, 729e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 730e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 731e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 732e1069839SBorislav Petkov }, 733e1069839SBorislav Petkov }, 734e1069839SBorislav Petkov }; 735e1069839SBorislav Petkov 736e1069839SBorislav Petkov #define SNB_DMND_DATA_RD (1ULL << 0) 737e1069839SBorislav Petkov #define SNB_DMND_RFO (1ULL << 1) 738e1069839SBorislav Petkov #define SNB_DMND_IFETCH (1ULL << 2) 739e1069839SBorislav Petkov #define SNB_DMND_WB (1ULL << 3) 740e1069839SBorislav Petkov #define SNB_PF_DATA_RD (1ULL << 4) 741e1069839SBorislav Petkov #define SNB_PF_RFO (1ULL << 5) 742e1069839SBorislav Petkov #define SNB_PF_IFETCH (1ULL << 6) 743e1069839SBorislav Petkov #define SNB_LLC_DATA_RD (1ULL << 7) 744e1069839SBorislav Petkov #define SNB_LLC_RFO (1ULL << 8) 745e1069839SBorislav Petkov #define SNB_LLC_IFETCH (1ULL << 9) 746e1069839SBorislav Petkov #define SNB_BUS_LOCKS (1ULL << 10) 747e1069839SBorislav Petkov #define SNB_STRM_ST (1ULL << 11) 748e1069839SBorislav Petkov #define SNB_OTHER (1ULL << 15) 749e1069839SBorislav Petkov #define SNB_RESP_ANY (1ULL << 16) 750e1069839SBorislav Petkov #define SNB_NO_SUPP (1ULL << 17) 751e1069839SBorislav Petkov #define SNB_LLC_HITM (1ULL << 18) 752e1069839SBorislav Petkov #define SNB_LLC_HITE (1ULL << 19) 753e1069839SBorislav Petkov #define SNB_LLC_HITS (1ULL << 20) 754e1069839SBorislav Petkov #define SNB_LLC_HITF (1ULL << 21) 755e1069839SBorislav Petkov #define SNB_LOCAL (1ULL << 22) 756e1069839SBorislav Petkov #define SNB_REMOTE (0xffULL << 23) 757e1069839SBorislav Petkov #define SNB_SNP_NONE (1ULL << 31) 758e1069839SBorislav Petkov #define SNB_SNP_NOT_NEEDED (1ULL << 32) 759e1069839SBorislav Petkov #define SNB_SNP_MISS (1ULL << 33) 760e1069839SBorislav Petkov #define SNB_NO_FWD (1ULL << 34) 761e1069839SBorislav Petkov #define SNB_SNP_FWD (1ULL << 35) 762e1069839SBorislav Petkov #define SNB_HITM (1ULL << 36) 763e1069839SBorislav Petkov #define SNB_NON_DRAM (1ULL << 37) 764e1069839SBorislav Petkov 765e1069839SBorislav Petkov #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 766e1069839SBorislav Petkov #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 767e1069839SBorislav Petkov #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 768e1069839SBorislav Petkov 769e1069839SBorislav Petkov #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 770e1069839SBorislav Petkov SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 771e1069839SBorislav Petkov SNB_HITM) 772e1069839SBorislav Petkov 773e1069839SBorislav Petkov #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 774e1069839SBorislav Petkov #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 775e1069839SBorislav Petkov 776e1069839SBorislav Petkov #define SNB_L3_ACCESS SNB_RESP_ANY 777e1069839SBorislav Petkov #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 778e1069839SBorislav Petkov 779e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_extra_regs 780e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 781e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 782e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 783e1069839SBorislav Petkov { 784e1069839SBorislav Petkov [ C(LL ) ] = { 785e1069839SBorislav Petkov [ C(OP_READ) ] = { 786e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 787e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 788e1069839SBorislav Petkov }, 789e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 790e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 791e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 792e1069839SBorislav Petkov }, 793e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 794e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 795e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 796e1069839SBorislav Petkov }, 797e1069839SBorislav Petkov }, 798e1069839SBorislav Petkov [ C(NODE) ] = { 799e1069839SBorislav Petkov [ C(OP_READ) ] = { 800e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 801e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 802e1069839SBorislav Petkov }, 803e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 804e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 805e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 806e1069839SBorislav Petkov }, 807e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 808e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 809e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 810e1069839SBorislav Petkov }, 811e1069839SBorislav Petkov }, 812e1069839SBorislav Petkov }; 813e1069839SBorislav Petkov 814e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_event_ids 815e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 816e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 817e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 818e1069839SBorislav Petkov { 819e1069839SBorislav Petkov [ C(L1D) ] = { 820e1069839SBorislav Petkov [ C(OP_READ) ] = { 821e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 822e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 823e1069839SBorislav Petkov }, 824e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 825e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 826e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 827e1069839SBorislav Petkov }, 828e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 829e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 830e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 831e1069839SBorislav Petkov }, 832e1069839SBorislav Petkov }, 833e1069839SBorislav Petkov [ C(L1I ) ] = { 834e1069839SBorislav Petkov [ C(OP_READ) ] = { 835e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 836e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 837e1069839SBorislav Petkov }, 838e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 839e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 840e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 841e1069839SBorislav Petkov }, 842e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 843e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 844e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 845e1069839SBorislav Petkov }, 846e1069839SBorislav Petkov }, 847e1069839SBorislav Petkov [ C(LL ) ] = { 848e1069839SBorislav Petkov [ C(OP_READ) ] = { 849e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 850e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 851e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 852e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 853e1069839SBorislav Petkov }, 854e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 855e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 856e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 857e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 858e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 859e1069839SBorislav Petkov }, 860e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 861e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 862e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 863e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 864e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 865e1069839SBorislav Petkov }, 866e1069839SBorislav Petkov }, 867e1069839SBorislav Petkov [ C(DTLB) ] = { 868e1069839SBorislav Petkov [ C(OP_READ) ] = { 869e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 870e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 871e1069839SBorislav Petkov }, 872e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 873e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 874e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 875e1069839SBorislav Petkov }, 876e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 877e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 878e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 879e1069839SBorislav Petkov }, 880e1069839SBorislav Petkov }, 881e1069839SBorislav Petkov [ C(ITLB) ] = { 882e1069839SBorislav Petkov [ C(OP_READ) ] = { 883e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 884e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 885e1069839SBorislav Petkov }, 886e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 887e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 888e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 889e1069839SBorislav Petkov }, 890e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 891e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 892e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 893e1069839SBorislav Petkov }, 894e1069839SBorislav Petkov }, 895e1069839SBorislav Petkov [ C(BPU ) ] = { 896e1069839SBorislav Petkov [ C(OP_READ) ] = { 897e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 898e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 899e1069839SBorislav Petkov }, 900e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 901e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 902e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 903e1069839SBorislav Petkov }, 904e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 905e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 906e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 907e1069839SBorislav Petkov }, 908e1069839SBorislav Petkov }, 909e1069839SBorislav Petkov [ C(NODE) ] = { 910e1069839SBorislav Petkov [ C(OP_READ) ] = { 911e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 912e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 913e1069839SBorislav Petkov }, 914e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 915e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 916e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 917e1069839SBorislav Petkov }, 918e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 919e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 920e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 921e1069839SBorislav Petkov }, 922e1069839SBorislav Petkov }, 923e1069839SBorislav Petkov 924e1069839SBorislav Petkov }; 925e1069839SBorislav Petkov 926e1069839SBorislav Petkov /* 927e1069839SBorislav Petkov * Notes on the events: 928e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 929e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 930e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 931e1069839SBorislav Petkov * - prefetches are not included in the counts because they are not 932e1069839SBorislav Petkov * reliably counted. 933e1069839SBorislav Petkov */ 934e1069839SBorislav Petkov 935e1069839SBorislav Petkov #define HSW_DEMAND_DATA_RD BIT_ULL(0) 936e1069839SBorislav Petkov #define HSW_DEMAND_RFO BIT_ULL(1) 937e1069839SBorislav Petkov #define HSW_ANY_RESPONSE BIT_ULL(16) 938e1069839SBorislav Petkov #define HSW_SUPPLIER_NONE BIT_ULL(17) 939e1069839SBorislav Petkov #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 940e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 941e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 942e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 943e1069839SBorislav Petkov #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 944e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 945e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 946e1069839SBorislav Petkov #define HSW_SNOOP_NONE BIT_ULL(31) 947e1069839SBorislav Petkov #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 948e1069839SBorislav Petkov #define HSW_SNOOP_MISS BIT_ULL(33) 949e1069839SBorislav Petkov #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 950e1069839SBorislav Petkov #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 951e1069839SBorislav Petkov #define HSW_SNOOP_HITM BIT_ULL(36) 952e1069839SBorislav Petkov #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 953e1069839SBorislav Petkov #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 954e1069839SBorislav Petkov HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 955e1069839SBorislav Petkov HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 956e1069839SBorislav Petkov HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 957e1069839SBorislav Petkov #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 958e1069839SBorislav Petkov #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 959e1069839SBorislav Petkov #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 960e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 961e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 962e1069839SBorislav Petkov #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 963e1069839SBorislav Petkov 964e1069839SBorislav Petkov #define BDW_L3_MISS_LOCAL BIT(26) 965e1069839SBorislav Petkov #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 966e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 967e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 968e1069839SBorislav Petkov 969e1069839SBorislav Petkov 970e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_event_ids 971e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 972e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 973e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 974e1069839SBorislav Petkov { 975e1069839SBorislav Petkov [ C(L1D ) ] = { 976e1069839SBorislav Petkov [ C(OP_READ) ] = { 977e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 978e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 979e1069839SBorislav Petkov }, 980e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 981e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 982e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 983e1069839SBorislav Petkov }, 984e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 985e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 986e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 987e1069839SBorislav Petkov }, 988e1069839SBorislav Petkov }, 989e1069839SBorislav Petkov [ C(L1I ) ] = { 990e1069839SBorislav Petkov [ C(OP_READ) ] = { 991e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 992e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 993e1069839SBorislav Petkov }, 994e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 995e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 996e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 997e1069839SBorislav Petkov }, 998e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 999e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1000e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1001e1069839SBorislav Petkov }, 1002e1069839SBorislav Petkov }, 1003e1069839SBorislav Petkov [ C(LL ) ] = { 1004e1069839SBorislav Petkov [ C(OP_READ) ] = { 1005e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1006e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1007e1069839SBorislav Petkov }, 1008e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1009e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1010e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1011e1069839SBorislav Petkov }, 1012e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1013e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1014e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1015e1069839SBorislav Petkov }, 1016e1069839SBorislav Petkov }, 1017e1069839SBorislav Petkov [ C(DTLB) ] = { 1018e1069839SBorislav Petkov [ C(OP_READ) ] = { 1019e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1020e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1021e1069839SBorislav Petkov }, 1022e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1023e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1024e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1025e1069839SBorislav Petkov }, 1026e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1027e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1028e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1029e1069839SBorislav Petkov }, 1030e1069839SBorislav Petkov }, 1031e1069839SBorislav Petkov [ C(ITLB) ] = { 1032e1069839SBorislav Petkov [ C(OP_READ) ] = { 1033e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1034e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1035e1069839SBorislav Petkov }, 1036e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1037e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1038e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1039e1069839SBorislav Petkov }, 1040e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1041e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1042e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1043e1069839SBorislav Petkov }, 1044e1069839SBorislav Petkov }, 1045e1069839SBorislav Petkov [ C(BPU ) ] = { 1046e1069839SBorislav Petkov [ C(OP_READ) ] = { 1047e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1048e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1049e1069839SBorislav Petkov }, 1050e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1051e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1052e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1053e1069839SBorislav Petkov }, 1054e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1055e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1056e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1057e1069839SBorislav Petkov }, 1058e1069839SBorislav Petkov }, 1059e1069839SBorislav Petkov [ C(NODE) ] = { 1060e1069839SBorislav Petkov [ C(OP_READ) ] = { 1061e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1062e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1063e1069839SBorislav Petkov }, 1064e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1065e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1066e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1067e1069839SBorislav Petkov }, 1068e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1069e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1070e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1071e1069839SBorislav Petkov }, 1072e1069839SBorislav Petkov }, 1073e1069839SBorislav Petkov }; 1074e1069839SBorislav Petkov 1075e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_extra_regs 1076e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1077e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1078e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1079e1069839SBorislav Petkov { 1080e1069839SBorislav Petkov [ C(LL ) ] = { 1081e1069839SBorislav Petkov [ C(OP_READ) ] = { 1082e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1083e1069839SBorislav Petkov HSW_LLC_ACCESS, 1084e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1085e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 1086e1069839SBorislav Petkov }, 1087e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1088e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1089e1069839SBorislav Petkov HSW_LLC_ACCESS, 1090e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1091e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 1092e1069839SBorislav Petkov }, 1093e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1094e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1095e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1096e1069839SBorislav Petkov }, 1097e1069839SBorislav Petkov }, 1098e1069839SBorislav Petkov [ C(NODE) ] = { 1099e1069839SBorislav Petkov [ C(OP_READ) ] = { 1100e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1101e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 1102e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1103e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1104e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 1105e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1106e1069839SBorislav Petkov }, 1107e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1108e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1109e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 1110e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1111e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1112e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 1113e1069839SBorislav Petkov HSW_SNOOP_DRAM, 1114e1069839SBorislav Petkov }, 1115e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1116e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1117e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1118e1069839SBorislav Petkov }, 1119e1069839SBorislav Petkov }, 1120e1069839SBorislav Petkov }; 1121e1069839SBorislav Petkov 1122e1069839SBorislav Petkov static __initconst const u64 westmere_hw_cache_event_ids 1123e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1124e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1125e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1126e1069839SBorislav Petkov { 1127e1069839SBorislav Petkov [ C(L1D) ] = { 1128e1069839SBorislav Petkov [ C(OP_READ) ] = { 1129e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1130e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1131e1069839SBorislav Petkov }, 1132e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1133e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1134e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1135e1069839SBorislav Petkov }, 1136e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1137e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1138e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1139e1069839SBorislav Petkov }, 1140e1069839SBorislav Petkov }, 1141e1069839SBorislav Petkov [ C(L1I ) ] = { 1142e1069839SBorislav Petkov [ C(OP_READ) ] = { 1143e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1144e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1145e1069839SBorislav Petkov }, 1146e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1147e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1148e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1149e1069839SBorislav Petkov }, 1150e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1151e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1152e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1153e1069839SBorislav Petkov }, 1154e1069839SBorislav Petkov }, 1155e1069839SBorislav Petkov [ C(LL ) ] = { 1156e1069839SBorislav Petkov [ C(OP_READ) ] = { 1157e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1158e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1159e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1160e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1161e1069839SBorislav Petkov }, 1162e1069839SBorislav Petkov /* 1163e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1164e1069839SBorislav Petkov * on RFO. 1165e1069839SBorislav Petkov */ 1166e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1167e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1168e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1169e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1170e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1171e1069839SBorislav Petkov }, 1172e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1173e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1174e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1175e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1176e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1177e1069839SBorislav Petkov }, 1178e1069839SBorislav Petkov }, 1179e1069839SBorislav Petkov [ C(DTLB) ] = { 1180e1069839SBorislav Petkov [ C(OP_READ) ] = { 1181e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1182e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1183e1069839SBorislav Petkov }, 1184e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1185e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1186e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1187e1069839SBorislav Petkov }, 1188e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1189e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1190e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1191e1069839SBorislav Petkov }, 1192e1069839SBorislav Petkov }, 1193e1069839SBorislav Petkov [ C(ITLB) ] = { 1194e1069839SBorislav Petkov [ C(OP_READ) ] = { 1195e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1196e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1197e1069839SBorislav Petkov }, 1198e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1199e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1200e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1201e1069839SBorislav Petkov }, 1202e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1203e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1204e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1205e1069839SBorislav Petkov }, 1206e1069839SBorislav Petkov }, 1207e1069839SBorislav Petkov [ C(BPU ) ] = { 1208e1069839SBorislav Petkov [ C(OP_READ) ] = { 1209e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1210e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1211e1069839SBorislav Petkov }, 1212e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1213e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1214e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1215e1069839SBorislav Petkov }, 1216e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1217e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1218e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1219e1069839SBorislav Petkov }, 1220e1069839SBorislav Petkov }, 1221e1069839SBorislav Petkov [ C(NODE) ] = { 1222e1069839SBorislav Petkov [ C(OP_READ) ] = { 1223e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1224e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1225e1069839SBorislav Petkov }, 1226e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1227e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1228e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1229e1069839SBorislav Petkov }, 1230e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1231e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1232e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1233e1069839SBorislav Petkov }, 1234e1069839SBorislav Petkov }, 1235e1069839SBorislav Petkov }; 1236e1069839SBorislav Petkov 1237e1069839SBorislav Petkov /* 1238e1069839SBorislav Petkov * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1239e1069839SBorislav Petkov * See IA32 SDM Vol 3B 30.6.1.3 1240e1069839SBorislav Petkov */ 1241e1069839SBorislav Petkov 1242e1069839SBorislav Petkov #define NHM_DMND_DATA_RD (1 << 0) 1243e1069839SBorislav Petkov #define NHM_DMND_RFO (1 << 1) 1244e1069839SBorislav Petkov #define NHM_DMND_IFETCH (1 << 2) 1245e1069839SBorislav Petkov #define NHM_DMND_WB (1 << 3) 1246e1069839SBorislav Petkov #define NHM_PF_DATA_RD (1 << 4) 1247e1069839SBorislav Petkov #define NHM_PF_DATA_RFO (1 << 5) 1248e1069839SBorislav Petkov #define NHM_PF_IFETCH (1 << 6) 1249e1069839SBorislav Petkov #define NHM_OFFCORE_OTHER (1 << 7) 1250e1069839SBorislav Petkov #define NHM_UNCORE_HIT (1 << 8) 1251e1069839SBorislav Petkov #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1252e1069839SBorislav Petkov #define NHM_OTHER_CORE_HITM (1 << 10) 1253e1069839SBorislav Petkov /* reserved */ 1254e1069839SBorislav Petkov #define NHM_REMOTE_CACHE_FWD (1 << 12) 1255e1069839SBorislav Petkov #define NHM_REMOTE_DRAM (1 << 13) 1256e1069839SBorislav Petkov #define NHM_LOCAL_DRAM (1 << 14) 1257e1069839SBorislav Petkov #define NHM_NON_DRAM (1 << 15) 1258e1069839SBorislav Petkov 1259e1069839SBorislav Petkov #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1260e1069839SBorislav Petkov #define NHM_REMOTE (NHM_REMOTE_DRAM) 1261e1069839SBorislav Petkov 1262e1069839SBorislav Petkov #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1263e1069839SBorislav Petkov #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1264e1069839SBorislav Petkov #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1265e1069839SBorislav Petkov 1266e1069839SBorislav Petkov #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1267e1069839SBorislav Petkov #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1268e1069839SBorislav Petkov #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1269e1069839SBorislav Petkov 1270e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_extra_regs 1271e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1272e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1273e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1274e1069839SBorislav Petkov { 1275e1069839SBorislav Petkov [ C(LL ) ] = { 1276e1069839SBorislav Petkov [ C(OP_READ) ] = { 1277e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1278e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1279e1069839SBorislav Petkov }, 1280e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1281e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1282e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1283e1069839SBorislav Petkov }, 1284e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1285e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1286e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1287e1069839SBorislav Petkov }, 1288e1069839SBorislav Petkov }, 1289e1069839SBorislav Petkov [ C(NODE) ] = { 1290e1069839SBorislav Petkov [ C(OP_READ) ] = { 1291e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1292e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1293e1069839SBorislav Petkov }, 1294e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1295e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1296e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1297e1069839SBorislav Petkov }, 1298e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1299e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1300e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1301e1069839SBorislav Petkov }, 1302e1069839SBorislav Petkov }, 1303e1069839SBorislav Petkov }; 1304e1069839SBorislav Petkov 1305e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_event_ids 1306e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1307e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1308e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1309e1069839SBorislav Petkov { 1310e1069839SBorislav Petkov [ C(L1D) ] = { 1311e1069839SBorislav Petkov [ C(OP_READ) ] = { 1312e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1313e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1314e1069839SBorislav Petkov }, 1315e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1316e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1317e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1318e1069839SBorislav Petkov }, 1319e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1320e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1321e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1322e1069839SBorislav Petkov }, 1323e1069839SBorislav Petkov }, 1324e1069839SBorislav Petkov [ C(L1I ) ] = { 1325e1069839SBorislav Petkov [ C(OP_READ) ] = { 1326e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1327e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1328e1069839SBorislav Petkov }, 1329e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1330e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1331e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1332e1069839SBorislav Petkov }, 1333e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1334e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1335e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1336e1069839SBorislav Petkov }, 1337e1069839SBorislav Petkov }, 1338e1069839SBorislav Petkov [ C(LL ) ] = { 1339e1069839SBorislav Petkov [ C(OP_READ) ] = { 1340e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1341e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1342e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1343e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1344e1069839SBorislav Petkov }, 1345e1069839SBorislav Petkov /* 1346e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1347e1069839SBorislav Petkov * on RFO. 1348e1069839SBorislav Petkov */ 1349e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1350e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1351e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1352e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1353e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1354e1069839SBorislav Petkov }, 1355e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1356e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1357e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1358e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1359e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1360e1069839SBorislav Petkov }, 1361e1069839SBorislav Petkov }, 1362e1069839SBorislav Petkov [ C(DTLB) ] = { 1363e1069839SBorislav Petkov [ C(OP_READ) ] = { 1364e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1365e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1366e1069839SBorislav Petkov }, 1367e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1368e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1369e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1370e1069839SBorislav Petkov }, 1371e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1372e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1373e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1374e1069839SBorislav Petkov }, 1375e1069839SBorislav Petkov }, 1376e1069839SBorislav Petkov [ C(ITLB) ] = { 1377e1069839SBorislav Petkov [ C(OP_READ) ] = { 1378e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1379e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1380e1069839SBorislav Petkov }, 1381e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1382e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1383e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1384e1069839SBorislav Petkov }, 1385e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1386e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1387e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1388e1069839SBorislav Petkov }, 1389e1069839SBorislav Petkov }, 1390e1069839SBorislav Petkov [ C(BPU ) ] = { 1391e1069839SBorislav Petkov [ C(OP_READ) ] = { 1392e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1393e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1394e1069839SBorislav Petkov }, 1395e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1396e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1397e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1398e1069839SBorislav Petkov }, 1399e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1400e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1401e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1402e1069839SBorislav Petkov }, 1403e1069839SBorislav Petkov }, 1404e1069839SBorislav Petkov [ C(NODE) ] = { 1405e1069839SBorislav Petkov [ C(OP_READ) ] = { 1406e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1407e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1408e1069839SBorislav Petkov }, 1409e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1410e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1411e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1412e1069839SBorislav Petkov }, 1413e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1414e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1415e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1416e1069839SBorislav Petkov }, 1417e1069839SBorislav Petkov }, 1418e1069839SBorislav Petkov }; 1419e1069839SBorislav Petkov 1420e1069839SBorislav Petkov static __initconst const u64 core2_hw_cache_event_ids 1421e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1422e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1423e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1424e1069839SBorislav Petkov { 1425e1069839SBorislav Petkov [ C(L1D) ] = { 1426e1069839SBorislav Petkov [ C(OP_READ) ] = { 1427e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1428e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1429e1069839SBorislav Petkov }, 1430e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1431e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1432e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1433e1069839SBorislav Petkov }, 1434e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1435e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1436e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1437e1069839SBorislav Petkov }, 1438e1069839SBorislav Petkov }, 1439e1069839SBorislav Petkov [ C(L1I ) ] = { 1440e1069839SBorislav Petkov [ C(OP_READ) ] = { 1441e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1442e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1443e1069839SBorislav Petkov }, 1444e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1445e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1446e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1447e1069839SBorislav Petkov }, 1448e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1449e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1450e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1451e1069839SBorislav Petkov }, 1452e1069839SBorislav Petkov }, 1453e1069839SBorislav Petkov [ C(LL ) ] = { 1454e1069839SBorislav Petkov [ C(OP_READ) ] = { 1455e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1456e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1457e1069839SBorislav Petkov }, 1458e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1459e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1460e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1461e1069839SBorislav Petkov }, 1462e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1463e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1464e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1465e1069839SBorislav Petkov }, 1466e1069839SBorislav Petkov }, 1467e1069839SBorislav Petkov [ C(DTLB) ] = { 1468e1069839SBorislav Petkov [ C(OP_READ) ] = { 1469e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1470e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1471e1069839SBorislav Petkov }, 1472e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1473e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1474e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1475e1069839SBorislav Petkov }, 1476e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1477e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1478e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1479e1069839SBorislav Petkov }, 1480e1069839SBorislav Petkov }, 1481e1069839SBorislav Petkov [ C(ITLB) ] = { 1482e1069839SBorislav Petkov [ C(OP_READ) ] = { 1483e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1484e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1485e1069839SBorislav Petkov }, 1486e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1487e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1488e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1489e1069839SBorislav Petkov }, 1490e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1491e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1492e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1493e1069839SBorislav Petkov }, 1494e1069839SBorislav Petkov }, 1495e1069839SBorislav Petkov [ C(BPU ) ] = { 1496e1069839SBorislav Petkov [ C(OP_READ) ] = { 1497e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1498e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1499e1069839SBorislav Petkov }, 1500e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1501e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1502e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1503e1069839SBorislav Petkov }, 1504e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1505e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1506e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1507e1069839SBorislav Petkov }, 1508e1069839SBorislav Petkov }, 1509e1069839SBorislav Petkov }; 1510e1069839SBorislav Petkov 1511e1069839SBorislav Petkov static __initconst const u64 atom_hw_cache_event_ids 1512e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1513e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1514e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1515e1069839SBorislav Petkov { 1516e1069839SBorislav Petkov [ C(L1D) ] = { 1517e1069839SBorislav Petkov [ C(OP_READ) ] = { 1518e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1519e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1520e1069839SBorislav Petkov }, 1521e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1522e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1523e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1524e1069839SBorislav Petkov }, 1525e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1526e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1527e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1528e1069839SBorislav Petkov }, 1529e1069839SBorislav Petkov }, 1530e1069839SBorislav Petkov [ C(L1I ) ] = { 1531e1069839SBorislav Petkov [ C(OP_READ) ] = { 1532e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1533e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1534e1069839SBorislav Petkov }, 1535e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1536e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1537e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1538e1069839SBorislav Petkov }, 1539e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1540e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1541e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1542e1069839SBorislav Petkov }, 1543e1069839SBorislav Petkov }, 1544e1069839SBorislav Petkov [ C(LL ) ] = { 1545e1069839SBorislav Petkov [ C(OP_READ) ] = { 1546e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1547e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1548e1069839SBorislav Petkov }, 1549e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1550e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1551e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1552e1069839SBorislav Petkov }, 1553e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1554e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1555e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1556e1069839SBorislav Petkov }, 1557e1069839SBorislav Petkov }, 1558e1069839SBorislav Petkov [ C(DTLB) ] = { 1559e1069839SBorislav Petkov [ C(OP_READ) ] = { 1560e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1561e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1562e1069839SBorislav Petkov }, 1563e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1564e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1565e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1566e1069839SBorislav Petkov }, 1567e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1568e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1569e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1570e1069839SBorislav Petkov }, 1571e1069839SBorislav Petkov }, 1572e1069839SBorislav Petkov [ C(ITLB) ] = { 1573e1069839SBorislav Petkov [ C(OP_READ) ] = { 1574e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1575e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1576e1069839SBorislav Petkov }, 1577e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1578e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1579e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1580e1069839SBorislav Petkov }, 1581e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1582e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1583e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1584e1069839SBorislav Petkov }, 1585e1069839SBorislav Petkov }, 1586e1069839SBorislav Petkov [ C(BPU ) ] = { 1587e1069839SBorislav Petkov [ C(OP_READ) ] = { 1588e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1589e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1590e1069839SBorislav Petkov }, 1591e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1592e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1593e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1594e1069839SBorislav Petkov }, 1595e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1596e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1597e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1598e1069839SBorislav Petkov }, 1599e1069839SBorislav Petkov }, 1600e1069839SBorislav Petkov }; 1601e1069839SBorislav Petkov 1602eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1603eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1604eb12b8ecSAndi Kleen /* no_alloc_cycles.not_delivered */ 1605eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1606eb12b8ecSAndi Kleen "event=0xca,umask=0x50"); 1607eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1608eb12b8ecSAndi Kleen /* uops_retired.all */ 1609eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1610eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1611eb12b8ecSAndi Kleen /* uops_retired.all */ 1612eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1613eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1614eb12b8ecSAndi Kleen 1615eb12b8ecSAndi Kleen static struct attribute *slm_events_attrs[] = { 1616eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_slm), 1617eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_scale_slm), 1618eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_slm), 1619eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_scale_slm), 1620eb12b8ecSAndi Kleen EVENT_PTR(td_slots_issued_slm), 1621eb12b8ecSAndi Kleen EVENT_PTR(td_slots_retired_slm), 1622eb12b8ecSAndi Kleen NULL 1623eb12b8ecSAndi Kleen }; 1624eb12b8ecSAndi Kleen 1625e1069839SBorislav Petkov static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1626e1069839SBorislav Petkov { 1627e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1628e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1629e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1630e1069839SBorislav Petkov EVENT_EXTRA_END 1631e1069839SBorislav Petkov }; 1632e1069839SBorislav Petkov 1633e1069839SBorislav Petkov #define SLM_DMND_READ SNB_DMND_DATA_RD 1634e1069839SBorislav Petkov #define SLM_DMND_WRITE SNB_DMND_RFO 1635e1069839SBorislav Petkov #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1636e1069839SBorislav Petkov 1637e1069839SBorislav Petkov #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1638e1069839SBorislav Petkov #define SLM_LLC_ACCESS SNB_RESP_ANY 1639e1069839SBorislav Petkov #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1640e1069839SBorislav Petkov 1641e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_extra_regs 1642e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1643e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1644e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1645e1069839SBorislav Petkov { 1646e1069839SBorislav Petkov [ C(LL ) ] = { 1647e1069839SBorislav Petkov [ C(OP_READ) ] = { 1648e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1649e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1650e1069839SBorislav Petkov }, 1651e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1652e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1653e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1654e1069839SBorislav Petkov }, 1655e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1656e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1657e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1658e1069839SBorislav Petkov }, 1659e1069839SBorislav Petkov }, 1660e1069839SBorislav Petkov }; 1661e1069839SBorislav Petkov 1662e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_event_ids 1663e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1664e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1665e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1666e1069839SBorislav Petkov { 1667e1069839SBorislav Petkov [ C(L1D) ] = { 1668e1069839SBorislav Petkov [ C(OP_READ) ] = { 1669e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1670e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1671e1069839SBorislav Petkov }, 1672e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1673e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1674e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1675e1069839SBorislav Petkov }, 1676e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1677e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1678e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1679e1069839SBorislav Petkov }, 1680e1069839SBorislav Petkov }, 1681e1069839SBorislav Petkov [ C(L1I ) ] = { 1682e1069839SBorislav Petkov [ C(OP_READ) ] = { 1683e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1684e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1685e1069839SBorislav Petkov }, 1686e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1687e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1688e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1689e1069839SBorislav Petkov }, 1690e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1691e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1692e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1693e1069839SBorislav Petkov }, 1694e1069839SBorislav Petkov }, 1695e1069839SBorislav Petkov [ C(LL ) ] = { 1696e1069839SBorislav Petkov [ C(OP_READ) ] = { 1697e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1698e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1699e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1700e1069839SBorislav Petkov }, 1701e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1702e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1703e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1704e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1705e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1706e1069839SBorislav Petkov }, 1707e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1708e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1709e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1710e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1711e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1712e1069839SBorislav Petkov }, 1713e1069839SBorislav Petkov }, 1714e1069839SBorislav Petkov [ C(DTLB) ] = { 1715e1069839SBorislav Petkov [ C(OP_READ) ] = { 1716e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1717e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1718e1069839SBorislav Petkov }, 1719e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1720e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1721e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1722e1069839SBorislav Petkov }, 1723e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1724e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1725e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1726e1069839SBorislav Petkov }, 1727e1069839SBorislav Petkov }, 1728e1069839SBorislav Petkov [ C(ITLB) ] = { 1729e1069839SBorislav Petkov [ C(OP_READ) ] = { 1730e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1731e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1732e1069839SBorislav Petkov }, 1733e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1734e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1735e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1736e1069839SBorislav Petkov }, 1737e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1738e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1739e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1740e1069839SBorislav Petkov }, 1741e1069839SBorislav Petkov }, 1742e1069839SBorislav Petkov [ C(BPU ) ] = { 1743e1069839SBorislav Petkov [ C(OP_READ) ] = { 1744e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1745e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1746e1069839SBorislav Petkov }, 1747e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1748e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1749e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1750e1069839SBorislav Petkov }, 1751e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1752e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1753e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1754e1069839SBorislav Petkov }, 1755e1069839SBorislav Petkov }, 1756e1069839SBorislav Petkov }; 1757e1069839SBorislav Petkov 1758ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1759ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1760ed827adbSKan Liang /* UOPS_NOT_DELIVERED.ANY */ 1761ed827adbSKan Liang EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1762ed827adbSKan Liang /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1763ed827adbSKan Liang EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1764ed827adbSKan Liang /* UOPS_RETIRED.ANY */ 1765ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1766ed827adbSKan Liang /* UOPS_ISSUED.ANY */ 1767ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1768ed827adbSKan Liang 1769ed827adbSKan Liang static struct attribute *glm_events_attrs[] = { 1770ed827adbSKan Liang EVENT_PTR(td_total_slots_glm), 1771ed827adbSKan Liang EVENT_PTR(td_total_slots_scale_glm), 1772ed827adbSKan Liang EVENT_PTR(td_fetch_bubbles_glm), 1773ed827adbSKan Liang EVENT_PTR(td_recovery_bubbles_glm), 1774ed827adbSKan Liang EVENT_PTR(td_slots_issued_glm), 1775ed827adbSKan Liang EVENT_PTR(td_slots_retired_glm), 1776ed827adbSKan Liang NULL 1777ed827adbSKan Liang }; 1778ed827adbSKan Liang 17798b92c3a7SKan Liang static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 17808b92c3a7SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 17818b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 17828b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 17838b92c3a7SKan Liang EVENT_EXTRA_END 17848b92c3a7SKan Liang }; 17858b92c3a7SKan Liang 17868b92c3a7SKan Liang #define GLM_DEMAND_DATA_RD BIT_ULL(0) 17878b92c3a7SKan Liang #define GLM_DEMAND_RFO BIT_ULL(1) 17888b92c3a7SKan Liang #define GLM_ANY_RESPONSE BIT_ULL(16) 17898b92c3a7SKan Liang #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 17908b92c3a7SKan Liang #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 17918b92c3a7SKan Liang #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 17928b92c3a7SKan Liang #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 17938b92c3a7SKan Liang #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 17948b92c3a7SKan Liang #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 17958b92c3a7SKan Liang #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 17968b92c3a7SKan Liang 17978b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_event_ids 17988b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 17998b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 18008b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 18018b92c3a7SKan Liang [C(L1D)] = { 18028b92c3a7SKan Liang [C(OP_READ)] = { 18038b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 18048b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18058b92c3a7SKan Liang }, 18068b92c3a7SKan Liang [C(OP_WRITE)] = { 18078b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 18088b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18098b92c3a7SKan Liang }, 18108b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18118b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 18128b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18138b92c3a7SKan Liang }, 18148b92c3a7SKan Liang }, 18158b92c3a7SKan Liang [C(L1I)] = { 18168b92c3a7SKan Liang [C(OP_READ)] = { 18178b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 18188b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 18198b92c3a7SKan Liang }, 18208b92c3a7SKan Liang [C(OP_WRITE)] = { 18218b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18228b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18238b92c3a7SKan Liang }, 18248b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18258b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 18268b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18278b92c3a7SKan Liang }, 18288b92c3a7SKan Liang }, 18298b92c3a7SKan Liang [C(LL)] = { 18308b92c3a7SKan Liang [C(OP_READ)] = { 18318b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18328b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18338b92c3a7SKan Liang }, 18348b92c3a7SKan Liang [C(OP_WRITE)] = { 18358b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18368b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18378b92c3a7SKan Liang }, 18388b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18398b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18408b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 18418b92c3a7SKan Liang }, 18428b92c3a7SKan Liang }, 18438b92c3a7SKan Liang [C(DTLB)] = { 18448b92c3a7SKan Liang [C(OP_READ)] = { 18458b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 18468b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18478b92c3a7SKan Liang }, 18488b92c3a7SKan Liang [C(OP_WRITE)] = { 18498b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 18508b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18518b92c3a7SKan Liang }, 18528b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18538b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 18548b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 18558b92c3a7SKan Liang }, 18568b92c3a7SKan Liang }, 18578b92c3a7SKan Liang [C(ITLB)] = { 18588b92c3a7SKan Liang [C(OP_READ)] = { 18598b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 18608b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 18618b92c3a7SKan Liang }, 18628b92c3a7SKan Liang [C(OP_WRITE)] = { 18638b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18648b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18658b92c3a7SKan Liang }, 18668b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18678b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18688b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18698b92c3a7SKan Liang }, 18708b92c3a7SKan Liang }, 18718b92c3a7SKan Liang [C(BPU)] = { 18728b92c3a7SKan Liang [C(OP_READ)] = { 18738b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 18748b92c3a7SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 18758b92c3a7SKan Liang }, 18768b92c3a7SKan Liang [C(OP_WRITE)] = { 18778b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18788b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18798b92c3a7SKan Liang }, 18808b92c3a7SKan Liang [C(OP_PREFETCH)] = { 18818b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 18828b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 18838b92c3a7SKan Liang }, 18848b92c3a7SKan Liang }, 18858b92c3a7SKan Liang }; 18868b92c3a7SKan Liang 18878b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_extra_regs 18888b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 18898b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 18908b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 18918b92c3a7SKan Liang [C(LL)] = { 18928b92c3a7SKan Liang [C(OP_READ)] = { 18938b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 18948b92c3a7SKan Liang GLM_LLC_ACCESS, 18958b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 18968b92c3a7SKan Liang GLM_LLC_MISS, 18978b92c3a7SKan Liang }, 18988b92c3a7SKan Liang [C(OP_WRITE)] = { 18998b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 19008b92c3a7SKan Liang GLM_LLC_ACCESS, 19018b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 19028b92c3a7SKan Liang GLM_LLC_MISS, 19038b92c3a7SKan Liang }, 19048b92c3a7SKan Liang [C(OP_PREFETCH)] = { 19058b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 19068b92c3a7SKan Liang GLM_LLC_ACCESS, 19078b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 19088b92c3a7SKan Liang GLM_LLC_MISS, 19098b92c3a7SKan Liang }, 19108b92c3a7SKan Liang }, 19118b92c3a7SKan Liang }; 19128b92c3a7SKan Liang 1913dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_event_ids 1914dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1915dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1916dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1917dd0b06b5SKan Liang [C(L1D)] = { 1918dd0b06b5SKan Liang [C(OP_READ)] = { 1919dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1920dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1921dd0b06b5SKan Liang }, 1922dd0b06b5SKan Liang [C(OP_WRITE)] = { 1923dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1924dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1925dd0b06b5SKan Liang }, 1926dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1927dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1928dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1929dd0b06b5SKan Liang }, 1930dd0b06b5SKan Liang }, 1931dd0b06b5SKan Liang [C(L1I)] = { 1932dd0b06b5SKan Liang [C(OP_READ)] = { 1933dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1934dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1935dd0b06b5SKan Liang }, 1936dd0b06b5SKan Liang [C(OP_WRITE)] = { 1937dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1938dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1939dd0b06b5SKan Liang }, 1940dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1941dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1942dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1943dd0b06b5SKan Liang }, 1944dd0b06b5SKan Liang }, 1945dd0b06b5SKan Liang [C(LL)] = { 1946dd0b06b5SKan Liang [C(OP_READ)] = { 1947dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1948dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1949dd0b06b5SKan Liang }, 1950dd0b06b5SKan Liang [C(OP_WRITE)] = { 1951dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1953dd0b06b5SKan Liang }, 1954dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1955dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1956dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1957dd0b06b5SKan Liang }, 1958dd0b06b5SKan Liang }, 1959dd0b06b5SKan Liang [C(DTLB)] = { 1960dd0b06b5SKan Liang [C(OP_READ)] = { 1961dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1962dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1963dd0b06b5SKan Liang }, 1964dd0b06b5SKan Liang [C(OP_WRITE)] = { 1965dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1966dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1967dd0b06b5SKan Liang }, 1968dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1969dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1970dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1971dd0b06b5SKan Liang }, 1972dd0b06b5SKan Liang }, 1973dd0b06b5SKan Liang [C(ITLB)] = { 1974dd0b06b5SKan Liang [C(OP_READ)] = { 1975dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1976dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1977dd0b06b5SKan Liang }, 1978dd0b06b5SKan Liang [C(OP_WRITE)] = { 1979dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1980dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1981dd0b06b5SKan Liang }, 1982dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1983dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1984dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1985dd0b06b5SKan Liang }, 1986dd0b06b5SKan Liang }, 1987dd0b06b5SKan Liang [C(BPU)] = { 1988dd0b06b5SKan Liang [C(OP_READ)] = { 1989dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1990dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1991dd0b06b5SKan Liang }, 1992dd0b06b5SKan Liang [C(OP_WRITE)] = { 1993dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1994dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1995dd0b06b5SKan Liang }, 1996dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1997dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1998dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1999dd0b06b5SKan Liang }, 2000dd0b06b5SKan Liang }, 2001dd0b06b5SKan Liang }; 2002dd0b06b5SKan Liang 2003dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_extra_regs 2004dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 2005dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 2006dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2007dd0b06b5SKan Liang [C(LL)] = { 2008dd0b06b5SKan Liang [C(OP_READ)] = { 2009dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2010dd0b06b5SKan Liang GLM_LLC_ACCESS, 2011dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 2012dd0b06b5SKan Liang GLM_LLC_MISS, 2013dd0b06b5SKan Liang }, 2014dd0b06b5SKan Liang [C(OP_WRITE)] = { 2015dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2016dd0b06b5SKan Liang GLM_LLC_ACCESS, 2017dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2018dd0b06b5SKan Liang GLM_LLC_MISS, 2019dd0b06b5SKan Liang }, 2020dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 2021dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 2022dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 2023dd0b06b5SKan Liang }, 2024dd0b06b5SKan Liang }, 2025dd0b06b5SKan Liang }; 2026dd0b06b5SKan Liang 20276daeb873SKan Liang #define TNT_LOCAL_DRAM BIT_ULL(26) 20286daeb873SKan Liang #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 20296daeb873SKan Liang #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 20306daeb873SKan Liang #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 20316daeb873SKan Liang #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 20326daeb873SKan Liang SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 20336daeb873SKan Liang #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 20346daeb873SKan Liang 20356daeb873SKan Liang static __initconst const u64 tnt_hw_cache_extra_regs 20366daeb873SKan Liang [PERF_COUNT_HW_CACHE_MAX] 20376daeb873SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 20386daeb873SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 20396daeb873SKan Liang [C(LL)] = { 20406daeb873SKan Liang [C(OP_READ)] = { 20416daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 20426daeb873SKan Liang TNT_LLC_ACCESS, 20436daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_READ| 20446daeb873SKan Liang TNT_LLC_MISS, 20456daeb873SKan Liang }, 20466daeb873SKan Liang [C(OP_WRITE)] = { 20476daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 20486daeb873SKan Liang TNT_LLC_ACCESS, 20496daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 20506daeb873SKan Liang TNT_LLC_MISS, 20516daeb873SKan Liang }, 20526daeb873SKan Liang [C(OP_PREFETCH)] = { 20536daeb873SKan Liang [C(RESULT_ACCESS)] = 0x0, 20546daeb873SKan Liang [C(RESULT_MISS)] = 0x0, 20556daeb873SKan Liang }, 20566daeb873SKan Liang }, 20576daeb873SKan Liang }; 20586daeb873SKan Liang 2059c2208046SKan Liang EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2060c2208046SKan Liang EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2061c2208046SKan Liang EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2062c2208046SKan Liang EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2063c2208046SKan Liang 2064c2208046SKan Liang static struct attribute *tnt_events_attrs[] = { 2065c2208046SKan Liang EVENT_PTR(td_fe_bound_tnt), 2066c2208046SKan Liang EVENT_PTR(td_retiring_tnt), 2067c2208046SKan Liang EVENT_PTR(td_bad_spec_tnt), 2068c2208046SKan Liang EVENT_PTR(td_be_bound_tnt), 2069c2208046SKan Liang NULL, 2070c2208046SKan Liang }; 2071c2208046SKan Liang 20726daeb873SKan Liang static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 20736daeb873SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 20740813c405SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 20750813c405SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 20766daeb873SKan Liang EVENT_EXTRA_END 20776daeb873SKan Liang }; 20786daeb873SKan Liang 2079e1069839SBorislav Petkov #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2080e1069839SBorislav Petkov #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2081e1069839SBorislav Petkov #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2082e1069839SBorislav Petkov #define KNL_MCDRAM_FAR BIT_ULL(22) 2083e1069839SBorislav Petkov #define KNL_DDR_LOCAL BIT_ULL(23) 2084e1069839SBorislav Petkov #define KNL_DDR_FAR BIT_ULL(24) 2085e1069839SBorislav Petkov #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2086e1069839SBorislav Petkov KNL_DDR_LOCAL | KNL_DDR_FAR) 2087e1069839SBorislav Petkov #define KNL_L2_READ SLM_DMND_READ 2088e1069839SBorislav Petkov #define KNL_L2_WRITE SLM_DMND_WRITE 2089e1069839SBorislav Petkov #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2090e1069839SBorislav Petkov #define KNL_L2_ACCESS SLM_LLC_ACCESS 2091e1069839SBorislav Petkov #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2092e1069839SBorislav Petkov KNL_DRAM_ANY | SNB_SNP_ANY | \ 2093e1069839SBorislav Petkov SNB_NON_DRAM) 2094e1069839SBorislav Petkov 2095e1069839SBorislav Petkov static __initconst const u64 knl_hw_cache_extra_regs 2096e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 2097e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 2098e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2099e1069839SBorislav Petkov [C(LL)] = { 2100e1069839SBorislav Petkov [C(OP_READ)] = { 2101e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2102e1069839SBorislav Petkov [C(RESULT_MISS)] = 0, 2103e1069839SBorislav Petkov }, 2104e1069839SBorislav Petkov [C(OP_WRITE)] = { 2105e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2106e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2107e1069839SBorislav Petkov }, 2108e1069839SBorislav Petkov [C(OP_PREFETCH)] = { 2109e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2110e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2111e1069839SBorislav Petkov }, 2112e1069839SBorislav Petkov }, 2113e1069839SBorislav Petkov }; 2114e1069839SBorislav Petkov 2115e1069839SBorislav Petkov /* 2116c3d266c8SKan Liang * Used from PMIs where the LBRs are already disabled. 2117c3d266c8SKan Liang * 2118c3d266c8SKan Liang * This function could be called consecutively. It is required to remain in 2119c3d266c8SKan Liang * disabled state if called consecutively. 2120c3d266c8SKan Liang * 2121c3d266c8SKan Liang * During consecutive calls, the same disable value will be written to related 2122cecf6235SAlexander Shishkin * registers, so the PMU state remains unchanged. 2123cecf6235SAlexander Shishkin * 2124cecf6235SAlexander Shishkin * intel_bts events don't coexist with intel PMU's BTS events because of 2125cecf6235SAlexander Shishkin * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2126cecf6235SAlexander Shishkin * disabled around intel PMU's event batching etc, only inside the PMI handler. 21276c1c07b3SKan Liang * 21286c1c07b3SKan Liang * Avoid PEBS_ENABLE MSR access in PMIs. 21296c1c07b3SKan Liang * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 21306c1c07b3SKan Liang * It doesn't matter if the PEBS is enabled or not. 21316c1c07b3SKan Liang * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 21326c1c07b3SKan Liang * access PEBS_ENABLE MSR in disable_all()/enable_all(). 21336c1c07b3SKan Liang * However, there are some cases which may change PEBS status, e.g. PMI 21346c1c07b3SKan Liang * throttle. The PEBS_ENABLE should be updated where the status changes. 2135e1069839SBorislav Petkov */ 2136e1069839SBorislav Petkov static void __intel_pmu_disable_all(void) 2137e1069839SBorislav Petkov { 2138e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2139e1069839SBorislav Petkov 2140e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2141e1069839SBorislav Petkov 2142e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2143e1069839SBorislav Petkov intel_pmu_disable_bts(); 2144e1069839SBorislav Petkov } 2145e1069839SBorislav Petkov 2146e1069839SBorislav Petkov static void intel_pmu_disable_all(void) 2147e1069839SBorislav Petkov { 2148e1069839SBorislav Petkov __intel_pmu_disable_all(); 21496c1c07b3SKan Liang intel_pmu_pebs_disable_all(); 2150e1069839SBorislav Petkov intel_pmu_lbr_disable_all(); 2151e1069839SBorislav Petkov } 2152e1069839SBorislav Petkov 2153e1069839SBorislav Petkov static void __intel_pmu_enable_all(int added, bool pmi) 2154e1069839SBorislav Petkov { 2155e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2156e1069839SBorislav Petkov 2157e1069839SBorislav Petkov intel_pmu_lbr_enable_all(pmi); 2158e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2159e1069839SBorislav Petkov x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2160e1069839SBorislav Petkov 2161e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2162e1069839SBorislav Petkov struct perf_event *event = 2163e1069839SBorislav Petkov cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2164e1069839SBorislav Petkov 2165e1069839SBorislav Petkov if (WARN_ON_ONCE(!event)) 2166e1069839SBorislav Petkov return; 2167e1069839SBorislav Petkov 2168e1069839SBorislav Petkov intel_pmu_enable_bts(event->hw.config); 2169cecf6235SAlexander Shishkin } 2170e1069839SBorislav Petkov } 2171e1069839SBorislav Petkov 2172e1069839SBorislav Petkov static void intel_pmu_enable_all(int added) 2173e1069839SBorislav Petkov { 21746c1c07b3SKan Liang intel_pmu_pebs_enable_all(); 2175e1069839SBorislav Petkov __intel_pmu_enable_all(added, false); 2176e1069839SBorislav Petkov } 2177e1069839SBorislav Petkov 2178e1069839SBorislav Petkov /* 2179e1069839SBorislav Petkov * Workaround for: 2180e1069839SBorislav Petkov * Intel Errata AAK100 (model 26) 2181e1069839SBorislav Petkov * Intel Errata AAP53 (model 30) 2182e1069839SBorislav Petkov * Intel Errata BD53 (model 44) 2183e1069839SBorislav Petkov * 2184e1069839SBorislav Petkov * The official story: 2185e1069839SBorislav Petkov * These chips need to be 'reset' when adding counters by programming the 2186e1069839SBorislav Petkov * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2187e1069839SBorislav Petkov * in sequence on the same PMC or on different PMCs. 2188e1069839SBorislav Petkov * 2189e1069839SBorislav Petkov * In practise it appears some of these events do in fact count, and 2190a97673a1SIngo Molnar * we need to program all 4 events. 2191e1069839SBorislav Petkov */ 2192e1069839SBorislav Petkov static void intel_pmu_nhm_workaround(void) 2193e1069839SBorislav Petkov { 2194e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2195e1069839SBorislav Petkov static const unsigned long nhm_magic[4] = { 2196e1069839SBorislav Petkov 0x4300B5, 2197e1069839SBorislav Petkov 0x4300D2, 2198e1069839SBorislav Petkov 0x4300B1, 2199e1069839SBorislav Petkov 0x4300B1 2200e1069839SBorislav Petkov }; 2201e1069839SBorislav Petkov struct perf_event *event; 2202e1069839SBorislav Petkov int i; 2203e1069839SBorislav Petkov 2204e1069839SBorislav Petkov /* 2205e1069839SBorislav Petkov * The Errata requires below steps: 2206e1069839SBorislav Petkov * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2207e1069839SBorislav Petkov * 2) Configure 4 PERFEVTSELx with the magic events and clear 2208e1069839SBorislav Petkov * the corresponding PMCx; 2209e1069839SBorislav Petkov * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2210e1069839SBorislav Petkov * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2211e1069839SBorislav Petkov * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2212e1069839SBorislav Petkov */ 2213e1069839SBorislav Petkov 2214e1069839SBorislav Petkov /* 2215e1069839SBorislav Petkov * The real steps we choose are a little different from above. 2216e1069839SBorislav Petkov * A) To reduce MSR operations, we don't run step 1) as they 2217e1069839SBorislav Petkov * are already cleared before this function is called; 2218e1069839SBorislav Petkov * B) Call x86_perf_event_update to save PMCx before configuring 2219e1069839SBorislav Petkov * PERFEVTSELx with magic number; 2220e1069839SBorislav Petkov * C) With step 5), we do clear only when the PERFEVTSELx is 2221e1069839SBorislav Petkov * not used currently. 2222e1069839SBorislav Petkov * D) Call x86_perf_event_set_period to restore PMCx; 2223e1069839SBorislav Petkov */ 2224e1069839SBorislav Petkov 2225e1069839SBorislav Petkov /* We always operate 4 pairs of PERF Counters */ 2226e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2227e1069839SBorislav Petkov event = cpuc->events[i]; 2228e1069839SBorislav Petkov if (event) 2229e1069839SBorislav Petkov x86_perf_event_update(event); 2230e1069839SBorislav Petkov } 2231e1069839SBorislav Petkov 2232e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2233e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2234e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2235e1069839SBorislav Petkov } 2236e1069839SBorislav Petkov 2237e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2238e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2239e1069839SBorislav Petkov 2240e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2241e1069839SBorislav Petkov event = cpuc->events[i]; 2242e1069839SBorislav Petkov 2243e1069839SBorislav Petkov if (event) { 2244e1069839SBorislav Petkov x86_perf_event_set_period(event); 2245e1069839SBorislav Petkov __x86_pmu_enable_event(&event->hw, 2246e1069839SBorislav Petkov ARCH_PERFMON_EVENTSEL_ENABLE); 2247e1069839SBorislav Petkov } else 2248e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2249e1069839SBorislav Petkov } 2250e1069839SBorislav Petkov } 2251e1069839SBorislav Petkov 2252e1069839SBorislav Petkov static void intel_pmu_nhm_enable_all(int added) 2253e1069839SBorislav Petkov { 2254e1069839SBorislav Petkov if (added) 2255e1069839SBorislav Petkov intel_pmu_nhm_workaround(); 2256e1069839SBorislav Petkov intel_pmu_enable_all(added); 2257e1069839SBorislav Petkov } 2258e1069839SBorislav Petkov 2259400816f6SPeter Zijlstra (Intel) static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2260400816f6SPeter Zijlstra (Intel) { 2261400816f6SPeter Zijlstra (Intel) u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2262400816f6SPeter Zijlstra (Intel) 2263400816f6SPeter Zijlstra (Intel) if (cpuc->tfa_shadow != val) { 2264400816f6SPeter Zijlstra (Intel) cpuc->tfa_shadow = val; 2265400816f6SPeter Zijlstra (Intel) wrmsrl(MSR_TSX_FORCE_ABORT, val); 2266400816f6SPeter Zijlstra (Intel) } 2267400816f6SPeter Zijlstra (Intel) } 2268400816f6SPeter Zijlstra (Intel) 2269400816f6SPeter Zijlstra (Intel) static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2270400816f6SPeter Zijlstra (Intel) { 2271400816f6SPeter Zijlstra (Intel) /* 2272400816f6SPeter Zijlstra (Intel) * We're going to use PMC3, make sure TFA is set before we touch it. 2273400816f6SPeter Zijlstra (Intel) */ 22741a81542aSPeter Zijlstra if (cntr == 3) 2275400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, true); 2276400816f6SPeter Zijlstra (Intel) } 2277400816f6SPeter Zijlstra (Intel) 2278400816f6SPeter Zijlstra (Intel) static void intel_tfa_pmu_enable_all(int added) 2279400816f6SPeter Zijlstra (Intel) { 2280400816f6SPeter Zijlstra (Intel) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2281400816f6SPeter Zijlstra (Intel) 2282400816f6SPeter Zijlstra (Intel) /* 2283400816f6SPeter Zijlstra (Intel) * If we find PMC3 is no longer used when we enable the PMU, we can 2284400816f6SPeter Zijlstra (Intel) * clear TFA. 2285400816f6SPeter Zijlstra (Intel) */ 2286400816f6SPeter Zijlstra (Intel) if (!test_bit(3, cpuc->active_mask)) 2287400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, false); 2288400816f6SPeter Zijlstra (Intel) 2289400816f6SPeter Zijlstra (Intel) intel_pmu_enable_all(added); 2290400816f6SPeter Zijlstra (Intel) } 2291400816f6SPeter Zijlstra (Intel) 2292e1069839SBorislav Petkov static inline u64 intel_pmu_get_status(void) 2293e1069839SBorislav Petkov { 2294e1069839SBorislav Petkov u64 status; 2295e1069839SBorislav Petkov 2296e1069839SBorislav Petkov rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2297e1069839SBorislav Petkov 2298e1069839SBorislav Petkov return status; 2299e1069839SBorislav Petkov } 2300e1069839SBorislav Petkov 2301e1069839SBorislav Petkov static inline void intel_pmu_ack_status(u64 ack) 2302e1069839SBorislav Petkov { 2303e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2304e1069839SBorislav Petkov } 2305e1069839SBorislav Petkov 2306027440b5SLike Xu static inline bool event_is_checkpointed(struct perf_event *event) 2307e1069839SBorislav Petkov { 2308027440b5SLike Xu return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2309027440b5SLike Xu } 2310027440b5SLike Xu 2311027440b5SLike Xu static inline void intel_set_masks(struct perf_event *event, int idx) 2312027440b5SLike Xu { 2313027440b5SLike Xu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2314027440b5SLike Xu 2315027440b5SLike Xu if (event->attr.exclude_host) 2316027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2317027440b5SLike Xu if (event->attr.exclude_guest) 2318027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2319027440b5SLike Xu if (event_is_checkpointed(event)) 2320027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2321027440b5SLike Xu } 2322027440b5SLike Xu 2323027440b5SLike Xu static inline void intel_clear_masks(struct perf_event *event, int idx) 2324027440b5SLike Xu { 2325027440b5SLike Xu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2326027440b5SLike Xu 2327027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2328027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2329027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2330027440b5SLike Xu } 2331027440b5SLike Xu 2332027440b5SLike Xu static void intel_pmu_disable_fixed(struct perf_event *event) 2333027440b5SLike Xu { 2334027440b5SLike Xu struct hw_perf_event *hwc = &event->hw; 2335e1069839SBorislav Petkov u64 ctrl_val, mask; 23367b2c05a1SKan Liang int idx = hwc->idx; 2337e1069839SBorislav Petkov 23387b2c05a1SKan Liang if (is_topdown_idx(idx)) { 23397b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2340e1069839SBorislav Petkov 23417b2c05a1SKan Liang /* 23427b2c05a1SKan Liang * When there are other active TopDown events, 23437b2c05a1SKan Liang * don't disable the fixed counter 3. 23447b2c05a1SKan Liang */ 23457b2c05a1SKan Liang if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 23467b2c05a1SKan Liang return; 23477b2c05a1SKan Liang idx = INTEL_PMC_IDX_FIXED_SLOTS; 23487b2c05a1SKan Liang } 23497b2c05a1SKan Liang 23507b2c05a1SKan Liang intel_clear_masks(event, idx); 23517b2c05a1SKan Liang 23527b2c05a1SKan Liang mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2353e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2354e1069839SBorislav Petkov ctrl_val &= ~mask; 2355e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2356e1069839SBorislav Petkov } 2357e1069839SBorislav Petkov 2358e1069839SBorislav Petkov static void intel_pmu_disable_event(struct perf_event *event) 2359e1069839SBorislav Petkov { 2360e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2361027440b5SLike Xu int idx = hwc->idx; 2362e1069839SBorislav Petkov 236358da7dbeSKan Liang switch (idx) { 236458da7dbeSKan Liang case 0 ... INTEL_PMC_IDX_FIXED - 1: 2365027440b5SLike Xu intel_clear_masks(event, idx); 2366027440b5SLike Xu x86_pmu_disable_event(event); 236758da7dbeSKan Liang break; 236858da7dbeSKan Liang case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 23697b2c05a1SKan Liang case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2370027440b5SLike Xu intel_pmu_disable_fixed(event); 237158da7dbeSKan Liang break; 237258da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_BTS: 2373e1069839SBorislav Petkov intel_pmu_disable_bts(); 2374e1069839SBorislav Petkov intel_pmu_drain_bts_buffer(); 237558da7dbeSKan Liang return; 237658da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_VLBR: 2377e1ad1ac2SLike Xu intel_clear_masks(event, idx); 237858da7dbeSKan Liang break; 237958da7dbeSKan Liang default: 238058da7dbeSKan Liang intel_clear_masks(event, idx); 238158da7dbeSKan Liang pr_warn("Failed to disable the event with invalid index %d\n", 238258da7dbeSKan Liang idx); 238358da7dbeSKan Liang return; 238458da7dbeSKan Liang } 2385e1069839SBorislav Petkov 23866f55967aSJiri Olsa /* 23876f55967aSJiri Olsa * Needs to be called after x86_pmu_disable_event, 23886f55967aSJiri Olsa * so we don't trigger the event without PEBS bit set. 23896f55967aSJiri Olsa */ 23906f55967aSJiri Olsa if (unlikely(event->attr.precise_ip)) 23916f55967aSJiri Olsa intel_pmu_pebs_disable(event); 2392e1069839SBorislav Petkov } 2393e1069839SBorislav Petkov 239468f7082fSPeter Zijlstra static void intel_pmu_del_event(struct perf_event *event) 239568f7082fSPeter Zijlstra { 239668f7082fSPeter Zijlstra if (needs_branch_stack(event)) 239768f7082fSPeter Zijlstra intel_pmu_lbr_del(event); 239868f7082fSPeter Zijlstra if (event->attr.precise_ip) 239968f7082fSPeter Zijlstra intel_pmu_pebs_del(event); 240068f7082fSPeter Zijlstra } 240168f7082fSPeter Zijlstra 240259a854e2SKan Liang static int icl_set_topdown_event_period(struct perf_event *event) 240359a854e2SKan Liang { 240459a854e2SKan Liang struct hw_perf_event *hwc = &event->hw; 240559a854e2SKan Liang s64 left = local64_read(&hwc->period_left); 240659a854e2SKan Liang 240759a854e2SKan Liang /* 240859a854e2SKan Liang * The values in PERF_METRICS MSR are derived from fixed counter 3. 240959a854e2SKan Liang * Software should start both registers, PERF_METRICS and fixed 241059a854e2SKan Liang * counter 3, from zero. 241159a854e2SKan Liang * Clear PERF_METRICS and Fixed counter 3 in initialization. 241259a854e2SKan Liang * After that, both MSRs will be cleared for each read. 241359a854e2SKan Liang * Don't need to clear them again. 241459a854e2SKan Liang */ 241559a854e2SKan Liang if (left == x86_pmu.max_period) { 241659a854e2SKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 241759a854e2SKan Liang wrmsrl(MSR_PERF_METRICS, 0); 24182cb5383bSKan Liang hwc->saved_slots = 0; 24192cb5383bSKan Liang hwc->saved_metric = 0; 24202cb5383bSKan Liang } 24212cb5383bSKan Liang 24222cb5383bSKan Liang if ((hwc->saved_slots) && is_slots_event(event)) { 24232cb5383bSKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 24242cb5383bSKan Liang wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 242559a854e2SKan Liang } 242659a854e2SKan Liang 242759a854e2SKan Liang perf_event_update_userpage(event); 242859a854e2SKan Liang 242959a854e2SKan Liang return 0; 243059a854e2SKan Liang } 243159a854e2SKan Liang 243259a854e2SKan Liang static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 243359a854e2SKan Liang { 243459a854e2SKan Liang u32 val; 243559a854e2SKan Liang 243659a854e2SKan Liang /* 243759a854e2SKan Liang * The metric is reported as an 8bit integer fraction 243859a854e2SKan Liang * suming up to 0xff. 243959a854e2SKan Liang * slots-in-metric = (Metric / 0xff) * slots 244059a854e2SKan Liang */ 244159a854e2SKan Liang val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 244259a854e2SKan Liang return mul_u64_u32_div(slots, val, 0xff); 244359a854e2SKan Liang } 244459a854e2SKan Liang 24452cb5383bSKan Liang static u64 icl_get_topdown_value(struct perf_event *event, 244659a854e2SKan Liang u64 slots, u64 metrics) 244759a854e2SKan Liang { 244859a854e2SKan Liang int idx = event->hw.idx; 244959a854e2SKan Liang u64 delta; 245059a854e2SKan Liang 245159a854e2SKan Liang if (is_metric_idx(idx)) 245259a854e2SKan Liang delta = icl_get_metrics_event_value(metrics, slots, idx); 245359a854e2SKan Liang else 245459a854e2SKan Liang delta = slots; 245559a854e2SKan Liang 24562cb5383bSKan Liang return delta; 24572cb5383bSKan Liang } 24582cb5383bSKan Liang 24592cb5383bSKan Liang static void __icl_update_topdown_event(struct perf_event *event, 24602cb5383bSKan Liang u64 slots, u64 metrics, 24612cb5383bSKan Liang u64 last_slots, u64 last_metrics) 24622cb5383bSKan Liang { 24632cb5383bSKan Liang u64 delta, last = 0; 24642cb5383bSKan Liang 24652cb5383bSKan Liang delta = icl_get_topdown_value(event, slots, metrics); 24662cb5383bSKan Liang if (last_slots) 24672cb5383bSKan Liang last = icl_get_topdown_value(event, last_slots, last_metrics); 24682cb5383bSKan Liang 24692cb5383bSKan Liang /* 24702cb5383bSKan Liang * The 8bit integer fraction of metric may be not accurate, 24712cb5383bSKan Liang * especially when the changes is very small. 24722cb5383bSKan Liang * For example, if only a few bad_spec happens, the fraction 24732cb5383bSKan Liang * may be reduced from 1 to 0. If so, the bad_spec event value 24742cb5383bSKan Liang * will be 0 which is definitely less than the last value. 24752cb5383bSKan Liang * Avoid update event->count for this case. 24762cb5383bSKan Liang */ 24772cb5383bSKan Liang if (delta > last) { 24782cb5383bSKan Liang delta -= last; 247959a854e2SKan Liang local64_add(delta, &event->count); 248059a854e2SKan Liang } 24812cb5383bSKan Liang } 24822cb5383bSKan Liang 2483628d923aSKan Liang static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2484628d923aSKan Liang u64 metrics, int metric_end) 24852cb5383bSKan Liang { 24862cb5383bSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 24872cb5383bSKan Liang struct perf_event *other; 24882cb5383bSKan Liang int idx; 24892cb5383bSKan Liang 24902cb5383bSKan Liang event->hw.saved_slots = slots; 24912cb5383bSKan Liang event->hw.saved_metric = metrics; 24922cb5383bSKan Liang 2493628d923aSKan Liang for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 24942cb5383bSKan Liang if (!is_topdown_idx(idx)) 24952cb5383bSKan Liang continue; 24962cb5383bSKan Liang other = cpuc->events[idx]; 24972cb5383bSKan Liang other->hw.saved_slots = slots; 24982cb5383bSKan Liang other->hw.saved_metric = metrics; 24992cb5383bSKan Liang } 25002cb5383bSKan Liang } 250159a854e2SKan Liang 250259a854e2SKan Liang /* 250359a854e2SKan Liang * Update all active Topdown events. 250459a854e2SKan Liang * 250559a854e2SKan Liang * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 250659a854e2SKan Liang * modify by a NMI. PMU has to be disabled before calling this function. 250759a854e2SKan Liang */ 2508628d923aSKan Liang 2509628d923aSKan Liang static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) 251059a854e2SKan Liang { 251159a854e2SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 251259a854e2SKan Liang struct perf_event *other; 251359a854e2SKan Liang u64 slots, metrics; 25142cb5383bSKan Liang bool reset = true; 251559a854e2SKan Liang int idx; 251659a854e2SKan Liang 251759a854e2SKan Liang /* read Fixed counter 3 */ 251859a854e2SKan Liang rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 251959a854e2SKan Liang if (!slots) 252059a854e2SKan Liang return 0; 252159a854e2SKan Liang 252259a854e2SKan Liang /* read PERF_METRICS */ 252359a854e2SKan Liang rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 252459a854e2SKan Liang 2525628d923aSKan Liang for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 252659a854e2SKan Liang if (!is_topdown_idx(idx)) 252759a854e2SKan Liang continue; 252859a854e2SKan Liang other = cpuc->events[idx]; 25292cb5383bSKan Liang __icl_update_topdown_event(other, slots, metrics, 25302cb5383bSKan Liang event ? event->hw.saved_slots : 0, 25312cb5383bSKan Liang event ? event->hw.saved_metric : 0); 253259a854e2SKan Liang } 253359a854e2SKan Liang 253459a854e2SKan Liang /* 253559a854e2SKan Liang * Check and update this event, which may have been cleared 253659a854e2SKan Liang * in active_mask e.g. x86_pmu_stop() 253759a854e2SKan Liang */ 25382cb5383bSKan Liang if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 25392cb5383bSKan Liang __icl_update_topdown_event(event, slots, metrics, 25402cb5383bSKan Liang event->hw.saved_slots, 25412cb5383bSKan Liang event->hw.saved_metric); 254259a854e2SKan Liang 25432cb5383bSKan Liang /* 25442cb5383bSKan Liang * In x86_pmu_stop(), the event is cleared in active_mask first, 25452cb5383bSKan Liang * then drain the delta, which indicates context switch for 25462cb5383bSKan Liang * counting. 25472cb5383bSKan Liang * Save metric and slots for context switch. 25482cb5383bSKan Liang * Don't need to reset the PERF_METRICS and Fixed counter 3. 25492cb5383bSKan Liang * Because the values will be restored in next schedule in. 25502cb5383bSKan Liang */ 2551628d923aSKan Liang update_saved_topdown_regs(event, slots, metrics, metric_end); 25522cb5383bSKan Liang reset = false; 25532cb5383bSKan Liang } 25542cb5383bSKan Liang 25552cb5383bSKan Liang if (reset) { 255659a854e2SKan Liang /* The fixed counter 3 has to be written before the PERF_METRICS. */ 255759a854e2SKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 255859a854e2SKan Liang wrmsrl(MSR_PERF_METRICS, 0); 25592cb5383bSKan Liang if (event) 2560628d923aSKan Liang update_saved_topdown_regs(event, 0, 0, metric_end); 25612cb5383bSKan Liang } 256259a854e2SKan Liang 256359a854e2SKan Liang return slots; 256459a854e2SKan Liang } 256559a854e2SKan Liang 2566628d923aSKan Liang static u64 icl_update_topdown_event(struct perf_event *event) 2567628d923aSKan Liang { 25681ab5f235SKan Liang return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 25691ab5f235SKan Liang x86_pmu.num_topdown_events - 1); 2570628d923aSKan Liang } 2571628d923aSKan Liang 25727b2c05a1SKan Liang static void intel_pmu_read_topdown_event(struct perf_event *event) 25737b2c05a1SKan Liang { 25747b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 25757b2c05a1SKan Liang 25767b2c05a1SKan Liang /* Only need to call update_topdown_event() once for group read. */ 25777b2c05a1SKan Liang if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 25787b2c05a1SKan Liang !is_slots_event(event)) 25797b2c05a1SKan Liang return; 25807b2c05a1SKan Liang 25817b2c05a1SKan Liang perf_pmu_disable(event->pmu); 25827b2c05a1SKan Liang x86_pmu.update_topdown_event(event); 25837b2c05a1SKan Liang perf_pmu_enable(event->pmu); 25847b2c05a1SKan Liang } 25857b2c05a1SKan Liang 2586ceb90d9eSKan Liang static void intel_pmu_read_event(struct perf_event *event) 2587ceb90d9eSKan Liang { 2588ceb90d9eSKan Liang if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2589ceb90d9eSKan Liang intel_pmu_auto_reload_read(event); 25907b2c05a1SKan Liang else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 25917b2c05a1SKan Liang intel_pmu_read_topdown_event(event); 2592ceb90d9eSKan Liang else 2593ceb90d9eSKan Liang x86_perf_event_update(event); 2594ceb90d9eSKan Liang } 2595ceb90d9eSKan Liang 25964f08b625SKan Liang static void intel_pmu_enable_fixed(struct perf_event *event) 2597e1069839SBorislav Petkov { 25984f08b625SKan Liang struct hw_perf_event *hwc = &event->hw; 25994f08b625SKan Liang u64 ctrl_val, mask, bits = 0; 26007b2c05a1SKan Liang int idx = hwc->idx; 26017b2c05a1SKan Liang 26027b2c05a1SKan Liang if (is_topdown_idx(idx)) { 26037b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 26047b2c05a1SKan Liang /* 26057b2c05a1SKan Liang * When there are other active TopDown events, 26067b2c05a1SKan Liang * don't enable the fixed counter 3 again. 26077b2c05a1SKan Liang */ 26087b2c05a1SKan Liang if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 26097b2c05a1SKan Liang return; 26107b2c05a1SKan Liang 26117b2c05a1SKan Liang idx = INTEL_PMC_IDX_FIXED_SLOTS; 26127b2c05a1SKan Liang } 26137b2c05a1SKan Liang 26147b2c05a1SKan Liang intel_set_masks(event, idx); 2615e1069839SBorislav Petkov 2616e1069839SBorislav Petkov /* 26174f08b625SKan Liang * Enable IRQ generation (0x8), if not PEBS, 2618e1069839SBorislav Petkov * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2619e1069839SBorislav Petkov * if requested: 2620e1069839SBorislav Petkov */ 26214f08b625SKan Liang if (!event->attr.precise_ip) 26224f08b625SKan Liang bits |= 0x8; 2623e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2624e1069839SBorislav Petkov bits |= 0x2; 2625e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2626e1069839SBorislav Petkov bits |= 0x1; 2627e1069839SBorislav Petkov 2628e1069839SBorislav Petkov /* 2629e1069839SBorislav Petkov * ANY bit is supported in v3 and up 2630e1069839SBorislav Petkov */ 2631e1069839SBorislav Petkov if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2632e1069839SBorislav Petkov bits |= 0x4; 2633e1069839SBorislav Petkov 26347b2c05a1SKan Liang idx -= INTEL_PMC_IDX_FIXED; 2635e1069839SBorislav Petkov bits <<= (idx * 4); 2636e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2637e1069839SBorislav Petkov 2638c22497f5SKan Liang if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2639c22497f5SKan Liang bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2640c22497f5SKan Liang mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2641c22497f5SKan Liang } 2642c22497f5SKan Liang 2643e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2644e1069839SBorislav Petkov ctrl_val &= ~mask; 2645e1069839SBorislav Petkov ctrl_val |= bits; 2646e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2647e1069839SBorislav Petkov } 2648e1069839SBorislav Petkov 2649e1069839SBorislav Petkov static void intel_pmu_enable_event(struct perf_event *event) 2650e1069839SBorislav Petkov { 2651e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2652027440b5SLike Xu int idx = hwc->idx; 2653e1069839SBorislav Petkov 2654e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2655e1069839SBorislav Petkov intel_pmu_pebs_enable(event); 2656e1069839SBorislav Petkov 265758da7dbeSKan Liang switch (idx) { 265858da7dbeSKan Liang case 0 ... INTEL_PMC_IDX_FIXED - 1: 2659027440b5SLike Xu intel_set_masks(event, idx); 2660e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 266158da7dbeSKan Liang break; 266258da7dbeSKan Liang case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 26637b2c05a1SKan Liang case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2664027440b5SLike Xu intel_pmu_enable_fixed(event); 266558da7dbeSKan Liang break; 266658da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_BTS: 2667027440b5SLike Xu if (!__this_cpu_read(cpu_hw_events.enabled)) 2668027440b5SLike Xu return; 2669027440b5SLike Xu intel_pmu_enable_bts(hwc->config); 267058da7dbeSKan Liang break; 267158da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_VLBR: 2672e1ad1ac2SLike Xu intel_set_masks(event, idx); 267358da7dbeSKan Liang break; 267458da7dbeSKan Liang default: 267558da7dbeSKan Liang pr_warn("Failed to enable the event with invalid index %d\n", 267658da7dbeSKan Liang idx); 267758da7dbeSKan Liang } 2678e1069839SBorislav Petkov } 2679e1069839SBorislav Petkov 268068f7082fSPeter Zijlstra static void intel_pmu_add_event(struct perf_event *event) 268168f7082fSPeter Zijlstra { 268268f7082fSPeter Zijlstra if (event->attr.precise_ip) 268368f7082fSPeter Zijlstra intel_pmu_pebs_add(event); 268468f7082fSPeter Zijlstra if (needs_branch_stack(event)) 268568f7082fSPeter Zijlstra intel_pmu_lbr_add(event); 268668f7082fSPeter Zijlstra } 268768f7082fSPeter Zijlstra 2688e1069839SBorislav Petkov /* 2689e1069839SBorislav Petkov * Save and restart an expired event. Called by NMI contexts, 2690e1069839SBorislav Petkov * so it has to be careful about preempting normal event ops: 2691e1069839SBorislav Petkov */ 2692e1069839SBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event) 2693e1069839SBorislav Petkov { 2694e1069839SBorislav Petkov x86_perf_event_update(event); 2695e1069839SBorislav Petkov /* 2696e1069839SBorislav Petkov * For a checkpointed counter always reset back to 0. This 2697e1069839SBorislav Petkov * avoids a situation where the counter overflows, aborts the 2698e1069839SBorislav Petkov * transaction and is then set back to shortly before the 2699e1069839SBorislav Petkov * overflow, and overflows and aborts again. 2700e1069839SBorislav Petkov */ 2701e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) { 2702e1069839SBorislav Petkov /* No race with NMIs because the counter should not be armed */ 2703e1069839SBorislav Petkov wrmsrl(event->hw.event_base, 0); 2704e1069839SBorislav Petkov local64_set(&event->hw.prev_count, 0); 2705e1069839SBorislav Petkov } 2706e1069839SBorislav Petkov return x86_perf_event_set_period(event); 2707e1069839SBorislav Petkov } 2708e1069839SBorislav Petkov 2709e1069839SBorislav Petkov static void intel_pmu_reset(void) 2710e1069839SBorislav Petkov { 2711e1069839SBorislav Petkov struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2712e1069839SBorislav Petkov unsigned long flags; 2713e1069839SBorislav Petkov int idx; 2714e1069839SBorislav Petkov 2715e1069839SBorislav Petkov if (!x86_pmu.num_counters) 2716e1069839SBorislav Petkov return; 2717e1069839SBorislav Petkov 2718e1069839SBorislav Petkov local_irq_save(flags); 2719e1069839SBorislav Petkov 2720e1069839SBorislav Petkov pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2721e1069839SBorislav Petkov 2722e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2723e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2724e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2725e1069839SBorislav Petkov } 2726e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2727e1069839SBorislav Petkov wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2728e1069839SBorislav Petkov 2729e1069839SBorislav Petkov if (ds) 2730e1069839SBorislav Petkov ds->bts_index = ds->bts_buffer_base; 2731e1069839SBorislav Petkov 2732e1069839SBorislav Petkov /* Ack all overflows and disable fixed counters */ 2733e1069839SBorislav Petkov if (x86_pmu.version >= 2) { 2734e1069839SBorislav Petkov intel_pmu_ack_status(intel_pmu_get_status()); 2735e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2736e1069839SBorislav Petkov } 2737e1069839SBorislav Petkov 2738e1069839SBorislav Petkov /* Reset LBRs and LBR freezing */ 2739e1069839SBorislav Petkov if (x86_pmu.lbr_nr) { 2740e1069839SBorislav Petkov update_debugctlmsr(get_debugctlmsr() & 2741e1069839SBorislav Petkov ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2742e1069839SBorislav Petkov } 2743e1069839SBorislav Petkov 2744e1069839SBorislav Petkov local_irq_restore(flags); 2745e1069839SBorislav Petkov } 2746e1069839SBorislav Petkov 2747ba12d20eSKan Liang static int handle_pmi_common(struct pt_regs *regs, u64 status) 2748e1069839SBorislav Petkov { 2749e1069839SBorislav Petkov struct perf_sample_data data; 2750ba12d20eSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2751ba12d20eSKan Liang int bit; 2752ba12d20eSKan Liang int handled = 0; 2753e1069839SBorislav Petkov 2754e1069839SBorislav Petkov inc_irq_stat(apic_perf_irqs); 2755e1069839SBorislav Petkov 2756e1069839SBorislav Petkov /* 2757e1069839SBorislav Petkov * Ignore a range of extra bits in status that do not indicate 2758e1069839SBorislav Petkov * overflow by themselves. 2759e1069839SBorislav Petkov */ 2760e1069839SBorislav Petkov status &= ~(GLOBAL_STATUS_COND_CHG | 2761e1069839SBorislav Petkov GLOBAL_STATUS_ASIF | 2762e1069839SBorislav Petkov GLOBAL_STATUS_LBRS_FROZEN); 2763e1069839SBorislav Petkov if (!status) 2764ba12d20eSKan Liang return 0; 2765daa864b8SStephane Eranian /* 2766daa864b8SStephane Eranian * In case multiple PEBS events are sampled at the same time, 2767daa864b8SStephane Eranian * it is possible to have GLOBAL_STATUS bit 62 set indicating 2768daa864b8SStephane Eranian * PEBS buffer overflow and also seeing at most 3 PEBS counters 2769daa864b8SStephane Eranian * having their bits set in the status register. This is a sign 2770daa864b8SStephane Eranian * that there was at least one PEBS record pending at the time 2771daa864b8SStephane Eranian * of the PMU interrupt. PEBS counters must only be processed 2772daa864b8SStephane Eranian * via the drain_pebs() calls and not via the regular sample 2773daa864b8SStephane Eranian * processing loop coming after that the function, otherwise 2774daa864b8SStephane Eranian * phony regular samples may be generated in the sampling buffer 2775daa864b8SStephane Eranian * not marked with the EXACT tag. Another possibility is to have 2776daa864b8SStephane Eranian * one PEBS event and at least one non-PEBS event whic hoverflows 2777daa864b8SStephane Eranian * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2778daa864b8SStephane Eranian * not be set, yet the overflow status bit for the PEBS counter will 2779daa864b8SStephane Eranian * be on Skylake. 2780daa864b8SStephane Eranian * 2781daa864b8SStephane Eranian * To avoid this problem, we systematically ignore the PEBS-enabled 2782daa864b8SStephane Eranian * counters from the GLOBAL_STATUS mask and we always process PEBS 2783daa864b8SStephane Eranian * events via drain_pebs(). 2784daa864b8SStephane Eranian */ 2785ec71a398SKan Liang if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2786ec71a398SKan Liang status &= ~cpuc->pebs_enabled; 2787ec71a398SKan Liang else 2788fd583ad1SKan Liang status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2789e1069839SBorislav Petkov 2790e1069839SBorislav Petkov /* 2791e1069839SBorislav Petkov * PEBS overflow sets bit 62 in the global status register 2792e1069839SBorislav Petkov */ 279360a2a271SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 27946c1c07b3SKan Liang u64 pebs_enabled = cpuc->pebs_enabled; 27956c1c07b3SKan Liang 2796e1069839SBorislav Petkov handled++; 27979dfa9a5cSPeter Zijlstra x86_pmu.drain_pebs(regs, &data); 27988077eca0SStephane Eranian status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 27996c1c07b3SKan Liang 28006c1c07b3SKan Liang /* 28016c1c07b3SKan Liang * PMI throttle may be triggered, which stops the PEBS event. 28026c1c07b3SKan Liang * Although cpuc->pebs_enabled is updated accordingly, the 28036c1c07b3SKan Liang * MSR_IA32_PEBS_ENABLE is not updated. Because the 28046c1c07b3SKan Liang * cpuc->enabled has been forced to 0 in PMI. 28056c1c07b3SKan Liang * Update the MSR if pebs_enabled is changed. 28066c1c07b3SKan Liang */ 28076c1c07b3SKan Liang if (pebs_enabled != cpuc->pebs_enabled) 28086c1c07b3SKan Liang wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2809e1069839SBorislav Petkov } 2810e1069839SBorislav Petkov 2811e1069839SBorislav Petkov /* 2812e1069839SBorislav Petkov * Intel PT 2813e1069839SBorislav Petkov */ 281460a2a271SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2815e1069839SBorislav Petkov handled++; 28168479e04eSLuwei Kang if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 28178479e04eSLuwei Kang perf_guest_cbs->handle_intel_pt_intr)) 28188479e04eSLuwei Kang perf_guest_cbs->handle_intel_pt_intr(); 28198479e04eSLuwei Kang else 2820e1069839SBorislav Petkov intel_pt_interrupt(); 2821e1069839SBorislav Petkov } 2822e1069839SBorislav Petkov 2823e1069839SBorislav Petkov /* 28247b2c05a1SKan Liang * Intel Perf mertrics 28257b2c05a1SKan Liang */ 28267b2c05a1SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 28277b2c05a1SKan Liang handled++; 28287b2c05a1SKan Liang if (x86_pmu.update_topdown_event) 28297b2c05a1SKan Liang x86_pmu.update_topdown_event(NULL); 28307b2c05a1SKan Liang } 28317b2c05a1SKan Liang 28327b2c05a1SKan Liang /* 2833e1069839SBorislav Petkov * Checkpointed counters can lead to 'spurious' PMIs because the 2834e1069839SBorislav Petkov * rollback caused by the PMI will have cleared the overflow status 2835e1069839SBorislav Petkov * bit. Therefore always force probe these counters. 2836e1069839SBorislav Petkov */ 2837e1069839SBorislav Petkov status |= cpuc->intel_cp_status; 2838e1069839SBorislav Petkov 2839e1069839SBorislav Petkov for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2840e1069839SBorislav Petkov struct perf_event *event = cpuc->events[bit]; 2841e1069839SBorislav Petkov 2842e1069839SBorislav Petkov handled++; 2843e1069839SBorislav Petkov 2844e1069839SBorislav Petkov if (!test_bit(bit, cpuc->active_mask)) 2845e1069839SBorislav Petkov continue; 2846e1069839SBorislav Petkov 2847e1069839SBorislav Petkov if (!intel_pmu_save_and_restart(event)) 2848e1069839SBorislav Petkov continue; 2849e1069839SBorislav Petkov 2850e1069839SBorislav Petkov perf_sample_data_init(&data, 0, event->hw.last_period); 2851e1069839SBorislav Petkov 2852e1069839SBorislav Petkov if (has_branch_stack(event)) 2853e1069839SBorislav Petkov data.br_stack = &cpuc->lbr_stack; 2854e1069839SBorislav Petkov 2855e1069839SBorislav Petkov if (perf_event_overflow(event, &data, regs)) 2856e1069839SBorislav Petkov x86_pmu_stop(event, 0); 2857e1069839SBorislav Petkov } 2858e1069839SBorislav Petkov 2859ba12d20eSKan Liang return handled; 2860ba12d20eSKan Liang } 2861ba12d20eSKan Liang 2862ba12d20eSKan Liang /* 2863ba12d20eSKan Liang * This handler is triggered by the local APIC, so the APIC IRQ handling 2864ba12d20eSKan Liang * rules apply: 2865ba12d20eSKan Liang */ 2866ba12d20eSKan Liang static int intel_pmu_handle_irq(struct pt_regs *regs) 2867ba12d20eSKan Liang { 2868ba12d20eSKan Liang struct cpu_hw_events *cpuc; 2869ba12d20eSKan Liang int loops; 2870ba12d20eSKan Liang u64 status; 2871ba12d20eSKan Liang int handled; 2872ba12d20eSKan Liang int pmu_enabled; 2873ba12d20eSKan Liang 2874ba12d20eSKan Liang cpuc = this_cpu_ptr(&cpu_hw_events); 2875ba12d20eSKan Liang 2876ba12d20eSKan Liang /* 2877ba12d20eSKan Liang * Save the PMU state. 2878ba12d20eSKan Liang * It needs to be restored when leaving the handler. 2879ba12d20eSKan Liang */ 2880ba12d20eSKan Liang pmu_enabled = cpuc->enabled; 2881ba12d20eSKan Liang /* 2882ba12d20eSKan Liang * No known reason to not always do late ACK, 2883ba12d20eSKan Liang * but just in case do it opt-in. 2884ba12d20eSKan Liang */ 2885ba12d20eSKan Liang if (!x86_pmu.late_ack) 2886ba12d20eSKan Liang apic_write(APIC_LVTPC, APIC_DM_NMI); 2887ba12d20eSKan Liang intel_bts_disable_local(); 2888ba12d20eSKan Liang cpuc->enabled = 0; 2889ba12d20eSKan Liang __intel_pmu_disable_all(); 2890ba12d20eSKan Liang handled = intel_pmu_drain_bts_buffer(); 2891ba12d20eSKan Liang handled += intel_bts_interrupt(); 2892ba12d20eSKan Liang status = intel_pmu_get_status(); 2893ba12d20eSKan Liang if (!status) 2894ba12d20eSKan Liang goto done; 2895ba12d20eSKan Liang 2896ba12d20eSKan Liang loops = 0; 2897ba12d20eSKan Liang again: 2898ba12d20eSKan Liang intel_pmu_lbr_read(); 2899ba12d20eSKan Liang intel_pmu_ack_status(status); 2900ba12d20eSKan Liang if (++loops > 100) { 2901ba12d20eSKan Liang static bool warned; 2902ba12d20eSKan Liang 2903ba12d20eSKan Liang if (!warned) { 2904ba12d20eSKan Liang WARN(1, "perfevents: irq loop stuck!\n"); 2905ba12d20eSKan Liang perf_event_print_debug(); 2906ba12d20eSKan Liang warned = true; 2907ba12d20eSKan Liang } 2908ba12d20eSKan Liang intel_pmu_reset(); 2909ba12d20eSKan Liang goto done; 2910ba12d20eSKan Liang } 2911ba12d20eSKan Liang 2912ba12d20eSKan Liang handled += handle_pmi_common(regs, status); 2913ba12d20eSKan Liang 2914e1069839SBorislav Petkov /* 2915e1069839SBorislav Petkov * Repeat if there is more work to be done: 2916e1069839SBorislav Petkov */ 2917e1069839SBorislav Petkov status = intel_pmu_get_status(); 2918e1069839SBorislav Petkov if (status) 2919e1069839SBorislav Petkov goto again; 2920e1069839SBorislav Petkov 2921e1069839SBorislav Petkov done: 2922c3d266c8SKan Liang /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 292382d71ed0SKan Liang cpuc->enabled = pmu_enabled; 292482d71ed0SKan Liang if (pmu_enabled) 2925e1069839SBorislav Petkov __intel_pmu_enable_all(0, true); 2926cecf6235SAlexander Shishkin intel_bts_enable_local(); 2927c3d266c8SKan Liang 2928e1069839SBorislav Petkov /* 2929e1069839SBorislav Petkov * Only unmask the NMI after the overflow counters 2930e1069839SBorislav Petkov * have been reset. This avoids spurious NMIs on 2931e1069839SBorislav Petkov * Haswell CPUs. 2932e1069839SBorislav Petkov */ 2933e1069839SBorislav Petkov if (x86_pmu.late_ack) 2934e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 2935e1069839SBorislav Petkov return handled; 2936e1069839SBorislav Petkov } 2937e1069839SBorislav Petkov 2938e1069839SBorislav Petkov static struct event_constraint * 2939e1069839SBorislav Petkov intel_bts_constraints(struct perf_event *event) 2940e1069839SBorislav Petkov { 294167266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) 2942e1069839SBorislav Petkov return &bts_constraint; 2943e1069839SBorislav Petkov 2944e1069839SBorislav Petkov return NULL; 2945e1069839SBorislav Petkov } 2946e1069839SBorislav Petkov 2947097e4311SLike Xu /* 2948097e4311SLike Xu * Note: matches a fake event, like Fixed2. 2949097e4311SLike Xu */ 2950097e4311SLike Xu static struct event_constraint * 2951097e4311SLike Xu intel_vlbr_constraints(struct perf_event *event) 2952097e4311SLike Xu { 2953097e4311SLike Xu struct event_constraint *c = &vlbr_constraint; 2954097e4311SLike Xu 2955097e4311SLike Xu if (unlikely(constraint_match(c, event->hw.config))) 2956097e4311SLike Xu return c; 2957097e4311SLike Xu 2958097e4311SLike Xu return NULL; 2959097e4311SLike Xu } 2960097e4311SLike Xu 2961e1069839SBorislav Petkov static int intel_alt_er(int idx, u64 config) 2962e1069839SBorislav Petkov { 2963e1069839SBorislav Petkov int alt_idx = idx; 2964e1069839SBorislav Petkov 2965e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2966e1069839SBorislav Petkov return idx; 2967e1069839SBorislav Petkov 2968e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) 2969e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_1; 2970e1069839SBorislav Petkov 2971e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_1) 2972e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_0; 2973e1069839SBorislav Petkov 2974e1069839SBorislav Petkov if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2975e1069839SBorislav Petkov return idx; 2976e1069839SBorislav Petkov 2977e1069839SBorislav Petkov return alt_idx; 2978e1069839SBorislav Petkov } 2979e1069839SBorislav Petkov 2980e1069839SBorislav Petkov static void intel_fixup_er(struct perf_event *event, int idx) 2981e1069839SBorislav Petkov { 2982e1069839SBorislav Petkov event->hw.extra_reg.idx = idx; 2983e1069839SBorislav Petkov 2984e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) { 2985e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2986e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2987e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2988e1069839SBorislav Petkov } else if (idx == EXTRA_REG_RSP_1) { 2989e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2990e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2991e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2992e1069839SBorislav Petkov } 2993e1069839SBorislav Petkov } 2994e1069839SBorislav Petkov 2995e1069839SBorislav Petkov /* 2996e1069839SBorislav Petkov * manage allocation of shared extra msr for certain events 2997e1069839SBorislav Petkov * 2998e1069839SBorislav Petkov * sharing can be: 2999e1069839SBorislav Petkov * per-cpu: to be shared between the various events on a single PMU 3000e1069839SBorislav Petkov * per-core: per-cpu + shared by HT threads 3001e1069839SBorislav Petkov */ 3002e1069839SBorislav Petkov static struct event_constraint * 3003e1069839SBorislav Petkov __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3004e1069839SBorislav Petkov struct perf_event *event, 3005e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 3006e1069839SBorislav Petkov { 3007e1069839SBorislav Petkov struct event_constraint *c = &emptyconstraint; 3008e1069839SBorislav Petkov struct er_account *era; 3009e1069839SBorislav Petkov unsigned long flags; 3010e1069839SBorislav Petkov int idx = reg->idx; 3011e1069839SBorislav Petkov 3012e1069839SBorislav Petkov /* 3013e1069839SBorislav Petkov * reg->alloc can be set due to existing state, so for fake cpuc we 3014e1069839SBorislav Petkov * need to ignore this, otherwise we might fail to allocate proper fake 3015e1069839SBorislav Petkov * state for this extra reg constraint. Also see the comment below. 3016e1069839SBorislav Petkov */ 3017e1069839SBorislav Petkov if (reg->alloc && !cpuc->is_fake) 3018e1069839SBorislav Petkov return NULL; /* call x86_get_event_constraint() */ 3019e1069839SBorislav Petkov 3020e1069839SBorislav Petkov again: 3021e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[idx]; 3022e1069839SBorislav Petkov /* 3023e1069839SBorislav Petkov * we use spin_lock_irqsave() to avoid lockdep issues when 3024e1069839SBorislav Petkov * passing a fake cpuc 3025e1069839SBorislav Petkov */ 3026e1069839SBorislav Petkov raw_spin_lock_irqsave(&era->lock, flags); 3027e1069839SBorislav Petkov 3028e1069839SBorislav Petkov if (!atomic_read(&era->ref) || era->config == reg->config) { 3029e1069839SBorislav Petkov 3030e1069839SBorislav Petkov /* 3031e1069839SBorislav Petkov * If its a fake cpuc -- as per validate_{group,event}() we 3032e1069839SBorislav Petkov * shouldn't touch event state and we can avoid doing so 3033e1069839SBorislav Petkov * since both will only call get_event_constraints() once 3034e1069839SBorislav Petkov * on each event, this avoids the need for reg->alloc. 3035e1069839SBorislav Petkov * 3036e1069839SBorislav Petkov * Not doing the ER fixup will only result in era->reg being 3037e1069839SBorislav Petkov * wrong, but since we won't actually try and program hardware 3038e1069839SBorislav Petkov * this isn't a problem either. 3039e1069839SBorislav Petkov */ 3040e1069839SBorislav Petkov if (!cpuc->is_fake) { 3041e1069839SBorislav Petkov if (idx != reg->idx) 3042e1069839SBorislav Petkov intel_fixup_er(event, idx); 3043e1069839SBorislav Petkov 3044e1069839SBorislav Petkov /* 3045e1069839SBorislav Petkov * x86_schedule_events() can call get_event_constraints() 3046e1069839SBorislav Petkov * multiple times on events in the case of incremental 3047e1069839SBorislav Petkov * scheduling(). reg->alloc ensures we only do the ER 3048e1069839SBorislav Petkov * allocation once. 3049e1069839SBorislav Petkov */ 3050e1069839SBorislav Petkov reg->alloc = 1; 3051e1069839SBorislav Petkov } 3052e1069839SBorislav Petkov 3053e1069839SBorislav Petkov /* lock in msr value */ 3054e1069839SBorislav Petkov era->config = reg->config; 3055e1069839SBorislav Petkov era->reg = reg->reg; 3056e1069839SBorislav Petkov 3057e1069839SBorislav Petkov /* one more user */ 3058e1069839SBorislav Petkov atomic_inc(&era->ref); 3059e1069839SBorislav Petkov 3060e1069839SBorislav Petkov /* 3061e1069839SBorislav Petkov * need to call x86_get_event_constraint() 3062e1069839SBorislav Petkov * to check if associated event has constraints 3063e1069839SBorislav Petkov */ 3064e1069839SBorislav Petkov c = NULL; 3065e1069839SBorislav Petkov } else { 3066e1069839SBorislav Petkov idx = intel_alt_er(idx, reg->config); 3067e1069839SBorislav Petkov if (idx != reg->idx) { 3068e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 3069e1069839SBorislav Petkov goto again; 3070e1069839SBorislav Petkov } 3071e1069839SBorislav Petkov } 3072e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 3073e1069839SBorislav Petkov 3074e1069839SBorislav Petkov return c; 3075e1069839SBorislav Petkov } 3076e1069839SBorislav Petkov 3077e1069839SBorislav Petkov static void 3078e1069839SBorislav Petkov __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3079e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 3080e1069839SBorislav Petkov { 3081e1069839SBorislav Petkov struct er_account *era; 3082e1069839SBorislav Petkov 3083e1069839SBorislav Petkov /* 3084e1069839SBorislav Petkov * Only put constraint if extra reg was actually allocated. Also takes 3085e1069839SBorislav Petkov * care of event which do not use an extra shared reg. 3086e1069839SBorislav Petkov * 3087e1069839SBorislav Petkov * Also, if this is a fake cpuc we shouldn't touch any event state 3088e1069839SBorislav Petkov * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3089e1069839SBorislav Petkov * either since it'll be thrown out. 3090e1069839SBorislav Petkov */ 3091e1069839SBorislav Petkov if (!reg->alloc || cpuc->is_fake) 3092e1069839SBorislav Petkov return; 3093e1069839SBorislav Petkov 3094e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[reg->idx]; 3095e1069839SBorislav Petkov 3096e1069839SBorislav Petkov /* one fewer user */ 3097e1069839SBorislav Petkov atomic_dec(&era->ref); 3098e1069839SBorislav Petkov 3099e1069839SBorislav Petkov /* allocate again next time */ 3100e1069839SBorislav Petkov reg->alloc = 0; 3101e1069839SBorislav Petkov } 3102e1069839SBorislav Petkov 3103e1069839SBorislav Petkov static struct event_constraint * 3104e1069839SBorislav Petkov intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3105e1069839SBorislav Petkov struct perf_event *event) 3106e1069839SBorislav Petkov { 3107e1069839SBorislav Petkov struct event_constraint *c = NULL, *d; 3108e1069839SBorislav Petkov struct hw_perf_event_extra *xreg, *breg; 3109e1069839SBorislav Petkov 3110e1069839SBorislav Petkov xreg = &event->hw.extra_reg; 3111e1069839SBorislav Petkov if (xreg->idx != EXTRA_REG_NONE) { 3112e1069839SBorislav Petkov c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3113e1069839SBorislav Petkov if (c == &emptyconstraint) 3114e1069839SBorislav Petkov return c; 3115e1069839SBorislav Petkov } 3116e1069839SBorislav Petkov breg = &event->hw.branch_reg; 3117e1069839SBorislav Petkov if (breg->idx != EXTRA_REG_NONE) { 3118e1069839SBorislav Petkov d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3119e1069839SBorislav Petkov if (d == &emptyconstraint) { 3120e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, xreg); 3121e1069839SBorislav Petkov c = d; 3122e1069839SBorislav Petkov } 3123e1069839SBorislav Petkov } 3124e1069839SBorislav Petkov return c; 3125e1069839SBorislav Petkov } 3126e1069839SBorislav Petkov 3127e1069839SBorislav Petkov struct event_constraint * 3128e1069839SBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3129e1069839SBorislav Petkov struct perf_event *event) 3130e1069839SBorislav Petkov { 3131e1069839SBorislav Petkov struct event_constraint *c; 3132e1069839SBorislav Petkov 3133e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 3134e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 313563b79f6eSPeter Zijlstra if (constraint_match(c, event->hw.config)) { 3136e1069839SBorislav Petkov event->hw.flags |= c->flags; 3137e1069839SBorislav Petkov return c; 3138e1069839SBorislav Petkov } 3139e1069839SBorislav Petkov } 3140e1069839SBorislav Petkov } 3141e1069839SBorislav Petkov 3142e1069839SBorislav Petkov return &unconstrained; 3143e1069839SBorislav Petkov } 3144e1069839SBorislav Petkov 3145e1069839SBorislav Petkov static struct event_constraint * 3146e1069839SBorislav Petkov __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3147e1069839SBorislav Petkov struct perf_event *event) 3148e1069839SBorislav Petkov { 3149e1069839SBorislav Petkov struct event_constraint *c; 3150e1069839SBorislav Petkov 3151097e4311SLike Xu c = intel_vlbr_constraints(event); 3152097e4311SLike Xu if (c) 3153097e4311SLike Xu return c; 3154097e4311SLike Xu 3155e1069839SBorislav Petkov c = intel_bts_constraints(event); 3156e1069839SBorislav Petkov if (c) 3157e1069839SBorislav Petkov return c; 3158e1069839SBorislav Petkov 3159e1069839SBorislav Petkov c = intel_shared_regs_constraints(cpuc, event); 3160e1069839SBorislav Petkov if (c) 3161e1069839SBorislav Petkov return c; 3162e1069839SBorislav Petkov 3163e1069839SBorislav Petkov c = intel_pebs_constraints(event); 3164e1069839SBorislav Petkov if (c) 3165e1069839SBorislav Petkov return c; 3166e1069839SBorislav Petkov 3167e1069839SBorislav Petkov return x86_get_event_constraints(cpuc, idx, event); 3168e1069839SBorislav Petkov } 3169e1069839SBorislav Petkov 3170e1069839SBorislav Petkov static void 3171e1069839SBorislav Petkov intel_start_scheduling(struct cpu_hw_events *cpuc) 3172e1069839SBorislav Petkov { 3173e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3174e1069839SBorislav Petkov struct intel_excl_states *xl; 3175e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3176e1069839SBorislav Petkov 3177e1069839SBorislav Petkov /* 3178e1069839SBorislav Petkov * nothing needed if in group validation mode 3179e1069839SBorislav Petkov */ 3180e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3181e1069839SBorislav Petkov return; 3182e1069839SBorislav Petkov 3183e1069839SBorislav Petkov /* 3184e1069839SBorislav Petkov * no exclusion needed 3185e1069839SBorislav Petkov */ 3186e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3187e1069839SBorislav Petkov return; 3188e1069839SBorislav Petkov 3189e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3190e1069839SBorislav Petkov 3191e1069839SBorislav Petkov xl->sched_started = true; 3192e1069839SBorislav Petkov /* 3193e1069839SBorislav Petkov * lock shared state until we are done scheduling 3194e1069839SBorislav Petkov * in stop_event_scheduling() 3195e1069839SBorislav Petkov * makes scheduling appear as a transaction 3196e1069839SBorislav Petkov */ 3197e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3198e1069839SBorislav Petkov } 3199e1069839SBorislav Petkov 3200e1069839SBorislav Petkov static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3201e1069839SBorislav Petkov { 3202e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3203e1069839SBorislav Petkov struct event_constraint *c = cpuc->event_constraint[idx]; 3204e1069839SBorislav Petkov struct intel_excl_states *xl; 3205e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3206e1069839SBorislav Petkov 3207e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3208e1069839SBorislav Petkov return; 3209e1069839SBorislav Petkov 3210e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3211e1069839SBorislav Petkov return; 3212e1069839SBorislav Petkov 3213e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3214e1069839SBorislav Petkov return; 3215e1069839SBorislav Petkov 3216e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3217e1069839SBorislav Petkov 3218e1069839SBorislav Petkov lockdep_assert_held(&excl_cntrs->lock); 3219e1069839SBorislav Petkov 3220e1069839SBorislav Petkov if (c->flags & PERF_X86_EVENT_EXCL) 3221e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3222e1069839SBorislav Petkov else 3223e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_SHARED; 3224e1069839SBorislav Petkov } 3225e1069839SBorislav Petkov 3226e1069839SBorislav Petkov static void 3227e1069839SBorislav Petkov intel_stop_scheduling(struct cpu_hw_events *cpuc) 3228e1069839SBorislav Petkov { 3229e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3230e1069839SBorislav Petkov struct intel_excl_states *xl; 3231e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3232e1069839SBorislav Petkov 3233e1069839SBorislav Petkov /* 3234e1069839SBorislav Petkov * nothing needed if in group validation mode 3235e1069839SBorislav Petkov */ 3236e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3237e1069839SBorislav Petkov return; 3238e1069839SBorislav Petkov /* 3239e1069839SBorislav Petkov * no exclusion needed 3240e1069839SBorislav Petkov */ 3241e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3242e1069839SBorislav Petkov return; 3243e1069839SBorislav Petkov 3244e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3245e1069839SBorislav Petkov 3246e1069839SBorislav Petkov xl->sched_started = false; 3247e1069839SBorislav Petkov /* 3248e1069839SBorislav Petkov * release shared state lock (acquired in intel_start_scheduling()) 3249e1069839SBorislav Petkov */ 3250e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3251e1069839SBorislav Petkov } 3252e1069839SBorislav Petkov 3253e1069839SBorislav Petkov static struct event_constraint * 325411f8b2d6SPeter Zijlstra (Intel) dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 325511f8b2d6SPeter Zijlstra (Intel) { 325611f8b2d6SPeter Zijlstra (Intel) WARN_ON_ONCE(!cpuc->constraint_list); 325711f8b2d6SPeter Zijlstra (Intel) 325811f8b2d6SPeter Zijlstra (Intel) if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 325911f8b2d6SPeter Zijlstra (Intel) struct event_constraint *cx; 326011f8b2d6SPeter Zijlstra (Intel) 326111f8b2d6SPeter Zijlstra (Intel) /* 326211f8b2d6SPeter Zijlstra (Intel) * grab pre-allocated constraint entry 326311f8b2d6SPeter Zijlstra (Intel) */ 326411f8b2d6SPeter Zijlstra (Intel) cx = &cpuc->constraint_list[idx]; 326511f8b2d6SPeter Zijlstra (Intel) 326611f8b2d6SPeter Zijlstra (Intel) /* 326711f8b2d6SPeter Zijlstra (Intel) * initialize dynamic constraint 326811f8b2d6SPeter Zijlstra (Intel) * with static constraint 326911f8b2d6SPeter Zijlstra (Intel) */ 327011f8b2d6SPeter Zijlstra (Intel) *cx = *c; 327111f8b2d6SPeter Zijlstra (Intel) 327211f8b2d6SPeter Zijlstra (Intel) /* 327311f8b2d6SPeter Zijlstra (Intel) * mark constraint as dynamic 327411f8b2d6SPeter Zijlstra (Intel) */ 327511f8b2d6SPeter Zijlstra (Intel) cx->flags |= PERF_X86_EVENT_DYNAMIC; 327611f8b2d6SPeter Zijlstra (Intel) c = cx; 327711f8b2d6SPeter Zijlstra (Intel) } 327811f8b2d6SPeter Zijlstra (Intel) 327911f8b2d6SPeter Zijlstra (Intel) return c; 328011f8b2d6SPeter Zijlstra (Intel) } 328111f8b2d6SPeter Zijlstra (Intel) 328211f8b2d6SPeter Zijlstra (Intel) static struct event_constraint * 3283e1069839SBorislav Petkov intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3284e1069839SBorislav Petkov int idx, struct event_constraint *c) 3285e1069839SBorislav Petkov { 3286e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3287e1069839SBorislav Petkov struct intel_excl_states *xlo; 3288e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3289c090cb70SPeter Zijlstra int is_excl, i, w; 3290e1069839SBorislav Petkov 3291e1069839SBorislav Petkov /* 3292e1069839SBorislav Petkov * validating a group does not require 3293e1069839SBorislav Petkov * enforcing cross-thread exclusion 3294e1069839SBorislav Petkov */ 3295e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3296e1069839SBorislav Petkov return c; 3297e1069839SBorislav Petkov 3298e1069839SBorislav Petkov /* 3299e1069839SBorislav Petkov * no exclusion needed 3300e1069839SBorislav Petkov */ 3301e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3302e1069839SBorislav Petkov return c; 3303e1069839SBorislav Petkov 3304e1069839SBorislav Petkov /* 3305e1069839SBorislav Petkov * because we modify the constraint, we need 3306e1069839SBorislav Petkov * to make a copy. Static constraints come 3307e1069839SBorislav Petkov * from static const tables. 3308e1069839SBorislav Petkov * 3309e1069839SBorislav Petkov * only needed when constraint has not yet 3310e1069839SBorislav Petkov * been cloned (marked dynamic) 3311e1069839SBorislav Petkov */ 331211f8b2d6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 3313e1069839SBorislav Petkov 3314e1069839SBorislav Petkov /* 3315e1069839SBorislav Petkov * From here on, the constraint is dynamic. 3316e1069839SBorislav Petkov * Either it was just allocated above, or it 3317e1069839SBorislav Petkov * was allocated during a earlier invocation 3318e1069839SBorislav Petkov * of this function 3319e1069839SBorislav Petkov */ 3320e1069839SBorislav Petkov 3321e1069839SBorislav Petkov /* 3322e1069839SBorislav Petkov * state of sibling HT 3323e1069839SBorislav Petkov */ 3324e1069839SBorislav Petkov xlo = &excl_cntrs->states[tid ^ 1]; 3325e1069839SBorislav Petkov 3326e1069839SBorislav Petkov /* 3327e1069839SBorislav Petkov * event requires exclusive counter access 3328e1069839SBorislav Petkov * across HT threads 3329e1069839SBorislav Petkov */ 3330e1069839SBorislav Petkov is_excl = c->flags & PERF_X86_EVENT_EXCL; 3331e1069839SBorislav Petkov if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3332e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3333e1069839SBorislav Petkov if (!cpuc->n_excl++) 3334e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3335e1069839SBorislav Petkov } 3336e1069839SBorislav Petkov 3337e1069839SBorislav Petkov /* 3338e1069839SBorislav Petkov * Modify static constraint with current dynamic 3339e1069839SBorislav Petkov * state of thread 3340e1069839SBorislav Petkov * 3341e1069839SBorislav Petkov * EXCLUSIVE: sibling counter measuring exclusive event 3342e1069839SBorislav Petkov * SHARED : sibling counter measuring non-exclusive event 3343e1069839SBorislav Petkov * UNUSED : sibling counter unused 3344e1069839SBorislav Petkov */ 3345c090cb70SPeter Zijlstra w = c->weight; 3346e1069839SBorislav Petkov for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3347e1069839SBorislav Petkov /* 3348e1069839SBorislav Petkov * exclusive event in sibling counter 3349e1069839SBorislav Petkov * our corresponding counter cannot be used 3350e1069839SBorislav Petkov * regardless of our event 3351e1069839SBorislav Petkov */ 3352c090cb70SPeter Zijlstra if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3353e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 3354c090cb70SPeter Zijlstra w--; 3355c090cb70SPeter Zijlstra continue; 3356c090cb70SPeter Zijlstra } 3357e1069839SBorislav Petkov /* 3358e1069839SBorislav Petkov * if measuring an exclusive event, sibling 3359e1069839SBorislav Petkov * measuring non-exclusive, then counter cannot 3360e1069839SBorislav Petkov * be used 3361e1069839SBorislav Petkov */ 3362c090cb70SPeter Zijlstra if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3363e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 3364c090cb70SPeter Zijlstra w--; 3365c090cb70SPeter Zijlstra continue; 3366e1069839SBorislav Petkov } 3367c090cb70SPeter Zijlstra } 3368e1069839SBorislav Petkov 3369e1069839SBorislav Petkov /* 3370e1069839SBorislav Petkov * if we return an empty mask, then switch 3371e1069839SBorislav Petkov * back to static empty constraint to avoid 3372e1069839SBorislav Petkov * the cost of freeing later on 3373e1069839SBorislav Petkov */ 3374c090cb70SPeter Zijlstra if (!w) 3375e1069839SBorislav Petkov c = &emptyconstraint; 3376e1069839SBorislav Petkov 3377c090cb70SPeter Zijlstra c->weight = w; 3378c090cb70SPeter Zijlstra 3379e1069839SBorislav Petkov return c; 3380e1069839SBorislav Petkov } 3381e1069839SBorislav Petkov 3382e1069839SBorislav Petkov static struct event_constraint * 3383e1069839SBorislav Petkov intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3384e1069839SBorislav Petkov struct perf_event *event) 3385e1069839SBorislav Petkov { 338621d65555SPeter Zijlstra struct event_constraint *c1, *c2; 3387e1069839SBorislav Petkov 3388e1069839SBorislav Petkov c1 = cpuc->event_constraint[idx]; 3389e1069839SBorislav Petkov 3390e1069839SBorislav Petkov /* 3391e1069839SBorislav Petkov * first time only 3392e1069839SBorislav Petkov * - static constraint: no change across incremental scheduling calls 3393e1069839SBorislav Petkov * - dynamic constraint: handled by intel_get_excl_constraints() 3394e1069839SBorislav Petkov */ 3395e1069839SBorislav Petkov c2 = __intel_get_event_constraints(cpuc, idx, event); 3396109717deSPeter Zijlstra if (c1) { 3397109717deSPeter Zijlstra WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3398e1069839SBorislav Petkov bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3399e1069839SBorislav Petkov c1->weight = c2->weight; 3400e1069839SBorislav Petkov c2 = c1; 3401e1069839SBorislav Petkov } 3402e1069839SBorislav Petkov 3403e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3404e1069839SBorislav Petkov return intel_get_excl_constraints(cpuc, event, idx, c2); 3405e1069839SBorislav Petkov 3406e1069839SBorislav Petkov return c2; 3407e1069839SBorislav Petkov } 3408e1069839SBorislav Petkov 3409e1069839SBorislav Petkov static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3410e1069839SBorislav Petkov struct perf_event *event) 3411e1069839SBorislav Petkov { 3412e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 3413e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3414e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3415e1069839SBorislav Petkov struct intel_excl_states *xl; 3416e1069839SBorislav Petkov 3417e1069839SBorislav Petkov /* 3418e1069839SBorislav Petkov * nothing needed if in group validation mode 3419e1069839SBorislav Petkov */ 3420e1069839SBorislav Petkov if (cpuc->is_fake) 3421e1069839SBorislav Petkov return; 3422e1069839SBorislav Petkov 3423e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3424e1069839SBorislav Petkov return; 3425e1069839SBorislav Petkov 3426e1069839SBorislav Petkov if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3427e1069839SBorislav Petkov hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3428e1069839SBorislav Petkov if (!--cpuc->n_excl) 3429e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3430e1069839SBorislav Petkov } 3431e1069839SBorislav Petkov 3432e1069839SBorislav Petkov /* 3433e1069839SBorislav Petkov * If event was actually assigned, then mark the counter state as 3434e1069839SBorislav Petkov * unused now. 3435e1069839SBorislav Petkov */ 3436e1069839SBorislav Petkov if (hwc->idx >= 0) { 3437e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3438e1069839SBorislav Petkov 3439e1069839SBorislav Petkov /* 3440e1069839SBorislav Petkov * put_constraint may be called from x86_schedule_events() 3441e1069839SBorislav Petkov * which already has the lock held so here make locking 3442e1069839SBorislav Petkov * conditional. 3443e1069839SBorislav Petkov */ 3444e1069839SBorislav Petkov if (!xl->sched_started) 3445e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3446e1069839SBorislav Petkov 3447e1069839SBorislav Petkov xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3448e1069839SBorislav Petkov 3449e1069839SBorislav Petkov if (!xl->sched_started) 3450e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3451e1069839SBorislav Petkov } 3452e1069839SBorislav Petkov } 3453e1069839SBorislav Petkov 3454e1069839SBorislav Petkov static void 3455e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3456e1069839SBorislav Petkov struct perf_event *event) 3457e1069839SBorislav Petkov { 3458e1069839SBorislav Petkov struct hw_perf_event_extra *reg; 3459e1069839SBorislav Petkov 3460e1069839SBorislav Petkov reg = &event->hw.extra_reg; 3461e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3462e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3463e1069839SBorislav Petkov 3464e1069839SBorislav Petkov reg = &event->hw.branch_reg; 3465e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3466e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3467e1069839SBorislav Petkov } 3468e1069839SBorislav Petkov 3469e1069839SBorislav Petkov static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3470e1069839SBorislav Petkov struct perf_event *event) 3471e1069839SBorislav Petkov { 3472e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(cpuc, event); 3473e1069839SBorislav Petkov 3474e1069839SBorislav Petkov /* 3475e1069839SBorislav Petkov * is PMU has exclusive counter restrictions, then 3476e1069839SBorislav Petkov * all events are subject to and must call the 3477e1069839SBorislav Petkov * put_excl_constraints() routine 3478e1069839SBorislav Petkov */ 3479e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3480e1069839SBorislav Petkov intel_put_excl_constraints(cpuc, event); 3481e1069839SBorislav Petkov } 3482e1069839SBorislav Petkov 3483e1069839SBorislav Petkov static void intel_pebs_aliases_core2(struct perf_event *event) 3484e1069839SBorislav Petkov { 3485e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3486e1069839SBorislav Petkov /* 3487e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3488e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3489e1069839SBorislav Petkov * 3490e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3491e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.ANY_P 3492e1069839SBorislav Petkov * (0x00c0), which is a PEBS capable event, to get the same 3493e1069839SBorislav Petkov * count. 3494e1069839SBorislav Petkov * 3495e1069839SBorislav Petkov * INST_RETIRED.ANY_P counts the number of cycles that retires 3496e1069839SBorislav Petkov * CNTMASK instructions. By setting CNTMASK to a value (16) 3497e1069839SBorislav Petkov * larger than the maximum number of instructions that can be 3498e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3499e1069839SBorislav Petkov * count all cycles that retire 16 or less instructions, which 3500e1069839SBorislav Petkov * is every cycle. 3501e1069839SBorislav Petkov * 3502e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3503e1069839SBorislav Petkov */ 3504e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3505e1069839SBorislav Petkov 3506e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3507e1069839SBorislav Petkov event->hw.config = alt_config; 3508e1069839SBorislav Petkov } 3509e1069839SBorislav Petkov } 3510e1069839SBorislav Petkov 3511e1069839SBorislav Petkov static void intel_pebs_aliases_snb(struct perf_event *event) 3512e1069839SBorislav Petkov { 3513e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3514e1069839SBorislav Petkov /* 3515e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3516e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3517e1069839SBorislav Petkov * 3518e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3519e1069839SBorislav Petkov * PEBS capable. However we can use UOPS_RETIRED.ALL 3520e1069839SBorislav Petkov * (0x01c2), which is a PEBS capable event, to get the same 3521e1069839SBorislav Petkov * count. 3522e1069839SBorislav Petkov * 3523e1069839SBorislav Petkov * UOPS_RETIRED.ALL counts the number of cycles that retires 3524e1069839SBorislav Petkov * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3525e1069839SBorislav Petkov * larger than the maximum number of micro-ops that can be 3526e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3527e1069839SBorislav Petkov * count all cycles that retire 16 or less micro-ops, which 3528e1069839SBorislav Petkov * is every cycle. 3529e1069839SBorislav Petkov * 3530e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3531e1069839SBorislav Petkov */ 3532e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3533e1069839SBorislav Petkov 3534e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3535e1069839SBorislav Petkov event->hw.config = alt_config; 3536e1069839SBorislav Petkov } 3537e1069839SBorislav Petkov } 3538e1069839SBorislav Petkov 3539e1069839SBorislav Petkov static void intel_pebs_aliases_precdist(struct perf_event *event) 3540e1069839SBorislav Petkov { 3541e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3542e1069839SBorislav Petkov /* 3543e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3544e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3545e1069839SBorislav Petkov * 3546e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3547e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3548e1069839SBorislav Petkov * (0x01c0), which is a PEBS capable event, to get the same 3549e1069839SBorislav Petkov * count. 3550e1069839SBorislav Petkov * 3551e1069839SBorislav Petkov * The PREC_DIST event has special support to minimize sample 3552e1069839SBorislav Petkov * shadowing effects. One drawback is that it can be 3553e1069839SBorislav Petkov * only programmed on counter 1, but that seems like an 3554e1069839SBorislav Petkov * acceptable trade off. 3555e1069839SBorislav Petkov */ 3556e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3557e1069839SBorislav Petkov 3558e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3559e1069839SBorislav Petkov event->hw.config = alt_config; 3560e1069839SBorislav Petkov } 3561e1069839SBorislav Petkov } 3562e1069839SBorislav Petkov 3563e1069839SBorislav Petkov static void intel_pebs_aliases_ivb(struct perf_event *event) 3564e1069839SBorislav Petkov { 3565e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3566e1069839SBorislav Petkov return intel_pebs_aliases_snb(event); 3567e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3568e1069839SBorislav Petkov } 3569e1069839SBorislav Petkov 3570e1069839SBorislav Petkov static void intel_pebs_aliases_skl(struct perf_event *event) 3571e1069839SBorislav Petkov { 3572e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3573e1069839SBorislav Petkov return intel_pebs_aliases_core2(event); 3574e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3575e1069839SBorislav Petkov } 3576e1069839SBorislav Petkov 3577174afc3eSKan Liang static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3578e1069839SBorislav Petkov { 3579174afc3eSKan Liang unsigned long flags = x86_pmu.large_pebs_flags; 3580e1069839SBorislav Petkov 3581e1069839SBorislav Petkov if (event->attr.use_clockid) 3582e1069839SBorislav Petkov flags &= ~PERF_SAMPLE_TIME; 3583a47ba4d7SAndi Kleen if (!event->attr.exclude_kernel) 3584a47ba4d7SAndi Kleen flags &= ~PERF_SAMPLE_REGS_USER; 35859d5dcc93SKan Liang if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3586a47ba4d7SAndi Kleen flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3587e1069839SBorislav Petkov return flags; 3588e1069839SBorislav Petkov } 3589e1069839SBorislav Petkov 3590ed6101bbSJiri Olsa static int intel_pmu_bts_config(struct perf_event *event) 3591ed6101bbSJiri Olsa { 3592ed6101bbSJiri Olsa struct perf_event_attr *attr = &event->attr; 3593ed6101bbSJiri Olsa 359467266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) { 3595ed6101bbSJiri Olsa /* BTS is not supported by this architecture. */ 3596ed6101bbSJiri Olsa if (!x86_pmu.bts_active) 3597ed6101bbSJiri Olsa return -EOPNOTSUPP; 3598ed6101bbSJiri Olsa 3599ed6101bbSJiri Olsa /* BTS is currently only allowed for user-mode. */ 3600ed6101bbSJiri Olsa if (!attr->exclude_kernel) 3601ed6101bbSJiri Olsa return -EOPNOTSUPP; 3602ed6101bbSJiri Olsa 3603472de49fSJiri Olsa /* BTS is not allowed for precise events. */ 3604472de49fSJiri Olsa if (attr->precise_ip) 3605472de49fSJiri Olsa return -EOPNOTSUPP; 3606472de49fSJiri Olsa 3607ed6101bbSJiri Olsa /* disallow bts if conflicting events are present */ 3608ed6101bbSJiri Olsa if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3609ed6101bbSJiri Olsa return -EBUSY; 3610ed6101bbSJiri Olsa 3611ed6101bbSJiri Olsa event->destroy = hw_perf_lbr_event_destroy; 3612ed6101bbSJiri Olsa } 3613ed6101bbSJiri Olsa 3614ed6101bbSJiri Olsa return 0; 3615ed6101bbSJiri Olsa } 3616ed6101bbSJiri Olsa 3617ed6101bbSJiri Olsa static int core_pmu_hw_config(struct perf_event *event) 3618ed6101bbSJiri Olsa { 3619ed6101bbSJiri Olsa int ret = x86_pmu_hw_config(event); 3620ed6101bbSJiri Olsa 3621ed6101bbSJiri Olsa if (ret) 3622ed6101bbSJiri Olsa return ret; 3623ed6101bbSJiri Olsa 3624ed6101bbSJiri Olsa return intel_pmu_bts_config(event); 3625ed6101bbSJiri Olsa } 3626ed6101bbSJiri Olsa 36271ab5f235SKan Liang #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 36281ab5f235SKan Liang ((x86_pmu.num_topdown_events - 1) << 8)) 36291ab5f235SKan Liang 36301ab5f235SKan Liang static bool is_available_metric_event(struct perf_event *event) 36311ab5f235SKan Liang { 36321ab5f235SKan Liang return is_metric_event(event) && 36331ab5f235SKan Liang event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 36341ab5f235SKan Liang } 36351ab5f235SKan Liang 3636*61b985e3SKan Liang static inline bool is_mem_loads_event(struct perf_event *event) 3637*61b985e3SKan Liang { 3638*61b985e3SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 3639*61b985e3SKan Liang } 3640*61b985e3SKan Liang 3641*61b985e3SKan Liang static inline bool is_mem_loads_aux_event(struct perf_event *event) 3642*61b985e3SKan Liang { 3643*61b985e3SKan Liang return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 3644*61b985e3SKan Liang } 3645*61b985e3SKan Liang 3646*61b985e3SKan Liang 3647e1069839SBorislav Petkov static int intel_pmu_hw_config(struct perf_event *event) 3648e1069839SBorislav Petkov { 3649e1069839SBorislav Petkov int ret = x86_pmu_hw_config(event); 3650e1069839SBorislav Petkov 3651e1069839SBorislav Petkov if (ret) 3652e1069839SBorislav Petkov return ret; 3653e1069839SBorislav Petkov 3654ed6101bbSJiri Olsa ret = intel_pmu_bts_config(event); 3655ed6101bbSJiri Olsa if (ret) 3656ed6101bbSJiri Olsa return ret; 3657ed6101bbSJiri Olsa 3658e1069839SBorislav Petkov if (event->attr.precise_ip) { 3659c7a28657SStephane Eranian if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3660e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3661e1069839SBorislav Petkov if (!(event->attr.sample_type & 3662174afc3eSKan Liang ~intel_pmu_large_pebs_flags(event))) 3663174afc3eSKan Liang event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3664e1069839SBorislav Petkov } 3665e1069839SBorislav Petkov if (x86_pmu.pebs_aliases) 3666e1069839SBorislav Petkov x86_pmu.pebs_aliases(event); 36676cbc304fSPeter Zijlstra 36686cbc304fSPeter Zijlstra if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 36696cbc304fSPeter Zijlstra event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3670e1069839SBorislav Petkov } 3671e1069839SBorislav Petkov 3672e1069839SBorislav Petkov if (needs_branch_stack(event)) { 3673e1069839SBorislav Petkov ret = intel_pmu_setup_lbr_filter(event); 3674e1069839SBorislav Petkov if (ret) 3675e1069839SBorislav Petkov return ret; 3676e1069839SBorislav Petkov 3677e1069839SBorislav Petkov /* 3678e1069839SBorislav Petkov * BTS is set up earlier in this path, so don't account twice 3679e1069839SBorislav Petkov */ 368067266c10SJiri Olsa if (!unlikely(intel_pmu_has_bts(event))) { 3681e1069839SBorislav Petkov /* disallow lbr if conflicting events are present */ 3682e1069839SBorislav Petkov if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3683e1069839SBorislav Petkov return -EBUSY; 3684e1069839SBorislav Petkov 3685e1069839SBorislav Petkov event->destroy = hw_perf_lbr_event_destroy; 3686e1069839SBorislav Petkov } 3687e1069839SBorislav Petkov } 3688e1069839SBorislav Petkov 368942880f72SAlexander Shishkin if (event->attr.aux_output) { 369042880f72SAlexander Shishkin if (!event->attr.precise_ip) 369142880f72SAlexander Shishkin return -EINVAL; 369242880f72SAlexander Shishkin 369342880f72SAlexander Shishkin event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 369442880f72SAlexander Shishkin } 369542880f72SAlexander Shishkin 3696e1069839SBorislav Petkov if (event->attr.type != PERF_TYPE_RAW) 3697e1069839SBorislav Petkov return 0; 3698e1069839SBorislav Petkov 36997b2c05a1SKan Liang /* 37007b2c05a1SKan Liang * Config Topdown slots and metric events 37017b2c05a1SKan Liang * 37027b2c05a1SKan Liang * The slots event on Fixed Counter 3 can support sampling, 37037b2c05a1SKan Liang * which will be handled normally in x86_perf_event_update(). 37047b2c05a1SKan Liang * 37057b2c05a1SKan Liang * Metric events don't support sampling and require being paired 37067b2c05a1SKan Liang * with a slots event as group leader. When the slots event 37077b2c05a1SKan Liang * is used in a metrics group, it too cannot support sampling. 37087b2c05a1SKan Liang */ 37097b2c05a1SKan Liang if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) { 37107b2c05a1SKan Liang if (event->attr.config1 || event->attr.config2) 37117b2c05a1SKan Liang return -EINVAL; 37127b2c05a1SKan Liang 37137b2c05a1SKan Liang /* 37147b2c05a1SKan Liang * The TopDown metrics events and slots event don't 37157b2c05a1SKan Liang * support any filters. 37167b2c05a1SKan Liang */ 37177b2c05a1SKan Liang if (event->attr.config & X86_ALL_EVENT_FLAGS) 37187b2c05a1SKan Liang return -EINVAL; 37197b2c05a1SKan Liang 37201ab5f235SKan Liang if (is_available_metric_event(event)) { 37217b2c05a1SKan Liang struct perf_event *leader = event->group_leader; 37227b2c05a1SKan Liang 37237b2c05a1SKan Liang /* The metric events don't support sampling. */ 37247b2c05a1SKan Liang if (is_sampling_event(event)) 37257b2c05a1SKan Liang return -EINVAL; 37267b2c05a1SKan Liang 37277b2c05a1SKan Liang /* The metric events require a slots group leader. */ 37287b2c05a1SKan Liang if (!is_slots_event(leader)) 37297b2c05a1SKan Liang return -EINVAL; 37307b2c05a1SKan Liang 37317b2c05a1SKan Liang /* 37327b2c05a1SKan Liang * The leader/SLOTS must not be a sampling event for 37337b2c05a1SKan Liang * metric use; hardware requires it starts at 0 when used 37347b2c05a1SKan Liang * in conjunction with MSR_PERF_METRICS. 37357b2c05a1SKan Liang */ 37367b2c05a1SKan Liang if (is_sampling_event(leader)) 37377b2c05a1SKan Liang return -EINVAL; 37387b2c05a1SKan Liang 37397b2c05a1SKan Liang event->event_caps |= PERF_EV_CAP_SIBLING; 37407b2c05a1SKan Liang /* 37417b2c05a1SKan Liang * Only once we have a METRICs sibling do we 37427b2c05a1SKan Liang * need TopDown magic. 37437b2c05a1SKan Liang */ 37447b2c05a1SKan Liang leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 37457b2c05a1SKan Liang event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 37467b2c05a1SKan Liang } 37477b2c05a1SKan Liang } 37487b2c05a1SKan Liang 3749*61b985e3SKan Liang /* 3750*61b985e3SKan Liang * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 3751*61b985e3SKan Liang * doesn't function quite right. As a work-around it needs to always be 3752*61b985e3SKan Liang * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 3753*61b985e3SKan Liang * The actual count of this second event is irrelevant it just needs 3754*61b985e3SKan Liang * to be active to make the first event function correctly. 3755*61b985e3SKan Liang * 3756*61b985e3SKan Liang * In a group, the auxiliary event must be in front of the load latency 3757*61b985e3SKan Liang * event. The rule is to simplify the implementation of the check. 3758*61b985e3SKan Liang * That's because perf cannot have a complete group at the moment. 3759*61b985e3SKan Liang */ 3760*61b985e3SKan Liang if (x86_pmu.flags & PMU_FL_MEM_LOADS_AUX && 3761*61b985e3SKan Liang (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 3762*61b985e3SKan Liang is_mem_loads_event(event)) { 3763*61b985e3SKan Liang struct perf_event *leader = event->group_leader; 3764*61b985e3SKan Liang struct perf_event *sibling = NULL; 3765*61b985e3SKan Liang 3766*61b985e3SKan Liang if (!is_mem_loads_aux_event(leader)) { 3767*61b985e3SKan Liang for_each_sibling_event(sibling, leader) { 3768*61b985e3SKan Liang if (is_mem_loads_aux_event(sibling)) 3769*61b985e3SKan Liang break; 3770*61b985e3SKan Liang } 3771*61b985e3SKan Liang if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 3772*61b985e3SKan Liang return -ENODATA; 3773*61b985e3SKan Liang } 3774*61b985e3SKan Liang } 3775*61b985e3SKan Liang 3776e1069839SBorislav Petkov if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3777e1069839SBorislav Petkov return 0; 3778e1069839SBorislav Petkov 3779e1069839SBorislav Petkov if (x86_pmu.version < 3) 3780e1069839SBorislav Petkov return -EINVAL; 3781e1069839SBorislav Petkov 3782da97e184SJoel Fernandes (Google) ret = perf_allow_cpu(&event->attr); 3783da97e184SJoel Fernandes (Google) if (ret) 3784da97e184SJoel Fernandes (Google) return ret; 3785e1069839SBorislav Petkov 3786e1069839SBorislav Petkov event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3787e1069839SBorislav Petkov 3788e1069839SBorislav Petkov return 0; 3789e1069839SBorislav Petkov } 3790e1069839SBorislav Petkov 3791e1069839SBorislav Petkov static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3792e1069839SBorislav Petkov { 3793e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3794e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3795e1069839SBorislav Petkov 3796e1069839SBorislav Petkov arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3797e1069839SBorislav Petkov arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3798e1069839SBorislav Petkov arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 37999b545c04SAndi Kleen if (x86_pmu.flags & PMU_FL_PEBS_ALL) 38009b545c04SAndi Kleen arr[0].guest &= ~cpuc->pebs_enabled; 38019b545c04SAndi Kleen else 38029b545c04SAndi Kleen arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 38039b545c04SAndi Kleen *nr = 1; 38049b545c04SAndi Kleen 38059b545c04SAndi Kleen if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3806e1069839SBorislav Petkov /* 38079b545c04SAndi Kleen * If PMU counter has PEBS enabled it is not enough to 38089b545c04SAndi Kleen * disable counter on a guest entry since PEBS memory 38099b545c04SAndi Kleen * write can overshoot guest entry and corrupt guest 38109b545c04SAndi Kleen * memory. Disabling PEBS solves the problem. 38119b545c04SAndi Kleen * 38129b545c04SAndi Kleen * Don't do this if the CPU already enforces it. 3813e1069839SBorislav Petkov */ 3814e1069839SBorislav Petkov arr[1].msr = MSR_IA32_PEBS_ENABLE; 3815e1069839SBorislav Petkov arr[1].host = cpuc->pebs_enabled; 3816e1069839SBorislav Petkov arr[1].guest = 0; 3817e1069839SBorislav Petkov *nr = 2; 38189b545c04SAndi Kleen } 38199b545c04SAndi Kleen 3820e1069839SBorislav Petkov return arr; 3821e1069839SBorislav Petkov } 3822e1069839SBorislav Petkov 3823e1069839SBorislav Petkov static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3824e1069839SBorislav Petkov { 3825e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3826e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3827e1069839SBorislav Petkov int idx; 3828e1069839SBorislav Petkov 3829e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3830e1069839SBorislav Petkov struct perf_event *event = cpuc->events[idx]; 3831e1069839SBorislav Petkov 3832e1069839SBorislav Petkov arr[idx].msr = x86_pmu_config_addr(idx); 3833e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 0; 3834e1069839SBorislav Petkov 3835e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) 3836e1069839SBorislav Petkov continue; 3837e1069839SBorislav Petkov 3838e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 3839e1069839SBorislav Petkov event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3840e1069839SBorislav Petkov 3841e1069839SBorislav Petkov if (event->attr.exclude_host) 3842e1069839SBorislav Petkov arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3843e1069839SBorislav Petkov else if (event->attr.exclude_guest) 3844e1069839SBorislav Petkov arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3845e1069839SBorislav Petkov } 3846e1069839SBorislav Petkov 3847e1069839SBorislav Petkov *nr = x86_pmu.num_counters; 3848e1069839SBorislav Petkov return arr; 3849e1069839SBorislav Petkov } 3850e1069839SBorislav Petkov 3851e1069839SBorislav Petkov static void core_pmu_enable_event(struct perf_event *event) 3852e1069839SBorislav Petkov { 3853e1069839SBorislav Petkov if (!event->attr.exclude_host) 3854e1069839SBorislav Petkov x86_pmu_enable_event(event); 3855e1069839SBorislav Petkov } 3856e1069839SBorislav Petkov 3857e1069839SBorislav Petkov static void core_pmu_enable_all(int added) 3858e1069839SBorislav Petkov { 3859e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3860e1069839SBorislav Petkov int idx; 3861e1069839SBorislav Petkov 3862e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3863e1069839SBorislav Petkov struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3864e1069839SBorislav Petkov 3865e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask) || 3866e1069839SBorislav Petkov cpuc->events[idx]->attr.exclude_host) 3867e1069839SBorislav Petkov continue; 3868e1069839SBorislav Petkov 3869e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3870e1069839SBorislav Petkov } 3871e1069839SBorislav Petkov } 3872e1069839SBorislav Petkov 3873e1069839SBorislav Petkov static int hsw_hw_config(struct perf_event *event) 3874e1069839SBorislav Petkov { 3875e1069839SBorislav Petkov int ret = intel_pmu_hw_config(event); 3876e1069839SBorislav Petkov 3877e1069839SBorislav Petkov if (ret) 3878e1069839SBorislav Petkov return ret; 3879e1069839SBorislav Petkov if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3880e1069839SBorislav Petkov return 0; 3881e1069839SBorislav Petkov event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3882e1069839SBorislav Petkov 3883e1069839SBorislav Petkov /* 3884e1069839SBorislav Petkov * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3885e1069839SBorislav Petkov * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3886e1069839SBorislav Petkov * this combination. 3887e1069839SBorislav Petkov */ 3888e1069839SBorislav Petkov if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3889e1069839SBorislav Petkov ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3890e1069839SBorislav Petkov event->attr.precise_ip > 0)) 3891e1069839SBorislav Petkov return -EOPNOTSUPP; 3892e1069839SBorislav Petkov 3893e1069839SBorislav Petkov if (event_is_checkpointed(event)) { 3894e1069839SBorislav Petkov /* 3895e1069839SBorislav Petkov * Sampling of checkpointed events can cause situations where 3896e1069839SBorislav Petkov * the CPU constantly aborts because of a overflow, which is 3897e1069839SBorislav Petkov * then checkpointed back and ignored. Forbid checkpointing 3898e1069839SBorislav Petkov * for sampling. 3899e1069839SBorislav Petkov * 3900e1069839SBorislav Petkov * But still allow a long sampling period, so that perf stat 3901e1069839SBorislav Petkov * from KVM works. 3902e1069839SBorislav Petkov */ 3903e1069839SBorislav Petkov if (event->attr.sample_period > 0 && 3904e1069839SBorislav Petkov event->attr.sample_period < 0x7fffffff) 3905e1069839SBorislav Petkov return -EOPNOTSUPP; 3906e1069839SBorislav Petkov } 3907e1069839SBorislav Petkov return 0; 3908e1069839SBorislav Petkov } 3909e1069839SBorislav Petkov 3910dd0b06b5SKan Liang static struct event_constraint counter0_constraint = 3911dd0b06b5SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3912dd0b06b5SKan Liang 3913e1069839SBorislav Petkov static struct event_constraint counter2_constraint = 3914e1069839SBorislav Petkov EVENT_CONSTRAINT(0, 0x4, 0); 3915e1069839SBorislav Petkov 391660176089SKan Liang static struct event_constraint fixed0_constraint = 391760176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0); 391860176089SKan Liang 39196daeb873SKan Liang static struct event_constraint fixed0_counter0_constraint = 39206daeb873SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 39216daeb873SKan Liang 3922e1069839SBorislav Petkov static struct event_constraint * 3923e1069839SBorislav Petkov hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3924e1069839SBorislav Petkov struct perf_event *event) 3925e1069839SBorislav Petkov { 3926e1069839SBorislav Petkov struct event_constraint *c; 3927e1069839SBorislav Petkov 3928e1069839SBorislav Petkov c = intel_get_event_constraints(cpuc, idx, event); 3929e1069839SBorislav Petkov 3930e1069839SBorislav Petkov /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3931e1069839SBorislav Petkov if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3932e1069839SBorislav Petkov if (c->idxmsk64 & (1U << 2)) 3933e1069839SBorislav Petkov return &counter2_constraint; 3934e1069839SBorislav Petkov return &emptyconstraint; 3935e1069839SBorislav Petkov } 3936e1069839SBorislav Petkov 3937e1069839SBorislav Petkov return c; 3938e1069839SBorislav Petkov } 3939e1069839SBorislav Petkov 3940dd0b06b5SKan Liang static struct event_constraint * 394160176089SKan Liang icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 394260176089SKan Liang struct perf_event *event) 394360176089SKan Liang { 394460176089SKan Liang /* 394560176089SKan Liang * Fixed counter 0 has less skid. 394660176089SKan Liang * Force instruction:ppp in Fixed counter 0 394760176089SKan Liang */ 394860176089SKan Liang if ((event->attr.precise_ip == 3) && 394960176089SKan Liang constraint_match(&fixed0_constraint, event->hw.config)) 395060176089SKan Liang return &fixed0_constraint; 395160176089SKan Liang 395260176089SKan Liang return hsw_get_event_constraints(cpuc, idx, event); 395360176089SKan Liang } 395460176089SKan Liang 395560176089SKan Liang static struct event_constraint * 3956*61b985e3SKan Liang spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3957*61b985e3SKan Liang struct perf_event *event) 3958*61b985e3SKan Liang { 3959*61b985e3SKan Liang struct event_constraint *c; 3960*61b985e3SKan Liang 3961*61b985e3SKan Liang c = icl_get_event_constraints(cpuc, idx, event); 3962*61b985e3SKan Liang 3963*61b985e3SKan Liang /* 3964*61b985e3SKan Liang * The :ppp indicates the Precise Distribution (PDist) facility, which 3965*61b985e3SKan Liang * is only supported on the GP counter 0. If a :ppp event which is not 3966*61b985e3SKan Liang * available on the GP counter 0, error out. 3967*61b985e3SKan Liang */ 3968*61b985e3SKan Liang if (event->attr.precise_ip == 3) { 3969*61b985e3SKan Liang if (c->idxmsk64 & BIT_ULL(0)) 3970*61b985e3SKan Liang return &counter0_constraint; 3971*61b985e3SKan Liang 3972*61b985e3SKan Liang return &emptyconstraint; 3973*61b985e3SKan Liang } 3974*61b985e3SKan Liang 3975*61b985e3SKan Liang return c; 3976*61b985e3SKan Liang } 3977*61b985e3SKan Liang 3978*61b985e3SKan Liang static struct event_constraint * 3979dd0b06b5SKan Liang glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3980dd0b06b5SKan Liang struct perf_event *event) 3981dd0b06b5SKan Liang { 3982dd0b06b5SKan Liang struct event_constraint *c; 3983dd0b06b5SKan Liang 3984dd0b06b5SKan Liang /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3985dd0b06b5SKan Liang if (event->attr.precise_ip == 3) 3986dd0b06b5SKan Liang return &counter0_constraint; 3987dd0b06b5SKan Liang 3988dd0b06b5SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 3989dd0b06b5SKan Liang 3990dd0b06b5SKan Liang return c; 3991dd0b06b5SKan Liang } 3992dd0b06b5SKan Liang 39936daeb873SKan Liang static struct event_constraint * 39946daeb873SKan Liang tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 39956daeb873SKan Liang struct perf_event *event) 39966daeb873SKan Liang { 39976daeb873SKan Liang struct event_constraint *c; 39986daeb873SKan Liang 39996daeb873SKan Liang /* 40006daeb873SKan Liang * :ppp means to do reduced skid PEBS, 40016daeb873SKan Liang * which is available on PMC0 and fixed counter 0. 40026daeb873SKan Liang */ 40036daeb873SKan Liang if (event->attr.precise_ip == 3) { 40046daeb873SKan Liang /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 40056daeb873SKan Liang if (constraint_match(&fixed0_constraint, event->hw.config)) 40066daeb873SKan Liang return &fixed0_counter0_constraint; 40076daeb873SKan Liang 40086daeb873SKan Liang return &counter0_constraint; 40096daeb873SKan Liang } 40106daeb873SKan Liang 40116daeb873SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 40126daeb873SKan Liang 40136daeb873SKan Liang return c; 40146daeb873SKan Liang } 40156daeb873SKan Liang 4016400816f6SPeter Zijlstra (Intel) static bool allow_tsx_force_abort = true; 4017400816f6SPeter Zijlstra (Intel) 4018400816f6SPeter Zijlstra (Intel) static struct event_constraint * 4019400816f6SPeter Zijlstra (Intel) tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4020400816f6SPeter Zijlstra (Intel) struct perf_event *event) 4021400816f6SPeter Zijlstra (Intel) { 4022400816f6SPeter Zijlstra (Intel) struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 4023400816f6SPeter Zijlstra (Intel) 4024400816f6SPeter Zijlstra (Intel) /* 4025400816f6SPeter Zijlstra (Intel) * Without TFA we must not use PMC3. 4026400816f6SPeter Zijlstra (Intel) */ 402721d65555SPeter Zijlstra if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 4028400816f6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 4029400816f6SPeter Zijlstra (Intel) c->idxmsk64 &= ~(1ULL << 3); 4030400816f6SPeter Zijlstra (Intel) c->weight--; 4031400816f6SPeter Zijlstra (Intel) } 4032400816f6SPeter Zijlstra (Intel) 4033400816f6SPeter Zijlstra (Intel) return c; 4034400816f6SPeter Zijlstra (Intel) } 4035400816f6SPeter Zijlstra (Intel) 4036e1069839SBorislav Petkov /* 4037e1069839SBorislav Petkov * Broadwell: 4038e1069839SBorislav Petkov * 4039e1069839SBorislav Petkov * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 4040e1069839SBorislav Petkov * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 4041e1069839SBorislav Petkov * the two to enforce a minimum period of 128 (the smallest value that has bits 4042e1069839SBorislav Petkov * 0-5 cleared and >= 100). 4043e1069839SBorislav Petkov * 4044e1069839SBorislav Petkov * Because of how the code in x86_perf_event_set_period() works, the truncation 4045e1069839SBorislav Petkov * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 4046e1069839SBorislav Petkov * to make up for the 'lost' events due to carrying the 'error' in period_left. 4047e1069839SBorislav Petkov * 4048e1069839SBorislav Petkov * Therefore the effective (average) period matches the requested period, 4049e1069839SBorislav Petkov * despite coarser hardware granularity. 4050e1069839SBorislav Petkov */ 4051f605cfcaSKan Liang static u64 bdw_limit_period(struct perf_event *event, u64 left) 4052e1069839SBorislav Petkov { 4053e1069839SBorislav Petkov if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 4054e1069839SBorislav Petkov X86_CONFIG(.event=0xc0, .umask=0x01)) { 4055e1069839SBorislav Petkov if (left < 128) 4056e1069839SBorislav Petkov left = 128; 4057e5ea9b54SDan Carpenter left &= ~0x3fULL; 4058e1069839SBorislav Petkov } 4059e1069839SBorislav Petkov return left; 4060e1069839SBorislav Petkov } 4061e1069839SBorislav Petkov 406244d3bbb6SJosh Hunt static u64 nhm_limit_period(struct perf_event *event, u64 left) 406344d3bbb6SJosh Hunt { 406444d3bbb6SJosh Hunt return max(left, 32ULL); 406544d3bbb6SJosh Hunt } 406644d3bbb6SJosh Hunt 4067*61b985e3SKan Liang static u64 spr_limit_period(struct perf_event *event, u64 left) 4068*61b985e3SKan Liang { 4069*61b985e3SKan Liang if (event->attr.precise_ip == 3) 4070*61b985e3SKan Liang return max(left, 128ULL); 4071*61b985e3SKan Liang 4072*61b985e3SKan Liang return left; 4073*61b985e3SKan Liang } 4074*61b985e3SKan Liang 4075e1069839SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 4076e1069839SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 4077e1069839SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 4078e1069839SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 4079e1069839SBorislav Petkov PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 4080e1069839SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 4081e1069839SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 4082e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx, "config:32"); 4083e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 4084e1069839SBorislav Petkov 4085e1069839SBorislav Petkov static struct attribute *intel_arch_formats_attr[] = { 4086e1069839SBorislav Petkov &format_attr_event.attr, 4087e1069839SBorislav Petkov &format_attr_umask.attr, 4088e1069839SBorislav Petkov &format_attr_edge.attr, 4089e1069839SBorislav Petkov &format_attr_pc.attr, 4090e1069839SBorislav Petkov &format_attr_inv.attr, 4091e1069839SBorislav Petkov &format_attr_cmask.attr, 4092e1069839SBorislav Petkov NULL, 4093e1069839SBorislav Petkov }; 4094e1069839SBorislav Petkov 4095e1069839SBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config) 4096e1069839SBorislav Petkov { 4097e1069839SBorislav Petkov u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 4098e1069839SBorislav Petkov 4099e1069839SBorislav Petkov return x86_event_sysfs_show(page, config, event); 4100e1069839SBorislav Petkov } 4101e1069839SBorislav Petkov 4102d01b1f96SPeter Zijlstra (Intel) static struct intel_shared_regs *allocate_shared_regs(int cpu) 4103e1069839SBorislav Petkov { 4104e1069839SBorislav Petkov struct intel_shared_regs *regs; 4105e1069839SBorislav Petkov int i; 4106e1069839SBorislav Petkov 4107e1069839SBorislav Petkov regs = kzalloc_node(sizeof(struct intel_shared_regs), 4108e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 4109e1069839SBorislav Petkov if (regs) { 4110e1069839SBorislav Petkov /* 4111e1069839SBorislav Petkov * initialize the locks to keep lockdep happy 4112e1069839SBorislav Petkov */ 4113e1069839SBorislav Petkov for (i = 0; i < EXTRA_REG_MAX; i++) 4114e1069839SBorislav Petkov raw_spin_lock_init(®s->regs[i].lock); 4115e1069839SBorislav Petkov 4116e1069839SBorislav Petkov regs->core_id = -1; 4117e1069839SBorislav Petkov } 4118e1069839SBorislav Petkov return regs; 4119e1069839SBorislav Petkov } 4120e1069839SBorislav Petkov 4121e1069839SBorislav Petkov static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4122e1069839SBorislav Petkov { 4123e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4124e1069839SBorislav Petkov 4125e1069839SBorislav Petkov c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4126e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 4127e1069839SBorislav Petkov if (c) { 4128e1069839SBorislav Petkov raw_spin_lock_init(&c->lock); 4129e1069839SBorislav Petkov c->core_id = -1; 4130e1069839SBorislav Petkov } 4131e1069839SBorislav Petkov return c; 4132e1069839SBorislav Petkov } 4133e1069839SBorislav Petkov 4134e1069839SBorislav Petkov 4135d01b1f96SPeter Zijlstra (Intel) int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4136d01b1f96SPeter Zijlstra (Intel) { 4137c22497f5SKan Liang cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4138c22497f5SKan Liang 4139e1069839SBorislav Petkov if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4140e1069839SBorislav Petkov cpuc->shared_regs = allocate_shared_regs(cpu); 4141e1069839SBorislav Petkov if (!cpuc->shared_regs) 4142e1069839SBorislav Petkov goto err; 4143e1069839SBorislav Petkov } 4144e1069839SBorislav Petkov 4145400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4146e1069839SBorislav Petkov size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4147e1069839SBorislav Petkov 4148d01b1f96SPeter Zijlstra (Intel) cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4149e1069839SBorislav Petkov if (!cpuc->constraint_list) 4150e1069839SBorislav Petkov goto err_shared_regs; 4151400816f6SPeter Zijlstra (Intel) } 4152e1069839SBorislav Petkov 4153400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4154e1069839SBorislav Petkov cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4155e1069839SBorislav Petkov if (!cpuc->excl_cntrs) 4156e1069839SBorislav Petkov goto err_constraint_list; 4157e1069839SBorislav Petkov 4158e1069839SBorislav Petkov cpuc->excl_thread_id = 0; 4159e1069839SBorislav Petkov } 4160e1069839SBorislav Petkov 416195ca792cSThomas Gleixner return 0; 4162e1069839SBorislav Petkov 4163e1069839SBorislav Petkov err_constraint_list: 4164e1069839SBorislav Petkov kfree(cpuc->constraint_list); 4165e1069839SBorislav Petkov cpuc->constraint_list = NULL; 4166e1069839SBorislav Petkov 4167e1069839SBorislav Petkov err_shared_regs: 4168e1069839SBorislav Petkov kfree(cpuc->shared_regs); 4169e1069839SBorislav Petkov cpuc->shared_regs = NULL; 4170e1069839SBorislav Petkov 4171e1069839SBorislav Petkov err: 417295ca792cSThomas Gleixner return -ENOMEM; 4173e1069839SBorislav Petkov } 4174e1069839SBorislav Petkov 4175d01b1f96SPeter Zijlstra (Intel) static int intel_pmu_cpu_prepare(int cpu) 4176d01b1f96SPeter Zijlstra (Intel) { 4177d01b1f96SPeter Zijlstra (Intel) return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4178d01b1f96SPeter Zijlstra (Intel) } 4179d01b1f96SPeter Zijlstra (Intel) 41806089327fSKan Liang static void flip_smm_bit(void *data) 41816089327fSKan Liang { 41826089327fSKan Liang unsigned long set = *(unsigned long *)data; 41836089327fSKan Liang 41846089327fSKan Liang if (set > 0) { 41856089327fSKan Liang msr_set_bit(MSR_IA32_DEBUGCTLMSR, 41866089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 41876089327fSKan Liang } else { 41886089327fSKan Liang msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 41896089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 41906089327fSKan Liang } 41916089327fSKan Liang } 41926089327fSKan Liang 4193e1069839SBorislav Petkov static void intel_pmu_cpu_starting(int cpu) 4194e1069839SBorislav Petkov { 4195e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4196e1069839SBorislav Petkov int core_id = topology_core_id(cpu); 4197e1069839SBorislav Petkov int i; 4198e1069839SBorislav Petkov 4199e1069839SBorislav Petkov init_debug_store_on_cpu(cpu); 4200e1069839SBorislav Petkov /* 4201e1069839SBorislav Petkov * Deal with CPUs that don't clear their LBRs on power-up. 4202e1069839SBorislav Petkov */ 4203e1069839SBorislav Petkov intel_pmu_lbr_reset(); 4204e1069839SBorislav Petkov 4205e1069839SBorislav Petkov cpuc->lbr_sel = NULL; 4206e1069839SBorislav Petkov 4207d7262457SPeter Zijlstra if (x86_pmu.flags & PMU_FL_TFA) { 4208d7262457SPeter Zijlstra WARN_ON_ONCE(cpuc->tfa_shadow); 4209d7262457SPeter Zijlstra cpuc->tfa_shadow = ~0ULL; 4210d7262457SPeter Zijlstra intel_set_tfa(cpuc, false); 4211d7262457SPeter Zijlstra } 4212d7262457SPeter Zijlstra 42134e949e9bSKan Liang if (x86_pmu.version > 1) 42146089327fSKan Liang flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 42156089327fSKan Liang 421680a5ce11SKan Liang /* Disable perf metrics if any added CPU doesn't support it. */ 421780a5ce11SKan Liang if (x86_pmu.intel_cap.perf_metrics) { 421880a5ce11SKan Liang union perf_capabilities perf_cap; 421980a5ce11SKan Liang 422080a5ce11SKan Liang rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 422180a5ce11SKan Liang if (!perf_cap.perf_metrics) { 422280a5ce11SKan Liang x86_pmu.intel_cap.perf_metrics = 0; 422380a5ce11SKan Liang x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 422480a5ce11SKan Liang } 422580a5ce11SKan Liang } 422680a5ce11SKan Liang 4227e1069839SBorislav Petkov if (!cpuc->shared_regs) 4228e1069839SBorislav Petkov return; 4229e1069839SBorislav Petkov 4230e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4231e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4232e1069839SBorislav Petkov struct intel_shared_regs *pc; 4233e1069839SBorislav Petkov 4234e1069839SBorislav Petkov pc = per_cpu(cpu_hw_events, i).shared_regs; 4235e1069839SBorislav Petkov if (pc && pc->core_id == core_id) { 4236e1069839SBorislav Petkov cpuc->kfree_on_online[0] = cpuc->shared_regs; 4237e1069839SBorislav Petkov cpuc->shared_regs = pc; 4238e1069839SBorislav Petkov break; 4239e1069839SBorislav Petkov } 4240e1069839SBorislav Petkov } 4241e1069839SBorislav Petkov cpuc->shared_regs->core_id = core_id; 4242e1069839SBorislav Petkov cpuc->shared_regs->refcnt++; 4243e1069839SBorislav Petkov } 4244e1069839SBorislav Petkov 4245e1069839SBorislav Petkov if (x86_pmu.lbr_sel_map) 4246e1069839SBorislav Petkov cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4247e1069839SBorislav Petkov 4248e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4249e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 42504e71de79SZhou Chengming struct cpu_hw_events *sibling; 4251e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4252e1069839SBorislav Petkov 42534e71de79SZhou Chengming sibling = &per_cpu(cpu_hw_events, i); 42544e71de79SZhou Chengming c = sibling->excl_cntrs; 4255e1069839SBorislav Petkov if (c && c->core_id == core_id) { 4256e1069839SBorislav Petkov cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4257e1069839SBorislav Petkov cpuc->excl_cntrs = c; 42584e71de79SZhou Chengming if (!sibling->excl_thread_id) 4259e1069839SBorislav Petkov cpuc->excl_thread_id = 1; 4260e1069839SBorislav Petkov break; 4261e1069839SBorislav Petkov } 4262e1069839SBorislav Petkov } 4263e1069839SBorislav Petkov cpuc->excl_cntrs->core_id = core_id; 4264e1069839SBorislav Petkov cpuc->excl_cntrs->refcnt++; 4265e1069839SBorislav Petkov } 4266e1069839SBorislav Petkov } 4267e1069839SBorislav Petkov 4268d01b1f96SPeter Zijlstra (Intel) static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4269e1069839SBorislav Petkov { 4270e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4271e1069839SBorislav Petkov 4272e1069839SBorislav Petkov c = cpuc->excl_cntrs; 4273e1069839SBorislav Petkov if (c) { 4274e1069839SBorislav Petkov if (c->core_id == -1 || --c->refcnt == 0) 4275e1069839SBorislav Petkov kfree(c); 4276e1069839SBorislav Petkov cpuc->excl_cntrs = NULL; 4277400816f6SPeter Zijlstra (Intel) } 4278400816f6SPeter Zijlstra (Intel) 4279e1069839SBorislav Petkov kfree(cpuc->constraint_list); 4280e1069839SBorislav Petkov cpuc->constraint_list = NULL; 4281e1069839SBorislav Petkov } 4282e1069839SBorislav Petkov 4283e1069839SBorislav Petkov static void intel_pmu_cpu_dying(int cpu) 4284e1069839SBorislav Petkov { 4285602cae04SPeter Zijlstra fini_debug_store_on_cpu(cpu); 4286602cae04SPeter Zijlstra } 4287602cae04SPeter Zijlstra 4288d01b1f96SPeter Zijlstra (Intel) void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4289602cae04SPeter Zijlstra { 4290e1069839SBorislav Petkov struct intel_shared_regs *pc; 4291e1069839SBorislav Petkov 4292e1069839SBorislav Petkov pc = cpuc->shared_regs; 4293e1069839SBorislav Petkov if (pc) { 4294e1069839SBorislav Petkov if (pc->core_id == -1 || --pc->refcnt == 0) 4295e1069839SBorislav Petkov kfree(pc); 4296e1069839SBorislav Petkov cpuc->shared_regs = NULL; 4297e1069839SBorislav Petkov } 4298e1069839SBorislav Petkov 4299d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(cpuc); 4300d01b1f96SPeter Zijlstra (Intel) } 4301d01b1f96SPeter Zijlstra (Intel) 4302d01b1f96SPeter Zijlstra (Intel) static void intel_pmu_cpu_dead(int cpu) 4303d01b1f96SPeter Zijlstra (Intel) { 4304d01b1f96SPeter Zijlstra (Intel) intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu)); 4305e1069839SBorislav Petkov } 4306e1069839SBorislav Petkov 4307e1069839SBorislav Petkov static void intel_pmu_sched_task(struct perf_event_context *ctx, 4308e1069839SBorislav Petkov bool sched_in) 4309e1069839SBorislav Petkov { 4310e1069839SBorislav Petkov intel_pmu_pebs_sched_task(ctx, sched_in); 4311e1069839SBorislav Petkov intel_pmu_lbr_sched_task(ctx, sched_in); 4312e1069839SBorislav Petkov } 4313e1069839SBorislav Petkov 4314c2b98a86SAlexey Budankov static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4315c2b98a86SAlexey Budankov struct perf_event_context *next) 4316c2b98a86SAlexey Budankov { 4317c2b98a86SAlexey Budankov intel_pmu_lbr_swap_task_ctx(prev, next); 4318c2b98a86SAlexey Budankov } 4319c2b98a86SAlexey Budankov 432081ec3f3cSJiri Olsa static int intel_pmu_check_period(struct perf_event *event, u64 value) 432181ec3f3cSJiri Olsa { 432281ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 432381ec3f3cSJiri Olsa } 432481ec3f3cSJiri Olsa 432542880f72SAlexander Shishkin static int intel_pmu_aux_output_match(struct perf_event *event) 432642880f72SAlexander Shishkin { 432742880f72SAlexander Shishkin if (!x86_pmu.intel_cap.pebs_output_pt_available) 432842880f72SAlexander Shishkin return 0; 432942880f72SAlexander Shishkin 433042880f72SAlexander Shishkin return is_intel_pt_event(event); 433142880f72SAlexander Shishkin } 433242880f72SAlexander Shishkin 4333e1069839SBorislav Petkov PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4334e1069839SBorislav Petkov 4335e1069839SBorislav Petkov PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4336e1069839SBorislav Petkov 4337e1069839SBorislav Petkov PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4338e1069839SBorislav Petkov 4339e1069839SBorislav Petkov static struct attribute *intel_arch3_formats_attr[] = { 4340e1069839SBorislav Petkov &format_attr_event.attr, 4341e1069839SBorislav Petkov &format_attr_umask.attr, 4342e1069839SBorislav Petkov &format_attr_edge.attr, 4343e1069839SBorislav Petkov &format_attr_pc.attr, 4344e1069839SBorislav Petkov &format_attr_any.attr, 4345e1069839SBorislav Petkov &format_attr_inv.attr, 4346e1069839SBorislav Petkov &format_attr_cmask.attr, 4347a5df70c3SAndi Kleen NULL, 4348a5df70c3SAndi Kleen }; 4349a5df70c3SAndi Kleen 4350a5df70c3SAndi Kleen static struct attribute *hsw_format_attr[] = { 4351e1069839SBorislav Petkov &format_attr_in_tx.attr, 4352e1069839SBorislav Petkov &format_attr_in_tx_cp.attr, 4353a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4354a5df70c3SAndi Kleen &format_attr_ldlat.attr, 4355a5df70c3SAndi Kleen NULL 4356a5df70c3SAndi Kleen }; 4357e1069839SBorislav Petkov 4358a5df70c3SAndi Kleen static struct attribute *nhm_format_attr[] = { 4359a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4360a5df70c3SAndi Kleen &format_attr_ldlat.attr, 4361a5df70c3SAndi Kleen NULL 4362a5df70c3SAndi Kleen }; 4363a5df70c3SAndi Kleen 4364a5df70c3SAndi Kleen static struct attribute *slm_format_attr[] = { 4365a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4366a5df70c3SAndi Kleen NULL 4367e1069839SBorislav Petkov }; 4368e1069839SBorislav Petkov 4369e1069839SBorislav Petkov static struct attribute *skl_format_attr[] = { 4370e1069839SBorislav Petkov &format_attr_frontend.attr, 4371e1069839SBorislav Petkov NULL, 4372e1069839SBorislav Petkov }; 4373e1069839SBorislav Petkov 4374e1069839SBorislav Petkov static __initconst const struct x86_pmu core_pmu = { 4375e1069839SBorislav Petkov .name = "core", 4376e1069839SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 4377e1069839SBorislav Petkov .disable_all = x86_pmu_disable_all, 4378e1069839SBorislav Petkov .enable_all = core_pmu_enable_all, 4379e1069839SBorislav Petkov .enable = core_pmu_enable_event, 4380e1069839SBorislav Petkov .disable = x86_pmu_disable_event, 4381ed6101bbSJiri Olsa .hw_config = core_pmu_hw_config, 4382e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 4383e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4384e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4385e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 4386e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4387e1069839SBorislav Petkov .apic = 1, 4388174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 4389e1069839SBorislav Petkov 4390e1069839SBorislav Petkov /* 4391e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32-bit width, 4392e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 4393e1069839SBorislav Petkov * the generic event period: 4394e1069839SBorislav Petkov */ 4395e1069839SBorislav Petkov .max_period = (1ULL<<31) - 1, 4396e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 4397e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 4398e1069839SBorislav Petkov .event_constraints = intel_core_event_constraints, 4399e1069839SBorislav Petkov .guest_get_msrs = core_guest_get_msrs, 4400e1069839SBorislav Petkov .format_attrs = intel_arch_formats_attr, 4401e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 4402e1069839SBorislav Petkov 4403e1069839SBorislav Petkov /* 4404e1069839SBorislav Petkov * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4405e1069839SBorislav Petkov * together with PMU version 1 and thus be using core_pmu with 4406e1069839SBorislav Petkov * shared_regs. We need following callbacks here to allocate 4407e1069839SBorislav Petkov * it properly. 4408e1069839SBorislav Petkov */ 4409e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 4410e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 4411e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 4412602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 441381ec3f3cSJiri Olsa 441481ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 44159f354a72SKan Liang 44169f354a72SKan Liang .lbr_reset = intel_pmu_lbr_reset_64, 4417c301b1d8SKan Liang .lbr_read = intel_pmu_lbr_read_64, 4418799571bfSKan Liang .lbr_save = intel_pmu_lbr_save, 4419799571bfSKan Liang .lbr_restore = intel_pmu_lbr_restore, 4420e1069839SBorislav Petkov }; 4421e1069839SBorislav Petkov 4422e1069839SBorislav Petkov static __initconst const struct x86_pmu intel_pmu = { 4423e1069839SBorislav Petkov .name = "Intel", 4424e1069839SBorislav Petkov .handle_irq = intel_pmu_handle_irq, 4425e1069839SBorislav Petkov .disable_all = intel_pmu_disable_all, 4426e1069839SBorislav Petkov .enable_all = intel_pmu_enable_all, 4427e1069839SBorislav Petkov .enable = intel_pmu_enable_event, 4428e1069839SBorislav Petkov .disable = intel_pmu_disable_event, 442968f7082fSPeter Zijlstra .add = intel_pmu_add_event, 443068f7082fSPeter Zijlstra .del = intel_pmu_del_event, 4431ceb90d9eSKan Liang .read = intel_pmu_read_event, 4432e1069839SBorislav Petkov .hw_config = intel_pmu_hw_config, 4433e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 4434e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4435e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4436e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 4437e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4438e1069839SBorislav Petkov .apic = 1, 4439174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 4440e1069839SBorislav Petkov /* 4441e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32 bit width, 4442e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 4443e1069839SBorislav Petkov * the generic event period: 4444e1069839SBorislav Petkov */ 4445e1069839SBorislav Petkov .max_period = (1ULL << 31) - 1, 4446e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 4447e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 4448e1069839SBorislav Petkov .pebs_aliases = intel_pebs_aliases_core2, 4449e1069839SBorislav Petkov 4450e1069839SBorislav Petkov .format_attrs = intel_arch3_formats_attr, 4451e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 4452e1069839SBorislav Petkov 4453e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 4454e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 4455e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 4456602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 4457602cae04SPeter Zijlstra 4458e1069839SBorislav Petkov .guest_get_msrs = intel_guest_get_msrs, 4459e1069839SBorislav Petkov .sched_task = intel_pmu_sched_task, 4460c2b98a86SAlexey Budankov .swap_task_ctx = intel_pmu_swap_task_ctx, 446181ec3f3cSJiri Olsa 446281ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 446342880f72SAlexander Shishkin 446442880f72SAlexander Shishkin .aux_output_match = intel_pmu_aux_output_match, 44659f354a72SKan Liang 44669f354a72SKan Liang .lbr_reset = intel_pmu_lbr_reset_64, 4467c301b1d8SKan Liang .lbr_read = intel_pmu_lbr_read_64, 4468799571bfSKan Liang .lbr_save = intel_pmu_lbr_save, 4469799571bfSKan Liang .lbr_restore = intel_pmu_lbr_restore, 4470e1069839SBorislav Petkov }; 4471e1069839SBorislav Petkov 4472e1069839SBorislav Petkov static __init void intel_clovertown_quirk(void) 4473e1069839SBorislav Petkov { 4474e1069839SBorislav Petkov /* 4475e1069839SBorislav Petkov * PEBS is unreliable due to: 4476e1069839SBorislav Petkov * 4477e1069839SBorislav Petkov * AJ67 - PEBS may experience CPL leaks 4478e1069839SBorislav Petkov * AJ68 - PEBS PMI may be delayed by one event 4479e1069839SBorislav Petkov * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4480e1069839SBorislav Petkov * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4481e1069839SBorislav Petkov * 4482e1069839SBorislav Petkov * AJ67 could be worked around by restricting the OS/USR flags. 4483e1069839SBorislav Petkov * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4484e1069839SBorislav Petkov * 4485e1069839SBorislav Petkov * AJ106 could possibly be worked around by not allowing LBR 4486e1069839SBorislav Petkov * usage from PEBS, including the fixup. 4487e1069839SBorislav Petkov * AJ68 could possibly be worked around by always programming 4488e1069839SBorislav Petkov * a pebs_event_reset[0] value and coping with the lost events. 4489e1069839SBorislav Petkov * 4490e1069839SBorislav Petkov * But taken together it might just make sense to not enable PEBS on 4491e1069839SBorislav Petkov * these chips. 4492e1069839SBorislav Petkov */ 4493e1069839SBorislav Petkov pr_warn("PEBS disabled due to CPU errata\n"); 4494e1069839SBorislav Petkov x86_pmu.pebs = 0; 4495e1069839SBorislav Petkov x86_pmu.pebs_constraints = NULL; 4496e1069839SBorislav Petkov } 4497e1069839SBorislav Petkov 44989b545c04SAndi Kleen static const struct x86_cpu_desc isolation_ucodes[] = { 4499c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4500af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 45015e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 45029b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 45039b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4504c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 45055e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 45065ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 45075ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 45085ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 45095ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 45109b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014), 45119b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 45129b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4513af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4514c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4515c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4516af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4517af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4518af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4519af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4520c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4521c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4522c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4523c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 45249b545c04SAndi Kleen {} 45259b545c04SAndi Kleen }; 45269b545c04SAndi Kleen 45279b545c04SAndi Kleen static void intel_check_pebs_isolation(void) 45289b545c04SAndi Kleen { 45299b545c04SAndi Kleen x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 45309b545c04SAndi Kleen } 45319b545c04SAndi Kleen 45329b545c04SAndi Kleen static __init void intel_pebs_isolation_quirk(void) 45339b545c04SAndi Kleen { 45349b545c04SAndi Kleen WARN_ON_ONCE(x86_pmu.check_microcode); 45359b545c04SAndi Kleen x86_pmu.check_microcode = intel_check_pebs_isolation; 45369b545c04SAndi Kleen intel_check_pebs_isolation(); 45379b545c04SAndi Kleen } 45389b545c04SAndi Kleen 4539a96fff8dSKan Liang static const struct x86_cpu_desc pebs_ucodes[] = { 4540a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4541a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4542a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4543a96fff8dSKan Liang {} 4544a96fff8dSKan Liang }; 4545a96fff8dSKan Liang 4546a96fff8dSKan Liang static bool intel_snb_pebs_broken(void) 4547e1069839SBorislav Petkov { 4548a96fff8dSKan Liang return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4549e1069839SBorislav Petkov } 4550e1069839SBorislav Petkov 4551e1069839SBorislav Petkov static void intel_snb_check_microcode(void) 4552e1069839SBorislav Petkov { 4553a96fff8dSKan Liang if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4554e1069839SBorislav Petkov return; 4555e1069839SBorislav Petkov 4556e1069839SBorislav Petkov /* 4557e1069839SBorislav Petkov * Serialized by the microcode lock.. 4558e1069839SBorislav Petkov */ 4559e1069839SBorislav Petkov if (x86_pmu.pebs_broken) { 4560e1069839SBorislav Petkov pr_info("PEBS enabled due to microcode update\n"); 4561e1069839SBorislav Petkov x86_pmu.pebs_broken = 0; 4562e1069839SBorislav Petkov } else { 4563e1069839SBorislav Petkov pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4564e1069839SBorislav Petkov x86_pmu.pebs_broken = 1; 4565e1069839SBorislav Petkov } 4566e1069839SBorislav Petkov } 4567e1069839SBorislav Petkov 456819fc9dddSDavid Carrillo-Cisneros static bool is_lbr_from(unsigned long msr) 456919fc9dddSDavid Carrillo-Cisneros { 457019fc9dddSDavid Carrillo-Cisneros unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 457119fc9dddSDavid Carrillo-Cisneros 457219fc9dddSDavid Carrillo-Cisneros return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 457319fc9dddSDavid Carrillo-Cisneros } 457419fc9dddSDavid Carrillo-Cisneros 4575e1069839SBorislav Petkov /* 4576e1069839SBorislav Petkov * Under certain circumstances, access certain MSR may cause #GP. 4577e1069839SBorislav Petkov * The function tests if the input MSR can be safely accessed. 4578e1069839SBorislav Petkov */ 4579e1069839SBorislav Petkov static bool check_msr(unsigned long msr, u64 mask) 4580e1069839SBorislav Petkov { 4581e1069839SBorislav Petkov u64 val_old, val_new, val_tmp; 4582e1069839SBorislav Petkov 4583e1069839SBorislav Petkov /* 4584d0e1a507SJiri Olsa * Disable the check for real HW, so we don't 4585d0e1a507SJiri Olsa * mess with potentionaly enabled registers: 4586d0e1a507SJiri Olsa */ 45875ea3f6fbSZhenzhong Duan if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4588d0e1a507SJiri Olsa return true; 4589d0e1a507SJiri Olsa 4590d0e1a507SJiri Olsa /* 4591e1069839SBorislav Petkov * Read the current value, change it and read it back to see if it 4592e1069839SBorislav Petkov * matches, this is needed to detect certain hardware emulators 4593e1069839SBorislav Petkov * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4594e1069839SBorislav Petkov */ 4595e1069839SBorislav Petkov if (rdmsrl_safe(msr, &val_old)) 4596e1069839SBorislav Petkov return false; 4597e1069839SBorislav Petkov 4598e1069839SBorislav Petkov /* 4599e1069839SBorislav Petkov * Only change the bits which can be updated by wrmsrl. 4600e1069839SBorislav Petkov */ 4601e1069839SBorislav Petkov val_tmp = val_old ^ mask; 460219fc9dddSDavid Carrillo-Cisneros 460319fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 460419fc9dddSDavid Carrillo-Cisneros val_tmp = lbr_from_signext_quirk_wr(val_tmp); 460519fc9dddSDavid Carrillo-Cisneros 4606e1069839SBorislav Petkov if (wrmsrl_safe(msr, val_tmp) || 4607e1069839SBorislav Petkov rdmsrl_safe(msr, &val_new)) 4608e1069839SBorislav Petkov return false; 4609e1069839SBorislav Petkov 461019fc9dddSDavid Carrillo-Cisneros /* 461119fc9dddSDavid Carrillo-Cisneros * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 461219fc9dddSDavid Carrillo-Cisneros * should equal rdmsrl()'s even with the quirk. 461319fc9dddSDavid Carrillo-Cisneros */ 4614e1069839SBorislav Petkov if (val_new != val_tmp) 4615e1069839SBorislav Petkov return false; 4616e1069839SBorislav Petkov 461719fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 461819fc9dddSDavid Carrillo-Cisneros val_old = lbr_from_signext_quirk_wr(val_old); 461919fc9dddSDavid Carrillo-Cisneros 4620e1069839SBorislav Petkov /* Here it's sure that the MSR can be safely accessed. 4621e1069839SBorislav Petkov * Restore the old value and return. 4622e1069839SBorislav Petkov */ 4623e1069839SBorislav Petkov wrmsrl(msr, val_old); 4624e1069839SBorislav Petkov 4625e1069839SBorislav Petkov return true; 4626e1069839SBorislav Petkov } 4627e1069839SBorislav Petkov 4628e1069839SBorislav Petkov static __init void intel_sandybridge_quirk(void) 4629e1069839SBorislav Petkov { 4630e1069839SBorislav Petkov x86_pmu.check_microcode = intel_snb_check_microcode; 46311ba143a5SSebastian Andrzej Siewior cpus_read_lock(); 4632e1069839SBorislav Petkov intel_snb_check_microcode(); 46331ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 4634e1069839SBorislav Petkov } 4635e1069839SBorislav Petkov 4636e1069839SBorislav Petkov static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4637e1069839SBorislav Petkov { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4638e1069839SBorislav Petkov { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4639e1069839SBorislav Petkov { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4640e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4641e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4642e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4643e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4644e1069839SBorislav Petkov }; 4645e1069839SBorislav Petkov 4646e1069839SBorislav Petkov static __init void intel_arch_events_quirk(void) 4647e1069839SBorislav Petkov { 4648e1069839SBorislav Petkov int bit; 4649e1069839SBorislav Petkov 4650e1069839SBorislav Petkov /* disable event that reported as not presend by cpuid */ 4651e1069839SBorislav Petkov for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4652e1069839SBorislav Petkov intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4653e1069839SBorislav Petkov pr_warn("CPUID marked event: \'%s\' unavailable\n", 4654e1069839SBorislav Petkov intel_arch_events_map[bit].name); 4655e1069839SBorislav Petkov } 4656e1069839SBorislav Petkov } 4657e1069839SBorislav Petkov 4658e1069839SBorislav Petkov static __init void intel_nehalem_quirk(void) 4659e1069839SBorislav Petkov { 4660e1069839SBorislav Petkov union cpuid10_ebx ebx; 4661e1069839SBorislav Petkov 4662e1069839SBorislav Petkov ebx.full = x86_pmu.events_maskl; 4663e1069839SBorislav Petkov if (ebx.split.no_branch_misses_retired) { 4664e1069839SBorislav Petkov /* 4665e1069839SBorislav Petkov * Erratum AAJ80 detected, we work it around by using 4666e1069839SBorislav Petkov * the BR_MISP_EXEC.ANY event. This will over-count 4667e1069839SBorislav Petkov * branch-misses, but it's still much better than the 4668e1069839SBorislav Petkov * architectural event which is often completely bogus: 4669e1069839SBorislav Petkov */ 4670e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4671e1069839SBorislav Petkov ebx.split.no_branch_misses_retired = 0; 4672e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4673e1069839SBorislav Petkov pr_info("CPU erratum AAJ80 worked around\n"); 4674e1069839SBorislav Petkov } 4675e1069839SBorislav Petkov } 4676e1069839SBorislav Petkov 4677e1069839SBorislav Petkov /* 4678e1069839SBorislav Petkov * enable software workaround for errata: 4679e1069839SBorislav Petkov * SNB: BJ122 4680e1069839SBorislav Petkov * IVB: BV98 4681e1069839SBorislav Petkov * HSW: HSD29 4682e1069839SBorislav Petkov * 4683e1069839SBorislav Petkov * Only needed when HT is enabled. However detecting 4684e1069839SBorislav Petkov * if HT is enabled is difficult (model specific). So instead, 4685e1069839SBorislav Petkov * we enable the workaround in the early boot, and verify if 4686e1069839SBorislav Petkov * it is needed in a later initcall phase once we have valid 4687e1069839SBorislav Petkov * topology information to check if HT is actually enabled 4688e1069839SBorislav Petkov */ 4689e1069839SBorislav Petkov static __init void intel_ht_bug(void) 4690e1069839SBorislav Petkov { 4691e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4692e1069839SBorislav Petkov 4693e1069839SBorislav Petkov x86_pmu.start_scheduling = intel_start_scheduling; 4694e1069839SBorislav Petkov x86_pmu.commit_scheduling = intel_commit_scheduling; 4695e1069839SBorislav Petkov x86_pmu.stop_scheduling = intel_stop_scheduling; 4696e1069839SBorislav Petkov } 4697e1069839SBorislav Petkov 4698e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4699e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4700e1069839SBorislav Petkov 4701e1069839SBorislav Petkov /* Haswell special events */ 4702e1069839SBorislav Petkov EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4703e1069839SBorislav Petkov EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4704e1069839SBorislav Petkov EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4705e1069839SBorislav Petkov EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4706e1069839SBorislav Petkov EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4707e1069839SBorislav Petkov EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4708e1069839SBorislav Petkov EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4709e1069839SBorislav Petkov EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4710e1069839SBorislav Petkov EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4711e1069839SBorislav Petkov EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4712e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4713e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4714e1069839SBorislav Petkov 4715e1069839SBorislav Petkov static struct attribute *hsw_events_attrs[] = { 471658ba4d5aSAndi Kleen EVENT_PTR(td_slots_issued), 471758ba4d5aSAndi Kleen EVENT_PTR(td_slots_retired), 471858ba4d5aSAndi Kleen EVENT_PTR(td_fetch_bubbles), 471958ba4d5aSAndi Kleen EVENT_PTR(td_total_slots), 472058ba4d5aSAndi Kleen EVENT_PTR(td_total_slots_scale), 472158ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles), 472258ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 472358ba4d5aSAndi Kleen NULL 472458ba4d5aSAndi Kleen }; 472558ba4d5aSAndi Kleen 4726d4ae5529SJiri Olsa static struct attribute *hsw_mem_events_attrs[] = { 4727d4ae5529SJiri Olsa EVENT_PTR(mem_ld_hsw), 4728d4ae5529SJiri Olsa EVENT_PTR(mem_st_hsw), 4729d4ae5529SJiri Olsa NULL, 4730d4ae5529SJiri Olsa }; 4731d4ae5529SJiri Olsa 473258ba4d5aSAndi Kleen static struct attribute *hsw_tsx_events_attrs[] = { 4733e1069839SBorislav Petkov EVENT_PTR(tx_start), 4734e1069839SBorislav Petkov EVENT_PTR(tx_commit), 4735e1069839SBorislav Petkov EVENT_PTR(tx_abort), 4736e1069839SBorislav Petkov EVENT_PTR(tx_capacity), 4737e1069839SBorislav Petkov EVENT_PTR(tx_conflict), 4738e1069839SBorislav Petkov EVENT_PTR(el_start), 4739e1069839SBorislav Petkov EVENT_PTR(el_commit), 4740e1069839SBorislav Petkov EVENT_PTR(el_abort), 4741e1069839SBorislav Petkov EVENT_PTR(el_capacity), 4742e1069839SBorislav Petkov EVENT_PTR(el_conflict), 4743e1069839SBorislav Petkov EVENT_PTR(cycles_t), 4744e1069839SBorislav Petkov EVENT_PTR(cycles_ct), 4745e1069839SBorislav Petkov NULL 4746e1069839SBorislav Petkov }; 4747e1069839SBorislav Petkov 474860176089SKan Liang EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 474960176089SKan Liang EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 475060176089SKan Liang EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 475160176089SKan Liang EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 475260176089SKan Liang 475360176089SKan Liang static struct attribute *icl_events_attrs[] = { 475460176089SKan Liang EVENT_PTR(mem_ld_hsw), 475560176089SKan Liang EVENT_PTR(mem_st_hsw), 475660176089SKan Liang NULL, 475760176089SKan Liang }; 475860176089SKan Liang 475959a854e2SKan Liang static struct attribute *icl_td_events_attrs[] = { 476059a854e2SKan Liang EVENT_PTR(slots), 476159a854e2SKan Liang EVENT_PTR(td_retiring), 476259a854e2SKan Liang EVENT_PTR(td_bad_spec), 476359a854e2SKan Liang EVENT_PTR(td_fe_bound), 476459a854e2SKan Liang EVENT_PTR(td_be_bound), 476559a854e2SKan Liang NULL, 476659a854e2SKan Liang }; 476759a854e2SKan Liang 476860176089SKan Liang static struct attribute *icl_tsx_events_attrs[] = { 476960176089SKan Liang EVENT_PTR(tx_start), 477060176089SKan Liang EVENT_PTR(tx_abort), 477160176089SKan Liang EVENT_PTR(tx_commit), 477260176089SKan Liang EVENT_PTR(tx_capacity_read), 477360176089SKan Liang EVENT_PTR(tx_capacity_write), 477460176089SKan Liang EVENT_PTR(tx_conflict), 477560176089SKan Liang EVENT_PTR(el_start), 477660176089SKan Liang EVENT_PTR(el_abort), 477760176089SKan Liang EVENT_PTR(el_commit), 477860176089SKan Liang EVENT_PTR(el_capacity_read), 477960176089SKan Liang EVENT_PTR(el_capacity_write), 478060176089SKan Liang EVENT_PTR(el_conflict), 478160176089SKan Liang EVENT_PTR(cycles_t), 478260176089SKan Liang EVENT_PTR(cycles_ct), 478360176089SKan Liang NULL, 478460176089SKan Liang }; 478560176089SKan Liang 4786*61b985e3SKan Liang 4787*61b985e3SKan Liang EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 4788*61b985e3SKan Liang EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 4789*61b985e3SKan Liang 4790*61b985e3SKan Liang static struct attribute *spr_events_attrs[] = { 4791*61b985e3SKan Liang EVENT_PTR(mem_ld_hsw), 4792*61b985e3SKan Liang EVENT_PTR(mem_st_spr), 4793*61b985e3SKan Liang EVENT_PTR(mem_ld_aux), 4794*61b985e3SKan Liang NULL, 4795*61b985e3SKan Liang }; 4796*61b985e3SKan Liang 4797*61b985e3SKan Liang static struct attribute *spr_td_events_attrs[] = { 4798*61b985e3SKan Liang EVENT_PTR(slots), 4799*61b985e3SKan Liang EVENT_PTR(td_retiring), 4800*61b985e3SKan Liang EVENT_PTR(td_bad_spec), 4801*61b985e3SKan Liang EVENT_PTR(td_fe_bound), 4802*61b985e3SKan Liang EVENT_PTR(td_be_bound), 4803*61b985e3SKan Liang EVENT_PTR(td_heavy_ops), 4804*61b985e3SKan Liang EVENT_PTR(td_br_mispredict), 4805*61b985e3SKan Liang EVENT_PTR(td_fetch_lat), 4806*61b985e3SKan Liang EVENT_PTR(td_mem_bound), 4807*61b985e3SKan Liang NULL, 4808*61b985e3SKan Liang }; 4809*61b985e3SKan Liang 4810*61b985e3SKan Liang static struct attribute *spr_tsx_events_attrs[] = { 4811*61b985e3SKan Liang EVENT_PTR(tx_start), 4812*61b985e3SKan Liang EVENT_PTR(tx_abort), 4813*61b985e3SKan Liang EVENT_PTR(tx_commit), 4814*61b985e3SKan Liang EVENT_PTR(tx_capacity_read), 4815*61b985e3SKan Liang EVENT_PTR(tx_capacity_write), 4816*61b985e3SKan Liang EVENT_PTR(tx_conflict), 4817*61b985e3SKan Liang EVENT_PTR(cycles_t), 4818*61b985e3SKan Liang EVENT_PTR(cycles_ct), 4819*61b985e3SKan Liang NULL, 4820*61b985e3SKan Liang }; 4821*61b985e3SKan Liang 48226089327fSKan Liang static ssize_t freeze_on_smi_show(struct device *cdev, 48236089327fSKan Liang struct device_attribute *attr, 48246089327fSKan Liang char *buf) 48256089327fSKan Liang { 48266089327fSKan Liang return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 48276089327fSKan Liang } 48286089327fSKan Liang 48296089327fSKan Liang static DEFINE_MUTEX(freeze_on_smi_mutex); 48306089327fSKan Liang 48316089327fSKan Liang static ssize_t freeze_on_smi_store(struct device *cdev, 48326089327fSKan Liang struct device_attribute *attr, 48336089327fSKan Liang const char *buf, size_t count) 48346089327fSKan Liang { 48356089327fSKan Liang unsigned long val; 48366089327fSKan Liang ssize_t ret; 48376089327fSKan Liang 48386089327fSKan Liang ret = kstrtoul(buf, 0, &val); 48396089327fSKan Liang if (ret) 48406089327fSKan Liang return ret; 48416089327fSKan Liang 48426089327fSKan Liang if (val > 1) 48436089327fSKan Liang return -EINVAL; 48446089327fSKan Liang 48456089327fSKan Liang mutex_lock(&freeze_on_smi_mutex); 48466089327fSKan Liang 48476089327fSKan Liang if (x86_pmu.attr_freeze_on_smi == val) 48486089327fSKan Liang goto done; 48496089327fSKan Liang 48506089327fSKan Liang x86_pmu.attr_freeze_on_smi = val; 48516089327fSKan Liang 48526089327fSKan Liang get_online_cpus(); 48536089327fSKan Liang on_each_cpu(flip_smm_bit, &val, 1); 48546089327fSKan Liang put_online_cpus(); 48556089327fSKan Liang done: 48566089327fSKan Liang mutex_unlock(&freeze_on_smi_mutex); 48576089327fSKan Liang 48586089327fSKan Liang return count; 48596089327fSKan Liang } 48606089327fSKan Liang 4861f447e4ebSStephane Eranian static void update_tfa_sched(void *ignored) 4862f447e4ebSStephane Eranian { 4863f447e4ebSStephane Eranian struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4864f447e4ebSStephane Eranian 4865f447e4ebSStephane Eranian /* 4866f447e4ebSStephane Eranian * check if PMC3 is used 4867f447e4ebSStephane Eranian * and if so force schedule out for all event types all contexts 4868f447e4ebSStephane Eranian */ 4869f447e4ebSStephane Eranian if (test_bit(3, cpuc->active_mask)) 4870f447e4ebSStephane Eranian perf_pmu_resched(x86_get_pmu()); 4871f447e4ebSStephane Eranian } 4872f447e4ebSStephane Eranian 4873f447e4ebSStephane Eranian static ssize_t show_sysctl_tfa(struct device *cdev, 4874f447e4ebSStephane Eranian struct device_attribute *attr, 4875f447e4ebSStephane Eranian char *buf) 4876f447e4ebSStephane Eranian { 4877f447e4ebSStephane Eranian return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 4878f447e4ebSStephane Eranian } 4879f447e4ebSStephane Eranian 4880f447e4ebSStephane Eranian static ssize_t set_sysctl_tfa(struct device *cdev, 4881f447e4ebSStephane Eranian struct device_attribute *attr, 4882f447e4ebSStephane Eranian const char *buf, size_t count) 4883f447e4ebSStephane Eranian { 4884f447e4ebSStephane Eranian bool val; 4885f447e4ebSStephane Eranian ssize_t ret; 4886f447e4ebSStephane Eranian 4887f447e4ebSStephane Eranian ret = kstrtobool(buf, &val); 4888f447e4ebSStephane Eranian if (ret) 4889f447e4ebSStephane Eranian return ret; 4890f447e4ebSStephane Eranian 4891f447e4ebSStephane Eranian /* no change */ 4892f447e4ebSStephane Eranian if (val == allow_tsx_force_abort) 4893f447e4ebSStephane Eranian return count; 4894f447e4ebSStephane Eranian 4895f447e4ebSStephane Eranian allow_tsx_force_abort = val; 4896f447e4ebSStephane Eranian 4897f447e4ebSStephane Eranian get_online_cpus(); 4898f447e4ebSStephane Eranian on_each_cpu(update_tfa_sched, NULL, 1); 4899f447e4ebSStephane Eranian put_online_cpus(); 4900f447e4ebSStephane Eranian 4901f447e4ebSStephane Eranian return count; 4902f447e4ebSStephane Eranian } 4903f447e4ebSStephane Eranian 4904f447e4ebSStephane Eranian 49056089327fSKan Liang static DEVICE_ATTR_RW(freeze_on_smi); 49066089327fSKan Liang 4907b00233b5SAndi Kleen static ssize_t branches_show(struct device *cdev, 4908b00233b5SAndi Kleen struct device_attribute *attr, 4909b00233b5SAndi Kleen char *buf) 4910b00233b5SAndi Kleen { 4911b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4912b00233b5SAndi Kleen } 4913b00233b5SAndi Kleen 4914b00233b5SAndi Kleen static DEVICE_ATTR_RO(branches); 4915b00233b5SAndi Kleen 4916b00233b5SAndi Kleen static struct attribute *lbr_attrs[] = { 4917b00233b5SAndi Kleen &dev_attr_branches.attr, 4918b00233b5SAndi Kleen NULL 4919b00233b5SAndi Kleen }; 4920b00233b5SAndi Kleen 4921b00233b5SAndi Kleen static char pmu_name_str[30]; 4922b00233b5SAndi Kleen 4923b00233b5SAndi Kleen static ssize_t pmu_name_show(struct device *cdev, 4924b00233b5SAndi Kleen struct device_attribute *attr, 4925b00233b5SAndi Kleen char *buf) 4926b00233b5SAndi Kleen { 4927b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4928b00233b5SAndi Kleen } 4929b00233b5SAndi Kleen 4930b00233b5SAndi Kleen static DEVICE_ATTR_RO(pmu_name); 4931b00233b5SAndi Kleen 4932b00233b5SAndi Kleen static struct attribute *intel_pmu_caps_attrs[] = { 4933b00233b5SAndi Kleen &dev_attr_pmu_name.attr, 4934b00233b5SAndi Kleen NULL 4935b00233b5SAndi Kleen }; 4936b00233b5SAndi Kleen 4937f447e4ebSStephane Eranian static DEVICE_ATTR(allow_tsx_force_abort, 0644, 4938f447e4ebSStephane Eranian show_sysctl_tfa, 4939f447e4ebSStephane Eranian set_sysctl_tfa); 4940400816f6SPeter Zijlstra (Intel) 49416089327fSKan Liang static struct attribute *intel_pmu_attrs[] = { 49426089327fSKan Liang &dev_attr_freeze_on_smi.attr, 4943b7c9b392SJiri Olsa &dev_attr_allow_tsx_force_abort.attr, 49446089327fSKan Liang NULL, 49456089327fSKan Liang }; 49466089327fSKan Liang 4947baa0c833SJiri Olsa static umode_t 4948baa0c833SJiri Olsa tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4949d4ae5529SJiri Olsa { 4950baa0c833SJiri Olsa return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 4951d4ae5529SJiri Olsa } 4952d4ae5529SJiri Olsa 4953baa0c833SJiri Olsa static umode_t 4954baa0c833SJiri Olsa pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4955baa0c833SJiri Olsa { 4956baa0c833SJiri Olsa return x86_pmu.pebs ? attr->mode : 0; 4957d4ae5529SJiri Olsa } 4958d4ae5529SJiri Olsa 49591f157286SJiri Olsa static umode_t 49601f157286SJiri Olsa lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 49611f157286SJiri Olsa { 49621f157286SJiri Olsa return x86_pmu.lbr_nr ? attr->mode : 0; 49631f157286SJiri Olsa } 49641f157286SJiri Olsa 49653ea40ac7SJiri Olsa static umode_t 49663ea40ac7SJiri Olsa exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 49673ea40ac7SJiri Olsa { 49683ea40ac7SJiri Olsa return x86_pmu.version >= 2 ? attr->mode : 0; 49693ea40ac7SJiri Olsa } 49703ea40ac7SJiri Olsa 4971b7c9b392SJiri Olsa static umode_t 4972b7c9b392SJiri Olsa default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4973b7c9b392SJiri Olsa { 4974b7c9b392SJiri Olsa if (attr == &dev_attr_allow_tsx_force_abort.attr) 4975b7c9b392SJiri Olsa return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 4976b7c9b392SJiri Olsa 4977b7c9b392SJiri Olsa return attr->mode; 4978b7c9b392SJiri Olsa } 4979b7c9b392SJiri Olsa 4980baa0c833SJiri Olsa static struct attribute_group group_events_td = { 4981baa0c833SJiri Olsa .name = "events", 4982baa0c833SJiri Olsa }; 4983baa0c833SJiri Olsa 4984baa0c833SJiri Olsa static struct attribute_group group_events_mem = { 4985baa0c833SJiri Olsa .name = "events", 4986baa0c833SJiri Olsa .is_visible = pebs_is_visible, 4987baa0c833SJiri Olsa }; 4988baa0c833SJiri Olsa 4989baa0c833SJiri Olsa static struct attribute_group group_events_tsx = { 4990baa0c833SJiri Olsa .name = "events", 4991baa0c833SJiri Olsa .is_visible = tsx_is_visible, 4992baa0c833SJiri Olsa }; 4993baa0c833SJiri Olsa 49941f157286SJiri Olsa static struct attribute_group group_caps_gen = { 49951f157286SJiri Olsa .name = "caps", 49961f157286SJiri Olsa .attrs = intel_pmu_caps_attrs, 49971f157286SJiri Olsa }; 49981f157286SJiri Olsa 49991f157286SJiri Olsa static struct attribute_group group_caps_lbr = { 50001f157286SJiri Olsa .name = "caps", 50011f157286SJiri Olsa .attrs = lbr_attrs, 50021f157286SJiri Olsa .is_visible = lbr_is_visible, 50031f157286SJiri Olsa }; 50041f157286SJiri Olsa 50053ea40ac7SJiri Olsa static struct attribute_group group_format_extra = { 50063ea40ac7SJiri Olsa .name = "format", 50073ea40ac7SJiri Olsa .is_visible = exra_is_visible, 50083ea40ac7SJiri Olsa }; 50093ea40ac7SJiri Olsa 5010b6576880SJiri Olsa static struct attribute_group group_format_extra_skl = { 5011b6576880SJiri Olsa .name = "format", 5012b6576880SJiri Olsa .is_visible = exra_is_visible, 5013b6576880SJiri Olsa }; 5014b6576880SJiri Olsa 50156a9f4efeSJiri Olsa static struct attribute_group group_default = { 50166a9f4efeSJiri Olsa .attrs = intel_pmu_attrs, 5017b7c9b392SJiri Olsa .is_visible = default_is_visible, 50186a9f4efeSJiri Olsa }; 50196a9f4efeSJiri Olsa 5020baa0c833SJiri Olsa static const struct attribute_group *attr_update[] = { 5021baa0c833SJiri Olsa &group_events_td, 5022baa0c833SJiri Olsa &group_events_mem, 5023baa0c833SJiri Olsa &group_events_tsx, 50241f157286SJiri Olsa &group_caps_gen, 50251f157286SJiri Olsa &group_caps_lbr, 50263ea40ac7SJiri Olsa &group_format_extra, 5027b6576880SJiri Olsa &group_format_extra_skl, 50286a9f4efeSJiri Olsa &group_default, 5029baa0c833SJiri Olsa NULL, 5030baa0c833SJiri Olsa }; 5031baa0c833SJiri Olsa 5032baa0c833SJiri Olsa static struct attribute *empty_attrs; 5033baa0c833SJiri Olsa 5034e1069839SBorislav Petkov __init int intel_pmu_init(void) 5035e1069839SBorislav Petkov { 5036b6576880SJiri Olsa struct attribute **extra_skl_attr = &empty_attrs; 5037baa0c833SJiri Olsa struct attribute **extra_attr = &empty_attrs; 5038baa0c833SJiri Olsa struct attribute **td_attr = &empty_attrs; 5039baa0c833SJiri Olsa struct attribute **mem_attr = &empty_attrs; 5040baa0c833SJiri Olsa struct attribute **tsx_attr = &empty_attrs; 5041e1069839SBorislav Petkov union cpuid10_edx edx; 5042e1069839SBorislav Petkov union cpuid10_eax eax; 5043e1069839SBorislav Petkov union cpuid10_ebx ebx; 5044e1069839SBorislav Petkov struct event_constraint *c; 5045e1069839SBorislav Petkov unsigned int unused; 5046e1069839SBorislav Petkov struct extra_reg *er; 5047faaeff98SKan Liang bool pmem = false; 5048e1069839SBorislav Petkov int version, i; 5049b00233b5SAndi Kleen char *name; 5050e1069839SBorislav Petkov 5051e1069839SBorislav Petkov if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 5052e1069839SBorislav Petkov switch (boot_cpu_data.x86) { 5053e1069839SBorislav Petkov case 0x6: 5054e1069839SBorislav Petkov return p6_pmu_init(); 5055e1069839SBorislav Petkov case 0xb: 5056e1069839SBorislav Petkov return knc_pmu_init(); 5057e1069839SBorislav Petkov case 0xf: 5058e1069839SBorislav Petkov return p4_pmu_init(); 5059e1069839SBorislav Petkov } 5060e1069839SBorislav Petkov return -ENODEV; 5061e1069839SBorislav Petkov } 5062e1069839SBorislav Petkov 5063e1069839SBorislav Petkov /* 5064e1069839SBorislav Petkov * Check whether the Architectural PerfMon supports 5065e1069839SBorislav Petkov * Branch Misses Retired hw_event or not. 5066e1069839SBorislav Petkov */ 5067e1069839SBorislav Petkov cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 5068e1069839SBorislav Petkov if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 5069e1069839SBorislav Petkov return -ENODEV; 5070e1069839SBorislav Petkov 5071e1069839SBorislav Petkov version = eax.split.version_id; 5072e1069839SBorislav Petkov if (version < 2) 5073e1069839SBorislav Petkov x86_pmu = core_pmu; 5074e1069839SBorislav Petkov else 5075e1069839SBorislav Petkov x86_pmu = intel_pmu; 5076e1069839SBorislav Petkov 5077e1069839SBorislav Petkov x86_pmu.version = version; 5078e1069839SBorislav Petkov x86_pmu.num_counters = eax.split.num_counters; 5079e1069839SBorislav Petkov x86_pmu.cntval_bits = eax.split.bit_width; 5080e1069839SBorislav Petkov x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 5081e1069839SBorislav Petkov 5082e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 5083e1069839SBorislav Petkov x86_pmu.events_mask_len = eax.split.mask_length; 5084e1069839SBorislav Petkov 5085e1069839SBorislav Petkov x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 5086e1069839SBorislav Petkov 5087e1069839SBorislav Petkov /* 5088e1069839SBorislav Petkov * Quirk: v2 perfmon does not report fixed-purpose events, so 5089f92b7604SImre Palik * assume at least 3 events, when not running in a hypervisor: 5090e1069839SBorislav Petkov */ 5091f92b7604SImre Palik if (version > 1) { 5092f92b7604SImre Palik int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 5093f92b7604SImre Palik 5094f92b7604SImre Palik x86_pmu.num_counters_fixed = 5095f92b7604SImre Palik max((int)edx.split.num_counters_fixed, assume); 5096f92b7604SImre Palik } 5097e1069839SBorislav Petkov 5098e1069839SBorislav Petkov if (boot_cpu_has(X86_FEATURE_PDCM)) { 5099e1069839SBorislav Petkov u64 capabilities; 5100e1069839SBorislav Petkov 5101e1069839SBorislav Petkov rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 5102e1069839SBorislav Petkov x86_pmu.intel_cap.capabilities = capabilities; 5103e1069839SBorislav Petkov } 5104e1069839SBorislav Petkov 5105c301b1d8SKan Liang if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 51069f354a72SKan Liang x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 5107c301b1d8SKan Liang x86_pmu.lbr_read = intel_pmu_lbr_read_32; 5108c301b1d8SKan Liang } 51099f354a72SKan Liang 511047125db2SKan Liang if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 511147125db2SKan Liang intel_pmu_arch_lbr_init(); 511247125db2SKan Liang 5113e1069839SBorislav Petkov intel_ds_init(); 5114e1069839SBorislav Petkov 5115e1069839SBorislav Petkov x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5116e1069839SBorislav Petkov 5117cadbaa03SStephane Eranian if (version >= 5) { 5118cadbaa03SStephane Eranian x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5119cadbaa03SStephane Eranian if (x86_pmu.intel_cap.anythread_deprecated) 5120cadbaa03SStephane Eranian pr_cont(" AnyThread deprecated, "); 5121cadbaa03SStephane Eranian } 5122cadbaa03SStephane Eranian 5123e1069839SBorislav Petkov /* 5124e1069839SBorislav Petkov * Install the hw-cache-events table: 5125e1069839SBorislav Petkov */ 5126e1069839SBorislav Petkov switch (boot_cpu_data.x86_model) { 5127ef5f9f47SDave Hansen case INTEL_FAM6_CORE_YONAH: 5128e1069839SBorislav Petkov pr_cont("Core events, "); 5129b00233b5SAndi Kleen name = "core"; 5130e1069839SBorislav Petkov break; 5131e1069839SBorislav Petkov 5132ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM: 5133e1069839SBorislav Petkov x86_add_quirk(intel_clovertown_quirk); 5134df561f66SGustavo A. R. Silva fallthrough; 51352b0fc374SGustavo A. R. Silva 5136ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM_L: 5137ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_PENRYN: 5138ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_DUNNINGTON: 5139e1069839SBorislav Petkov memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5140e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5141e1069839SBorislav Petkov 5142e1069839SBorislav Petkov intel_pmu_lbr_init_core(); 5143e1069839SBorislav Petkov 5144e1069839SBorislav Petkov x86_pmu.event_constraints = intel_core2_event_constraints; 5145e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5146e1069839SBorislav Petkov pr_cont("Core2 events, "); 5147b00233b5SAndi Kleen name = "core2"; 5148e1069839SBorislav Petkov break; 5149e1069839SBorislav Petkov 5150ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM: 5151ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EP: 5152ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EX: 5153e1069839SBorislav Petkov memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5154e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5155e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5156e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5157e1069839SBorislav Petkov 5158e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 5159e1069839SBorislav Petkov 5160e1069839SBorislav Petkov x86_pmu.event_constraints = intel_nehalem_event_constraints; 5161e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5162e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5163e1069839SBorislav Petkov x86_pmu.extra_regs = intel_nehalem_extra_regs; 516444d3bbb6SJosh Hunt x86_pmu.limit_period = nhm_limit_period; 5165e1069839SBorislav Petkov 5166d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 5167e1069839SBorislav Petkov 5168e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 5169e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5170e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5171e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5172e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5173e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5174e1069839SBorislav Petkov 5175e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 5176e1069839SBorislav Petkov x86_add_quirk(intel_nehalem_quirk); 517795298355SAndi Kleen x86_pmu.pebs_no_tlb = 1; 5178a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5179e1069839SBorislav Petkov 5180e1069839SBorislav Petkov pr_cont("Nehalem events, "); 5181b00233b5SAndi Kleen name = "nehalem"; 5182e1069839SBorislav Petkov break; 5183e1069839SBorislav Petkov 5184f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL: 5185f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL_MID: 5186f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL: 5187f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_MID: 5188f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5189e1069839SBorislav Petkov memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5190e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5191e1069839SBorislav Petkov 5192e1069839SBorislav Petkov intel_pmu_lbr_init_atom(); 5193e1069839SBorislav Petkov 5194e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 5195e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5196e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5197e1069839SBorislav Petkov pr_cont("Atom events, "); 5198b00233b5SAndi Kleen name = "bonnell"; 5199e1069839SBorislav Petkov break; 5200e1069839SBorislav Petkov 5201f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT: 52025ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_D: 5203f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_MID: 5204ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_AIRMONT: 5205f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_AIRMONT_MID: 5206e1069839SBorislav Petkov memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5207e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5208e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5209e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5210e1069839SBorislav Petkov 5211f21d5adcSKan Liang intel_pmu_lbr_init_slm(); 5212e1069839SBorislav Petkov 5213e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 5214e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5215e1069839SBorislav Petkov x86_pmu.extra_regs = intel_slm_extra_regs; 5216e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5217baa0c833SJiri Olsa td_attr = slm_events_attrs; 5218a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5219e1069839SBorislav Petkov pr_cont("Silvermont events, "); 5220b00233b5SAndi Kleen name = "silvermont"; 5221e1069839SBorislav Petkov break; 5222e1069839SBorislav Petkov 5223ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_GOLDMONT: 52245ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_D: 52258b92c3a7SKan Liang memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 52268b92c3a7SKan Liang sizeof(hw_cache_event_ids)); 52278b92c3a7SKan Liang memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 52288b92c3a7SKan Liang sizeof(hw_cache_extra_regs)); 52298b92c3a7SKan Liang 52308b92c3a7SKan Liang intel_pmu_lbr_init_skl(); 52318b92c3a7SKan Liang 52328b92c3a7SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 52338b92c3a7SKan Liang x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 52348b92c3a7SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 52358b92c3a7SKan Liang /* 52368b92c3a7SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 52378b92c3a7SKan Liang * for precise cycles. 52388b92c3a7SKan Liang * :pp is identical to :ppp 52398b92c3a7SKan Liang */ 52408b92c3a7SKan Liang x86_pmu.pebs_aliases = NULL; 52418b92c3a7SKan Liang x86_pmu.pebs_prec_dist = true; 5242ccbebba4SAlexander Shishkin x86_pmu.lbr_pt_coexist = true; 52438b92c3a7SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5244baa0c833SJiri Olsa td_attr = glm_events_attrs; 5245a5df70c3SAndi Kleen extra_attr = slm_format_attr; 52468b92c3a7SKan Liang pr_cont("Goldmont events, "); 5247b00233b5SAndi Kleen name = "goldmont"; 52488b92c3a7SKan Liang break; 52498b92c3a7SKan Liang 5250f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5251dd0b06b5SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5252dd0b06b5SKan Liang sizeof(hw_cache_event_ids)); 5253dd0b06b5SKan Liang memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5254dd0b06b5SKan Liang sizeof(hw_cache_extra_regs)); 5255dd0b06b5SKan Liang 5256dd0b06b5SKan Liang intel_pmu_lbr_init_skl(); 5257dd0b06b5SKan Liang 5258dd0b06b5SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 5259dd0b06b5SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 5260dd0b06b5SKan Liang /* 5261dd0b06b5SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5262dd0b06b5SKan Liang * for precise cycles. 5263dd0b06b5SKan Liang */ 5264dd0b06b5SKan Liang x86_pmu.pebs_aliases = NULL; 5265dd0b06b5SKan Liang x86_pmu.pebs_prec_dist = true; 5266dd0b06b5SKan Liang x86_pmu.lbr_pt_coexist = true; 5267dd0b06b5SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5268a38b0ba1SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 5269dd0b06b5SKan Liang x86_pmu.get_event_constraints = glp_get_event_constraints; 5270baa0c833SJiri Olsa td_attr = glm_events_attrs; 5271dd0b06b5SKan Liang /* Goldmont Plus has 4-wide pipeline */ 5272dd0b06b5SKan Liang event_attr_td_total_slots_scale_glm.event_str = "4"; 5273a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5274dd0b06b5SKan Liang pr_cont("Goldmont plus events, "); 5275b00233b5SAndi Kleen name = "goldmont_plus"; 5276dd0b06b5SKan Liang break; 5277dd0b06b5SKan Liang 52785ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_TREMONT_D: 5279eda23b38SKan Liang case INTEL_FAM6_ATOM_TREMONT: 5280dbfd6388SKan Liang case INTEL_FAM6_ATOM_TREMONT_L: 52816daeb873SKan Liang x86_pmu.late_ack = true; 52826daeb873SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 52836daeb873SKan Liang sizeof(hw_cache_event_ids)); 52846daeb873SKan Liang memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 52856daeb873SKan Liang sizeof(hw_cache_extra_regs)); 52866daeb873SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 52876daeb873SKan Liang 52886daeb873SKan Liang intel_pmu_lbr_init_skl(); 52896daeb873SKan Liang 52906daeb873SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 52916daeb873SKan Liang x86_pmu.extra_regs = intel_tnt_extra_regs; 52926daeb873SKan Liang /* 52936daeb873SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 52946daeb873SKan Liang * for precise cycles. 52956daeb873SKan Liang */ 52966daeb873SKan Liang x86_pmu.pebs_aliases = NULL; 52976daeb873SKan Liang x86_pmu.pebs_prec_dist = true; 52986daeb873SKan Liang x86_pmu.lbr_pt_coexist = true; 52996daeb873SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 53006daeb873SKan Liang x86_pmu.get_event_constraints = tnt_get_event_constraints; 5301c2208046SKan Liang td_attr = tnt_events_attrs; 53026daeb873SKan Liang extra_attr = slm_format_attr; 53036daeb873SKan Liang pr_cont("Tremont events, "); 53046daeb873SKan Liang name = "Tremont"; 53056daeb873SKan Liang break; 53066daeb873SKan Liang 5307ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE: 5308ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EP: 5309ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EX: 5310e1069839SBorislav Petkov memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5311e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5312e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5313e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5314e1069839SBorislav Petkov 5315e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 5316e1069839SBorislav Petkov 5317e1069839SBorislav Petkov x86_pmu.event_constraints = intel_westmere_event_constraints; 5318e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5319e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5320e1069839SBorislav Petkov x86_pmu.extra_regs = intel_westmere_extra_regs; 5321e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5322e1069839SBorislav Petkov 5323d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 5324e1069839SBorislav Petkov 5325e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 5326e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5327e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5328e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5329e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5330e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5331e1069839SBorislav Petkov 5332e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 5333a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5334e1069839SBorislav Petkov pr_cont("Westmere events, "); 5335b00233b5SAndi Kleen name = "westmere"; 5336e1069839SBorislav Petkov break; 5337e1069839SBorislav Petkov 5338ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 5339ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 5340e1069839SBorislav Petkov x86_add_quirk(intel_sandybridge_quirk); 5341e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 5342e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5343e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5344e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5345e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5346e1069839SBorislav Petkov 5347e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 5348e1069839SBorislav Petkov 5349e1069839SBorislav Petkov x86_pmu.event_constraints = intel_snb_event_constraints; 5350e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5351e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5352ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5353e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5354e1069839SBorislav Petkov else 5355e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 5356e1069839SBorislav Petkov 5357e1069839SBorislav Petkov 5358e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5359e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5360e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5361e1069839SBorislav Petkov 5362baa0c833SJiri Olsa td_attr = snb_events_attrs; 5363d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 5364e1069839SBorislav Petkov 5365e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5366e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5367e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5368e1069839SBorislav Petkov /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5369e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5370e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5371e1069839SBorislav Petkov 5372a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5373a5df70c3SAndi Kleen 5374e1069839SBorislav Petkov pr_cont("SandyBridge events, "); 5375b00233b5SAndi Kleen name = "sandybridge"; 5376e1069839SBorislav Petkov break; 5377e1069839SBorislav Petkov 5378ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE: 5379ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE_X: 5380e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 5381e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5382e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5383e1069839SBorislav Petkov /* dTLB-load-misses on IVB is different than SNB */ 5384e1069839SBorislav Petkov hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5385e1069839SBorislav Petkov 5386e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5387e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5388e1069839SBorislav Petkov 5389e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 5390e1069839SBorislav Petkov 5391e1069839SBorislav Petkov x86_pmu.event_constraints = intel_ivb_event_constraints; 5392e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5393e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5394e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5395ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5396e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5397e1069839SBorislav Petkov else 5398e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 5399e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5400e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5401e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5402e1069839SBorislav Petkov 5403baa0c833SJiri Olsa td_attr = snb_events_attrs; 5404d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 5405e1069839SBorislav Petkov 5406e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5407e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5408e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5409e1069839SBorislav Petkov 5410a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5411a5df70c3SAndi Kleen 5412e1069839SBorislav Petkov pr_cont("IvyBridge events, "); 5413b00233b5SAndi Kleen name = "ivybridge"; 5414e1069839SBorislav Petkov break; 5415e1069839SBorislav Petkov 5416e1069839SBorislav Petkov 5417c66f78a6SPeter Zijlstra case INTEL_FAM6_HASWELL: 5418ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_X: 5419af239c44SPeter Zijlstra case INTEL_FAM6_HASWELL_L: 54205e741407SPeter Zijlstra case INTEL_FAM6_HASWELL_G: 5421e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 54229b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5423e1069839SBorislav Petkov x86_pmu.late_ack = true; 5424e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5425e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5426e1069839SBorislav Petkov 5427e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 5428e1069839SBorislav Petkov 5429e1069839SBorislav Petkov x86_pmu.event_constraints = intel_hsw_event_constraints; 5430e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5431e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5432e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5433e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5434e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5435e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5436e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5437e1069839SBorislav Petkov 5438e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5439e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5440e1069839SBorislav Petkov x86_pmu.lbr_double_abort = true; 5441a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5442a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5443baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5444d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5445d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5446e1069839SBorislav Petkov pr_cont("Haswell events, "); 5447b00233b5SAndi Kleen name = "haswell"; 5448e1069839SBorislav Petkov break; 5449e1069839SBorislav Petkov 5450c66f78a6SPeter Zijlstra case INTEL_FAM6_BROADWELL: 54515ebb34edSPeter Zijlstra case INTEL_FAM6_BROADWELL_D: 54525e741407SPeter Zijlstra case INTEL_FAM6_BROADWELL_G: 5453ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_X: 54549b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5455e1069839SBorislav Petkov x86_pmu.late_ack = true; 5456e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5457e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5458e1069839SBorislav Petkov 5459e1069839SBorislav Petkov /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5460e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5461e1069839SBorislav Petkov BDW_L3_MISS|HSW_SNOOP_DRAM; 5462e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 5463e1069839SBorislav Petkov HSW_SNOOP_DRAM; 5464e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 5465e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5466e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 5467e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5468e1069839SBorislav Petkov 5469e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 5470e1069839SBorislav Petkov 5471e1069839SBorislav Petkov x86_pmu.event_constraints = intel_bdw_event_constraints; 5472b3e62463SStephane Eranian x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 5473e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5474e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5475e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5476e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5477e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5478e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5479e1069839SBorislav Petkov 5480e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5481e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5482e1069839SBorislav Petkov x86_pmu.limit_period = bdw_limit_period; 5483a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5484a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5485baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5486d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5487d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5488e1069839SBorislav Petkov pr_cont("Broadwell events, "); 5489b00233b5SAndi Kleen name = "broadwell"; 5490e1069839SBorislav Petkov break; 5491e1069839SBorislav Petkov 5492ef5f9f47SDave Hansen case INTEL_FAM6_XEON_PHI_KNL: 5493608284bfSPiotr Luc case INTEL_FAM6_XEON_PHI_KNM: 5494e1069839SBorislav Petkov memcpy(hw_cache_event_ids, 5495e1069839SBorislav Petkov slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5496e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, 5497e1069839SBorislav Petkov knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5498e1069839SBorislav Petkov intel_pmu_lbr_init_knl(); 5499e1069839SBorislav Petkov 5500e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 5501e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5502e1069839SBorislav Petkov x86_pmu.extra_regs = intel_knl_extra_regs; 5503e1069839SBorislav Petkov 5504e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5505e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5506e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5507a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5508608284bfSPiotr Luc pr_cont("Knights Landing/Mill events, "); 5509b00233b5SAndi Kleen name = "knights-landing"; 5510e1069839SBorislav Petkov break; 5511e1069839SBorislav Petkov 5512faaeff98SKan Liang case INTEL_FAM6_SKYLAKE_X: 5513faaeff98SKan Liang pmem = true; 5514df561f66SGustavo A. R. Silva fallthrough; 5515af239c44SPeter Zijlstra case INTEL_FAM6_SKYLAKE_L: 5516c66f78a6SPeter Zijlstra case INTEL_FAM6_SKYLAKE: 5517af239c44SPeter Zijlstra case INTEL_FAM6_KABYLAKE_L: 5518c66f78a6SPeter Zijlstra case INTEL_FAM6_KABYLAKE: 55199066288bSKan Liang case INTEL_FAM6_COMETLAKE_L: 55209066288bSKan Liang case INTEL_FAM6_COMETLAKE: 55219b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5522e1069839SBorislav Petkov x86_pmu.late_ack = true; 5523e1069839SBorislav Petkov memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5524e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5525e1069839SBorislav Petkov intel_pmu_lbr_init_skl(); 5526e1069839SBorislav Petkov 5527a39fcae7SAndi Kleen /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 5528a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_noht = 5529a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1"; 5530a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_ht = 5531a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1,any=1"; 5532a39fcae7SAndi Kleen 5533e1069839SBorislav Petkov x86_pmu.event_constraints = intel_skl_event_constraints; 5534e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 5535e1069839SBorislav Petkov x86_pmu.extra_regs = intel_skl_extra_regs; 5536e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 5537e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5538e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5539e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5540e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5541e1069839SBorislav Petkov 5542e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5543e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5544a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5545a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5546b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 5547baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5548d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5549d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5550faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 5551400816f6SPeter Zijlstra (Intel) 5552400816f6SPeter Zijlstra (Intel) if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 5553400816f6SPeter Zijlstra (Intel) x86_pmu.flags |= PMU_FL_TFA; 5554400816f6SPeter Zijlstra (Intel) x86_pmu.get_event_constraints = tfa_get_event_constraints; 5555400816f6SPeter Zijlstra (Intel) x86_pmu.enable_all = intel_tfa_pmu_enable_all; 5556400816f6SPeter Zijlstra (Intel) x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 5557400816f6SPeter Zijlstra (Intel) } 5558400816f6SPeter Zijlstra (Intel) 5559e1069839SBorislav Petkov pr_cont("Skylake events, "); 5560b00233b5SAndi Kleen name = "skylake"; 5561e1069839SBorislav Petkov break; 5562e1069839SBorislav Petkov 5563faaeff98SKan Liang case INTEL_FAM6_ICELAKE_X: 55645ebb34edSPeter Zijlstra case INTEL_FAM6_ICELAKE_D: 5565faaeff98SKan Liang pmem = true; 5566df561f66SGustavo A. R. Silva fallthrough; 5567af239c44SPeter Zijlstra case INTEL_FAM6_ICELAKE_L: 5568c66f78a6SPeter Zijlstra case INTEL_FAM6_ICELAKE: 556923645a76SKan Liang case INTEL_FAM6_TIGERLAKE_L: 557023645a76SKan Liang case INTEL_FAM6_TIGERLAKE: 5571b14d0db5SKan Liang case INTEL_FAM6_ROCKETLAKE: 557260176089SKan Liang x86_pmu.late_ack = true; 557360176089SKan Liang memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 557460176089SKan Liang memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 557560176089SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 557660176089SKan Liang intel_pmu_lbr_init_skl(); 557760176089SKan Liang 557860176089SKan Liang x86_pmu.event_constraints = intel_icl_event_constraints; 557960176089SKan Liang x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 558060176089SKan Liang x86_pmu.extra_regs = intel_icl_extra_regs; 558160176089SKan Liang x86_pmu.pebs_aliases = NULL; 558260176089SKan Liang x86_pmu.pebs_prec_dist = true; 558360176089SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 558460176089SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 558560176089SKan Liang 558660176089SKan Liang x86_pmu.hw_config = hsw_hw_config; 558760176089SKan Liang x86_pmu.get_event_constraints = icl_get_event_constraints; 558860176089SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 558960176089SKan Liang hsw_format_attr : nhm_format_attr; 5590b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 5591baa0c833SJiri Olsa mem_attr = icl_events_attrs; 559259a854e2SKan Liang td_attr = icl_td_events_attrs; 5593baa0c833SJiri Olsa tsx_attr = icl_tsx_events_attrs; 559446b72e1bSKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 559560176089SKan Liang x86_pmu.lbr_pt_coexist = true; 5596faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 55971ab5f235SKan Liang x86_pmu.num_topdown_events = 4; 559859a854e2SKan Liang x86_pmu.update_topdown_event = icl_update_topdown_event; 559959a854e2SKan Liang x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 560060176089SKan Liang pr_cont("Icelake events, "); 560160176089SKan Liang name = "icelake"; 560260176089SKan Liang break; 560360176089SKan Liang 5604*61b985e3SKan Liang case INTEL_FAM6_SAPPHIRERAPIDS_X: 5605*61b985e3SKan Liang pmem = true; 5606*61b985e3SKan Liang x86_pmu.late_ack = true; 5607*61b985e3SKan Liang memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5608*61b985e3SKan Liang memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5609*61b985e3SKan Liang 5610*61b985e3SKan Liang x86_pmu.event_constraints = intel_spr_event_constraints; 5611*61b985e3SKan Liang x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; 5612*61b985e3SKan Liang x86_pmu.extra_regs = intel_spr_extra_regs; 5613*61b985e3SKan Liang x86_pmu.limit_period = spr_limit_period; 5614*61b985e3SKan Liang x86_pmu.pebs_aliases = NULL; 5615*61b985e3SKan Liang x86_pmu.pebs_prec_dist = true; 5616*61b985e3SKan Liang x86_pmu.pebs_block = true; 5617*61b985e3SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5618*61b985e3SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5619*61b985e3SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 5620*61b985e3SKan Liang x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 5621*61b985e3SKan Liang x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 5622*61b985e3SKan Liang 5623*61b985e3SKan Liang x86_pmu.hw_config = hsw_hw_config; 5624*61b985e3SKan Liang x86_pmu.get_event_constraints = spr_get_event_constraints; 5625*61b985e3SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5626*61b985e3SKan Liang hsw_format_attr : nhm_format_attr; 5627*61b985e3SKan Liang extra_skl_attr = skl_format_attr; 5628*61b985e3SKan Liang mem_attr = spr_events_attrs; 5629*61b985e3SKan Liang td_attr = spr_td_events_attrs; 5630*61b985e3SKan Liang tsx_attr = spr_tsx_events_attrs; 5631*61b985e3SKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 5632*61b985e3SKan Liang x86_pmu.lbr_pt_coexist = true; 5633*61b985e3SKan Liang intel_pmu_pebs_data_source_skl(pmem); 5634*61b985e3SKan Liang x86_pmu.num_topdown_events = 8; 5635*61b985e3SKan Liang x86_pmu.update_topdown_event = icl_update_topdown_event; 5636*61b985e3SKan Liang x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 5637*61b985e3SKan Liang pr_cont("Sapphire Rapids events, "); 5638*61b985e3SKan Liang name = "sapphire_rapids"; 5639*61b985e3SKan Liang break; 5640*61b985e3SKan Liang 5641e1069839SBorislav Petkov default: 5642e1069839SBorislav Petkov switch (x86_pmu.version) { 5643e1069839SBorislav Petkov case 1: 5644e1069839SBorislav Petkov x86_pmu.event_constraints = intel_v1_event_constraints; 5645e1069839SBorislav Petkov pr_cont("generic architected perfmon v1, "); 5646b00233b5SAndi Kleen name = "generic_arch_v1"; 5647e1069839SBorislav Petkov break; 5648e1069839SBorislav Petkov default: 5649e1069839SBorislav Petkov /* 5650e1069839SBorislav Petkov * default constraints for v2 and up 5651e1069839SBorislav Petkov */ 5652e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 5653e1069839SBorislav Petkov pr_cont("generic architected perfmon, "); 5654b00233b5SAndi Kleen name = "generic_arch_v2+"; 5655e1069839SBorislav Petkov break; 5656e1069839SBorislav Petkov } 5657e1069839SBorislav Petkov } 5658e1069839SBorislav Petkov 56590e96f31eSJordan Borgner snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 5660b00233b5SAndi Kleen 5661a5df70c3SAndi Kleen 5662baa0c833SJiri Olsa group_events_td.attrs = td_attr; 5663baa0c833SJiri Olsa group_events_mem.attrs = mem_attr; 5664baa0c833SJiri Olsa group_events_tsx.attrs = tsx_attr; 56653ea40ac7SJiri Olsa group_format_extra.attrs = extra_attr; 5666b6576880SJiri Olsa group_format_extra_skl.attrs = extra_skl_attr; 5667baa0c833SJiri Olsa 5668baa0c833SJiri Olsa x86_pmu.attr_update = attr_update; 5669d4ae5529SJiri Olsa 5670e1069839SBorislav Petkov if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 5671e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5672e1069839SBorislav Petkov x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 5673e1069839SBorislav Petkov x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 5674e1069839SBorislav Petkov } 5675ad5013d5SColin King x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 5676e1069839SBorislav Petkov 5677e1069839SBorislav Petkov if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5678e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5679e1069839SBorislav Petkov x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 5680e1069839SBorislav Petkov x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 5681e1069839SBorislav Petkov } 5682e1069839SBorislav Petkov 5683e1069839SBorislav Petkov x86_pmu.intel_ctrl |= 5684e1069839SBorislav Petkov ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 5685e1069839SBorislav Petkov 5686cadbaa03SStephane Eranian /* AnyThread may be deprecated on arch perfmon v5 or later */ 5687cadbaa03SStephane Eranian if (x86_pmu.intel_cap.anythread_deprecated) 5688cadbaa03SStephane Eranian x86_pmu.format_attrs = intel_arch_formats_attr; 5689cadbaa03SStephane Eranian 5690e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 5691e1069839SBorislav Petkov /* 5692e1069839SBorislav Petkov * event on fixed counter2 (REF_CYCLES) only works on this 5693e1069839SBorislav Petkov * counter, so do not extend mask to generic counters 5694e1069839SBorislav Petkov */ 5695e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 56967b2c05a1SKan Liang /* 56977b2c05a1SKan Liang * Don't extend the topdown slots and metrics 56987b2c05a1SKan Liang * events to the generic counters. 56997b2c05a1SKan Liang */ 57007b2c05a1SKan Liang if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 57017b2c05a1SKan Liang c->weight = hweight64(c->idxmsk64); 57027b2c05a1SKan Liang continue; 57037b2c05a1SKan Liang } 57047b2c05a1SKan Liang 5705e1069839SBorislav Petkov if (c->cmask == FIXED_EVENT_FLAGS 5706e1069839SBorislav Petkov && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 5707e1069839SBorislav Petkov c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 5708e1069839SBorislav Petkov } 5709e1069839SBorislav Petkov c->idxmsk64 &= 57106d6f2833SAndrey Ryabinin ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 5711e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 5712e1069839SBorislav Petkov } 5713e1069839SBorislav Petkov } 5714e1069839SBorislav Petkov 5715e1069839SBorislav Petkov /* 5716e1069839SBorislav Petkov * Access LBR MSR may cause #GP under certain circumstances. 5717e1069839SBorislav Petkov * E.g. KVM doesn't support LBR MSR 5718e1069839SBorislav Petkov * Check all LBT MSR here. 5719e1069839SBorislav Petkov * Disable LBR access if any LBR MSRs can not be accessed. 5720e1069839SBorislav Petkov */ 5721e1069839SBorislav Petkov if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 5722e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 5723e1069839SBorislav Petkov for (i = 0; i < x86_pmu.lbr_nr; i++) { 5724e1069839SBorislav Petkov if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 5725e1069839SBorislav Petkov check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 5726e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 5727e1069839SBorislav Petkov } 5728e1069839SBorislav Petkov 57291f157286SJiri Olsa if (x86_pmu.lbr_nr) 5730f09509b9SDavid Carrillo-Cisneros pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 5731b00233b5SAndi Kleen 5732e1069839SBorislav Petkov /* 5733e1069839SBorislav Petkov * Access extra MSR may cause #GP under certain circumstances. 5734e1069839SBorislav Petkov * E.g. KVM doesn't support offcore event 5735e1069839SBorislav Petkov * Check all extra_regs here. 5736e1069839SBorislav Petkov */ 5737e1069839SBorislav Petkov if (x86_pmu.extra_regs) { 5738e1069839SBorislav Petkov for (er = x86_pmu.extra_regs; er->msr; er++) { 5739e1069839SBorislav Petkov er->extra_msr_access = check_msr(er->msr, 0x11UL); 5740e1069839SBorislav Petkov /* Disable LBR select mapping */ 5741e1069839SBorislav Petkov if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5742e1069839SBorislav Petkov x86_pmu.lbr_sel_map = NULL; 5743e1069839SBorislav Petkov } 5744e1069839SBorislav Petkov } 5745e1069839SBorislav Petkov 5746e1069839SBorislav Petkov /* Support full width counters using alternative MSR range */ 5747e1069839SBorislav Petkov if (x86_pmu.intel_cap.full_width_write) { 57487f612a7fSPeter Zijlstra (Intel) x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 5749e1069839SBorislav Petkov x86_pmu.perfctr = MSR_IA32_PMC0; 5750e1069839SBorislav Petkov pr_cont("full-width counters, "); 5751e1069839SBorislav Petkov } 5752e1069839SBorislav Petkov 575359a854e2SKan Liang if (x86_pmu.intel_cap.perf_metrics) 575459a854e2SKan Liang x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 575559a854e2SKan Liang 5756e1069839SBorislav Petkov return 0; 5757e1069839SBorislav Petkov } 5758e1069839SBorislav Petkov 5759e1069839SBorislav Petkov /* 5760e1069839SBorislav Petkov * HT bug: phase 2 init 5761e1069839SBorislav Petkov * Called once we have valid topology information to check 5762e1069839SBorislav Petkov * whether or not HT is enabled 5763e1069839SBorislav Petkov * If HT is off, then we disable the workaround 5764e1069839SBorislav Petkov */ 5765e1069839SBorislav Petkov static __init int fixup_ht_bug(void) 5766e1069839SBorislav Petkov { 5767030ba6cdSAndi Kleen int c; 5768e1069839SBorislav Petkov /* 5769e1069839SBorislav Petkov * problem not present on this CPU model, nothing to do 5770e1069839SBorislav Petkov */ 5771e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 5772e1069839SBorislav Petkov return 0; 5773e1069839SBorislav Petkov 5774030ba6cdSAndi Kleen if (topology_max_smt_threads() > 1) { 5775e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 5776e1069839SBorislav Petkov return 0; 5777e1069839SBorislav Petkov } 5778e1069839SBorislav Petkov 57792406e3b1SPeter Zijlstra cpus_read_lock(); 57802406e3b1SPeter Zijlstra 57812406e3b1SPeter Zijlstra hardlockup_detector_perf_stop(); 5782e1069839SBorislav Petkov 5783e1069839SBorislav Petkov x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 5784e1069839SBorislav Petkov 5785e1069839SBorislav Petkov x86_pmu.start_scheduling = NULL; 5786e1069839SBorislav Petkov x86_pmu.commit_scheduling = NULL; 5787e1069839SBorislav Petkov x86_pmu.stop_scheduling = NULL; 5788e1069839SBorislav Petkov 57892406e3b1SPeter Zijlstra hardlockup_detector_perf_restart(); 5790e1069839SBorislav Petkov 57911ba143a5SSebastian Andrzej Siewior for_each_online_cpu(c) 5792d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 5793e1069839SBorislav Petkov 57941ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 5795e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 5796e1069839SBorislav Petkov return 0; 5797e1069839SBorislav Petkov } 5798e1069839SBorislav Petkov subsys_initcall(fixup_ht_bug) 5799