1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1069839SBorislav Petkov /* 3e1069839SBorislav Petkov * Per core/cpu state 4e1069839SBorislav Petkov * 5e1069839SBorislav Petkov * Used to coordinate shared registers between HT threads or 6e1069839SBorislav Petkov * among events on a single PMU. 7e1069839SBorislav Petkov */ 8e1069839SBorislav Petkov 9e1069839SBorislav Petkov #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10e1069839SBorislav Petkov 11e1069839SBorislav Petkov #include <linux/stddef.h> 12e1069839SBorislav Petkov #include <linux/types.h> 13e1069839SBorislav Petkov #include <linux/init.h> 14e1069839SBorislav Petkov #include <linux/slab.h> 15e1069839SBorislav Petkov #include <linux/export.h> 16e1069839SBorislav Petkov #include <linux/nmi.h> 17e1069839SBorislav Petkov 18e1069839SBorislav Petkov #include <asm/cpufeature.h> 19e1069839SBorislav Petkov #include <asm/hardirq.h> 20ef5f9f47SDave Hansen #include <asm/intel-family.h> 2142880f72SAlexander Shishkin #include <asm/intel_pt.h> 22e1069839SBorislav Petkov #include <asm/apic.h> 239b545c04SAndi Kleen #include <asm/cpu_device_id.h> 24e1069839SBorislav Petkov 2527f6d22bSBorislav Petkov #include "../perf_event.h" 26e1069839SBorislav Petkov 27e1069839SBorislav Petkov /* 28e1069839SBorislav Petkov * Intel PerfMon, used on Core and later. 29e1069839SBorislav Petkov */ 30e1069839SBorislav Petkov static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31e1069839SBorislav Petkov { 32e1069839SBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33e1069839SBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37e1069839SBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38e1069839SBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39e1069839SBorislav Petkov [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40e1069839SBorislav Petkov }; 41e1069839SBorislav Petkov 42e1069839SBorislav Petkov static struct event_constraint intel_core_event_constraints[] __read_mostly = 43e1069839SBorislav Petkov { 44e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50e1069839SBorislav Petkov EVENT_CONSTRAINT_END 51e1069839SBorislav Petkov }; 52e1069839SBorislav Petkov 53e1069839SBorislav Petkov static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54e1069839SBorislav Petkov { 55e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68e1069839SBorislav Petkov EVENT_CONSTRAINT_END 69e1069839SBorislav Petkov }; 70e1069839SBorislav Petkov 71e1069839SBorislav Petkov static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72e1069839SBorislav Petkov { 73e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84e1069839SBorislav Petkov EVENT_CONSTRAINT_END 85e1069839SBorislav Petkov }; 86e1069839SBorislav Petkov 87e1069839SBorislav Petkov static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88e1069839SBorislav Petkov { 89e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92e1069839SBorislav Petkov EVENT_EXTRA_END 93e1069839SBorislav Petkov }; 94e1069839SBorislav Petkov 95e1069839SBorislav Petkov static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96e1069839SBorislav Petkov { 97e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104e1069839SBorislav Petkov EVENT_CONSTRAINT_END 105e1069839SBorislav Petkov }; 106e1069839SBorislav Petkov 107e1069839SBorislav Petkov static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108e1069839SBorislav Petkov { 109e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121e1069839SBorislav Petkov 1229010ae4aSStephane Eranian /* 1239010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1249010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1259010ae4aSStephane Eranian */ 126e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130e1069839SBorislav Petkov 131e1069839SBorislav Petkov EVENT_CONSTRAINT_END 132e1069839SBorislav Petkov }; 133e1069839SBorislav Petkov 134e1069839SBorislav Petkov static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135e1069839SBorislav Petkov { 136e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 141e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149e1069839SBorislav Petkov 1509010ae4aSStephane Eranian /* 1519010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 1529010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 1539010ae4aSStephane Eranian */ 154e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158e1069839SBorislav Petkov 159e1069839SBorislav Petkov EVENT_CONSTRAINT_END 160e1069839SBorislav Petkov }; 161e1069839SBorislav Petkov 162e1069839SBorislav Petkov static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163e1069839SBorislav Petkov { 164e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168e1069839SBorislav Petkov EVENT_EXTRA_END 169e1069839SBorislav Petkov }; 170e1069839SBorislav Petkov 171e1069839SBorislav Petkov static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172e1069839SBorislav Petkov { 173e1069839SBorislav Petkov EVENT_CONSTRAINT_END 174e1069839SBorislav Petkov }; 175e1069839SBorislav Petkov 176e1069839SBorislav Petkov static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177e1069839SBorislav Petkov { 178e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181e1069839SBorislav Petkov EVENT_CONSTRAINT_END 182e1069839SBorislav Petkov }; 183e1069839SBorislav Petkov 184e1069839SBorislav Petkov static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185e1069839SBorislav Petkov { 186e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189e1069839SBorislav Petkov EVENT_CONSTRAINT_END 190e1069839SBorislav Petkov }; 191e1069839SBorislav Petkov 19220f36278SLukasz Odzioba static struct event_constraint intel_skl_event_constraints[] = { 193e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1979010ae4aSStephane Eranian 1989010ae4aSStephane Eranian /* 1999010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 2009010ae4aSStephane Eranian */ 2019010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 2029010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 2039010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 2049010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 2059010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 2069010ae4aSStephane Eranian 207e1069839SBorislav Petkov EVENT_CONSTRAINT_END 208e1069839SBorislav Petkov }; 209e1069839SBorislav Petkov 210e1069839SBorislav Petkov static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 2119c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 2129c489fceSLukasz Odzioba INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213e1069839SBorislav Petkov EVENT_EXTRA_END 214e1069839SBorislav Petkov }; 215e1069839SBorislav Petkov 216e1069839SBorislav Petkov static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221e1069839SBorislav Petkov EVENT_EXTRA_END 222e1069839SBorislav Petkov }; 223e1069839SBorislav Petkov 224e1069839SBorislav Petkov static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229e1069839SBorislav Petkov EVENT_EXTRA_END 230e1069839SBorislav Petkov }; 231e1069839SBorislav Petkov 232e1069839SBorislav Petkov static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235e1069839SBorislav Petkov INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236e1069839SBorislav Petkov /* 237e1069839SBorislav Petkov * Note the low 8 bits eventsel code is not a continuous field, containing 238e1069839SBorislav Petkov * some #GPing bits. These are masked out. 239e1069839SBorislav Petkov */ 240e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241e1069839SBorislav Petkov EVENT_EXTRA_END 242e1069839SBorislav Petkov }; 243e1069839SBorislav Petkov 24460176089SKan Liang static struct event_constraint intel_icl_event_constraints[] = { 24560176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246010cb002SKan Liang FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */ 24760176089SKan Liang FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 24860176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 24960176089SKan Liang FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 25059a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 25159a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 25259a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 25359a854e2SKan Liang METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 25460176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 25560176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 25660176089SKan Liang INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 25760176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 25860176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 25960176089SKan Liang INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 260306e3e91SKan Liang INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 261306e3e91SKan Liang INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 26260176089SKan Liang INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 26360176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 26460176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 26560176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 26660176089SKan Liang INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 26760176089SKan Liang EVENT_CONSTRAINT_END 26860176089SKan Liang }; 26960176089SKan Liang 27060176089SKan Liang static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 2713b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 2723b238a64SYunying Sun INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 27360176089SKan Liang INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 27460176089SKan Liang INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 27560176089SKan Liang EVENT_EXTRA_END 27660176089SKan Liang }; 27760176089SKan Liang 278e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 279e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 280e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 281e1069839SBorislav Petkov 282d4ae5529SJiri Olsa static struct attribute *nhm_mem_events_attrs[] = { 283e1069839SBorislav Petkov EVENT_PTR(mem_ld_nhm), 284e1069839SBorislav Petkov NULL, 285e1069839SBorislav Petkov }; 286e1069839SBorislav Petkov 287a39fcae7SAndi Kleen /* 288a39fcae7SAndi Kleen * topdown events for Intel Core CPUs. 289a39fcae7SAndi Kleen * 290a39fcae7SAndi Kleen * The events are all in slots, which is a free slot in a 4 wide 291a39fcae7SAndi Kleen * pipeline. Some events are already reported in slots, for cycle 292a39fcae7SAndi Kleen * events we multiply by the pipeline width (4). 293a39fcae7SAndi Kleen * 294a39fcae7SAndi Kleen * With Hyper Threading on, topdown metrics are either summed or averaged 295a39fcae7SAndi Kleen * between the threads of a core: (count_t0 + count_t1). 296a39fcae7SAndi Kleen * 297a39fcae7SAndi Kleen * For the average case the metric is always scaled to pipeline width, 298a39fcae7SAndi Kleen * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 299a39fcae7SAndi Kleen */ 300a39fcae7SAndi Kleen 301a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 302a39fcae7SAndi Kleen "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 303a39fcae7SAndi Kleen "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 304a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 305a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 306a39fcae7SAndi Kleen "event=0xe,umask=0x1"); /* uops_issued.any */ 307a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 308a39fcae7SAndi Kleen "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 309a39fcae7SAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 310a39fcae7SAndi Kleen "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 311a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 312a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 313a39fcae7SAndi Kleen "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 314a39fcae7SAndi Kleen EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 315a39fcae7SAndi Kleen "4", "2"); 316a39fcae7SAndi Kleen 31759a854e2SKan Liang EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 31859a854e2SKan Liang EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 31959a854e2SKan Liang EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 32059a854e2SKan Liang EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 32159a854e2SKan Liang EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 32259a854e2SKan Liang 32320f36278SLukasz Odzioba static struct attribute *snb_events_attrs[] = { 324a39fcae7SAndi Kleen EVENT_PTR(td_slots_issued), 325a39fcae7SAndi Kleen EVENT_PTR(td_slots_retired), 326a39fcae7SAndi Kleen EVENT_PTR(td_fetch_bubbles), 327a39fcae7SAndi Kleen EVENT_PTR(td_total_slots), 328a39fcae7SAndi Kleen EVENT_PTR(td_total_slots_scale), 329a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles), 330a39fcae7SAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 331e1069839SBorislav Petkov NULL, 332e1069839SBorislav Petkov }; 333e1069839SBorislav Petkov 334d4ae5529SJiri Olsa static struct attribute *snb_mem_events_attrs[] = { 335d4ae5529SJiri Olsa EVENT_PTR(mem_ld_snb), 336d4ae5529SJiri Olsa EVENT_PTR(mem_st_snb), 337d4ae5529SJiri Olsa NULL, 338d4ae5529SJiri Olsa }; 339d4ae5529SJiri Olsa 340e1069839SBorislav Petkov static struct event_constraint intel_hsw_event_constraints[] = { 341e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 342e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 343e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 344e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 345e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 346e1069839SBorislav Petkov INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 347e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 348e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 349e1069839SBorislav Petkov /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 350e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 351e1069839SBorislav Petkov /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 352e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 353e1069839SBorislav Petkov 3549010ae4aSStephane Eranian /* 3559010ae4aSStephane Eranian * When HT is off these events can only run on the bottom 4 counters 3569010ae4aSStephane Eranian * When HT is on, they are impacted by the HT bug and require EXCL access 3579010ae4aSStephane Eranian */ 358e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 359e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 360e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 361e1069839SBorislav Petkov INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 362e1069839SBorislav Petkov 363e1069839SBorislav Petkov EVENT_CONSTRAINT_END 364e1069839SBorislav Petkov }; 365e1069839SBorislav Petkov 36620f36278SLukasz Odzioba static struct event_constraint intel_bdw_event_constraints[] = { 367e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 368e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 369e1069839SBorislav Petkov FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 370e1069839SBorislav Petkov INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 371e1069839SBorislav Petkov INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 3729010ae4aSStephane Eranian /* 3739010ae4aSStephane Eranian * when HT is off, these can only run on the bottom 4 counters 3749010ae4aSStephane Eranian */ 3759010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 3769010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 3779010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 3789010ae4aSStephane Eranian INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 379e1069839SBorislav Petkov EVENT_CONSTRAINT_END 380e1069839SBorislav Petkov }; 381e1069839SBorislav Petkov 382e1069839SBorislav Petkov static u64 intel_pmu_event_map(int hw_event) 383e1069839SBorislav Petkov { 384e1069839SBorislav Petkov return intel_perfmon_event_map[hw_event]; 385e1069839SBorislav Petkov } 386e1069839SBorislav Petkov 387e1069839SBorislav Petkov /* 388e1069839SBorislav Petkov * Notes on the events: 389e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 390e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 391e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 392e1069839SBorislav Petkov * - prefetches are not included in the counts. 393e1069839SBorislav Petkov * - icache miss does not include decoded icache 394e1069839SBorislav Petkov */ 395e1069839SBorislav Petkov 396e1069839SBorislav Petkov #define SKL_DEMAND_DATA_RD BIT_ULL(0) 397e1069839SBorislav Petkov #define SKL_DEMAND_RFO BIT_ULL(1) 398e1069839SBorislav Petkov #define SKL_ANY_RESPONSE BIT_ULL(16) 399e1069839SBorislav Petkov #define SKL_SUPPLIER_NONE BIT_ULL(17) 400e1069839SBorislav Petkov #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 401e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 402e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 403e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 404e1069839SBorislav Petkov #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 405e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 406e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 407e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 408e1069839SBorislav Petkov #define SKL_SPL_HIT BIT_ULL(30) 409e1069839SBorislav Petkov #define SKL_SNOOP_NONE BIT_ULL(31) 410e1069839SBorislav Petkov #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 411e1069839SBorislav Petkov #define SKL_SNOOP_MISS BIT_ULL(33) 412e1069839SBorislav Petkov #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 413e1069839SBorislav Petkov #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 414e1069839SBorislav Petkov #define SKL_SNOOP_HITM BIT_ULL(36) 415e1069839SBorislav Petkov #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 416e1069839SBorislav Petkov #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 417e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 418e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 419e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 420e1069839SBorislav Petkov #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 421e1069839SBorislav Petkov #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 422e1069839SBorislav Petkov SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 423e1069839SBorislav Petkov SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 424e1069839SBorislav Petkov SKL_SNOOP_HITM|SKL_SPL_HIT) 425e1069839SBorislav Petkov #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 426e1069839SBorislav Petkov #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 427e1069839SBorislav Petkov #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 428e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 429e1069839SBorislav Petkov SKL_L3_MISS_REMOTE_HOP2P_DRAM) 430e1069839SBorislav Petkov 431e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_event_ids 432e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 433e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 434e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 435e1069839SBorislav Petkov { 436e1069839SBorislav Petkov [ C(L1D ) ] = { 437e1069839SBorislav Petkov [ C(OP_READ) ] = { 438e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 439e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 440e1069839SBorislav Petkov }, 441e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 442e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 443e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 444e1069839SBorislav Petkov }, 445e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 446e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 447e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 448e1069839SBorislav Petkov }, 449e1069839SBorislav Petkov }, 450e1069839SBorislav Petkov [ C(L1I ) ] = { 451e1069839SBorislav Petkov [ C(OP_READ) ] = { 452e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 453e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 454e1069839SBorislav Petkov }, 455e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 456e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 457e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 458e1069839SBorislav Petkov }, 459e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 460e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 461e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 462e1069839SBorislav Petkov }, 463e1069839SBorislav Petkov }, 464e1069839SBorislav Petkov [ C(LL ) ] = { 465e1069839SBorislav Petkov [ C(OP_READ) ] = { 466e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 467e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 468e1069839SBorislav Petkov }, 469e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 470e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 471e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 472e1069839SBorislav Petkov }, 473e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 474e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 475e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 476e1069839SBorislav Petkov }, 477e1069839SBorislav Petkov }, 478e1069839SBorislav Petkov [ C(DTLB) ] = { 479e1069839SBorislav Petkov [ C(OP_READ) ] = { 480e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 481fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 482e1069839SBorislav Petkov }, 483e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 484e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 485fb3a5055SKan Liang [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 486e1069839SBorislav Petkov }, 487e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 488e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 489e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 490e1069839SBorislav Petkov }, 491e1069839SBorislav Petkov }, 492e1069839SBorislav Petkov [ C(ITLB) ] = { 493e1069839SBorislav Petkov [ C(OP_READ) ] = { 494e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 495e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 496e1069839SBorislav Petkov }, 497e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 498e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 499e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 500e1069839SBorislav Petkov }, 501e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 502e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 503e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 504e1069839SBorislav Petkov }, 505e1069839SBorislav Petkov }, 506e1069839SBorislav Petkov [ C(BPU ) ] = { 507e1069839SBorislav Petkov [ C(OP_READ) ] = { 508e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 509e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 510e1069839SBorislav Petkov }, 511e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 512e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 513e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 514e1069839SBorislav Petkov }, 515e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 516e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 517e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 518e1069839SBorislav Petkov }, 519e1069839SBorislav Petkov }, 520e1069839SBorislav Petkov [ C(NODE) ] = { 521e1069839SBorislav Petkov [ C(OP_READ) ] = { 522e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 523e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 524e1069839SBorislav Petkov }, 525e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 526e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 527e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 528e1069839SBorislav Petkov }, 529e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 530e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 531e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 532e1069839SBorislav Petkov }, 533e1069839SBorislav Petkov }, 534e1069839SBorislav Petkov }; 535e1069839SBorislav Petkov 536e1069839SBorislav Petkov static __initconst const u64 skl_hw_cache_extra_regs 537e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 538e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 539e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 540e1069839SBorislav Petkov { 541e1069839SBorislav Petkov [ C(LL ) ] = { 542e1069839SBorislav Petkov [ C(OP_READ) ] = { 543e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 544e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 545e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 546e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 547e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 548e1069839SBorislav Petkov }, 549e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 550e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 551e1069839SBorislav Petkov SKL_LLC_ACCESS|SKL_ANY_SNOOP, 552e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 553e1069839SBorislav Petkov SKL_L3_MISS|SKL_ANY_SNOOP| 554e1069839SBorislav Petkov SKL_SUPPLIER_NONE, 555e1069839SBorislav Petkov }, 556e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 557e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 558e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 559e1069839SBorislav Petkov }, 560e1069839SBorislav Petkov }, 561e1069839SBorislav Petkov [ C(NODE) ] = { 562e1069839SBorislav Petkov [ C(OP_READ) ] = { 563e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 564e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 565e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 566e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 567e1069839SBorislav Petkov }, 568e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 569e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 570e1069839SBorislav Petkov SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 571e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 572e1069839SBorislav Petkov SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 573e1069839SBorislav Petkov }, 574e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 575e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 576e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 577e1069839SBorislav Petkov }, 578e1069839SBorislav Petkov }, 579e1069839SBorislav Petkov }; 580e1069839SBorislav Petkov 581e1069839SBorislav Petkov #define SNB_DMND_DATA_RD (1ULL << 0) 582e1069839SBorislav Petkov #define SNB_DMND_RFO (1ULL << 1) 583e1069839SBorislav Petkov #define SNB_DMND_IFETCH (1ULL << 2) 584e1069839SBorislav Petkov #define SNB_DMND_WB (1ULL << 3) 585e1069839SBorislav Petkov #define SNB_PF_DATA_RD (1ULL << 4) 586e1069839SBorislav Petkov #define SNB_PF_RFO (1ULL << 5) 587e1069839SBorislav Petkov #define SNB_PF_IFETCH (1ULL << 6) 588e1069839SBorislav Petkov #define SNB_LLC_DATA_RD (1ULL << 7) 589e1069839SBorislav Petkov #define SNB_LLC_RFO (1ULL << 8) 590e1069839SBorislav Petkov #define SNB_LLC_IFETCH (1ULL << 9) 591e1069839SBorislav Petkov #define SNB_BUS_LOCKS (1ULL << 10) 592e1069839SBorislav Petkov #define SNB_STRM_ST (1ULL << 11) 593e1069839SBorislav Petkov #define SNB_OTHER (1ULL << 15) 594e1069839SBorislav Petkov #define SNB_RESP_ANY (1ULL << 16) 595e1069839SBorislav Petkov #define SNB_NO_SUPP (1ULL << 17) 596e1069839SBorislav Petkov #define SNB_LLC_HITM (1ULL << 18) 597e1069839SBorislav Petkov #define SNB_LLC_HITE (1ULL << 19) 598e1069839SBorislav Petkov #define SNB_LLC_HITS (1ULL << 20) 599e1069839SBorislav Petkov #define SNB_LLC_HITF (1ULL << 21) 600e1069839SBorislav Petkov #define SNB_LOCAL (1ULL << 22) 601e1069839SBorislav Petkov #define SNB_REMOTE (0xffULL << 23) 602e1069839SBorislav Petkov #define SNB_SNP_NONE (1ULL << 31) 603e1069839SBorislav Petkov #define SNB_SNP_NOT_NEEDED (1ULL << 32) 604e1069839SBorislav Petkov #define SNB_SNP_MISS (1ULL << 33) 605e1069839SBorislav Petkov #define SNB_NO_FWD (1ULL << 34) 606e1069839SBorislav Petkov #define SNB_SNP_FWD (1ULL << 35) 607e1069839SBorislav Petkov #define SNB_HITM (1ULL << 36) 608e1069839SBorislav Petkov #define SNB_NON_DRAM (1ULL << 37) 609e1069839SBorislav Petkov 610e1069839SBorislav Petkov #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 611e1069839SBorislav Petkov #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 612e1069839SBorislav Petkov #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 613e1069839SBorislav Petkov 614e1069839SBorislav Petkov #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 615e1069839SBorislav Petkov SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 616e1069839SBorislav Petkov SNB_HITM) 617e1069839SBorislav Petkov 618e1069839SBorislav Petkov #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 619e1069839SBorislav Petkov #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 620e1069839SBorislav Petkov 621e1069839SBorislav Petkov #define SNB_L3_ACCESS SNB_RESP_ANY 622e1069839SBorislav Petkov #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 623e1069839SBorislav Petkov 624e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_extra_regs 625e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 626e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 627e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 628e1069839SBorislav Petkov { 629e1069839SBorislav Petkov [ C(LL ) ] = { 630e1069839SBorislav Petkov [ C(OP_READ) ] = { 631e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 632e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 633e1069839SBorislav Petkov }, 634e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 635e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 636e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 637e1069839SBorislav Petkov }, 638e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 639e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 640e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 641e1069839SBorislav Petkov }, 642e1069839SBorislav Petkov }, 643e1069839SBorislav Petkov [ C(NODE) ] = { 644e1069839SBorislav Petkov [ C(OP_READ) ] = { 645e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 646e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 647e1069839SBorislav Petkov }, 648e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 649e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 650e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 651e1069839SBorislav Petkov }, 652e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 653e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 654e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 655e1069839SBorislav Petkov }, 656e1069839SBorislav Petkov }, 657e1069839SBorislav Petkov }; 658e1069839SBorislav Petkov 659e1069839SBorislav Petkov static __initconst const u64 snb_hw_cache_event_ids 660e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 661e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 662e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 663e1069839SBorislav Petkov { 664e1069839SBorislav Petkov [ C(L1D) ] = { 665e1069839SBorislav Petkov [ C(OP_READ) ] = { 666e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 667e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 668e1069839SBorislav Petkov }, 669e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 670e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 671e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 672e1069839SBorislav Petkov }, 673e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 674e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 675e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 676e1069839SBorislav Petkov }, 677e1069839SBorislav Petkov }, 678e1069839SBorislav Petkov [ C(L1I ) ] = { 679e1069839SBorislav Petkov [ C(OP_READ) ] = { 680e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 681e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 682e1069839SBorislav Petkov }, 683e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 684e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 685e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 686e1069839SBorislav Petkov }, 687e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 688e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 689e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 690e1069839SBorislav Petkov }, 691e1069839SBorislav Petkov }, 692e1069839SBorislav Petkov [ C(LL ) ] = { 693e1069839SBorislav Petkov [ C(OP_READ) ] = { 694e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 695e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 696e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 697e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 698e1069839SBorislav Petkov }, 699e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 700e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 701e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 702e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 703e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 704e1069839SBorislav Petkov }, 705e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 706e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 707e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 708e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 709e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 710e1069839SBorislav Petkov }, 711e1069839SBorislav Petkov }, 712e1069839SBorislav Petkov [ C(DTLB) ] = { 713e1069839SBorislav Petkov [ C(OP_READ) ] = { 714e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 715e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 716e1069839SBorislav Petkov }, 717e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 718e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 719e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 720e1069839SBorislav Petkov }, 721e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 722e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 723e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 724e1069839SBorislav Petkov }, 725e1069839SBorislav Petkov }, 726e1069839SBorislav Petkov [ C(ITLB) ] = { 727e1069839SBorislav Petkov [ C(OP_READ) ] = { 728e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 729e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 730e1069839SBorislav Petkov }, 731e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 732e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 733e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 734e1069839SBorislav Petkov }, 735e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 736e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 737e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 738e1069839SBorislav Petkov }, 739e1069839SBorislav Petkov }, 740e1069839SBorislav Petkov [ C(BPU ) ] = { 741e1069839SBorislav Petkov [ C(OP_READ) ] = { 742e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 743e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 744e1069839SBorislav Petkov }, 745e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 746e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 747e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 748e1069839SBorislav Petkov }, 749e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 750e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 751e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 752e1069839SBorislav Petkov }, 753e1069839SBorislav Petkov }, 754e1069839SBorislav Petkov [ C(NODE) ] = { 755e1069839SBorislav Petkov [ C(OP_READ) ] = { 756e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 757e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 758e1069839SBorislav Petkov }, 759e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 760e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 761e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 762e1069839SBorislav Petkov }, 763e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 764e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 765e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 766e1069839SBorislav Petkov }, 767e1069839SBorislav Petkov }, 768e1069839SBorislav Petkov 769e1069839SBorislav Petkov }; 770e1069839SBorislav Petkov 771e1069839SBorislav Petkov /* 772e1069839SBorislav Petkov * Notes on the events: 773e1069839SBorislav Petkov * - data reads do not include code reads (comparable to earlier tables) 774e1069839SBorislav Petkov * - data counts include speculative execution (except L1 write, dtlb, bpu) 775e1069839SBorislav Petkov * - remote node access includes remote memory, remote cache, remote mmio. 776e1069839SBorislav Petkov * - prefetches are not included in the counts because they are not 777e1069839SBorislav Petkov * reliably counted. 778e1069839SBorislav Petkov */ 779e1069839SBorislav Petkov 780e1069839SBorislav Petkov #define HSW_DEMAND_DATA_RD BIT_ULL(0) 781e1069839SBorislav Petkov #define HSW_DEMAND_RFO BIT_ULL(1) 782e1069839SBorislav Petkov #define HSW_ANY_RESPONSE BIT_ULL(16) 783e1069839SBorislav Petkov #define HSW_SUPPLIER_NONE BIT_ULL(17) 784e1069839SBorislav Petkov #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 785e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 786e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 787e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 788e1069839SBorislav Petkov #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 789e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 790e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 791e1069839SBorislav Petkov #define HSW_SNOOP_NONE BIT_ULL(31) 792e1069839SBorislav Petkov #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 793e1069839SBorislav Petkov #define HSW_SNOOP_MISS BIT_ULL(33) 794e1069839SBorislav Petkov #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 795e1069839SBorislav Petkov #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 796e1069839SBorislav Petkov #define HSW_SNOOP_HITM BIT_ULL(36) 797e1069839SBorislav Petkov #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 798e1069839SBorislav Petkov #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 799e1069839SBorislav Petkov HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 800e1069839SBorislav Petkov HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 801e1069839SBorislav Petkov HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 802e1069839SBorislav Petkov #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 803e1069839SBorislav Petkov #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 804e1069839SBorislav Petkov #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 805e1069839SBorislav Petkov #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 806e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 807e1069839SBorislav Petkov #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 808e1069839SBorislav Petkov 809e1069839SBorislav Petkov #define BDW_L3_MISS_LOCAL BIT(26) 810e1069839SBorislav Petkov #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 811e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 812e1069839SBorislav Petkov HSW_L3_MISS_REMOTE_HOP2P) 813e1069839SBorislav Petkov 814e1069839SBorislav Petkov 815e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_event_ids 816e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 817e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 818e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 819e1069839SBorislav Petkov { 820e1069839SBorislav Petkov [ C(L1D ) ] = { 821e1069839SBorislav Petkov [ C(OP_READ) ] = { 822e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 823e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 824e1069839SBorislav Petkov }, 825e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 826e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 827e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 828e1069839SBorislav Petkov }, 829e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 830e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 831e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 832e1069839SBorislav Petkov }, 833e1069839SBorislav Petkov }, 834e1069839SBorislav Petkov [ C(L1I ) ] = { 835e1069839SBorislav Petkov [ C(OP_READ) ] = { 836e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 837e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 838e1069839SBorislav Petkov }, 839e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 840e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 841e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 842e1069839SBorislav Petkov }, 843e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 844e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 845e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 846e1069839SBorislav Petkov }, 847e1069839SBorislav Petkov }, 848e1069839SBorislav Petkov [ C(LL ) ] = { 849e1069839SBorislav Petkov [ C(OP_READ) ] = { 850e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 851e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 852e1069839SBorislav Petkov }, 853e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 854e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 855e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 856e1069839SBorislav Petkov }, 857e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 858e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 859e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 860e1069839SBorislav Petkov }, 861e1069839SBorislav Petkov }, 862e1069839SBorislav Petkov [ C(DTLB) ] = { 863e1069839SBorislav Petkov [ C(OP_READ) ] = { 864e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 865e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 866e1069839SBorislav Petkov }, 867e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 868e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 869e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 870e1069839SBorislav Petkov }, 871e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 872e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 873e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 874e1069839SBorislav Petkov }, 875e1069839SBorislav Petkov }, 876e1069839SBorislav Petkov [ C(ITLB) ] = { 877e1069839SBorislav Petkov [ C(OP_READ) ] = { 878e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 879e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 880e1069839SBorislav Petkov }, 881e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 882e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 883e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 884e1069839SBorislav Petkov }, 885e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 886e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 887e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 888e1069839SBorislav Petkov }, 889e1069839SBorislav Petkov }, 890e1069839SBorislav Petkov [ C(BPU ) ] = { 891e1069839SBorislav Petkov [ C(OP_READ) ] = { 892e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 893e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 894e1069839SBorislav Petkov }, 895e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 896e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 897e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 898e1069839SBorislav Petkov }, 899e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 900e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 901e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 902e1069839SBorislav Petkov }, 903e1069839SBorislav Petkov }, 904e1069839SBorislav Petkov [ C(NODE) ] = { 905e1069839SBorislav Petkov [ C(OP_READ) ] = { 906e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 907e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 908e1069839SBorislav Petkov }, 909e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 910e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 911e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 912e1069839SBorislav Petkov }, 913e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 914e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 915e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 916e1069839SBorislav Petkov }, 917e1069839SBorislav Petkov }, 918e1069839SBorislav Petkov }; 919e1069839SBorislav Petkov 920e1069839SBorislav Petkov static __initconst const u64 hsw_hw_cache_extra_regs 921e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 922e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 923e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 924e1069839SBorislav Petkov { 925e1069839SBorislav Petkov [ C(LL ) ] = { 926e1069839SBorislav Petkov [ C(OP_READ) ] = { 927e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 928e1069839SBorislav Petkov HSW_LLC_ACCESS, 929e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 930e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 931e1069839SBorislav Petkov }, 932e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 933e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 934e1069839SBorislav Petkov HSW_LLC_ACCESS, 935e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 936e1069839SBorislav Petkov HSW_L3_MISS|HSW_ANY_SNOOP, 937e1069839SBorislav Petkov }, 938e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 939e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 940e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 941e1069839SBorislav Petkov }, 942e1069839SBorislav Petkov }, 943e1069839SBorislav Petkov [ C(NODE) ] = { 944e1069839SBorislav Petkov [ C(OP_READ) ] = { 945e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 946e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 947e1069839SBorislav Petkov HSW_SNOOP_DRAM, 948e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 949e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 950e1069839SBorislav Petkov HSW_SNOOP_DRAM, 951e1069839SBorislav Petkov }, 952e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 953e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 954e1069839SBorislav Petkov HSW_L3_MISS_LOCAL_DRAM| 955e1069839SBorislav Petkov HSW_SNOOP_DRAM, 956e1069839SBorislav Petkov [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 957e1069839SBorislav Petkov HSW_L3_MISS_REMOTE| 958e1069839SBorislav Petkov HSW_SNOOP_DRAM, 959e1069839SBorislav Petkov }, 960e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 961e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 962e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 963e1069839SBorislav Petkov }, 964e1069839SBorislav Petkov }, 965e1069839SBorislav Petkov }; 966e1069839SBorislav Petkov 967e1069839SBorislav Petkov static __initconst const u64 westmere_hw_cache_event_ids 968e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 969e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 970e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 971e1069839SBorislav Petkov { 972e1069839SBorislav Petkov [ C(L1D) ] = { 973e1069839SBorislav Petkov [ C(OP_READ) ] = { 974e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 975e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 976e1069839SBorislav Petkov }, 977e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 978e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 979e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 980e1069839SBorislav Petkov }, 981e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 982e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 983e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 984e1069839SBorislav Petkov }, 985e1069839SBorislav Petkov }, 986e1069839SBorislav Petkov [ C(L1I ) ] = { 987e1069839SBorislav Petkov [ C(OP_READ) ] = { 988e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 989e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 990e1069839SBorislav Petkov }, 991e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 992e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 993e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 994e1069839SBorislav Petkov }, 995e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 996e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 997e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 998e1069839SBorislav Petkov }, 999e1069839SBorislav Petkov }, 1000e1069839SBorislav Petkov [ C(LL ) ] = { 1001e1069839SBorislav Petkov [ C(OP_READ) ] = { 1002e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1003e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1004e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1005e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1006e1069839SBorislav Petkov }, 1007e1069839SBorislav Petkov /* 1008e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1009e1069839SBorislav Petkov * on RFO. 1010e1069839SBorislav Petkov */ 1011e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1012e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1013e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1014e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1015e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1016e1069839SBorislav Petkov }, 1017e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1018e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1019e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1020e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1021e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1022e1069839SBorislav Petkov }, 1023e1069839SBorislav Petkov }, 1024e1069839SBorislav Petkov [ C(DTLB) ] = { 1025e1069839SBorislav Petkov [ C(OP_READ) ] = { 1026e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1027e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1028e1069839SBorislav Petkov }, 1029e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1030e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1031e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1032e1069839SBorislav Petkov }, 1033e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1034e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1035e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1036e1069839SBorislav Petkov }, 1037e1069839SBorislav Petkov }, 1038e1069839SBorislav Petkov [ C(ITLB) ] = { 1039e1069839SBorislav Petkov [ C(OP_READ) ] = { 1040e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1041e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1042e1069839SBorislav Petkov }, 1043e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1044e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1045e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1046e1069839SBorislav Petkov }, 1047e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1048e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1049e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1050e1069839SBorislav Petkov }, 1051e1069839SBorislav Petkov }, 1052e1069839SBorislav Petkov [ C(BPU ) ] = { 1053e1069839SBorislav Petkov [ C(OP_READ) ] = { 1054e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1055e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1056e1069839SBorislav Petkov }, 1057e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1058e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1059e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1060e1069839SBorislav Petkov }, 1061e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1062e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1063e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1064e1069839SBorislav Petkov }, 1065e1069839SBorislav Petkov }, 1066e1069839SBorislav Petkov [ C(NODE) ] = { 1067e1069839SBorislav Petkov [ C(OP_READ) ] = { 1068e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1069e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1070e1069839SBorislav Petkov }, 1071e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1072e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1073e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1074e1069839SBorislav Petkov }, 1075e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1076e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1077e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1078e1069839SBorislav Petkov }, 1079e1069839SBorislav Petkov }, 1080e1069839SBorislav Petkov }; 1081e1069839SBorislav Petkov 1082e1069839SBorislav Petkov /* 1083e1069839SBorislav Petkov * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1084e1069839SBorislav Petkov * See IA32 SDM Vol 3B 30.6.1.3 1085e1069839SBorislav Petkov */ 1086e1069839SBorislav Petkov 1087e1069839SBorislav Petkov #define NHM_DMND_DATA_RD (1 << 0) 1088e1069839SBorislav Petkov #define NHM_DMND_RFO (1 << 1) 1089e1069839SBorislav Petkov #define NHM_DMND_IFETCH (1 << 2) 1090e1069839SBorislav Petkov #define NHM_DMND_WB (1 << 3) 1091e1069839SBorislav Petkov #define NHM_PF_DATA_RD (1 << 4) 1092e1069839SBorislav Petkov #define NHM_PF_DATA_RFO (1 << 5) 1093e1069839SBorislav Petkov #define NHM_PF_IFETCH (1 << 6) 1094e1069839SBorislav Petkov #define NHM_OFFCORE_OTHER (1 << 7) 1095e1069839SBorislav Petkov #define NHM_UNCORE_HIT (1 << 8) 1096e1069839SBorislav Petkov #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1097e1069839SBorislav Petkov #define NHM_OTHER_CORE_HITM (1 << 10) 1098e1069839SBorislav Petkov /* reserved */ 1099e1069839SBorislav Petkov #define NHM_REMOTE_CACHE_FWD (1 << 12) 1100e1069839SBorislav Petkov #define NHM_REMOTE_DRAM (1 << 13) 1101e1069839SBorislav Petkov #define NHM_LOCAL_DRAM (1 << 14) 1102e1069839SBorislav Petkov #define NHM_NON_DRAM (1 << 15) 1103e1069839SBorislav Petkov 1104e1069839SBorislav Petkov #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1105e1069839SBorislav Petkov #define NHM_REMOTE (NHM_REMOTE_DRAM) 1106e1069839SBorislav Petkov 1107e1069839SBorislav Petkov #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1108e1069839SBorislav Petkov #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1109e1069839SBorislav Petkov #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1110e1069839SBorislav Petkov 1111e1069839SBorislav Petkov #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1112e1069839SBorislav Petkov #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1113e1069839SBorislav Petkov #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1114e1069839SBorislav Petkov 1115e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_extra_regs 1116e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1117e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1118e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1119e1069839SBorislav Petkov { 1120e1069839SBorislav Petkov [ C(LL ) ] = { 1121e1069839SBorislav Petkov [ C(OP_READ) ] = { 1122e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1123e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1124e1069839SBorislav Petkov }, 1125e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1126e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1127e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1128e1069839SBorislav Petkov }, 1129e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1130e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1131e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1132e1069839SBorislav Petkov }, 1133e1069839SBorislav Petkov }, 1134e1069839SBorislav Petkov [ C(NODE) ] = { 1135e1069839SBorislav Petkov [ C(OP_READ) ] = { 1136e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1137e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1138e1069839SBorislav Petkov }, 1139e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1140e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1141e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1142e1069839SBorislav Petkov }, 1143e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1144e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1145e1069839SBorislav Petkov [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1146e1069839SBorislav Petkov }, 1147e1069839SBorislav Petkov }, 1148e1069839SBorislav Petkov }; 1149e1069839SBorislav Petkov 1150e1069839SBorislav Petkov static __initconst const u64 nehalem_hw_cache_event_ids 1151e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1152e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1153e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1154e1069839SBorislav Petkov { 1155e1069839SBorislav Petkov [ C(L1D) ] = { 1156e1069839SBorislav Petkov [ C(OP_READ) ] = { 1157e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1158e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1159e1069839SBorislav Petkov }, 1160e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1161e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1162e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1163e1069839SBorislav Petkov }, 1164e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1165e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1166e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1167e1069839SBorislav Petkov }, 1168e1069839SBorislav Petkov }, 1169e1069839SBorislav Petkov [ C(L1I ) ] = { 1170e1069839SBorislav Petkov [ C(OP_READ) ] = { 1171e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1172e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1173e1069839SBorislav Petkov }, 1174e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1175e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1176e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1177e1069839SBorislav Petkov }, 1178e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1179e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1180e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1181e1069839SBorislav Petkov }, 1182e1069839SBorislav Petkov }, 1183e1069839SBorislav Petkov [ C(LL ) ] = { 1184e1069839SBorislav Petkov [ C(OP_READ) ] = { 1185e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1186e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1187e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1188e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1189e1069839SBorislav Petkov }, 1190e1069839SBorislav Petkov /* 1191e1069839SBorislav Petkov * Use RFO, not WRITEBACK, because a write miss would typically occur 1192e1069839SBorislav Petkov * on RFO. 1193e1069839SBorislav Petkov */ 1194e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1195e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1196e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1197e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1198e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1199e1069839SBorislav Petkov }, 1200e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1201e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1202e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1203e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1204e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1205e1069839SBorislav Petkov }, 1206e1069839SBorislav Petkov }, 1207e1069839SBorislav Petkov [ C(DTLB) ] = { 1208e1069839SBorislav Petkov [ C(OP_READ) ] = { 1209e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1210e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1211e1069839SBorislav Petkov }, 1212e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1213e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1214e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1215e1069839SBorislav Petkov }, 1216e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1217e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1218e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0, 1219e1069839SBorislav Petkov }, 1220e1069839SBorislav Petkov }, 1221e1069839SBorislav Petkov [ C(ITLB) ] = { 1222e1069839SBorislav Petkov [ C(OP_READ) ] = { 1223e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1224e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1225e1069839SBorislav Petkov }, 1226e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1227e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1228e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1229e1069839SBorislav Petkov }, 1230e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1231e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1232e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1233e1069839SBorislav Petkov }, 1234e1069839SBorislav Petkov }, 1235e1069839SBorislav Petkov [ C(BPU ) ] = { 1236e1069839SBorislav Petkov [ C(OP_READ) ] = { 1237e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1238e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1239e1069839SBorislav Petkov }, 1240e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1241e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1242e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1243e1069839SBorislav Petkov }, 1244e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1245e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1246e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1247e1069839SBorislav Petkov }, 1248e1069839SBorislav Petkov }, 1249e1069839SBorislav Petkov [ C(NODE) ] = { 1250e1069839SBorislav Petkov [ C(OP_READ) ] = { 1251e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1252e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1253e1069839SBorislav Petkov }, 1254e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1255e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1256e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1257e1069839SBorislav Petkov }, 1258e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1259e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1260e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1261e1069839SBorislav Petkov }, 1262e1069839SBorislav Petkov }, 1263e1069839SBorislav Petkov }; 1264e1069839SBorislav Petkov 1265e1069839SBorislav Petkov static __initconst const u64 core2_hw_cache_event_ids 1266e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1267e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1268e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1269e1069839SBorislav Petkov { 1270e1069839SBorislav Petkov [ C(L1D) ] = { 1271e1069839SBorislav Petkov [ C(OP_READ) ] = { 1272e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1273e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1274e1069839SBorislav Petkov }, 1275e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1276e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1277e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1278e1069839SBorislav Petkov }, 1279e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1280e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1281e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1282e1069839SBorislav Petkov }, 1283e1069839SBorislav Petkov }, 1284e1069839SBorislav Petkov [ C(L1I ) ] = { 1285e1069839SBorislav Petkov [ C(OP_READ) ] = { 1286e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1287e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1288e1069839SBorislav Petkov }, 1289e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1290e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1291e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1292e1069839SBorislav Petkov }, 1293e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1294e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1295e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1296e1069839SBorislav Petkov }, 1297e1069839SBorislav Petkov }, 1298e1069839SBorislav Petkov [ C(LL ) ] = { 1299e1069839SBorislav Petkov [ C(OP_READ) ] = { 1300e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1301e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1302e1069839SBorislav Petkov }, 1303e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1304e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1305e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1306e1069839SBorislav Petkov }, 1307e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1308e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1309e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1310e1069839SBorislav Petkov }, 1311e1069839SBorislav Petkov }, 1312e1069839SBorislav Petkov [ C(DTLB) ] = { 1313e1069839SBorislav Petkov [ C(OP_READ) ] = { 1314e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1315e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1316e1069839SBorislav Petkov }, 1317e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1318e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1319e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1320e1069839SBorislav Petkov }, 1321e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1322e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1323e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1324e1069839SBorislav Petkov }, 1325e1069839SBorislav Petkov }, 1326e1069839SBorislav Petkov [ C(ITLB) ] = { 1327e1069839SBorislav Petkov [ C(OP_READ) ] = { 1328e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1329e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1330e1069839SBorislav Petkov }, 1331e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1332e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1333e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1334e1069839SBorislav Petkov }, 1335e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1336e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1337e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1338e1069839SBorislav Petkov }, 1339e1069839SBorislav Petkov }, 1340e1069839SBorislav Petkov [ C(BPU ) ] = { 1341e1069839SBorislav Petkov [ C(OP_READ) ] = { 1342e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1343e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1344e1069839SBorislav Petkov }, 1345e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1346e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1347e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1348e1069839SBorislav Petkov }, 1349e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1350e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1351e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1352e1069839SBorislav Petkov }, 1353e1069839SBorislav Petkov }, 1354e1069839SBorislav Petkov }; 1355e1069839SBorislav Petkov 1356e1069839SBorislav Petkov static __initconst const u64 atom_hw_cache_event_ids 1357e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1358e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1359e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1360e1069839SBorislav Petkov { 1361e1069839SBorislav Petkov [ C(L1D) ] = { 1362e1069839SBorislav Petkov [ C(OP_READ) ] = { 1363e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1364e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1365e1069839SBorislav Petkov }, 1366e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1367e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1368e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1369e1069839SBorislav Petkov }, 1370e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1371e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0, 1372e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1373e1069839SBorislav Petkov }, 1374e1069839SBorislav Petkov }, 1375e1069839SBorislav Petkov [ C(L1I ) ] = { 1376e1069839SBorislav Petkov [ C(OP_READ) ] = { 1377e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1378e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1379e1069839SBorislav Petkov }, 1380e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1381e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1382e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1383e1069839SBorislav Petkov }, 1384e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1385e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1386e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1387e1069839SBorislav Petkov }, 1388e1069839SBorislav Petkov }, 1389e1069839SBorislav Petkov [ C(LL ) ] = { 1390e1069839SBorislav Petkov [ C(OP_READ) ] = { 1391e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1392e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1393e1069839SBorislav Petkov }, 1394e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1395e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1396e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1397e1069839SBorislav Petkov }, 1398e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1399e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1400e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1401e1069839SBorislav Petkov }, 1402e1069839SBorislav Petkov }, 1403e1069839SBorislav Petkov [ C(DTLB) ] = { 1404e1069839SBorislav Petkov [ C(OP_READ) ] = { 1405e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1406e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1407e1069839SBorislav Petkov }, 1408e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1409e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1410e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1411e1069839SBorislav Petkov }, 1412e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1413e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1414e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1415e1069839SBorislav Petkov }, 1416e1069839SBorislav Petkov }, 1417e1069839SBorislav Petkov [ C(ITLB) ] = { 1418e1069839SBorislav Petkov [ C(OP_READ) ] = { 1419e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1420e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1421e1069839SBorislav Petkov }, 1422e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1423e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1424e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1425e1069839SBorislav Petkov }, 1426e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1427e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1428e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1429e1069839SBorislav Petkov }, 1430e1069839SBorislav Petkov }, 1431e1069839SBorislav Petkov [ C(BPU ) ] = { 1432e1069839SBorislav Petkov [ C(OP_READ) ] = { 1433e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1434e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1435e1069839SBorislav Petkov }, 1436e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1437e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1438e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1439e1069839SBorislav Petkov }, 1440e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1441e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1442e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1443e1069839SBorislav Petkov }, 1444e1069839SBorislav Petkov }, 1445e1069839SBorislav Petkov }; 1446e1069839SBorislav Petkov 1447eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1448eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1449eb12b8ecSAndi Kleen /* no_alloc_cycles.not_delivered */ 1450eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1451eb12b8ecSAndi Kleen "event=0xca,umask=0x50"); 1452eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1453eb12b8ecSAndi Kleen /* uops_retired.all */ 1454eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1455eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1456eb12b8ecSAndi Kleen /* uops_retired.all */ 1457eb12b8ecSAndi Kleen EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1458eb12b8ecSAndi Kleen "event=0xc2,umask=0x10"); 1459eb12b8ecSAndi Kleen 1460eb12b8ecSAndi Kleen static struct attribute *slm_events_attrs[] = { 1461eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_slm), 1462eb12b8ecSAndi Kleen EVENT_PTR(td_total_slots_scale_slm), 1463eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_slm), 1464eb12b8ecSAndi Kleen EVENT_PTR(td_fetch_bubbles_scale_slm), 1465eb12b8ecSAndi Kleen EVENT_PTR(td_slots_issued_slm), 1466eb12b8ecSAndi Kleen EVENT_PTR(td_slots_retired_slm), 1467eb12b8ecSAndi Kleen NULL 1468eb12b8ecSAndi Kleen }; 1469eb12b8ecSAndi Kleen 1470e1069839SBorislav Petkov static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1471e1069839SBorislav Petkov { 1472e1069839SBorislav Petkov /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1473e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1474e1069839SBorislav Petkov INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1475e1069839SBorislav Petkov EVENT_EXTRA_END 1476e1069839SBorislav Petkov }; 1477e1069839SBorislav Petkov 1478e1069839SBorislav Petkov #define SLM_DMND_READ SNB_DMND_DATA_RD 1479e1069839SBorislav Petkov #define SLM_DMND_WRITE SNB_DMND_RFO 1480e1069839SBorislav Petkov #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1481e1069839SBorislav Petkov 1482e1069839SBorislav Petkov #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1483e1069839SBorislav Petkov #define SLM_LLC_ACCESS SNB_RESP_ANY 1484e1069839SBorislav Petkov #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1485e1069839SBorislav Petkov 1486e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_extra_regs 1487e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1488e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1489e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1490e1069839SBorislav Petkov { 1491e1069839SBorislav Petkov [ C(LL ) ] = { 1492e1069839SBorislav Petkov [ C(OP_READ) ] = { 1493e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1494e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1495e1069839SBorislav Petkov }, 1496e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1497e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1498e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1499e1069839SBorislav Petkov }, 1500e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1501e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1502e1069839SBorislav Petkov [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1503e1069839SBorislav Petkov }, 1504e1069839SBorislav Petkov }, 1505e1069839SBorislav Petkov }; 1506e1069839SBorislav Petkov 1507e1069839SBorislav Petkov static __initconst const u64 slm_hw_cache_event_ids 1508e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1509e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1510e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1511e1069839SBorislav Petkov { 1512e1069839SBorislav Petkov [ C(L1D) ] = { 1513e1069839SBorislav Petkov [ C(OP_READ) ] = { 1514e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1515e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1516e1069839SBorislav Petkov }, 1517e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1518e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1519e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1520e1069839SBorislav Petkov }, 1521e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1522e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1523e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1524e1069839SBorislav Petkov }, 1525e1069839SBorislav Petkov }, 1526e1069839SBorislav Petkov [ C(L1I ) ] = { 1527e1069839SBorislav Petkov [ C(OP_READ) ] = { 1528e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1529e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1530e1069839SBorislav Petkov }, 1531e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1532e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1533e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1534e1069839SBorislav Petkov }, 1535e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1536e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1537e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1538e1069839SBorislav Petkov }, 1539e1069839SBorislav Petkov }, 1540e1069839SBorislav Petkov [ C(LL ) ] = { 1541e1069839SBorislav Petkov [ C(OP_READ) ] = { 1542e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1543e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1544e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1545e1069839SBorislav Petkov }, 1546e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1547e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1548e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1549e1069839SBorislav Petkov /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1550e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1551e1069839SBorislav Petkov }, 1552e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1553e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1554e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x01b7, 1555e1069839SBorislav Petkov /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1556e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x01b7, 1557e1069839SBorislav Petkov }, 1558e1069839SBorislav Petkov }, 1559e1069839SBorislav Petkov [ C(DTLB) ] = { 1560e1069839SBorislav Petkov [ C(OP_READ) ] = { 1561e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1562e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1563e1069839SBorislav Petkov }, 1564e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1565e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1566e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1567e1069839SBorislav Petkov }, 1568e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1569e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0, 1570e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0, 1571e1069839SBorislav Petkov }, 1572e1069839SBorislav Petkov }, 1573e1069839SBorislav Petkov [ C(ITLB) ] = { 1574e1069839SBorislav Petkov [ C(OP_READ) ] = { 1575e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1576e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1577e1069839SBorislav Petkov }, 1578e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1579e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1580e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1581e1069839SBorislav Petkov }, 1582e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1583e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1584e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1585e1069839SBorislav Petkov }, 1586e1069839SBorislav Petkov }, 1587e1069839SBorislav Petkov [ C(BPU ) ] = { 1588e1069839SBorislav Petkov [ C(OP_READ) ] = { 1589e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1590e1069839SBorislav Petkov [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1591e1069839SBorislav Petkov }, 1592e1069839SBorislav Petkov [ C(OP_WRITE) ] = { 1593e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1594e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1595e1069839SBorislav Petkov }, 1596e1069839SBorislav Petkov [ C(OP_PREFETCH) ] = { 1597e1069839SBorislav Petkov [ C(RESULT_ACCESS) ] = -1, 1598e1069839SBorislav Petkov [ C(RESULT_MISS) ] = -1, 1599e1069839SBorislav Petkov }, 1600e1069839SBorislav Petkov }, 1601e1069839SBorislav Petkov }; 1602e1069839SBorislav Petkov 1603ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1604ed827adbSKan Liang EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1605ed827adbSKan Liang /* UOPS_NOT_DELIVERED.ANY */ 1606ed827adbSKan Liang EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1607ed827adbSKan Liang /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1608ed827adbSKan Liang EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1609ed827adbSKan Liang /* UOPS_RETIRED.ANY */ 1610ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1611ed827adbSKan Liang /* UOPS_ISSUED.ANY */ 1612ed827adbSKan Liang EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1613ed827adbSKan Liang 1614ed827adbSKan Liang static struct attribute *glm_events_attrs[] = { 1615ed827adbSKan Liang EVENT_PTR(td_total_slots_glm), 1616ed827adbSKan Liang EVENT_PTR(td_total_slots_scale_glm), 1617ed827adbSKan Liang EVENT_PTR(td_fetch_bubbles_glm), 1618ed827adbSKan Liang EVENT_PTR(td_recovery_bubbles_glm), 1619ed827adbSKan Liang EVENT_PTR(td_slots_issued_glm), 1620ed827adbSKan Liang EVENT_PTR(td_slots_retired_glm), 1621ed827adbSKan Liang NULL 1622ed827adbSKan Liang }; 1623ed827adbSKan Liang 16248b92c3a7SKan Liang static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 16258b92c3a7SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 16268b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 16278b92c3a7SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 16288b92c3a7SKan Liang EVENT_EXTRA_END 16298b92c3a7SKan Liang }; 16308b92c3a7SKan Liang 16318b92c3a7SKan Liang #define GLM_DEMAND_DATA_RD BIT_ULL(0) 16328b92c3a7SKan Liang #define GLM_DEMAND_RFO BIT_ULL(1) 16338b92c3a7SKan Liang #define GLM_ANY_RESPONSE BIT_ULL(16) 16348b92c3a7SKan Liang #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 16358b92c3a7SKan Liang #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 16368b92c3a7SKan Liang #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 16378b92c3a7SKan Liang #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 16388b92c3a7SKan Liang #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 16398b92c3a7SKan Liang #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 16408b92c3a7SKan Liang #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 16418b92c3a7SKan Liang 16428b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_event_ids 16438b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 16448b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 16458b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 16468b92c3a7SKan Liang [C(L1D)] = { 16478b92c3a7SKan Liang [C(OP_READ)] = { 16488b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16498b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16508b92c3a7SKan Liang }, 16518b92c3a7SKan Liang [C(OP_WRITE)] = { 16528b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16538b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16548b92c3a7SKan Liang }, 16558b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16568b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16578b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16588b92c3a7SKan Liang }, 16598b92c3a7SKan Liang }, 16608b92c3a7SKan Liang [C(L1I)] = { 16618b92c3a7SKan Liang [C(OP_READ)] = { 16628b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 16638b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 16648b92c3a7SKan Liang }, 16658b92c3a7SKan Liang [C(OP_WRITE)] = { 16668b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 16678b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 16688b92c3a7SKan Liang }, 16698b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16708b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16718b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16728b92c3a7SKan Liang }, 16738b92c3a7SKan Liang }, 16748b92c3a7SKan Liang [C(LL)] = { 16758b92c3a7SKan Liang [C(OP_READ)] = { 16768b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16778b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16788b92c3a7SKan Liang }, 16798b92c3a7SKan Liang [C(OP_WRITE)] = { 16808b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16818b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16828b92c3a7SKan Liang }, 16838b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16848b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16858b92c3a7SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 16868b92c3a7SKan Liang }, 16878b92c3a7SKan Liang }, 16888b92c3a7SKan Liang [C(DTLB)] = { 16898b92c3a7SKan Liang [C(OP_READ)] = { 16908b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 16918b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16928b92c3a7SKan Liang }, 16938b92c3a7SKan Liang [C(OP_WRITE)] = { 16948b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 16958b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 16968b92c3a7SKan Liang }, 16978b92c3a7SKan Liang [C(OP_PREFETCH)] = { 16988b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x0, 16998b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0, 17008b92c3a7SKan Liang }, 17018b92c3a7SKan Liang }, 17028b92c3a7SKan Liang [C(ITLB)] = { 17038b92c3a7SKan Liang [C(OP_READ)] = { 17048b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 17058b92c3a7SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 17068b92c3a7SKan Liang }, 17078b92c3a7SKan Liang [C(OP_WRITE)] = { 17088b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17098b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17108b92c3a7SKan Liang }, 17118b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17128b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17138b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17148b92c3a7SKan Liang }, 17158b92c3a7SKan Liang }, 17168b92c3a7SKan Liang [C(BPU)] = { 17178b92c3a7SKan Liang [C(OP_READ)] = { 17188b92c3a7SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 17198b92c3a7SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 17208b92c3a7SKan Liang }, 17218b92c3a7SKan Liang [C(OP_WRITE)] = { 17228b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17238b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17248b92c3a7SKan Liang }, 17258b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17268b92c3a7SKan Liang [C(RESULT_ACCESS)] = -1, 17278b92c3a7SKan Liang [C(RESULT_MISS)] = -1, 17288b92c3a7SKan Liang }, 17298b92c3a7SKan Liang }, 17308b92c3a7SKan Liang }; 17318b92c3a7SKan Liang 17328b92c3a7SKan Liang static __initconst const u64 glm_hw_cache_extra_regs 17338b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_MAX] 17348b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 17358b92c3a7SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 17368b92c3a7SKan Liang [C(LL)] = { 17378b92c3a7SKan Liang [C(OP_READ)] = { 17388b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 17398b92c3a7SKan Liang GLM_LLC_ACCESS, 17408b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 17418b92c3a7SKan Liang GLM_LLC_MISS, 17428b92c3a7SKan Liang }, 17438b92c3a7SKan Liang [C(OP_WRITE)] = { 17448b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 17458b92c3a7SKan Liang GLM_LLC_ACCESS, 17468b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 17478b92c3a7SKan Liang GLM_LLC_MISS, 17488b92c3a7SKan Liang }, 17498b92c3a7SKan Liang [C(OP_PREFETCH)] = { 17508b92c3a7SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 17518b92c3a7SKan Liang GLM_LLC_ACCESS, 17528b92c3a7SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 17538b92c3a7SKan Liang GLM_LLC_MISS, 17548b92c3a7SKan Liang }, 17558b92c3a7SKan Liang }, 17568b92c3a7SKan Liang }; 17578b92c3a7SKan Liang 1758dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_event_ids 1759dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1760dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1761dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1762dd0b06b5SKan Liang [C(L1D)] = { 1763dd0b06b5SKan Liang [C(OP_READ)] = { 1764dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1765dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1766dd0b06b5SKan Liang }, 1767dd0b06b5SKan Liang [C(OP_WRITE)] = { 1768dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1769dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1770dd0b06b5SKan Liang }, 1771dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1772dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1773dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1774dd0b06b5SKan Liang }, 1775dd0b06b5SKan Liang }, 1776dd0b06b5SKan Liang [C(L1I)] = { 1777dd0b06b5SKan Liang [C(OP_READ)] = { 1778dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1779dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1780dd0b06b5SKan Liang }, 1781dd0b06b5SKan Liang [C(OP_WRITE)] = { 1782dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1783dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1784dd0b06b5SKan Liang }, 1785dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1786dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1787dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1788dd0b06b5SKan Liang }, 1789dd0b06b5SKan Liang }, 1790dd0b06b5SKan Liang [C(LL)] = { 1791dd0b06b5SKan Liang [C(OP_READ)] = { 1792dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1793dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1794dd0b06b5SKan Liang }, 1795dd0b06b5SKan Liang [C(OP_WRITE)] = { 1796dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1797dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1798dd0b06b5SKan Liang }, 1799dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1800dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1801dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1802dd0b06b5SKan Liang }, 1803dd0b06b5SKan Liang }, 1804dd0b06b5SKan Liang [C(DTLB)] = { 1805dd0b06b5SKan Liang [C(OP_READ)] = { 1806dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1807dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1808dd0b06b5SKan Liang }, 1809dd0b06b5SKan Liang [C(OP_WRITE)] = { 1810dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1811dd0b06b5SKan Liang [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1812dd0b06b5SKan Liang }, 1813dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1814dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1815dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1816dd0b06b5SKan Liang }, 1817dd0b06b5SKan Liang }, 1818dd0b06b5SKan Liang [C(ITLB)] = { 1819dd0b06b5SKan Liang [C(OP_READ)] = { 1820dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1821dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1822dd0b06b5SKan Liang }, 1823dd0b06b5SKan Liang [C(OP_WRITE)] = { 1824dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1825dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1826dd0b06b5SKan Liang }, 1827dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1828dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1829dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1830dd0b06b5SKan Liang }, 1831dd0b06b5SKan Liang }, 1832dd0b06b5SKan Liang [C(BPU)] = { 1833dd0b06b5SKan Liang [C(OP_READ)] = { 1834dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1835dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1836dd0b06b5SKan Liang }, 1837dd0b06b5SKan Liang [C(OP_WRITE)] = { 1838dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1839dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1840dd0b06b5SKan Liang }, 1841dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1842dd0b06b5SKan Liang [C(RESULT_ACCESS)] = -1, 1843dd0b06b5SKan Liang [C(RESULT_MISS)] = -1, 1844dd0b06b5SKan Liang }, 1845dd0b06b5SKan Liang }, 1846dd0b06b5SKan Liang }; 1847dd0b06b5SKan Liang 1848dd0b06b5SKan Liang static __initconst const u64 glp_hw_cache_extra_regs 1849dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_MAX] 1850dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 1851dd0b06b5SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1852dd0b06b5SKan Liang [C(LL)] = { 1853dd0b06b5SKan Liang [C(OP_READ)] = { 1854dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1855dd0b06b5SKan Liang GLM_LLC_ACCESS, 1856dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_READ| 1857dd0b06b5SKan Liang GLM_LLC_MISS, 1858dd0b06b5SKan Liang }, 1859dd0b06b5SKan Liang [C(OP_WRITE)] = { 1860dd0b06b5SKan Liang [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1861dd0b06b5SKan Liang GLM_LLC_ACCESS, 1862dd0b06b5SKan Liang [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1863dd0b06b5SKan Liang GLM_LLC_MISS, 1864dd0b06b5SKan Liang }, 1865dd0b06b5SKan Liang [C(OP_PREFETCH)] = { 1866dd0b06b5SKan Liang [C(RESULT_ACCESS)] = 0x0, 1867dd0b06b5SKan Liang [C(RESULT_MISS)] = 0x0, 1868dd0b06b5SKan Liang }, 1869dd0b06b5SKan Liang }, 1870dd0b06b5SKan Liang }; 1871dd0b06b5SKan Liang 18726daeb873SKan Liang #define TNT_LOCAL_DRAM BIT_ULL(26) 18736daeb873SKan Liang #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 18746daeb873SKan Liang #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 18756daeb873SKan Liang #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 18766daeb873SKan Liang #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 18776daeb873SKan Liang SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 18786daeb873SKan Liang #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 18796daeb873SKan Liang 18806daeb873SKan Liang static __initconst const u64 tnt_hw_cache_extra_regs 18816daeb873SKan Liang [PERF_COUNT_HW_CACHE_MAX] 18826daeb873SKan Liang [PERF_COUNT_HW_CACHE_OP_MAX] 18836daeb873SKan Liang [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 18846daeb873SKan Liang [C(LL)] = { 18856daeb873SKan Liang [C(OP_READ)] = { 18866daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 18876daeb873SKan Liang TNT_LLC_ACCESS, 18886daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_READ| 18896daeb873SKan Liang TNT_LLC_MISS, 18906daeb873SKan Liang }, 18916daeb873SKan Liang [C(OP_WRITE)] = { 18926daeb873SKan Liang [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 18936daeb873SKan Liang TNT_LLC_ACCESS, 18946daeb873SKan Liang [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 18956daeb873SKan Liang TNT_LLC_MISS, 18966daeb873SKan Liang }, 18976daeb873SKan Liang [C(OP_PREFETCH)] = { 18986daeb873SKan Liang [C(RESULT_ACCESS)] = 0x0, 18996daeb873SKan Liang [C(RESULT_MISS)] = 0x0, 19006daeb873SKan Liang }, 19016daeb873SKan Liang }, 19026daeb873SKan Liang }; 19036daeb873SKan Liang 19046daeb873SKan Liang static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 19056daeb873SKan Liang /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 19060813c405SKan Liang INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 19070813c405SKan Liang INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 19086daeb873SKan Liang EVENT_EXTRA_END 19096daeb873SKan Liang }; 19106daeb873SKan Liang 1911e1069839SBorislav Petkov #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1912e1069839SBorislav Petkov #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1913e1069839SBorislav Petkov #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1914e1069839SBorislav Petkov #define KNL_MCDRAM_FAR BIT_ULL(22) 1915e1069839SBorislav Petkov #define KNL_DDR_LOCAL BIT_ULL(23) 1916e1069839SBorislav Petkov #define KNL_DDR_FAR BIT_ULL(24) 1917e1069839SBorislav Petkov #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1918e1069839SBorislav Petkov KNL_DDR_LOCAL | KNL_DDR_FAR) 1919e1069839SBorislav Petkov #define KNL_L2_READ SLM_DMND_READ 1920e1069839SBorislav Petkov #define KNL_L2_WRITE SLM_DMND_WRITE 1921e1069839SBorislav Petkov #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1922e1069839SBorislav Petkov #define KNL_L2_ACCESS SLM_LLC_ACCESS 1923e1069839SBorislav Petkov #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1924e1069839SBorislav Petkov KNL_DRAM_ANY | SNB_SNP_ANY | \ 1925e1069839SBorislav Petkov SNB_NON_DRAM) 1926e1069839SBorislav Petkov 1927e1069839SBorislav Petkov static __initconst const u64 knl_hw_cache_extra_regs 1928e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_MAX] 1929e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX] 1930e1069839SBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1931e1069839SBorislav Petkov [C(LL)] = { 1932e1069839SBorislav Petkov [C(OP_READ)] = { 1933e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1934e1069839SBorislav Petkov [C(RESULT_MISS)] = 0, 1935e1069839SBorislav Petkov }, 1936e1069839SBorislav Petkov [C(OP_WRITE)] = { 1937e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1938e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1939e1069839SBorislav Petkov }, 1940e1069839SBorislav Petkov [C(OP_PREFETCH)] = { 1941e1069839SBorislav Petkov [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1942e1069839SBorislav Petkov [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1943e1069839SBorislav Petkov }, 1944e1069839SBorislav Petkov }, 1945e1069839SBorislav Petkov }; 1946e1069839SBorislav Petkov 1947e1069839SBorislav Petkov /* 1948c3d266c8SKan Liang * Used from PMIs where the LBRs are already disabled. 1949c3d266c8SKan Liang * 1950c3d266c8SKan Liang * This function could be called consecutively. It is required to remain in 1951c3d266c8SKan Liang * disabled state if called consecutively. 1952c3d266c8SKan Liang * 1953c3d266c8SKan Liang * During consecutive calls, the same disable value will be written to related 1954cecf6235SAlexander Shishkin * registers, so the PMU state remains unchanged. 1955cecf6235SAlexander Shishkin * 1956cecf6235SAlexander Shishkin * intel_bts events don't coexist with intel PMU's BTS events because of 1957cecf6235SAlexander Shishkin * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1958cecf6235SAlexander Shishkin * disabled around intel PMU's event batching etc, only inside the PMI handler. 19596c1c07b3SKan Liang * 19606c1c07b3SKan Liang * Avoid PEBS_ENABLE MSR access in PMIs. 19616c1c07b3SKan Liang * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 19626c1c07b3SKan Liang * It doesn't matter if the PEBS is enabled or not. 19636c1c07b3SKan Liang * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 19646c1c07b3SKan Liang * access PEBS_ENABLE MSR in disable_all()/enable_all(). 19656c1c07b3SKan Liang * However, there are some cases which may change PEBS status, e.g. PMI 19666c1c07b3SKan Liang * throttle. The PEBS_ENABLE should be updated where the status changes. 1967e1069839SBorislav Petkov */ 1968e1069839SBorislav Petkov static void __intel_pmu_disable_all(void) 1969e1069839SBorislav Petkov { 1970e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1971e1069839SBorislav Petkov 1972e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1973e1069839SBorislav Petkov 1974e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1975e1069839SBorislav Petkov intel_pmu_disable_bts(); 1976e1069839SBorislav Petkov } 1977e1069839SBorislav Petkov 1978e1069839SBorislav Petkov static void intel_pmu_disable_all(void) 1979e1069839SBorislav Petkov { 1980e1069839SBorislav Petkov __intel_pmu_disable_all(); 19816c1c07b3SKan Liang intel_pmu_pebs_disable_all(); 1982e1069839SBorislav Petkov intel_pmu_lbr_disable_all(); 1983e1069839SBorislav Petkov } 1984e1069839SBorislav Petkov 1985e1069839SBorislav Petkov static void __intel_pmu_enable_all(int added, bool pmi) 1986e1069839SBorislav Petkov { 1987e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1988e1069839SBorislav Petkov 1989e1069839SBorislav Petkov intel_pmu_lbr_enable_all(pmi); 1990e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 1991e1069839SBorislav Petkov x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 1992e1069839SBorislav Petkov 1993e1069839SBorislav Petkov if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 1994e1069839SBorislav Petkov struct perf_event *event = 1995e1069839SBorislav Petkov cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 1996e1069839SBorislav Petkov 1997e1069839SBorislav Petkov if (WARN_ON_ONCE(!event)) 1998e1069839SBorislav Petkov return; 1999e1069839SBorislav Petkov 2000e1069839SBorislav Petkov intel_pmu_enable_bts(event->hw.config); 2001cecf6235SAlexander Shishkin } 2002e1069839SBorislav Petkov } 2003e1069839SBorislav Petkov 2004e1069839SBorislav Petkov static void intel_pmu_enable_all(int added) 2005e1069839SBorislav Petkov { 20066c1c07b3SKan Liang intel_pmu_pebs_enable_all(); 2007e1069839SBorislav Petkov __intel_pmu_enable_all(added, false); 2008e1069839SBorislav Petkov } 2009e1069839SBorislav Petkov 2010e1069839SBorislav Petkov /* 2011e1069839SBorislav Petkov * Workaround for: 2012e1069839SBorislav Petkov * Intel Errata AAK100 (model 26) 2013e1069839SBorislav Petkov * Intel Errata AAP53 (model 30) 2014e1069839SBorislav Petkov * Intel Errata BD53 (model 44) 2015e1069839SBorislav Petkov * 2016e1069839SBorislav Petkov * The official story: 2017e1069839SBorislav Petkov * These chips need to be 'reset' when adding counters by programming the 2018e1069839SBorislav Petkov * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2019e1069839SBorislav Petkov * in sequence on the same PMC or on different PMCs. 2020e1069839SBorislav Petkov * 2021e1069839SBorislav Petkov * In practise it appears some of these events do in fact count, and 2022a97673a1SIngo Molnar * we need to program all 4 events. 2023e1069839SBorislav Petkov */ 2024e1069839SBorislav Petkov static void intel_pmu_nhm_workaround(void) 2025e1069839SBorislav Petkov { 2026e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2027e1069839SBorislav Petkov static const unsigned long nhm_magic[4] = { 2028e1069839SBorislav Petkov 0x4300B5, 2029e1069839SBorislav Petkov 0x4300D2, 2030e1069839SBorislav Petkov 0x4300B1, 2031e1069839SBorislav Petkov 0x4300B1 2032e1069839SBorislav Petkov }; 2033e1069839SBorislav Petkov struct perf_event *event; 2034e1069839SBorislav Petkov int i; 2035e1069839SBorislav Petkov 2036e1069839SBorislav Petkov /* 2037e1069839SBorislav Petkov * The Errata requires below steps: 2038e1069839SBorislav Petkov * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2039e1069839SBorislav Petkov * 2) Configure 4 PERFEVTSELx with the magic events and clear 2040e1069839SBorislav Petkov * the corresponding PMCx; 2041e1069839SBorislav Petkov * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2042e1069839SBorislav Petkov * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2043e1069839SBorislav Petkov * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2044e1069839SBorislav Petkov */ 2045e1069839SBorislav Petkov 2046e1069839SBorislav Petkov /* 2047e1069839SBorislav Petkov * The real steps we choose are a little different from above. 2048e1069839SBorislav Petkov * A) To reduce MSR operations, we don't run step 1) as they 2049e1069839SBorislav Petkov * are already cleared before this function is called; 2050e1069839SBorislav Petkov * B) Call x86_perf_event_update to save PMCx before configuring 2051e1069839SBorislav Petkov * PERFEVTSELx with magic number; 2052e1069839SBorislav Petkov * C) With step 5), we do clear only when the PERFEVTSELx is 2053e1069839SBorislav Petkov * not used currently. 2054e1069839SBorislav Petkov * D) Call x86_perf_event_set_period to restore PMCx; 2055e1069839SBorislav Petkov */ 2056e1069839SBorislav Petkov 2057e1069839SBorislav Petkov /* We always operate 4 pairs of PERF Counters */ 2058e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2059e1069839SBorislav Petkov event = cpuc->events[i]; 2060e1069839SBorislav Petkov if (event) 2061e1069839SBorislav Petkov x86_perf_event_update(event); 2062e1069839SBorislav Petkov } 2063e1069839SBorislav Petkov 2064e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2065e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2066e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2067e1069839SBorislav Petkov } 2068e1069839SBorislav Petkov 2069e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2070e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2071e1069839SBorislav Petkov 2072e1069839SBorislav Petkov for (i = 0; i < 4; i++) { 2073e1069839SBorislav Petkov event = cpuc->events[i]; 2074e1069839SBorislav Petkov 2075e1069839SBorislav Petkov if (event) { 2076e1069839SBorislav Petkov x86_perf_event_set_period(event); 2077e1069839SBorislav Petkov __x86_pmu_enable_event(&event->hw, 2078e1069839SBorislav Petkov ARCH_PERFMON_EVENTSEL_ENABLE); 2079e1069839SBorislav Petkov } else 2080e1069839SBorislav Petkov wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2081e1069839SBorislav Petkov } 2082e1069839SBorislav Petkov } 2083e1069839SBorislav Petkov 2084e1069839SBorislav Petkov static void intel_pmu_nhm_enable_all(int added) 2085e1069839SBorislav Petkov { 2086e1069839SBorislav Petkov if (added) 2087e1069839SBorislav Petkov intel_pmu_nhm_workaround(); 2088e1069839SBorislav Petkov intel_pmu_enable_all(added); 2089e1069839SBorislav Petkov } 2090e1069839SBorislav Petkov 2091400816f6SPeter Zijlstra (Intel) static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2092400816f6SPeter Zijlstra (Intel) { 2093400816f6SPeter Zijlstra (Intel) u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2094400816f6SPeter Zijlstra (Intel) 2095400816f6SPeter Zijlstra (Intel) if (cpuc->tfa_shadow != val) { 2096400816f6SPeter Zijlstra (Intel) cpuc->tfa_shadow = val; 2097400816f6SPeter Zijlstra (Intel) wrmsrl(MSR_TSX_FORCE_ABORT, val); 2098400816f6SPeter Zijlstra (Intel) } 2099400816f6SPeter Zijlstra (Intel) } 2100400816f6SPeter Zijlstra (Intel) 2101400816f6SPeter Zijlstra (Intel) static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2102400816f6SPeter Zijlstra (Intel) { 2103400816f6SPeter Zijlstra (Intel) /* 2104400816f6SPeter Zijlstra (Intel) * We're going to use PMC3, make sure TFA is set before we touch it. 2105400816f6SPeter Zijlstra (Intel) */ 21061a81542aSPeter Zijlstra if (cntr == 3) 2107400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, true); 2108400816f6SPeter Zijlstra (Intel) } 2109400816f6SPeter Zijlstra (Intel) 2110400816f6SPeter Zijlstra (Intel) static void intel_tfa_pmu_enable_all(int added) 2111400816f6SPeter Zijlstra (Intel) { 2112400816f6SPeter Zijlstra (Intel) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2113400816f6SPeter Zijlstra (Intel) 2114400816f6SPeter Zijlstra (Intel) /* 2115400816f6SPeter Zijlstra (Intel) * If we find PMC3 is no longer used when we enable the PMU, we can 2116400816f6SPeter Zijlstra (Intel) * clear TFA. 2117400816f6SPeter Zijlstra (Intel) */ 2118400816f6SPeter Zijlstra (Intel) if (!test_bit(3, cpuc->active_mask)) 2119400816f6SPeter Zijlstra (Intel) intel_set_tfa(cpuc, false); 2120400816f6SPeter Zijlstra (Intel) 2121400816f6SPeter Zijlstra (Intel) intel_pmu_enable_all(added); 2122400816f6SPeter Zijlstra (Intel) } 2123400816f6SPeter Zijlstra (Intel) 2124af3bdb99SAndi Kleen static void enable_counter_freeze(void) 2125af3bdb99SAndi Kleen { 2126af3bdb99SAndi Kleen update_debugctlmsr(get_debugctlmsr() | 2127af3bdb99SAndi Kleen DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2128af3bdb99SAndi Kleen } 2129af3bdb99SAndi Kleen 2130af3bdb99SAndi Kleen static void disable_counter_freeze(void) 2131af3bdb99SAndi Kleen { 2132af3bdb99SAndi Kleen update_debugctlmsr(get_debugctlmsr() & 2133af3bdb99SAndi Kleen ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2134af3bdb99SAndi Kleen } 2135af3bdb99SAndi Kleen 2136e1069839SBorislav Petkov static inline u64 intel_pmu_get_status(void) 2137e1069839SBorislav Petkov { 2138e1069839SBorislav Petkov u64 status; 2139e1069839SBorislav Petkov 2140e1069839SBorislav Petkov rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2141e1069839SBorislav Petkov 2142e1069839SBorislav Petkov return status; 2143e1069839SBorislav Petkov } 2144e1069839SBorislav Petkov 2145e1069839SBorislav Petkov static inline void intel_pmu_ack_status(u64 ack) 2146e1069839SBorislav Petkov { 2147e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2148e1069839SBorislav Petkov } 2149e1069839SBorislav Petkov 2150027440b5SLike Xu static inline bool event_is_checkpointed(struct perf_event *event) 2151e1069839SBorislav Petkov { 2152027440b5SLike Xu return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2153027440b5SLike Xu } 2154027440b5SLike Xu 2155027440b5SLike Xu static inline void intel_set_masks(struct perf_event *event, int idx) 2156027440b5SLike Xu { 2157027440b5SLike Xu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2158027440b5SLike Xu 2159027440b5SLike Xu if (event->attr.exclude_host) 2160027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2161027440b5SLike Xu if (event->attr.exclude_guest) 2162027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2163027440b5SLike Xu if (event_is_checkpointed(event)) 2164027440b5SLike Xu __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2165027440b5SLike Xu } 2166027440b5SLike Xu 2167027440b5SLike Xu static inline void intel_clear_masks(struct perf_event *event, int idx) 2168027440b5SLike Xu { 2169027440b5SLike Xu struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2170027440b5SLike Xu 2171027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2172027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2173027440b5SLike Xu __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2174027440b5SLike Xu } 2175027440b5SLike Xu 2176027440b5SLike Xu static void intel_pmu_disable_fixed(struct perf_event *event) 2177027440b5SLike Xu { 2178027440b5SLike Xu struct hw_perf_event *hwc = &event->hw; 2179e1069839SBorislav Petkov u64 ctrl_val, mask; 21807b2c05a1SKan Liang int idx = hwc->idx; 2181e1069839SBorislav Petkov 21827b2c05a1SKan Liang if (is_topdown_idx(idx)) { 21837b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2184e1069839SBorislav Petkov 21857b2c05a1SKan Liang /* 21867b2c05a1SKan Liang * When there are other active TopDown events, 21877b2c05a1SKan Liang * don't disable the fixed counter 3. 21887b2c05a1SKan Liang */ 21897b2c05a1SKan Liang if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 21907b2c05a1SKan Liang return; 21917b2c05a1SKan Liang idx = INTEL_PMC_IDX_FIXED_SLOTS; 21927b2c05a1SKan Liang } 21937b2c05a1SKan Liang 21947b2c05a1SKan Liang intel_clear_masks(event, idx); 21957b2c05a1SKan Liang 21967b2c05a1SKan Liang mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2197e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2198e1069839SBorislav Petkov ctrl_val &= ~mask; 2199e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2200e1069839SBorislav Petkov } 2201e1069839SBorislav Petkov 2202e1069839SBorislav Petkov static void intel_pmu_disable_event(struct perf_event *event) 2203e1069839SBorislav Petkov { 2204e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2205027440b5SLike Xu int idx = hwc->idx; 2206e1069839SBorislav Petkov 220758da7dbeSKan Liang switch (idx) { 220858da7dbeSKan Liang case 0 ... INTEL_PMC_IDX_FIXED - 1: 2209027440b5SLike Xu intel_clear_masks(event, idx); 2210027440b5SLike Xu x86_pmu_disable_event(event); 221158da7dbeSKan Liang break; 221258da7dbeSKan Liang case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 22137b2c05a1SKan Liang case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2214027440b5SLike Xu intel_pmu_disable_fixed(event); 221558da7dbeSKan Liang break; 221658da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_BTS: 2217e1069839SBorislav Petkov intel_pmu_disable_bts(); 2218e1069839SBorislav Petkov intel_pmu_drain_bts_buffer(); 221958da7dbeSKan Liang return; 222058da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_VLBR: 2221e1ad1ac2SLike Xu intel_clear_masks(event, idx); 222258da7dbeSKan Liang break; 222358da7dbeSKan Liang default: 222458da7dbeSKan Liang intel_clear_masks(event, idx); 222558da7dbeSKan Liang pr_warn("Failed to disable the event with invalid index %d\n", 222658da7dbeSKan Liang idx); 222758da7dbeSKan Liang return; 222858da7dbeSKan Liang } 2229e1069839SBorislav Petkov 22306f55967aSJiri Olsa /* 22316f55967aSJiri Olsa * Needs to be called after x86_pmu_disable_event, 22326f55967aSJiri Olsa * so we don't trigger the event without PEBS bit set. 22336f55967aSJiri Olsa */ 22346f55967aSJiri Olsa if (unlikely(event->attr.precise_ip)) 22356f55967aSJiri Olsa intel_pmu_pebs_disable(event); 2236e1069839SBorislav Petkov } 2237e1069839SBorislav Petkov 223868f7082fSPeter Zijlstra static void intel_pmu_del_event(struct perf_event *event) 223968f7082fSPeter Zijlstra { 224068f7082fSPeter Zijlstra if (needs_branch_stack(event)) 224168f7082fSPeter Zijlstra intel_pmu_lbr_del(event); 224268f7082fSPeter Zijlstra if (event->attr.precise_ip) 224368f7082fSPeter Zijlstra intel_pmu_pebs_del(event); 224468f7082fSPeter Zijlstra } 224568f7082fSPeter Zijlstra 224659a854e2SKan Liang static int icl_set_topdown_event_period(struct perf_event *event) 224759a854e2SKan Liang { 224859a854e2SKan Liang struct hw_perf_event *hwc = &event->hw; 224959a854e2SKan Liang s64 left = local64_read(&hwc->period_left); 225059a854e2SKan Liang 225159a854e2SKan Liang /* 225259a854e2SKan Liang * The values in PERF_METRICS MSR are derived from fixed counter 3. 225359a854e2SKan Liang * Software should start both registers, PERF_METRICS and fixed 225459a854e2SKan Liang * counter 3, from zero. 225559a854e2SKan Liang * Clear PERF_METRICS and Fixed counter 3 in initialization. 225659a854e2SKan Liang * After that, both MSRs will be cleared for each read. 225759a854e2SKan Liang * Don't need to clear them again. 225859a854e2SKan Liang */ 225959a854e2SKan Liang if (left == x86_pmu.max_period) { 226059a854e2SKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 226159a854e2SKan Liang wrmsrl(MSR_PERF_METRICS, 0); 22622cb5383bSKan Liang hwc->saved_slots = 0; 22632cb5383bSKan Liang hwc->saved_metric = 0; 22642cb5383bSKan Liang } 22652cb5383bSKan Liang 22662cb5383bSKan Liang if ((hwc->saved_slots) && is_slots_event(event)) { 22672cb5383bSKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 22682cb5383bSKan Liang wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 226959a854e2SKan Liang } 227059a854e2SKan Liang 227159a854e2SKan Liang perf_event_update_userpage(event); 227259a854e2SKan Liang 227359a854e2SKan Liang return 0; 227459a854e2SKan Liang } 227559a854e2SKan Liang 227659a854e2SKan Liang static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 227759a854e2SKan Liang { 227859a854e2SKan Liang u32 val; 227959a854e2SKan Liang 228059a854e2SKan Liang /* 228159a854e2SKan Liang * The metric is reported as an 8bit integer fraction 228259a854e2SKan Liang * suming up to 0xff. 228359a854e2SKan Liang * slots-in-metric = (Metric / 0xff) * slots 228459a854e2SKan Liang */ 228559a854e2SKan Liang val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 228659a854e2SKan Liang return mul_u64_u32_div(slots, val, 0xff); 228759a854e2SKan Liang } 228859a854e2SKan Liang 22892cb5383bSKan Liang static u64 icl_get_topdown_value(struct perf_event *event, 229059a854e2SKan Liang u64 slots, u64 metrics) 229159a854e2SKan Liang { 229259a854e2SKan Liang int idx = event->hw.idx; 229359a854e2SKan Liang u64 delta; 229459a854e2SKan Liang 229559a854e2SKan Liang if (is_metric_idx(idx)) 229659a854e2SKan Liang delta = icl_get_metrics_event_value(metrics, slots, idx); 229759a854e2SKan Liang else 229859a854e2SKan Liang delta = slots; 229959a854e2SKan Liang 23002cb5383bSKan Liang return delta; 23012cb5383bSKan Liang } 23022cb5383bSKan Liang 23032cb5383bSKan Liang static void __icl_update_topdown_event(struct perf_event *event, 23042cb5383bSKan Liang u64 slots, u64 metrics, 23052cb5383bSKan Liang u64 last_slots, u64 last_metrics) 23062cb5383bSKan Liang { 23072cb5383bSKan Liang u64 delta, last = 0; 23082cb5383bSKan Liang 23092cb5383bSKan Liang delta = icl_get_topdown_value(event, slots, metrics); 23102cb5383bSKan Liang if (last_slots) 23112cb5383bSKan Liang last = icl_get_topdown_value(event, last_slots, last_metrics); 23122cb5383bSKan Liang 23132cb5383bSKan Liang /* 23142cb5383bSKan Liang * The 8bit integer fraction of metric may be not accurate, 23152cb5383bSKan Liang * especially when the changes is very small. 23162cb5383bSKan Liang * For example, if only a few bad_spec happens, the fraction 23172cb5383bSKan Liang * may be reduced from 1 to 0. If so, the bad_spec event value 23182cb5383bSKan Liang * will be 0 which is definitely less than the last value. 23192cb5383bSKan Liang * Avoid update event->count for this case. 23202cb5383bSKan Liang */ 23212cb5383bSKan Liang if (delta > last) { 23222cb5383bSKan Liang delta -= last; 232359a854e2SKan Liang local64_add(delta, &event->count); 232459a854e2SKan Liang } 23252cb5383bSKan Liang } 23262cb5383bSKan Liang 23272cb5383bSKan Liang static void update_saved_topdown_regs(struct perf_event *event, 23282cb5383bSKan Liang u64 slots, u64 metrics) 23292cb5383bSKan Liang { 23302cb5383bSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 23312cb5383bSKan Liang struct perf_event *other; 23322cb5383bSKan Liang int idx; 23332cb5383bSKan Liang 23342cb5383bSKan Liang event->hw.saved_slots = slots; 23352cb5383bSKan Liang event->hw.saved_metric = metrics; 23362cb5383bSKan Liang 23372cb5383bSKan Liang for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) { 23382cb5383bSKan Liang if (!is_topdown_idx(idx)) 23392cb5383bSKan Liang continue; 23402cb5383bSKan Liang other = cpuc->events[idx]; 23412cb5383bSKan Liang other->hw.saved_slots = slots; 23422cb5383bSKan Liang other->hw.saved_metric = metrics; 23432cb5383bSKan Liang } 23442cb5383bSKan Liang } 234559a854e2SKan Liang 234659a854e2SKan Liang /* 234759a854e2SKan Liang * Update all active Topdown events. 234859a854e2SKan Liang * 234959a854e2SKan Liang * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 235059a854e2SKan Liang * modify by a NMI. PMU has to be disabled before calling this function. 235159a854e2SKan Liang */ 235259a854e2SKan Liang static u64 icl_update_topdown_event(struct perf_event *event) 235359a854e2SKan Liang { 235459a854e2SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 235559a854e2SKan Liang struct perf_event *other; 235659a854e2SKan Liang u64 slots, metrics; 23572cb5383bSKan Liang bool reset = true; 235859a854e2SKan Liang int idx; 235959a854e2SKan Liang 236059a854e2SKan Liang /* read Fixed counter 3 */ 236159a854e2SKan Liang rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 236259a854e2SKan Liang if (!slots) 236359a854e2SKan Liang return 0; 236459a854e2SKan Liang 236559a854e2SKan Liang /* read PERF_METRICS */ 236659a854e2SKan Liang rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 236759a854e2SKan Liang 236859a854e2SKan Liang for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) { 236959a854e2SKan Liang if (!is_topdown_idx(idx)) 237059a854e2SKan Liang continue; 237159a854e2SKan Liang other = cpuc->events[idx]; 23722cb5383bSKan Liang __icl_update_topdown_event(other, slots, metrics, 23732cb5383bSKan Liang event ? event->hw.saved_slots : 0, 23742cb5383bSKan Liang event ? event->hw.saved_metric : 0); 237559a854e2SKan Liang } 237659a854e2SKan Liang 237759a854e2SKan Liang /* 237859a854e2SKan Liang * Check and update this event, which may have been cleared 237959a854e2SKan Liang * in active_mask e.g. x86_pmu_stop() 238059a854e2SKan Liang */ 23812cb5383bSKan Liang if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 23822cb5383bSKan Liang __icl_update_topdown_event(event, slots, metrics, 23832cb5383bSKan Liang event->hw.saved_slots, 23842cb5383bSKan Liang event->hw.saved_metric); 238559a854e2SKan Liang 23862cb5383bSKan Liang /* 23872cb5383bSKan Liang * In x86_pmu_stop(), the event is cleared in active_mask first, 23882cb5383bSKan Liang * then drain the delta, which indicates context switch for 23892cb5383bSKan Liang * counting. 23902cb5383bSKan Liang * Save metric and slots for context switch. 23912cb5383bSKan Liang * Don't need to reset the PERF_METRICS and Fixed counter 3. 23922cb5383bSKan Liang * Because the values will be restored in next schedule in. 23932cb5383bSKan Liang */ 23942cb5383bSKan Liang update_saved_topdown_regs(event, slots, metrics); 23952cb5383bSKan Liang reset = false; 23962cb5383bSKan Liang } 23972cb5383bSKan Liang 23982cb5383bSKan Liang if (reset) { 239959a854e2SKan Liang /* The fixed counter 3 has to be written before the PERF_METRICS. */ 240059a854e2SKan Liang wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 240159a854e2SKan Liang wrmsrl(MSR_PERF_METRICS, 0); 24022cb5383bSKan Liang if (event) 24032cb5383bSKan Liang update_saved_topdown_regs(event, 0, 0); 24042cb5383bSKan Liang } 240559a854e2SKan Liang 240659a854e2SKan Liang return slots; 240759a854e2SKan Liang } 240859a854e2SKan Liang 24097b2c05a1SKan Liang static void intel_pmu_read_topdown_event(struct perf_event *event) 24107b2c05a1SKan Liang { 24117b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 24127b2c05a1SKan Liang 24137b2c05a1SKan Liang /* Only need to call update_topdown_event() once for group read. */ 24147b2c05a1SKan Liang if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 24157b2c05a1SKan Liang !is_slots_event(event)) 24167b2c05a1SKan Liang return; 24177b2c05a1SKan Liang 24187b2c05a1SKan Liang perf_pmu_disable(event->pmu); 24197b2c05a1SKan Liang x86_pmu.update_topdown_event(event); 24207b2c05a1SKan Liang perf_pmu_enable(event->pmu); 24217b2c05a1SKan Liang } 24227b2c05a1SKan Liang 2423ceb90d9eSKan Liang static void intel_pmu_read_event(struct perf_event *event) 2424ceb90d9eSKan Liang { 2425ceb90d9eSKan Liang if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2426ceb90d9eSKan Liang intel_pmu_auto_reload_read(event); 24277b2c05a1SKan Liang else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 24287b2c05a1SKan Liang intel_pmu_read_topdown_event(event); 2429ceb90d9eSKan Liang else 2430ceb90d9eSKan Liang x86_perf_event_update(event); 2431ceb90d9eSKan Liang } 2432ceb90d9eSKan Liang 24334f08b625SKan Liang static void intel_pmu_enable_fixed(struct perf_event *event) 2434e1069839SBorislav Petkov { 24354f08b625SKan Liang struct hw_perf_event *hwc = &event->hw; 24364f08b625SKan Liang u64 ctrl_val, mask, bits = 0; 24377b2c05a1SKan Liang int idx = hwc->idx; 24387b2c05a1SKan Liang 24397b2c05a1SKan Liang if (is_topdown_idx(idx)) { 24407b2c05a1SKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 24417b2c05a1SKan Liang /* 24427b2c05a1SKan Liang * When there are other active TopDown events, 24437b2c05a1SKan Liang * don't enable the fixed counter 3 again. 24447b2c05a1SKan Liang */ 24457b2c05a1SKan Liang if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 24467b2c05a1SKan Liang return; 24477b2c05a1SKan Liang 24487b2c05a1SKan Liang idx = INTEL_PMC_IDX_FIXED_SLOTS; 24497b2c05a1SKan Liang } 24507b2c05a1SKan Liang 24517b2c05a1SKan Liang intel_set_masks(event, idx); 2452e1069839SBorislav Petkov 2453e1069839SBorislav Petkov /* 24544f08b625SKan Liang * Enable IRQ generation (0x8), if not PEBS, 2455e1069839SBorislav Petkov * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2456e1069839SBorislav Petkov * if requested: 2457e1069839SBorislav Petkov */ 24584f08b625SKan Liang if (!event->attr.precise_ip) 24594f08b625SKan Liang bits |= 0x8; 2460e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2461e1069839SBorislav Petkov bits |= 0x2; 2462e1069839SBorislav Petkov if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2463e1069839SBorislav Petkov bits |= 0x1; 2464e1069839SBorislav Petkov 2465e1069839SBorislav Petkov /* 2466e1069839SBorislav Petkov * ANY bit is supported in v3 and up 2467e1069839SBorislav Petkov */ 2468e1069839SBorislav Petkov if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2469e1069839SBorislav Petkov bits |= 0x4; 2470e1069839SBorislav Petkov 24717b2c05a1SKan Liang idx -= INTEL_PMC_IDX_FIXED; 2472e1069839SBorislav Petkov bits <<= (idx * 4); 2473e1069839SBorislav Petkov mask = 0xfULL << (idx * 4); 2474e1069839SBorislav Petkov 2475c22497f5SKan Liang if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2476c22497f5SKan Liang bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2477c22497f5SKan Liang mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2478c22497f5SKan Liang } 2479c22497f5SKan Liang 2480e1069839SBorislav Petkov rdmsrl(hwc->config_base, ctrl_val); 2481e1069839SBorislav Petkov ctrl_val &= ~mask; 2482e1069839SBorislav Petkov ctrl_val |= bits; 2483e1069839SBorislav Petkov wrmsrl(hwc->config_base, ctrl_val); 2484e1069839SBorislav Petkov } 2485e1069839SBorislav Petkov 2486e1069839SBorislav Petkov static void intel_pmu_enable_event(struct perf_event *event) 2487e1069839SBorislav Petkov { 2488e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 2489027440b5SLike Xu int idx = hwc->idx; 2490e1069839SBorislav Petkov 2491e1069839SBorislav Petkov if (unlikely(event->attr.precise_ip)) 2492e1069839SBorislav Petkov intel_pmu_pebs_enable(event); 2493e1069839SBorislav Petkov 249458da7dbeSKan Liang switch (idx) { 249558da7dbeSKan Liang case 0 ... INTEL_PMC_IDX_FIXED - 1: 2496027440b5SLike Xu intel_set_masks(event, idx); 2497e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 249858da7dbeSKan Liang break; 249958da7dbeSKan Liang case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 25007b2c05a1SKan Liang case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2501027440b5SLike Xu intel_pmu_enable_fixed(event); 250258da7dbeSKan Liang break; 250358da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_BTS: 2504027440b5SLike Xu if (!__this_cpu_read(cpu_hw_events.enabled)) 2505027440b5SLike Xu return; 2506027440b5SLike Xu intel_pmu_enable_bts(hwc->config); 250758da7dbeSKan Liang break; 250858da7dbeSKan Liang case INTEL_PMC_IDX_FIXED_VLBR: 2509e1ad1ac2SLike Xu intel_set_masks(event, idx); 251058da7dbeSKan Liang break; 251158da7dbeSKan Liang default: 251258da7dbeSKan Liang pr_warn("Failed to enable the event with invalid index %d\n", 251358da7dbeSKan Liang idx); 251458da7dbeSKan Liang } 2515e1069839SBorislav Petkov } 2516e1069839SBorislav Petkov 251768f7082fSPeter Zijlstra static void intel_pmu_add_event(struct perf_event *event) 251868f7082fSPeter Zijlstra { 251968f7082fSPeter Zijlstra if (event->attr.precise_ip) 252068f7082fSPeter Zijlstra intel_pmu_pebs_add(event); 252168f7082fSPeter Zijlstra if (needs_branch_stack(event)) 252268f7082fSPeter Zijlstra intel_pmu_lbr_add(event); 252368f7082fSPeter Zijlstra } 252468f7082fSPeter Zijlstra 2525e1069839SBorislav Petkov /* 2526e1069839SBorislav Petkov * Save and restart an expired event. Called by NMI contexts, 2527e1069839SBorislav Petkov * so it has to be careful about preempting normal event ops: 2528e1069839SBorislav Petkov */ 2529e1069839SBorislav Petkov int intel_pmu_save_and_restart(struct perf_event *event) 2530e1069839SBorislav Petkov { 2531e1069839SBorislav Petkov x86_perf_event_update(event); 2532e1069839SBorislav Petkov /* 2533e1069839SBorislav Petkov * For a checkpointed counter always reset back to 0. This 2534e1069839SBorislav Petkov * avoids a situation where the counter overflows, aborts the 2535e1069839SBorislav Petkov * transaction and is then set back to shortly before the 2536e1069839SBorislav Petkov * overflow, and overflows and aborts again. 2537e1069839SBorislav Petkov */ 2538e1069839SBorislav Petkov if (unlikely(event_is_checkpointed(event))) { 2539e1069839SBorislav Petkov /* No race with NMIs because the counter should not be armed */ 2540e1069839SBorislav Petkov wrmsrl(event->hw.event_base, 0); 2541e1069839SBorislav Petkov local64_set(&event->hw.prev_count, 0); 2542e1069839SBorislav Petkov } 2543e1069839SBorislav Petkov return x86_perf_event_set_period(event); 2544e1069839SBorislav Petkov } 2545e1069839SBorislav Petkov 2546e1069839SBorislav Petkov static void intel_pmu_reset(void) 2547e1069839SBorislav Petkov { 2548e1069839SBorislav Petkov struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2549e1069839SBorislav Petkov unsigned long flags; 2550e1069839SBorislav Petkov int idx; 2551e1069839SBorislav Petkov 2552e1069839SBorislav Petkov if (!x86_pmu.num_counters) 2553e1069839SBorislav Petkov return; 2554e1069839SBorislav Petkov 2555e1069839SBorislav Petkov local_irq_save(flags); 2556e1069839SBorislav Petkov 2557e1069839SBorislav Petkov pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2558e1069839SBorislav Petkov 2559e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2560e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2561e1069839SBorislav Petkov wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2562e1069839SBorislav Petkov } 2563e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2564e1069839SBorislav Petkov wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2565e1069839SBorislav Petkov 2566e1069839SBorislav Petkov if (ds) 2567e1069839SBorislav Petkov ds->bts_index = ds->bts_buffer_base; 2568e1069839SBorislav Petkov 2569e1069839SBorislav Petkov /* Ack all overflows and disable fixed counters */ 2570e1069839SBorislav Petkov if (x86_pmu.version >= 2) { 2571e1069839SBorislav Petkov intel_pmu_ack_status(intel_pmu_get_status()); 2572e1069839SBorislav Petkov wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2573e1069839SBorislav Petkov } 2574e1069839SBorislav Petkov 2575e1069839SBorislav Petkov /* Reset LBRs and LBR freezing */ 2576e1069839SBorislav Petkov if (x86_pmu.lbr_nr) { 2577e1069839SBorislav Petkov update_debugctlmsr(get_debugctlmsr() & 2578e1069839SBorislav Petkov ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2579e1069839SBorislav Petkov } 2580e1069839SBorislav Petkov 2581e1069839SBorislav Petkov local_irq_restore(flags); 2582e1069839SBorislav Petkov } 2583e1069839SBorislav Petkov 2584ba12d20eSKan Liang static int handle_pmi_common(struct pt_regs *regs, u64 status) 2585e1069839SBorislav Petkov { 2586e1069839SBorislav Petkov struct perf_sample_data data; 2587ba12d20eSKan Liang struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2588ba12d20eSKan Liang int bit; 2589ba12d20eSKan Liang int handled = 0; 2590e1069839SBorislav Petkov 2591e1069839SBorislav Petkov inc_irq_stat(apic_perf_irqs); 2592e1069839SBorislav Petkov 2593e1069839SBorislav Petkov /* 2594e1069839SBorislav Petkov * Ignore a range of extra bits in status that do not indicate 2595e1069839SBorislav Petkov * overflow by themselves. 2596e1069839SBorislav Petkov */ 2597e1069839SBorislav Petkov status &= ~(GLOBAL_STATUS_COND_CHG | 2598e1069839SBorislav Petkov GLOBAL_STATUS_ASIF | 2599e1069839SBorislav Petkov GLOBAL_STATUS_LBRS_FROZEN); 2600e1069839SBorislav Petkov if (!status) 2601ba12d20eSKan Liang return 0; 2602daa864b8SStephane Eranian /* 2603daa864b8SStephane Eranian * In case multiple PEBS events are sampled at the same time, 2604daa864b8SStephane Eranian * it is possible to have GLOBAL_STATUS bit 62 set indicating 2605daa864b8SStephane Eranian * PEBS buffer overflow and also seeing at most 3 PEBS counters 2606daa864b8SStephane Eranian * having their bits set in the status register. This is a sign 2607daa864b8SStephane Eranian * that there was at least one PEBS record pending at the time 2608daa864b8SStephane Eranian * of the PMU interrupt. PEBS counters must only be processed 2609daa864b8SStephane Eranian * via the drain_pebs() calls and not via the regular sample 2610daa864b8SStephane Eranian * processing loop coming after that the function, otherwise 2611daa864b8SStephane Eranian * phony regular samples may be generated in the sampling buffer 2612daa864b8SStephane Eranian * not marked with the EXACT tag. Another possibility is to have 2613daa864b8SStephane Eranian * one PEBS event and at least one non-PEBS event whic hoverflows 2614daa864b8SStephane Eranian * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2615daa864b8SStephane Eranian * not be set, yet the overflow status bit for the PEBS counter will 2616daa864b8SStephane Eranian * be on Skylake. 2617daa864b8SStephane Eranian * 2618daa864b8SStephane Eranian * To avoid this problem, we systematically ignore the PEBS-enabled 2619daa864b8SStephane Eranian * counters from the GLOBAL_STATUS mask and we always process PEBS 2620daa864b8SStephane Eranian * events via drain_pebs(). 2621daa864b8SStephane Eranian */ 2622ec71a398SKan Liang if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2623ec71a398SKan Liang status &= ~cpuc->pebs_enabled; 2624ec71a398SKan Liang else 2625fd583ad1SKan Liang status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2626e1069839SBorislav Petkov 2627e1069839SBorislav Petkov /* 2628e1069839SBorislav Petkov * PEBS overflow sets bit 62 in the global status register 2629e1069839SBorislav Petkov */ 263060a2a271SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 26316c1c07b3SKan Liang u64 pebs_enabled = cpuc->pebs_enabled; 26326c1c07b3SKan Liang 2633e1069839SBorislav Petkov handled++; 26349dfa9a5cSPeter Zijlstra x86_pmu.drain_pebs(regs, &data); 26358077eca0SStephane Eranian status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 26366c1c07b3SKan Liang 26376c1c07b3SKan Liang /* 26386c1c07b3SKan Liang * PMI throttle may be triggered, which stops the PEBS event. 26396c1c07b3SKan Liang * Although cpuc->pebs_enabled is updated accordingly, the 26406c1c07b3SKan Liang * MSR_IA32_PEBS_ENABLE is not updated. Because the 26416c1c07b3SKan Liang * cpuc->enabled has been forced to 0 in PMI. 26426c1c07b3SKan Liang * Update the MSR if pebs_enabled is changed. 26436c1c07b3SKan Liang */ 26446c1c07b3SKan Liang if (pebs_enabled != cpuc->pebs_enabled) 26456c1c07b3SKan Liang wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2646e1069839SBorislav Petkov } 2647e1069839SBorislav Petkov 2648e1069839SBorislav Petkov /* 2649e1069839SBorislav Petkov * Intel PT 2650e1069839SBorislav Petkov */ 265160a2a271SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2652e1069839SBorislav Petkov handled++; 26538479e04eSLuwei Kang if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 26548479e04eSLuwei Kang perf_guest_cbs->handle_intel_pt_intr)) 26558479e04eSLuwei Kang perf_guest_cbs->handle_intel_pt_intr(); 26568479e04eSLuwei Kang else 2657e1069839SBorislav Petkov intel_pt_interrupt(); 2658e1069839SBorislav Petkov } 2659e1069839SBorislav Petkov 2660e1069839SBorislav Petkov /* 26617b2c05a1SKan Liang * Intel Perf mertrics 26627b2c05a1SKan Liang */ 26637b2c05a1SKan Liang if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 26647b2c05a1SKan Liang handled++; 26657b2c05a1SKan Liang if (x86_pmu.update_topdown_event) 26667b2c05a1SKan Liang x86_pmu.update_topdown_event(NULL); 26677b2c05a1SKan Liang } 26687b2c05a1SKan Liang 26697b2c05a1SKan Liang /* 2670e1069839SBorislav Petkov * Checkpointed counters can lead to 'spurious' PMIs because the 2671e1069839SBorislav Petkov * rollback caused by the PMI will have cleared the overflow status 2672e1069839SBorislav Petkov * bit. Therefore always force probe these counters. 2673e1069839SBorislav Petkov */ 2674e1069839SBorislav Petkov status |= cpuc->intel_cp_status; 2675e1069839SBorislav Petkov 2676e1069839SBorislav Petkov for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2677e1069839SBorislav Petkov struct perf_event *event = cpuc->events[bit]; 2678e1069839SBorislav Petkov 2679e1069839SBorislav Petkov handled++; 2680e1069839SBorislav Petkov 2681e1069839SBorislav Petkov if (!test_bit(bit, cpuc->active_mask)) 2682e1069839SBorislav Petkov continue; 2683e1069839SBorislav Petkov 2684e1069839SBorislav Petkov if (!intel_pmu_save_and_restart(event)) 2685e1069839SBorislav Petkov continue; 2686e1069839SBorislav Petkov 2687e1069839SBorislav Petkov perf_sample_data_init(&data, 0, event->hw.last_period); 2688e1069839SBorislav Petkov 2689e1069839SBorislav Petkov if (has_branch_stack(event)) 2690e1069839SBorislav Petkov data.br_stack = &cpuc->lbr_stack; 2691e1069839SBorislav Petkov 2692e1069839SBorislav Petkov if (perf_event_overflow(event, &data, regs)) 2693e1069839SBorislav Petkov x86_pmu_stop(event, 0); 2694e1069839SBorislav Petkov } 2695e1069839SBorislav Petkov 2696ba12d20eSKan Liang return handled; 2697ba12d20eSKan Liang } 2698ba12d20eSKan Liang 26992a5bf23dSPeter Zijlstra static bool disable_counter_freezing = true; 2700af3bdb99SAndi Kleen static int __init intel_perf_counter_freezing_setup(char *s) 2701af3bdb99SAndi Kleen { 27022a5bf23dSPeter Zijlstra bool res; 27032a5bf23dSPeter Zijlstra 27042a5bf23dSPeter Zijlstra if (kstrtobool(s, &res)) 27052a5bf23dSPeter Zijlstra return -EINVAL; 27062a5bf23dSPeter Zijlstra 27072a5bf23dSPeter Zijlstra disable_counter_freezing = !res; 2708af3bdb99SAndi Kleen return 1; 2709af3bdb99SAndi Kleen } 27102a5bf23dSPeter Zijlstra __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup); 2711af3bdb99SAndi Kleen 2712af3bdb99SAndi Kleen /* 2713af3bdb99SAndi Kleen * Simplified handler for Arch Perfmon v4: 2714af3bdb99SAndi Kleen * - We rely on counter freezing/unfreezing to enable/disable the PMU. 2715af3bdb99SAndi Kleen * This is done automatically on PMU ack. 2716af3bdb99SAndi Kleen * - Ack the PMU only after the APIC. 2717af3bdb99SAndi Kleen */ 2718af3bdb99SAndi Kleen 2719af3bdb99SAndi Kleen static int intel_pmu_handle_irq_v4(struct pt_regs *regs) 2720af3bdb99SAndi Kleen { 2721af3bdb99SAndi Kleen struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2722af3bdb99SAndi Kleen int handled = 0; 2723af3bdb99SAndi Kleen bool bts = false; 2724af3bdb99SAndi Kleen u64 status; 2725af3bdb99SAndi Kleen int pmu_enabled = cpuc->enabled; 2726af3bdb99SAndi Kleen int loops = 0; 2727af3bdb99SAndi Kleen 2728af3bdb99SAndi Kleen /* PMU has been disabled because of counter freezing */ 2729af3bdb99SAndi Kleen cpuc->enabled = 0; 2730af3bdb99SAndi Kleen if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2731af3bdb99SAndi Kleen bts = true; 2732af3bdb99SAndi Kleen intel_bts_disable_local(); 2733af3bdb99SAndi Kleen handled = intel_pmu_drain_bts_buffer(); 2734af3bdb99SAndi Kleen handled += intel_bts_interrupt(); 2735af3bdb99SAndi Kleen } 2736af3bdb99SAndi Kleen status = intel_pmu_get_status(); 2737af3bdb99SAndi Kleen if (!status) 2738af3bdb99SAndi Kleen goto done; 2739af3bdb99SAndi Kleen again: 2740af3bdb99SAndi Kleen intel_pmu_lbr_read(); 2741af3bdb99SAndi Kleen if (++loops > 100) { 2742af3bdb99SAndi Kleen static bool warned; 2743af3bdb99SAndi Kleen 2744af3bdb99SAndi Kleen if (!warned) { 2745af3bdb99SAndi Kleen WARN(1, "perfevents: irq loop stuck!\n"); 2746af3bdb99SAndi Kleen perf_event_print_debug(); 2747af3bdb99SAndi Kleen warned = true; 2748af3bdb99SAndi Kleen } 2749af3bdb99SAndi Kleen intel_pmu_reset(); 2750af3bdb99SAndi Kleen goto done; 2751af3bdb99SAndi Kleen } 2752af3bdb99SAndi Kleen 2753af3bdb99SAndi Kleen 2754af3bdb99SAndi Kleen handled += handle_pmi_common(regs, status); 2755af3bdb99SAndi Kleen done: 2756af3bdb99SAndi Kleen /* Ack the PMI in the APIC */ 2757af3bdb99SAndi Kleen apic_write(APIC_LVTPC, APIC_DM_NMI); 2758af3bdb99SAndi Kleen 2759af3bdb99SAndi Kleen /* 2760af3bdb99SAndi Kleen * The counters start counting immediately while ack the status. 2761af3bdb99SAndi Kleen * Make it as close as possible to IRET. This avoids bogus 2762af3bdb99SAndi Kleen * freezing on Skylake CPUs. 2763af3bdb99SAndi Kleen */ 2764af3bdb99SAndi Kleen if (status) { 2765af3bdb99SAndi Kleen intel_pmu_ack_status(status); 2766af3bdb99SAndi Kleen } else { 2767af3bdb99SAndi Kleen /* 2768af3bdb99SAndi Kleen * CPU may issues two PMIs very close to each other. 2769af3bdb99SAndi Kleen * When the PMI handler services the first one, the 2770af3bdb99SAndi Kleen * GLOBAL_STATUS is already updated to reflect both. 2771af3bdb99SAndi Kleen * When it IRETs, the second PMI is immediately 2772af3bdb99SAndi Kleen * handled and it sees clear status. At the meantime, 2773af3bdb99SAndi Kleen * there may be a third PMI, because the freezing bit 2774af3bdb99SAndi Kleen * isn't set since the ack in first PMI handlers. 2775af3bdb99SAndi Kleen * Double check if there is more work to be done. 2776af3bdb99SAndi Kleen */ 2777af3bdb99SAndi Kleen status = intel_pmu_get_status(); 2778af3bdb99SAndi Kleen if (status) 2779af3bdb99SAndi Kleen goto again; 2780af3bdb99SAndi Kleen } 2781af3bdb99SAndi Kleen 2782af3bdb99SAndi Kleen if (bts) 2783af3bdb99SAndi Kleen intel_bts_enable_local(); 2784af3bdb99SAndi Kleen cpuc->enabled = pmu_enabled; 2785af3bdb99SAndi Kleen return handled; 2786af3bdb99SAndi Kleen } 2787af3bdb99SAndi Kleen 2788ba12d20eSKan Liang /* 2789ba12d20eSKan Liang * This handler is triggered by the local APIC, so the APIC IRQ handling 2790ba12d20eSKan Liang * rules apply: 2791ba12d20eSKan Liang */ 2792ba12d20eSKan Liang static int intel_pmu_handle_irq(struct pt_regs *regs) 2793ba12d20eSKan Liang { 2794ba12d20eSKan Liang struct cpu_hw_events *cpuc; 2795ba12d20eSKan Liang int loops; 2796ba12d20eSKan Liang u64 status; 2797ba12d20eSKan Liang int handled; 2798ba12d20eSKan Liang int pmu_enabled; 2799ba12d20eSKan Liang 2800ba12d20eSKan Liang cpuc = this_cpu_ptr(&cpu_hw_events); 2801ba12d20eSKan Liang 2802ba12d20eSKan Liang /* 2803ba12d20eSKan Liang * Save the PMU state. 2804ba12d20eSKan Liang * It needs to be restored when leaving the handler. 2805ba12d20eSKan Liang */ 2806ba12d20eSKan Liang pmu_enabled = cpuc->enabled; 2807ba12d20eSKan Liang /* 2808ba12d20eSKan Liang * No known reason to not always do late ACK, 2809ba12d20eSKan Liang * but just in case do it opt-in. 2810ba12d20eSKan Liang */ 2811ba12d20eSKan Liang if (!x86_pmu.late_ack) 2812ba12d20eSKan Liang apic_write(APIC_LVTPC, APIC_DM_NMI); 2813ba12d20eSKan Liang intel_bts_disable_local(); 2814ba12d20eSKan Liang cpuc->enabled = 0; 2815ba12d20eSKan Liang __intel_pmu_disable_all(); 2816ba12d20eSKan Liang handled = intel_pmu_drain_bts_buffer(); 2817ba12d20eSKan Liang handled += intel_bts_interrupt(); 2818ba12d20eSKan Liang status = intel_pmu_get_status(); 2819ba12d20eSKan Liang if (!status) 2820ba12d20eSKan Liang goto done; 2821ba12d20eSKan Liang 2822ba12d20eSKan Liang loops = 0; 2823ba12d20eSKan Liang again: 2824ba12d20eSKan Liang intel_pmu_lbr_read(); 2825ba12d20eSKan Liang intel_pmu_ack_status(status); 2826ba12d20eSKan Liang if (++loops > 100) { 2827ba12d20eSKan Liang static bool warned; 2828ba12d20eSKan Liang 2829ba12d20eSKan Liang if (!warned) { 2830ba12d20eSKan Liang WARN(1, "perfevents: irq loop stuck!\n"); 2831ba12d20eSKan Liang perf_event_print_debug(); 2832ba12d20eSKan Liang warned = true; 2833ba12d20eSKan Liang } 2834ba12d20eSKan Liang intel_pmu_reset(); 2835ba12d20eSKan Liang goto done; 2836ba12d20eSKan Liang } 2837ba12d20eSKan Liang 2838ba12d20eSKan Liang handled += handle_pmi_common(regs, status); 2839ba12d20eSKan Liang 2840e1069839SBorislav Petkov /* 2841e1069839SBorislav Petkov * Repeat if there is more work to be done: 2842e1069839SBorislav Petkov */ 2843e1069839SBorislav Petkov status = intel_pmu_get_status(); 2844e1069839SBorislav Petkov if (status) 2845e1069839SBorislav Petkov goto again; 2846e1069839SBorislav Petkov 2847e1069839SBorislav Petkov done: 2848c3d266c8SKan Liang /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 284982d71ed0SKan Liang cpuc->enabled = pmu_enabled; 285082d71ed0SKan Liang if (pmu_enabled) 2851e1069839SBorislav Petkov __intel_pmu_enable_all(0, true); 2852cecf6235SAlexander Shishkin intel_bts_enable_local(); 2853c3d266c8SKan Liang 2854e1069839SBorislav Petkov /* 2855e1069839SBorislav Petkov * Only unmask the NMI after the overflow counters 2856e1069839SBorislav Petkov * have been reset. This avoids spurious NMIs on 2857e1069839SBorislav Petkov * Haswell CPUs. 2858e1069839SBorislav Petkov */ 2859e1069839SBorislav Petkov if (x86_pmu.late_ack) 2860e1069839SBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI); 2861e1069839SBorislav Petkov return handled; 2862e1069839SBorislav Petkov } 2863e1069839SBorislav Petkov 2864e1069839SBorislav Petkov static struct event_constraint * 2865e1069839SBorislav Petkov intel_bts_constraints(struct perf_event *event) 2866e1069839SBorislav Petkov { 286767266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) 2868e1069839SBorislav Petkov return &bts_constraint; 2869e1069839SBorislav Petkov 2870e1069839SBorislav Petkov return NULL; 2871e1069839SBorislav Petkov } 2872e1069839SBorislav Petkov 2873097e4311SLike Xu /* 2874097e4311SLike Xu * Note: matches a fake event, like Fixed2. 2875097e4311SLike Xu */ 2876097e4311SLike Xu static struct event_constraint * 2877097e4311SLike Xu intel_vlbr_constraints(struct perf_event *event) 2878097e4311SLike Xu { 2879097e4311SLike Xu struct event_constraint *c = &vlbr_constraint; 2880097e4311SLike Xu 2881097e4311SLike Xu if (unlikely(constraint_match(c, event->hw.config))) 2882097e4311SLike Xu return c; 2883097e4311SLike Xu 2884097e4311SLike Xu return NULL; 2885097e4311SLike Xu } 2886097e4311SLike Xu 2887e1069839SBorislav Petkov static int intel_alt_er(int idx, u64 config) 2888e1069839SBorislav Petkov { 2889e1069839SBorislav Petkov int alt_idx = idx; 2890e1069839SBorislav Petkov 2891e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2892e1069839SBorislav Petkov return idx; 2893e1069839SBorislav Petkov 2894e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) 2895e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_1; 2896e1069839SBorislav Petkov 2897e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_1) 2898e1069839SBorislav Petkov alt_idx = EXTRA_REG_RSP_0; 2899e1069839SBorislav Petkov 2900e1069839SBorislav Petkov if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2901e1069839SBorislav Petkov return idx; 2902e1069839SBorislav Petkov 2903e1069839SBorislav Petkov return alt_idx; 2904e1069839SBorislav Petkov } 2905e1069839SBorislav Petkov 2906e1069839SBorislav Petkov static void intel_fixup_er(struct perf_event *event, int idx) 2907e1069839SBorislav Petkov { 2908e1069839SBorislav Petkov event->hw.extra_reg.idx = idx; 2909e1069839SBorislav Petkov 2910e1069839SBorislav Petkov if (idx == EXTRA_REG_RSP_0) { 2911e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2912e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2913e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2914e1069839SBorislav Petkov } else if (idx == EXTRA_REG_RSP_1) { 2915e1069839SBorislav Petkov event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2916e1069839SBorislav Petkov event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2917e1069839SBorislav Petkov event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2918e1069839SBorislav Petkov } 2919e1069839SBorislav Petkov } 2920e1069839SBorislav Petkov 2921e1069839SBorislav Petkov /* 2922e1069839SBorislav Petkov * manage allocation of shared extra msr for certain events 2923e1069839SBorislav Petkov * 2924e1069839SBorislav Petkov * sharing can be: 2925e1069839SBorislav Petkov * per-cpu: to be shared between the various events on a single PMU 2926e1069839SBorislav Petkov * per-core: per-cpu + shared by HT threads 2927e1069839SBorislav Petkov */ 2928e1069839SBorislav Petkov static struct event_constraint * 2929e1069839SBorislav Petkov __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2930e1069839SBorislav Petkov struct perf_event *event, 2931e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 2932e1069839SBorislav Petkov { 2933e1069839SBorislav Petkov struct event_constraint *c = &emptyconstraint; 2934e1069839SBorislav Petkov struct er_account *era; 2935e1069839SBorislav Petkov unsigned long flags; 2936e1069839SBorislav Petkov int idx = reg->idx; 2937e1069839SBorislav Petkov 2938e1069839SBorislav Petkov /* 2939e1069839SBorislav Petkov * reg->alloc can be set due to existing state, so for fake cpuc we 2940e1069839SBorislav Petkov * need to ignore this, otherwise we might fail to allocate proper fake 2941e1069839SBorislav Petkov * state for this extra reg constraint. Also see the comment below. 2942e1069839SBorislav Petkov */ 2943e1069839SBorislav Petkov if (reg->alloc && !cpuc->is_fake) 2944e1069839SBorislav Petkov return NULL; /* call x86_get_event_constraint() */ 2945e1069839SBorislav Petkov 2946e1069839SBorislav Petkov again: 2947e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[idx]; 2948e1069839SBorislav Petkov /* 2949e1069839SBorislav Petkov * we use spin_lock_irqsave() to avoid lockdep issues when 2950e1069839SBorislav Petkov * passing a fake cpuc 2951e1069839SBorislav Petkov */ 2952e1069839SBorislav Petkov raw_spin_lock_irqsave(&era->lock, flags); 2953e1069839SBorislav Petkov 2954e1069839SBorislav Petkov if (!atomic_read(&era->ref) || era->config == reg->config) { 2955e1069839SBorislav Petkov 2956e1069839SBorislav Petkov /* 2957e1069839SBorislav Petkov * If its a fake cpuc -- as per validate_{group,event}() we 2958e1069839SBorislav Petkov * shouldn't touch event state and we can avoid doing so 2959e1069839SBorislav Petkov * since both will only call get_event_constraints() once 2960e1069839SBorislav Petkov * on each event, this avoids the need for reg->alloc. 2961e1069839SBorislav Petkov * 2962e1069839SBorislav Petkov * Not doing the ER fixup will only result in era->reg being 2963e1069839SBorislav Petkov * wrong, but since we won't actually try and program hardware 2964e1069839SBorislav Petkov * this isn't a problem either. 2965e1069839SBorislav Petkov */ 2966e1069839SBorislav Petkov if (!cpuc->is_fake) { 2967e1069839SBorislav Petkov if (idx != reg->idx) 2968e1069839SBorislav Petkov intel_fixup_er(event, idx); 2969e1069839SBorislav Petkov 2970e1069839SBorislav Petkov /* 2971e1069839SBorislav Petkov * x86_schedule_events() can call get_event_constraints() 2972e1069839SBorislav Petkov * multiple times on events in the case of incremental 2973e1069839SBorislav Petkov * scheduling(). reg->alloc ensures we only do the ER 2974e1069839SBorislav Petkov * allocation once. 2975e1069839SBorislav Petkov */ 2976e1069839SBorislav Petkov reg->alloc = 1; 2977e1069839SBorislav Petkov } 2978e1069839SBorislav Petkov 2979e1069839SBorislav Petkov /* lock in msr value */ 2980e1069839SBorislav Petkov era->config = reg->config; 2981e1069839SBorislav Petkov era->reg = reg->reg; 2982e1069839SBorislav Petkov 2983e1069839SBorislav Petkov /* one more user */ 2984e1069839SBorislav Petkov atomic_inc(&era->ref); 2985e1069839SBorislav Petkov 2986e1069839SBorislav Petkov /* 2987e1069839SBorislav Petkov * need to call x86_get_event_constraint() 2988e1069839SBorislav Petkov * to check if associated event has constraints 2989e1069839SBorislav Petkov */ 2990e1069839SBorislav Petkov c = NULL; 2991e1069839SBorislav Petkov } else { 2992e1069839SBorislav Petkov idx = intel_alt_er(idx, reg->config); 2993e1069839SBorislav Petkov if (idx != reg->idx) { 2994e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2995e1069839SBorislav Petkov goto again; 2996e1069839SBorislav Petkov } 2997e1069839SBorislav Petkov } 2998e1069839SBorislav Petkov raw_spin_unlock_irqrestore(&era->lock, flags); 2999e1069839SBorislav Petkov 3000e1069839SBorislav Petkov return c; 3001e1069839SBorislav Petkov } 3002e1069839SBorislav Petkov 3003e1069839SBorislav Petkov static void 3004e1069839SBorislav Petkov __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3005e1069839SBorislav Petkov struct hw_perf_event_extra *reg) 3006e1069839SBorislav Petkov { 3007e1069839SBorislav Petkov struct er_account *era; 3008e1069839SBorislav Petkov 3009e1069839SBorislav Petkov /* 3010e1069839SBorislav Petkov * Only put constraint if extra reg was actually allocated. Also takes 3011e1069839SBorislav Petkov * care of event which do not use an extra shared reg. 3012e1069839SBorislav Petkov * 3013e1069839SBorislav Petkov * Also, if this is a fake cpuc we shouldn't touch any event state 3014e1069839SBorislav Petkov * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3015e1069839SBorislav Petkov * either since it'll be thrown out. 3016e1069839SBorislav Petkov */ 3017e1069839SBorislav Petkov if (!reg->alloc || cpuc->is_fake) 3018e1069839SBorislav Petkov return; 3019e1069839SBorislav Petkov 3020e1069839SBorislav Petkov era = &cpuc->shared_regs->regs[reg->idx]; 3021e1069839SBorislav Petkov 3022e1069839SBorislav Petkov /* one fewer user */ 3023e1069839SBorislav Petkov atomic_dec(&era->ref); 3024e1069839SBorislav Petkov 3025e1069839SBorislav Petkov /* allocate again next time */ 3026e1069839SBorislav Petkov reg->alloc = 0; 3027e1069839SBorislav Petkov } 3028e1069839SBorislav Petkov 3029e1069839SBorislav Petkov static struct event_constraint * 3030e1069839SBorislav Petkov intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3031e1069839SBorislav Petkov struct perf_event *event) 3032e1069839SBorislav Petkov { 3033e1069839SBorislav Petkov struct event_constraint *c = NULL, *d; 3034e1069839SBorislav Petkov struct hw_perf_event_extra *xreg, *breg; 3035e1069839SBorislav Petkov 3036e1069839SBorislav Petkov xreg = &event->hw.extra_reg; 3037e1069839SBorislav Petkov if (xreg->idx != EXTRA_REG_NONE) { 3038e1069839SBorislav Petkov c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3039e1069839SBorislav Petkov if (c == &emptyconstraint) 3040e1069839SBorislav Petkov return c; 3041e1069839SBorislav Petkov } 3042e1069839SBorislav Petkov breg = &event->hw.branch_reg; 3043e1069839SBorislav Petkov if (breg->idx != EXTRA_REG_NONE) { 3044e1069839SBorislav Petkov d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3045e1069839SBorislav Petkov if (d == &emptyconstraint) { 3046e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, xreg); 3047e1069839SBorislav Petkov c = d; 3048e1069839SBorislav Petkov } 3049e1069839SBorislav Petkov } 3050e1069839SBorislav Petkov return c; 3051e1069839SBorislav Petkov } 3052e1069839SBorislav Petkov 3053e1069839SBorislav Petkov struct event_constraint * 3054e1069839SBorislav Petkov x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3055e1069839SBorislav Petkov struct perf_event *event) 3056e1069839SBorislav Petkov { 3057e1069839SBorislav Petkov struct event_constraint *c; 3058e1069839SBorislav Petkov 3059e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 3060e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 306163b79f6eSPeter Zijlstra if (constraint_match(c, event->hw.config)) { 3062e1069839SBorislav Petkov event->hw.flags |= c->flags; 3063e1069839SBorislav Petkov return c; 3064e1069839SBorislav Petkov } 3065e1069839SBorislav Petkov } 3066e1069839SBorislav Petkov } 3067e1069839SBorislav Petkov 3068e1069839SBorislav Petkov return &unconstrained; 3069e1069839SBorislav Petkov } 3070e1069839SBorislav Petkov 3071e1069839SBorislav Petkov static struct event_constraint * 3072e1069839SBorislav Petkov __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3073e1069839SBorislav Petkov struct perf_event *event) 3074e1069839SBorislav Petkov { 3075e1069839SBorislav Petkov struct event_constraint *c; 3076e1069839SBorislav Petkov 3077097e4311SLike Xu c = intel_vlbr_constraints(event); 3078097e4311SLike Xu if (c) 3079097e4311SLike Xu return c; 3080097e4311SLike Xu 3081e1069839SBorislav Petkov c = intel_bts_constraints(event); 3082e1069839SBorislav Petkov if (c) 3083e1069839SBorislav Petkov return c; 3084e1069839SBorislav Petkov 3085e1069839SBorislav Petkov c = intel_shared_regs_constraints(cpuc, event); 3086e1069839SBorislav Petkov if (c) 3087e1069839SBorislav Petkov return c; 3088e1069839SBorislav Petkov 3089e1069839SBorislav Petkov c = intel_pebs_constraints(event); 3090e1069839SBorislav Petkov if (c) 3091e1069839SBorislav Petkov return c; 3092e1069839SBorislav Petkov 3093e1069839SBorislav Petkov return x86_get_event_constraints(cpuc, idx, event); 3094e1069839SBorislav Petkov } 3095e1069839SBorislav Petkov 3096e1069839SBorislav Petkov static void 3097e1069839SBorislav Petkov intel_start_scheduling(struct cpu_hw_events *cpuc) 3098e1069839SBorislav Petkov { 3099e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3100e1069839SBorislav Petkov struct intel_excl_states *xl; 3101e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3102e1069839SBorislav Petkov 3103e1069839SBorislav Petkov /* 3104e1069839SBorislav Petkov * nothing needed if in group validation mode 3105e1069839SBorislav Petkov */ 3106e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3107e1069839SBorislav Petkov return; 3108e1069839SBorislav Petkov 3109e1069839SBorislav Petkov /* 3110e1069839SBorislav Petkov * no exclusion needed 3111e1069839SBorislav Petkov */ 3112e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3113e1069839SBorislav Petkov return; 3114e1069839SBorislav Petkov 3115e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3116e1069839SBorislav Petkov 3117e1069839SBorislav Petkov xl->sched_started = true; 3118e1069839SBorislav Petkov /* 3119e1069839SBorislav Petkov * lock shared state until we are done scheduling 3120e1069839SBorislav Petkov * in stop_event_scheduling() 3121e1069839SBorislav Petkov * makes scheduling appear as a transaction 3122e1069839SBorislav Petkov */ 3123e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3124e1069839SBorislav Petkov } 3125e1069839SBorislav Petkov 3126e1069839SBorislav Petkov static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3127e1069839SBorislav Petkov { 3128e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3129e1069839SBorislav Petkov struct event_constraint *c = cpuc->event_constraint[idx]; 3130e1069839SBorislav Petkov struct intel_excl_states *xl; 3131e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3132e1069839SBorislav Petkov 3133e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3134e1069839SBorislav Petkov return; 3135e1069839SBorislav Petkov 3136e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3137e1069839SBorislav Petkov return; 3138e1069839SBorislav Petkov 3139e1069839SBorislav Petkov if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3140e1069839SBorislav Petkov return; 3141e1069839SBorislav Petkov 3142e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3143e1069839SBorislav Petkov 3144e1069839SBorislav Petkov lockdep_assert_held(&excl_cntrs->lock); 3145e1069839SBorislav Petkov 3146e1069839SBorislav Petkov if (c->flags & PERF_X86_EVENT_EXCL) 3147e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3148e1069839SBorislav Petkov else 3149e1069839SBorislav Petkov xl->state[cntr] = INTEL_EXCL_SHARED; 3150e1069839SBorislav Petkov } 3151e1069839SBorislav Petkov 3152e1069839SBorislav Petkov static void 3153e1069839SBorislav Petkov intel_stop_scheduling(struct cpu_hw_events *cpuc) 3154e1069839SBorislav Petkov { 3155e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3156e1069839SBorislav Petkov struct intel_excl_states *xl; 3157e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3158e1069839SBorislav Petkov 3159e1069839SBorislav Petkov /* 3160e1069839SBorislav Petkov * nothing needed if in group validation mode 3161e1069839SBorislav Petkov */ 3162e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3163e1069839SBorislav Petkov return; 3164e1069839SBorislav Petkov /* 3165e1069839SBorislav Petkov * no exclusion needed 3166e1069839SBorislav Petkov */ 3167e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3168e1069839SBorislav Petkov return; 3169e1069839SBorislav Petkov 3170e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3171e1069839SBorislav Petkov 3172e1069839SBorislav Petkov xl->sched_started = false; 3173e1069839SBorislav Petkov /* 3174e1069839SBorislav Petkov * release shared state lock (acquired in intel_start_scheduling()) 3175e1069839SBorislav Petkov */ 3176e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3177e1069839SBorislav Petkov } 3178e1069839SBorislav Petkov 3179e1069839SBorislav Petkov static struct event_constraint * 318011f8b2d6SPeter Zijlstra (Intel) dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 318111f8b2d6SPeter Zijlstra (Intel) { 318211f8b2d6SPeter Zijlstra (Intel) WARN_ON_ONCE(!cpuc->constraint_list); 318311f8b2d6SPeter Zijlstra (Intel) 318411f8b2d6SPeter Zijlstra (Intel) if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 318511f8b2d6SPeter Zijlstra (Intel) struct event_constraint *cx; 318611f8b2d6SPeter Zijlstra (Intel) 318711f8b2d6SPeter Zijlstra (Intel) /* 318811f8b2d6SPeter Zijlstra (Intel) * grab pre-allocated constraint entry 318911f8b2d6SPeter Zijlstra (Intel) */ 319011f8b2d6SPeter Zijlstra (Intel) cx = &cpuc->constraint_list[idx]; 319111f8b2d6SPeter Zijlstra (Intel) 319211f8b2d6SPeter Zijlstra (Intel) /* 319311f8b2d6SPeter Zijlstra (Intel) * initialize dynamic constraint 319411f8b2d6SPeter Zijlstra (Intel) * with static constraint 319511f8b2d6SPeter Zijlstra (Intel) */ 319611f8b2d6SPeter Zijlstra (Intel) *cx = *c; 319711f8b2d6SPeter Zijlstra (Intel) 319811f8b2d6SPeter Zijlstra (Intel) /* 319911f8b2d6SPeter Zijlstra (Intel) * mark constraint as dynamic 320011f8b2d6SPeter Zijlstra (Intel) */ 320111f8b2d6SPeter Zijlstra (Intel) cx->flags |= PERF_X86_EVENT_DYNAMIC; 320211f8b2d6SPeter Zijlstra (Intel) c = cx; 320311f8b2d6SPeter Zijlstra (Intel) } 320411f8b2d6SPeter Zijlstra (Intel) 320511f8b2d6SPeter Zijlstra (Intel) return c; 320611f8b2d6SPeter Zijlstra (Intel) } 320711f8b2d6SPeter Zijlstra (Intel) 320811f8b2d6SPeter Zijlstra (Intel) static struct event_constraint * 3209e1069839SBorislav Petkov intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3210e1069839SBorislav Petkov int idx, struct event_constraint *c) 3211e1069839SBorislav Petkov { 3212e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3213e1069839SBorislav Petkov struct intel_excl_states *xlo; 3214e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3215c090cb70SPeter Zijlstra int is_excl, i, w; 3216e1069839SBorislav Petkov 3217e1069839SBorislav Petkov /* 3218e1069839SBorislav Petkov * validating a group does not require 3219e1069839SBorislav Petkov * enforcing cross-thread exclusion 3220e1069839SBorislav Petkov */ 3221e1069839SBorislav Petkov if (cpuc->is_fake || !is_ht_workaround_enabled()) 3222e1069839SBorislav Petkov return c; 3223e1069839SBorislav Petkov 3224e1069839SBorislav Petkov /* 3225e1069839SBorislav Petkov * no exclusion needed 3226e1069839SBorislav Petkov */ 3227e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3228e1069839SBorislav Petkov return c; 3229e1069839SBorislav Petkov 3230e1069839SBorislav Petkov /* 3231e1069839SBorislav Petkov * because we modify the constraint, we need 3232e1069839SBorislav Petkov * to make a copy. Static constraints come 3233e1069839SBorislav Petkov * from static const tables. 3234e1069839SBorislav Petkov * 3235e1069839SBorislav Petkov * only needed when constraint has not yet 3236e1069839SBorislav Petkov * been cloned (marked dynamic) 3237e1069839SBorislav Petkov */ 323811f8b2d6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 3239e1069839SBorislav Petkov 3240e1069839SBorislav Petkov /* 3241e1069839SBorislav Petkov * From here on, the constraint is dynamic. 3242e1069839SBorislav Petkov * Either it was just allocated above, or it 3243e1069839SBorislav Petkov * was allocated during a earlier invocation 3244e1069839SBorislav Petkov * of this function 3245e1069839SBorislav Petkov */ 3246e1069839SBorislav Petkov 3247e1069839SBorislav Petkov /* 3248e1069839SBorislav Petkov * state of sibling HT 3249e1069839SBorislav Petkov */ 3250e1069839SBorislav Petkov xlo = &excl_cntrs->states[tid ^ 1]; 3251e1069839SBorislav Petkov 3252e1069839SBorislav Petkov /* 3253e1069839SBorislav Petkov * event requires exclusive counter access 3254e1069839SBorislav Petkov * across HT threads 3255e1069839SBorislav Petkov */ 3256e1069839SBorislav Petkov is_excl = c->flags & PERF_X86_EVENT_EXCL; 3257e1069839SBorislav Petkov if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3258e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3259e1069839SBorislav Petkov if (!cpuc->n_excl++) 3260e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3261e1069839SBorislav Petkov } 3262e1069839SBorislav Petkov 3263e1069839SBorislav Petkov /* 3264e1069839SBorislav Petkov * Modify static constraint with current dynamic 3265e1069839SBorislav Petkov * state of thread 3266e1069839SBorislav Petkov * 3267e1069839SBorislav Petkov * EXCLUSIVE: sibling counter measuring exclusive event 3268e1069839SBorislav Petkov * SHARED : sibling counter measuring non-exclusive event 3269e1069839SBorislav Petkov * UNUSED : sibling counter unused 3270e1069839SBorislav Petkov */ 3271c090cb70SPeter Zijlstra w = c->weight; 3272e1069839SBorislav Petkov for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3273e1069839SBorislav Petkov /* 3274e1069839SBorislav Petkov * exclusive event in sibling counter 3275e1069839SBorislav Petkov * our corresponding counter cannot be used 3276e1069839SBorislav Petkov * regardless of our event 3277e1069839SBorislav Petkov */ 3278c090cb70SPeter Zijlstra if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3279e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 3280c090cb70SPeter Zijlstra w--; 3281c090cb70SPeter Zijlstra continue; 3282c090cb70SPeter Zijlstra } 3283e1069839SBorislav Petkov /* 3284e1069839SBorislav Petkov * if measuring an exclusive event, sibling 3285e1069839SBorislav Petkov * measuring non-exclusive, then counter cannot 3286e1069839SBorislav Petkov * be used 3287e1069839SBorislav Petkov */ 3288c090cb70SPeter Zijlstra if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3289e1069839SBorislav Petkov __clear_bit(i, c->idxmsk); 3290c090cb70SPeter Zijlstra w--; 3291c090cb70SPeter Zijlstra continue; 3292e1069839SBorislav Petkov } 3293c090cb70SPeter Zijlstra } 3294e1069839SBorislav Petkov 3295e1069839SBorislav Petkov /* 3296e1069839SBorislav Petkov * if we return an empty mask, then switch 3297e1069839SBorislav Petkov * back to static empty constraint to avoid 3298e1069839SBorislav Petkov * the cost of freeing later on 3299e1069839SBorislav Petkov */ 3300c090cb70SPeter Zijlstra if (!w) 3301e1069839SBorislav Petkov c = &emptyconstraint; 3302e1069839SBorislav Petkov 3303c090cb70SPeter Zijlstra c->weight = w; 3304c090cb70SPeter Zijlstra 3305e1069839SBorislav Petkov return c; 3306e1069839SBorislav Petkov } 3307e1069839SBorislav Petkov 3308e1069839SBorislav Petkov static struct event_constraint * 3309e1069839SBorislav Petkov intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3310e1069839SBorislav Petkov struct perf_event *event) 3311e1069839SBorislav Petkov { 331221d65555SPeter Zijlstra struct event_constraint *c1, *c2; 3313e1069839SBorislav Petkov 3314e1069839SBorislav Petkov c1 = cpuc->event_constraint[idx]; 3315e1069839SBorislav Petkov 3316e1069839SBorislav Petkov /* 3317e1069839SBorislav Petkov * first time only 3318e1069839SBorislav Petkov * - static constraint: no change across incremental scheduling calls 3319e1069839SBorislav Petkov * - dynamic constraint: handled by intel_get_excl_constraints() 3320e1069839SBorislav Petkov */ 3321e1069839SBorislav Petkov c2 = __intel_get_event_constraints(cpuc, idx, event); 3322109717deSPeter Zijlstra if (c1) { 3323109717deSPeter Zijlstra WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3324e1069839SBorislav Petkov bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3325e1069839SBorislav Petkov c1->weight = c2->weight; 3326e1069839SBorislav Petkov c2 = c1; 3327e1069839SBorislav Petkov } 3328e1069839SBorislav Petkov 3329e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3330e1069839SBorislav Petkov return intel_get_excl_constraints(cpuc, event, idx, c2); 3331e1069839SBorislav Petkov 3332e1069839SBorislav Petkov return c2; 3333e1069839SBorislav Petkov } 3334e1069839SBorislav Petkov 3335e1069839SBorislav Petkov static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3336e1069839SBorislav Petkov struct perf_event *event) 3337e1069839SBorislav Petkov { 3338e1069839SBorislav Petkov struct hw_perf_event *hwc = &event->hw; 3339e1069839SBorislav Petkov struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3340e1069839SBorislav Petkov int tid = cpuc->excl_thread_id; 3341e1069839SBorislav Petkov struct intel_excl_states *xl; 3342e1069839SBorislav Petkov 3343e1069839SBorislav Petkov /* 3344e1069839SBorislav Petkov * nothing needed if in group validation mode 3345e1069839SBorislav Petkov */ 3346e1069839SBorislav Petkov if (cpuc->is_fake) 3347e1069839SBorislav Petkov return; 3348e1069839SBorislav Petkov 3349e1069839SBorislav Petkov if (WARN_ON_ONCE(!excl_cntrs)) 3350e1069839SBorislav Petkov return; 3351e1069839SBorislav Petkov 3352e1069839SBorislav Petkov if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3353e1069839SBorislav Petkov hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3354e1069839SBorislav Petkov if (!--cpuc->n_excl) 3355e1069839SBorislav Petkov WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3356e1069839SBorislav Petkov } 3357e1069839SBorislav Petkov 3358e1069839SBorislav Petkov /* 3359e1069839SBorislav Petkov * If event was actually assigned, then mark the counter state as 3360e1069839SBorislav Petkov * unused now. 3361e1069839SBorislav Petkov */ 3362e1069839SBorislav Petkov if (hwc->idx >= 0) { 3363e1069839SBorislav Petkov xl = &excl_cntrs->states[tid]; 3364e1069839SBorislav Petkov 3365e1069839SBorislav Petkov /* 3366e1069839SBorislav Petkov * put_constraint may be called from x86_schedule_events() 3367e1069839SBorislav Petkov * which already has the lock held so here make locking 3368e1069839SBorislav Petkov * conditional. 3369e1069839SBorislav Petkov */ 3370e1069839SBorislav Petkov if (!xl->sched_started) 3371e1069839SBorislav Petkov raw_spin_lock(&excl_cntrs->lock); 3372e1069839SBorislav Petkov 3373e1069839SBorislav Petkov xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3374e1069839SBorislav Petkov 3375e1069839SBorislav Petkov if (!xl->sched_started) 3376e1069839SBorislav Petkov raw_spin_unlock(&excl_cntrs->lock); 3377e1069839SBorislav Petkov } 3378e1069839SBorislav Petkov } 3379e1069839SBorislav Petkov 3380e1069839SBorislav Petkov static void 3381e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3382e1069839SBorislav Petkov struct perf_event *event) 3383e1069839SBorislav Petkov { 3384e1069839SBorislav Petkov struct hw_perf_event_extra *reg; 3385e1069839SBorislav Petkov 3386e1069839SBorislav Petkov reg = &event->hw.extra_reg; 3387e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3388e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3389e1069839SBorislav Petkov 3390e1069839SBorislav Petkov reg = &event->hw.branch_reg; 3391e1069839SBorislav Petkov if (reg->idx != EXTRA_REG_NONE) 3392e1069839SBorislav Petkov __intel_shared_reg_put_constraints(cpuc, reg); 3393e1069839SBorislav Petkov } 3394e1069839SBorislav Petkov 3395e1069839SBorislav Petkov static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3396e1069839SBorislav Petkov struct perf_event *event) 3397e1069839SBorislav Petkov { 3398e1069839SBorislav Petkov intel_put_shared_regs_event_constraints(cpuc, event); 3399e1069839SBorislav Petkov 3400e1069839SBorislav Petkov /* 3401e1069839SBorislav Petkov * is PMU has exclusive counter restrictions, then 3402e1069839SBorislav Petkov * all events are subject to and must call the 3403e1069839SBorislav Petkov * put_excl_constraints() routine 3404e1069839SBorislav Petkov */ 3405e1069839SBorislav Petkov if (cpuc->excl_cntrs) 3406e1069839SBorislav Petkov intel_put_excl_constraints(cpuc, event); 3407e1069839SBorislav Petkov } 3408e1069839SBorislav Petkov 3409e1069839SBorislav Petkov static void intel_pebs_aliases_core2(struct perf_event *event) 3410e1069839SBorislav Petkov { 3411e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3412e1069839SBorislav Petkov /* 3413e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3414e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3415e1069839SBorislav Petkov * 3416e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3417e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.ANY_P 3418e1069839SBorislav Petkov * (0x00c0), which is a PEBS capable event, to get the same 3419e1069839SBorislav Petkov * count. 3420e1069839SBorislav Petkov * 3421e1069839SBorislav Petkov * INST_RETIRED.ANY_P counts the number of cycles that retires 3422e1069839SBorislav Petkov * CNTMASK instructions. By setting CNTMASK to a value (16) 3423e1069839SBorislav Petkov * larger than the maximum number of instructions that can be 3424e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3425e1069839SBorislav Petkov * count all cycles that retire 16 or less instructions, which 3426e1069839SBorislav Petkov * is every cycle. 3427e1069839SBorislav Petkov * 3428e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3429e1069839SBorislav Petkov */ 3430e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3431e1069839SBorislav Petkov 3432e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3433e1069839SBorislav Petkov event->hw.config = alt_config; 3434e1069839SBorislav Petkov } 3435e1069839SBorislav Petkov } 3436e1069839SBorislav Petkov 3437e1069839SBorislav Petkov static void intel_pebs_aliases_snb(struct perf_event *event) 3438e1069839SBorislav Petkov { 3439e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3440e1069839SBorislav Petkov /* 3441e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3442e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3443e1069839SBorislav Petkov * 3444e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3445e1069839SBorislav Petkov * PEBS capable. However we can use UOPS_RETIRED.ALL 3446e1069839SBorislav Petkov * (0x01c2), which is a PEBS capable event, to get the same 3447e1069839SBorislav Petkov * count. 3448e1069839SBorislav Petkov * 3449e1069839SBorislav Petkov * UOPS_RETIRED.ALL counts the number of cycles that retires 3450e1069839SBorislav Petkov * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3451e1069839SBorislav Petkov * larger than the maximum number of micro-ops that can be 3452e1069839SBorislav Petkov * retired per cycle (4) and then inverting the condition, we 3453e1069839SBorislav Petkov * count all cycles that retire 16 or less micro-ops, which 3454e1069839SBorislav Petkov * is every cycle. 3455e1069839SBorislav Petkov * 3456e1069839SBorislav Petkov * Thereby we gain a PEBS capable cycle counter. 3457e1069839SBorislav Petkov */ 3458e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3459e1069839SBorislav Petkov 3460e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3461e1069839SBorislav Petkov event->hw.config = alt_config; 3462e1069839SBorislav Petkov } 3463e1069839SBorislav Petkov } 3464e1069839SBorislav Petkov 3465e1069839SBorislav Petkov static void intel_pebs_aliases_precdist(struct perf_event *event) 3466e1069839SBorislav Petkov { 3467e1069839SBorislav Petkov if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3468e1069839SBorislav Petkov /* 3469e1069839SBorislav Petkov * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3470e1069839SBorislav Petkov * (0x003c) so that we can use it with PEBS. 3471e1069839SBorislav Petkov * 3472e1069839SBorislav Petkov * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3473e1069839SBorislav Petkov * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3474e1069839SBorislav Petkov * (0x01c0), which is a PEBS capable event, to get the same 3475e1069839SBorislav Petkov * count. 3476e1069839SBorislav Petkov * 3477e1069839SBorislav Petkov * The PREC_DIST event has special support to minimize sample 3478e1069839SBorislav Petkov * shadowing effects. One drawback is that it can be 3479e1069839SBorislav Petkov * only programmed on counter 1, but that seems like an 3480e1069839SBorislav Petkov * acceptable trade off. 3481e1069839SBorislav Petkov */ 3482e1069839SBorislav Petkov u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3483e1069839SBorislav Petkov 3484e1069839SBorislav Petkov alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3485e1069839SBorislav Petkov event->hw.config = alt_config; 3486e1069839SBorislav Petkov } 3487e1069839SBorislav Petkov } 3488e1069839SBorislav Petkov 3489e1069839SBorislav Petkov static void intel_pebs_aliases_ivb(struct perf_event *event) 3490e1069839SBorislav Petkov { 3491e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3492e1069839SBorislav Petkov return intel_pebs_aliases_snb(event); 3493e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3494e1069839SBorislav Petkov } 3495e1069839SBorislav Petkov 3496e1069839SBorislav Petkov static void intel_pebs_aliases_skl(struct perf_event *event) 3497e1069839SBorislav Petkov { 3498e1069839SBorislav Petkov if (event->attr.precise_ip < 3) 3499e1069839SBorislav Petkov return intel_pebs_aliases_core2(event); 3500e1069839SBorislav Petkov return intel_pebs_aliases_precdist(event); 3501e1069839SBorislav Petkov } 3502e1069839SBorislav Petkov 3503174afc3eSKan Liang static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3504e1069839SBorislav Petkov { 3505174afc3eSKan Liang unsigned long flags = x86_pmu.large_pebs_flags; 3506e1069839SBorislav Petkov 3507e1069839SBorislav Petkov if (event->attr.use_clockid) 3508e1069839SBorislav Petkov flags &= ~PERF_SAMPLE_TIME; 3509a47ba4d7SAndi Kleen if (!event->attr.exclude_kernel) 3510a47ba4d7SAndi Kleen flags &= ~PERF_SAMPLE_REGS_USER; 35119d5dcc93SKan Liang if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3512a47ba4d7SAndi Kleen flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3513e1069839SBorislav Petkov return flags; 3514e1069839SBorislav Petkov } 3515e1069839SBorislav Petkov 3516ed6101bbSJiri Olsa static int intel_pmu_bts_config(struct perf_event *event) 3517ed6101bbSJiri Olsa { 3518ed6101bbSJiri Olsa struct perf_event_attr *attr = &event->attr; 3519ed6101bbSJiri Olsa 352067266c10SJiri Olsa if (unlikely(intel_pmu_has_bts(event))) { 3521ed6101bbSJiri Olsa /* BTS is not supported by this architecture. */ 3522ed6101bbSJiri Olsa if (!x86_pmu.bts_active) 3523ed6101bbSJiri Olsa return -EOPNOTSUPP; 3524ed6101bbSJiri Olsa 3525ed6101bbSJiri Olsa /* BTS is currently only allowed for user-mode. */ 3526ed6101bbSJiri Olsa if (!attr->exclude_kernel) 3527ed6101bbSJiri Olsa return -EOPNOTSUPP; 3528ed6101bbSJiri Olsa 3529472de49fSJiri Olsa /* BTS is not allowed for precise events. */ 3530472de49fSJiri Olsa if (attr->precise_ip) 3531472de49fSJiri Olsa return -EOPNOTSUPP; 3532472de49fSJiri Olsa 3533ed6101bbSJiri Olsa /* disallow bts if conflicting events are present */ 3534ed6101bbSJiri Olsa if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3535ed6101bbSJiri Olsa return -EBUSY; 3536ed6101bbSJiri Olsa 3537ed6101bbSJiri Olsa event->destroy = hw_perf_lbr_event_destroy; 3538ed6101bbSJiri Olsa } 3539ed6101bbSJiri Olsa 3540ed6101bbSJiri Olsa return 0; 3541ed6101bbSJiri Olsa } 3542ed6101bbSJiri Olsa 3543ed6101bbSJiri Olsa static int core_pmu_hw_config(struct perf_event *event) 3544ed6101bbSJiri Olsa { 3545ed6101bbSJiri Olsa int ret = x86_pmu_hw_config(event); 3546ed6101bbSJiri Olsa 3547ed6101bbSJiri Olsa if (ret) 3548ed6101bbSJiri Olsa return ret; 3549ed6101bbSJiri Olsa 3550ed6101bbSJiri Olsa return intel_pmu_bts_config(event); 3551ed6101bbSJiri Olsa } 3552ed6101bbSJiri Olsa 3553e1069839SBorislav Petkov static int intel_pmu_hw_config(struct perf_event *event) 3554e1069839SBorislav Petkov { 3555e1069839SBorislav Petkov int ret = x86_pmu_hw_config(event); 3556e1069839SBorislav Petkov 3557e1069839SBorislav Petkov if (ret) 3558e1069839SBorislav Petkov return ret; 3559e1069839SBorislav Petkov 3560ed6101bbSJiri Olsa ret = intel_pmu_bts_config(event); 3561ed6101bbSJiri Olsa if (ret) 3562ed6101bbSJiri Olsa return ret; 3563ed6101bbSJiri Olsa 3564e1069839SBorislav Petkov if (event->attr.precise_ip) { 3565c7a28657SStephane Eranian if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3566e1069839SBorislav Petkov event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3567e1069839SBorislav Petkov if (!(event->attr.sample_type & 3568174afc3eSKan Liang ~intel_pmu_large_pebs_flags(event))) 3569174afc3eSKan Liang event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3570e1069839SBorislav Petkov } 3571e1069839SBorislav Petkov if (x86_pmu.pebs_aliases) 3572e1069839SBorislav Petkov x86_pmu.pebs_aliases(event); 35736cbc304fSPeter Zijlstra 35746cbc304fSPeter Zijlstra if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 35756cbc304fSPeter Zijlstra event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3576e1069839SBorislav Petkov } 3577e1069839SBorislav Petkov 3578e1069839SBorislav Petkov if (needs_branch_stack(event)) { 3579e1069839SBorislav Petkov ret = intel_pmu_setup_lbr_filter(event); 3580e1069839SBorislav Petkov if (ret) 3581e1069839SBorislav Petkov return ret; 3582e1069839SBorislav Petkov 3583e1069839SBorislav Petkov /* 3584e1069839SBorislav Petkov * BTS is set up earlier in this path, so don't account twice 3585e1069839SBorislav Petkov */ 358667266c10SJiri Olsa if (!unlikely(intel_pmu_has_bts(event))) { 3587e1069839SBorislav Petkov /* disallow lbr if conflicting events are present */ 3588e1069839SBorislav Petkov if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3589e1069839SBorislav Petkov return -EBUSY; 3590e1069839SBorislav Petkov 3591e1069839SBorislav Petkov event->destroy = hw_perf_lbr_event_destroy; 3592e1069839SBorislav Petkov } 3593e1069839SBorislav Petkov } 3594e1069839SBorislav Petkov 359542880f72SAlexander Shishkin if (event->attr.aux_output) { 359642880f72SAlexander Shishkin if (!event->attr.precise_ip) 359742880f72SAlexander Shishkin return -EINVAL; 359842880f72SAlexander Shishkin 359942880f72SAlexander Shishkin event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 360042880f72SAlexander Shishkin } 360142880f72SAlexander Shishkin 3602e1069839SBorislav Petkov if (event->attr.type != PERF_TYPE_RAW) 3603e1069839SBorislav Petkov return 0; 3604e1069839SBorislav Petkov 36057b2c05a1SKan Liang /* 36067b2c05a1SKan Liang * Config Topdown slots and metric events 36077b2c05a1SKan Liang * 36087b2c05a1SKan Liang * The slots event on Fixed Counter 3 can support sampling, 36097b2c05a1SKan Liang * which will be handled normally in x86_perf_event_update(). 36107b2c05a1SKan Liang * 36117b2c05a1SKan Liang * Metric events don't support sampling and require being paired 36127b2c05a1SKan Liang * with a slots event as group leader. When the slots event 36137b2c05a1SKan Liang * is used in a metrics group, it too cannot support sampling. 36147b2c05a1SKan Liang */ 36157b2c05a1SKan Liang if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) { 36167b2c05a1SKan Liang if (event->attr.config1 || event->attr.config2) 36177b2c05a1SKan Liang return -EINVAL; 36187b2c05a1SKan Liang 36197b2c05a1SKan Liang /* 36207b2c05a1SKan Liang * The TopDown metrics events and slots event don't 36217b2c05a1SKan Liang * support any filters. 36227b2c05a1SKan Liang */ 36237b2c05a1SKan Liang if (event->attr.config & X86_ALL_EVENT_FLAGS) 36247b2c05a1SKan Liang return -EINVAL; 36257b2c05a1SKan Liang 36267b2c05a1SKan Liang if (is_metric_event(event)) { 36277b2c05a1SKan Liang struct perf_event *leader = event->group_leader; 36287b2c05a1SKan Liang 36297b2c05a1SKan Liang /* The metric events don't support sampling. */ 36307b2c05a1SKan Liang if (is_sampling_event(event)) 36317b2c05a1SKan Liang return -EINVAL; 36327b2c05a1SKan Liang 36337b2c05a1SKan Liang /* The metric events require a slots group leader. */ 36347b2c05a1SKan Liang if (!is_slots_event(leader)) 36357b2c05a1SKan Liang return -EINVAL; 36367b2c05a1SKan Liang 36377b2c05a1SKan Liang /* 36387b2c05a1SKan Liang * The leader/SLOTS must not be a sampling event for 36397b2c05a1SKan Liang * metric use; hardware requires it starts at 0 when used 36407b2c05a1SKan Liang * in conjunction with MSR_PERF_METRICS. 36417b2c05a1SKan Liang */ 36427b2c05a1SKan Liang if (is_sampling_event(leader)) 36437b2c05a1SKan Liang return -EINVAL; 36447b2c05a1SKan Liang 36457b2c05a1SKan Liang event->event_caps |= PERF_EV_CAP_SIBLING; 36467b2c05a1SKan Liang /* 36477b2c05a1SKan Liang * Only once we have a METRICs sibling do we 36487b2c05a1SKan Liang * need TopDown magic. 36497b2c05a1SKan Liang */ 36507b2c05a1SKan Liang leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 36517b2c05a1SKan Liang event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 36527b2c05a1SKan Liang } 36537b2c05a1SKan Liang } 36547b2c05a1SKan Liang 3655e1069839SBorislav Petkov if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3656e1069839SBorislav Petkov return 0; 3657e1069839SBorislav Petkov 3658e1069839SBorislav Petkov if (x86_pmu.version < 3) 3659e1069839SBorislav Petkov return -EINVAL; 3660e1069839SBorislav Petkov 3661da97e184SJoel Fernandes (Google) ret = perf_allow_cpu(&event->attr); 3662da97e184SJoel Fernandes (Google) if (ret) 3663da97e184SJoel Fernandes (Google) return ret; 3664e1069839SBorislav Petkov 3665e1069839SBorislav Petkov event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3666e1069839SBorislav Petkov 3667e1069839SBorislav Petkov return 0; 3668e1069839SBorislav Petkov } 3669e1069839SBorislav Petkov 367074c504a6SAndrea Arcangeli #ifdef CONFIG_RETPOLINE 367174c504a6SAndrea Arcangeli static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr); 367274c504a6SAndrea Arcangeli static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr); 367374c504a6SAndrea Arcangeli #endif 367474c504a6SAndrea Arcangeli 3675e1069839SBorislav Petkov struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3676e1069839SBorislav Petkov { 367774c504a6SAndrea Arcangeli #ifdef CONFIG_RETPOLINE 367874c504a6SAndrea Arcangeli if (x86_pmu.guest_get_msrs == intel_guest_get_msrs) 367974c504a6SAndrea Arcangeli return intel_guest_get_msrs(nr); 368074c504a6SAndrea Arcangeli else if (x86_pmu.guest_get_msrs == core_guest_get_msrs) 368174c504a6SAndrea Arcangeli return core_guest_get_msrs(nr); 368274c504a6SAndrea Arcangeli #endif 3683e1069839SBorislav Petkov if (x86_pmu.guest_get_msrs) 3684e1069839SBorislav Petkov return x86_pmu.guest_get_msrs(nr); 3685e1069839SBorislav Petkov *nr = 0; 3686e1069839SBorislav Petkov return NULL; 3687e1069839SBorislav Petkov } 3688e1069839SBorislav Petkov EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3689e1069839SBorislav Petkov 3690e1069839SBorislav Petkov static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3691e1069839SBorislav Petkov { 3692e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3693e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3694e1069839SBorislav Petkov 3695e1069839SBorislav Petkov arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3696e1069839SBorislav Petkov arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3697e1069839SBorislav Petkov arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 36989b545c04SAndi Kleen if (x86_pmu.flags & PMU_FL_PEBS_ALL) 36999b545c04SAndi Kleen arr[0].guest &= ~cpuc->pebs_enabled; 37009b545c04SAndi Kleen else 37019b545c04SAndi Kleen arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 37029b545c04SAndi Kleen *nr = 1; 37039b545c04SAndi Kleen 37049b545c04SAndi Kleen if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3705e1069839SBorislav Petkov /* 37069b545c04SAndi Kleen * If PMU counter has PEBS enabled it is not enough to 37079b545c04SAndi Kleen * disable counter on a guest entry since PEBS memory 37089b545c04SAndi Kleen * write can overshoot guest entry and corrupt guest 37099b545c04SAndi Kleen * memory. Disabling PEBS solves the problem. 37109b545c04SAndi Kleen * 37119b545c04SAndi Kleen * Don't do this if the CPU already enforces it. 3712e1069839SBorislav Petkov */ 3713e1069839SBorislav Petkov arr[1].msr = MSR_IA32_PEBS_ENABLE; 3714e1069839SBorislav Petkov arr[1].host = cpuc->pebs_enabled; 3715e1069839SBorislav Petkov arr[1].guest = 0; 3716e1069839SBorislav Petkov *nr = 2; 37179b545c04SAndi Kleen } 37189b545c04SAndi Kleen 3719e1069839SBorislav Petkov return arr; 3720e1069839SBorislav Petkov } 3721e1069839SBorislav Petkov 3722e1069839SBorislav Petkov static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3723e1069839SBorislav Petkov { 3724e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3725e1069839SBorislav Petkov struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3726e1069839SBorislav Petkov int idx; 3727e1069839SBorislav Petkov 3728e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3729e1069839SBorislav Petkov struct perf_event *event = cpuc->events[idx]; 3730e1069839SBorislav Petkov 3731e1069839SBorislav Petkov arr[idx].msr = x86_pmu_config_addr(idx); 3732e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 0; 3733e1069839SBorislav Petkov 3734e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) 3735e1069839SBorislav Petkov continue; 3736e1069839SBorislav Petkov 3737e1069839SBorislav Petkov arr[idx].host = arr[idx].guest = 3738e1069839SBorislav Petkov event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3739e1069839SBorislav Petkov 3740e1069839SBorislav Petkov if (event->attr.exclude_host) 3741e1069839SBorislav Petkov arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3742e1069839SBorislav Petkov else if (event->attr.exclude_guest) 3743e1069839SBorislav Petkov arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3744e1069839SBorislav Petkov } 3745e1069839SBorislav Petkov 3746e1069839SBorislav Petkov *nr = x86_pmu.num_counters; 3747e1069839SBorislav Petkov return arr; 3748e1069839SBorislav Petkov } 3749e1069839SBorislav Petkov 3750e1069839SBorislav Petkov static void core_pmu_enable_event(struct perf_event *event) 3751e1069839SBorislav Petkov { 3752e1069839SBorislav Petkov if (!event->attr.exclude_host) 3753e1069839SBorislav Petkov x86_pmu_enable_event(event); 3754e1069839SBorislav Petkov } 3755e1069839SBorislav Petkov 3756e1069839SBorislav Petkov static void core_pmu_enable_all(int added) 3757e1069839SBorislav Petkov { 3758e1069839SBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3759e1069839SBorislav Petkov int idx; 3760e1069839SBorislav Petkov 3761e1069839SBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3762e1069839SBorislav Petkov struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3763e1069839SBorislav Petkov 3764e1069839SBorislav Petkov if (!test_bit(idx, cpuc->active_mask) || 3765e1069839SBorislav Petkov cpuc->events[idx]->attr.exclude_host) 3766e1069839SBorislav Petkov continue; 3767e1069839SBorislav Petkov 3768e1069839SBorislav Petkov __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3769e1069839SBorislav Petkov } 3770e1069839SBorislav Petkov } 3771e1069839SBorislav Petkov 3772e1069839SBorislav Petkov static int hsw_hw_config(struct perf_event *event) 3773e1069839SBorislav Petkov { 3774e1069839SBorislav Petkov int ret = intel_pmu_hw_config(event); 3775e1069839SBorislav Petkov 3776e1069839SBorislav Petkov if (ret) 3777e1069839SBorislav Petkov return ret; 3778e1069839SBorislav Petkov if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3779e1069839SBorislav Petkov return 0; 3780e1069839SBorislav Petkov event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3781e1069839SBorislav Petkov 3782e1069839SBorislav Petkov /* 3783e1069839SBorislav Petkov * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3784e1069839SBorislav Petkov * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3785e1069839SBorislav Petkov * this combination. 3786e1069839SBorislav Petkov */ 3787e1069839SBorislav Petkov if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3788e1069839SBorislav Petkov ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3789e1069839SBorislav Petkov event->attr.precise_ip > 0)) 3790e1069839SBorislav Petkov return -EOPNOTSUPP; 3791e1069839SBorislav Petkov 3792e1069839SBorislav Petkov if (event_is_checkpointed(event)) { 3793e1069839SBorislav Petkov /* 3794e1069839SBorislav Petkov * Sampling of checkpointed events can cause situations where 3795e1069839SBorislav Petkov * the CPU constantly aborts because of a overflow, which is 3796e1069839SBorislav Petkov * then checkpointed back and ignored. Forbid checkpointing 3797e1069839SBorislav Petkov * for sampling. 3798e1069839SBorislav Petkov * 3799e1069839SBorislav Petkov * But still allow a long sampling period, so that perf stat 3800e1069839SBorislav Petkov * from KVM works. 3801e1069839SBorislav Petkov */ 3802e1069839SBorislav Petkov if (event->attr.sample_period > 0 && 3803e1069839SBorislav Petkov event->attr.sample_period < 0x7fffffff) 3804e1069839SBorislav Petkov return -EOPNOTSUPP; 3805e1069839SBorislav Petkov } 3806e1069839SBorislav Petkov return 0; 3807e1069839SBorislav Petkov } 3808e1069839SBorislav Petkov 3809dd0b06b5SKan Liang static struct event_constraint counter0_constraint = 3810dd0b06b5SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3811dd0b06b5SKan Liang 3812e1069839SBorislav Petkov static struct event_constraint counter2_constraint = 3813e1069839SBorislav Petkov EVENT_CONSTRAINT(0, 0x4, 0); 3814e1069839SBorislav Petkov 381560176089SKan Liang static struct event_constraint fixed0_constraint = 381660176089SKan Liang FIXED_EVENT_CONSTRAINT(0x00c0, 0); 381760176089SKan Liang 38186daeb873SKan Liang static struct event_constraint fixed0_counter0_constraint = 38196daeb873SKan Liang INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 38206daeb873SKan Liang 3821e1069839SBorislav Petkov static struct event_constraint * 3822e1069839SBorislav Petkov hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3823e1069839SBorislav Petkov struct perf_event *event) 3824e1069839SBorislav Petkov { 3825e1069839SBorislav Petkov struct event_constraint *c; 3826e1069839SBorislav Petkov 3827e1069839SBorislav Petkov c = intel_get_event_constraints(cpuc, idx, event); 3828e1069839SBorislav Petkov 3829e1069839SBorislav Petkov /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3830e1069839SBorislav Petkov if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3831e1069839SBorislav Petkov if (c->idxmsk64 & (1U << 2)) 3832e1069839SBorislav Petkov return &counter2_constraint; 3833e1069839SBorislav Petkov return &emptyconstraint; 3834e1069839SBorislav Petkov } 3835e1069839SBorislav Petkov 3836e1069839SBorislav Petkov return c; 3837e1069839SBorislav Petkov } 3838e1069839SBorislav Petkov 3839dd0b06b5SKan Liang static struct event_constraint * 384060176089SKan Liang icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 384160176089SKan Liang struct perf_event *event) 384260176089SKan Liang { 384360176089SKan Liang /* 384460176089SKan Liang * Fixed counter 0 has less skid. 384560176089SKan Liang * Force instruction:ppp in Fixed counter 0 384660176089SKan Liang */ 384760176089SKan Liang if ((event->attr.precise_ip == 3) && 384860176089SKan Liang constraint_match(&fixed0_constraint, event->hw.config)) 384960176089SKan Liang return &fixed0_constraint; 385060176089SKan Liang 385160176089SKan Liang return hsw_get_event_constraints(cpuc, idx, event); 385260176089SKan Liang } 385360176089SKan Liang 385460176089SKan Liang static struct event_constraint * 3855dd0b06b5SKan Liang glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3856dd0b06b5SKan Liang struct perf_event *event) 3857dd0b06b5SKan Liang { 3858dd0b06b5SKan Liang struct event_constraint *c; 3859dd0b06b5SKan Liang 3860dd0b06b5SKan Liang /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3861dd0b06b5SKan Liang if (event->attr.precise_ip == 3) 3862dd0b06b5SKan Liang return &counter0_constraint; 3863dd0b06b5SKan Liang 3864dd0b06b5SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 3865dd0b06b5SKan Liang 3866dd0b06b5SKan Liang return c; 3867dd0b06b5SKan Liang } 3868dd0b06b5SKan Liang 38696daeb873SKan Liang static struct event_constraint * 38706daeb873SKan Liang tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 38716daeb873SKan Liang struct perf_event *event) 38726daeb873SKan Liang { 38736daeb873SKan Liang struct event_constraint *c; 38746daeb873SKan Liang 38756daeb873SKan Liang /* 38766daeb873SKan Liang * :ppp means to do reduced skid PEBS, 38776daeb873SKan Liang * which is available on PMC0 and fixed counter 0. 38786daeb873SKan Liang */ 38796daeb873SKan Liang if (event->attr.precise_ip == 3) { 38806daeb873SKan Liang /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 38816daeb873SKan Liang if (constraint_match(&fixed0_constraint, event->hw.config)) 38826daeb873SKan Liang return &fixed0_counter0_constraint; 38836daeb873SKan Liang 38846daeb873SKan Liang return &counter0_constraint; 38856daeb873SKan Liang } 38866daeb873SKan Liang 38876daeb873SKan Liang c = intel_get_event_constraints(cpuc, idx, event); 38886daeb873SKan Liang 38896daeb873SKan Liang return c; 38906daeb873SKan Liang } 38916daeb873SKan Liang 3892400816f6SPeter Zijlstra (Intel) static bool allow_tsx_force_abort = true; 3893400816f6SPeter Zijlstra (Intel) 3894400816f6SPeter Zijlstra (Intel) static struct event_constraint * 3895400816f6SPeter Zijlstra (Intel) tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3896400816f6SPeter Zijlstra (Intel) struct perf_event *event) 3897400816f6SPeter Zijlstra (Intel) { 3898400816f6SPeter Zijlstra (Intel) struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 3899400816f6SPeter Zijlstra (Intel) 3900400816f6SPeter Zijlstra (Intel) /* 3901400816f6SPeter Zijlstra (Intel) * Without TFA we must not use PMC3. 3902400816f6SPeter Zijlstra (Intel) */ 390321d65555SPeter Zijlstra if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 3904400816f6SPeter Zijlstra (Intel) c = dyn_constraint(cpuc, c, idx); 3905400816f6SPeter Zijlstra (Intel) c->idxmsk64 &= ~(1ULL << 3); 3906400816f6SPeter Zijlstra (Intel) c->weight--; 3907400816f6SPeter Zijlstra (Intel) } 3908400816f6SPeter Zijlstra (Intel) 3909400816f6SPeter Zijlstra (Intel) return c; 3910400816f6SPeter Zijlstra (Intel) } 3911400816f6SPeter Zijlstra (Intel) 3912e1069839SBorislav Petkov /* 3913e1069839SBorislav Petkov * Broadwell: 3914e1069839SBorislav Petkov * 3915e1069839SBorislav Petkov * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3916e1069839SBorislav Petkov * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3917e1069839SBorislav Petkov * the two to enforce a minimum period of 128 (the smallest value that has bits 3918e1069839SBorislav Petkov * 0-5 cleared and >= 100). 3919e1069839SBorislav Petkov * 3920e1069839SBorislav Petkov * Because of how the code in x86_perf_event_set_period() works, the truncation 3921e1069839SBorislav Petkov * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3922e1069839SBorislav Petkov * to make up for the 'lost' events due to carrying the 'error' in period_left. 3923e1069839SBorislav Petkov * 3924e1069839SBorislav Petkov * Therefore the effective (average) period matches the requested period, 3925e1069839SBorislav Petkov * despite coarser hardware granularity. 3926e1069839SBorislav Petkov */ 3927f605cfcaSKan Liang static u64 bdw_limit_period(struct perf_event *event, u64 left) 3928e1069839SBorislav Petkov { 3929e1069839SBorislav Petkov if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3930e1069839SBorislav Petkov X86_CONFIG(.event=0xc0, .umask=0x01)) { 3931e1069839SBorislav Petkov if (left < 128) 3932e1069839SBorislav Petkov left = 128; 3933e5ea9b54SDan Carpenter left &= ~0x3fULL; 3934e1069839SBorislav Petkov } 3935e1069839SBorislav Petkov return left; 3936e1069839SBorislav Petkov } 3937e1069839SBorislav Petkov 393844d3bbb6SJosh Hunt static u64 nhm_limit_period(struct perf_event *event, u64 left) 393944d3bbb6SJosh Hunt { 394044d3bbb6SJosh Hunt return max(left, 32ULL); 394144d3bbb6SJosh Hunt } 394244d3bbb6SJosh Hunt 3943e1069839SBorislav Petkov PMU_FORMAT_ATTR(event, "config:0-7" ); 3944e1069839SBorislav Petkov PMU_FORMAT_ATTR(umask, "config:8-15" ); 3945e1069839SBorislav Petkov PMU_FORMAT_ATTR(edge, "config:18" ); 3946e1069839SBorislav Petkov PMU_FORMAT_ATTR(pc, "config:19" ); 3947e1069839SBorislav Petkov PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3948e1069839SBorislav Petkov PMU_FORMAT_ATTR(inv, "config:23" ); 3949e1069839SBorislav Petkov PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3950e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx, "config:32"); 3951e1069839SBorislav Petkov PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3952e1069839SBorislav Petkov 3953e1069839SBorislav Petkov static struct attribute *intel_arch_formats_attr[] = { 3954e1069839SBorislav Petkov &format_attr_event.attr, 3955e1069839SBorislav Petkov &format_attr_umask.attr, 3956e1069839SBorislav Petkov &format_attr_edge.attr, 3957e1069839SBorislav Petkov &format_attr_pc.attr, 3958e1069839SBorislav Petkov &format_attr_inv.attr, 3959e1069839SBorislav Petkov &format_attr_cmask.attr, 3960e1069839SBorislav Petkov NULL, 3961e1069839SBorislav Petkov }; 3962e1069839SBorislav Petkov 3963e1069839SBorislav Petkov ssize_t intel_event_sysfs_show(char *page, u64 config) 3964e1069839SBorislav Petkov { 3965e1069839SBorislav Petkov u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3966e1069839SBorislav Petkov 3967e1069839SBorislav Petkov return x86_event_sysfs_show(page, config, event); 3968e1069839SBorislav Petkov } 3969e1069839SBorislav Petkov 3970d01b1f96SPeter Zijlstra (Intel) static struct intel_shared_regs *allocate_shared_regs(int cpu) 3971e1069839SBorislav Petkov { 3972e1069839SBorislav Petkov struct intel_shared_regs *regs; 3973e1069839SBorislav Petkov int i; 3974e1069839SBorislav Petkov 3975e1069839SBorislav Petkov regs = kzalloc_node(sizeof(struct intel_shared_regs), 3976e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3977e1069839SBorislav Petkov if (regs) { 3978e1069839SBorislav Petkov /* 3979e1069839SBorislav Petkov * initialize the locks to keep lockdep happy 3980e1069839SBorislav Petkov */ 3981e1069839SBorislav Petkov for (i = 0; i < EXTRA_REG_MAX; i++) 3982e1069839SBorislav Petkov raw_spin_lock_init(®s->regs[i].lock); 3983e1069839SBorislav Petkov 3984e1069839SBorislav Petkov regs->core_id = -1; 3985e1069839SBorislav Petkov } 3986e1069839SBorislav Petkov return regs; 3987e1069839SBorislav Petkov } 3988e1069839SBorislav Petkov 3989e1069839SBorislav Petkov static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 3990e1069839SBorislav Petkov { 3991e1069839SBorislav Petkov struct intel_excl_cntrs *c; 3992e1069839SBorislav Petkov 3993e1069839SBorislav Petkov c = kzalloc_node(sizeof(struct intel_excl_cntrs), 3994e1069839SBorislav Petkov GFP_KERNEL, cpu_to_node(cpu)); 3995e1069839SBorislav Petkov if (c) { 3996e1069839SBorislav Petkov raw_spin_lock_init(&c->lock); 3997e1069839SBorislav Petkov c->core_id = -1; 3998e1069839SBorislav Petkov } 3999e1069839SBorislav Petkov return c; 4000e1069839SBorislav Petkov } 4001e1069839SBorislav Petkov 4002e1069839SBorislav Petkov 4003d01b1f96SPeter Zijlstra (Intel) int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4004d01b1f96SPeter Zijlstra (Intel) { 4005c22497f5SKan Liang cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4006c22497f5SKan Liang 4007e1069839SBorislav Petkov if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4008e1069839SBorislav Petkov cpuc->shared_regs = allocate_shared_regs(cpu); 4009e1069839SBorislav Petkov if (!cpuc->shared_regs) 4010e1069839SBorislav Petkov goto err; 4011e1069839SBorislav Petkov } 4012e1069839SBorislav Petkov 4013400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4014e1069839SBorislav Petkov size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4015e1069839SBorislav Petkov 4016d01b1f96SPeter Zijlstra (Intel) cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4017e1069839SBorislav Petkov if (!cpuc->constraint_list) 4018e1069839SBorislav Petkov goto err_shared_regs; 4019400816f6SPeter Zijlstra (Intel) } 4020e1069839SBorislav Petkov 4021400816f6SPeter Zijlstra (Intel) if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4022e1069839SBorislav Petkov cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4023e1069839SBorislav Petkov if (!cpuc->excl_cntrs) 4024e1069839SBorislav Petkov goto err_constraint_list; 4025e1069839SBorislav Petkov 4026e1069839SBorislav Petkov cpuc->excl_thread_id = 0; 4027e1069839SBorislav Petkov } 4028e1069839SBorislav Petkov 402995ca792cSThomas Gleixner return 0; 4030e1069839SBorislav Petkov 4031e1069839SBorislav Petkov err_constraint_list: 4032e1069839SBorislav Petkov kfree(cpuc->constraint_list); 4033e1069839SBorislav Petkov cpuc->constraint_list = NULL; 4034e1069839SBorislav Petkov 4035e1069839SBorislav Petkov err_shared_regs: 4036e1069839SBorislav Petkov kfree(cpuc->shared_regs); 4037e1069839SBorislav Petkov cpuc->shared_regs = NULL; 4038e1069839SBorislav Petkov 4039e1069839SBorislav Petkov err: 404095ca792cSThomas Gleixner return -ENOMEM; 4041e1069839SBorislav Petkov } 4042e1069839SBorislav Petkov 4043d01b1f96SPeter Zijlstra (Intel) static int intel_pmu_cpu_prepare(int cpu) 4044d01b1f96SPeter Zijlstra (Intel) { 4045d01b1f96SPeter Zijlstra (Intel) return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4046d01b1f96SPeter Zijlstra (Intel) } 4047d01b1f96SPeter Zijlstra (Intel) 40486089327fSKan Liang static void flip_smm_bit(void *data) 40496089327fSKan Liang { 40506089327fSKan Liang unsigned long set = *(unsigned long *)data; 40516089327fSKan Liang 40526089327fSKan Liang if (set > 0) { 40536089327fSKan Liang msr_set_bit(MSR_IA32_DEBUGCTLMSR, 40546089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 40556089327fSKan Liang } else { 40566089327fSKan Liang msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 40576089327fSKan Liang DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 40586089327fSKan Liang } 40596089327fSKan Liang } 40606089327fSKan Liang 4061e1069839SBorislav Petkov static void intel_pmu_cpu_starting(int cpu) 4062e1069839SBorislav Petkov { 4063e1069839SBorislav Petkov struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4064e1069839SBorislav Petkov int core_id = topology_core_id(cpu); 4065e1069839SBorislav Petkov int i; 4066e1069839SBorislav Petkov 4067e1069839SBorislav Petkov init_debug_store_on_cpu(cpu); 4068e1069839SBorislav Petkov /* 4069e1069839SBorislav Petkov * Deal with CPUs that don't clear their LBRs on power-up. 4070e1069839SBorislav Petkov */ 4071e1069839SBorislav Petkov intel_pmu_lbr_reset(); 4072e1069839SBorislav Petkov 4073e1069839SBorislav Petkov cpuc->lbr_sel = NULL; 4074e1069839SBorislav Petkov 4075d7262457SPeter Zijlstra if (x86_pmu.flags & PMU_FL_TFA) { 4076d7262457SPeter Zijlstra WARN_ON_ONCE(cpuc->tfa_shadow); 4077d7262457SPeter Zijlstra cpuc->tfa_shadow = ~0ULL; 4078d7262457SPeter Zijlstra intel_set_tfa(cpuc, false); 4079d7262457SPeter Zijlstra } 4080d7262457SPeter Zijlstra 40814e949e9bSKan Liang if (x86_pmu.version > 1) 40826089327fSKan Liang flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 40836089327fSKan Liang 4084af3bdb99SAndi Kleen if (x86_pmu.counter_freezing) 4085af3bdb99SAndi Kleen enable_counter_freeze(); 4086af3bdb99SAndi Kleen 408780a5ce11SKan Liang /* Disable perf metrics if any added CPU doesn't support it. */ 408880a5ce11SKan Liang if (x86_pmu.intel_cap.perf_metrics) { 408980a5ce11SKan Liang union perf_capabilities perf_cap; 409080a5ce11SKan Liang 409180a5ce11SKan Liang rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 409280a5ce11SKan Liang if (!perf_cap.perf_metrics) { 409380a5ce11SKan Liang x86_pmu.intel_cap.perf_metrics = 0; 409480a5ce11SKan Liang x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 409580a5ce11SKan Liang } 409680a5ce11SKan Liang } 409780a5ce11SKan Liang 4098e1069839SBorislav Petkov if (!cpuc->shared_regs) 4099e1069839SBorislav Petkov return; 4100e1069839SBorislav Petkov 4101e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4102e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4103e1069839SBorislav Petkov struct intel_shared_regs *pc; 4104e1069839SBorislav Petkov 4105e1069839SBorislav Petkov pc = per_cpu(cpu_hw_events, i).shared_regs; 4106e1069839SBorislav Petkov if (pc && pc->core_id == core_id) { 4107e1069839SBorislav Petkov cpuc->kfree_on_online[0] = cpuc->shared_regs; 4108e1069839SBorislav Petkov cpuc->shared_regs = pc; 4109e1069839SBorislav Petkov break; 4110e1069839SBorislav Petkov } 4111e1069839SBorislav Petkov } 4112e1069839SBorislav Petkov cpuc->shared_regs->core_id = core_id; 4113e1069839SBorislav Petkov cpuc->shared_regs->refcnt++; 4114e1069839SBorislav Petkov } 4115e1069839SBorislav Petkov 4116e1069839SBorislav Petkov if (x86_pmu.lbr_sel_map) 4117e1069839SBorislav Petkov cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4118e1069839SBorislav Petkov 4119e1069839SBorislav Petkov if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4120e1069839SBorislav Petkov for_each_cpu(i, topology_sibling_cpumask(cpu)) { 41214e71de79SZhou Chengming struct cpu_hw_events *sibling; 4122e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4123e1069839SBorislav Petkov 41244e71de79SZhou Chengming sibling = &per_cpu(cpu_hw_events, i); 41254e71de79SZhou Chengming c = sibling->excl_cntrs; 4126e1069839SBorislav Petkov if (c && c->core_id == core_id) { 4127e1069839SBorislav Petkov cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4128e1069839SBorislav Petkov cpuc->excl_cntrs = c; 41294e71de79SZhou Chengming if (!sibling->excl_thread_id) 4130e1069839SBorislav Petkov cpuc->excl_thread_id = 1; 4131e1069839SBorislav Petkov break; 4132e1069839SBorislav Petkov } 4133e1069839SBorislav Petkov } 4134e1069839SBorislav Petkov cpuc->excl_cntrs->core_id = core_id; 4135e1069839SBorislav Petkov cpuc->excl_cntrs->refcnt++; 4136e1069839SBorislav Petkov } 4137e1069839SBorislav Petkov } 4138e1069839SBorislav Petkov 4139d01b1f96SPeter Zijlstra (Intel) static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4140e1069839SBorislav Petkov { 4141e1069839SBorislav Petkov struct intel_excl_cntrs *c; 4142e1069839SBorislav Petkov 4143e1069839SBorislav Petkov c = cpuc->excl_cntrs; 4144e1069839SBorislav Petkov if (c) { 4145e1069839SBorislav Petkov if (c->core_id == -1 || --c->refcnt == 0) 4146e1069839SBorislav Petkov kfree(c); 4147e1069839SBorislav Petkov cpuc->excl_cntrs = NULL; 4148400816f6SPeter Zijlstra (Intel) } 4149400816f6SPeter Zijlstra (Intel) 4150e1069839SBorislav Petkov kfree(cpuc->constraint_list); 4151e1069839SBorislav Petkov cpuc->constraint_list = NULL; 4152e1069839SBorislav Petkov } 4153e1069839SBorislav Petkov 4154e1069839SBorislav Petkov static void intel_pmu_cpu_dying(int cpu) 4155e1069839SBorislav Petkov { 4156602cae04SPeter Zijlstra fini_debug_store_on_cpu(cpu); 4157602cae04SPeter Zijlstra 4158602cae04SPeter Zijlstra if (x86_pmu.counter_freezing) 4159602cae04SPeter Zijlstra disable_counter_freeze(); 4160602cae04SPeter Zijlstra } 4161602cae04SPeter Zijlstra 4162d01b1f96SPeter Zijlstra (Intel) void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4163602cae04SPeter Zijlstra { 4164e1069839SBorislav Petkov struct intel_shared_regs *pc; 4165e1069839SBorislav Petkov 4166e1069839SBorislav Petkov pc = cpuc->shared_regs; 4167e1069839SBorislav Petkov if (pc) { 4168e1069839SBorislav Petkov if (pc->core_id == -1 || --pc->refcnt == 0) 4169e1069839SBorislav Petkov kfree(pc); 4170e1069839SBorislav Petkov cpuc->shared_regs = NULL; 4171e1069839SBorislav Petkov } 4172e1069839SBorislav Petkov 4173d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(cpuc); 4174d01b1f96SPeter Zijlstra (Intel) } 4175d01b1f96SPeter Zijlstra (Intel) 4176d01b1f96SPeter Zijlstra (Intel) static void intel_pmu_cpu_dead(int cpu) 4177d01b1f96SPeter Zijlstra (Intel) { 4178d01b1f96SPeter Zijlstra (Intel) intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu)); 4179e1069839SBorislav Petkov } 4180e1069839SBorislav Petkov 4181e1069839SBorislav Petkov static void intel_pmu_sched_task(struct perf_event_context *ctx, 4182e1069839SBorislav Petkov bool sched_in) 4183e1069839SBorislav Petkov { 4184e1069839SBorislav Petkov intel_pmu_pebs_sched_task(ctx, sched_in); 4185e1069839SBorislav Petkov intel_pmu_lbr_sched_task(ctx, sched_in); 4186e1069839SBorislav Petkov } 4187e1069839SBorislav Petkov 4188c2b98a86SAlexey Budankov static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4189c2b98a86SAlexey Budankov struct perf_event_context *next) 4190c2b98a86SAlexey Budankov { 4191c2b98a86SAlexey Budankov intel_pmu_lbr_swap_task_ctx(prev, next); 4192c2b98a86SAlexey Budankov } 4193c2b98a86SAlexey Budankov 419481ec3f3cSJiri Olsa static int intel_pmu_check_period(struct perf_event *event, u64 value) 419581ec3f3cSJiri Olsa { 419681ec3f3cSJiri Olsa return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 419781ec3f3cSJiri Olsa } 419881ec3f3cSJiri Olsa 419942880f72SAlexander Shishkin static int intel_pmu_aux_output_match(struct perf_event *event) 420042880f72SAlexander Shishkin { 420142880f72SAlexander Shishkin if (!x86_pmu.intel_cap.pebs_output_pt_available) 420242880f72SAlexander Shishkin return 0; 420342880f72SAlexander Shishkin 420442880f72SAlexander Shishkin return is_intel_pt_event(event); 420542880f72SAlexander Shishkin } 420642880f72SAlexander Shishkin 4207e1069839SBorislav Petkov PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4208e1069839SBorislav Petkov 4209e1069839SBorislav Petkov PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4210e1069839SBorislav Petkov 4211e1069839SBorislav Petkov PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4212e1069839SBorislav Petkov 4213e1069839SBorislav Petkov static struct attribute *intel_arch3_formats_attr[] = { 4214e1069839SBorislav Petkov &format_attr_event.attr, 4215e1069839SBorislav Petkov &format_attr_umask.attr, 4216e1069839SBorislav Petkov &format_attr_edge.attr, 4217e1069839SBorislav Petkov &format_attr_pc.attr, 4218e1069839SBorislav Petkov &format_attr_any.attr, 4219e1069839SBorislav Petkov &format_attr_inv.attr, 4220e1069839SBorislav Petkov &format_attr_cmask.attr, 4221a5df70c3SAndi Kleen NULL, 4222a5df70c3SAndi Kleen }; 4223a5df70c3SAndi Kleen 4224a5df70c3SAndi Kleen static struct attribute *hsw_format_attr[] = { 4225e1069839SBorislav Petkov &format_attr_in_tx.attr, 4226e1069839SBorislav Petkov &format_attr_in_tx_cp.attr, 4227a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4228a5df70c3SAndi Kleen &format_attr_ldlat.attr, 4229a5df70c3SAndi Kleen NULL 4230a5df70c3SAndi Kleen }; 4231e1069839SBorislav Petkov 4232a5df70c3SAndi Kleen static struct attribute *nhm_format_attr[] = { 4233a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4234a5df70c3SAndi Kleen &format_attr_ldlat.attr, 4235a5df70c3SAndi Kleen NULL 4236a5df70c3SAndi Kleen }; 4237a5df70c3SAndi Kleen 4238a5df70c3SAndi Kleen static struct attribute *slm_format_attr[] = { 4239a5df70c3SAndi Kleen &format_attr_offcore_rsp.attr, 4240a5df70c3SAndi Kleen NULL 4241e1069839SBorislav Petkov }; 4242e1069839SBorislav Petkov 4243e1069839SBorislav Petkov static struct attribute *skl_format_attr[] = { 4244e1069839SBorislav Petkov &format_attr_frontend.attr, 4245e1069839SBorislav Petkov NULL, 4246e1069839SBorislav Petkov }; 4247e1069839SBorislav Petkov 4248e1069839SBorislav Petkov static __initconst const struct x86_pmu core_pmu = { 4249e1069839SBorislav Petkov .name = "core", 4250e1069839SBorislav Petkov .handle_irq = x86_pmu_handle_irq, 4251e1069839SBorislav Petkov .disable_all = x86_pmu_disable_all, 4252e1069839SBorislav Petkov .enable_all = core_pmu_enable_all, 4253e1069839SBorislav Petkov .enable = core_pmu_enable_event, 4254e1069839SBorislav Petkov .disable = x86_pmu_disable_event, 4255ed6101bbSJiri Olsa .hw_config = core_pmu_hw_config, 4256e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 4257e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4258e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4259e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 4260e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4261e1069839SBorislav Petkov .apic = 1, 4262174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 4263e1069839SBorislav Petkov 4264e1069839SBorislav Petkov /* 4265e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32-bit width, 4266e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 4267e1069839SBorislav Petkov * the generic event period: 4268e1069839SBorislav Petkov */ 4269e1069839SBorislav Petkov .max_period = (1ULL<<31) - 1, 4270e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 4271e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 4272e1069839SBorislav Petkov .event_constraints = intel_core_event_constraints, 4273e1069839SBorislav Petkov .guest_get_msrs = core_guest_get_msrs, 4274e1069839SBorislav Petkov .format_attrs = intel_arch_formats_attr, 4275e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 4276e1069839SBorislav Petkov 4277e1069839SBorislav Petkov /* 4278e1069839SBorislav Petkov * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4279e1069839SBorislav Petkov * together with PMU version 1 and thus be using core_pmu with 4280e1069839SBorislav Petkov * shared_regs. We need following callbacks here to allocate 4281e1069839SBorislav Petkov * it properly. 4282e1069839SBorislav Petkov */ 4283e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 4284e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 4285e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 4286602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 428781ec3f3cSJiri Olsa 428881ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 42899f354a72SKan Liang 42909f354a72SKan Liang .lbr_reset = intel_pmu_lbr_reset_64, 4291c301b1d8SKan Liang .lbr_read = intel_pmu_lbr_read_64, 4292799571bfSKan Liang .lbr_save = intel_pmu_lbr_save, 4293799571bfSKan Liang .lbr_restore = intel_pmu_lbr_restore, 4294e1069839SBorislav Petkov }; 4295e1069839SBorislav Petkov 4296e1069839SBorislav Petkov static __initconst const struct x86_pmu intel_pmu = { 4297e1069839SBorislav Petkov .name = "Intel", 4298e1069839SBorislav Petkov .handle_irq = intel_pmu_handle_irq, 4299e1069839SBorislav Petkov .disable_all = intel_pmu_disable_all, 4300e1069839SBorislav Petkov .enable_all = intel_pmu_enable_all, 4301e1069839SBorislav Petkov .enable = intel_pmu_enable_event, 4302e1069839SBorislav Petkov .disable = intel_pmu_disable_event, 430368f7082fSPeter Zijlstra .add = intel_pmu_add_event, 430468f7082fSPeter Zijlstra .del = intel_pmu_del_event, 4305ceb90d9eSKan Liang .read = intel_pmu_read_event, 4306e1069839SBorislav Petkov .hw_config = intel_pmu_hw_config, 4307e1069839SBorislav Petkov .schedule_events = x86_schedule_events, 4308e1069839SBorislav Petkov .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4309e1069839SBorislav Petkov .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4310e1069839SBorislav Petkov .event_map = intel_pmu_event_map, 4311e1069839SBorislav Petkov .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4312e1069839SBorislav Petkov .apic = 1, 4313174afc3eSKan Liang .large_pebs_flags = LARGE_PEBS_FLAGS, 4314e1069839SBorislav Petkov /* 4315e1069839SBorislav Petkov * Intel PMCs cannot be accessed sanely above 32 bit width, 4316e1069839SBorislav Petkov * so we install an artificial 1<<31 period regardless of 4317e1069839SBorislav Petkov * the generic event period: 4318e1069839SBorislav Petkov */ 4319e1069839SBorislav Petkov .max_period = (1ULL << 31) - 1, 4320e1069839SBorislav Petkov .get_event_constraints = intel_get_event_constraints, 4321e1069839SBorislav Petkov .put_event_constraints = intel_put_event_constraints, 4322e1069839SBorislav Petkov .pebs_aliases = intel_pebs_aliases_core2, 4323e1069839SBorislav Petkov 4324e1069839SBorislav Petkov .format_attrs = intel_arch3_formats_attr, 4325e1069839SBorislav Petkov .events_sysfs_show = intel_event_sysfs_show, 4326e1069839SBorislav Petkov 4327e1069839SBorislav Petkov .cpu_prepare = intel_pmu_cpu_prepare, 4328e1069839SBorislav Petkov .cpu_starting = intel_pmu_cpu_starting, 4329e1069839SBorislav Petkov .cpu_dying = intel_pmu_cpu_dying, 4330602cae04SPeter Zijlstra .cpu_dead = intel_pmu_cpu_dead, 4331602cae04SPeter Zijlstra 4332e1069839SBorislav Petkov .guest_get_msrs = intel_guest_get_msrs, 4333e1069839SBorislav Petkov .sched_task = intel_pmu_sched_task, 4334c2b98a86SAlexey Budankov .swap_task_ctx = intel_pmu_swap_task_ctx, 433581ec3f3cSJiri Olsa 433681ec3f3cSJiri Olsa .check_period = intel_pmu_check_period, 433742880f72SAlexander Shishkin 433842880f72SAlexander Shishkin .aux_output_match = intel_pmu_aux_output_match, 43399f354a72SKan Liang 43409f354a72SKan Liang .lbr_reset = intel_pmu_lbr_reset_64, 4341c301b1d8SKan Liang .lbr_read = intel_pmu_lbr_read_64, 4342799571bfSKan Liang .lbr_save = intel_pmu_lbr_save, 4343799571bfSKan Liang .lbr_restore = intel_pmu_lbr_restore, 4344e1069839SBorislav Petkov }; 4345e1069839SBorislav Petkov 4346e1069839SBorislav Petkov static __init void intel_clovertown_quirk(void) 4347e1069839SBorislav Petkov { 4348e1069839SBorislav Petkov /* 4349e1069839SBorislav Petkov * PEBS is unreliable due to: 4350e1069839SBorislav Petkov * 4351e1069839SBorislav Petkov * AJ67 - PEBS may experience CPL leaks 4352e1069839SBorislav Petkov * AJ68 - PEBS PMI may be delayed by one event 4353e1069839SBorislav Petkov * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4354e1069839SBorislav Petkov * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4355e1069839SBorislav Petkov * 4356e1069839SBorislav Petkov * AJ67 could be worked around by restricting the OS/USR flags. 4357e1069839SBorislav Petkov * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4358e1069839SBorislav Petkov * 4359e1069839SBorislav Petkov * AJ106 could possibly be worked around by not allowing LBR 4360e1069839SBorislav Petkov * usage from PEBS, including the fixup. 4361e1069839SBorislav Petkov * AJ68 could possibly be worked around by always programming 4362e1069839SBorislav Petkov * a pebs_event_reset[0] value and coping with the lost events. 4363e1069839SBorislav Petkov * 4364e1069839SBorislav Petkov * But taken together it might just make sense to not enable PEBS on 4365e1069839SBorislav Petkov * these chips. 4366e1069839SBorislav Petkov */ 4367e1069839SBorislav Petkov pr_warn("PEBS disabled due to CPU errata\n"); 4368e1069839SBorislav Petkov x86_pmu.pebs = 0; 4369e1069839SBorislav Petkov x86_pmu.pebs_constraints = NULL; 4370e1069839SBorislav Petkov } 4371e1069839SBorislav Petkov 43729b545c04SAndi Kleen static const struct x86_cpu_desc isolation_ucodes[] = { 4373c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4374af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 43755e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 43769b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 43779b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4378c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 43795e741407SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 43805ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 43815ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 43825ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 43835ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 43849b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014), 43859b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 43869b545c04SAndi Kleen INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4387af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4388c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4389c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4390af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4391af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4392af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4393af239c44SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4394c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4395c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4396c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4397c66f78a6SPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 43989b545c04SAndi Kleen {} 43999b545c04SAndi Kleen }; 44009b545c04SAndi Kleen 44019b545c04SAndi Kleen static void intel_check_pebs_isolation(void) 44029b545c04SAndi Kleen { 44039b545c04SAndi Kleen x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 44049b545c04SAndi Kleen } 44059b545c04SAndi Kleen 44069b545c04SAndi Kleen static __init void intel_pebs_isolation_quirk(void) 44079b545c04SAndi Kleen { 44089b545c04SAndi Kleen WARN_ON_ONCE(x86_pmu.check_microcode); 44099b545c04SAndi Kleen x86_pmu.check_microcode = intel_check_pebs_isolation; 44109b545c04SAndi Kleen intel_check_pebs_isolation(); 44119b545c04SAndi Kleen } 44129b545c04SAndi Kleen 4413a96fff8dSKan Liang static const struct x86_cpu_desc pebs_ucodes[] = { 4414a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4415a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4416a96fff8dSKan Liang INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4417a96fff8dSKan Liang {} 4418a96fff8dSKan Liang }; 4419a96fff8dSKan Liang 4420a96fff8dSKan Liang static bool intel_snb_pebs_broken(void) 4421e1069839SBorislav Petkov { 4422a96fff8dSKan Liang return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4423e1069839SBorislav Petkov } 4424e1069839SBorislav Petkov 4425e1069839SBorislav Petkov static void intel_snb_check_microcode(void) 4426e1069839SBorislav Petkov { 4427a96fff8dSKan Liang if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4428e1069839SBorislav Petkov return; 4429e1069839SBorislav Petkov 4430e1069839SBorislav Petkov /* 4431e1069839SBorislav Petkov * Serialized by the microcode lock.. 4432e1069839SBorislav Petkov */ 4433e1069839SBorislav Petkov if (x86_pmu.pebs_broken) { 4434e1069839SBorislav Petkov pr_info("PEBS enabled due to microcode update\n"); 4435e1069839SBorislav Petkov x86_pmu.pebs_broken = 0; 4436e1069839SBorislav Petkov } else { 4437e1069839SBorislav Petkov pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4438e1069839SBorislav Petkov x86_pmu.pebs_broken = 1; 4439e1069839SBorislav Petkov } 4440e1069839SBorislav Petkov } 4441e1069839SBorislav Petkov 444219fc9dddSDavid Carrillo-Cisneros static bool is_lbr_from(unsigned long msr) 444319fc9dddSDavid Carrillo-Cisneros { 444419fc9dddSDavid Carrillo-Cisneros unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 444519fc9dddSDavid Carrillo-Cisneros 444619fc9dddSDavid Carrillo-Cisneros return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 444719fc9dddSDavid Carrillo-Cisneros } 444819fc9dddSDavid Carrillo-Cisneros 4449e1069839SBorislav Petkov /* 4450e1069839SBorislav Petkov * Under certain circumstances, access certain MSR may cause #GP. 4451e1069839SBorislav Petkov * The function tests if the input MSR can be safely accessed. 4452e1069839SBorislav Petkov */ 4453e1069839SBorislav Petkov static bool check_msr(unsigned long msr, u64 mask) 4454e1069839SBorislav Petkov { 4455e1069839SBorislav Petkov u64 val_old, val_new, val_tmp; 4456e1069839SBorislav Petkov 4457e1069839SBorislav Petkov /* 4458d0e1a507SJiri Olsa * Disable the check for real HW, so we don't 4459d0e1a507SJiri Olsa * mess with potentionaly enabled registers: 4460d0e1a507SJiri Olsa */ 44615ea3f6fbSZhenzhong Duan if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4462d0e1a507SJiri Olsa return true; 4463d0e1a507SJiri Olsa 4464d0e1a507SJiri Olsa /* 4465e1069839SBorislav Petkov * Read the current value, change it and read it back to see if it 4466e1069839SBorislav Petkov * matches, this is needed to detect certain hardware emulators 4467e1069839SBorislav Petkov * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4468e1069839SBorislav Petkov */ 4469e1069839SBorislav Petkov if (rdmsrl_safe(msr, &val_old)) 4470e1069839SBorislav Petkov return false; 4471e1069839SBorislav Petkov 4472e1069839SBorislav Petkov /* 4473e1069839SBorislav Petkov * Only change the bits which can be updated by wrmsrl. 4474e1069839SBorislav Petkov */ 4475e1069839SBorislav Petkov val_tmp = val_old ^ mask; 447619fc9dddSDavid Carrillo-Cisneros 447719fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 447819fc9dddSDavid Carrillo-Cisneros val_tmp = lbr_from_signext_quirk_wr(val_tmp); 447919fc9dddSDavid Carrillo-Cisneros 4480e1069839SBorislav Petkov if (wrmsrl_safe(msr, val_tmp) || 4481e1069839SBorislav Petkov rdmsrl_safe(msr, &val_new)) 4482e1069839SBorislav Petkov return false; 4483e1069839SBorislav Petkov 448419fc9dddSDavid Carrillo-Cisneros /* 448519fc9dddSDavid Carrillo-Cisneros * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 448619fc9dddSDavid Carrillo-Cisneros * should equal rdmsrl()'s even with the quirk. 448719fc9dddSDavid Carrillo-Cisneros */ 4488e1069839SBorislav Petkov if (val_new != val_tmp) 4489e1069839SBorislav Petkov return false; 4490e1069839SBorislav Petkov 449119fc9dddSDavid Carrillo-Cisneros if (is_lbr_from(msr)) 449219fc9dddSDavid Carrillo-Cisneros val_old = lbr_from_signext_quirk_wr(val_old); 449319fc9dddSDavid Carrillo-Cisneros 4494e1069839SBorislav Petkov /* Here it's sure that the MSR can be safely accessed. 4495e1069839SBorislav Petkov * Restore the old value and return. 4496e1069839SBorislav Petkov */ 4497e1069839SBorislav Petkov wrmsrl(msr, val_old); 4498e1069839SBorislav Petkov 4499e1069839SBorislav Petkov return true; 4500e1069839SBorislav Petkov } 4501e1069839SBorislav Petkov 4502e1069839SBorislav Petkov static __init void intel_sandybridge_quirk(void) 4503e1069839SBorislav Petkov { 4504e1069839SBorislav Petkov x86_pmu.check_microcode = intel_snb_check_microcode; 45051ba143a5SSebastian Andrzej Siewior cpus_read_lock(); 4506e1069839SBorislav Petkov intel_snb_check_microcode(); 45071ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 4508e1069839SBorislav Petkov } 4509e1069839SBorislav Petkov 4510e1069839SBorislav Petkov static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4511e1069839SBorislav Petkov { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4512e1069839SBorislav Petkov { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4513e1069839SBorislav Petkov { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4514e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4515e1069839SBorislav Petkov { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4516e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4517e1069839SBorislav Petkov { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4518e1069839SBorislav Petkov }; 4519e1069839SBorislav Petkov 4520e1069839SBorislav Petkov static __init void intel_arch_events_quirk(void) 4521e1069839SBorislav Petkov { 4522e1069839SBorislav Petkov int bit; 4523e1069839SBorislav Petkov 4524e1069839SBorislav Petkov /* disable event that reported as not presend by cpuid */ 4525e1069839SBorislav Petkov for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4526e1069839SBorislav Petkov intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4527e1069839SBorislav Petkov pr_warn("CPUID marked event: \'%s\' unavailable\n", 4528e1069839SBorislav Petkov intel_arch_events_map[bit].name); 4529e1069839SBorislav Petkov } 4530e1069839SBorislav Petkov } 4531e1069839SBorislav Petkov 4532e1069839SBorislav Petkov static __init void intel_nehalem_quirk(void) 4533e1069839SBorislav Petkov { 4534e1069839SBorislav Petkov union cpuid10_ebx ebx; 4535e1069839SBorislav Petkov 4536e1069839SBorislav Petkov ebx.full = x86_pmu.events_maskl; 4537e1069839SBorislav Petkov if (ebx.split.no_branch_misses_retired) { 4538e1069839SBorislav Petkov /* 4539e1069839SBorislav Petkov * Erratum AAJ80 detected, we work it around by using 4540e1069839SBorislav Petkov * the BR_MISP_EXEC.ANY event. This will over-count 4541e1069839SBorislav Petkov * branch-misses, but it's still much better than the 4542e1069839SBorislav Petkov * architectural event which is often completely bogus: 4543e1069839SBorislav Petkov */ 4544e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4545e1069839SBorislav Petkov ebx.split.no_branch_misses_retired = 0; 4546e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4547e1069839SBorislav Petkov pr_info("CPU erratum AAJ80 worked around\n"); 4548e1069839SBorislav Petkov } 4549e1069839SBorislav Petkov } 4550e1069839SBorislav Petkov 4551bef9f271SKan Liang static const struct x86_cpu_desc counter_freezing_ucodes[] = { 4552af63147cSKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e), 4553af63147cSKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e), 4554af63147cSKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008), 45555ebb34edSPeter Zijlstra INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028), 4556bef9f271SKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028), 4557bef9f271SKan Liang INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006), 4558bef9f271SKan Liang {} 4559bef9f271SKan Liang }; 4560bef9f271SKan Liang 4561bef9f271SKan Liang static bool intel_counter_freezing_broken(void) 45627c5314b8SKan Liang { 4563bef9f271SKan Liang return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes); 45647c5314b8SKan Liang } 45657c5314b8SKan Liang 4566bef9f271SKan Liang static __init void intel_counter_freezing_quirk(void) 45677c5314b8SKan Liang { 45687c5314b8SKan Liang /* Check if it's already disabled */ 45697c5314b8SKan Liang if (disable_counter_freezing) 45707c5314b8SKan Liang return; 45717c5314b8SKan Liang 45727c5314b8SKan Liang /* 45737c5314b8SKan Liang * If the system starts with the wrong ucode, leave the 45747c5314b8SKan Liang * counter-freezing feature permanently disabled. 45757c5314b8SKan Liang */ 4576bef9f271SKan Liang if (intel_counter_freezing_broken()) { 45777c5314b8SKan Liang pr_info("PMU counter freezing disabled due to CPU errata," 45787c5314b8SKan Liang "please upgrade microcode\n"); 45797c5314b8SKan Liang x86_pmu.counter_freezing = false; 45807c5314b8SKan Liang x86_pmu.handle_irq = intel_pmu_handle_irq; 45817c5314b8SKan Liang } 45827c5314b8SKan Liang } 45837c5314b8SKan Liang 4584e1069839SBorislav Petkov /* 4585e1069839SBorislav Petkov * enable software workaround for errata: 4586e1069839SBorislav Petkov * SNB: BJ122 4587e1069839SBorislav Petkov * IVB: BV98 4588e1069839SBorislav Petkov * HSW: HSD29 4589e1069839SBorislav Petkov * 4590e1069839SBorislav Petkov * Only needed when HT is enabled. However detecting 4591e1069839SBorislav Petkov * if HT is enabled is difficult (model specific). So instead, 4592e1069839SBorislav Petkov * we enable the workaround in the early boot, and verify if 4593e1069839SBorislav Petkov * it is needed in a later initcall phase once we have valid 4594e1069839SBorislav Petkov * topology information to check if HT is actually enabled 4595e1069839SBorislav Petkov */ 4596e1069839SBorislav Petkov static __init void intel_ht_bug(void) 4597e1069839SBorislav Petkov { 4598e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4599e1069839SBorislav Petkov 4600e1069839SBorislav Petkov x86_pmu.start_scheduling = intel_start_scheduling; 4601e1069839SBorislav Petkov x86_pmu.commit_scheduling = intel_commit_scheduling; 4602e1069839SBorislav Petkov x86_pmu.stop_scheduling = intel_stop_scheduling; 4603e1069839SBorislav Petkov } 4604e1069839SBorislav Petkov 4605e1069839SBorislav Petkov EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4606e1069839SBorislav Petkov EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4607e1069839SBorislav Petkov 4608e1069839SBorislav Petkov /* Haswell special events */ 4609e1069839SBorislav Petkov EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4610e1069839SBorislav Petkov EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4611e1069839SBorislav Petkov EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4612e1069839SBorislav Petkov EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4613e1069839SBorislav Petkov EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4614e1069839SBorislav Petkov EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4615e1069839SBorislav Petkov EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4616e1069839SBorislav Petkov EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4617e1069839SBorislav Petkov EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4618e1069839SBorislav Petkov EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4619e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4620e1069839SBorislav Petkov EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4621e1069839SBorislav Petkov 4622e1069839SBorislav Petkov static struct attribute *hsw_events_attrs[] = { 462358ba4d5aSAndi Kleen EVENT_PTR(td_slots_issued), 462458ba4d5aSAndi Kleen EVENT_PTR(td_slots_retired), 462558ba4d5aSAndi Kleen EVENT_PTR(td_fetch_bubbles), 462658ba4d5aSAndi Kleen EVENT_PTR(td_total_slots), 462758ba4d5aSAndi Kleen EVENT_PTR(td_total_slots_scale), 462858ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles), 462958ba4d5aSAndi Kleen EVENT_PTR(td_recovery_bubbles_scale), 463058ba4d5aSAndi Kleen NULL 463158ba4d5aSAndi Kleen }; 463258ba4d5aSAndi Kleen 4633d4ae5529SJiri Olsa static struct attribute *hsw_mem_events_attrs[] = { 4634d4ae5529SJiri Olsa EVENT_PTR(mem_ld_hsw), 4635d4ae5529SJiri Olsa EVENT_PTR(mem_st_hsw), 4636d4ae5529SJiri Olsa NULL, 4637d4ae5529SJiri Olsa }; 4638d4ae5529SJiri Olsa 463958ba4d5aSAndi Kleen static struct attribute *hsw_tsx_events_attrs[] = { 4640e1069839SBorislav Petkov EVENT_PTR(tx_start), 4641e1069839SBorislav Petkov EVENT_PTR(tx_commit), 4642e1069839SBorislav Petkov EVENT_PTR(tx_abort), 4643e1069839SBorislav Petkov EVENT_PTR(tx_capacity), 4644e1069839SBorislav Petkov EVENT_PTR(tx_conflict), 4645e1069839SBorislav Petkov EVENT_PTR(el_start), 4646e1069839SBorislav Petkov EVENT_PTR(el_commit), 4647e1069839SBorislav Petkov EVENT_PTR(el_abort), 4648e1069839SBorislav Petkov EVENT_PTR(el_capacity), 4649e1069839SBorislav Petkov EVENT_PTR(el_conflict), 4650e1069839SBorislav Petkov EVENT_PTR(cycles_t), 4651e1069839SBorislav Petkov EVENT_PTR(cycles_ct), 4652e1069839SBorislav Petkov NULL 4653e1069839SBorislav Petkov }; 4654e1069839SBorislav Petkov 465560176089SKan Liang EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 465660176089SKan Liang EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 465760176089SKan Liang EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 465860176089SKan Liang EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 465960176089SKan Liang 466060176089SKan Liang static struct attribute *icl_events_attrs[] = { 466160176089SKan Liang EVENT_PTR(mem_ld_hsw), 466260176089SKan Liang EVENT_PTR(mem_st_hsw), 466360176089SKan Liang NULL, 466460176089SKan Liang }; 466560176089SKan Liang 466659a854e2SKan Liang static struct attribute *icl_td_events_attrs[] = { 466759a854e2SKan Liang EVENT_PTR(slots), 466859a854e2SKan Liang EVENT_PTR(td_retiring), 466959a854e2SKan Liang EVENT_PTR(td_bad_spec), 467059a854e2SKan Liang EVENT_PTR(td_fe_bound), 467159a854e2SKan Liang EVENT_PTR(td_be_bound), 467259a854e2SKan Liang NULL, 467359a854e2SKan Liang }; 467459a854e2SKan Liang 467560176089SKan Liang static struct attribute *icl_tsx_events_attrs[] = { 467660176089SKan Liang EVENT_PTR(tx_start), 467760176089SKan Liang EVENT_PTR(tx_abort), 467860176089SKan Liang EVENT_PTR(tx_commit), 467960176089SKan Liang EVENT_PTR(tx_capacity_read), 468060176089SKan Liang EVENT_PTR(tx_capacity_write), 468160176089SKan Liang EVENT_PTR(tx_conflict), 468260176089SKan Liang EVENT_PTR(el_start), 468360176089SKan Liang EVENT_PTR(el_abort), 468460176089SKan Liang EVENT_PTR(el_commit), 468560176089SKan Liang EVENT_PTR(el_capacity_read), 468660176089SKan Liang EVENT_PTR(el_capacity_write), 468760176089SKan Liang EVENT_PTR(el_conflict), 468860176089SKan Liang EVENT_PTR(cycles_t), 468960176089SKan Liang EVENT_PTR(cycles_ct), 469060176089SKan Liang NULL, 469160176089SKan Liang }; 469260176089SKan Liang 46936089327fSKan Liang static ssize_t freeze_on_smi_show(struct device *cdev, 46946089327fSKan Liang struct device_attribute *attr, 46956089327fSKan Liang char *buf) 46966089327fSKan Liang { 46976089327fSKan Liang return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 46986089327fSKan Liang } 46996089327fSKan Liang 47006089327fSKan Liang static DEFINE_MUTEX(freeze_on_smi_mutex); 47016089327fSKan Liang 47026089327fSKan Liang static ssize_t freeze_on_smi_store(struct device *cdev, 47036089327fSKan Liang struct device_attribute *attr, 47046089327fSKan Liang const char *buf, size_t count) 47056089327fSKan Liang { 47066089327fSKan Liang unsigned long val; 47076089327fSKan Liang ssize_t ret; 47086089327fSKan Liang 47096089327fSKan Liang ret = kstrtoul(buf, 0, &val); 47106089327fSKan Liang if (ret) 47116089327fSKan Liang return ret; 47126089327fSKan Liang 47136089327fSKan Liang if (val > 1) 47146089327fSKan Liang return -EINVAL; 47156089327fSKan Liang 47166089327fSKan Liang mutex_lock(&freeze_on_smi_mutex); 47176089327fSKan Liang 47186089327fSKan Liang if (x86_pmu.attr_freeze_on_smi == val) 47196089327fSKan Liang goto done; 47206089327fSKan Liang 47216089327fSKan Liang x86_pmu.attr_freeze_on_smi = val; 47226089327fSKan Liang 47236089327fSKan Liang get_online_cpus(); 47246089327fSKan Liang on_each_cpu(flip_smm_bit, &val, 1); 47256089327fSKan Liang put_online_cpus(); 47266089327fSKan Liang done: 47276089327fSKan Liang mutex_unlock(&freeze_on_smi_mutex); 47286089327fSKan Liang 47296089327fSKan Liang return count; 47306089327fSKan Liang } 47316089327fSKan Liang 4732f447e4ebSStephane Eranian static void update_tfa_sched(void *ignored) 4733f447e4ebSStephane Eranian { 4734f447e4ebSStephane Eranian struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4735f447e4ebSStephane Eranian 4736f447e4ebSStephane Eranian /* 4737f447e4ebSStephane Eranian * check if PMC3 is used 4738f447e4ebSStephane Eranian * and if so force schedule out for all event types all contexts 4739f447e4ebSStephane Eranian */ 4740f447e4ebSStephane Eranian if (test_bit(3, cpuc->active_mask)) 4741f447e4ebSStephane Eranian perf_pmu_resched(x86_get_pmu()); 4742f447e4ebSStephane Eranian } 4743f447e4ebSStephane Eranian 4744f447e4ebSStephane Eranian static ssize_t show_sysctl_tfa(struct device *cdev, 4745f447e4ebSStephane Eranian struct device_attribute *attr, 4746f447e4ebSStephane Eranian char *buf) 4747f447e4ebSStephane Eranian { 4748f447e4ebSStephane Eranian return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 4749f447e4ebSStephane Eranian } 4750f447e4ebSStephane Eranian 4751f447e4ebSStephane Eranian static ssize_t set_sysctl_tfa(struct device *cdev, 4752f447e4ebSStephane Eranian struct device_attribute *attr, 4753f447e4ebSStephane Eranian const char *buf, size_t count) 4754f447e4ebSStephane Eranian { 4755f447e4ebSStephane Eranian bool val; 4756f447e4ebSStephane Eranian ssize_t ret; 4757f447e4ebSStephane Eranian 4758f447e4ebSStephane Eranian ret = kstrtobool(buf, &val); 4759f447e4ebSStephane Eranian if (ret) 4760f447e4ebSStephane Eranian return ret; 4761f447e4ebSStephane Eranian 4762f447e4ebSStephane Eranian /* no change */ 4763f447e4ebSStephane Eranian if (val == allow_tsx_force_abort) 4764f447e4ebSStephane Eranian return count; 4765f447e4ebSStephane Eranian 4766f447e4ebSStephane Eranian allow_tsx_force_abort = val; 4767f447e4ebSStephane Eranian 4768f447e4ebSStephane Eranian get_online_cpus(); 4769f447e4ebSStephane Eranian on_each_cpu(update_tfa_sched, NULL, 1); 4770f447e4ebSStephane Eranian put_online_cpus(); 4771f447e4ebSStephane Eranian 4772f447e4ebSStephane Eranian return count; 4773f447e4ebSStephane Eranian } 4774f447e4ebSStephane Eranian 4775f447e4ebSStephane Eranian 47766089327fSKan Liang static DEVICE_ATTR_RW(freeze_on_smi); 47776089327fSKan Liang 4778b00233b5SAndi Kleen static ssize_t branches_show(struct device *cdev, 4779b00233b5SAndi Kleen struct device_attribute *attr, 4780b00233b5SAndi Kleen char *buf) 4781b00233b5SAndi Kleen { 4782b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4783b00233b5SAndi Kleen } 4784b00233b5SAndi Kleen 4785b00233b5SAndi Kleen static DEVICE_ATTR_RO(branches); 4786b00233b5SAndi Kleen 4787b00233b5SAndi Kleen static struct attribute *lbr_attrs[] = { 4788b00233b5SAndi Kleen &dev_attr_branches.attr, 4789b00233b5SAndi Kleen NULL 4790b00233b5SAndi Kleen }; 4791b00233b5SAndi Kleen 4792b00233b5SAndi Kleen static char pmu_name_str[30]; 4793b00233b5SAndi Kleen 4794b00233b5SAndi Kleen static ssize_t pmu_name_show(struct device *cdev, 4795b00233b5SAndi Kleen struct device_attribute *attr, 4796b00233b5SAndi Kleen char *buf) 4797b00233b5SAndi Kleen { 4798b00233b5SAndi Kleen return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4799b00233b5SAndi Kleen } 4800b00233b5SAndi Kleen 4801b00233b5SAndi Kleen static DEVICE_ATTR_RO(pmu_name); 4802b00233b5SAndi Kleen 4803b00233b5SAndi Kleen static struct attribute *intel_pmu_caps_attrs[] = { 4804b00233b5SAndi Kleen &dev_attr_pmu_name.attr, 4805b00233b5SAndi Kleen NULL 4806b00233b5SAndi Kleen }; 4807b00233b5SAndi Kleen 4808f447e4ebSStephane Eranian static DEVICE_ATTR(allow_tsx_force_abort, 0644, 4809f447e4ebSStephane Eranian show_sysctl_tfa, 4810f447e4ebSStephane Eranian set_sysctl_tfa); 4811400816f6SPeter Zijlstra (Intel) 48126089327fSKan Liang static struct attribute *intel_pmu_attrs[] = { 48136089327fSKan Liang &dev_attr_freeze_on_smi.attr, 4814b7c9b392SJiri Olsa &dev_attr_allow_tsx_force_abort.attr, 48156089327fSKan Liang NULL, 48166089327fSKan Liang }; 48176089327fSKan Liang 4818baa0c833SJiri Olsa static umode_t 4819baa0c833SJiri Olsa tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4820d4ae5529SJiri Olsa { 4821baa0c833SJiri Olsa return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 4822d4ae5529SJiri Olsa } 4823d4ae5529SJiri Olsa 4824baa0c833SJiri Olsa static umode_t 4825baa0c833SJiri Olsa pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4826baa0c833SJiri Olsa { 4827baa0c833SJiri Olsa return x86_pmu.pebs ? attr->mode : 0; 4828d4ae5529SJiri Olsa } 4829d4ae5529SJiri Olsa 48301f157286SJiri Olsa static umode_t 48311f157286SJiri Olsa lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 48321f157286SJiri Olsa { 48331f157286SJiri Olsa return x86_pmu.lbr_nr ? attr->mode : 0; 48341f157286SJiri Olsa } 48351f157286SJiri Olsa 48363ea40ac7SJiri Olsa static umode_t 48373ea40ac7SJiri Olsa exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 48383ea40ac7SJiri Olsa { 48393ea40ac7SJiri Olsa return x86_pmu.version >= 2 ? attr->mode : 0; 48403ea40ac7SJiri Olsa } 48413ea40ac7SJiri Olsa 4842b7c9b392SJiri Olsa static umode_t 4843b7c9b392SJiri Olsa default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4844b7c9b392SJiri Olsa { 4845b7c9b392SJiri Olsa if (attr == &dev_attr_allow_tsx_force_abort.attr) 4846b7c9b392SJiri Olsa return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 4847b7c9b392SJiri Olsa 4848b7c9b392SJiri Olsa return attr->mode; 4849b7c9b392SJiri Olsa } 4850b7c9b392SJiri Olsa 4851baa0c833SJiri Olsa static struct attribute_group group_events_td = { 4852baa0c833SJiri Olsa .name = "events", 4853baa0c833SJiri Olsa }; 4854baa0c833SJiri Olsa 4855baa0c833SJiri Olsa static struct attribute_group group_events_mem = { 4856baa0c833SJiri Olsa .name = "events", 4857baa0c833SJiri Olsa .is_visible = pebs_is_visible, 4858baa0c833SJiri Olsa }; 4859baa0c833SJiri Olsa 4860baa0c833SJiri Olsa static struct attribute_group group_events_tsx = { 4861baa0c833SJiri Olsa .name = "events", 4862baa0c833SJiri Olsa .is_visible = tsx_is_visible, 4863baa0c833SJiri Olsa }; 4864baa0c833SJiri Olsa 48651f157286SJiri Olsa static struct attribute_group group_caps_gen = { 48661f157286SJiri Olsa .name = "caps", 48671f157286SJiri Olsa .attrs = intel_pmu_caps_attrs, 48681f157286SJiri Olsa }; 48691f157286SJiri Olsa 48701f157286SJiri Olsa static struct attribute_group group_caps_lbr = { 48711f157286SJiri Olsa .name = "caps", 48721f157286SJiri Olsa .attrs = lbr_attrs, 48731f157286SJiri Olsa .is_visible = lbr_is_visible, 48741f157286SJiri Olsa }; 48751f157286SJiri Olsa 48763ea40ac7SJiri Olsa static struct attribute_group group_format_extra = { 48773ea40ac7SJiri Olsa .name = "format", 48783ea40ac7SJiri Olsa .is_visible = exra_is_visible, 48793ea40ac7SJiri Olsa }; 48803ea40ac7SJiri Olsa 4881b6576880SJiri Olsa static struct attribute_group group_format_extra_skl = { 4882b6576880SJiri Olsa .name = "format", 4883b6576880SJiri Olsa .is_visible = exra_is_visible, 4884b6576880SJiri Olsa }; 4885b6576880SJiri Olsa 48866a9f4efeSJiri Olsa static struct attribute_group group_default = { 48876a9f4efeSJiri Olsa .attrs = intel_pmu_attrs, 4888b7c9b392SJiri Olsa .is_visible = default_is_visible, 48896a9f4efeSJiri Olsa }; 48906a9f4efeSJiri Olsa 4891baa0c833SJiri Olsa static const struct attribute_group *attr_update[] = { 4892baa0c833SJiri Olsa &group_events_td, 4893baa0c833SJiri Olsa &group_events_mem, 4894baa0c833SJiri Olsa &group_events_tsx, 48951f157286SJiri Olsa &group_caps_gen, 48961f157286SJiri Olsa &group_caps_lbr, 48973ea40ac7SJiri Olsa &group_format_extra, 4898b6576880SJiri Olsa &group_format_extra_skl, 48996a9f4efeSJiri Olsa &group_default, 4900baa0c833SJiri Olsa NULL, 4901baa0c833SJiri Olsa }; 4902baa0c833SJiri Olsa 4903baa0c833SJiri Olsa static struct attribute *empty_attrs; 4904baa0c833SJiri Olsa 4905e1069839SBorislav Petkov __init int intel_pmu_init(void) 4906e1069839SBorislav Petkov { 4907b6576880SJiri Olsa struct attribute **extra_skl_attr = &empty_attrs; 4908baa0c833SJiri Olsa struct attribute **extra_attr = &empty_attrs; 4909baa0c833SJiri Olsa struct attribute **td_attr = &empty_attrs; 4910baa0c833SJiri Olsa struct attribute **mem_attr = &empty_attrs; 4911baa0c833SJiri Olsa struct attribute **tsx_attr = &empty_attrs; 4912e1069839SBorislav Petkov union cpuid10_edx edx; 4913e1069839SBorislav Petkov union cpuid10_eax eax; 4914e1069839SBorislav Petkov union cpuid10_ebx ebx; 4915e1069839SBorislav Petkov struct event_constraint *c; 4916e1069839SBorislav Petkov unsigned int unused; 4917e1069839SBorislav Petkov struct extra_reg *er; 4918faaeff98SKan Liang bool pmem = false; 4919e1069839SBorislav Petkov int version, i; 4920b00233b5SAndi Kleen char *name; 4921e1069839SBorislav Petkov 4922e1069839SBorislav Petkov if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4923e1069839SBorislav Petkov switch (boot_cpu_data.x86) { 4924e1069839SBorislav Petkov case 0x6: 4925e1069839SBorislav Petkov return p6_pmu_init(); 4926e1069839SBorislav Petkov case 0xb: 4927e1069839SBorislav Petkov return knc_pmu_init(); 4928e1069839SBorislav Petkov case 0xf: 4929e1069839SBorislav Petkov return p4_pmu_init(); 4930e1069839SBorislav Petkov } 4931e1069839SBorislav Petkov return -ENODEV; 4932e1069839SBorislav Petkov } 4933e1069839SBorislav Petkov 4934e1069839SBorislav Petkov /* 4935e1069839SBorislav Petkov * Check whether the Architectural PerfMon supports 4936e1069839SBorislav Petkov * Branch Misses Retired hw_event or not. 4937e1069839SBorislav Petkov */ 4938e1069839SBorislav Petkov cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4939e1069839SBorislav Petkov if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4940e1069839SBorislav Petkov return -ENODEV; 4941e1069839SBorislav Petkov 4942e1069839SBorislav Petkov version = eax.split.version_id; 4943e1069839SBorislav Petkov if (version < 2) 4944e1069839SBorislav Petkov x86_pmu = core_pmu; 4945e1069839SBorislav Petkov else 4946e1069839SBorislav Petkov x86_pmu = intel_pmu; 4947e1069839SBorislav Petkov 4948e1069839SBorislav Petkov x86_pmu.version = version; 4949e1069839SBorislav Petkov x86_pmu.num_counters = eax.split.num_counters; 4950e1069839SBorislav Petkov x86_pmu.cntval_bits = eax.split.bit_width; 4951e1069839SBorislav Petkov x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4952e1069839SBorislav Petkov 4953e1069839SBorislav Petkov x86_pmu.events_maskl = ebx.full; 4954e1069839SBorislav Petkov x86_pmu.events_mask_len = eax.split.mask_length; 4955e1069839SBorislav Petkov 4956e1069839SBorislav Petkov x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4957e1069839SBorislav Petkov 4958e1069839SBorislav Petkov /* 4959e1069839SBorislav Petkov * Quirk: v2 perfmon does not report fixed-purpose events, so 4960f92b7604SImre Palik * assume at least 3 events, when not running in a hypervisor: 4961e1069839SBorislav Petkov */ 4962f92b7604SImre Palik if (version > 1) { 4963f92b7604SImre Palik int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4964f92b7604SImre Palik 4965f92b7604SImre Palik x86_pmu.num_counters_fixed = 4966f92b7604SImre Palik max((int)edx.split.num_counters_fixed, assume); 4967f92b7604SImre Palik } 4968e1069839SBorislav Petkov 4969af3bdb99SAndi Kleen if (version >= 4) 4970af3bdb99SAndi Kleen x86_pmu.counter_freezing = !disable_counter_freezing; 4971af3bdb99SAndi Kleen 4972e1069839SBorislav Petkov if (boot_cpu_has(X86_FEATURE_PDCM)) { 4973e1069839SBorislav Petkov u64 capabilities; 4974e1069839SBorislav Petkov 4975e1069839SBorislav Petkov rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4976e1069839SBorislav Petkov x86_pmu.intel_cap.capabilities = capabilities; 4977e1069839SBorislav Petkov } 4978e1069839SBorislav Petkov 4979c301b1d8SKan Liang if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 49809f354a72SKan Liang x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 4981c301b1d8SKan Liang x86_pmu.lbr_read = intel_pmu_lbr_read_32; 4982c301b1d8SKan Liang } 49839f354a72SKan Liang 498447125db2SKan Liang if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 498547125db2SKan Liang intel_pmu_arch_lbr_init(); 498647125db2SKan Liang 4987e1069839SBorislav Petkov intel_ds_init(); 4988e1069839SBorislav Petkov 4989e1069839SBorislav Petkov x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 4990e1069839SBorislav Petkov 4991cadbaa03SStephane Eranian if (version >= 5) { 4992cadbaa03SStephane Eranian x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 4993cadbaa03SStephane Eranian if (x86_pmu.intel_cap.anythread_deprecated) 4994cadbaa03SStephane Eranian pr_cont(" AnyThread deprecated, "); 4995cadbaa03SStephane Eranian } 4996cadbaa03SStephane Eranian 4997e1069839SBorislav Petkov /* 4998e1069839SBorislav Petkov * Install the hw-cache-events table: 4999e1069839SBorislav Petkov */ 5000e1069839SBorislav Petkov switch (boot_cpu_data.x86_model) { 5001ef5f9f47SDave Hansen case INTEL_FAM6_CORE_YONAH: 5002e1069839SBorislav Petkov pr_cont("Core events, "); 5003b00233b5SAndi Kleen name = "core"; 5004e1069839SBorislav Petkov break; 5005e1069839SBorislav Petkov 5006ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM: 5007e1069839SBorislav Petkov x86_add_quirk(intel_clovertown_quirk); 5008df561f66SGustavo A. R. Silva fallthrough; 50092b0fc374SGustavo A. R. Silva 5010ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_MEROM_L: 5011ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_PENRYN: 5012ef5f9f47SDave Hansen case INTEL_FAM6_CORE2_DUNNINGTON: 5013e1069839SBorislav Petkov memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5014e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5015e1069839SBorislav Petkov 5016e1069839SBorislav Petkov intel_pmu_lbr_init_core(); 5017e1069839SBorislav Petkov 5018e1069839SBorislav Petkov x86_pmu.event_constraints = intel_core2_event_constraints; 5019e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5020e1069839SBorislav Petkov pr_cont("Core2 events, "); 5021b00233b5SAndi Kleen name = "core2"; 5022e1069839SBorislav Petkov break; 5023e1069839SBorislav Petkov 5024ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM: 5025ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EP: 5026ef5f9f47SDave Hansen case INTEL_FAM6_NEHALEM_EX: 5027e1069839SBorislav Petkov memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5028e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5029e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5030e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5031e1069839SBorislav Petkov 5032e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 5033e1069839SBorislav Petkov 5034e1069839SBorislav Petkov x86_pmu.event_constraints = intel_nehalem_event_constraints; 5035e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5036e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5037e1069839SBorislav Petkov x86_pmu.extra_regs = intel_nehalem_extra_regs; 503844d3bbb6SJosh Hunt x86_pmu.limit_period = nhm_limit_period; 5039e1069839SBorislav Petkov 5040d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 5041e1069839SBorislav Petkov 5042e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 5043e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5044e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5045e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5046e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5047e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5048e1069839SBorislav Petkov 5049e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 5050e1069839SBorislav Petkov x86_add_quirk(intel_nehalem_quirk); 505195298355SAndi Kleen x86_pmu.pebs_no_tlb = 1; 5052a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5053e1069839SBorislav Petkov 5054e1069839SBorislav Petkov pr_cont("Nehalem events, "); 5055b00233b5SAndi Kleen name = "nehalem"; 5056e1069839SBorislav Petkov break; 5057e1069839SBorislav Petkov 5058f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL: 5059f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_BONNELL_MID: 5060f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL: 5061f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_MID: 5062f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5063e1069839SBorislav Petkov memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5064e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5065e1069839SBorislav Petkov 5066e1069839SBorislav Petkov intel_pmu_lbr_init_atom(); 5067e1069839SBorislav Petkov 5068e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 5069e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5070e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5071e1069839SBorislav Petkov pr_cont("Atom events, "); 5072b00233b5SAndi Kleen name = "bonnell"; 5073e1069839SBorislav Petkov break; 5074e1069839SBorislav Petkov 5075f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT: 50765ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_D: 5077f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_SILVERMONT_MID: 5078ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_AIRMONT: 5079f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_AIRMONT_MID: 5080e1069839SBorislav Petkov memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5081e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5082e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5083e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5084e1069839SBorislav Petkov 5085f21d5adcSKan Liang intel_pmu_lbr_init_slm(); 5086e1069839SBorislav Petkov 5087e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 5088e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5089e1069839SBorislav Petkov x86_pmu.extra_regs = intel_slm_extra_regs; 5090e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5091baa0c833SJiri Olsa td_attr = slm_events_attrs; 5092a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5093e1069839SBorislav Petkov pr_cont("Silvermont events, "); 5094b00233b5SAndi Kleen name = "silvermont"; 5095e1069839SBorislav Petkov break; 5096e1069839SBorislav Petkov 5097ef5f9f47SDave Hansen case INTEL_FAM6_ATOM_GOLDMONT: 50985ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_D: 5099af63147cSKan Liang x86_add_quirk(intel_counter_freezing_quirk); 51008b92c3a7SKan Liang memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 51018b92c3a7SKan Liang sizeof(hw_cache_event_ids)); 51028b92c3a7SKan Liang memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 51038b92c3a7SKan Liang sizeof(hw_cache_extra_regs)); 51048b92c3a7SKan Liang 51058b92c3a7SKan Liang intel_pmu_lbr_init_skl(); 51068b92c3a7SKan Liang 51078b92c3a7SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 51088b92c3a7SKan Liang x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 51098b92c3a7SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 51108b92c3a7SKan Liang /* 51118b92c3a7SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 51128b92c3a7SKan Liang * for precise cycles. 51138b92c3a7SKan Liang * :pp is identical to :ppp 51148b92c3a7SKan Liang */ 51158b92c3a7SKan Liang x86_pmu.pebs_aliases = NULL; 51168b92c3a7SKan Liang x86_pmu.pebs_prec_dist = true; 5117ccbebba4SAlexander Shishkin x86_pmu.lbr_pt_coexist = true; 51188b92c3a7SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5119baa0c833SJiri Olsa td_attr = glm_events_attrs; 5120a5df70c3SAndi Kleen extra_attr = slm_format_attr; 51218b92c3a7SKan Liang pr_cont("Goldmont events, "); 5122b00233b5SAndi Kleen name = "goldmont"; 51238b92c3a7SKan Liang break; 51248b92c3a7SKan Liang 5125f2c4db1bSPeter Zijlstra case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5126bef9f271SKan Liang x86_add_quirk(intel_counter_freezing_quirk); 5127dd0b06b5SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5128dd0b06b5SKan Liang sizeof(hw_cache_event_ids)); 5129dd0b06b5SKan Liang memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5130dd0b06b5SKan Liang sizeof(hw_cache_extra_regs)); 5131dd0b06b5SKan Liang 5132dd0b06b5SKan Liang intel_pmu_lbr_init_skl(); 5133dd0b06b5SKan Liang 5134dd0b06b5SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 5135dd0b06b5SKan Liang x86_pmu.extra_regs = intel_glm_extra_regs; 5136dd0b06b5SKan Liang /* 5137dd0b06b5SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5138dd0b06b5SKan Liang * for precise cycles. 5139dd0b06b5SKan Liang */ 5140dd0b06b5SKan Liang x86_pmu.pebs_aliases = NULL; 5141dd0b06b5SKan Liang x86_pmu.pebs_prec_dist = true; 5142dd0b06b5SKan Liang x86_pmu.lbr_pt_coexist = true; 5143dd0b06b5SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5144a38b0ba1SKan Liang x86_pmu.flags |= PMU_FL_PEBS_ALL; 5145dd0b06b5SKan Liang x86_pmu.get_event_constraints = glp_get_event_constraints; 5146baa0c833SJiri Olsa td_attr = glm_events_attrs; 5147dd0b06b5SKan Liang /* Goldmont Plus has 4-wide pipeline */ 5148dd0b06b5SKan Liang event_attr_td_total_slots_scale_glm.event_str = "4"; 5149a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5150dd0b06b5SKan Liang pr_cont("Goldmont plus events, "); 5151b00233b5SAndi Kleen name = "goldmont_plus"; 5152dd0b06b5SKan Liang break; 5153dd0b06b5SKan Liang 51545ebb34edSPeter Zijlstra case INTEL_FAM6_ATOM_TREMONT_D: 5155eda23b38SKan Liang case INTEL_FAM6_ATOM_TREMONT: 5156dbfd6388SKan Liang case INTEL_FAM6_ATOM_TREMONT_L: 51576daeb873SKan Liang x86_pmu.late_ack = true; 51586daeb873SKan Liang memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 51596daeb873SKan Liang sizeof(hw_cache_event_ids)); 51606daeb873SKan Liang memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 51616daeb873SKan Liang sizeof(hw_cache_extra_regs)); 51626daeb873SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 51636daeb873SKan Liang 51646daeb873SKan Liang intel_pmu_lbr_init_skl(); 51656daeb873SKan Liang 51666daeb873SKan Liang x86_pmu.event_constraints = intel_slm_event_constraints; 51676daeb873SKan Liang x86_pmu.extra_regs = intel_tnt_extra_regs; 51686daeb873SKan Liang /* 51696daeb873SKan Liang * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 51706daeb873SKan Liang * for precise cycles. 51716daeb873SKan Liang */ 51726daeb873SKan Liang x86_pmu.pebs_aliases = NULL; 51736daeb873SKan Liang x86_pmu.pebs_prec_dist = true; 51746daeb873SKan Liang x86_pmu.lbr_pt_coexist = true; 51756daeb873SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 51766daeb873SKan Liang x86_pmu.get_event_constraints = tnt_get_event_constraints; 51776daeb873SKan Liang extra_attr = slm_format_attr; 51786daeb873SKan Liang pr_cont("Tremont events, "); 51796daeb873SKan Liang name = "Tremont"; 51806daeb873SKan Liang break; 51816daeb873SKan Liang 5182ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE: 5183ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EP: 5184ef5f9f47SDave Hansen case INTEL_FAM6_WESTMERE_EX: 5185e1069839SBorislav Petkov memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5186e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5187e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5188e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5189e1069839SBorislav Petkov 5190e1069839SBorislav Petkov intel_pmu_lbr_init_nhm(); 5191e1069839SBorislav Petkov 5192e1069839SBorislav Petkov x86_pmu.event_constraints = intel_westmere_event_constraints; 5193e1069839SBorislav Petkov x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5194e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5195e1069839SBorislav Petkov x86_pmu.extra_regs = intel_westmere_extra_regs; 5196e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5197e1069839SBorislav Petkov 5198d4ae5529SJiri Olsa mem_attr = nhm_mem_events_attrs; 5199e1069839SBorislav Petkov 5200e1069839SBorislav Petkov /* UOPS_ISSUED.STALLED_CYCLES */ 5201e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5202e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5203e1069839SBorislav Petkov /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5204e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5205e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5206e1069839SBorislav Petkov 5207e17dc653SAndi Kleen intel_pmu_pebs_data_source_nhm(); 5208a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5209e1069839SBorislav Petkov pr_cont("Westmere events, "); 5210b00233b5SAndi Kleen name = "westmere"; 5211e1069839SBorislav Petkov break; 5212e1069839SBorislav Petkov 5213ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE: 5214ef5f9f47SDave Hansen case INTEL_FAM6_SANDYBRIDGE_X: 5215e1069839SBorislav Petkov x86_add_quirk(intel_sandybridge_quirk); 5216e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 5217e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5218e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5219e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5220e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5221e1069839SBorislav Petkov 5222e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 5223e1069839SBorislav Petkov 5224e1069839SBorislav Petkov x86_pmu.event_constraints = intel_snb_event_constraints; 5225e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5226e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5227ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5228e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5229e1069839SBorislav Petkov else 5230e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 5231e1069839SBorislav Petkov 5232e1069839SBorislav Petkov 5233e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5234e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5235e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5236e1069839SBorislav Petkov 5237baa0c833SJiri Olsa td_attr = snb_events_attrs; 5238d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 5239e1069839SBorislav Petkov 5240e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5241e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5242e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5243e1069839SBorislav Petkov /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5244e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5245e1069839SBorislav Petkov X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5246e1069839SBorislav Petkov 5247a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5248a5df70c3SAndi Kleen 5249e1069839SBorislav Petkov pr_cont("SandyBridge events, "); 5250b00233b5SAndi Kleen name = "sandybridge"; 5251e1069839SBorislav Petkov break; 5252e1069839SBorislav Petkov 5253ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE: 5254ef5f9f47SDave Hansen case INTEL_FAM6_IVYBRIDGE_X: 5255e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 5256e1069839SBorislav Petkov memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5257e1069839SBorislav Petkov sizeof(hw_cache_event_ids)); 5258e1069839SBorislav Petkov /* dTLB-load-misses on IVB is different than SNB */ 5259e1069839SBorislav Petkov hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5260e1069839SBorislav Petkov 5261e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5262e1069839SBorislav Petkov sizeof(hw_cache_extra_regs)); 5263e1069839SBorislav Petkov 5264e1069839SBorislav Petkov intel_pmu_lbr_init_snb(); 5265e1069839SBorislav Petkov 5266e1069839SBorislav Petkov x86_pmu.event_constraints = intel_ivb_event_constraints; 5267e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5268e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5269e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5270ef5f9f47SDave Hansen if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5271e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5272e1069839SBorislav Petkov else 5273e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snb_extra_regs; 5274e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5275e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5276e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5277e1069839SBorislav Petkov 5278baa0c833SJiri Olsa td_attr = snb_events_attrs; 5279d4ae5529SJiri Olsa mem_attr = snb_mem_events_attrs; 5280e1069839SBorislav Petkov 5281e1069839SBorislav Petkov /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5282e1069839SBorislav Petkov intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5283e1069839SBorislav Petkov X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5284e1069839SBorislav Petkov 5285a5df70c3SAndi Kleen extra_attr = nhm_format_attr; 5286a5df70c3SAndi Kleen 5287e1069839SBorislav Petkov pr_cont("IvyBridge events, "); 5288b00233b5SAndi Kleen name = "ivybridge"; 5289e1069839SBorislav Petkov break; 5290e1069839SBorislav Petkov 5291e1069839SBorislav Petkov 5292c66f78a6SPeter Zijlstra case INTEL_FAM6_HASWELL: 5293ef5f9f47SDave Hansen case INTEL_FAM6_HASWELL_X: 5294af239c44SPeter Zijlstra case INTEL_FAM6_HASWELL_L: 52955e741407SPeter Zijlstra case INTEL_FAM6_HASWELL_G: 5296e1069839SBorislav Petkov x86_add_quirk(intel_ht_bug); 52979b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5298e1069839SBorislav Petkov x86_pmu.late_ack = true; 5299e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5300e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5301e1069839SBorislav Petkov 5302e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 5303e1069839SBorislav Petkov 5304e1069839SBorislav Petkov x86_pmu.event_constraints = intel_hsw_event_constraints; 5305e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5306e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5307e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5308e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5309e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5310e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5311e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5312e1069839SBorislav Petkov 5313e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5314e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5315e1069839SBorislav Petkov x86_pmu.lbr_double_abort = true; 5316a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5317a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5318baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5319d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5320d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5321e1069839SBorislav Petkov pr_cont("Haswell events, "); 5322b00233b5SAndi Kleen name = "haswell"; 5323e1069839SBorislav Petkov break; 5324e1069839SBorislav Petkov 5325c66f78a6SPeter Zijlstra case INTEL_FAM6_BROADWELL: 53265ebb34edSPeter Zijlstra case INTEL_FAM6_BROADWELL_D: 53275e741407SPeter Zijlstra case INTEL_FAM6_BROADWELL_G: 5328ef5f9f47SDave Hansen case INTEL_FAM6_BROADWELL_X: 53299b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5330e1069839SBorislav Petkov x86_pmu.late_ack = true; 5331e1069839SBorislav Petkov memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5332e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5333e1069839SBorislav Petkov 5334e1069839SBorislav Petkov /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5335e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5336e1069839SBorislav Petkov BDW_L3_MISS|HSW_SNOOP_DRAM; 5337e1069839SBorislav Petkov hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 5338e1069839SBorislav Petkov HSW_SNOOP_DRAM; 5339e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 5340e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5341e1069839SBorislav Petkov hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 5342e1069839SBorislav Petkov BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5343e1069839SBorislav Petkov 5344e1069839SBorislav Petkov intel_pmu_lbr_init_hsw(); 5345e1069839SBorislav Petkov 5346e1069839SBorislav Petkov x86_pmu.event_constraints = intel_bdw_event_constraints; 5347b3e62463SStephane Eranian x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 5348e1069839SBorislav Petkov x86_pmu.extra_regs = intel_snbep_extra_regs; 5349e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5350e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5351e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5352e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5353e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5354e1069839SBorislav Petkov 5355e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5356e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5357e1069839SBorislav Petkov x86_pmu.limit_period = bdw_limit_period; 5358a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5359a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5360baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5361d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5362d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5363e1069839SBorislav Petkov pr_cont("Broadwell events, "); 5364b00233b5SAndi Kleen name = "broadwell"; 5365e1069839SBorislav Petkov break; 5366e1069839SBorislav Petkov 5367ef5f9f47SDave Hansen case INTEL_FAM6_XEON_PHI_KNL: 5368608284bfSPiotr Luc case INTEL_FAM6_XEON_PHI_KNM: 5369e1069839SBorislav Petkov memcpy(hw_cache_event_ids, 5370e1069839SBorislav Petkov slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5371e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, 5372e1069839SBorislav Petkov knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5373e1069839SBorislav Petkov intel_pmu_lbr_init_knl(); 5374e1069839SBorislav Petkov 5375e1069839SBorislav Petkov x86_pmu.event_constraints = intel_slm_event_constraints; 5376e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5377e1069839SBorislav Petkov x86_pmu.extra_regs = intel_knl_extra_regs; 5378e1069839SBorislav Petkov 5379e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5380e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5381e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5382a5df70c3SAndi Kleen extra_attr = slm_format_attr; 5383608284bfSPiotr Luc pr_cont("Knights Landing/Mill events, "); 5384b00233b5SAndi Kleen name = "knights-landing"; 5385e1069839SBorislav Petkov break; 5386e1069839SBorislav Petkov 5387faaeff98SKan Liang case INTEL_FAM6_SKYLAKE_X: 5388faaeff98SKan Liang pmem = true; 5389df561f66SGustavo A. R. Silva fallthrough; 5390af239c44SPeter Zijlstra case INTEL_FAM6_SKYLAKE_L: 5391c66f78a6SPeter Zijlstra case INTEL_FAM6_SKYLAKE: 5392af239c44SPeter Zijlstra case INTEL_FAM6_KABYLAKE_L: 5393c66f78a6SPeter Zijlstra case INTEL_FAM6_KABYLAKE: 53949066288bSKan Liang case INTEL_FAM6_COMETLAKE_L: 53959066288bSKan Liang case INTEL_FAM6_COMETLAKE: 53969b545c04SAndi Kleen x86_add_quirk(intel_pebs_isolation_quirk); 5397e1069839SBorislav Petkov x86_pmu.late_ack = true; 5398e1069839SBorislav Petkov memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5399e1069839SBorislav Petkov memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5400e1069839SBorislav Petkov intel_pmu_lbr_init_skl(); 5401e1069839SBorislav Petkov 5402a39fcae7SAndi Kleen /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 5403a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_noht = 5404a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1"; 5405a39fcae7SAndi Kleen event_attr_td_recovery_bubbles.event_str_ht = 5406a39fcae7SAndi Kleen "event=0xd,umask=0x1,cmask=1,any=1"; 5407a39fcae7SAndi Kleen 5408e1069839SBorislav Petkov x86_pmu.event_constraints = intel_skl_event_constraints; 5409e1069839SBorislav Petkov x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 5410e1069839SBorislav Petkov x86_pmu.extra_regs = intel_skl_extra_regs; 5411e1069839SBorislav Petkov x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 5412e1069839SBorislav Petkov x86_pmu.pebs_prec_dist = true; 5413e1069839SBorislav Petkov /* all extra regs are per-cpu when HT is on */ 5414e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5415e1069839SBorislav Petkov x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5416e1069839SBorislav Petkov 5417e1069839SBorislav Petkov x86_pmu.hw_config = hsw_hw_config; 5418e1069839SBorislav Petkov x86_pmu.get_event_constraints = hsw_get_event_constraints; 5419a5df70c3SAndi Kleen extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5420a5df70c3SAndi Kleen hsw_format_attr : nhm_format_attr; 5421b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 5422baa0c833SJiri Olsa td_attr = hsw_events_attrs; 5423d4ae5529SJiri Olsa mem_attr = hsw_mem_events_attrs; 5424d4ae5529SJiri Olsa tsx_attr = hsw_tsx_events_attrs; 5425faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 5426400816f6SPeter Zijlstra (Intel) 5427400816f6SPeter Zijlstra (Intel) if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 5428400816f6SPeter Zijlstra (Intel) x86_pmu.flags |= PMU_FL_TFA; 5429400816f6SPeter Zijlstra (Intel) x86_pmu.get_event_constraints = tfa_get_event_constraints; 5430400816f6SPeter Zijlstra (Intel) x86_pmu.enable_all = intel_tfa_pmu_enable_all; 5431400816f6SPeter Zijlstra (Intel) x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 5432400816f6SPeter Zijlstra (Intel) } 5433400816f6SPeter Zijlstra (Intel) 5434e1069839SBorislav Petkov pr_cont("Skylake events, "); 5435b00233b5SAndi Kleen name = "skylake"; 5436e1069839SBorislav Petkov break; 5437e1069839SBorislav Petkov 5438faaeff98SKan Liang case INTEL_FAM6_ICELAKE_X: 54395ebb34edSPeter Zijlstra case INTEL_FAM6_ICELAKE_D: 5440faaeff98SKan Liang pmem = true; 5441df561f66SGustavo A. R. Silva fallthrough; 5442af239c44SPeter Zijlstra case INTEL_FAM6_ICELAKE_L: 5443c66f78a6SPeter Zijlstra case INTEL_FAM6_ICELAKE: 544423645a76SKan Liang case INTEL_FAM6_TIGERLAKE_L: 544523645a76SKan Liang case INTEL_FAM6_TIGERLAKE: 5446b14d0db5SKan Liang case INTEL_FAM6_ROCKETLAKE: 544760176089SKan Liang x86_pmu.late_ack = true; 544860176089SKan Liang memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 544960176089SKan Liang memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 545060176089SKan Liang hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 545160176089SKan Liang intel_pmu_lbr_init_skl(); 545260176089SKan Liang 545360176089SKan Liang x86_pmu.event_constraints = intel_icl_event_constraints; 545460176089SKan Liang x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 545560176089SKan Liang x86_pmu.extra_regs = intel_icl_extra_regs; 545660176089SKan Liang x86_pmu.pebs_aliases = NULL; 545760176089SKan Liang x86_pmu.pebs_prec_dist = true; 545860176089SKan Liang x86_pmu.flags |= PMU_FL_HAS_RSP_1; 545960176089SKan Liang x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 546060176089SKan Liang 546160176089SKan Liang x86_pmu.hw_config = hsw_hw_config; 546260176089SKan Liang x86_pmu.get_event_constraints = icl_get_event_constraints; 546360176089SKan Liang extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 546460176089SKan Liang hsw_format_attr : nhm_format_attr; 5465b6576880SJiri Olsa extra_skl_attr = skl_format_attr; 5466baa0c833SJiri Olsa mem_attr = icl_events_attrs; 546759a854e2SKan Liang td_attr = icl_td_events_attrs; 5468baa0c833SJiri Olsa tsx_attr = icl_tsx_events_attrs; 5469*46b72e1bSKan Liang x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 547060176089SKan Liang x86_pmu.lbr_pt_coexist = true; 5471faaeff98SKan Liang intel_pmu_pebs_data_source_skl(pmem); 547259a854e2SKan Liang x86_pmu.update_topdown_event = icl_update_topdown_event; 547359a854e2SKan Liang x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 547460176089SKan Liang pr_cont("Icelake events, "); 547560176089SKan Liang name = "icelake"; 547660176089SKan Liang break; 547760176089SKan Liang 5478e1069839SBorislav Petkov default: 5479e1069839SBorislav Petkov switch (x86_pmu.version) { 5480e1069839SBorislav Petkov case 1: 5481e1069839SBorislav Petkov x86_pmu.event_constraints = intel_v1_event_constraints; 5482e1069839SBorislav Petkov pr_cont("generic architected perfmon v1, "); 5483b00233b5SAndi Kleen name = "generic_arch_v1"; 5484e1069839SBorislav Petkov break; 5485e1069839SBorislav Petkov default: 5486e1069839SBorislav Petkov /* 5487e1069839SBorislav Petkov * default constraints for v2 and up 5488e1069839SBorislav Petkov */ 5489e1069839SBorislav Petkov x86_pmu.event_constraints = intel_gen_event_constraints; 5490e1069839SBorislav Petkov pr_cont("generic architected perfmon, "); 5491b00233b5SAndi Kleen name = "generic_arch_v2+"; 5492e1069839SBorislav Petkov break; 5493e1069839SBorislav Petkov } 5494e1069839SBorislav Petkov } 5495e1069839SBorislav Petkov 54960e96f31eSJordan Borgner snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 5497b00233b5SAndi Kleen 5498a5df70c3SAndi Kleen 5499baa0c833SJiri Olsa group_events_td.attrs = td_attr; 5500baa0c833SJiri Olsa group_events_mem.attrs = mem_attr; 5501baa0c833SJiri Olsa group_events_tsx.attrs = tsx_attr; 55023ea40ac7SJiri Olsa group_format_extra.attrs = extra_attr; 5503b6576880SJiri Olsa group_format_extra_skl.attrs = extra_skl_attr; 5504baa0c833SJiri Olsa 5505baa0c833SJiri Olsa x86_pmu.attr_update = attr_update; 5506d4ae5529SJiri Olsa 5507e1069839SBorislav Petkov if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 5508e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5509e1069839SBorislav Petkov x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 5510e1069839SBorislav Petkov x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 5511e1069839SBorislav Petkov } 5512ad5013d5SColin King x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 5513e1069839SBorislav Petkov 5514e1069839SBorislav Petkov if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5515e1069839SBorislav Petkov WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5516e1069839SBorislav Petkov x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 5517e1069839SBorislav Petkov x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 5518e1069839SBorislav Petkov } 5519e1069839SBorislav Petkov 5520e1069839SBorislav Petkov x86_pmu.intel_ctrl |= 5521e1069839SBorislav Petkov ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 5522e1069839SBorislav Petkov 5523cadbaa03SStephane Eranian /* AnyThread may be deprecated on arch perfmon v5 or later */ 5524cadbaa03SStephane Eranian if (x86_pmu.intel_cap.anythread_deprecated) 5525cadbaa03SStephane Eranian x86_pmu.format_attrs = intel_arch_formats_attr; 5526cadbaa03SStephane Eranian 5527e1069839SBorislav Petkov if (x86_pmu.event_constraints) { 5528e1069839SBorislav Petkov /* 5529e1069839SBorislav Petkov * event on fixed counter2 (REF_CYCLES) only works on this 5530e1069839SBorislav Petkov * counter, so do not extend mask to generic counters 5531e1069839SBorislav Petkov */ 5532e1069839SBorislav Petkov for_each_event_constraint(c, x86_pmu.event_constraints) { 55337b2c05a1SKan Liang /* 55347b2c05a1SKan Liang * Don't extend the topdown slots and metrics 55357b2c05a1SKan Liang * events to the generic counters. 55367b2c05a1SKan Liang */ 55377b2c05a1SKan Liang if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 55387b2c05a1SKan Liang c->weight = hweight64(c->idxmsk64); 55397b2c05a1SKan Liang continue; 55407b2c05a1SKan Liang } 55417b2c05a1SKan Liang 5542e1069839SBorislav Petkov if (c->cmask == FIXED_EVENT_FLAGS 5543e1069839SBorislav Petkov && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 5544e1069839SBorislav Petkov c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 5545e1069839SBorislav Petkov } 5546e1069839SBorislav Petkov c->idxmsk64 &= 55476d6f2833SAndrey Ryabinin ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 5548e1069839SBorislav Petkov c->weight = hweight64(c->idxmsk64); 5549e1069839SBorislav Petkov } 5550e1069839SBorislav Petkov } 5551e1069839SBorislav Petkov 5552e1069839SBorislav Petkov /* 5553e1069839SBorislav Petkov * Access LBR MSR may cause #GP under certain circumstances. 5554e1069839SBorislav Petkov * E.g. KVM doesn't support LBR MSR 5555e1069839SBorislav Petkov * Check all LBT MSR here. 5556e1069839SBorislav Petkov * Disable LBR access if any LBR MSRs can not be accessed. 5557e1069839SBorislav Petkov */ 5558e1069839SBorislav Petkov if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 5559e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 5560e1069839SBorislav Petkov for (i = 0; i < x86_pmu.lbr_nr; i++) { 5561e1069839SBorislav Petkov if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 5562e1069839SBorislav Petkov check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 5563e1069839SBorislav Petkov x86_pmu.lbr_nr = 0; 5564e1069839SBorislav Petkov } 5565e1069839SBorislav Petkov 55661f157286SJiri Olsa if (x86_pmu.lbr_nr) 5567f09509b9SDavid Carrillo-Cisneros pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 5568b00233b5SAndi Kleen 5569e1069839SBorislav Petkov /* 5570e1069839SBorislav Petkov * Access extra MSR may cause #GP under certain circumstances. 5571e1069839SBorislav Petkov * E.g. KVM doesn't support offcore event 5572e1069839SBorislav Petkov * Check all extra_regs here. 5573e1069839SBorislav Petkov */ 5574e1069839SBorislav Petkov if (x86_pmu.extra_regs) { 5575e1069839SBorislav Petkov for (er = x86_pmu.extra_regs; er->msr; er++) { 5576e1069839SBorislav Petkov er->extra_msr_access = check_msr(er->msr, 0x11UL); 5577e1069839SBorislav Petkov /* Disable LBR select mapping */ 5578e1069839SBorislav Petkov if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5579e1069839SBorislav Petkov x86_pmu.lbr_sel_map = NULL; 5580e1069839SBorislav Petkov } 5581e1069839SBorislav Petkov } 5582e1069839SBorislav Petkov 5583e1069839SBorislav Petkov /* Support full width counters using alternative MSR range */ 5584e1069839SBorislav Petkov if (x86_pmu.intel_cap.full_width_write) { 55857f612a7fSPeter Zijlstra (Intel) x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 5586e1069839SBorislav Petkov x86_pmu.perfctr = MSR_IA32_PMC0; 5587e1069839SBorislav Petkov pr_cont("full-width counters, "); 5588e1069839SBorislav Petkov } 5589e1069839SBorislav Petkov 5590af3bdb99SAndi Kleen /* 5591af3bdb99SAndi Kleen * For arch perfmon 4 use counter freezing to avoid 5592af3bdb99SAndi Kleen * several MSR accesses in the PMI. 5593af3bdb99SAndi Kleen */ 5594af3bdb99SAndi Kleen if (x86_pmu.counter_freezing) 5595af3bdb99SAndi Kleen x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 5596af3bdb99SAndi Kleen 559759a854e2SKan Liang if (x86_pmu.intel_cap.perf_metrics) 559859a854e2SKan Liang x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 559959a854e2SKan Liang 5600e1069839SBorislav Petkov return 0; 5601e1069839SBorislav Petkov } 5602e1069839SBorislav Petkov 5603e1069839SBorislav Petkov /* 5604e1069839SBorislav Petkov * HT bug: phase 2 init 5605e1069839SBorislav Petkov * Called once we have valid topology information to check 5606e1069839SBorislav Petkov * whether or not HT is enabled 5607e1069839SBorislav Petkov * If HT is off, then we disable the workaround 5608e1069839SBorislav Petkov */ 5609e1069839SBorislav Petkov static __init int fixup_ht_bug(void) 5610e1069839SBorislav Petkov { 5611030ba6cdSAndi Kleen int c; 5612e1069839SBorislav Petkov /* 5613e1069839SBorislav Petkov * problem not present on this CPU model, nothing to do 5614e1069839SBorislav Petkov */ 5615e1069839SBorislav Petkov if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 5616e1069839SBorislav Petkov return 0; 5617e1069839SBorislav Petkov 5618030ba6cdSAndi Kleen if (topology_max_smt_threads() > 1) { 5619e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 5620e1069839SBorislav Petkov return 0; 5621e1069839SBorislav Petkov } 5622e1069839SBorislav Petkov 56232406e3b1SPeter Zijlstra cpus_read_lock(); 56242406e3b1SPeter Zijlstra 56252406e3b1SPeter Zijlstra hardlockup_detector_perf_stop(); 5626e1069839SBorislav Petkov 5627e1069839SBorislav Petkov x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 5628e1069839SBorislav Petkov 5629e1069839SBorislav Petkov x86_pmu.start_scheduling = NULL; 5630e1069839SBorislav Petkov x86_pmu.commit_scheduling = NULL; 5631e1069839SBorislav Petkov x86_pmu.stop_scheduling = NULL; 5632e1069839SBorislav Petkov 56332406e3b1SPeter Zijlstra hardlockup_detector_perf_restart(); 5634e1069839SBorislav Petkov 56351ba143a5SSebastian Andrzej Siewior for_each_online_cpu(c) 5636d01b1f96SPeter Zijlstra (Intel) free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 5637e1069839SBorislav Petkov 56381ba143a5SSebastian Andrzej Siewior cpus_read_unlock(); 5639e1069839SBorislav Petkov pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 5640e1069839SBorislav Petkov return 0; 5641e1069839SBorislav Petkov } 5642e1069839SBorislav Petkov subsys_initcall(fixup_ht_bug) 5643