1 /* 2 * Performance events x86 architecture code 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 #include <linux/capability.h> 17 #include <linux/notifier.h> 18 #include <linux/hardirq.h> 19 #include <linux/kprobes.h> 20 #include <linux/export.h> 21 #include <linux/init.h> 22 #include <linux/kdebug.h> 23 #include <linux/sched/mm.h> 24 #include <linux/sched/clock.h> 25 #include <linux/uaccess.h> 26 #include <linux/slab.h> 27 #include <linux/cpu.h> 28 #include <linux/bitops.h> 29 #include <linux/device.h> 30 #include <linux/nospec.h> 31 32 #include <asm/apic.h> 33 #include <asm/stacktrace.h> 34 #include <asm/nmi.h> 35 #include <asm/smp.h> 36 #include <asm/alternative.h> 37 #include <asm/mmu_context.h> 38 #include <asm/tlbflush.h> 39 #include <asm/timer.h> 40 #include <asm/desc.h> 41 #include <asm/ldt.h> 42 #include <asm/unwind.h> 43 44 #include "perf_event.h" 45 46 struct x86_pmu x86_pmu __read_mostly; 47 48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { 49 .enabled = 1, 50 }; 51 52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key); 53 54 u64 __read_mostly hw_cache_event_ids 55 [PERF_COUNT_HW_CACHE_MAX] 56 [PERF_COUNT_HW_CACHE_OP_MAX] 57 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 58 u64 __read_mostly hw_cache_extra_regs 59 [PERF_COUNT_HW_CACHE_MAX] 60 [PERF_COUNT_HW_CACHE_OP_MAX] 61 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 62 63 /* 64 * Propagate event elapsed time into the generic event. 65 * Can only be executed on the CPU where the event is active. 66 * Returns the delta events processed. 67 */ 68 u64 x86_perf_event_update(struct perf_event *event) 69 { 70 struct hw_perf_event *hwc = &event->hw; 71 int shift = 64 - x86_pmu.cntval_bits; 72 u64 prev_raw_count, new_raw_count; 73 int idx = hwc->idx; 74 u64 delta; 75 76 if (idx == INTEL_PMC_IDX_FIXED_BTS) 77 return 0; 78 79 /* 80 * Careful: an NMI might modify the previous event value. 81 * 82 * Our tactic to handle this is to first atomically read and 83 * exchange a new raw count - then add that new-prev delta 84 * count to the generic event atomically: 85 */ 86 again: 87 prev_raw_count = local64_read(&hwc->prev_count); 88 rdpmcl(hwc->event_base_rdpmc, new_raw_count); 89 90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 91 new_raw_count) != prev_raw_count) 92 goto again; 93 94 /* 95 * Now we have the new raw value and have updated the prev 96 * timestamp already. We can now calculate the elapsed delta 97 * (event-)time and add that to the generic event. 98 * 99 * Careful, not all hw sign-extends above the physical width 100 * of the count. 101 */ 102 delta = (new_raw_count << shift) - (prev_raw_count << shift); 103 delta >>= shift; 104 105 local64_add(delta, &event->count); 106 local64_sub(delta, &hwc->period_left); 107 108 return new_raw_count; 109 } 110 111 /* 112 * Find and validate any extra registers to set up. 113 */ 114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event) 115 { 116 struct hw_perf_event_extra *reg; 117 struct extra_reg *er; 118 119 reg = &event->hw.extra_reg; 120 121 if (!x86_pmu.extra_regs) 122 return 0; 123 124 for (er = x86_pmu.extra_regs; er->msr; er++) { 125 if (er->event != (config & er->config_mask)) 126 continue; 127 if (event->attr.config1 & ~er->valid_mask) 128 return -EINVAL; 129 /* Check if the extra msrs can be safely accessed*/ 130 if (!er->extra_msr_access) 131 return -ENXIO; 132 133 reg->idx = er->idx; 134 reg->config = event->attr.config1; 135 reg->reg = er->msr; 136 break; 137 } 138 return 0; 139 } 140 141 static atomic_t active_events; 142 static atomic_t pmc_refcount; 143 static DEFINE_MUTEX(pmc_reserve_mutex); 144 145 #ifdef CONFIG_X86_LOCAL_APIC 146 147 static bool reserve_pmc_hardware(void) 148 { 149 int i; 150 151 for (i = 0; i < x86_pmu.num_counters; i++) { 152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) 153 goto perfctr_fail; 154 } 155 156 for (i = 0; i < x86_pmu.num_counters; i++) { 157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) 158 goto eventsel_fail; 159 } 160 161 return true; 162 163 eventsel_fail: 164 for (i--; i >= 0; i--) 165 release_evntsel_nmi(x86_pmu_config_addr(i)); 166 167 i = x86_pmu.num_counters; 168 169 perfctr_fail: 170 for (i--; i >= 0; i--) 171 release_perfctr_nmi(x86_pmu_event_addr(i)); 172 173 return false; 174 } 175 176 static void release_pmc_hardware(void) 177 { 178 int i; 179 180 for (i = 0; i < x86_pmu.num_counters; i++) { 181 release_perfctr_nmi(x86_pmu_event_addr(i)); 182 release_evntsel_nmi(x86_pmu_config_addr(i)); 183 } 184 } 185 186 #else 187 188 static bool reserve_pmc_hardware(void) { return true; } 189 static void release_pmc_hardware(void) {} 190 191 #endif 192 193 static bool check_hw_exists(void) 194 { 195 u64 val, val_fail = -1, val_new= ~0; 196 int i, reg, reg_fail = -1, ret = 0; 197 int bios_fail = 0; 198 int reg_safe = -1; 199 200 /* 201 * Check to see if the BIOS enabled any of the counters, if so 202 * complain and bail. 203 */ 204 for (i = 0; i < x86_pmu.num_counters; i++) { 205 reg = x86_pmu_config_addr(i); 206 ret = rdmsrl_safe(reg, &val); 207 if (ret) 208 goto msr_fail; 209 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { 210 bios_fail = 1; 211 val_fail = val; 212 reg_fail = reg; 213 } else { 214 reg_safe = i; 215 } 216 } 217 218 if (x86_pmu.num_counters_fixed) { 219 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 220 ret = rdmsrl_safe(reg, &val); 221 if (ret) 222 goto msr_fail; 223 for (i = 0; i < x86_pmu.num_counters_fixed; i++) { 224 if (val & (0x03 << i*4)) { 225 bios_fail = 1; 226 val_fail = val; 227 reg_fail = reg; 228 } 229 } 230 } 231 232 /* 233 * If all the counters are enabled, the below test will always 234 * fail. The tools will also become useless in this scenario. 235 * Just fail and disable the hardware counters. 236 */ 237 238 if (reg_safe == -1) { 239 reg = reg_safe; 240 goto msr_fail; 241 } 242 243 /* 244 * Read the current value, change it and read it back to see if it 245 * matches, this is needed to detect certain hardware emulators 246 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 247 */ 248 reg = x86_pmu_event_addr(reg_safe); 249 if (rdmsrl_safe(reg, &val)) 250 goto msr_fail; 251 val ^= 0xffffUL; 252 ret = wrmsrl_safe(reg, val); 253 ret |= rdmsrl_safe(reg, &val_new); 254 if (ret || val != val_new) 255 goto msr_fail; 256 257 /* 258 * We still allow the PMU driver to operate: 259 */ 260 if (bios_fail) { 261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); 262 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", 263 reg_fail, val_fail); 264 } 265 266 return true; 267 268 msr_fail: 269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 270 pr_cont("PMU not available due to virtualization, using software events only.\n"); 271 } else { 272 pr_cont("Broken PMU hardware detected, using software events only.\n"); 273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n", 274 reg, val_new); 275 } 276 277 return false; 278 } 279 280 static void hw_perf_event_destroy(struct perf_event *event) 281 { 282 x86_release_hardware(); 283 atomic_dec(&active_events); 284 } 285 286 void hw_perf_lbr_event_destroy(struct perf_event *event) 287 { 288 hw_perf_event_destroy(event); 289 290 /* undo the lbr/bts event accounting */ 291 x86_del_exclusive(x86_lbr_exclusive_lbr); 292 } 293 294 static inline int x86_pmu_initialized(void) 295 { 296 return x86_pmu.handle_irq != NULL; 297 } 298 299 static inline int 300 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) 301 { 302 struct perf_event_attr *attr = &event->attr; 303 unsigned int cache_type, cache_op, cache_result; 304 u64 config, val; 305 306 config = attr->config; 307 308 cache_type = (config >> 0) & 0xff; 309 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 310 return -EINVAL; 311 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX); 312 313 cache_op = (config >> 8) & 0xff; 314 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 315 return -EINVAL; 316 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX); 317 318 cache_result = (config >> 16) & 0xff; 319 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 320 return -EINVAL; 321 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX); 322 323 val = hw_cache_event_ids[cache_type][cache_op][cache_result]; 324 325 if (val == 0) 326 return -ENOENT; 327 328 if (val == -1) 329 return -EINVAL; 330 331 hwc->config |= val; 332 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; 333 return x86_pmu_extra_regs(val, event); 334 } 335 336 int x86_reserve_hardware(void) 337 { 338 int err = 0; 339 340 if (!atomic_inc_not_zero(&pmc_refcount)) { 341 mutex_lock(&pmc_reserve_mutex); 342 if (atomic_read(&pmc_refcount) == 0) { 343 if (!reserve_pmc_hardware()) 344 err = -EBUSY; 345 else 346 reserve_ds_buffers(); 347 } 348 if (!err) 349 atomic_inc(&pmc_refcount); 350 mutex_unlock(&pmc_reserve_mutex); 351 } 352 353 return err; 354 } 355 356 void x86_release_hardware(void) 357 { 358 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { 359 release_pmc_hardware(); 360 release_ds_buffers(); 361 mutex_unlock(&pmc_reserve_mutex); 362 } 363 } 364 365 /* 366 * Check if we can create event of a certain type (that no conflicting events 367 * are present). 368 */ 369 int x86_add_exclusive(unsigned int what) 370 { 371 int i; 372 373 /* 374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. 375 * LBR and BTS are still mutually exclusive. 376 */ 377 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) 378 return 0; 379 380 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { 381 mutex_lock(&pmc_reserve_mutex); 382 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { 383 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) 384 goto fail_unlock; 385 } 386 atomic_inc(&x86_pmu.lbr_exclusive[what]); 387 mutex_unlock(&pmc_reserve_mutex); 388 } 389 390 atomic_inc(&active_events); 391 return 0; 392 393 fail_unlock: 394 mutex_unlock(&pmc_reserve_mutex); 395 return -EBUSY; 396 } 397 398 void x86_del_exclusive(unsigned int what) 399 { 400 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) 401 return; 402 403 atomic_dec(&x86_pmu.lbr_exclusive[what]); 404 atomic_dec(&active_events); 405 } 406 407 int x86_setup_perfctr(struct perf_event *event) 408 { 409 struct perf_event_attr *attr = &event->attr; 410 struct hw_perf_event *hwc = &event->hw; 411 u64 config; 412 413 if (!is_sampling_event(event)) { 414 hwc->sample_period = x86_pmu.max_period; 415 hwc->last_period = hwc->sample_period; 416 local64_set(&hwc->period_left, hwc->sample_period); 417 } 418 419 if (attr->type == PERF_TYPE_RAW) 420 return x86_pmu_extra_regs(event->attr.config, event); 421 422 if (attr->type == PERF_TYPE_HW_CACHE) 423 return set_ext_hw_attr(hwc, event); 424 425 if (attr->config >= x86_pmu.max_events) 426 return -EINVAL; 427 428 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events); 429 430 /* 431 * The generic map: 432 */ 433 config = x86_pmu.event_map(attr->config); 434 435 if (config == 0) 436 return -ENOENT; 437 438 if (config == -1LL) 439 return -EINVAL; 440 441 /* 442 * Branch tracing: 443 */ 444 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && 445 !attr->freq && hwc->sample_period == 1) { 446 /* BTS is not supported by this architecture. */ 447 if (!x86_pmu.bts_active) 448 return -EOPNOTSUPP; 449 450 /* BTS is currently only allowed for user-mode. */ 451 if (!attr->exclude_kernel) 452 return -EOPNOTSUPP; 453 454 /* disallow bts if conflicting events are present */ 455 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 456 return -EBUSY; 457 458 event->destroy = hw_perf_lbr_event_destroy; 459 } 460 461 hwc->config |= config; 462 463 return 0; 464 } 465 466 /* 467 * check that branch_sample_type is compatible with 468 * settings needed for precise_ip > 1 which implies 469 * using the LBR to capture ALL taken branches at the 470 * priv levels of the measurement 471 */ 472 static inline int precise_br_compat(struct perf_event *event) 473 { 474 u64 m = event->attr.branch_sample_type; 475 u64 b = 0; 476 477 /* must capture all branches */ 478 if (!(m & PERF_SAMPLE_BRANCH_ANY)) 479 return 0; 480 481 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; 482 483 if (!event->attr.exclude_user) 484 b |= PERF_SAMPLE_BRANCH_USER; 485 486 if (!event->attr.exclude_kernel) 487 b |= PERF_SAMPLE_BRANCH_KERNEL; 488 489 /* 490 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 491 */ 492 493 return m == b; 494 } 495 496 int x86_pmu_max_precise(void) 497 { 498 int precise = 0; 499 500 /* Support for constant skid */ 501 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { 502 precise++; 503 504 /* Support for IP fixup */ 505 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) 506 precise++; 507 508 if (x86_pmu.pebs_prec_dist) 509 precise++; 510 } 511 return precise; 512 } 513 514 int x86_pmu_hw_config(struct perf_event *event) 515 { 516 if (event->attr.precise_ip) { 517 int precise = x86_pmu_max_precise(); 518 519 if (event->attr.precise_ip > precise) 520 return -EOPNOTSUPP; 521 522 /* There's no sense in having PEBS for non sampling events: */ 523 if (!is_sampling_event(event)) 524 return -EINVAL; 525 } 526 /* 527 * check that PEBS LBR correction does not conflict with 528 * whatever the user is asking with attr->branch_sample_type 529 */ 530 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { 531 u64 *br_type = &event->attr.branch_sample_type; 532 533 if (has_branch_stack(event)) { 534 if (!precise_br_compat(event)) 535 return -EOPNOTSUPP; 536 537 /* branch_sample_type is compatible */ 538 539 } else { 540 /* 541 * user did not specify branch_sample_type 542 * 543 * For PEBS fixups, we capture all 544 * the branches at the priv level of the 545 * event. 546 */ 547 *br_type = PERF_SAMPLE_BRANCH_ANY; 548 549 if (!event->attr.exclude_user) 550 *br_type |= PERF_SAMPLE_BRANCH_USER; 551 552 if (!event->attr.exclude_kernel) 553 *br_type |= PERF_SAMPLE_BRANCH_KERNEL; 554 } 555 } 556 557 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) 558 event->attach_state |= PERF_ATTACH_TASK_DATA; 559 560 /* 561 * Generate PMC IRQs: 562 * (keep 'enabled' bit clear for now) 563 */ 564 event->hw.config = ARCH_PERFMON_EVENTSEL_INT; 565 566 /* 567 * Count user and OS events unless requested not to 568 */ 569 if (!event->attr.exclude_user) 570 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; 571 if (!event->attr.exclude_kernel) 572 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; 573 574 if (event->attr.type == PERF_TYPE_RAW) 575 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; 576 577 if (event->attr.sample_period && x86_pmu.limit_period) { 578 if (x86_pmu.limit_period(event, event->attr.sample_period) > 579 event->attr.sample_period) 580 return -EINVAL; 581 } 582 583 return x86_setup_perfctr(event); 584 } 585 586 /* 587 * Setup the hardware configuration for a given attr_type 588 */ 589 static int __x86_pmu_event_init(struct perf_event *event) 590 { 591 int err; 592 593 if (!x86_pmu_initialized()) 594 return -ENODEV; 595 596 err = x86_reserve_hardware(); 597 if (err) 598 return err; 599 600 atomic_inc(&active_events); 601 event->destroy = hw_perf_event_destroy; 602 603 event->hw.idx = -1; 604 event->hw.last_cpu = -1; 605 event->hw.last_tag = ~0ULL; 606 607 /* mark unused */ 608 event->hw.extra_reg.idx = EXTRA_REG_NONE; 609 event->hw.branch_reg.idx = EXTRA_REG_NONE; 610 611 return x86_pmu.hw_config(event); 612 } 613 614 void x86_pmu_disable_all(void) 615 { 616 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 617 int idx; 618 619 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 620 u64 val; 621 622 if (!test_bit(idx, cpuc->active_mask)) 623 continue; 624 rdmsrl(x86_pmu_config_addr(idx), val); 625 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) 626 continue; 627 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 628 wrmsrl(x86_pmu_config_addr(idx), val); 629 } 630 } 631 632 /* 633 * There may be PMI landing after enabled=0. The PMI hitting could be before or 634 * after disable_all. 635 * 636 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. 637 * It will not be re-enabled in the NMI handler again, because enabled=0. After 638 * handling the NMI, disable_all will be called, which will not change the 639 * state either. If PMI hits after disable_all, the PMU is already disabled 640 * before entering NMI handler. The NMI handler will not change the state 641 * either. 642 * 643 * So either situation is harmless. 644 */ 645 static void x86_pmu_disable(struct pmu *pmu) 646 { 647 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 648 649 if (!x86_pmu_initialized()) 650 return; 651 652 if (!cpuc->enabled) 653 return; 654 655 cpuc->n_added = 0; 656 cpuc->enabled = 0; 657 barrier(); 658 659 x86_pmu.disable_all(); 660 } 661 662 void x86_pmu_enable_all(int added) 663 { 664 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 665 int idx; 666 667 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 668 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 669 670 if (!test_bit(idx, cpuc->active_mask)) 671 continue; 672 673 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 674 } 675 } 676 677 static struct pmu pmu; 678 679 static inline int is_x86_event(struct perf_event *event) 680 { 681 return event->pmu == &pmu; 682 } 683 684 /* 685 * Event scheduler state: 686 * 687 * Assign events iterating over all events and counters, beginning 688 * with events with least weights first. Keep the current iterator 689 * state in struct sched_state. 690 */ 691 struct sched_state { 692 int weight; 693 int event; /* event index */ 694 int counter; /* counter index */ 695 int unassigned; /* number of events to be assigned left */ 696 int nr_gp; /* number of GP counters used */ 697 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 698 }; 699 700 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ 701 #define SCHED_STATES_MAX 2 702 703 struct perf_sched { 704 int max_weight; 705 int max_events; 706 int max_gp; 707 int saved_states; 708 struct event_constraint **constraints; 709 struct sched_state state; 710 struct sched_state saved[SCHED_STATES_MAX]; 711 }; 712 713 /* 714 * Initialize interator that runs through all events and counters. 715 */ 716 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, 717 int num, int wmin, int wmax, int gpmax) 718 { 719 int idx; 720 721 memset(sched, 0, sizeof(*sched)); 722 sched->max_events = num; 723 sched->max_weight = wmax; 724 sched->max_gp = gpmax; 725 sched->constraints = constraints; 726 727 for (idx = 0; idx < num; idx++) { 728 if (constraints[idx]->weight == wmin) 729 break; 730 } 731 732 sched->state.event = idx; /* start with min weight */ 733 sched->state.weight = wmin; 734 sched->state.unassigned = num; 735 } 736 737 static void perf_sched_save_state(struct perf_sched *sched) 738 { 739 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) 740 return; 741 742 sched->saved[sched->saved_states] = sched->state; 743 sched->saved_states++; 744 } 745 746 static bool perf_sched_restore_state(struct perf_sched *sched) 747 { 748 if (!sched->saved_states) 749 return false; 750 751 sched->saved_states--; 752 sched->state = sched->saved[sched->saved_states]; 753 754 /* continue with next counter: */ 755 clear_bit(sched->state.counter++, sched->state.used); 756 757 return true; 758 } 759 760 /* 761 * Select a counter for the current event to schedule. Return true on 762 * success. 763 */ 764 static bool __perf_sched_find_counter(struct perf_sched *sched) 765 { 766 struct event_constraint *c; 767 int idx; 768 769 if (!sched->state.unassigned) 770 return false; 771 772 if (sched->state.event >= sched->max_events) 773 return false; 774 775 c = sched->constraints[sched->state.event]; 776 /* Prefer fixed purpose counters */ 777 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { 778 idx = INTEL_PMC_IDX_FIXED; 779 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { 780 if (!__test_and_set_bit(idx, sched->state.used)) 781 goto done; 782 } 783 } 784 785 /* Grab the first unused counter starting with idx */ 786 idx = sched->state.counter; 787 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { 788 if (!__test_and_set_bit(idx, sched->state.used)) { 789 if (sched->state.nr_gp++ >= sched->max_gp) 790 return false; 791 792 goto done; 793 } 794 } 795 796 return false; 797 798 done: 799 sched->state.counter = idx; 800 801 if (c->overlap) 802 perf_sched_save_state(sched); 803 804 return true; 805 } 806 807 static bool perf_sched_find_counter(struct perf_sched *sched) 808 { 809 while (!__perf_sched_find_counter(sched)) { 810 if (!perf_sched_restore_state(sched)) 811 return false; 812 } 813 814 return true; 815 } 816 817 /* 818 * Go through all unassigned events and find the next one to schedule. 819 * Take events with the least weight first. Return true on success. 820 */ 821 static bool perf_sched_next_event(struct perf_sched *sched) 822 { 823 struct event_constraint *c; 824 825 if (!sched->state.unassigned || !--sched->state.unassigned) 826 return false; 827 828 do { 829 /* next event */ 830 sched->state.event++; 831 if (sched->state.event >= sched->max_events) { 832 /* next weight */ 833 sched->state.event = 0; 834 sched->state.weight++; 835 if (sched->state.weight > sched->max_weight) 836 return false; 837 } 838 c = sched->constraints[sched->state.event]; 839 } while (c->weight != sched->state.weight); 840 841 sched->state.counter = 0; /* start with first counter */ 842 843 return true; 844 } 845 846 /* 847 * Assign a counter for each event. 848 */ 849 int perf_assign_events(struct event_constraint **constraints, int n, 850 int wmin, int wmax, int gpmax, int *assign) 851 { 852 struct perf_sched sched; 853 854 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); 855 856 do { 857 if (!perf_sched_find_counter(&sched)) 858 break; /* failed */ 859 if (assign) 860 assign[sched.state.event] = sched.state.counter; 861 } while (perf_sched_next_event(&sched)); 862 863 return sched.state.unassigned; 864 } 865 EXPORT_SYMBOL_GPL(perf_assign_events); 866 867 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) 868 { 869 struct event_constraint *c; 870 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 871 struct perf_event *e; 872 int i, wmin, wmax, unsched = 0; 873 struct hw_perf_event *hwc; 874 875 bitmap_zero(used_mask, X86_PMC_IDX_MAX); 876 877 if (x86_pmu.start_scheduling) 878 x86_pmu.start_scheduling(cpuc); 879 880 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { 881 cpuc->event_constraint[i] = NULL; 882 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); 883 cpuc->event_constraint[i] = c; 884 885 wmin = min(wmin, c->weight); 886 wmax = max(wmax, c->weight); 887 } 888 889 /* 890 * fastpath, try to reuse previous register 891 */ 892 for (i = 0; i < n; i++) { 893 hwc = &cpuc->event_list[i]->hw; 894 c = cpuc->event_constraint[i]; 895 896 /* never assigned */ 897 if (hwc->idx == -1) 898 break; 899 900 /* constraint still honored */ 901 if (!test_bit(hwc->idx, c->idxmsk)) 902 break; 903 904 /* not already used */ 905 if (test_bit(hwc->idx, used_mask)) 906 break; 907 908 __set_bit(hwc->idx, used_mask); 909 if (assign) 910 assign[i] = hwc->idx; 911 } 912 913 /* slow path */ 914 if (i != n) { 915 int gpmax = x86_pmu.num_counters; 916 917 /* 918 * Do not allow scheduling of more than half the available 919 * generic counters. 920 * 921 * This helps avoid counter starvation of sibling thread by 922 * ensuring at most half the counters cannot be in exclusive 923 * mode. There is no designated counters for the limits. Any 924 * N/2 counters can be used. This helps with events with 925 * specific counter constraints. 926 */ 927 if (is_ht_workaround_enabled() && !cpuc->is_fake && 928 READ_ONCE(cpuc->excl_cntrs->exclusive_present)) 929 gpmax /= 2; 930 931 unsched = perf_assign_events(cpuc->event_constraint, n, wmin, 932 wmax, gpmax, assign); 933 } 934 935 /* 936 * In case of success (unsched = 0), mark events as committed, 937 * so we do not put_constraint() in case new events are added 938 * and fail to be scheduled 939 * 940 * We invoke the lower level commit callback to lock the resource 941 * 942 * We do not need to do all of this in case we are called to 943 * validate an event group (assign == NULL) 944 */ 945 if (!unsched && assign) { 946 for (i = 0; i < n; i++) { 947 e = cpuc->event_list[i]; 948 e->hw.flags |= PERF_X86_EVENT_COMMITTED; 949 if (x86_pmu.commit_scheduling) 950 x86_pmu.commit_scheduling(cpuc, i, assign[i]); 951 } 952 } else { 953 for (i = 0; i < n; i++) { 954 e = cpuc->event_list[i]; 955 /* 956 * do not put_constraint() on comitted events, 957 * because they are good to go 958 */ 959 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) 960 continue; 961 962 /* 963 * release events that failed scheduling 964 */ 965 if (x86_pmu.put_event_constraints) 966 x86_pmu.put_event_constraints(cpuc, e); 967 } 968 } 969 970 if (x86_pmu.stop_scheduling) 971 x86_pmu.stop_scheduling(cpuc); 972 973 return unsched ? -EINVAL : 0; 974 } 975 976 /* 977 * dogrp: true if must collect siblings events (group) 978 * returns total number of events and error code 979 */ 980 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) 981 { 982 struct perf_event *event; 983 int n, max_count; 984 985 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; 986 987 /* current number of events already accepted */ 988 n = cpuc->n_events; 989 990 if (is_x86_event(leader)) { 991 if (n >= max_count) 992 return -EINVAL; 993 cpuc->event_list[n] = leader; 994 n++; 995 } 996 if (!dogrp) 997 return n; 998 999 for_each_sibling_event(event, leader) { 1000 if (!is_x86_event(event) || 1001 event->state <= PERF_EVENT_STATE_OFF) 1002 continue; 1003 1004 if (n >= max_count) 1005 return -EINVAL; 1006 1007 cpuc->event_list[n] = event; 1008 n++; 1009 } 1010 return n; 1011 } 1012 1013 static inline void x86_assign_hw_event(struct perf_event *event, 1014 struct cpu_hw_events *cpuc, int i) 1015 { 1016 struct hw_perf_event *hwc = &event->hw; 1017 1018 hwc->idx = cpuc->assign[i]; 1019 hwc->last_cpu = smp_processor_id(); 1020 hwc->last_tag = ++cpuc->tags[i]; 1021 1022 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { 1023 hwc->config_base = 0; 1024 hwc->event_base = 0; 1025 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { 1026 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 1027 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); 1028 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; 1029 } else { 1030 hwc->config_base = x86_pmu_config_addr(hwc->idx); 1031 hwc->event_base = x86_pmu_event_addr(hwc->idx); 1032 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); 1033 } 1034 } 1035 1036 static inline int match_prev_assignment(struct hw_perf_event *hwc, 1037 struct cpu_hw_events *cpuc, 1038 int i) 1039 { 1040 return hwc->idx == cpuc->assign[i] && 1041 hwc->last_cpu == smp_processor_id() && 1042 hwc->last_tag == cpuc->tags[i]; 1043 } 1044 1045 static void x86_pmu_start(struct perf_event *event, int flags); 1046 1047 static void x86_pmu_enable(struct pmu *pmu) 1048 { 1049 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1050 struct perf_event *event; 1051 struct hw_perf_event *hwc; 1052 int i, added = cpuc->n_added; 1053 1054 if (!x86_pmu_initialized()) 1055 return; 1056 1057 if (cpuc->enabled) 1058 return; 1059 1060 if (cpuc->n_added) { 1061 int n_running = cpuc->n_events - cpuc->n_added; 1062 /* 1063 * apply assignment obtained either from 1064 * hw_perf_group_sched_in() or x86_pmu_enable() 1065 * 1066 * step1: save events moving to new counters 1067 */ 1068 for (i = 0; i < n_running; i++) { 1069 event = cpuc->event_list[i]; 1070 hwc = &event->hw; 1071 1072 /* 1073 * we can avoid reprogramming counter if: 1074 * - assigned same counter as last time 1075 * - running on same CPU as last time 1076 * - no other event has used the counter since 1077 */ 1078 if (hwc->idx == -1 || 1079 match_prev_assignment(hwc, cpuc, i)) 1080 continue; 1081 1082 /* 1083 * Ensure we don't accidentally enable a stopped 1084 * counter simply because we rescheduled. 1085 */ 1086 if (hwc->state & PERF_HES_STOPPED) 1087 hwc->state |= PERF_HES_ARCH; 1088 1089 x86_pmu_stop(event, PERF_EF_UPDATE); 1090 } 1091 1092 /* 1093 * step2: reprogram moved events into new counters 1094 */ 1095 for (i = 0; i < cpuc->n_events; i++) { 1096 event = cpuc->event_list[i]; 1097 hwc = &event->hw; 1098 1099 if (!match_prev_assignment(hwc, cpuc, i)) 1100 x86_assign_hw_event(event, cpuc, i); 1101 else if (i < n_running) 1102 continue; 1103 1104 if (hwc->state & PERF_HES_ARCH) 1105 continue; 1106 1107 x86_pmu_start(event, PERF_EF_RELOAD); 1108 } 1109 cpuc->n_added = 0; 1110 perf_events_lapic_init(); 1111 } 1112 1113 cpuc->enabled = 1; 1114 barrier(); 1115 1116 x86_pmu.enable_all(added); 1117 } 1118 1119 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1120 1121 /* 1122 * Set the next IRQ period, based on the hwc->period_left value. 1123 * To be called with the event disabled in hw: 1124 */ 1125 int x86_perf_event_set_period(struct perf_event *event) 1126 { 1127 struct hw_perf_event *hwc = &event->hw; 1128 s64 left = local64_read(&hwc->period_left); 1129 s64 period = hwc->sample_period; 1130 int ret = 0, idx = hwc->idx; 1131 1132 if (idx == INTEL_PMC_IDX_FIXED_BTS) 1133 return 0; 1134 1135 /* 1136 * If we are way outside a reasonable range then just skip forward: 1137 */ 1138 if (unlikely(left <= -period)) { 1139 left = period; 1140 local64_set(&hwc->period_left, left); 1141 hwc->last_period = period; 1142 ret = 1; 1143 } 1144 1145 if (unlikely(left <= 0)) { 1146 left += period; 1147 local64_set(&hwc->period_left, left); 1148 hwc->last_period = period; 1149 ret = 1; 1150 } 1151 /* 1152 * Quirk: certain CPUs dont like it if just 1 hw_event is left: 1153 */ 1154 if (unlikely(left < 2)) 1155 left = 2; 1156 1157 if (left > x86_pmu.max_period) 1158 left = x86_pmu.max_period; 1159 1160 if (x86_pmu.limit_period) 1161 left = x86_pmu.limit_period(event, left); 1162 1163 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; 1164 1165 /* 1166 * The hw event starts counting from this event offset, 1167 * mark it to be able to extra future deltas: 1168 */ 1169 local64_set(&hwc->prev_count, (u64)-left); 1170 1171 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1172 1173 /* 1174 * Due to erratum on certan cpu we need 1175 * a second write to be sure the register 1176 * is updated properly 1177 */ 1178 if (x86_pmu.perfctr_second_write) { 1179 wrmsrl(hwc->event_base, 1180 (u64)(-left) & x86_pmu.cntval_mask); 1181 } 1182 1183 perf_event_update_userpage(event); 1184 1185 return ret; 1186 } 1187 1188 void x86_pmu_enable_event(struct perf_event *event) 1189 { 1190 if (__this_cpu_read(cpu_hw_events.enabled)) 1191 __x86_pmu_enable_event(&event->hw, 1192 ARCH_PERFMON_EVENTSEL_ENABLE); 1193 } 1194 1195 /* 1196 * Add a single event to the PMU. 1197 * 1198 * The event is added to the group of enabled events 1199 * but only if it can be scehduled with existing events. 1200 */ 1201 static int x86_pmu_add(struct perf_event *event, int flags) 1202 { 1203 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1204 struct hw_perf_event *hwc; 1205 int assign[X86_PMC_IDX_MAX]; 1206 int n, n0, ret; 1207 1208 hwc = &event->hw; 1209 1210 n0 = cpuc->n_events; 1211 ret = n = collect_events(cpuc, event, false); 1212 if (ret < 0) 1213 goto out; 1214 1215 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1216 if (!(flags & PERF_EF_START)) 1217 hwc->state |= PERF_HES_ARCH; 1218 1219 /* 1220 * If group events scheduling transaction was started, 1221 * skip the schedulability test here, it will be performed 1222 * at commit time (->commit_txn) as a whole. 1223 * 1224 * If commit fails, we'll call ->del() on all events 1225 * for which ->add() was called. 1226 */ 1227 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1228 goto done_collect; 1229 1230 ret = x86_pmu.schedule_events(cpuc, n, assign); 1231 if (ret) 1232 goto out; 1233 /* 1234 * copy new assignment, now we know it is possible 1235 * will be used by hw_perf_enable() 1236 */ 1237 memcpy(cpuc->assign, assign, n*sizeof(int)); 1238 1239 done_collect: 1240 /* 1241 * Commit the collect_events() state. See x86_pmu_del() and 1242 * x86_pmu_*_txn(). 1243 */ 1244 cpuc->n_events = n; 1245 cpuc->n_added += n - n0; 1246 cpuc->n_txn += n - n0; 1247 1248 if (x86_pmu.add) { 1249 /* 1250 * This is before x86_pmu_enable() will call x86_pmu_start(), 1251 * so we enable LBRs before an event needs them etc.. 1252 */ 1253 x86_pmu.add(event); 1254 } 1255 1256 ret = 0; 1257 out: 1258 return ret; 1259 } 1260 1261 static void x86_pmu_start(struct perf_event *event, int flags) 1262 { 1263 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1264 int idx = event->hw.idx; 1265 1266 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) 1267 return; 1268 1269 if (WARN_ON_ONCE(idx == -1)) 1270 return; 1271 1272 if (flags & PERF_EF_RELOAD) { 1273 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1274 x86_perf_event_set_period(event); 1275 } 1276 1277 event->hw.state = 0; 1278 1279 cpuc->events[idx] = event; 1280 __set_bit(idx, cpuc->active_mask); 1281 __set_bit(idx, cpuc->running); 1282 x86_pmu.enable(event); 1283 perf_event_update_userpage(event); 1284 } 1285 1286 void perf_event_print_debug(void) 1287 { 1288 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; 1289 u64 pebs, debugctl; 1290 struct cpu_hw_events *cpuc; 1291 unsigned long flags; 1292 int cpu, idx; 1293 1294 if (!x86_pmu.num_counters) 1295 return; 1296 1297 local_irq_save(flags); 1298 1299 cpu = smp_processor_id(); 1300 cpuc = &per_cpu(cpu_hw_events, cpu); 1301 1302 if (x86_pmu.version >= 2) { 1303 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); 1304 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 1305 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); 1306 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); 1307 1308 pr_info("\n"); 1309 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); 1310 pr_info("CPU#%d: status: %016llx\n", cpu, status); 1311 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); 1312 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); 1313 if (x86_pmu.pebs_constraints) { 1314 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); 1315 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); 1316 } 1317 if (x86_pmu.lbr_nr) { 1318 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1319 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); 1320 } 1321 } 1322 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); 1323 1324 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1325 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); 1326 rdmsrl(x86_pmu_event_addr(idx), pmc_count); 1327 1328 prev_left = per_cpu(pmc_prev_left[idx], cpu); 1329 1330 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", 1331 cpu, idx, pmc_ctrl); 1332 pr_info("CPU#%d: gen-PMC%d count: %016llx\n", 1333 cpu, idx, pmc_count); 1334 pr_info("CPU#%d: gen-PMC%d left: %016llx\n", 1335 cpu, idx, prev_left); 1336 } 1337 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { 1338 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); 1339 1340 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", 1341 cpu, idx, pmc_count); 1342 } 1343 local_irq_restore(flags); 1344 } 1345 1346 void x86_pmu_stop(struct perf_event *event, int flags) 1347 { 1348 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1349 struct hw_perf_event *hwc = &event->hw; 1350 1351 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { 1352 x86_pmu.disable(event); 1353 cpuc->events[hwc->idx] = NULL; 1354 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); 1355 hwc->state |= PERF_HES_STOPPED; 1356 } 1357 1358 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 1359 /* 1360 * Drain the remaining delta count out of a event 1361 * that we are disabling: 1362 */ 1363 x86_perf_event_update(event); 1364 hwc->state |= PERF_HES_UPTODATE; 1365 } 1366 } 1367 1368 static void x86_pmu_del(struct perf_event *event, int flags) 1369 { 1370 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1371 int i; 1372 1373 /* 1374 * event is descheduled 1375 */ 1376 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; 1377 1378 /* 1379 * If we're called during a txn, we only need to undo x86_pmu.add. 1380 * The events never got scheduled and ->cancel_txn will truncate 1381 * the event_list. 1382 * 1383 * XXX assumes any ->del() called during a TXN will only be on 1384 * an event added during that same TXN. 1385 */ 1386 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1387 goto do_del; 1388 1389 /* 1390 * Not a TXN, therefore cleanup properly. 1391 */ 1392 x86_pmu_stop(event, PERF_EF_UPDATE); 1393 1394 for (i = 0; i < cpuc->n_events; i++) { 1395 if (event == cpuc->event_list[i]) 1396 break; 1397 } 1398 1399 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ 1400 return; 1401 1402 /* If we have a newly added event; make sure to decrease n_added. */ 1403 if (i >= cpuc->n_events - cpuc->n_added) 1404 --cpuc->n_added; 1405 1406 if (x86_pmu.put_event_constraints) 1407 x86_pmu.put_event_constraints(cpuc, event); 1408 1409 /* Delete the array entry. */ 1410 while (++i < cpuc->n_events) { 1411 cpuc->event_list[i-1] = cpuc->event_list[i]; 1412 cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; 1413 } 1414 --cpuc->n_events; 1415 1416 perf_event_update_userpage(event); 1417 1418 do_del: 1419 if (x86_pmu.del) { 1420 /* 1421 * This is after x86_pmu_stop(); so we disable LBRs after any 1422 * event can need them etc.. 1423 */ 1424 x86_pmu.del(event); 1425 } 1426 } 1427 1428 int x86_pmu_handle_irq(struct pt_regs *regs) 1429 { 1430 struct perf_sample_data data; 1431 struct cpu_hw_events *cpuc; 1432 struct perf_event *event; 1433 int idx, handled = 0; 1434 u64 val; 1435 1436 cpuc = this_cpu_ptr(&cpu_hw_events); 1437 1438 /* 1439 * Some chipsets need to unmask the LVTPC in a particular spot 1440 * inside the nmi handler. As a result, the unmasking was pushed 1441 * into all the nmi handlers. 1442 * 1443 * This generic handler doesn't seem to have any issues where the 1444 * unmasking occurs so it was left at the top. 1445 */ 1446 apic_write(APIC_LVTPC, APIC_DM_NMI); 1447 1448 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1449 if (!test_bit(idx, cpuc->active_mask)) { 1450 /* 1451 * Though we deactivated the counter some cpus 1452 * might still deliver spurious interrupts still 1453 * in flight. Catch them: 1454 */ 1455 if (__test_and_clear_bit(idx, cpuc->running)) 1456 handled++; 1457 continue; 1458 } 1459 1460 event = cpuc->events[idx]; 1461 1462 val = x86_perf_event_update(event); 1463 if (val & (1ULL << (x86_pmu.cntval_bits - 1))) 1464 continue; 1465 1466 /* 1467 * event overflow 1468 */ 1469 handled++; 1470 perf_sample_data_init(&data, 0, event->hw.last_period); 1471 1472 if (!x86_perf_event_set_period(event)) 1473 continue; 1474 1475 if (perf_event_overflow(event, &data, regs)) 1476 x86_pmu_stop(event, 0); 1477 } 1478 1479 if (handled) 1480 inc_irq_stat(apic_perf_irqs); 1481 1482 return handled; 1483 } 1484 1485 void perf_events_lapic_init(void) 1486 { 1487 if (!x86_pmu.apic || !x86_pmu_initialized()) 1488 return; 1489 1490 /* 1491 * Always use NMI for PMU 1492 */ 1493 apic_write(APIC_LVTPC, APIC_DM_NMI); 1494 } 1495 1496 static int 1497 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) 1498 { 1499 u64 start_clock; 1500 u64 finish_clock; 1501 int ret; 1502 1503 /* 1504 * All PMUs/events that share this PMI handler should make sure to 1505 * increment active_events for their events. 1506 */ 1507 if (!atomic_read(&active_events)) 1508 return NMI_DONE; 1509 1510 start_clock = sched_clock(); 1511 ret = x86_pmu.handle_irq(regs); 1512 finish_clock = sched_clock(); 1513 1514 perf_sample_event_took(finish_clock - start_clock); 1515 1516 return ret; 1517 } 1518 NOKPROBE_SYMBOL(perf_event_nmi_handler); 1519 1520 struct event_constraint emptyconstraint; 1521 struct event_constraint unconstrained; 1522 1523 static int x86_pmu_prepare_cpu(unsigned int cpu) 1524 { 1525 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1526 int i; 1527 1528 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) 1529 cpuc->kfree_on_online[i] = NULL; 1530 if (x86_pmu.cpu_prepare) 1531 return x86_pmu.cpu_prepare(cpu); 1532 return 0; 1533 } 1534 1535 static int x86_pmu_dead_cpu(unsigned int cpu) 1536 { 1537 if (x86_pmu.cpu_dead) 1538 x86_pmu.cpu_dead(cpu); 1539 return 0; 1540 } 1541 1542 static int x86_pmu_online_cpu(unsigned int cpu) 1543 { 1544 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1545 int i; 1546 1547 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { 1548 kfree(cpuc->kfree_on_online[i]); 1549 cpuc->kfree_on_online[i] = NULL; 1550 } 1551 return 0; 1552 } 1553 1554 static int x86_pmu_starting_cpu(unsigned int cpu) 1555 { 1556 if (x86_pmu.cpu_starting) 1557 x86_pmu.cpu_starting(cpu); 1558 return 0; 1559 } 1560 1561 static int x86_pmu_dying_cpu(unsigned int cpu) 1562 { 1563 if (x86_pmu.cpu_dying) 1564 x86_pmu.cpu_dying(cpu); 1565 return 0; 1566 } 1567 1568 static void __init pmu_check_apic(void) 1569 { 1570 if (boot_cpu_has(X86_FEATURE_APIC)) 1571 return; 1572 1573 x86_pmu.apic = 0; 1574 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); 1575 pr_info("no hardware sampling interrupt available.\n"); 1576 1577 /* 1578 * If we have a PMU initialized but no APIC 1579 * interrupts, we cannot sample hardware 1580 * events (user-space has to fall back and 1581 * sample via a hrtimer based software event): 1582 */ 1583 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; 1584 1585 } 1586 1587 static struct attribute_group x86_pmu_format_group = { 1588 .name = "format", 1589 .attrs = NULL, 1590 }; 1591 1592 /* 1593 * Remove all undefined events (x86_pmu.event_map(id) == 0) 1594 * out of events_attr attributes. 1595 */ 1596 static void __init filter_events(struct attribute **attrs) 1597 { 1598 struct device_attribute *d; 1599 struct perf_pmu_events_attr *pmu_attr; 1600 int offset = 0; 1601 int i, j; 1602 1603 for (i = 0; attrs[i]; i++) { 1604 d = (struct device_attribute *)attrs[i]; 1605 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); 1606 /* str trumps id */ 1607 if (pmu_attr->event_str) 1608 continue; 1609 if (x86_pmu.event_map(i + offset)) 1610 continue; 1611 1612 for (j = i; attrs[j]; j++) 1613 attrs[j] = attrs[j + 1]; 1614 1615 /* Check the shifted attr. */ 1616 i--; 1617 1618 /* 1619 * event_map() is index based, the attrs array is organized 1620 * by increasing event index. If we shift the events, then 1621 * we need to compensate for the event_map(), otherwise 1622 * we are looking up the wrong event in the map 1623 */ 1624 offset++; 1625 } 1626 } 1627 1628 /* Merge two pointer arrays */ 1629 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) 1630 { 1631 struct attribute **new; 1632 int j, i; 1633 1634 for (j = 0; a[j]; j++) 1635 ; 1636 for (i = 0; b[i]; i++) 1637 j++; 1638 j++; 1639 1640 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL); 1641 if (!new) 1642 return NULL; 1643 1644 j = 0; 1645 for (i = 0; a[i]; i++) 1646 new[j++] = a[i]; 1647 for (i = 0; b[i]; i++) 1648 new[j++] = b[i]; 1649 new[j] = NULL; 1650 1651 return new; 1652 } 1653 1654 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) 1655 { 1656 struct perf_pmu_events_attr *pmu_attr = \ 1657 container_of(attr, struct perf_pmu_events_attr, attr); 1658 u64 config = x86_pmu.event_map(pmu_attr->id); 1659 1660 /* string trumps id */ 1661 if (pmu_attr->event_str) 1662 return sprintf(page, "%s", pmu_attr->event_str); 1663 1664 return x86_pmu.events_sysfs_show(page, config); 1665 } 1666 EXPORT_SYMBOL_GPL(events_sysfs_show); 1667 1668 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1669 char *page) 1670 { 1671 struct perf_pmu_events_ht_attr *pmu_attr = 1672 container_of(attr, struct perf_pmu_events_ht_attr, attr); 1673 1674 /* 1675 * Report conditional events depending on Hyper-Threading. 1676 * 1677 * This is overly conservative as usually the HT special 1678 * handling is not needed if the other CPU thread is idle. 1679 * 1680 * Note this does not (and cannot) handle the case when thread 1681 * siblings are invisible, for example with virtualization 1682 * if they are owned by some other guest. The user tool 1683 * has to re-read when a thread sibling gets onlined later. 1684 */ 1685 return sprintf(page, "%s", 1686 topology_max_smt_threads() > 1 ? 1687 pmu_attr->event_str_ht : 1688 pmu_attr->event_str_noht); 1689 } 1690 1691 EVENT_ATTR(cpu-cycles, CPU_CYCLES ); 1692 EVENT_ATTR(instructions, INSTRUCTIONS ); 1693 EVENT_ATTR(cache-references, CACHE_REFERENCES ); 1694 EVENT_ATTR(cache-misses, CACHE_MISSES ); 1695 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); 1696 EVENT_ATTR(branch-misses, BRANCH_MISSES ); 1697 EVENT_ATTR(bus-cycles, BUS_CYCLES ); 1698 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); 1699 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); 1700 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); 1701 1702 static struct attribute *empty_attrs; 1703 1704 static struct attribute *events_attr[] = { 1705 EVENT_PTR(CPU_CYCLES), 1706 EVENT_PTR(INSTRUCTIONS), 1707 EVENT_PTR(CACHE_REFERENCES), 1708 EVENT_PTR(CACHE_MISSES), 1709 EVENT_PTR(BRANCH_INSTRUCTIONS), 1710 EVENT_PTR(BRANCH_MISSES), 1711 EVENT_PTR(BUS_CYCLES), 1712 EVENT_PTR(STALLED_CYCLES_FRONTEND), 1713 EVENT_PTR(STALLED_CYCLES_BACKEND), 1714 EVENT_PTR(REF_CPU_CYCLES), 1715 NULL, 1716 }; 1717 1718 static struct attribute_group x86_pmu_events_group = { 1719 .name = "events", 1720 .attrs = events_attr, 1721 }; 1722 1723 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) 1724 { 1725 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; 1726 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; 1727 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); 1728 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); 1729 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); 1730 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); 1731 ssize_t ret; 1732 1733 /* 1734 * We have whole page size to spend and just little data 1735 * to write, so we can safely use sprintf. 1736 */ 1737 ret = sprintf(page, "event=0x%02llx", event); 1738 1739 if (umask) 1740 ret += sprintf(page + ret, ",umask=0x%02llx", umask); 1741 1742 if (edge) 1743 ret += sprintf(page + ret, ",edge"); 1744 1745 if (pc) 1746 ret += sprintf(page + ret, ",pc"); 1747 1748 if (any) 1749 ret += sprintf(page + ret, ",any"); 1750 1751 if (inv) 1752 ret += sprintf(page + ret, ",inv"); 1753 1754 if (cmask) 1755 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); 1756 1757 ret += sprintf(page + ret, "\n"); 1758 1759 return ret; 1760 } 1761 1762 static struct attribute_group x86_pmu_attr_group; 1763 static struct attribute_group x86_pmu_caps_group; 1764 1765 static int __init init_hw_perf_events(void) 1766 { 1767 struct x86_pmu_quirk *quirk; 1768 int err; 1769 1770 pr_info("Performance Events: "); 1771 1772 switch (boot_cpu_data.x86_vendor) { 1773 case X86_VENDOR_INTEL: 1774 err = intel_pmu_init(); 1775 break; 1776 case X86_VENDOR_AMD: 1777 err = amd_pmu_init(); 1778 break; 1779 default: 1780 err = -ENOTSUPP; 1781 } 1782 if (err != 0) { 1783 pr_cont("no PMU driver, software events only.\n"); 1784 return 0; 1785 } 1786 1787 pmu_check_apic(); 1788 1789 /* sanity check that the hardware exists or is emulated */ 1790 if (!check_hw_exists()) 1791 return 0; 1792 1793 pr_cont("%s PMU driver.\n", x86_pmu.name); 1794 1795 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ 1796 1797 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) 1798 quirk->func(); 1799 1800 if (!x86_pmu.intel_ctrl) 1801 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; 1802 1803 perf_events_lapic_init(); 1804 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); 1805 1806 unconstrained = (struct event_constraint) 1807 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, 1808 0, x86_pmu.num_counters, 0, 0); 1809 1810 x86_pmu_format_group.attrs = x86_pmu.format_attrs; 1811 1812 if (x86_pmu.caps_attrs) { 1813 struct attribute **tmp; 1814 1815 tmp = merge_attr(x86_pmu_caps_group.attrs, x86_pmu.caps_attrs); 1816 if (!WARN_ON(!tmp)) 1817 x86_pmu_caps_group.attrs = tmp; 1818 } 1819 1820 if (x86_pmu.event_attrs) 1821 x86_pmu_events_group.attrs = x86_pmu.event_attrs; 1822 1823 if (!x86_pmu.events_sysfs_show) 1824 x86_pmu_events_group.attrs = &empty_attrs; 1825 else 1826 filter_events(x86_pmu_events_group.attrs); 1827 1828 if (x86_pmu.cpu_events) { 1829 struct attribute **tmp; 1830 1831 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); 1832 if (!WARN_ON(!tmp)) 1833 x86_pmu_events_group.attrs = tmp; 1834 } 1835 1836 if (x86_pmu.attrs) { 1837 struct attribute **tmp; 1838 1839 tmp = merge_attr(x86_pmu_attr_group.attrs, x86_pmu.attrs); 1840 if (!WARN_ON(!tmp)) 1841 x86_pmu_attr_group.attrs = tmp; 1842 } 1843 1844 pr_info("... version: %d\n", x86_pmu.version); 1845 pr_info("... bit width: %d\n", x86_pmu.cntval_bits); 1846 pr_info("... generic registers: %d\n", x86_pmu.num_counters); 1847 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); 1848 pr_info("... max period: %016Lx\n", x86_pmu.max_period); 1849 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); 1850 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); 1851 1852 /* 1853 * Install callbacks. Core will call them for each online 1854 * cpu. 1855 */ 1856 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", 1857 x86_pmu_prepare_cpu, x86_pmu_dead_cpu); 1858 if (err) 1859 return err; 1860 1861 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, 1862 "perf/x86:starting", x86_pmu_starting_cpu, 1863 x86_pmu_dying_cpu); 1864 if (err) 1865 goto out; 1866 1867 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online", 1868 x86_pmu_online_cpu, NULL); 1869 if (err) 1870 goto out1; 1871 1872 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1873 if (err) 1874 goto out2; 1875 1876 return 0; 1877 1878 out2: 1879 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); 1880 out1: 1881 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); 1882 out: 1883 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); 1884 return err; 1885 } 1886 early_initcall(init_hw_perf_events); 1887 1888 static inline void x86_pmu_read(struct perf_event *event) 1889 { 1890 if (x86_pmu.read) 1891 return x86_pmu.read(event); 1892 x86_perf_event_update(event); 1893 } 1894 1895 /* 1896 * Start group events scheduling transaction 1897 * Set the flag to make pmu::enable() not perform the 1898 * schedulability test, it will be performed at commit time 1899 * 1900 * We only support PERF_PMU_TXN_ADD transactions. Save the 1901 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1902 * transactions. 1903 */ 1904 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1905 { 1906 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1907 1908 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ 1909 1910 cpuc->txn_flags = txn_flags; 1911 if (txn_flags & ~PERF_PMU_TXN_ADD) 1912 return; 1913 1914 perf_pmu_disable(pmu); 1915 __this_cpu_write(cpu_hw_events.n_txn, 0); 1916 } 1917 1918 /* 1919 * Stop group events scheduling transaction 1920 * Clear the flag and pmu::enable() will perform the 1921 * schedulability test. 1922 */ 1923 static void x86_pmu_cancel_txn(struct pmu *pmu) 1924 { 1925 unsigned int txn_flags; 1926 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1927 1928 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1929 1930 txn_flags = cpuc->txn_flags; 1931 cpuc->txn_flags = 0; 1932 if (txn_flags & ~PERF_PMU_TXN_ADD) 1933 return; 1934 1935 /* 1936 * Truncate collected array by the number of events added in this 1937 * transaction. See x86_pmu_add() and x86_pmu_*_txn(). 1938 */ 1939 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); 1940 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); 1941 perf_pmu_enable(pmu); 1942 } 1943 1944 /* 1945 * Commit group events scheduling transaction 1946 * Perform the group schedulability test as a whole 1947 * Return 0 if success 1948 * 1949 * Does not cancel the transaction on failure; expects the caller to do this. 1950 */ 1951 static int x86_pmu_commit_txn(struct pmu *pmu) 1952 { 1953 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1954 int assign[X86_PMC_IDX_MAX]; 1955 int n, ret; 1956 1957 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1958 1959 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { 1960 cpuc->txn_flags = 0; 1961 return 0; 1962 } 1963 1964 n = cpuc->n_events; 1965 1966 if (!x86_pmu_initialized()) 1967 return -EAGAIN; 1968 1969 ret = x86_pmu.schedule_events(cpuc, n, assign); 1970 if (ret) 1971 return ret; 1972 1973 /* 1974 * copy new assignment, now we know it is possible 1975 * will be used by hw_perf_enable() 1976 */ 1977 memcpy(cpuc->assign, assign, n*sizeof(int)); 1978 1979 cpuc->txn_flags = 0; 1980 perf_pmu_enable(pmu); 1981 return 0; 1982 } 1983 /* 1984 * a fake_cpuc is used to validate event groups. Due to 1985 * the extra reg logic, we need to also allocate a fake 1986 * per_core and per_cpu structure. Otherwise, group events 1987 * using extra reg may conflict without the kernel being 1988 * able to catch this when the last event gets added to 1989 * the group. 1990 */ 1991 static void free_fake_cpuc(struct cpu_hw_events *cpuc) 1992 { 1993 kfree(cpuc->shared_regs); 1994 kfree(cpuc); 1995 } 1996 1997 static struct cpu_hw_events *allocate_fake_cpuc(void) 1998 { 1999 struct cpu_hw_events *cpuc; 2000 int cpu = raw_smp_processor_id(); 2001 2002 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); 2003 if (!cpuc) 2004 return ERR_PTR(-ENOMEM); 2005 2006 /* only needed, if we have extra_regs */ 2007 if (x86_pmu.extra_regs) { 2008 cpuc->shared_regs = allocate_shared_regs(cpu); 2009 if (!cpuc->shared_regs) 2010 goto error; 2011 } 2012 cpuc->is_fake = 1; 2013 return cpuc; 2014 error: 2015 free_fake_cpuc(cpuc); 2016 return ERR_PTR(-ENOMEM); 2017 } 2018 2019 /* 2020 * validate that we can schedule this event 2021 */ 2022 static int validate_event(struct perf_event *event) 2023 { 2024 struct cpu_hw_events *fake_cpuc; 2025 struct event_constraint *c; 2026 int ret = 0; 2027 2028 fake_cpuc = allocate_fake_cpuc(); 2029 if (IS_ERR(fake_cpuc)) 2030 return PTR_ERR(fake_cpuc); 2031 2032 c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); 2033 2034 if (!c || !c->weight) 2035 ret = -EINVAL; 2036 2037 if (x86_pmu.put_event_constraints) 2038 x86_pmu.put_event_constraints(fake_cpuc, event); 2039 2040 free_fake_cpuc(fake_cpuc); 2041 2042 return ret; 2043 } 2044 2045 /* 2046 * validate a single event group 2047 * 2048 * validation include: 2049 * - check events are compatible which each other 2050 * - events do not compete for the same counter 2051 * - number of events <= number of counters 2052 * 2053 * validation ensures the group can be loaded onto the 2054 * PMU if it was the only group available. 2055 */ 2056 static int validate_group(struct perf_event *event) 2057 { 2058 struct perf_event *leader = event->group_leader; 2059 struct cpu_hw_events *fake_cpuc; 2060 int ret = -EINVAL, n; 2061 2062 fake_cpuc = allocate_fake_cpuc(); 2063 if (IS_ERR(fake_cpuc)) 2064 return PTR_ERR(fake_cpuc); 2065 /* 2066 * the event is not yet connected with its 2067 * siblings therefore we must first collect 2068 * existing siblings, then add the new event 2069 * before we can simulate the scheduling 2070 */ 2071 n = collect_events(fake_cpuc, leader, true); 2072 if (n < 0) 2073 goto out; 2074 2075 fake_cpuc->n_events = n; 2076 n = collect_events(fake_cpuc, event, false); 2077 if (n < 0) 2078 goto out; 2079 2080 fake_cpuc->n_events = n; 2081 2082 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); 2083 2084 out: 2085 free_fake_cpuc(fake_cpuc); 2086 return ret; 2087 } 2088 2089 static int x86_pmu_event_init(struct perf_event *event) 2090 { 2091 struct pmu *tmp; 2092 int err; 2093 2094 switch (event->attr.type) { 2095 case PERF_TYPE_RAW: 2096 case PERF_TYPE_HARDWARE: 2097 case PERF_TYPE_HW_CACHE: 2098 break; 2099 2100 default: 2101 return -ENOENT; 2102 } 2103 2104 err = __x86_pmu_event_init(event); 2105 if (!err) { 2106 /* 2107 * we temporarily connect event to its pmu 2108 * such that validate_group() can classify 2109 * it as an x86 event using is_x86_event() 2110 */ 2111 tmp = event->pmu; 2112 event->pmu = &pmu; 2113 2114 if (event->group_leader != event) 2115 err = validate_group(event); 2116 else 2117 err = validate_event(event); 2118 2119 event->pmu = tmp; 2120 } 2121 if (err) { 2122 if (event->destroy) 2123 event->destroy(event); 2124 } 2125 2126 if (READ_ONCE(x86_pmu.attr_rdpmc) && 2127 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) 2128 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; 2129 2130 return err; 2131 } 2132 2133 static void refresh_pce(void *ignored) 2134 { 2135 load_mm_cr4(this_cpu_read(cpu_tlbstate.loaded_mm)); 2136 } 2137 2138 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) 2139 { 2140 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2141 return; 2142 2143 /* 2144 * This function relies on not being called concurrently in two 2145 * tasks in the same mm. Otherwise one task could observe 2146 * perf_rdpmc_allowed > 1 and return all the way back to 2147 * userspace with CR4.PCE clear while another task is still 2148 * doing on_each_cpu_mask() to propagate CR4.PCE. 2149 * 2150 * For now, this can't happen because all callers hold mmap_sem 2151 * for write. If this changes, we'll need a different solution. 2152 */ 2153 lockdep_assert_held_exclusive(&mm->mmap_sem); 2154 2155 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1) 2156 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1); 2157 } 2158 2159 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) 2160 { 2161 2162 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2163 return; 2164 2165 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed)) 2166 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1); 2167 } 2168 2169 static int x86_pmu_event_idx(struct perf_event *event) 2170 { 2171 int idx = event->hw.idx; 2172 2173 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2174 return 0; 2175 2176 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { 2177 idx -= INTEL_PMC_IDX_FIXED; 2178 idx |= 1 << 30; 2179 } 2180 2181 return idx + 1; 2182 } 2183 2184 static ssize_t get_attr_rdpmc(struct device *cdev, 2185 struct device_attribute *attr, 2186 char *buf) 2187 { 2188 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); 2189 } 2190 2191 static ssize_t set_attr_rdpmc(struct device *cdev, 2192 struct device_attribute *attr, 2193 const char *buf, size_t count) 2194 { 2195 unsigned long val; 2196 ssize_t ret; 2197 2198 ret = kstrtoul(buf, 0, &val); 2199 if (ret) 2200 return ret; 2201 2202 if (val > 2) 2203 return -EINVAL; 2204 2205 if (x86_pmu.attr_rdpmc_broken) 2206 return -ENOTSUPP; 2207 2208 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { 2209 /* 2210 * Changing into or out of always available, aka 2211 * perf-event-bypassing mode. This path is extremely slow, 2212 * but only root can trigger it, so it's okay. 2213 */ 2214 if (val == 2) 2215 static_branch_inc(&rdpmc_always_available_key); 2216 else 2217 static_branch_dec(&rdpmc_always_available_key); 2218 on_each_cpu(refresh_pce, NULL, 1); 2219 } 2220 2221 x86_pmu.attr_rdpmc = val; 2222 2223 return count; 2224 } 2225 2226 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); 2227 2228 static struct attribute *x86_pmu_attrs[] = { 2229 &dev_attr_rdpmc.attr, 2230 NULL, 2231 }; 2232 2233 static struct attribute_group x86_pmu_attr_group = { 2234 .attrs = x86_pmu_attrs, 2235 }; 2236 2237 static ssize_t max_precise_show(struct device *cdev, 2238 struct device_attribute *attr, 2239 char *buf) 2240 { 2241 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise()); 2242 } 2243 2244 static DEVICE_ATTR_RO(max_precise); 2245 2246 static struct attribute *x86_pmu_caps_attrs[] = { 2247 &dev_attr_max_precise.attr, 2248 NULL 2249 }; 2250 2251 static struct attribute_group x86_pmu_caps_group = { 2252 .name = "caps", 2253 .attrs = x86_pmu_caps_attrs, 2254 }; 2255 2256 static const struct attribute_group *x86_pmu_attr_groups[] = { 2257 &x86_pmu_attr_group, 2258 &x86_pmu_format_group, 2259 &x86_pmu_events_group, 2260 &x86_pmu_caps_group, 2261 NULL, 2262 }; 2263 2264 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 2265 { 2266 if (x86_pmu.sched_task) 2267 x86_pmu.sched_task(ctx, sched_in); 2268 } 2269 2270 void perf_check_microcode(void) 2271 { 2272 if (x86_pmu.check_microcode) 2273 x86_pmu.check_microcode(); 2274 } 2275 2276 static struct pmu pmu = { 2277 .pmu_enable = x86_pmu_enable, 2278 .pmu_disable = x86_pmu_disable, 2279 2280 .attr_groups = x86_pmu_attr_groups, 2281 2282 .event_init = x86_pmu_event_init, 2283 2284 .event_mapped = x86_pmu_event_mapped, 2285 .event_unmapped = x86_pmu_event_unmapped, 2286 2287 .add = x86_pmu_add, 2288 .del = x86_pmu_del, 2289 .start = x86_pmu_start, 2290 .stop = x86_pmu_stop, 2291 .read = x86_pmu_read, 2292 2293 .start_txn = x86_pmu_start_txn, 2294 .cancel_txn = x86_pmu_cancel_txn, 2295 .commit_txn = x86_pmu_commit_txn, 2296 2297 .event_idx = x86_pmu_event_idx, 2298 .sched_task = x86_pmu_sched_task, 2299 .task_ctx_size = sizeof(struct x86_perf_task_context), 2300 }; 2301 2302 void arch_perf_update_userpage(struct perf_event *event, 2303 struct perf_event_mmap_page *userpg, u64 now) 2304 { 2305 struct cyc2ns_data data; 2306 u64 offset; 2307 2308 userpg->cap_user_time = 0; 2309 userpg->cap_user_time_zero = 0; 2310 userpg->cap_user_rdpmc = 2311 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); 2312 userpg->pmc_width = x86_pmu.cntval_bits; 2313 2314 if (!using_native_sched_clock() || !sched_clock_stable()) 2315 return; 2316 2317 cyc2ns_read_begin(&data); 2318 2319 offset = data.cyc2ns_offset + __sched_clock_offset; 2320 2321 /* 2322 * Internal timekeeping for enabled/running/stopped times 2323 * is always in the local_clock domain. 2324 */ 2325 userpg->cap_user_time = 1; 2326 userpg->time_mult = data.cyc2ns_mul; 2327 userpg->time_shift = data.cyc2ns_shift; 2328 userpg->time_offset = offset - now; 2329 2330 /* 2331 * cap_user_time_zero doesn't make sense when we're using a different 2332 * time base for the records. 2333 */ 2334 if (!event->attr.use_clockid) { 2335 userpg->cap_user_time_zero = 1; 2336 userpg->time_zero = offset; 2337 } 2338 2339 cyc2ns_read_end(); 2340 } 2341 2342 void 2343 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2344 { 2345 struct unwind_state state; 2346 unsigned long addr; 2347 2348 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2349 /* TODO: We don't support guest os callchain now */ 2350 return; 2351 } 2352 2353 if (perf_callchain_store(entry, regs->ip)) 2354 return; 2355 2356 for (unwind_start(&state, current, regs, NULL); !unwind_done(&state); 2357 unwind_next_frame(&state)) { 2358 addr = unwind_get_return_address(&state); 2359 if (!addr || perf_callchain_store(entry, addr)) 2360 return; 2361 } 2362 } 2363 2364 static inline int 2365 valid_user_frame(const void __user *fp, unsigned long size) 2366 { 2367 return (__range_not_ok(fp, size, TASK_SIZE) == 0); 2368 } 2369 2370 static unsigned long get_segment_base(unsigned int segment) 2371 { 2372 struct desc_struct *desc; 2373 unsigned int idx = segment >> 3; 2374 2375 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { 2376 #ifdef CONFIG_MODIFY_LDT_SYSCALL 2377 struct ldt_struct *ldt; 2378 2379 /* IRQs are off, so this synchronizes with smp_store_release */ 2380 ldt = READ_ONCE(current->active_mm->context.ldt); 2381 if (!ldt || idx >= ldt->nr_entries) 2382 return 0; 2383 2384 desc = &ldt->entries[idx]; 2385 #else 2386 return 0; 2387 #endif 2388 } else { 2389 if (idx >= GDT_ENTRIES) 2390 return 0; 2391 2392 desc = raw_cpu_ptr(gdt_page.gdt) + idx; 2393 } 2394 2395 return get_desc_base(desc); 2396 } 2397 2398 #ifdef CONFIG_IA32_EMULATION 2399 2400 #include <linux/compat.h> 2401 2402 static inline int 2403 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) 2404 { 2405 /* 32-bit process in 64-bit kernel. */ 2406 unsigned long ss_base, cs_base; 2407 struct stack_frame_ia32 frame; 2408 const void __user *fp; 2409 2410 if (!test_thread_flag(TIF_IA32)) 2411 return 0; 2412 2413 cs_base = get_segment_base(regs->cs); 2414 ss_base = get_segment_base(regs->ss); 2415 2416 fp = compat_ptr(ss_base + regs->bp); 2417 pagefault_disable(); 2418 while (entry->nr < entry->max_stack) { 2419 unsigned long bytes; 2420 frame.next_frame = 0; 2421 frame.return_address = 0; 2422 2423 if (!valid_user_frame(fp, sizeof(frame))) 2424 break; 2425 2426 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); 2427 if (bytes != 0) 2428 break; 2429 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); 2430 if (bytes != 0) 2431 break; 2432 2433 perf_callchain_store(entry, cs_base + frame.return_address); 2434 fp = compat_ptr(ss_base + frame.next_frame); 2435 } 2436 pagefault_enable(); 2437 return 1; 2438 } 2439 #else 2440 static inline int 2441 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) 2442 { 2443 return 0; 2444 } 2445 #endif 2446 2447 void 2448 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2449 { 2450 struct stack_frame frame; 2451 const unsigned long __user *fp; 2452 2453 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2454 /* TODO: We don't support guest os callchain now */ 2455 return; 2456 } 2457 2458 /* 2459 * We don't know what to do with VM86 stacks.. ignore them for now. 2460 */ 2461 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) 2462 return; 2463 2464 fp = (unsigned long __user *)regs->bp; 2465 2466 perf_callchain_store(entry, regs->ip); 2467 2468 if (!current->mm) 2469 return; 2470 2471 if (perf_callchain_user32(regs, entry)) 2472 return; 2473 2474 pagefault_disable(); 2475 while (entry->nr < entry->max_stack) { 2476 unsigned long bytes; 2477 2478 frame.next_frame = NULL; 2479 frame.return_address = 0; 2480 2481 if (!valid_user_frame(fp, sizeof(frame))) 2482 break; 2483 2484 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp)); 2485 if (bytes != 0) 2486 break; 2487 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp)); 2488 if (bytes != 0) 2489 break; 2490 2491 perf_callchain_store(entry, frame.return_address); 2492 fp = (void __user *)frame.next_frame; 2493 } 2494 pagefault_enable(); 2495 } 2496 2497 /* 2498 * Deal with code segment offsets for the various execution modes: 2499 * 2500 * VM86 - the good olde 16 bit days, where the linear address is 2501 * 20 bits and we use regs->ip + 0x10 * regs->cs. 2502 * 2503 * IA32 - Where we need to look at GDT/LDT segment descriptor tables 2504 * to figure out what the 32bit base address is. 2505 * 2506 * X32 - has TIF_X32 set, but is running in x86_64 2507 * 2508 * X86_64 - CS,DS,SS,ES are all zero based. 2509 */ 2510 static unsigned long code_segment_base(struct pt_regs *regs) 2511 { 2512 /* 2513 * For IA32 we look at the GDT/LDT segment base to convert the 2514 * effective IP to a linear address. 2515 */ 2516 2517 #ifdef CONFIG_X86_32 2518 /* 2519 * If we are in VM86 mode, add the segment offset to convert to a 2520 * linear address. 2521 */ 2522 if (regs->flags & X86_VM_MASK) 2523 return 0x10 * regs->cs; 2524 2525 if (user_mode(regs) && regs->cs != __USER_CS) 2526 return get_segment_base(regs->cs); 2527 #else 2528 if (user_mode(regs) && !user_64bit_mode(regs) && 2529 regs->cs != __USER32_CS) 2530 return get_segment_base(regs->cs); 2531 #endif 2532 return 0; 2533 } 2534 2535 unsigned long perf_instruction_pointer(struct pt_regs *regs) 2536 { 2537 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) 2538 return perf_guest_cbs->get_guest_ip(); 2539 2540 return regs->ip + code_segment_base(regs); 2541 } 2542 2543 unsigned long perf_misc_flags(struct pt_regs *regs) 2544 { 2545 int misc = 0; 2546 2547 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2548 if (perf_guest_cbs->is_user_mode()) 2549 misc |= PERF_RECORD_MISC_GUEST_USER; 2550 else 2551 misc |= PERF_RECORD_MISC_GUEST_KERNEL; 2552 } else { 2553 if (user_mode(regs)) 2554 misc |= PERF_RECORD_MISC_USER; 2555 else 2556 misc |= PERF_RECORD_MISC_KERNEL; 2557 } 2558 2559 if (regs->flags & PERF_EFLAGS_EXACT) 2560 misc |= PERF_RECORD_MISC_EXACT_IP; 2561 2562 return misc; 2563 } 2564 2565 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) 2566 { 2567 cap->version = x86_pmu.version; 2568 cap->num_counters_gp = x86_pmu.num_counters; 2569 cap->num_counters_fixed = x86_pmu.num_counters_fixed; 2570 cap->bit_width_gp = x86_pmu.cntval_bits; 2571 cap->bit_width_fixed = x86_pmu.cntval_bits; 2572 cap->events_mask = (unsigned int)x86_pmu.events_maskl; 2573 cap->events_mask_len = x86_pmu.events_mask_len; 2574 } 2575 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); 2576