1 /* 2 * Performance events x86 architecture code 3 * 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 #include <linux/capability.h> 17 #include <linux/notifier.h> 18 #include <linux/hardirq.h> 19 #include <linux/kprobes.h> 20 #include <linux/export.h> 21 #include <linux/init.h> 22 #include <linux/kdebug.h> 23 #include <linux/sched/mm.h> 24 #include <linux/sched/clock.h> 25 #include <linux/uaccess.h> 26 #include <linux/slab.h> 27 #include <linux/cpu.h> 28 #include <linux/bitops.h> 29 #include <linux/device.h> 30 #include <linux/nospec.h> 31 32 #include <asm/apic.h> 33 #include <asm/stacktrace.h> 34 #include <asm/nmi.h> 35 #include <asm/smp.h> 36 #include <asm/alternative.h> 37 #include <asm/mmu_context.h> 38 #include <asm/tlbflush.h> 39 #include <asm/timer.h> 40 #include <asm/desc.h> 41 #include <asm/ldt.h> 42 #include <asm/unwind.h> 43 44 #include "perf_event.h" 45 46 struct x86_pmu x86_pmu __read_mostly; 47 48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { 49 .enabled = 1, 50 }; 51 52 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key); 53 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key); 54 55 u64 __read_mostly hw_cache_event_ids 56 [PERF_COUNT_HW_CACHE_MAX] 57 [PERF_COUNT_HW_CACHE_OP_MAX] 58 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 59 u64 __read_mostly hw_cache_extra_regs 60 [PERF_COUNT_HW_CACHE_MAX] 61 [PERF_COUNT_HW_CACHE_OP_MAX] 62 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 63 64 /* 65 * Propagate event elapsed time into the generic event. 66 * Can only be executed on the CPU where the event is active. 67 * Returns the delta events processed. 68 */ 69 u64 x86_perf_event_update(struct perf_event *event) 70 { 71 struct hw_perf_event *hwc = &event->hw; 72 int shift = 64 - x86_pmu.cntval_bits; 73 u64 prev_raw_count, new_raw_count; 74 int idx = hwc->idx; 75 u64 delta; 76 77 if (idx == INTEL_PMC_IDX_FIXED_BTS) 78 return 0; 79 80 /* 81 * Careful: an NMI might modify the previous event value. 82 * 83 * Our tactic to handle this is to first atomically read and 84 * exchange a new raw count - then add that new-prev delta 85 * count to the generic event atomically: 86 */ 87 again: 88 prev_raw_count = local64_read(&hwc->prev_count); 89 rdpmcl(hwc->event_base_rdpmc, new_raw_count); 90 91 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 92 new_raw_count) != prev_raw_count) 93 goto again; 94 95 /* 96 * Now we have the new raw value and have updated the prev 97 * timestamp already. We can now calculate the elapsed delta 98 * (event-)time and add that to the generic event. 99 * 100 * Careful, not all hw sign-extends above the physical width 101 * of the count. 102 */ 103 delta = (new_raw_count << shift) - (prev_raw_count << shift); 104 delta >>= shift; 105 106 local64_add(delta, &event->count); 107 local64_sub(delta, &hwc->period_left); 108 109 return new_raw_count; 110 } 111 112 /* 113 * Find and validate any extra registers to set up. 114 */ 115 static int x86_pmu_extra_regs(u64 config, struct perf_event *event) 116 { 117 struct hw_perf_event_extra *reg; 118 struct extra_reg *er; 119 120 reg = &event->hw.extra_reg; 121 122 if (!x86_pmu.extra_regs) 123 return 0; 124 125 for (er = x86_pmu.extra_regs; er->msr; er++) { 126 if (er->event != (config & er->config_mask)) 127 continue; 128 if (event->attr.config1 & ~er->valid_mask) 129 return -EINVAL; 130 /* Check if the extra msrs can be safely accessed*/ 131 if (!er->extra_msr_access) 132 return -ENXIO; 133 134 reg->idx = er->idx; 135 reg->config = event->attr.config1; 136 reg->reg = er->msr; 137 break; 138 } 139 return 0; 140 } 141 142 static atomic_t active_events; 143 static atomic_t pmc_refcount; 144 static DEFINE_MUTEX(pmc_reserve_mutex); 145 146 #ifdef CONFIG_X86_LOCAL_APIC 147 148 static bool reserve_pmc_hardware(void) 149 { 150 int i; 151 152 for (i = 0; i < x86_pmu.num_counters; i++) { 153 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) 154 goto perfctr_fail; 155 } 156 157 for (i = 0; i < x86_pmu.num_counters; i++) { 158 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) 159 goto eventsel_fail; 160 } 161 162 return true; 163 164 eventsel_fail: 165 for (i--; i >= 0; i--) 166 release_evntsel_nmi(x86_pmu_config_addr(i)); 167 168 i = x86_pmu.num_counters; 169 170 perfctr_fail: 171 for (i--; i >= 0; i--) 172 release_perfctr_nmi(x86_pmu_event_addr(i)); 173 174 return false; 175 } 176 177 static void release_pmc_hardware(void) 178 { 179 int i; 180 181 for (i = 0; i < x86_pmu.num_counters; i++) { 182 release_perfctr_nmi(x86_pmu_event_addr(i)); 183 release_evntsel_nmi(x86_pmu_config_addr(i)); 184 } 185 } 186 187 #else 188 189 static bool reserve_pmc_hardware(void) { return true; } 190 static void release_pmc_hardware(void) {} 191 192 #endif 193 194 static bool check_hw_exists(void) 195 { 196 u64 val, val_fail = -1, val_new= ~0; 197 int i, reg, reg_fail = -1, ret = 0; 198 int bios_fail = 0; 199 int reg_safe = -1; 200 201 /* 202 * Check to see if the BIOS enabled any of the counters, if so 203 * complain and bail. 204 */ 205 for (i = 0; i < x86_pmu.num_counters; i++) { 206 reg = x86_pmu_config_addr(i); 207 ret = rdmsrl_safe(reg, &val); 208 if (ret) 209 goto msr_fail; 210 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { 211 bios_fail = 1; 212 val_fail = val; 213 reg_fail = reg; 214 } else { 215 reg_safe = i; 216 } 217 } 218 219 if (x86_pmu.num_counters_fixed) { 220 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 221 ret = rdmsrl_safe(reg, &val); 222 if (ret) 223 goto msr_fail; 224 for (i = 0; i < x86_pmu.num_counters_fixed; i++) { 225 if (val & (0x03 << i*4)) { 226 bios_fail = 1; 227 val_fail = val; 228 reg_fail = reg; 229 } 230 } 231 } 232 233 /* 234 * If all the counters are enabled, the below test will always 235 * fail. The tools will also become useless in this scenario. 236 * Just fail and disable the hardware counters. 237 */ 238 239 if (reg_safe == -1) { 240 reg = reg_safe; 241 goto msr_fail; 242 } 243 244 /* 245 * Read the current value, change it and read it back to see if it 246 * matches, this is needed to detect certain hardware emulators 247 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 248 */ 249 reg = x86_pmu_event_addr(reg_safe); 250 if (rdmsrl_safe(reg, &val)) 251 goto msr_fail; 252 val ^= 0xffffUL; 253 ret = wrmsrl_safe(reg, val); 254 ret |= rdmsrl_safe(reg, &val_new); 255 if (ret || val != val_new) 256 goto msr_fail; 257 258 /* 259 * We still allow the PMU driver to operate: 260 */ 261 if (bios_fail) { 262 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); 263 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", 264 reg_fail, val_fail); 265 } 266 267 return true; 268 269 msr_fail: 270 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { 271 pr_cont("PMU not available due to virtualization, using software events only.\n"); 272 } else { 273 pr_cont("Broken PMU hardware detected, using software events only.\n"); 274 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n", 275 reg, val_new); 276 } 277 278 return false; 279 } 280 281 static void hw_perf_event_destroy(struct perf_event *event) 282 { 283 x86_release_hardware(); 284 atomic_dec(&active_events); 285 } 286 287 void hw_perf_lbr_event_destroy(struct perf_event *event) 288 { 289 hw_perf_event_destroy(event); 290 291 /* undo the lbr/bts event accounting */ 292 x86_del_exclusive(x86_lbr_exclusive_lbr); 293 } 294 295 static inline int x86_pmu_initialized(void) 296 { 297 return x86_pmu.handle_irq != NULL; 298 } 299 300 static inline int 301 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) 302 { 303 struct perf_event_attr *attr = &event->attr; 304 unsigned int cache_type, cache_op, cache_result; 305 u64 config, val; 306 307 config = attr->config; 308 309 cache_type = (config >> 0) & 0xff; 310 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 311 return -EINVAL; 312 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX); 313 314 cache_op = (config >> 8) & 0xff; 315 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 316 return -EINVAL; 317 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX); 318 319 cache_result = (config >> 16) & 0xff; 320 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 321 return -EINVAL; 322 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX); 323 324 val = hw_cache_event_ids[cache_type][cache_op][cache_result]; 325 326 if (val == 0) 327 return -ENOENT; 328 329 if (val == -1) 330 return -EINVAL; 331 332 hwc->config |= val; 333 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; 334 return x86_pmu_extra_regs(val, event); 335 } 336 337 int x86_reserve_hardware(void) 338 { 339 int err = 0; 340 341 if (!atomic_inc_not_zero(&pmc_refcount)) { 342 mutex_lock(&pmc_reserve_mutex); 343 if (atomic_read(&pmc_refcount) == 0) { 344 if (!reserve_pmc_hardware()) 345 err = -EBUSY; 346 else 347 reserve_ds_buffers(); 348 } 349 if (!err) 350 atomic_inc(&pmc_refcount); 351 mutex_unlock(&pmc_reserve_mutex); 352 } 353 354 return err; 355 } 356 357 void x86_release_hardware(void) 358 { 359 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { 360 release_pmc_hardware(); 361 release_ds_buffers(); 362 mutex_unlock(&pmc_reserve_mutex); 363 } 364 } 365 366 /* 367 * Check if we can create event of a certain type (that no conflicting events 368 * are present). 369 */ 370 int x86_add_exclusive(unsigned int what) 371 { 372 int i; 373 374 /* 375 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. 376 * LBR and BTS are still mutually exclusive. 377 */ 378 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) 379 goto out; 380 381 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { 382 mutex_lock(&pmc_reserve_mutex); 383 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { 384 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) 385 goto fail_unlock; 386 } 387 atomic_inc(&x86_pmu.lbr_exclusive[what]); 388 mutex_unlock(&pmc_reserve_mutex); 389 } 390 391 out: 392 atomic_inc(&active_events); 393 return 0; 394 395 fail_unlock: 396 mutex_unlock(&pmc_reserve_mutex); 397 return -EBUSY; 398 } 399 400 void x86_del_exclusive(unsigned int what) 401 { 402 atomic_dec(&active_events); 403 404 /* 405 * See the comment in x86_add_exclusive(). 406 */ 407 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) 408 return; 409 410 atomic_dec(&x86_pmu.lbr_exclusive[what]); 411 } 412 413 int x86_setup_perfctr(struct perf_event *event) 414 { 415 struct perf_event_attr *attr = &event->attr; 416 struct hw_perf_event *hwc = &event->hw; 417 u64 config; 418 419 if (!is_sampling_event(event)) { 420 hwc->sample_period = x86_pmu.max_period; 421 hwc->last_period = hwc->sample_period; 422 local64_set(&hwc->period_left, hwc->sample_period); 423 } 424 425 if (attr->type == PERF_TYPE_RAW) 426 return x86_pmu_extra_regs(event->attr.config, event); 427 428 if (attr->type == PERF_TYPE_HW_CACHE) 429 return set_ext_hw_attr(hwc, event); 430 431 if (attr->config >= x86_pmu.max_events) 432 return -EINVAL; 433 434 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events); 435 436 /* 437 * The generic map: 438 */ 439 config = x86_pmu.event_map(attr->config); 440 441 if (config == 0) 442 return -ENOENT; 443 444 if (config == -1LL) 445 return -EINVAL; 446 447 hwc->config |= config; 448 449 return 0; 450 } 451 452 /* 453 * check that branch_sample_type is compatible with 454 * settings needed for precise_ip > 1 which implies 455 * using the LBR to capture ALL taken branches at the 456 * priv levels of the measurement 457 */ 458 static inline int precise_br_compat(struct perf_event *event) 459 { 460 u64 m = event->attr.branch_sample_type; 461 u64 b = 0; 462 463 /* must capture all branches */ 464 if (!(m & PERF_SAMPLE_BRANCH_ANY)) 465 return 0; 466 467 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; 468 469 if (!event->attr.exclude_user) 470 b |= PERF_SAMPLE_BRANCH_USER; 471 472 if (!event->attr.exclude_kernel) 473 b |= PERF_SAMPLE_BRANCH_KERNEL; 474 475 /* 476 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 477 */ 478 479 return m == b; 480 } 481 482 int x86_pmu_max_precise(void) 483 { 484 int precise = 0; 485 486 /* Support for constant skid */ 487 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { 488 precise++; 489 490 /* Support for IP fixup */ 491 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) 492 precise++; 493 494 if (x86_pmu.pebs_prec_dist) 495 precise++; 496 } 497 return precise; 498 } 499 500 int x86_pmu_hw_config(struct perf_event *event) 501 { 502 if (event->attr.precise_ip) { 503 int precise = x86_pmu_max_precise(); 504 505 if (event->attr.precise_ip > precise) 506 return -EOPNOTSUPP; 507 508 /* There's no sense in having PEBS for non sampling events: */ 509 if (!is_sampling_event(event)) 510 return -EINVAL; 511 } 512 /* 513 * check that PEBS LBR correction does not conflict with 514 * whatever the user is asking with attr->branch_sample_type 515 */ 516 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { 517 u64 *br_type = &event->attr.branch_sample_type; 518 519 if (has_branch_stack(event)) { 520 if (!precise_br_compat(event)) 521 return -EOPNOTSUPP; 522 523 /* branch_sample_type is compatible */ 524 525 } else { 526 /* 527 * user did not specify branch_sample_type 528 * 529 * For PEBS fixups, we capture all 530 * the branches at the priv level of the 531 * event. 532 */ 533 *br_type = PERF_SAMPLE_BRANCH_ANY; 534 535 if (!event->attr.exclude_user) 536 *br_type |= PERF_SAMPLE_BRANCH_USER; 537 538 if (!event->attr.exclude_kernel) 539 *br_type |= PERF_SAMPLE_BRANCH_KERNEL; 540 } 541 } 542 543 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) 544 event->attach_state |= PERF_ATTACH_TASK_DATA; 545 546 /* 547 * Generate PMC IRQs: 548 * (keep 'enabled' bit clear for now) 549 */ 550 event->hw.config = ARCH_PERFMON_EVENTSEL_INT; 551 552 /* 553 * Count user and OS events unless requested not to 554 */ 555 if (!event->attr.exclude_user) 556 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; 557 if (!event->attr.exclude_kernel) 558 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; 559 560 if (event->attr.type == PERF_TYPE_RAW) 561 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; 562 563 if (event->attr.sample_period && x86_pmu.limit_period) { 564 if (x86_pmu.limit_period(event, event->attr.sample_period) > 565 event->attr.sample_period) 566 return -EINVAL; 567 } 568 569 /* sample_regs_user never support XMM registers */ 570 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK)) 571 return -EINVAL; 572 /* 573 * Besides the general purpose registers, XMM registers may 574 * be collected in PEBS on some platforms, e.g. Icelake 575 */ 576 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) { 577 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS)) 578 return -EINVAL; 579 580 if (!event->attr.precise_ip) 581 return -EINVAL; 582 } 583 584 return x86_setup_perfctr(event); 585 } 586 587 /* 588 * Setup the hardware configuration for a given attr_type 589 */ 590 static int __x86_pmu_event_init(struct perf_event *event) 591 { 592 int err; 593 594 if (!x86_pmu_initialized()) 595 return -ENODEV; 596 597 err = x86_reserve_hardware(); 598 if (err) 599 return err; 600 601 atomic_inc(&active_events); 602 event->destroy = hw_perf_event_destroy; 603 604 event->hw.idx = -1; 605 event->hw.last_cpu = -1; 606 event->hw.last_tag = ~0ULL; 607 608 /* mark unused */ 609 event->hw.extra_reg.idx = EXTRA_REG_NONE; 610 event->hw.branch_reg.idx = EXTRA_REG_NONE; 611 612 return x86_pmu.hw_config(event); 613 } 614 615 void x86_pmu_disable_all(void) 616 { 617 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 618 int idx; 619 620 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 621 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 622 u64 val; 623 624 if (!test_bit(idx, cpuc->active_mask)) 625 continue; 626 rdmsrl(x86_pmu_config_addr(idx), val); 627 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) 628 continue; 629 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 630 wrmsrl(x86_pmu_config_addr(idx), val); 631 if (is_counter_pair(hwc)) 632 wrmsrl(x86_pmu_config_addr(idx + 1), 0); 633 } 634 } 635 636 /* 637 * There may be PMI landing after enabled=0. The PMI hitting could be before or 638 * after disable_all. 639 * 640 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. 641 * It will not be re-enabled in the NMI handler again, because enabled=0. After 642 * handling the NMI, disable_all will be called, which will not change the 643 * state either. If PMI hits after disable_all, the PMU is already disabled 644 * before entering NMI handler. The NMI handler will not change the state 645 * either. 646 * 647 * So either situation is harmless. 648 */ 649 static void x86_pmu_disable(struct pmu *pmu) 650 { 651 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 652 653 if (!x86_pmu_initialized()) 654 return; 655 656 if (!cpuc->enabled) 657 return; 658 659 cpuc->n_added = 0; 660 cpuc->enabled = 0; 661 barrier(); 662 663 x86_pmu.disable_all(); 664 } 665 666 void x86_pmu_enable_all(int added) 667 { 668 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 669 int idx; 670 671 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 672 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 673 674 if (!test_bit(idx, cpuc->active_mask)) 675 continue; 676 677 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 678 } 679 } 680 681 static struct pmu pmu; 682 683 static inline int is_x86_event(struct perf_event *event) 684 { 685 return event->pmu == &pmu; 686 } 687 688 struct pmu *x86_get_pmu(void) 689 { 690 return &pmu; 691 } 692 /* 693 * Event scheduler state: 694 * 695 * Assign events iterating over all events and counters, beginning 696 * with events with least weights first. Keep the current iterator 697 * state in struct sched_state. 698 */ 699 struct sched_state { 700 int weight; 701 int event; /* event index */ 702 int counter; /* counter index */ 703 int unassigned; /* number of events to be assigned left */ 704 int nr_gp; /* number of GP counters used */ 705 u64 used; 706 }; 707 708 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ 709 #define SCHED_STATES_MAX 2 710 711 struct perf_sched { 712 int max_weight; 713 int max_events; 714 int max_gp; 715 int saved_states; 716 struct event_constraint **constraints; 717 struct sched_state state; 718 struct sched_state saved[SCHED_STATES_MAX]; 719 }; 720 721 /* 722 * Initialize interator that runs through all events and counters. 723 */ 724 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, 725 int num, int wmin, int wmax, int gpmax) 726 { 727 int idx; 728 729 memset(sched, 0, sizeof(*sched)); 730 sched->max_events = num; 731 sched->max_weight = wmax; 732 sched->max_gp = gpmax; 733 sched->constraints = constraints; 734 735 for (idx = 0; idx < num; idx++) { 736 if (constraints[idx]->weight == wmin) 737 break; 738 } 739 740 sched->state.event = idx; /* start with min weight */ 741 sched->state.weight = wmin; 742 sched->state.unassigned = num; 743 } 744 745 static void perf_sched_save_state(struct perf_sched *sched) 746 { 747 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) 748 return; 749 750 sched->saved[sched->saved_states] = sched->state; 751 sched->saved_states++; 752 } 753 754 static bool perf_sched_restore_state(struct perf_sched *sched) 755 { 756 if (!sched->saved_states) 757 return false; 758 759 sched->saved_states--; 760 sched->state = sched->saved[sched->saved_states]; 761 762 /* this assignment didn't work out */ 763 /* XXX broken vs EVENT_PAIR */ 764 sched->state.used &= ~BIT_ULL(sched->state.counter); 765 766 /* try the next one */ 767 sched->state.counter++; 768 769 return true; 770 } 771 772 /* 773 * Select a counter for the current event to schedule. Return true on 774 * success. 775 */ 776 static bool __perf_sched_find_counter(struct perf_sched *sched) 777 { 778 struct event_constraint *c; 779 int idx; 780 781 if (!sched->state.unassigned) 782 return false; 783 784 if (sched->state.event >= sched->max_events) 785 return false; 786 787 c = sched->constraints[sched->state.event]; 788 /* Prefer fixed purpose counters */ 789 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { 790 idx = INTEL_PMC_IDX_FIXED; 791 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { 792 u64 mask = BIT_ULL(idx); 793 794 if (sched->state.used & mask) 795 continue; 796 797 sched->state.used |= mask; 798 goto done; 799 } 800 } 801 802 /* Grab the first unused counter starting with idx */ 803 idx = sched->state.counter; 804 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { 805 u64 mask = BIT_ULL(idx); 806 807 if (c->flags & PERF_X86_EVENT_PAIR) 808 mask |= mask << 1; 809 810 if (sched->state.used & mask) 811 continue; 812 813 if (sched->state.nr_gp++ >= sched->max_gp) 814 return false; 815 816 sched->state.used |= mask; 817 goto done; 818 } 819 820 return false; 821 822 done: 823 sched->state.counter = idx; 824 825 if (c->overlap) 826 perf_sched_save_state(sched); 827 828 return true; 829 } 830 831 static bool perf_sched_find_counter(struct perf_sched *sched) 832 { 833 while (!__perf_sched_find_counter(sched)) { 834 if (!perf_sched_restore_state(sched)) 835 return false; 836 } 837 838 return true; 839 } 840 841 /* 842 * Go through all unassigned events and find the next one to schedule. 843 * Take events with the least weight first. Return true on success. 844 */ 845 static bool perf_sched_next_event(struct perf_sched *sched) 846 { 847 struct event_constraint *c; 848 849 if (!sched->state.unassigned || !--sched->state.unassigned) 850 return false; 851 852 do { 853 /* next event */ 854 sched->state.event++; 855 if (sched->state.event >= sched->max_events) { 856 /* next weight */ 857 sched->state.event = 0; 858 sched->state.weight++; 859 if (sched->state.weight > sched->max_weight) 860 return false; 861 } 862 c = sched->constraints[sched->state.event]; 863 } while (c->weight != sched->state.weight); 864 865 sched->state.counter = 0; /* start with first counter */ 866 867 return true; 868 } 869 870 /* 871 * Assign a counter for each event. 872 */ 873 int perf_assign_events(struct event_constraint **constraints, int n, 874 int wmin, int wmax, int gpmax, int *assign) 875 { 876 struct perf_sched sched; 877 878 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); 879 880 do { 881 if (!perf_sched_find_counter(&sched)) 882 break; /* failed */ 883 if (assign) 884 assign[sched.state.event] = sched.state.counter; 885 } while (perf_sched_next_event(&sched)); 886 887 return sched.state.unassigned; 888 } 889 EXPORT_SYMBOL_GPL(perf_assign_events); 890 891 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) 892 { 893 struct event_constraint *c; 894 struct perf_event *e; 895 int n0, i, wmin, wmax, unsched = 0; 896 struct hw_perf_event *hwc; 897 u64 used_mask = 0; 898 899 /* 900 * Compute the number of events already present; see x86_pmu_add(), 901 * validate_group() and x86_pmu_commit_txn(). For the former two 902 * cpuc->n_events hasn't been updated yet, while for the latter 903 * cpuc->n_txn contains the number of events added in the current 904 * transaction. 905 */ 906 n0 = cpuc->n_events; 907 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 908 n0 -= cpuc->n_txn; 909 910 if (x86_pmu.start_scheduling) 911 x86_pmu.start_scheduling(cpuc); 912 913 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { 914 c = cpuc->event_constraint[i]; 915 916 /* 917 * Previously scheduled events should have a cached constraint, 918 * while new events should not have one. 919 */ 920 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0)); 921 922 /* 923 * Request constraints for new events; or for those events that 924 * have a dynamic constraint -- for those the constraint can 925 * change due to external factors (sibling state, allow_tfa). 926 */ 927 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) { 928 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); 929 cpuc->event_constraint[i] = c; 930 } 931 932 wmin = min(wmin, c->weight); 933 wmax = max(wmax, c->weight); 934 } 935 936 /* 937 * fastpath, try to reuse previous register 938 */ 939 for (i = 0; i < n; i++) { 940 u64 mask; 941 942 hwc = &cpuc->event_list[i]->hw; 943 c = cpuc->event_constraint[i]; 944 945 /* never assigned */ 946 if (hwc->idx == -1) 947 break; 948 949 /* constraint still honored */ 950 if (!test_bit(hwc->idx, c->idxmsk)) 951 break; 952 953 mask = BIT_ULL(hwc->idx); 954 if (is_counter_pair(hwc)) 955 mask |= mask << 1; 956 957 /* not already used */ 958 if (used_mask & mask) 959 break; 960 961 used_mask |= mask; 962 963 if (assign) 964 assign[i] = hwc->idx; 965 } 966 967 /* slow path */ 968 if (i != n) { 969 int gpmax = x86_pmu.num_counters; 970 971 /* 972 * Do not allow scheduling of more than half the available 973 * generic counters. 974 * 975 * This helps avoid counter starvation of sibling thread by 976 * ensuring at most half the counters cannot be in exclusive 977 * mode. There is no designated counters for the limits. Any 978 * N/2 counters can be used. This helps with events with 979 * specific counter constraints. 980 */ 981 if (is_ht_workaround_enabled() && !cpuc->is_fake && 982 READ_ONCE(cpuc->excl_cntrs->exclusive_present)) 983 gpmax /= 2; 984 985 /* 986 * Reduce the amount of available counters to allow fitting 987 * the extra Merge events needed by large increment events. 988 */ 989 if (x86_pmu.flags & PMU_FL_PAIR) { 990 gpmax = x86_pmu.num_counters - cpuc->n_pair; 991 WARN_ON(gpmax <= 0); 992 } 993 994 unsched = perf_assign_events(cpuc->event_constraint, n, wmin, 995 wmax, gpmax, assign); 996 } 997 998 /* 999 * In case of success (unsched = 0), mark events as committed, 1000 * so we do not put_constraint() in case new events are added 1001 * and fail to be scheduled 1002 * 1003 * We invoke the lower level commit callback to lock the resource 1004 * 1005 * We do not need to do all of this in case we are called to 1006 * validate an event group (assign == NULL) 1007 */ 1008 if (!unsched && assign) { 1009 for (i = 0; i < n; i++) { 1010 e = cpuc->event_list[i]; 1011 if (x86_pmu.commit_scheduling) 1012 x86_pmu.commit_scheduling(cpuc, i, assign[i]); 1013 } 1014 } else { 1015 for (i = n0; i < n; i++) { 1016 e = cpuc->event_list[i]; 1017 1018 /* 1019 * release events that failed scheduling 1020 */ 1021 if (x86_pmu.put_event_constraints) 1022 x86_pmu.put_event_constraints(cpuc, e); 1023 1024 cpuc->event_constraint[i] = NULL; 1025 } 1026 } 1027 1028 if (x86_pmu.stop_scheduling) 1029 x86_pmu.stop_scheduling(cpuc); 1030 1031 return unsched ? -EINVAL : 0; 1032 } 1033 1034 /* 1035 * dogrp: true if must collect siblings events (group) 1036 * returns total number of events and error code 1037 */ 1038 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) 1039 { 1040 struct perf_event *event; 1041 int n, max_count; 1042 1043 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; 1044 1045 /* current number of events already accepted */ 1046 n = cpuc->n_events; 1047 if (!cpuc->n_events) 1048 cpuc->pebs_output = 0; 1049 1050 if (!cpuc->is_fake && leader->attr.precise_ip) { 1051 /* 1052 * For PEBS->PT, if !aux_event, the group leader (PT) went 1053 * away, the group was broken down and this singleton event 1054 * can't schedule any more. 1055 */ 1056 if (is_pebs_pt(leader) && !leader->aux_event) 1057 return -EINVAL; 1058 1059 /* 1060 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS 1061 */ 1062 if (cpuc->pebs_output && 1063 cpuc->pebs_output != is_pebs_pt(leader) + 1) 1064 return -EINVAL; 1065 1066 cpuc->pebs_output = is_pebs_pt(leader) + 1; 1067 } 1068 1069 if (is_x86_event(leader)) { 1070 if (n >= max_count) 1071 return -EINVAL; 1072 cpuc->event_list[n] = leader; 1073 n++; 1074 if (is_counter_pair(&leader->hw)) 1075 cpuc->n_pair++; 1076 } 1077 if (!dogrp) 1078 return n; 1079 1080 for_each_sibling_event(event, leader) { 1081 if (!is_x86_event(event) || 1082 event->state <= PERF_EVENT_STATE_OFF) 1083 continue; 1084 1085 if (n >= max_count) 1086 return -EINVAL; 1087 1088 cpuc->event_list[n] = event; 1089 n++; 1090 if (is_counter_pair(&event->hw)) 1091 cpuc->n_pair++; 1092 } 1093 return n; 1094 } 1095 1096 static inline void x86_assign_hw_event(struct perf_event *event, 1097 struct cpu_hw_events *cpuc, int i) 1098 { 1099 struct hw_perf_event *hwc = &event->hw; 1100 1101 hwc->idx = cpuc->assign[i]; 1102 hwc->last_cpu = smp_processor_id(); 1103 hwc->last_tag = ++cpuc->tags[i]; 1104 1105 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { 1106 hwc->config_base = 0; 1107 hwc->event_base = 0; 1108 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { 1109 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 1110 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); 1111 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; 1112 } else { 1113 hwc->config_base = x86_pmu_config_addr(hwc->idx); 1114 hwc->event_base = x86_pmu_event_addr(hwc->idx); 1115 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); 1116 } 1117 } 1118 1119 /** 1120 * x86_perf_rdpmc_index - Return PMC counter used for event 1121 * @event: the perf_event to which the PMC counter was assigned 1122 * 1123 * The counter assigned to this performance event may change if interrupts 1124 * are enabled. This counter should thus never be used while interrupts are 1125 * enabled. Before this function is used to obtain the assigned counter the 1126 * event should be checked for validity using, for example, 1127 * perf_event_read_local(), within the same interrupt disabled section in 1128 * which this counter is planned to be used. 1129 * 1130 * Return: The index of the performance monitoring counter assigned to 1131 * @perf_event. 1132 */ 1133 int x86_perf_rdpmc_index(struct perf_event *event) 1134 { 1135 lockdep_assert_irqs_disabled(); 1136 1137 return event->hw.event_base_rdpmc; 1138 } 1139 1140 static inline int match_prev_assignment(struct hw_perf_event *hwc, 1141 struct cpu_hw_events *cpuc, 1142 int i) 1143 { 1144 return hwc->idx == cpuc->assign[i] && 1145 hwc->last_cpu == smp_processor_id() && 1146 hwc->last_tag == cpuc->tags[i]; 1147 } 1148 1149 static void x86_pmu_start(struct perf_event *event, int flags); 1150 1151 static void x86_pmu_enable(struct pmu *pmu) 1152 { 1153 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1154 struct perf_event *event; 1155 struct hw_perf_event *hwc; 1156 int i, added = cpuc->n_added; 1157 1158 if (!x86_pmu_initialized()) 1159 return; 1160 1161 if (cpuc->enabled) 1162 return; 1163 1164 if (cpuc->n_added) { 1165 int n_running = cpuc->n_events - cpuc->n_added; 1166 /* 1167 * apply assignment obtained either from 1168 * hw_perf_group_sched_in() or x86_pmu_enable() 1169 * 1170 * step1: save events moving to new counters 1171 */ 1172 for (i = 0; i < n_running; i++) { 1173 event = cpuc->event_list[i]; 1174 hwc = &event->hw; 1175 1176 /* 1177 * we can avoid reprogramming counter if: 1178 * - assigned same counter as last time 1179 * - running on same CPU as last time 1180 * - no other event has used the counter since 1181 */ 1182 if (hwc->idx == -1 || 1183 match_prev_assignment(hwc, cpuc, i)) 1184 continue; 1185 1186 /* 1187 * Ensure we don't accidentally enable a stopped 1188 * counter simply because we rescheduled. 1189 */ 1190 if (hwc->state & PERF_HES_STOPPED) 1191 hwc->state |= PERF_HES_ARCH; 1192 1193 x86_pmu_stop(event, PERF_EF_UPDATE); 1194 } 1195 1196 /* 1197 * step2: reprogram moved events into new counters 1198 */ 1199 for (i = 0; i < cpuc->n_events; i++) { 1200 event = cpuc->event_list[i]; 1201 hwc = &event->hw; 1202 1203 if (!match_prev_assignment(hwc, cpuc, i)) 1204 x86_assign_hw_event(event, cpuc, i); 1205 else if (i < n_running) 1206 continue; 1207 1208 if (hwc->state & PERF_HES_ARCH) 1209 continue; 1210 1211 x86_pmu_start(event, PERF_EF_RELOAD); 1212 } 1213 cpuc->n_added = 0; 1214 perf_events_lapic_init(); 1215 } 1216 1217 cpuc->enabled = 1; 1218 barrier(); 1219 1220 x86_pmu.enable_all(added); 1221 } 1222 1223 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1224 1225 /* 1226 * Set the next IRQ period, based on the hwc->period_left value. 1227 * To be called with the event disabled in hw: 1228 */ 1229 int x86_perf_event_set_period(struct perf_event *event) 1230 { 1231 struct hw_perf_event *hwc = &event->hw; 1232 s64 left = local64_read(&hwc->period_left); 1233 s64 period = hwc->sample_period; 1234 int ret = 0, idx = hwc->idx; 1235 1236 if (idx == INTEL_PMC_IDX_FIXED_BTS) 1237 return 0; 1238 1239 /* 1240 * If we are way outside a reasonable range then just skip forward: 1241 */ 1242 if (unlikely(left <= -period)) { 1243 left = period; 1244 local64_set(&hwc->period_left, left); 1245 hwc->last_period = period; 1246 ret = 1; 1247 } 1248 1249 if (unlikely(left <= 0)) { 1250 left += period; 1251 local64_set(&hwc->period_left, left); 1252 hwc->last_period = period; 1253 ret = 1; 1254 } 1255 /* 1256 * Quirk: certain CPUs dont like it if just 1 hw_event is left: 1257 */ 1258 if (unlikely(left < 2)) 1259 left = 2; 1260 1261 if (left > x86_pmu.max_period) 1262 left = x86_pmu.max_period; 1263 1264 if (x86_pmu.limit_period) 1265 left = x86_pmu.limit_period(event, left); 1266 1267 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; 1268 1269 /* 1270 * The hw event starts counting from this event offset, 1271 * mark it to be able to extra future deltas: 1272 */ 1273 local64_set(&hwc->prev_count, (u64)-left); 1274 1275 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1276 1277 /* 1278 * Clear the Merge event counter's upper 16 bits since 1279 * we currently declare a 48-bit counter width 1280 */ 1281 if (is_counter_pair(hwc)) 1282 wrmsrl(x86_pmu_event_addr(idx + 1), 0); 1283 1284 /* 1285 * Due to erratum on certan cpu we need 1286 * a second write to be sure the register 1287 * is updated properly 1288 */ 1289 if (x86_pmu.perfctr_second_write) { 1290 wrmsrl(hwc->event_base, 1291 (u64)(-left) & x86_pmu.cntval_mask); 1292 } 1293 1294 perf_event_update_userpage(event); 1295 1296 return ret; 1297 } 1298 1299 void x86_pmu_enable_event(struct perf_event *event) 1300 { 1301 if (__this_cpu_read(cpu_hw_events.enabled)) 1302 __x86_pmu_enable_event(&event->hw, 1303 ARCH_PERFMON_EVENTSEL_ENABLE); 1304 } 1305 1306 /* 1307 * Add a single event to the PMU. 1308 * 1309 * The event is added to the group of enabled events 1310 * but only if it can be scheduled with existing events. 1311 */ 1312 static int x86_pmu_add(struct perf_event *event, int flags) 1313 { 1314 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1315 struct hw_perf_event *hwc; 1316 int assign[X86_PMC_IDX_MAX]; 1317 int n, n0, ret; 1318 1319 hwc = &event->hw; 1320 1321 n0 = cpuc->n_events; 1322 ret = n = collect_events(cpuc, event, false); 1323 if (ret < 0) 1324 goto out; 1325 1326 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1327 if (!(flags & PERF_EF_START)) 1328 hwc->state |= PERF_HES_ARCH; 1329 1330 /* 1331 * If group events scheduling transaction was started, 1332 * skip the schedulability test here, it will be performed 1333 * at commit time (->commit_txn) as a whole. 1334 * 1335 * If commit fails, we'll call ->del() on all events 1336 * for which ->add() was called. 1337 */ 1338 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1339 goto done_collect; 1340 1341 ret = x86_pmu.schedule_events(cpuc, n, assign); 1342 if (ret) 1343 goto out; 1344 /* 1345 * copy new assignment, now we know it is possible 1346 * will be used by hw_perf_enable() 1347 */ 1348 memcpy(cpuc->assign, assign, n*sizeof(int)); 1349 1350 done_collect: 1351 /* 1352 * Commit the collect_events() state. See x86_pmu_del() and 1353 * x86_pmu_*_txn(). 1354 */ 1355 cpuc->n_events = n; 1356 cpuc->n_added += n - n0; 1357 cpuc->n_txn += n - n0; 1358 1359 if (x86_pmu.add) { 1360 /* 1361 * This is before x86_pmu_enable() will call x86_pmu_start(), 1362 * so we enable LBRs before an event needs them etc.. 1363 */ 1364 x86_pmu.add(event); 1365 } 1366 1367 ret = 0; 1368 out: 1369 return ret; 1370 } 1371 1372 static void x86_pmu_start(struct perf_event *event, int flags) 1373 { 1374 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1375 int idx = event->hw.idx; 1376 1377 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) 1378 return; 1379 1380 if (WARN_ON_ONCE(idx == -1)) 1381 return; 1382 1383 if (flags & PERF_EF_RELOAD) { 1384 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1385 x86_perf_event_set_period(event); 1386 } 1387 1388 event->hw.state = 0; 1389 1390 cpuc->events[idx] = event; 1391 __set_bit(idx, cpuc->active_mask); 1392 __set_bit(idx, cpuc->running); 1393 x86_pmu.enable(event); 1394 perf_event_update_userpage(event); 1395 } 1396 1397 void perf_event_print_debug(void) 1398 { 1399 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; 1400 u64 pebs, debugctl; 1401 struct cpu_hw_events *cpuc; 1402 unsigned long flags; 1403 int cpu, idx; 1404 1405 if (!x86_pmu.num_counters) 1406 return; 1407 1408 local_irq_save(flags); 1409 1410 cpu = smp_processor_id(); 1411 cpuc = &per_cpu(cpu_hw_events, cpu); 1412 1413 if (x86_pmu.version >= 2) { 1414 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); 1415 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 1416 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); 1417 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); 1418 1419 pr_info("\n"); 1420 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); 1421 pr_info("CPU#%d: status: %016llx\n", cpu, status); 1422 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); 1423 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); 1424 if (x86_pmu.pebs_constraints) { 1425 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); 1426 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); 1427 } 1428 if (x86_pmu.lbr_nr) { 1429 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1430 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); 1431 } 1432 } 1433 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); 1434 1435 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1436 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); 1437 rdmsrl(x86_pmu_event_addr(idx), pmc_count); 1438 1439 prev_left = per_cpu(pmc_prev_left[idx], cpu); 1440 1441 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", 1442 cpu, idx, pmc_ctrl); 1443 pr_info("CPU#%d: gen-PMC%d count: %016llx\n", 1444 cpu, idx, pmc_count); 1445 pr_info("CPU#%d: gen-PMC%d left: %016llx\n", 1446 cpu, idx, prev_left); 1447 } 1448 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { 1449 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); 1450 1451 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", 1452 cpu, idx, pmc_count); 1453 } 1454 local_irq_restore(flags); 1455 } 1456 1457 void x86_pmu_stop(struct perf_event *event, int flags) 1458 { 1459 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1460 struct hw_perf_event *hwc = &event->hw; 1461 1462 if (test_bit(hwc->idx, cpuc->active_mask)) { 1463 x86_pmu.disable(event); 1464 __clear_bit(hwc->idx, cpuc->active_mask); 1465 cpuc->events[hwc->idx] = NULL; 1466 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); 1467 hwc->state |= PERF_HES_STOPPED; 1468 } 1469 1470 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 1471 /* 1472 * Drain the remaining delta count out of a event 1473 * that we are disabling: 1474 */ 1475 x86_perf_event_update(event); 1476 hwc->state |= PERF_HES_UPTODATE; 1477 } 1478 } 1479 1480 static void x86_pmu_del(struct perf_event *event, int flags) 1481 { 1482 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1483 int i; 1484 1485 /* 1486 * If we're called during a txn, we only need to undo x86_pmu.add. 1487 * The events never got scheduled and ->cancel_txn will truncate 1488 * the event_list. 1489 * 1490 * XXX assumes any ->del() called during a TXN will only be on 1491 * an event added during that same TXN. 1492 */ 1493 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1494 goto do_del; 1495 1496 /* 1497 * Not a TXN, therefore cleanup properly. 1498 */ 1499 x86_pmu_stop(event, PERF_EF_UPDATE); 1500 1501 for (i = 0; i < cpuc->n_events; i++) { 1502 if (event == cpuc->event_list[i]) 1503 break; 1504 } 1505 1506 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ 1507 return; 1508 1509 /* If we have a newly added event; make sure to decrease n_added. */ 1510 if (i >= cpuc->n_events - cpuc->n_added) 1511 --cpuc->n_added; 1512 1513 if (x86_pmu.put_event_constraints) 1514 x86_pmu.put_event_constraints(cpuc, event); 1515 1516 /* Delete the array entry. */ 1517 while (++i < cpuc->n_events) { 1518 cpuc->event_list[i-1] = cpuc->event_list[i]; 1519 cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; 1520 } 1521 cpuc->event_constraint[i-1] = NULL; 1522 --cpuc->n_events; 1523 1524 perf_event_update_userpage(event); 1525 1526 do_del: 1527 if (x86_pmu.del) { 1528 /* 1529 * This is after x86_pmu_stop(); so we disable LBRs after any 1530 * event can need them etc.. 1531 */ 1532 x86_pmu.del(event); 1533 } 1534 } 1535 1536 int x86_pmu_handle_irq(struct pt_regs *regs) 1537 { 1538 struct perf_sample_data data; 1539 struct cpu_hw_events *cpuc; 1540 struct perf_event *event; 1541 int idx, handled = 0; 1542 u64 val; 1543 1544 cpuc = this_cpu_ptr(&cpu_hw_events); 1545 1546 /* 1547 * Some chipsets need to unmask the LVTPC in a particular spot 1548 * inside the nmi handler. As a result, the unmasking was pushed 1549 * into all the nmi handlers. 1550 * 1551 * This generic handler doesn't seem to have any issues where the 1552 * unmasking occurs so it was left at the top. 1553 */ 1554 apic_write(APIC_LVTPC, APIC_DM_NMI); 1555 1556 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 1557 if (!test_bit(idx, cpuc->active_mask)) 1558 continue; 1559 1560 event = cpuc->events[idx]; 1561 1562 val = x86_perf_event_update(event); 1563 if (val & (1ULL << (x86_pmu.cntval_bits - 1))) 1564 continue; 1565 1566 /* 1567 * event overflow 1568 */ 1569 handled++; 1570 perf_sample_data_init(&data, 0, event->hw.last_period); 1571 1572 if (!x86_perf_event_set_period(event)) 1573 continue; 1574 1575 if (perf_event_overflow(event, &data, regs)) 1576 x86_pmu_stop(event, 0); 1577 } 1578 1579 if (handled) 1580 inc_irq_stat(apic_perf_irqs); 1581 1582 return handled; 1583 } 1584 1585 void perf_events_lapic_init(void) 1586 { 1587 if (!x86_pmu.apic || !x86_pmu_initialized()) 1588 return; 1589 1590 /* 1591 * Always use NMI for PMU 1592 */ 1593 apic_write(APIC_LVTPC, APIC_DM_NMI); 1594 } 1595 1596 static int 1597 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) 1598 { 1599 u64 start_clock; 1600 u64 finish_clock; 1601 int ret; 1602 1603 /* 1604 * All PMUs/events that share this PMI handler should make sure to 1605 * increment active_events for their events. 1606 */ 1607 if (!atomic_read(&active_events)) 1608 return NMI_DONE; 1609 1610 start_clock = sched_clock(); 1611 ret = x86_pmu.handle_irq(regs); 1612 finish_clock = sched_clock(); 1613 1614 perf_sample_event_took(finish_clock - start_clock); 1615 1616 return ret; 1617 } 1618 NOKPROBE_SYMBOL(perf_event_nmi_handler); 1619 1620 struct event_constraint emptyconstraint; 1621 struct event_constraint unconstrained; 1622 1623 static int x86_pmu_prepare_cpu(unsigned int cpu) 1624 { 1625 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1626 int i; 1627 1628 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) 1629 cpuc->kfree_on_online[i] = NULL; 1630 if (x86_pmu.cpu_prepare) 1631 return x86_pmu.cpu_prepare(cpu); 1632 return 0; 1633 } 1634 1635 static int x86_pmu_dead_cpu(unsigned int cpu) 1636 { 1637 if (x86_pmu.cpu_dead) 1638 x86_pmu.cpu_dead(cpu); 1639 return 0; 1640 } 1641 1642 static int x86_pmu_online_cpu(unsigned int cpu) 1643 { 1644 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1645 int i; 1646 1647 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { 1648 kfree(cpuc->kfree_on_online[i]); 1649 cpuc->kfree_on_online[i] = NULL; 1650 } 1651 return 0; 1652 } 1653 1654 static int x86_pmu_starting_cpu(unsigned int cpu) 1655 { 1656 if (x86_pmu.cpu_starting) 1657 x86_pmu.cpu_starting(cpu); 1658 return 0; 1659 } 1660 1661 static int x86_pmu_dying_cpu(unsigned int cpu) 1662 { 1663 if (x86_pmu.cpu_dying) 1664 x86_pmu.cpu_dying(cpu); 1665 return 0; 1666 } 1667 1668 static void __init pmu_check_apic(void) 1669 { 1670 if (boot_cpu_has(X86_FEATURE_APIC)) 1671 return; 1672 1673 x86_pmu.apic = 0; 1674 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); 1675 pr_info("no hardware sampling interrupt available.\n"); 1676 1677 /* 1678 * If we have a PMU initialized but no APIC 1679 * interrupts, we cannot sample hardware 1680 * events (user-space has to fall back and 1681 * sample via a hrtimer based software event): 1682 */ 1683 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; 1684 1685 } 1686 1687 static struct attribute_group x86_pmu_format_group __ro_after_init = { 1688 .name = "format", 1689 .attrs = NULL, 1690 }; 1691 1692 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) 1693 { 1694 struct perf_pmu_events_attr *pmu_attr = 1695 container_of(attr, struct perf_pmu_events_attr, attr); 1696 u64 config = 0; 1697 1698 if (pmu_attr->id < x86_pmu.max_events) 1699 config = x86_pmu.event_map(pmu_attr->id); 1700 1701 /* string trumps id */ 1702 if (pmu_attr->event_str) 1703 return sprintf(page, "%s", pmu_attr->event_str); 1704 1705 return x86_pmu.events_sysfs_show(page, config); 1706 } 1707 EXPORT_SYMBOL_GPL(events_sysfs_show); 1708 1709 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1710 char *page) 1711 { 1712 struct perf_pmu_events_ht_attr *pmu_attr = 1713 container_of(attr, struct perf_pmu_events_ht_attr, attr); 1714 1715 /* 1716 * Report conditional events depending on Hyper-Threading. 1717 * 1718 * This is overly conservative as usually the HT special 1719 * handling is not needed if the other CPU thread is idle. 1720 * 1721 * Note this does not (and cannot) handle the case when thread 1722 * siblings are invisible, for example with virtualization 1723 * if they are owned by some other guest. The user tool 1724 * has to re-read when a thread sibling gets onlined later. 1725 */ 1726 return sprintf(page, "%s", 1727 topology_max_smt_threads() > 1 ? 1728 pmu_attr->event_str_ht : 1729 pmu_attr->event_str_noht); 1730 } 1731 1732 EVENT_ATTR(cpu-cycles, CPU_CYCLES ); 1733 EVENT_ATTR(instructions, INSTRUCTIONS ); 1734 EVENT_ATTR(cache-references, CACHE_REFERENCES ); 1735 EVENT_ATTR(cache-misses, CACHE_MISSES ); 1736 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); 1737 EVENT_ATTR(branch-misses, BRANCH_MISSES ); 1738 EVENT_ATTR(bus-cycles, BUS_CYCLES ); 1739 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); 1740 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); 1741 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); 1742 1743 static struct attribute *empty_attrs; 1744 1745 static struct attribute *events_attr[] = { 1746 EVENT_PTR(CPU_CYCLES), 1747 EVENT_PTR(INSTRUCTIONS), 1748 EVENT_PTR(CACHE_REFERENCES), 1749 EVENT_PTR(CACHE_MISSES), 1750 EVENT_PTR(BRANCH_INSTRUCTIONS), 1751 EVENT_PTR(BRANCH_MISSES), 1752 EVENT_PTR(BUS_CYCLES), 1753 EVENT_PTR(STALLED_CYCLES_FRONTEND), 1754 EVENT_PTR(STALLED_CYCLES_BACKEND), 1755 EVENT_PTR(REF_CPU_CYCLES), 1756 NULL, 1757 }; 1758 1759 /* 1760 * Remove all undefined events (x86_pmu.event_map(id) == 0) 1761 * out of events_attr attributes. 1762 */ 1763 static umode_t 1764 is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1765 { 1766 struct perf_pmu_events_attr *pmu_attr; 1767 1768 if (idx >= x86_pmu.max_events) 1769 return 0; 1770 1771 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); 1772 /* str trumps id */ 1773 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0; 1774 } 1775 1776 static struct attribute_group x86_pmu_events_group __ro_after_init = { 1777 .name = "events", 1778 .attrs = events_attr, 1779 .is_visible = is_visible, 1780 }; 1781 1782 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) 1783 { 1784 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; 1785 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; 1786 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); 1787 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); 1788 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); 1789 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); 1790 ssize_t ret; 1791 1792 /* 1793 * We have whole page size to spend and just little data 1794 * to write, so we can safely use sprintf. 1795 */ 1796 ret = sprintf(page, "event=0x%02llx", event); 1797 1798 if (umask) 1799 ret += sprintf(page + ret, ",umask=0x%02llx", umask); 1800 1801 if (edge) 1802 ret += sprintf(page + ret, ",edge"); 1803 1804 if (pc) 1805 ret += sprintf(page + ret, ",pc"); 1806 1807 if (any) 1808 ret += sprintf(page + ret, ",any"); 1809 1810 if (inv) 1811 ret += sprintf(page + ret, ",inv"); 1812 1813 if (cmask) 1814 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); 1815 1816 ret += sprintf(page + ret, "\n"); 1817 1818 return ret; 1819 } 1820 1821 static struct attribute_group x86_pmu_attr_group; 1822 static struct attribute_group x86_pmu_caps_group; 1823 1824 static int __init init_hw_perf_events(void) 1825 { 1826 struct x86_pmu_quirk *quirk; 1827 int err; 1828 1829 pr_info("Performance Events: "); 1830 1831 switch (boot_cpu_data.x86_vendor) { 1832 case X86_VENDOR_INTEL: 1833 err = intel_pmu_init(); 1834 break; 1835 case X86_VENDOR_AMD: 1836 err = amd_pmu_init(); 1837 break; 1838 case X86_VENDOR_HYGON: 1839 err = amd_pmu_init(); 1840 x86_pmu.name = "HYGON"; 1841 break; 1842 default: 1843 err = -ENOTSUPP; 1844 } 1845 if (err != 0) { 1846 pr_cont("no PMU driver, software events only.\n"); 1847 return 0; 1848 } 1849 1850 pmu_check_apic(); 1851 1852 /* sanity check that the hardware exists or is emulated */ 1853 if (!check_hw_exists()) 1854 return 0; 1855 1856 pr_cont("%s PMU driver.\n", x86_pmu.name); 1857 1858 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ 1859 1860 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) 1861 quirk->func(); 1862 1863 if (!x86_pmu.intel_ctrl) 1864 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; 1865 1866 perf_events_lapic_init(); 1867 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); 1868 1869 unconstrained = (struct event_constraint) 1870 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, 1871 0, x86_pmu.num_counters, 0, 0); 1872 1873 x86_pmu_format_group.attrs = x86_pmu.format_attrs; 1874 1875 if (!x86_pmu.events_sysfs_show) 1876 x86_pmu_events_group.attrs = &empty_attrs; 1877 1878 pmu.attr_update = x86_pmu.attr_update; 1879 1880 pr_info("... version: %d\n", x86_pmu.version); 1881 pr_info("... bit width: %d\n", x86_pmu.cntval_bits); 1882 pr_info("... generic registers: %d\n", x86_pmu.num_counters); 1883 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); 1884 pr_info("... max period: %016Lx\n", x86_pmu.max_period); 1885 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); 1886 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); 1887 1888 /* 1889 * Install callbacks. Core will call them for each online 1890 * cpu. 1891 */ 1892 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", 1893 x86_pmu_prepare_cpu, x86_pmu_dead_cpu); 1894 if (err) 1895 return err; 1896 1897 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, 1898 "perf/x86:starting", x86_pmu_starting_cpu, 1899 x86_pmu_dying_cpu); 1900 if (err) 1901 goto out; 1902 1903 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online", 1904 x86_pmu_online_cpu, NULL); 1905 if (err) 1906 goto out1; 1907 1908 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1909 if (err) 1910 goto out2; 1911 1912 return 0; 1913 1914 out2: 1915 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); 1916 out1: 1917 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); 1918 out: 1919 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); 1920 return err; 1921 } 1922 early_initcall(init_hw_perf_events); 1923 1924 static inline void x86_pmu_read(struct perf_event *event) 1925 { 1926 if (x86_pmu.read) 1927 return x86_pmu.read(event); 1928 x86_perf_event_update(event); 1929 } 1930 1931 /* 1932 * Start group events scheduling transaction 1933 * Set the flag to make pmu::enable() not perform the 1934 * schedulability test, it will be performed at commit time 1935 * 1936 * We only support PERF_PMU_TXN_ADD transactions. Save the 1937 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1938 * transactions. 1939 */ 1940 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1941 { 1942 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1943 1944 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ 1945 1946 cpuc->txn_flags = txn_flags; 1947 if (txn_flags & ~PERF_PMU_TXN_ADD) 1948 return; 1949 1950 perf_pmu_disable(pmu); 1951 __this_cpu_write(cpu_hw_events.n_txn, 0); 1952 } 1953 1954 /* 1955 * Stop group events scheduling transaction 1956 * Clear the flag and pmu::enable() will perform the 1957 * schedulability test. 1958 */ 1959 static void x86_pmu_cancel_txn(struct pmu *pmu) 1960 { 1961 unsigned int txn_flags; 1962 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1963 1964 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1965 1966 txn_flags = cpuc->txn_flags; 1967 cpuc->txn_flags = 0; 1968 if (txn_flags & ~PERF_PMU_TXN_ADD) 1969 return; 1970 1971 /* 1972 * Truncate collected array by the number of events added in this 1973 * transaction. See x86_pmu_add() and x86_pmu_*_txn(). 1974 */ 1975 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); 1976 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); 1977 perf_pmu_enable(pmu); 1978 } 1979 1980 /* 1981 * Commit group events scheduling transaction 1982 * Perform the group schedulability test as a whole 1983 * Return 0 if success 1984 * 1985 * Does not cancel the transaction on failure; expects the caller to do this. 1986 */ 1987 static int x86_pmu_commit_txn(struct pmu *pmu) 1988 { 1989 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1990 int assign[X86_PMC_IDX_MAX]; 1991 int n, ret; 1992 1993 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1994 1995 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { 1996 cpuc->txn_flags = 0; 1997 return 0; 1998 } 1999 2000 n = cpuc->n_events; 2001 2002 if (!x86_pmu_initialized()) 2003 return -EAGAIN; 2004 2005 ret = x86_pmu.schedule_events(cpuc, n, assign); 2006 if (ret) 2007 return ret; 2008 2009 /* 2010 * copy new assignment, now we know it is possible 2011 * will be used by hw_perf_enable() 2012 */ 2013 memcpy(cpuc->assign, assign, n*sizeof(int)); 2014 2015 cpuc->txn_flags = 0; 2016 perf_pmu_enable(pmu); 2017 return 0; 2018 } 2019 /* 2020 * a fake_cpuc is used to validate event groups. Due to 2021 * the extra reg logic, we need to also allocate a fake 2022 * per_core and per_cpu structure. Otherwise, group events 2023 * using extra reg may conflict without the kernel being 2024 * able to catch this when the last event gets added to 2025 * the group. 2026 */ 2027 static void free_fake_cpuc(struct cpu_hw_events *cpuc) 2028 { 2029 intel_cpuc_finish(cpuc); 2030 kfree(cpuc); 2031 } 2032 2033 static struct cpu_hw_events *allocate_fake_cpuc(void) 2034 { 2035 struct cpu_hw_events *cpuc; 2036 int cpu = raw_smp_processor_id(); 2037 2038 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); 2039 if (!cpuc) 2040 return ERR_PTR(-ENOMEM); 2041 cpuc->is_fake = 1; 2042 2043 if (intel_cpuc_prepare(cpuc, cpu)) 2044 goto error; 2045 2046 return cpuc; 2047 error: 2048 free_fake_cpuc(cpuc); 2049 return ERR_PTR(-ENOMEM); 2050 } 2051 2052 /* 2053 * validate that we can schedule this event 2054 */ 2055 static int validate_event(struct perf_event *event) 2056 { 2057 struct cpu_hw_events *fake_cpuc; 2058 struct event_constraint *c; 2059 int ret = 0; 2060 2061 fake_cpuc = allocate_fake_cpuc(); 2062 if (IS_ERR(fake_cpuc)) 2063 return PTR_ERR(fake_cpuc); 2064 2065 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event); 2066 2067 if (!c || !c->weight) 2068 ret = -EINVAL; 2069 2070 if (x86_pmu.put_event_constraints) 2071 x86_pmu.put_event_constraints(fake_cpuc, event); 2072 2073 free_fake_cpuc(fake_cpuc); 2074 2075 return ret; 2076 } 2077 2078 /* 2079 * validate a single event group 2080 * 2081 * validation include: 2082 * - check events are compatible which each other 2083 * - events do not compete for the same counter 2084 * - number of events <= number of counters 2085 * 2086 * validation ensures the group can be loaded onto the 2087 * PMU if it was the only group available. 2088 */ 2089 static int validate_group(struct perf_event *event) 2090 { 2091 struct perf_event *leader = event->group_leader; 2092 struct cpu_hw_events *fake_cpuc; 2093 int ret = -EINVAL, n; 2094 2095 fake_cpuc = allocate_fake_cpuc(); 2096 if (IS_ERR(fake_cpuc)) 2097 return PTR_ERR(fake_cpuc); 2098 /* 2099 * the event is not yet connected with its 2100 * siblings therefore we must first collect 2101 * existing siblings, then add the new event 2102 * before we can simulate the scheduling 2103 */ 2104 n = collect_events(fake_cpuc, leader, true); 2105 if (n < 0) 2106 goto out; 2107 2108 fake_cpuc->n_events = n; 2109 n = collect_events(fake_cpuc, event, false); 2110 if (n < 0) 2111 goto out; 2112 2113 fake_cpuc->n_events = 0; 2114 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); 2115 2116 out: 2117 free_fake_cpuc(fake_cpuc); 2118 return ret; 2119 } 2120 2121 static int x86_pmu_event_init(struct perf_event *event) 2122 { 2123 struct pmu *tmp; 2124 int err; 2125 2126 switch (event->attr.type) { 2127 case PERF_TYPE_RAW: 2128 case PERF_TYPE_HARDWARE: 2129 case PERF_TYPE_HW_CACHE: 2130 break; 2131 2132 default: 2133 return -ENOENT; 2134 } 2135 2136 err = __x86_pmu_event_init(event); 2137 if (!err) { 2138 /* 2139 * we temporarily connect event to its pmu 2140 * such that validate_group() can classify 2141 * it as an x86 event using is_x86_event() 2142 */ 2143 tmp = event->pmu; 2144 event->pmu = &pmu; 2145 2146 if (event->group_leader != event) 2147 err = validate_group(event); 2148 else 2149 err = validate_event(event); 2150 2151 event->pmu = tmp; 2152 } 2153 if (err) { 2154 if (event->destroy) 2155 event->destroy(event); 2156 } 2157 2158 if (READ_ONCE(x86_pmu.attr_rdpmc) && 2159 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) 2160 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; 2161 2162 return err; 2163 } 2164 2165 static void refresh_pce(void *ignored) 2166 { 2167 load_mm_cr4_irqsoff(this_cpu_read(cpu_tlbstate.loaded_mm)); 2168 } 2169 2170 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) 2171 { 2172 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2173 return; 2174 2175 /* 2176 * This function relies on not being called concurrently in two 2177 * tasks in the same mm. Otherwise one task could observe 2178 * perf_rdpmc_allowed > 1 and return all the way back to 2179 * userspace with CR4.PCE clear while another task is still 2180 * doing on_each_cpu_mask() to propagate CR4.PCE. 2181 * 2182 * For now, this can't happen because all callers hold mmap_sem 2183 * for write. If this changes, we'll need a different solution. 2184 */ 2185 lockdep_assert_held_write(&mm->mmap_sem); 2186 2187 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1) 2188 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1); 2189 } 2190 2191 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) 2192 { 2193 2194 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2195 return; 2196 2197 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed)) 2198 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1); 2199 } 2200 2201 static int x86_pmu_event_idx(struct perf_event *event) 2202 { 2203 int idx = event->hw.idx; 2204 2205 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) 2206 return 0; 2207 2208 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { 2209 idx -= INTEL_PMC_IDX_FIXED; 2210 idx |= 1 << 30; 2211 } 2212 2213 return idx + 1; 2214 } 2215 2216 static ssize_t get_attr_rdpmc(struct device *cdev, 2217 struct device_attribute *attr, 2218 char *buf) 2219 { 2220 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); 2221 } 2222 2223 static ssize_t set_attr_rdpmc(struct device *cdev, 2224 struct device_attribute *attr, 2225 const char *buf, size_t count) 2226 { 2227 unsigned long val; 2228 ssize_t ret; 2229 2230 ret = kstrtoul(buf, 0, &val); 2231 if (ret) 2232 return ret; 2233 2234 if (val > 2) 2235 return -EINVAL; 2236 2237 if (x86_pmu.attr_rdpmc_broken) 2238 return -ENOTSUPP; 2239 2240 if (val != x86_pmu.attr_rdpmc) { 2241 /* 2242 * Changing into or out of never available or always available, 2243 * aka perf-event-bypassing mode. This path is extremely slow, 2244 * but only root can trigger it, so it's okay. 2245 */ 2246 if (val == 0) 2247 static_branch_inc(&rdpmc_never_available_key); 2248 else if (x86_pmu.attr_rdpmc == 0) 2249 static_branch_dec(&rdpmc_never_available_key); 2250 2251 if (val == 2) 2252 static_branch_inc(&rdpmc_always_available_key); 2253 else if (x86_pmu.attr_rdpmc == 2) 2254 static_branch_dec(&rdpmc_always_available_key); 2255 2256 on_each_cpu(refresh_pce, NULL, 1); 2257 x86_pmu.attr_rdpmc = val; 2258 } 2259 2260 return count; 2261 } 2262 2263 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); 2264 2265 static struct attribute *x86_pmu_attrs[] = { 2266 &dev_attr_rdpmc.attr, 2267 NULL, 2268 }; 2269 2270 static struct attribute_group x86_pmu_attr_group __ro_after_init = { 2271 .attrs = x86_pmu_attrs, 2272 }; 2273 2274 static ssize_t max_precise_show(struct device *cdev, 2275 struct device_attribute *attr, 2276 char *buf) 2277 { 2278 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise()); 2279 } 2280 2281 static DEVICE_ATTR_RO(max_precise); 2282 2283 static struct attribute *x86_pmu_caps_attrs[] = { 2284 &dev_attr_max_precise.attr, 2285 NULL 2286 }; 2287 2288 static struct attribute_group x86_pmu_caps_group __ro_after_init = { 2289 .name = "caps", 2290 .attrs = x86_pmu_caps_attrs, 2291 }; 2292 2293 static const struct attribute_group *x86_pmu_attr_groups[] = { 2294 &x86_pmu_attr_group, 2295 &x86_pmu_format_group, 2296 &x86_pmu_events_group, 2297 &x86_pmu_caps_group, 2298 NULL, 2299 }; 2300 2301 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 2302 { 2303 if (x86_pmu.sched_task) 2304 x86_pmu.sched_task(ctx, sched_in); 2305 } 2306 2307 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev, 2308 struct perf_event_context *next) 2309 { 2310 if (x86_pmu.swap_task_ctx) 2311 x86_pmu.swap_task_ctx(prev, next); 2312 } 2313 2314 void perf_check_microcode(void) 2315 { 2316 if (x86_pmu.check_microcode) 2317 x86_pmu.check_microcode(); 2318 } 2319 2320 static int x86_pmu_check_period(struct perf_event *event, u64 value) 2321 { 2322 if (x86_pmu.check_period && x86_pmu.check_period(event, value)) 2323 return -EINVAL; 2324 2325 if (value && x86_pmu.limit_period) { 2326 if (x86_pmu.limit_period(event, value) > value) 2327 return -EINVAL; 2328 } 2329 2330 return 0; 2331 } 2332 2333 static int x86_pmu_aux_output_match(struct perf_event *event) 2334 { 2335 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT)) 2336 return 0; 2337 2338 if (x86_pmu.aux_output_match) 2339 return x86_pmu.aux_output_match(event); 2340 2341 return 0; 2342 } 2343 2344 static struct pmu pmu = { 2345 .pmu_enable = x86_pmu_enable, 2346 .pmu_disable = x86_pmu_disable, 2347 2348 .attr_groups = x86_pmu_attr_groups, 2349 2350 .event_init = x86_pmu_event_init, 2351 2352 .event_mapped = x86_pmu_event_mapped, 2353 .event_unmapped = x86_pmu_event_unmapped, 2354 2355 .add = x86_pmu_add, 2356 .del = x86_pmu_del, 2357 .start = x86_pmu_start, 2358 .stop = x86_pmu_stop, 2359 .read = x86_pmu_read, 2360 2361 .start_txn = x86_pmu_start_txn, 2362 .cancel_txn = x86_pmu_cancel_txn, 2363 .commit_txn = x86_pmu_commit_txn, 2364 2365 .event_idx = x86_pmu_event_idx, 2366 .sched_task = x86_pmu_sched_task, 2367 .task_ctx_size = sizeof(struct x86_perf_task_context), 2368 .swap_task_ctx = x86_pmu_swap_task_ctx, 2369 .check_period = x86_pmu_check_period, 2370 2371 .aux_output_match = x86_pmu_aux_output_match, 2372 }; 2373 2374 void arch_perf_update_userpage(struct perf_event *event, 2375 struct perf_event_mmap_page *userpg, u64 now) 2376 { 2377 struct cyc2ns_data data; 2378 u64 offset; 2379 2380 userpg->cap_user_time = 0; 2381 userpg->cap_user_time_zero = 0; 2382 userpg->cap_user_rdpmc = 2383 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); 2384 userpg->pmc_width = x86_pmu.cntval_bits; 2385 2386 if (!using_native_sched_clock() || !sched_clock_stable()) 2387 return; 2388 2389 cyc2ns_read_begin(&data); 2390 2391 offset = data.cyc2ns_offset + __sched_clock_offset; 2392 2393 /* 2394 * Internal timekeeping for enabled/running/stopped times 2395 * is always in the local_clock domain. 2396 */ 2397 userpg->cap_user_time = 1; 2398 userpg->time_mult = data.cyc2ns_mul; 2399 userpg->time_shift = data.cyc2ns_shift; 2400 userpg->time_offset = offset - now; 2401 2402 /* 2403 * cap_user_time_zero doesn't make sense when we're using a different 2404 * time base for the records. 2405 */ 2406 if (!event->attr.use_clockid) { 2407 userpg->cap_user_time_zero = 1; 2408 userpg->time_zero = offset; 2409 } 2410 2411 cyc2ns_read_end(); 2412 } 2413 2414 /* 2415 * Determine whether the regs were taken from an irq/exception handler rather 2416 * than from perf_arch_fetch_caller_regs(). 2417 */ 2418 static bool perf_hw_regs(struct pt_regs *regs) 2419 { 2420 return regs->flags & X86_EFLAGS_FIXED; 2421 } 2422 2423 void 2424 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2425 { 2426 struct unwind_state state; 2427 unsigned long addr; 2428 2429 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2430 /* TODO: We don't support guest os callchain now */ 2431 return; 2432 } 2433 2434 if (perf_callchain_store(entry, regs->ip)) 2435 return; 2436 2437 if (perf_hw_regs(regs)) 2438 unwind_start(&state, current, regs, NULL); 2439 else 2440 unwind_start(&state, current, NULL, (void *)regs->sp); 2441 2442 for (; !unwind_done(&state); unwind_next_frame(&state)) { 2443 addr = unwind_get_return_address(&state); 2444 if (!addr || perf_callchain_store(entry, addr)) 2445 return; 2446 } 2447 } 2448 2449 static inline int 2450 valid_user_frame(const void __user *fp, unsigned long size) 2451 { 2452 return (__range_not_ok(fp, size, TASK_SIZE) == 0); 2453 } 2454 2455 static unsigned long get_segment_base(unsigned int segment) 2456 { 2457 struct desc_struct *desc; 2458 unsigned int idx = segment >> 3; 2459 2460 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { 2461 #ifdef CONFIG_MODIFY_LDT_SYSCALL 2462 struct ldt_struct *ldt; 2463 2464 /* IRQs are off, so this synchronizes with smp_store_release */ 2465 ldt = READ_ONCE(current->active_mm->context.ldt); 2466 if (!ldt || idx >= ldt->nr_entries) 2467 return 0; 2468 2469 desc = &ldt->entries[idx]; 2470 #else 2471 return 0; 2472 #endif 2473 } else { 2474 if (idx >= GDT_ENTRIES) 2475 return 0; 2476 2477 desc = raw_cpu_ptr(gdt_page.gdt) + idx; 2478 } 2479 2480 return get_desc_base(desc); 2481 } 2482 2483 #ifdef CONFIG_IA32_EMULATION 2484 2485 #include <linux/compat.h> 2486 2487 static inline int 2488 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) 2489 { 2490 /* 32-bit process in 64-bit kernel. */ 2491 unsigned long ss_base, cs_base; 2492 struct stack_frame_ia32 frame; 2493 const void __user *fp; 2494 2495 if (!test_thread_flag(TIF_IA32)) 2496 return 0; 2497 2498 cs_base = get_segment_base(regs->cs); 2499 ss_base = get_segment_base(regs->ss); 2500 2501 fp = compat_ptr(ss_base + regs->bp); 2502 pagefault_disable(); 2503 while (entry->nr < entry->max_stack) { 2504 unsigned long bytes; 2505 frame.next_frame = 0; 2506 frame.return_address = 0; 2507 2508 if (!valid_user_frame(fp, sizeof(frame))) 2509 break; 2510 2511 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); 2512 if (bytes != 0) 2513 break; 2514 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); 2515 if (bytes != 0) 2516 break; 2517 2518 perf_callchain_store(entry, cs_base + frame.return_address); 2519 fp = compat_ptr(ss_base + frame.next_frame); 2520 } 2521 pagefault_enable(); 2522 return 1; 2523 } 2524 #else 2525 static inline int 2526 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) 2527 { 2528 return 0; 2529 } 2530 #endif 2531 2532 void 2533 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2534 { 2535 struct stack_frame frame; 2536 const unsigned long __user *fp; 2537 2538 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2539 /* TODO: We don't support guest os callchain now */ 2540 return; 2541 } 2542 2543 /* 2544 * We don't know what to do with VM86 stacks.. ignore them for now. 2545 */ 2546 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) 2547 return; 2548 2549 fp = (unsigned long __user *)regs->bp; 2550 2551 perf_callchain_store(entry, regs->ip); 2552 2553 if (!nmi_uaccess_okay()) 2554 return; 2555 2556 if (perf_callchain_user32(regs, entry)) 2557 return; 2558 2559 pagefault_disable(); 2560 while (entry->nr < entry->max_stack) { 2561 unsigned long bytes; 2562 2563 frame.next_frame = NULL; 2564 frame.return_address = 0; 2565 2566 if (!valid_user_frame(fp, sizeof(frame))) 2567 break; 2568 2569 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp)); 2570 if (bytes != 0) 2571 break; 2572 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp)); 2573 if (bytes != 0) 2574 break; 2575 2576 perf_callchain_store(entry, frame.return_address); 2577 fp = (void __user *)frame.next_frame; 2578 } 2579 pagefault_enable(); 2580 } 2581 2582 /* 2583 * Deal with code segment offsets for the various execution modes: 2584 * 2585 * VM86 - the good olde 16 bit days, where the linear address is 2586 * 20 bits and we use regs->ip + 0x10 * regs->cs. 2587 * 2588 * IA32 - Where we need to look at GDT/LDT segment descriptor tables 2589 * to figure out what the 32bit base address is. 2590 * 2591 * X32 - has TIF_X32 set, but is running in x86_64 2592 * 2593 * X86_64 - CS,DS,SS,ES are all zero based. 2594 */ 2595 static unsigned long code_segment_base(struct pt_regs *regs) 2596 { 2597 /* 2598 * For IA32 we look at the GDT/LDT segment base to convert the 2599 * effective IP to a linear address. 2600 */ 2601 2602 #ifdef CONFIG_X86_32 2603 /* 2604 * If we are in VM86 mode, add the segment offset to convert to a 2605 * linear address. 2606 */ 2607 if (regs->flags & X86_VM_MASK) 2608 return 0x10 * regs->cs; 2609 2610 if (user_mode(regs) && regs->cs != __USER_CS) 2611 return get_segment_base(regs->cs); 2612 #else 2613 if (user_mode(regs) && !user_64bit_mode(regs) && 2614 regs->cs != __USER32_CS) 2615 return get_segment_base(regs->cs); 2616 #endif 2617 return 0; 2618 } 2619 2620 unsigned long perf_instruction_pointer(struct pt_regs *regs) 2621 { 2622 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) 2623 return perf_guest_cbs->get_guest_ip(); 2624 2625 return regs->ip + code_segment_base(regs); 2626 } 2627 2628 unsigned long perf_misc_flags(struct pt_regs *regs) 2629 { 2630 int misc = 0; 2631 2632 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2633 if (perf_guest_cbs->is_user_mode()) 2634 misc |= PERF_RECORD_MISC_GUEST_USER; 2635 else 2636 misc |= PERF_RECORD_MISC_GUEST_KERNEL; 2637 } else { 2638 if (user_mode(regs)) 2639 misc |= PERF_RECORD_MISC_USER; 2640 else 2641 misc |= PERF_RECORD_MISC_KERNEL; 2642 } 2643 2644 if (regs->flags & PERF_EFLAGS_EXACT) 2645 misc |= PERF_RECORD_MISC_EXACT_IP; 2646 2647 return misc; 2648 } 2649 2650 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) 2651 { 2652 cap->version = x86_pmu.version; 2653 cap->num_counters_gp = x86_pmu.num_counters; 2654 cap->num_counters_fixed = x86_pmu.num_counters_fixed; 2655 cap->bit_width_gp = x86_pmu.cntval_bits; 2656 cap->bit_width_fixed = x86_pmu.cntval_bits; 2657 cap->events_mask = (unsigned int)x86_pmu.events_maskl; 2658 cap->events_mask_len = x86_pmu.events_mask_len; 2659 } 2660 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); 2661