1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 btl $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 bt $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 .pushsection .entry_trampoline, "ax" 146 147/* 148 * The code in here gets remapped into cpu_entry_area's trampoline. This means 149 * that the assembler and linker have the wrong idea as to where this code 150 * lives (and, in fact, it's mapped more than once, so it's not even at a 151 * fixed address). So we can't reference any symbols outside the entry 152 * trampoline and expect it to work. 153 * 154 * Instead, we carefully abuse %rip-relative addressing. 155 * _entry_trampoline(%rip) refers to the start of the remapped) entry 156 * trampoline. We can thus find cpu_entry_area with this macro: 157 */ 158 159#define CPU_ENTRY_AREA \ 160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) 161 162/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ 163#define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ 164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA 165 166ENTRY(entry_SYSCALL_64_trampoline) 167 UNWIND_HINT_EMPTY 168 swapgs 169 170 /* Stash the user RSP. */ 171 movq %rsp, RSP_SCRATCH 172 173 /* Note: using %rsp as a scratch reg. */ 174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 175 176 /* Load the top of the task stack into RSP */ 177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp 178 179 /* Start building the simulated IRET frame. */ 180 pushq $__USER_DS /* pt_regs->ss */ 181 pushq RSP_SCRATCH /* pt_regs->sp */ 182 pushq %r11 /* pt_regs->flags */ 183 pushq $__USER_CS /* pt_regs->cs */ 184 pushq %rcx /* pt_regs->ip */ 185 186 /* 187 * x86 lacks a near absolute jump, and we can't jump to the real 188 * entry text with a relative jump. We could push the target 189 * address and then use retq, but this destroys the pipeline on 190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, 191 * spill RDI and restore it in a second-stage trampoline. 192 */ 193 pushq %rdi 194 movq $entry_SYSCALL_64_stage2, %rdi 195 JMP_NOSPEC %rdi 196END(entry_SYSCALL_64_trampoline) 197 198 .popsection 199 200ENTRY(entry_SYSCALL_64_stage2) 201 UNWIND_HINT_EMPTY 202 popq %rdi 203 jmp entry_SYSCALL_64_after_hwframe 204END(entry_SYSCALL_64_stage2) 205 206ENTRY(entry_SYSCALL_64) 207 UNWIND_HINT_EMPTY 208 /* 209 * Interrupts are off on entry. 210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 211 * it is too small to ever cause noticeable irq latency. 212 */ 213 214 swapgs 215 /* 216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it 217 * is not required to switch CR3. 218 */ 219 movq %rsp, PER_CPU_VAR(rsp_scratch) 220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 221 222 /* Construct struct pt_regs on stack */ 223 pushq $__USER_DS /* pt_regs->ss */ 224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 225 pushq %r11 /* pt_regs->flags */ 226 pushq $__USER_CS /* pt_regs->cs */ 227 pushq %rcx /* pt_regs->ip */ 228GLOBAL(entry_SYSCALL_64_after_hwframe) 229 pushq %rax /* pt_regs->orig_ax */ 230 231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 232 233 TRACE_IRQS_OFF 234 235 /* IRQs are off. */ 236 movq %rsp, %rdi 237 call do_syscall_64 /* returns with IRQs disabled */ 238 239 TRACE_IRQS_IRETQ /* we're about to change IF */ 240 241 /* 242 * Try to use SYSRET instead of IRET if we're returning to 243 * a completely clean 64-bit userspace context. If we're not, 244 * go to the slow exit path. 245 */ 246 movq RCX(%rsp), %rcx 247 movq RIP(%rsp), %r11 248 249 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 250 jne swapgs_restore_regs_and_return_to_usermode 251 252 /* 253 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 254 * in kernel space. This essentially lets the user take over 255 * the kernel, since userspace controls RSP. 256 * 257 * If width of "canonical tail" ever becomes variable, this will need 258 * to be updated to remain correct on both old and new CPUs. 259 * 260 * Change top bits to match most significant bit (47th or 56th bit 261 * depending on paging mode) in the address. 262 */ 263 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 264 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 265 266 /* If this changed %rcx, it was not canonical */ 267 cmpq %rcx, %r11 268 jne swapgs_restore_regs_and_return_to_usermode 269 270 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 271 jne swapgs_restore_regs_and_return_to_usermode 272 273 movq R11(%rsp), %r11 274 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 275 jne swapgs_restore_regs_and_return_to_usermode 276 277 /* 278 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 279 * restore RF properly. If the slowpath sets it for whatever reason, we 280 * need to restore it correctly. 281 * 282 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 283 * trap from userspace immediately after SYSRET. This would cause an 284 * infinite loop whenever #DB happens with register state that satisfies 285 * the opportunistic SYSRET conditions. For example, single-stepping 286 * this user code: 287 * 288 * movq $stuck_here, %rcx 289 * pushfq 290 * popq %r11 291 * stuck_here: 292 * 293 * would never get past 'stuck_here'. 294 */ 295 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 296 jnz swapgs_restore_regs_and_return_to_usermode 297 298 /* nothing to check for RSP */ 299 300 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 301 jne swapgs_restore_regs_and_return_to_usermode 302 303 /* 304 * We win! This label is here just for ease of understanding 305 * perf profiles. Nothing jumps here. 306 */ 307syscall_return_via_sysret: 308 /* rcx and r11 are already restored (see code above) */ 309 UNWIND_HINT_EMPTY 310 POP_REGS pop_rdi=0 skip_r11rcx=1 311 312 /* 313 * Now all regs are restored except RSP and RDI. 314 * Save old stack pointer and switch to trampoline stack. 315 */ 316 movq %rsp, %rdi 317 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 318 319 pushq RSP-RDI(%rdi) /* RSP */ 320 pushq (%rdi) /* RDI */ 321 322 /* 323 * We are on the trampoline stack. All regs except RDI are live. 324 * We can do future final exit work right here. 325 */ 326 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 327 328 popq %rdi 329 popq %rsp 330 USERGS_SYSRET64 331END(entry_SYSCALL_64) 332 333/* 334 * %rdi: prev task 335 * %rsi: next task 336 */ 337ENTRY(__switch_to_asm) 338 UNWIND_HINT_FUNC 339 /* 340 * Save callee-saved registers 341 * This must match the order in inactive_task_frame 342 */ 343 pushq %rbp 344 pushq %rbx 345 pushq %r12 346 pushq %r13 347 pushq %r14 348 pushq %r15 349 350 /* switch stack */ 351 movq %rsp, TASK_threadsp(%rdi) 352 movq TASK_threadsp(%rsi), %rsp 353 354#ifdef CONFIG_CC_STACKPROTECTOR 355 movq TASK_stack_canary(%rsi), %rbx 356 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 357#endif 358 359#ifdef CONFIG_RETPOLINE 360 /* 361 * When switching from a shallower to a deeper call stack 362 * the RSB may either underflow or use entries populated 363 * with userspace addresses. On CPUs where those concerns 364 * exist, overwrite the RSB with entries which capture 365 * speculative execution to prevent attack. 366 */ 367 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 368#endif 369 370 /* restore callee-saved registers */ 371 popq %r15 372 popq %r14 373 popq %r13 374 popq %r12 375 popq %rbx 376 popq %rbp 377 378 jmp __switch_to 379END(__switch_to_asm) 380 381/* 382 * A newly forked process directly context switches into this address. 383 * 384 * rax: prev task we switched from 385 * rbx: kernel thread func (NULL for user thread) 386 * r12: kernel thread arg 387 */ 388ENTRY(ret_from_fork) 389 UNWIND_HINT_EMPTY 390 movq %rax, %rdi 391 call schedule_tail /* rdi: 'prev' task parameter */ 392 393 testq %rbx, %rbx /* from kernel_thread? */ 394 jnz 1f /* kernel threads are uncommon */ 395 3962: 397 UNWIND_HINT_REGS 398 movq %rsp, %rdi 399 call syscall_return_slowpath /* returns with IRQs disabled */ 400 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 401 jmp swapgs_restore_regs_and_return_to_usermode 402 4031: 404 /* kernel thread */ 405 movq %r12, %rdi 406 CALL_NOSPEC %rbx 407 /* 408 * A kernel thread is allowed to return here after successfully 409 * calling do_execve(). Exit to userspace to complete the execve() 410 * syscall. 411 */ 412 movq $0, RAX(%rsp) 413 jmp 2b 414END(ret_from_fork) 415 416/* 417 * Build the entry stubs with some assembler magic. 418 * We pack 1 stub into every 8-byte block. 419 */ 420 .align 8 421ENTRY(irq_entries_start) 422 vector=FIRST_EXTERNAL_VECTOR 423 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 424 UNWIND_HINT_IRET_REGS 425 pushq $(~vector+0x80) /* Note: always in signed byte range */ 426 jmp common_interrupt 427 .align 8 428 vector=vector+1 429 .endr 430END(irq_entries_start) 431 432.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 433#ifdef CONFIG_DEBUG_ENTRY 434 pushq %rax 435 SAVE_FLAGS(CLBR_RAX) 436 testl $X86_EFLAGS_IF, %eax 437 jz .Lokay_\@ 438 ud2 439.Lokay_\@: 440 popq %rax 441#endif 442.endm 443 444/* 445 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 446 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 447 * Requires kernel GSBASE. 448 * 449 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 450 */ 451.macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 452 DEBUG_ENTRY_ASSERT_IRQS_OFF 453 454 .if \save_ret 455 /* 456 * If save_ret is set, the original stack contains one additional 457 * entry -- the return address. Therefore, move the address one 458 * entry below %rsp to \old_rsp. 459 */ 460 leaq 8(%rsp), \old_rsp 461 .else 462 movq %rsp, \old_rsp 463 .endif 464 465 .if \regs 466 UNWIND_HINT_REGS base=\old_rsp 467 .endif 468 469 incl PER_CPU_VAR(irq_count) 470 jnz .Lirq_stack_push_old_rsp_\@ 471 472 /* 473 * Right now, if we just incremented irq_count to zero, we've 474 * claimed the IRQ stack but we haven't switched to it yet. 475 * 476 * If anything is added that can interrupt us here without using IST, 477 * it must be *extremely* careful to limit its stack usage. This 478 * could include kprobes and a hypothetical future IST-less #DB 479 * handler. 480 * 481 * The OOPS unwinder relies on the word at the top of the IRQ 482 * stack linking back to the previous RSP for the entire time we're 483 * on the IRQ stack. For this to work reliably, we need to write 484 * it before we actually move ourselves to the IRQ stack. 485 */ 486 487 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 488 movq PER_CPU_VAR(irq_stack_ptr), %rsp 489 490#ifdef CONFIG_DEBUG_ENTRY 491 /* 492 * If the first movq above becomes wrong due to IRQ stack layout 493 * changes, the only way we'll notice is if we try to unwind right 494 * here. Assert that we set up the stack right to catch this type 495 * of bug quickly. 496 */ 497 cmpq -8(%rsp), \old_rsp 498 je .Lirq_stack_okay\@ 499 ud2 500 .Lirq_stack_okay\@: 501#endif 502 503.Lirq_stack_push_old_rsp_\@: 504 pushq \old_rsp 505 506 .if \regs 507 UNWIND_HINT_REGS indirect=1 508 .endif 509 510 .if \save_ret 511 /* 512 * Push the return address to the stack. This return address can 513 * be found at the "real" original RSP, which was offset by 8 at 514 * the beginning of this macro. 515 */ 516 pushq -8(\old_rsp) 517 .endif 518.endm 519 520/* 521 * Undoes ENTER_IRQ_STACK. 522 */ 523.macro LEAVE_IRQ_STACK regs=1 524 DEBUG_ENTRY_ASSERT_IRQS_OFF 525 /* We need to be off the IRQ stack before decrementing irq_count. */ 526 popq %rsp 527 528 .if \regs 529 UNWIND_HINT_REGS 530 .endif 531 532 /* 533 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 534 * the irq stack but we're not on it. 535 */ 536 537 decl PER_CPU_VAR(irq_count) 538.endm 539 540/* 541 * Interrupt entry helper function. 542 * 543 * Entry runs with interrupts off. Stack layout at entry: 544 * +----------------------------------------------------+ 545 * | regs->ss | 546 * | regs->rsp | 547 * | regs->eflags | 548 * | regs->cs | 549 * | regs->ip | 550 * +----------------------------------------------------+ 551 * | regs->orig_ax = ~(interrupt number) | 552 * +----------------------------------------------------+ 553 * | return address | 554 * +----------------------------------------------------+ 555 */ 556ENTRY(interrupt_entry) 557 UNWIND_HINT_FUNC 558 ASM_CLAC 559 cld 560 561 testb $3, CS-ORIG_RAX+8(%rsp) 562 jz 1f 563 SWAPGS 564 565 /* 566 * Switch to the thread stack. The IRET frame and orig_ax are 567 * on the stack, as well as the return address. RDI..R12 are 568 * not (yet) on the stack and space has not (yet) been 569 * allocated for them. 570 */ 571 pushq %rdi 572 573 /* Need to switch before accessing the thread stack. */ 574 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 575 movq %rsp, %rdi 576 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 577 578 /* 579 * We have RDI, return address, and orig_ax on the stack on 580 * top of the IRET frame. That means offset=24 581 */ 582 UNWIND_HINT_IRET_REGS base=%rdi offset=24 583 584 pushq 7*8(%rdi) /* regs->ss */ 585 pushq 6*8(%rdi) /* regs->rsp */ 586 pushq 5*8(%rdi) /* regs->eflags */ 587 pushq 4*8(%rdi) /* regs->cs */ 588 pushq 3*8(%rdi) /* regs->ip */ 589 pushq 2*8(%rdi) /* regs->orig_ax */ 590 pushq 8(%rdi) /* return address */ 591 UNWIND_HINT_FUNC 592 593 movq (%rdi), %rdi 5941: 595 596 PUSH_AND_CLEAR_REGS save_ret=1 597 ENCODE_FRAME_POINTER 8 598 599 testb $3, CS+8(%rsp) 600 jz 1f 601 602 /* 603 * IRQ from user mode. 604 * 605 * We need to tell lockdep that IRQs are off. We can't do this until 606 * we fix gsbase, and we should do it before enter_from_user_mode 607 * (which can take locks). Since TRACE_IRQS_OFF is idempotent, 608 * the simplest way to handle it is to just call it twice if 609 * we enter from user mode. There's no reason to optimize this since 610 * TRACE_IRQS_OFF is a no-op if lockdep is off. 611 */ 612 TRACE_IRQS_OFF 613 614 CALL_enter_from_user_mode 615 6161: 617 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 618 /* We entered an interrupt context - irqs are off: */ 619 TRACE_IRQS_OFF 620 621 ret 622END(interrupt_entry) 623 624 625/* Interrupt entry/exit. */ 626 627 /* 628 * The interrupt stubs push (~vector+0x80) onto the stack and 629 * then jump to common_interrupt. 630 */ 631 .p2align CONFIG_X86_L1_CACHE_SHIFT 632common_interrupt: 633 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 634 call interrupt_entry 635 UNWIND_HINT_REGS indirect=1 636 call do_IRQ /* rdi points to pt_regs */ 637 /* 0(%rsp): old RSP */ 638ret_from_intr: 639 DISABLE_INTERRUPTS(CLBR_ANY) 640 TRACE_IRQS_OFF 641 642 LEAVE_IRQ_STACK 643 644 testb $3, CS(%rsp) 645 jz retint_kernel 646 647 /* Interrupt came from user space */ 648GLOBAL(retint_user) 649 mov %rsp,%rdi 650 call prepare_exit_to_usermode 651 TRACE_IRQS_IRETQ 652 653GLOBAL(swapgs_restore_regs_and_return_to_usermode) 654#ifdef CONFIG_DEBUG_ENTRY 655 /* Assert that pt_regs indicates user mode. */ 656 testb $3, CS(%rsp) 657 jnz 1f 658 ud2 6591: 660#endif 661 POP_REGS pop_rdi=0 662 663 /* 664 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 665 * Save old stack pointer and switch to trampoline stack. 666 */ 667 movq %rsp, %rdi 668 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 669 670 /* Copy the IRET frame to the trampoline stack. */ 671 pushq 6*8(%rdi) /* SS */ 672 pushq 5*8(%rdi) /* RSP */ 673 pushq 4*8(%rdi) /* EFLAGS */ 674 pushq 3*8(%rdi) /* CS */ 675 pushq 2*8(%rdi) /* RIP */ 676 677 /* Push user RDI on the trampoline stack. */ 678 pushq (%rdi) 679 680 /* 681 * We are on the trampoline stack. All regs except RDI are live. 682 * We can do future final exit work right here. 683 */ 684 685 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 686 687 /* Restore RDI. */ 688 popq %rdi 689 SWAPGS 690 INTERRUPT_RETURN 691 692 693/* Returning to kernel space */ 694retint_kernel: 695#ifdef CONFIG_PREEMPT 696 /* Interrupts are off */ 697 /* Check if we need preemption */ 698 bt $9, EFLAGS(%rsp) /* were interrupts off? */ 699 jnc 1f 7000: cmpl $0, PER_CPU_VAR(__preempt_count) 701 jnz 1f 702 call preempt_schedule_irq 703 jmp 0b 7041: 705#endif 706 /* 707 * The iretq could re-enable interrupts: 708 */ 709 TRACE_IRQS_IRETQ 710 711GLOBAL(restore_regs_and_return_to_kernel) 712#ifdef CONFIG_DEBUG_ENTRY 713 /* Assert that pt_regs indicates kernel mode. */ 714 testb $3, CS(%rsp) 715 jz 1f 716 ud2 7171: 718#endif 719 POP_REGS 720 addq $8, %rsp /* skip regs->orig_ax */ 721 /* 722 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 723 * when returning from IPI handler. 724 */ 725 INTERRUPT_RETURN 726 727ENTRY(native_iret) 728 UNWIND_HINT_IRET_REGS 729 /* 730 * Are we returning to a stack segment from the LDT? Note: in 731 * 64-bit mode SS:RSP on the exception stack is always valid. 732 */ 733#ifdef CONFIG_X86_ESPFIX64 734 testb $4, (SS-RIP)(%rsp) 735 jnz native_irq_return_ldt 736#endif 737 738.global native_irq_return_iret 739native_irq_return_iret: 740 /* 741 * This may fault. Non-paranoid faults on return to userspace are 742 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 743 * Double-faults due to espfix64 are handled in do_double_fault. 744 * Other faults here are fatal. 745 */ 746 iretq 747 748#ifdef CONFIG_X86_ESPFIX64 749native_irq_return_ldt: 750 /* 751 * We are running with user GSBASE. All GPRs contain their user 752 * values. We have a percpu ESPFIX stack that is eight slots 753 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 754 * of the ESPFIX stack. 755 * 756 * We clobber RAX and RDI in this code. We stash RDI on the 757 * normal stack and RAX on the ESPFIX stack. 758 * 759 * The ESPFIX stack layout we set up looks like this: 760 * 761 * --- top of ESPFIX stack --- 762 * SS 763 * RSP 764 * RFLAGS 765 * CS 766 * RIP <-- RSP points here when we're done 767 * RAX <-- espfix_waddr points here 768 * --- bottom of ESPFIX stack --- 769 */ 770 771 pushq %rdi /* Stash user RDI */ 772 SWAPGS /* to kernel GS */ 773 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 774 775 movq PER_CPU_VAR(espfix_waddr), %rdi 776 movq %rax, (0*8)(%rdi) /* user RAX */ 777 movq (1*8)(%rsp), %rax /* user RIP */ 778 movq %rax, (1*8)(%rdi) 779 movq (2*8)(%rsp), %rax /* user CS */ 780 movq %rax, (2*8)(%rdi) 781 movq (3*8)(%rsp), %rax /* user RFLAGS */ 782 movq %rax, (3*8)(%rdi) 783 movq (5*8)(%rsp), %rax /* user SS */ 784 movq %rax, (5*8)(%rdi) 785 movq (4*8)(%rsp), %rax /* user RSP */ 786 movq %rax, (4*8)(%rdi) 787 /* Now RAX == RSP. */ 788 789 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 790 791 /* 792 * espfix_stack[31:16] == 0. The page tables are set up such that 793 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 794 * espfix_waddr for any X. That is, there are 65536 RO aliases of 795 * the same page. Set up RSP so that RSP[31:16] contains the 796 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 797 * still points to an RO alias of the ESPFIX stack. 798 */ 799 orq PER_CPU_VAR(espfix_stack), %rax 800 801 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 802 SWAPGS /* to user GS */ 803 popq %rdi /* Restore user RDI */ 804 805 movq %rax, %rsp 806 UNWIND_HINT_IRET_REGS offset=8 807 808 /* 809 * At this point, we cannot write to the stack any more, but we can 810 * still read. 811 */ 812 popq %rax /* Restore user RAX */ 813 814 /* 815 * RSP now points to an ordinary IRET frame, except that the page 816 * is read-only and RSP[31:16] are preloaded with the userspace 817 * values. We can now IRET back to userspace. 818 */ 819 jmp native_irq_return_iret 820#endif 821END(common_interrupt) 822 823/* 824 * APIC interrupts. 825 */ 826.macro apicinterrupt3 num sym do_sym 827ENTRY(\sym) 828 UNWIND_HINT_IRET_REGS 829 pushq $~(\num) 830.Lcommon_\sym: 831 call interrupt_entry 832 UNWIND_HINT_REGS indirect=1 833 call \do_sym /* rdi points to pt_regs */ 834 jmp ret_from_intr 835END(\sym) 836.endm 837 838/* Make sure APIC interrupt handlers end up in the irqentry section: */ 839#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 840#define POP_SECTION_IRQENTRY .popsection 841 842.macro apicinterrupt num sym do_sym 843PUSH_SECTION_IRQENTRY 844apicinterrupt3 \num \sym \do_sym 845POP_SECTION_IRQENTRY 846.endm 847 848#ifdef CONFIG_SMP 849apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 850apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 851#endif 852 853#ifdef CONFIG_X86_UV 854apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 855#endif 856 857apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 858apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 859 860#ifdef CONFIG_HAVE_KVM 861apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 862apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 863apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 864#endif 865 866#ifdef CONFIG_X86_MCE_THRESHOLD 867apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 868#endif 869 870#ifdef CONFIG_X86_MCE_AMD 871apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 872#endif 873 874#ifdef CONFIG_X86_THERMAL_VECTOR 875apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 876#endif 877 878#ifdef CONFIG_SMP 879apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 880apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 881apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 882#endif 883 884apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 885apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 886 887#ifdef CONFIG_IRQ_WORK 888apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 889#endif 890 891/* 892 * Exception entry points. 893 */ 894#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 895 896.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 897ENTRY(\sym) 898 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 899 900 /* Sanity check */ 901 .if \shift_ist != -1 && \paranoid == 0 902 .error "using shift_ist requires paranoid=1" 903 .endif 904 905 ASM_CLAC 906 907 .if \has_error_code == 0 908 pushq $-1 /* ORIG_RAX: no syscall to restart */ 909 .endif 910 911 .if \paranoid < 2 912 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ 913 jnz .Lfrom_usermode_switch_stack_\@ 914 .endif 915 916 .if \paranoid 917 call paranoid_entry 918 .else 919 call error_entry 920 .endif 921 UNWIND_HINT_REGS 922 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 923 924 .if \paranoid 925 .if \shift_ist != -1 926 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 927 .else 928 TRACE_IRQS_OFF 929 .endif 930 .endif 931 932 movq %rsp, %rdi /* pt_regs pointer */ 933 934 .if \has_error_code 935 movq ORIG_RAX(%rsp), %rsi /* get error code */ 936 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 937 .else 938 xorl %esi, %esi /* no error code */ 939 .endif 940 941 .if \shift_ist != -1 942 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 943 .endif 944 945 call \do_sym 946 947 .if \shift_ist != -1 948 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 949 .endif 950 951 /* these procedures expect "no swapgs" flag in ebx */ 952 .if \paranoid 953 jmp paranoid_exit 954 .else 955 jmp error_exit 956 .endif 957 958 .if \paranoid < 2 959 /* 960 * Entry from userspace. Switch stacks and treat it 961 * as a normal entry. This means that paranoid handlers 962 * run in real process context if user_mode(regs). 963 */ 964.Lfrom_usermode_switch_stack_\@: 965 call error_entry 966 967 movq %rsp, %rdi /* pt_regs pointer */ 968 969 .if \has_error_code 970 movq ORIG_RAX(%rsp), %rsi /* get error code */ 971 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 972 .else 973 xorl %esi, %esi /* no error code */ 974 .endif 975 976 call \do_sym 977 978 jmp error_exit /* %ebx: no swapgs flag */ 979 .endif 980END(\sym) 981.endm 982 983idtentry divide_error do_divide_error has_error_code=0 984idtentry overflow do_overflow has_error_code=0 985idtentry bounds do_bounds has_error_code=0 986idtentry invalid_op do_invalid_op has_error_code=0 987idtentry device_not_available do_device_not_available has_error_code=0 988idtentry double_fault do_double_fault has_error_code=1 paranoid=2 989idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 990idtentry invalid_TSS do_invalid_TSS has_error_code=1 991idtentry segment_not_present do_segment_not_present has_error_code=1 992idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 993idtentry coprocessor_error do_coprocessor_error has_error_code=0 994idtentry alignment_check do_alignment_check has_error_code=1 995idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 996 997 998 /* 999 * Reload gs selector with exception handling 1000 * edi: new selector 1001 */ 1002ENTRY(native_load_gs_index) 1003 FRAME_BEGIN 1004 pushfq 1005 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1006 TRACE_IRQS_OFF 1007 SWAPGS 1008.Lgs_change: 1009 movl %edi, %gs 10102: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1011 SWAPGS 1012 TRACE_IRQS_FLAGS (%rsp) 1013 popfq 1014 FRAME_END 1015 ret 1016ENDPROC(native_load_gs_index) 1017EXPORT_SYMBOL(native_load_gs_index) 1018 1019 _ASM_EXTABLE(.Lgs_change, bad_gs) 1020 .section .fixup, "ax" 1021 /* running with kernelgs */ 1022bad_gs: 1023 SWAPGS /* switch back to user gs */ 1024.macro ZAP_GS 1025 /* This can't be a string because the preprocessor needs to see it. */ 1026 movl $__USER_DS, %eax 1027 movl %eax, %gs 1028.endm 1029 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1030 xorl %eax, %eax 1031 movl %eax, %gs 1032 jmp 2b 1033 .previous 1034 1035/* Call softirq on interrupt stack. Interrupts are off. */ 1036ENTRY(do_softirq_own_stack) 1037 pushq %rbp 1038 mov %rsp, %rbp 1039 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1040 call __do_softirq 1041 LEAVE_IRQ_STACK regs=0 1042 leaveq 1043 ret 1044ENDPROC(do_softirq_own_stack) 1045 1046#ifdef CONFIG_XEN 1047idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1048 1049/* 1050 * A note on the "critical region" in our callback handler. 1051 * We want to avoid stacking callback handlers due to events occurring 1052 * during handling of the last event. To do this, we keep events disabled 1053 * until we've done all processing. HOWEVER, we must enable events before 1054 * popping the stack frame (can't be done atomically) and so it would still 1055 * be possible to get enough handler activations to overflow the stack. 1056 * Although unlikely, bugs of that kind are hard to track down, so we'd 1057 * like to avoid the possibility. 1058 * So, on entry to the handler we detect whether we interrupted an 1059 * existing activation in its critical region -- if so, we pop the current 1060 * activation and restart the handler using the previous one. 1061 */ 1062ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1063 1064/* 1065 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1066 * see the correct pointer to the pt_regs 1067 */ 1068 UNWIND_HINT_FUNC 1069 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1070 UNWIND_HINT_REGS 1071 1072 ENTER_IRQ_STACK old_rsp=%r10 1073 call xen_evtchn_do_upcall 1074 LEAVE_IRQ_STACK 1075 1076#ifndef CONFIG_PREEMPT 1077 call xen_maybe_preempt_hcall 1078#endif 1079 jmp error_exit 1080END(xen_do_hypervisor_callback) 1081 1082/* 1083 * Hypervisor uses this for application faults while it executes. 1084 * We get here for two reasons: 1085 * 1. Fault while reloading DS, ES, FS or GS 1086 * 2. Fault while executing IRET 1087 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1088 * registers that could be reloaded and zeroed the others. 1089 * Category 2 we fix up by killing the current process. We cannot use the 1090 * normal Linux return path in this case because if we use the IRET hypercall 1091 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1092 * We distinguish between categories by comparing each saved segment register 1093 * with its current contents: any discrepancy means we in category 1. 1094 */ 1095ENTRY(xen_failsafe_callback) 1096 UNWIND_HINT_EMPTY 1097 movl %ds, %ecx 1098 cmpw %cx, 0x10(%rsp) 1099 jne 1f 1100 movl %es, %ecx 1101 cmpw %cx, 0x18(%rsp) 1102 jne 1f 1103 movl %fs, %ecx 1104 cmpw %cx, 0x20(%rsp) 1105 jne 1f 1106 movl %gs, %ecx 1107 cmpw %cx, 0x28(%rsp) 1108 jne 1f 1109 /* All segments match their saved values => Category 2 (Bad IRET). */ 1110 movq (%rsp), %rcx 1111 movq 8(%rsp), %r11 1112 addq $0x30, %rsp 1113 pushq $0 /* RIP */ 1114 UNWIND_HINT_IRET_REGS offset=8 1115 jmp general_protection 11161: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1117 movq (%rsp), %rcx 1118 movq 8(%rsp), %r11 1119 addq $0x30, %rsp 1120 UNWIND_HINT_IRET_REGS 1121 pushq $-1 /* orig_ax = -1 => not a system call */ 1122 PUSH_AND_CLEAR_REGS 1123 ENCODE_FRAME_POINTER 1124 jmp error_exit 1125END(xen_failsafe_callback) 1126 1127apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1128 xen_hvm_callback_vector xen_evtchn_do_upcall 1129 1130#endif /* CONFIG_XEN */ 1131 1132#if IS_ENABLED(CONFIG_HYPERV) 1133apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1134 hyperv_callback_vector hyperv_vector_handler 1135 1136apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1137 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1138 1139apicinterrupt3 HYPERV_STIMER0_VECTOR \ 1140 hv_stimer0_callback_vector hv_stimer0_vector_handler 1141#endif /* CONFIG_HYPERV */ 1142 1143idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1144idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1145idtentry stack_segment do_stack_segment has_error_code=1 1146 1147#ifdef CONFIG_XEN 1148idtentry xennmi do_nmi has_error_code=0 1149idtentry xendebug do_debug has_error_code=0 1150idtentry xenint3 do_int3 has_error_code=0 1151#endif 1152 1153idtentry general_protection do_general_protection has_error_code=1 1154idtentry page_fault do_page_fault has_error_code=1 1155 1156#ifdef CONFIG_KVM_GUEST 1157idtentry async_page_fault do_async_page_fault has_error_code=1 1158#endif 1159 1160#ifdef CONFIG_X86_MCE 1161idtentry machine_check do_mce has_error_code=0 paranoid=1 1162#endif 1163 1164/* 1165 * Save all registers in pt_regs, and switch gs if needed. 1166 * Use slow, but surefire "are we in kernel?" check. 1167 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1168 */ 1169ENTRY(paranoid_entry) 1170 UNWIND_HINT_FUNC 1171 cld 1172 PUSH_AND_CLEAR_REGS save_ret=1 1173 ENCODE_FRAME_POINTER 8 1174 movl $1, %ebx 1175 movl $MSR_GS_BASE, %ecx 1176 rdmsr 1177 testl %edx, %edx 1178 js 1f /* negative -> in kernel */ 1179 SWAPGS 1180 xorl %ebx, %ebx 1181 11821: 1183 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1184 1185 ret 1186END(paranoid_entry) 1187 1188/* 1189 * "Paranoid" exit path from exception stack. This is invoked 1190 * only on return from non-NMI IST interrupts that came 1191 * from kernel space. 1192 * 1193 * We may be returning to very strange contexts (e.g. very early 1194 * in syscall entry), so checking for preemption here would 1195 * be complicated. Fortunately, we there's no good reason 1196 * to try to handle preemption here. 1197 * 1198 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1199 */ 1200ENTRY(paranoid_exit) 1201 UNWIND_HINT_REGS 1202 DISABLE_INTERRUPTS(CLBR_ANY) 1203 TRACE_IRQS_OFF_DEBUG 1204 testl %ebx, %ebx /* swapgs needed? */ 1205 jnz .Lparanoid_exit_no_swapgs 1206 TRACE_IRQS_IRETQ 1207 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1208 SWAPGS_UNSAFE_STACK 1209 jmp .Lparanoid_exit_restore 1210.Lparanoid_exit_no_swapgs: 1211 TRACE_IRQS_IRETQ_DEBUG 1212 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1213.Lparanoid_exit_restore: 1214 jmp restore_regs_and_return_to_kernel 1215END(paranoid_exit) 1216 1217/* 1218 * Save all registers in pt_regs, and switch GS if needed. 1219 * Return: EBX=0: came from user mode; EBX=1: otherwise 1220 */ 1221ENTRY(error_entry) 1222 UNWIND_HINT_FUNC 1223 cld 1224 PUSH_AND_CLEAR_REGS save_ret=1 1225 ENCODE_FRAME_POINTER 8 1226 testb $3, CS+8(%rsp) 1227 jz .Lerror_kernelspace 1228 1229 /* 1230 * We entered from user mode or we're pretending to have entered 1231 * from user mode due to an IRET fault. 1232 */ 1233 SWAPGS 1234 /* We have user CR3. Change to kernel CR3. */ 1235 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1236 1237.Lerror_entry_from_usermode_after_swapgs: 1238 /* Put us onto the real thread stack. */ 1239 popq %r12 /* save return addr in %12 */ 1240 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1241 call sync_regs 1242 movq %rax, %rsp /* switch stack */ 1243 ENCODE_FRAME_POINTER 1244 pushq %r12 1245 1246 /* 1247 * We need to tell lockdep that IRQs are off. We can't do this until 1248 * we fix gsbase, and we should do it before enter_from_user_mode 1249 * (which can take locks). 1250 */ 1251 TRACE_IRQS_OFF 1252 CALL_enter_from_user_mode 1253 ret 1254 1255.Lerror_entry_done: 1256 TRACE_IRQS_OFF 1257 ret 1258 1259 /* 1260 * There are two places in the kernel that can potentially fault with 1261 * usergs. Handle them here. B stepping K8s sometimes report a 1262 * truncated RIP for IRET exceptions returning to compat mode. Check 1263 * for these here too. 1264 */ 1265.Lerror_kernelspace: 1266 incl %ebx 1267 leaq native_irq_return_iret(%rip), %rcx 1268 cmpq %rcx, RIP+8(%rsp) 1269 je .Lerror_bad_iret 1270 movl %ecx, %eax /* zero extend */ 1271 cmpq %rax, RIP+8(%rsp) 1272 je .Lbstep_iret 1273 cmpq $.Lgs_change, RIP+8(%rsp) 1274 jne .Lerror_entry_done 1275 1276 /* 1277 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1278 * gsbase and proceed. We'll fix up the exception and land in 1279 * .Lgs_change's error handler with kernel gsbase. 1280 */ 1281 SWAPGS 1282 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1283 jmp .Lerror_entry_done 1284 1285.Lbstep_iret: 1286 /* Fix truncated RIP */ 1287 movq %rcx, RIP+8(%rsp) 1288 /* fall through */ 1289 1290.Lerror_bad_iret: 1291 /* 1292 * We came from an IRET to user mode, so we have user 1293 * gsbase and CR3. Switch to kernel gsbase and CR3: 1294 */ 1295 SWAPGS 1296 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1297 1298 /* 1299 * Pretend that the exception came from user mode: set up pt_regs 1300 * as if we faulted immediately after IRET and clear EBX so that 1301 * error_exit knows that we will be returning to user mode. 1302 */ 1303 mov %rsp, %rdi 1304 call fixup_bad_iret 1305 mov %rax, %rsp 1306 decl %ebx 1307 jmp .Lerror_entry_from_usermode_after_swapgs 1308END(error_entry) 1309 1310 1311/* 1312 * On entry, EBX is a "return to kernel mode" flag: 1313 * 1: already in kernel mode, don't need SWAPGS 1314 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode 1315 */ 1316ENTRY(error_exit) 1317 UNWIND_HINT_REGS 1318 DISABLE_INTERRUPTS(CLBR_ANY) 1319 TRACE_IRQS_OFF 1320 testl %ebx, %ebx 1321 jnz retint_kernel 1322 jmp retint_user 1323END(error_exit) 1324 1325/* 1326 * Runs on exception stack. Xen PV does not go through this path at all, 1327 * so we can use real assembly here. 1328 * 1329 * Registers: 1330 * %r14: Used to save/restore the CR3 of the interrupted context 1331 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1332 */ 1333ENTRY(nmi) 1334 UNWIND_HINT_IRET_REGS 1335 1336 /* 1337 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1338 * the iretq it performs will take us out of NMI context. 1339 * This means that we can have nested NMIs where the next 1340 * NMI is using the top of the stack of the previous NMI. We 1341 * can't let it execute because the nested NMI will corrupt the 1342 * stack of the previous NMI. NMI handlers are not re-entrant 1343 * anyway. 1344 * 1345 * To handle this case we do the following: 1346 * Check the a special location on the stack that contains 1347 * a variable that is set when NMIs are executing. 1348 * The interrupted task's stack is also checked to see if it 1349 * is an NMI stack. 1350 * If the variable is not set and the stack is not the NMI 1351 * stack then: 1352 * o Set the special variable on the stack 1353 * o Copy the interrupt frame into an "outermost" location on the 1354 * stack 1355 * o Copy the interrupt frame into an "iret" location on the stack 1356 * o Continue processing the NMI 1357 * If the variable is set or the previous stack is the NMI stack: 1358 * o Modify the "iret" location to jump to the repeat_nmi 1359 * o return back to the first NMI 1360 * 1361 * Now on exit of the first NMI, we first clear the stack variable 1362 * The NMI stack will tell any nested NMIs at that point that it is 1363 * nested. Then we pop the stack normally with iret, and if there was 1364 * a nested NMI that updated the copy interrupt stack frame, a 1365 * jump will be made to the repeat_nmi code that will handle the second 1366 * NMI. 1367 * 1368 * However, espfix prevents us from directly returning to userspace 1369 * with a single IRET instruction. Similarly, IRET to user mode 1370 * can fault. We therefore handle NMIs from user space like 1371 * other IST entries. 1372 */ 1373 1374 ASM_CLAC 1375 1376 /* Use %rdx as our temp variable throughout */ 1377 pushq %rdx 1378 1379 testb $3, CS-RIP+8(%rsp) 1380 jz .Lnmi_from_kernel 1381 1382 /* 1383 * NMI from user mode. We need to run on the thread stack, but we 1384 * can't go through the normal entry paths: NMIs are masked, and 1385 * we don't want to enable interrupts, because then we'll end 1386 * up in an awkward situation in which IRQs are on but NMIs 1387 * are off. 1388 * 1389 * We also must not push anything to the stack before switching 1390 * stacks lest we corrupt the "NMI executing" variable. 1391 */ 1392 1393 swapgs 1394 cld 1395 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1396 movq %rsp, %rdx 1397 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1398 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1399 pushq 5*8(%rdx) /* pt_regs->ss */ 1400 pushq 4*8(%rdx) /* pt_regs->rsp */ 1401 pushq 3*8(%rdx) /* pt_regs->flags */ 1402 pushq 2*8(%rdx) /* pt_regs->cs */ 1403 pushq 1*8(%rdx) /* pt_regs->rip */ 1404 UNWIND_HINT_IRET_REGS 1405 pushq $-1 /* pt_regs->orig_ax */ 1406 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1407 ENCODE_FRAME_POINTER 1408 1409 /* 1410 * At this point we no longer need to worry about stack damage 1411 * due to nesting -- we're on the normal thread stack and we're 1412 * done with the NMI stack. 1413 */ 1414 1415 movq %rsp, %rdi 1416 movq $-1, %rsi 1417 call do_nmi 1418 1419 /* 1420 * Return back to user mode. We must *not* do the normal exit 1421 * work, because we don't want to enable interrupts. 1422 */ 1423 jmp swapgs_restore_regs_and_return_to_usermode 1424 1425.Lnmi_from_kernel: 1426 /* 1427 * Here's what our stack frame will look like: 1428 * +---------------------------------------------------------+ 1429 * | original SS | 1430 * | original Return RSP | 1431 * | original RFLAGS | 1432 * | original CS | 1433 * | original RIP | 1434 * +---------------------------------------------------------+ 1435 * | temp storage for rdx | 1436 * +---------------------------------------------------------+ 1437 * | "NMI executing" variable | 1438 * +---------------------------------------------------------+ 1439 * | iret SS } Copied from "outermost" frame | 1440 * | iret Return RSP } on each loop iteration; overwritten | 1441 * | iret RFLAGS } by a nested NMI to force another | 1442 * | iret CS } iteration if needed. | 1443 * | iret RIP } | 1444 * +---------------------------------------------------------+ 1445 * | outermost SS } initialized in first_nmi; | 1446 * | outermost Return RSP } will not be changed before | 1447 * | outermost RFLAGS } NMI processing is done. | 1448 * | outermost CS } Copied to "iret" frame on each | 1449 * | outermost RIP } iteration. | 1450 * +---------------------------------------------------------+ 1451 * | pt_regs | 1452 * +---------------------------------------------------------+ 1453 * 1454 * The "original" frame is used by hardware. Before re-enabling 1455 * NMIs, we need to be done with it, and we need to leave enough 1456 * space for the asm code here. 1457 * 1458 * We return by executing IRET while RSP points to the "iret" frame. 1459 * That will either return for real or it will loop back into NMI 1460 * processing. 1461 * 1462 * The "outermost" frame is copied to the "iret" frame on each 1463 * iteration of the loop, so each iteration starts with the "iret" 1464 * frame pointing to the final return target. 1465 */ 1466 1467 /* 1468 * Determine whether we're a nested NMI. 1469 * 1470 * If we interrupted kernel code between repeat_nmi and 1471 * end_repeat_nmi, then we are a nested NMI. We must not 1472 * modify the "iret" frame because it's being written by 1473 * the outer NMI. That's okay; the outer NMI handler is 1474 * about to about to call do_nmi anyway, so we can just 1475 * resume the outer NMI. 1476 */ 1477 1478 movq $repeat_nmi, %rdx 1479 cmpq 8(%rsp), %rdx 1480 ja 1f 1481 movq $end_repeat_nmi, %rdx 1482 cmpq 8(%rsp), %rdx 1483 ja nested_nmi_out 14841: 1485 1486 /* 1487 * Now check "NMI executing". If it's set, then we're nested. 1488 * This will not detect if we interrupted an outer NMI just 1489 * before IRET. 1490 */ 1491 cmpl $1, -8(%rsp) 1492 je nested_nmi 1493 1494 /* 1495 * Now test if the previous stack was an NMI stack. This covers 1496 * the case where we interrupt an outer NMI after it clears 1497 * "NMI executing" but before IRET. We need to be careful, though: 1498 * there is one case in which RSP could point to the NMI stack 1499 * despite there being no NMI active: naughty userspace controls 1500 * RSP at the very beginning of the SYSCALL targets. We can 1501 * pull a fast one on naughty userspace, though: we program 1502 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1503 * if it controls the kernel's RSP. We set DF before we clear 1504 * "NMI executing". 1505 */ 1506 lea 6*8(%rsp), %rdx 1507 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1508 cmpq %rdx, 4*8(%rsp) 1509 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1510 ja first_nmi 1511 1512 subq $EXCEPTION_STKSZ, %rdx 1513 cmpq %rdx, 4*8(%rsp) 1514 /* If it is below the NMI stack, it is a normal NMI */ 1515 jb first_nmi 1516 1517 /* Ah, it is within the NMI stack. */ 1518 1519 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1520 jz first_nmi /* RSP was user controlled. */ 1521 1522 /* This is a nested NMI. */ 1523 1524nested_nmi: 1525 /* 1526 * Modify the "iret" frame to point to repeat_nmi, forcing another 1527 * iteration of NMI handling. 1528 */ 1529 subq $8, %rsp 1530 leaq -10*8(%rsp), %rdx 1531 pushq $__KERNEL_DS 1532 pushq %rdx 1533 pushfq 1534 pushq $__KERNEL_CS 1535 pushq $repeat_nmi 1536 1537 /* Put stack back */ 1538 addq $(6*8), %rsp 1539 1540nested_nmi_out: 1541 popq %rdx 1542 1543 /* We are returning to kernel mode, so this cannot result in a fault. */ 1544 iretq 1545 1546first_nmi: 1547 /* Restore rdx. */ 1548 movq (%rsp), %rdx 1549 1550 /* Make room for "NMI executing". */ 1551 pushq $0 1552 1553 /* Leave room for the "iret" frame */ 1554 subq $(5*8), %rsp 1555 1556 /* Copy the "original" frame to the "outermost" frame */ 1557 .rept 5 1558 pushq 11*8(%rsp) 1559 .endr 1560 UNWIND_HINT_IRET_REGS 1561 1562 /* Everything up to here is safe from nested NMIs */ 1563 1564#ifdef CONFIG_DEBUG_ENTRY 1565 /* 1566 * For ease of testing, unmask NMIs right away. Disabled by 1567 * default because IRET is very expensive. 1568 */ 1569 pushq $0 /* SS */ 1570 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1571 addq $8, (%rsp) /* Fix up RSP */ 1572 pushfq /* RFLAGS */ 1573 pushq $__KERNEL_CS /* CS */ 1574 pushq $1f /* RIP */ 1575 iretq /* continues at repeat_nmi below */ 1576 UNWIND_HINT_IRET_REGS 15771: 1578#endif 1579 1580repeat_nmi: 1581 /* 1582 * If there was a nested NMI, the first NMI's iret will return 1583 * here. But NMIs are still enabled and we can take another 1584 * nested NMI. The nested NMI checks the interrupted RIP to see 1585 * if it is between repeat_nmi and end_repeat_nmi, and if so 1586 * it will just return, as we are about to repeat an NMI anyway. 1587 * This makes it safe to copy to the stack frame that a nested 1588 * NMI will update. 1589 * 1590 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1591 * we're repeating an NMI, gsbase has the same value that it had on 1592 * the first iteration. paranoid_entry will load the kernel 1593 * gsbase if needed before we call do_nmi. "NMI executing" 1594 * is zero. 1595 */ 1596 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1597 1598 /* 1599 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1600 * here must not modify the "iret" frame while we're writing to 1601 * it or it will end up containing garbage. 1602 */ 1603 addq $(10*8), %rsp 1604 .rept 5 1605 pushq -6*8(%rsp) 1606 .endr 1607 subq $(5*8), %rsp 1608end_repeat_nmi: 1609 1610 /* 1611 * Everything below this point can be preempted by a nested NMI. 1612 * If this happens, then the inner NMI will change the "iret" 1613 * frame to point back to repeat_nmi. 1614 */ 1615 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1616 1617 /* 1618 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1619 * as we should not be calling schedule in NMI context. 1620 * Even with normal interrupts enabled. An NMI should not be 1621 * setting NEED_RESCHED or anything that normal interrupts and 1622 * exceptions might do. 1623 */ 1624 call paranoid_entry 1625 UNWIND_HINT_REGS 1626 1627 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1628 movq %rsp, %rdi 1629 movq $-1, %rsi 1630 call do_nmi 1631 1632 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1633 1634 testl %ebx, %ebx /* swapgs needed? */ 1635 jnz nmi_restore 1636nmi_swapgs: 1637 SWAPGS_UNSAFE_STACK 1638nmi_restore: 1639 POP_REGS 1640 1641 /* 1642 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1643 * at the "iret" frame. 1644 */ 1645 addq $6*8, %rsp 1646 1647 /* 1648 * Clear "NMI executing". Set DF first so that we can easily 1649 * distinguish the remaining code between here and IRET from 1650 * the SYSCALL entry and exit paths. 1651 * 1652 * We arguably should just inspect RIP instead, but I (Andy) wrote 1653 * this code when I had the misapprehension that Xen PV supported 1654 * NMIs, and Xen PV would break that approach. 1655 */ 1656 std 1657 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1658 1659 /* 1660 * iretq reads the "iret" frame and exits the NMI stack in a 1661 * single instruction. We are returning to kernel mode, so this 1662 * cannot result in a fault. Similarly, we don't need to worry 1663 * about espfix64 on the way back to kernel mode. 1664 */ 1665 iretq 1666END(nmi) 1667 1668ENTRY(ignore_sysret) 1669 UNWIND_HINT_EMPTY 1670 mov $-ENOSYS, %eax 1671 sysret 1672END(ignore_sysret) 1673 1674ENTRY(rewind_stack_do_exit) 1675 UNWIND_HINT_FUNC 1676 /* Prevent any naive code from trying to unwind to our caller. */ 1677 xorl %ebp, %ebp 1678 1679 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1680 leaq -PTREGS_SIZE(%rax), %rsp 1681 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1682 1683 call do_exit 1684END(rewind_stack_do_exit) 1685