1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 btl $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 btl $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145ENTRY(entry_SYSCALL_64) 146 UNWIND_HINT_EMPTY 147 /* 148 * Interrupts are off on entry. 149 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 150 * it is too small to ever cause noticeable irq latency. 151 */ 152 153 swapgs 154 /* tss.sp2 is scratch space. */ 155 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 156 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 157 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 158 159 /* Construct struct pt_regs on stack */ 160 pushq $__USER_DS /* pt_regs->ss */ 161 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 162 pushq %r11 /* pt_regs->flags */ 163 pushq $__USER_CS /* pt_regs->cs */ 164 pushq %rcx /* pt_regs->ip */ 165GLOBAL(entry_SYSCALL_64_after_hwframe) 166 pushq %rax /* pt_regs->orig_ax */ 167 168 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 169 170 TRACE_IRQS_OFF 171 172 /* IRQs are off. */ 173 movq %rax, %rdi 174 movq %rsp, %rsi 175 call do_syscall_64 /* returns with IRQs disabled */ 176 177 TRACE_IRQS_IRETQ /* we're about to change IF */ 178 179 /* 180 * Try to use SYSRET instead of IRET if we're returning to 181 * a completely clean 64-bit userspace context. If we're not, 182 * go to the slow exit path. 183 */ 184 movq RCX(%rsp), %rcx 185 movq RIP(%rsp), %r11 186 187 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 188 jne swapgs_restore_regs_and_return_to_usermode 189 190 /* 191 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 192 * in kernel space. This essentially lets the user take over 193 * the kernel, since userspace controls RSP. 194 * 195 * If width of "canonical tail" ever becomes variable, this will need 196 * to be updated to remain correct on both old and new CPUs. 197 * 198 * Change top bits to match most significant bit (47th or 56th bit 199 * depending on paging mode) in the address. 200 */ 201#ifdef CONFIG_X86_5LEVEL 202 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 203 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 204#else 205 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 206 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 207#endif 208 209 /* If this changed %rcx, it was not canonical */ 210 cmpq %rcx, %r11 211 jne swapgs_restore_regs_and_return_to_usermode 212 213 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 214 jne swapgs_restore_regs_and_return_to_usermode 215 216 movq R11(%rsp), %r11 217 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 218 jne swapgs_restore_regs_and_return_to_usermode 219 220 /* 221 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 222 * restore RF properly. If the slowpath sets it for whatever reason, we 223 * need to restore it correctly. 224 * 225 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 226 * trap from userspace immediately after SYSRET. This would cause an 227 * infinite loop whenever #DB happens with register state that satisfies 228 * the opportunistic SYSRET conditions. For example, single-stepping 229 * this user code: 230 * 231 * movq $stuck_here, %rcx 232 * pushfq 233 * popq %r11 234 * stuck_here: 235 * 236 * would never get past 'stuck_here'. 237 */ 238 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 239 jnz swapgs_restore_regs_and_return_to_usermode 240 241 /* nothing to check for RSP */ 242 243 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 244 jne swapgs_restore_regs_and_return_to_usermode 245 246 /* 247 * We win! This label is here just for ease of understanding 248 * perf profiles. Nothing jumps here. 249 */ 250syscall_return_via_sysret: 251 /* rcx and r11 are already restored (see code above) */ 252 UNWIND_HINT_EMPTY 253 POP_REGS pop_rdi=0 skip_r11rcx=1 254 255 /* 256 * Now all regs are restored except RSP and RDI. 257 * Save old stack pointer and switch to trampoline stack. 258 */ 259 movq %rsp, %rdi 260 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 261 262 pushq RSP-RDI(%rdi) /* RSP */ 263 pushq (%rdi) /* RDI */ 264 265 /* 266 * We are on the trampoline stack. All regs except RDI are live. 267 * We can do future final exit work right here. 268 */ 269 STACKLEAK_ERASE_NOCLOBBER 270 271 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 272 273 popq %rdi 274 popq %rsp 275 USERGS_SYSRET64 276END(entry_SYSCALL_64) 277 278/* 279 * %rdi: prev task 280 * %rsi: next task 281 */ 282ENTRY(__switch_to_asm) 283 UNWIND_HINT_FUNC 284 /* 285 * Save callee-saved registers 286 * This must match the order in inactive_task_frame 287 */ 288 pushq %rbp 289 pushq %rbx 290 pushq %r12 291 pushq %r13 292 pushq %r14 293 pushq %r15 294 295 /* switch stack */ 296 movq %rsp, TASK_threadsp(%rdi) 297 movq TASK_threadsp(%rsi), %rsp 298 299#ifdef CONFIG_STACKPROTECTOR 300 movq TASK_stack_canary(%rsi), %rbx 301 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset 302#endif 303 304#ifdef CONFIG_RETPOLINE 305 /* 306 * When switching from a shallower to a deeper call stack 307 * the RSB may either underflow or use entries populated 308 * with userspace addresses. On CPUs where those concerns 309 * exist, overwrite the RSB with entries which capture 310 * speculative execution to prevent attack. 311 */ 312 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 313#endif 314 315 /* restore callee-saved registers */ 316 popq %r15 317 popq %r14 318 popq %r13 319 popq %r12 320 popq %rbx 321 popq %rbp 322 323 jmp __switch_to 324END(__switch_to_asm) 325 326/* 327 * A newly forked process directly context switches into this address. 328 * 329 * rax: prev task we switched from 330 * rbx: kernel thread func (NULL for user thread) 331 * r12: kernel thread arg 332 */ 333ENTRY(ret_from_fork) 334 UNWIND_HINT_EMPTY 335 movq %rax, %rdi 336 call schedule_tail /* rdi: 'prev' task parameter */ 337 338 testq %rbx, %rbx /* from kernel_thread? */ 339 jnz 1f /* kernel threads are uncommon */ 340 3412: 342 UNWIND_HINT_REGS 343 movq %rsp, %rdi 344 call syscall_return_slowpath /* returns with IRQs disabled */ 345 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 346 jmp swapgs_restore_regs_and_return_to_usermode 347 3481: 349 /* kernel thread */ 350 UNWIND_HINT_EMPTY 351 movq %r12, %rdi 352 CALL_NOSPEC %rbx 353 /* 354 * A kernel thread is allowed to return here after successfully 355 * calling do_execve(). Exit to userspace to complete the execve() 356 * syscall. 357 */ 358 movq $0, RAX(%rsp) 359 jmp 2b 360END(ret_from_fork) 361 362/* 363 * Build the entry stubs with some assembler magic. 364 * We pack 1 stub into every 8-byte block. 365 */ 366 .align 8 367ENTRY(irq_entries_start) 368 vector=FIRST_EXTERNAL_VECTOR 369 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 370 UNWIND_HINT_IRET_REGS 371 pushq $(~vector+0x80) /* Note: always in signed byte range */ 372 jmp common_interrupt 373 .align 8 374 vector=vector+1 375 .endr 376END(irq_entries_start) 377 378.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 379#ifdef CONFIG_DEBUG_ENTRY 380 pushq %rax 381 SAVE_FLAGS(CLBR_RAX) 382 testl $X86_EFLAGS_IF, %eax 383 jz .Lokay_\@ 384 ud2 385.Lokay_\@: 386 popq %rax 387#endif 388.endm 389 390/* 391 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 392 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 393 * Requires kernel GSBASE. 394 * 395 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 396 */ 397.macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 398 DEBUG_ENTRY_ASSERT_IRQS_OFF 399 400 .if \save_ret 401 /* 402 * If save_ret is set, the original stack contains one additional 403 * entry -- the return address. Therefore, move the address one 404 * entry below %rsp to \old_rsp. 405 */ 406 leaq 8(%rsp), \old_rsp 407 .else 408 movq %rsp, \old_rsp 409 .endif 410 411 .if \regs 412 UNWIND_HINT_REGS base=\old_rsp 413 .endif 414 415 incl PER_CPU_VAR(irq_count) 416 jnz .Lirq_stack_push_old_rsp_\@ 417 418 /* 419 * Right now, if we just incremented irq_count to zero, we've 420 * claimed the IRQ stack but we haven't switched to it yet. 421 * 422 * If anything is added that can interrupt us here without using IST, 423 * it must be *extremely* careful to limit its stack usage. This 424 * could include kprobes and a hypothetical future IST-less #DB 425 * handler. 426 * 427 * The OOPS unwinder relies on the word at the top of the IRQ 428 * stack linking back to the previous RSP for the entire time we're 429 * on the IRQ stack. For this to work reliably, we need to write 430 * it before we actually move ourselves to the IRQ stack. 431 */ 432 433 movq \old_rsp, PER_CPU_VAR(irq_stack_backing_store + IRQ_STACK_SIZE - 8) 434 movq PER_CPU_VAR(hardirq_stack_ptr), %rsp 435 436#ifdef CONFIG_DEBUG_ENTRY 437 /* 438 * If the first movq above becomes wrong due to IRQ stack layout 439 * changes, the only way we'll notice is if we try to unwind right 440 * here. Assert that we set up the stack right to catch this type 441 * of bug quickly. 442 */ 443 cmpq -8(%rsp), \old_rsp 444 je .Lirq_stack_okay\@ 445 ud2 446 .Lirq_stack_okay\@: 447#endif 448 449.Lirq_stack_push_old_rsp_\@: 450 pushq \old_rsp 451 452 .if \regs 453 UNWIND_HINT_REGS indirect=1 454 .endif 455 456 .if \save_ret 457 /* 458 * Push the return address to the stack. This return address can 459 * be found at the "real" original RSP, which was offset by 8 at 460 * the beginning of this macro. 461 */ 462 pushq -8(\old_rsp) 463 .endif 464.endm 465 466/* 467 * Undoes ENTER_IRQ_STACK. 468 */ 469.macro LEAVE_IRQ_STACK regs=1 470 DEBUG_ENTRY_ASSERT_IRQS_OFF 471 /* We need to be off the IRQ stack before decrementing irq_count. */ 472 popq %rsp 473 474 .if \regs 475 UNWIND_HINT_REGS 476 .endif 477 478 /* 479 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 480 * the irq stack but we're not on it. 481 */ 482 483 decl PER_CPU_VAR(irq_count) 484.endm 485 486/* 487 * Interrupt entry helper function. 488 * 489 * Entry runs with interrupts off. Stack layout at entry: 490 * +----------------------------------------------------+ 491 * | regs->ss | 492 * | regs->rsp | 493 * | regs->eflags | 494 * | regs->cs | 495 * | regs->ip | 496 * +----------------------------------------------------+ 497 * | regs->orig_ax = ~(interrupt number) | 498 * +----------------------------------------------------+ 499 * | return address | 500 * +----------------------------------------------------+ 501 */ 502ENTRY(interrupt_entry) 503 UNWIND_HINT_FUNC 504 ASM_CLAC 505 cld 506 507 testb $3, CS-ORIG_RAX+8(%rsp) 508 jz 1f 509 SWAPGS 510 511 /* 512 * Switch to the thread stack. The IRET frame and orig_ax are 513 * on the stack, as well as the return address. RDI..R12 are 514 * not (yet) on the stack and space has not (yet) been 515 * allocated for them. 516 */ 517 pushq %rdi 518 519 /* Need to switch before accessing the thread stack. */ 520 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 521 movq %rsp, %rdi 522 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 523 524 /* 525 * We have RDI, return address, and orig_ax on the stack on 526 * top of the IRET frame. That means offset=24 527 */ 528 UNWIND_HINT_IRET_REGS base=%rdi offset=24 529 530 pushq 7*8(%rdi) /* regs->ss */ 531 pushq 6*8(%rdi) /* regs->rsp */ 532 pushq 5*8(%rdi) /* regs->eflags */ 533 pushq 4*8(%rdi) /* regs->cs */ 534 pushq 3*8(%rdi) /* regs->ip */ 535 pushq 2*8(%rdi) /* regs->orig_ax */ 536 pushq 8(%rdi) /* return address */ 537 UNWIND_HINT_FUNC 538 539 movq (%rdi), %rdi 5401: 541 542 PUSH_AND_CLEAR_REGS save_ret=1 543 ENCODE_FRAME_POINTER 8 544 545 testb $3, CS+8(%rsp) 546 jz 1f 547 548 /* 549 * IRQ from user mode. 550 * 551 * We need to tell lockdep that IRQs are off. We can't do this until 552 * we fix gsbase, and we should do it before enter_from_user_mode 553 * (which can take locks). Since TRACE_IRQS_OFF is idempotent, 554 * the simplest way to handle it is to just call it twice if 555 * we enter from user mode. There's no reason to optimize this since 556 * TRACE_IRQS_OFF is a no-op if lockdep is off. 557 */ 558 TRACE_IRQS_OFF 559 560 CALL_enter_from_user_mode 561 5621: 563 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 564 /* We entered an interrupt context - irqs are off: */ 565 TRACE_IRQS_OFF 566 567 ret 568END(interrupt_entry) 569_ASM_NOKPROBE(interrupt_entry) 570 571 572/* Interrupt entry/exit. */ 573 574 /* 575 * The interrupt stubs push (~vector+0x80) onto the stack and 576 * then jump to common_interrupt. 577 */ 578 .p2align CONFIG_X86_L1_CACHE_SHIFT 579common_interrupt: 580 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 581 call interrupt_entry 582 UNWIND_HINT_REGS indirect=1 583 call do_IRQ /* rdi points to pt_regs */ 584 /* 0(%rsp): old RSP */ 585ret_from_intr: 586 DISABLE_INTERRUPTS(CLBR_ANY) 587 TRACE_IRQS_OFF 588 589 LEAVE_IRQ_STACK 590 591 testb $3, CS(%rsp) 592 jz retint_kernel 593 594 /* Interrupt came from user space */ 595GLOBAL(retint_user) 596 mov %rsp,%rdi 597 call prepare_exit_to_usermode 598 TRACE_IRQS_IRETQ 599 600GLOBAL(swapgs_restore_regs_and_return_to_usermode) 601#ifdef CONFIG_DEBUG_ENTRY 602 /* Assert that pt_regs indicates user mode. */ 603 testb $3, CS(%rsp) 604 jnz 1f 605 ud2 6061: 607#endif 608 POP_REGS pop_rdi=0 609 610 /* 611 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 612 * Save old stack pointer and switch to trampoline stack. 613 */ 614 movq %rsp, %rdi 615 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 616 617 /* Copy the IRET frame to the trampoline stack. */ 618 pushq 6*8(%rdi) /* SS */ 619 pushq 5*8(%rdi) /* RSP */ 620 pushq 4*8(%rdi) /* EFLAGS */ 621 pushq 3*8(%rdi) /* CS */ 622 pushq 2*8(%rdi) /* RIP */ 623 624 /* Push user RDI on the trampoline stack. */ 625 pushq (%rdi) 626 627 /* 628 * We are on the trampoline stack. All regs except RDI are live. 629 * We can do future final exit work right here. 630 */ 631 STACKLEAK_ERASE_NOCLOBBER 632 633 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 634 635 /* Restore RDI. */ 636 popq %rdi 637 SWAPGS 638 INTERRUPT_RETURN 639 640 641/* Returning to kernel space */ 642retint_kernel: 643#ifdef CONFIG_PREEMPT 644 /* Interrupts are off */ 645 /* Check if we need preemption */ 646 btl $9, EFLAGS(%rsp) /* were interrupts off? */ 647 jnc 1f 648 cmpl $0, PER_CPU_VAR(__preempt_count) 649 jnz 1f 650 call preempt_schedule_irq 6511: 652#endif 653 /* 654 * The iretq could re-enable interrupts: 655 */ 656 TRACE_IRQS_IRETQ 657 658GLOBAL(restore_regs_and_return_to_kernel) 659#ifdef CONFIG_DEBUG_ENTRY 660 /* Assert that pt_regs indicates kernel mode. */ 661 testb $3, CS(%rsp) 662 jz 1f 663 ud2 6641: 665#endif 666 POP_REGS 667 addq $8, %rsp /* skip regs->orig_ax */ 668 /* 669 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 670 * when returning from IPI handler. 671 */ 672 INTERRUPT_RETURN 673 674ENTRY(native_iret) 675 UNWIND_HINT_IRET_REGS 676 /* 677 * Are we returning to a stack segment from the LDT? Note: in 678 * 64-bit mode SS:RSP on the exception stack is always valid. 679 */ 680#ifdef CONFIG_X86_ESPFIX64 681 testb $4, (SS-RIP)(%rsp) 682 jnz native_irq_return_ldt 683#endif 684 685.global native_irq_return_iret 686native_irq_return_iret: 687 /* 688 * This may fault. Non-paranoid faults on return to userspace are 689 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 690 * Double-faults due to espfix64 are handled in do_double_fault. 691 * Other faults here are fatal. 692 */ 693 iretq 694 695#ifdef CONFIG_X86_ESPFIX64 696native_irq_return_ldt: 697 /* 698 * We are running with user GSBASE. All GPRs contain their user 699 * values. We have a percpu ESPFIX stack that is eight slots 700 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 701 * of the ESPFIX stack. 702 * 703 * We clobber RAX and RDI in this code. We stash RDI on the 704 * normal stack and RAX on the ESPFIX stack. 705 * 706 * The ESPFIX stack layout we set up looks like this: 707 * 708 * --- top of ESPFIX stack --- 709 * SS 710 * RSP 711 * RFLAGS 712 * CS 713 * RIP <-- RSP points here when we're done 714 * RAX <-- espfix_waddr points here 715 * --- bottom of ESPFIX stack --- 716 */ 717 718 pushq %rdi /* Stash user RDI */ 719 SWAPGS /* to kernel GS */ 720 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 721 722 movq PER_CPU_VAR(espfix_waddr), %rdi 723 movq %rax, (0*8)(%rdi) /* user RAX */ 724 movq (1*8)(%rsp), %rax /* user RIP */ 725 movq %rax, (1*8)(%rdi) 726 movq (2*8)(%rsp), %rax /* user CS */ 727 movq %rax, (2*8)(%rdi) 728 movq (3*8)(%rsp), %rax /* user RFLAGS */ 729 movq %rax, (3*8)(%rdi) 730 movq (5*8)(%rsp), %rax /* user SS */ 731 movq %rax, (5*8)(%rdi) 732 movq (4*8)(%rsp), %rax /* user RSP */ 733 movq %rax, (4*8)(%rdi) 734 /* Now RAX == RSP. */ 735 736 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 737 738 /* 739 * espfix_stack[31:16] == 0. The page tables are set up such that 740 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 741 * espfix_waddr for any X. That is, there are 65536 RO aliases of 742 * the same page. Set up RSP so that RSP[31:16] contains the 743 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 744 * still points to an RO alias of the ESPFIX stack. 745 */ 746 orq PER_CPU_VAR(espfix_stack), %rax 747 748 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 749 SWAPGS /* to user GS */ 750 popq %rdi /* Restore user RDI */ 751 752 movq %rax, %rsp 753 UNWIND_HINT_IRET_REGS offset=8 754 755 /* 756 * At this point, we cannot write to the stack any more, but we can 757 * still read. 758 */ 759 popq %rax /* Restore user RAX */ 760 761 /* 762 * RSP now points to an ordinary IRET frame, except that the page 763 * is read-only and RSP[31:16] are preloaded with the userspace 764 * values. We can now IRET back to userspace. 765 */ 766 jmp native_irq_return_iret 767#endif 768END(common_interrupt) 769_ASM_NOKPROBE(common_interrupt) 770 771/* 772 * APIC interrupts. 773 */ 774.macro apicinterrupt3 num sym do_sym 775ENTRY(\sym) 776 UNWIND_HINT_IRET_REGS 777 pushq $~(\num) 778.Lcommon_\sym: 779 call interrupt_entry 780 UNWIND_HINT_REGS indirect=1 781 call \do_sym /* rdi points to pt_regs */ 782 jmp ret_from_intr 783END(\sym) 784_ASM_NOKPROBE(\sym) 785.endm 786 787/* Make sure APIC interrupt handlers end up in the irqentry section: */ 788#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 789#define POP_SECTION_IRQENTRY .popsection 790 791.macro apicinterrupt num sym do_sym 792PUSH_SECTION_IRQENTRY 793apicinterrupt3 \num \sym \do_sym 794POP_SECTION_IRQENTRY 795.endm 796 797#ifdef CONFIG_SMP 798apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 799apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 800#endif 801 802#ifdef CONFIG_X86_UV 803apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 804#endif 805 806apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 807apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 808 809#ifdef CONFIG_HAVE_KVM 810apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 811apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 812apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 813#endif 814 815#ifdef CONFIG_X86_MCE_THRESHOLD 816apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 817#endif 818 819#ifdef CONFIG_X86_MCE_AMD 820apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 821#endif 822 823#ifdef CONFIG_X86_THERMAL_VECTOR 824apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 825#endif 826 827#ifdef CONFIG_SMP 828apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 829apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 830apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 831#endif 832 833apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 834apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 835 836#ifdef CONFIG_IRQ_WORK 837apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 838#endif 839 840/* 841 * Exception entry points. 842 */ 843#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + (x) * 8) 844 845/** 846 * idtentry - Generate an IDT entry stub 847 * @sym: Name of the generated entry point 848 * @do_sym: C function to be called 849 * @has_error_code: True if this IDT vector has an error code on the stack 850 * @paranoid: non-zero means that this vector may be invoked from 851 * kernel mode with user GSBASE and/or user CR3. 852 * 2 is special -- see below. 853 * @shift_ist: Set to an IST index if entries from kernel mode should 854 * decrement the IST stack so that nested entries get a 855 * fresh stack. (This is for #DB, which has a nasty habit 856 * of recursing.) 857 * 858 * idtentry generates an IDT stub that sets up a usable kernel context, 859 * creates struct pt_regs, and calls @do_sym. The stub has the following 860 * special behaviors: 861 * 862 * On an entry from user mode, the stub switches from the trampoline or 863 * IST stack to the normal thread stack. On an exit to user mode, the 864 * normal exit-to-usermode path is invoked. 865 * 866 * On an exit to kernel mode, if @paranoid == 0, we check for preemption, 867 * whereas we omit the preemption check if @paranoid != 0. This is purely 868 * because the implementation is simpler this way. The kernel only needs 869 * to check for asynchronous kernel preemption when IRQ handlers return. 870 * 871 * If @paranoid == 0, then the stub will handle IRET faults by pretending 872 * that the fault came from user mode. It will handle gs_change faults by 873 * pretending that the fault happened with kernel GSBASE. Since this handling 874 * is omitted for @paranoid != 0, the #GP, #SS, and #NP stubs must have 875 * @paranoid == 0. This special handling will do the wrong thing for 876 * espfix-induced #DF on IRET, so #DF must not use @paranoid == 0. 877 * 878 * @paranoid == 2 is special: the stub will never switch stacks. This is for 879 * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS. 880 */ 881.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ist_offset=0 create_gap=0 882ENTRY(\sym) 883 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 884 885 /* Sanity check */ 886 .if \shift_ist != -1 && \paranoid == 0 887 .error "using shift_ist requires paranoid=1" 888 .endif 889 890 ASM_CLAC 891 892 .if \has_error_code == 0 893 pushq $-1 /* ORIG_RAX: no syscall to restart */ 894 .endif 895 896 .if \paranoid == 1 897 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ 898 jnz .Lfrom_usermode_switch_stack_\@ 899 .endif 900 901 .if \create_gap == 1 902 /* 903 * If coming from kernel space, create a 6-word gap to allow the 904 * int3 handler to emulate a call instruction. 905 */ 906 testb $3, CS-ORIG_RAX(%rsp) 907 jnz .Lfrom_usermode_no_gap_\@ 908 .rept 6 909 pushq 5*8(%rsp) 910 .endr 911 UNWIND_HINT_IRET_REGS offset=8 912.Lfrom_usermode_no_gap_\@: 913 .endif 914 915 .if \paranoid 916 call paranoid_entry 917 .else 918 call error_entry 919 .endif 920 UNWIND_HINT_REGS 921 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 922 923 .if \paranoid 924 .if \shift_ist != -1 925 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 926 .else 927 TRACE_IRQS_OFF 928 .endif 929 .endif 930 931 movq %rsp, %rdi /* pt_regs pointer */ 932 933 .if \has_error_code 934 movq ORIG_RAX(%rsp), %rsi /* get error code */ 935 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 936 .else 937 xorl %esi, %esi /* no error code */ 938 .endif 939 940 .if \shift_ist != -1 941 subq $\ist_offset, CPU_TSS_IST(\shift_ist) 942 .endif 943 944 call \do_sym 945 946 .if \shift_ist != -1 947 addq $\ist_offset, CPU_TSS_IST(\shift_ist) 948 .endif 949 950 /* these procedures expect "no swapgs" flag in ebx */ 951 .if \paranoid 952 jmp paranoid_exit 953 .else 954 jmp error_exit 955 .endif 956 957 .if \paranoid == 1 958 /* 959 * Entry from userspace. Switch stacks and treat it 960 * as a normal entry. This means that paranoid handlers 961 * run in real process context if user_mode(regs). 962 */ 963.Lfrom_usermode_switch_stack_\@: 964 call error_entry 965 966 movq %rsp, %rdi /* pt_regs pointer */ 967 968 .if \has_error_code 969 movq ORIG_RAX(%rsp), %rsi /* get error code */ 970 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 971 .else 972 xorl %esi, %esi /* no error code */ 973 .endif 974 975 call \do_sym 976 977 jmp error_exit 978 .endif 979_ASM_NOKPROBE(\sym) 980END(\sym) 981.endm 982 983idtentry divide_error do_divide_error has_error_code=0 984idtentry overflow do_overflow has_error_code=0 985idtentry bounds do_bounds has_error_code=0 986idtentry invalid_op do_invalid_op has_error_code=0 987idtentry device_not_available do_device_not_available has_error_code=0 988idtentry double_fault do_double_fault has_error_code=1 paranoid=2 989idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 990idtentry invalid_TSS do_invalid_TSS has_error_code=1 991idtentry segment_not_present do_segment_not_present has_error_code=1 992idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 993idtentry coprocessor_error do_coprocessor_error has_error_code=0 994idtentry alignment_check do_alignment_check has_error_code=1 995idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 996 997 998 /* 999 * Reload gs selector with exception handling 1000 * edi: new selector 1001 */ 1002ENTRY(native_load_gs_index) 1003 FRAME_BEGIN 1004 pushfq 1005 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1006 TRACE_IRQS_OFF 1007 SWAPGS 1008.Lgs_change: 1009 movl %edi, %gs 10102: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1011 SWAPGS 1012 TRACE_IRQS_FLAGS (%rsp) 1013 popfq 1014 FRAME_END 1015 ret 1016ENDPROC(native_load_gs_index) 1017EXPORT_SYMBOL(native_load_gs_index) 1018 1019 _ASM_EXTABLE(.Lgs_change, bad_gs) 1020 .section .fixup, "ax" 1021 /* running with kernelgs */ 1022bad_gs: 1023 SWAPGS /* switch back to user gs */ 1024.macro ZAP_GS 1025 /* This can't be a string because the preprocessor needs to see it. */ 1026 movl $__USER_DS, %eax 1027 movl %eax, %gs 1028.endm 1029 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1030 xorl %eax, %eax 1031 movl %eax, %gs 1032 jmp 2b 1033 .previous 1034 1035/* Call softirq on interrupt stack. Interrupts are off. */ 1036ENTRY(do_softirq_own_stack) 1037 pushq %rbp 1038 mov %rsp, %rbp 1039 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1040 call __do_softirq 1041 LEAVE_IRQ_STACK regs=0 1042 leaveq 1043 ret 1044ENDPROC(do_softirq_own_stack) 1045 1046#ifdef CONFIG_XEN_PV 1047idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1048 1049/* 1050 * A note on the "critical region" in our callback handler. 1051 * We want to avoid stacking callback handlers due to events occurring 1052 * during handling of the last event. To do this, we keep events disabled 1053 * until we've done all processing. HOWEVER, we must enable events before 1054 * popping the stack frame (can't be done atomically) and so it would still 1055 * be possible to get enough handler activations to overflow the stack. 1056 * Although unlikely, bugs of that kind are hard to track down, so we'd 1057 * like to avoid the possibility. 1058 * So, on entry to the handler we detect whether we interrupted an 1059 * existing activation in its critical region -- if so, we pop the current 1060 * activation and restart the handler using the previous one. 1061 */ 1062ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1063 1064/* 1065 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1066 * see the correct pointer to the pt_regs 1067 */ 1068 UNWIND_HINT_FUNC 1069 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1070 UNWIND_HINT_REGS 1071 1072 ENTER_IRQ_STACK old_rsp=%r10 1073 call xen_evtchn_do_upcall 1074 LEAVE_IRQ_STACK 1075 1076#ifndef CONFIG_PREEMPT 1077 call xen_maybe_preempt_hcall 1078#endif 1079 jmp error_exit 1080END(xen_do_hypervisor_callback) 1081 1082/* 1083 * Hypervisor uses this for application faults while it executes. 1084 * We get here for two reasons: 1085 * 1. Fault while reloading DS, ES, FS or GS 1086 * 2. Fault while executing IRET 1087 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1088 * registers that could be reloaded and zeroed the others. 1089 * Category 2 we fix up by killing the current process. We cannot use the 1090 * normal Linux return path in this case because if we use the IRET hypercall 1091 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1092 * We distinguish between categories by comparing each saved segment register 1093 * with its current contents: any discrepancy means we in category 1. 1094 */ 1095ENTRY(xen_failsafe_callback) 1096 UNWIND_HINT_EMPTY 1097 movl %ds, %ecx 1098 cmpw %cx, 0x10(%rsp) 1099 jne 1f 1100 movl %es, %ecx 1101 cmpw %cx, 0x18(%rsp) 1102 jne 1f 1103 movl %fs, %ecx 1104 cmpw %cx, 0x20(%rsp) 1105 jne 1f 1106 movl %gs, %ecx 1107 cmpw %cx, 0x28(%rsp) 1108 jne 1f 1109 /* All segments match their saved values => Category 2 (Bad IRET). */ 1110 movq (%rsp), %rcx 1111 movq 8(%rsp), %r11 1112 addq $0x30, %rsp 1113 pushq $0 /* RIP */ 1114 UNWIND_HINT_IRET_REGS offset=8 1115 jmp general_protection 11161: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1117 movq (%rsp), %rcx 1118 movq 8(%rsp), %r11 1119 addq $0x30, %rsp 1120 UNWIND_HINT_IRET_REGS 1121 pushq $-1 /* orig_ax = -1 => not a system call */ 1122 PUSH_AND_CLEAR_REGS 1123 ENCODE_FRAME_POINTER 1124 jmp error_exit 1125END(xen_failsafe_callback) 1126#endif /* CONFIG_XEN_PV */ 1127 1128#ifdef CONFIG_XEN_PVHVM 1129apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1130 xen_hvm_callback_vector xen_evtchn_do_upcall 1131#endif 1132 1133 1134#if IS_ENABLED(CONFIG_HYPERV) 1135apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1136 hyperv_callback_vector hyperv_vector_handler 1137 1138apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1139 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1140 1141apicinterrupt3 HYPERV_STIMER0_VECTOR \ 1142 hv_stimer0_callback_vector hv_stimer0_vector_handler 1143#endif /* CONFIG_HYPERV */ 1144 1145idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=IST_INDEX_DB ist_offset=DB_STACK_OFFSET 1146idtentry int3 do_int3 has_error_code=0 create_gap=1 1147idtentry stack_segment do_stack_segment has_error_code=1 1148 1149#ifdef CONFIG_XEN_PV 1150idtentry xennmi do_nmi has_error_code=0 1151idtentry xendebug do_debug has_error_code=0 1152idtentry xenint3 do_int3 has_error_code=0 1153#endif 1154 1155idtentry general_protection do_general_protection has_error_code=1 1156idtentry page_fault do_page_fault has_error_code=1 1157 1158#ifdef CONFIG_KVM_GUEST 1159idtentry async_page_fault do_async_page_fault has_error_code=1 1160#endif 1161 1162#ifdef CONFIG_X86_MCE 1163idtentry machine_check do_mce has_error_code=0 paranoid=1 1164#endif 1165 1166/* 1167 * Save all registers in pt_regs, and switch gs if needed. 1168 * Use slow, but surefire "are we in kernel?" check. 1169 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1170 */ 1171ENTRY(paranoid_entry) 1172 UNWIND_HINT_FUNC 1173 cld 1174 PUSH_AND_CLEAR_REGS save_ret=1 1175 ENCODE_FRAME_POINTER 8 1176 movl $1, %ebx 1177 movl $MSR_GS_BASE, %ecx 1178 rdmsr 1179 testl %edx, %edx 1180 js 1f /* negative -> in kernel */ 1181 SWAPGS 1182 xorl %ebx, %ebx 1183 11841: 1185 /* 1186 * Always stash CR3 in %r14. This value will be restored, 1187 * verbatim, at exit. Needed if paranoid_entry interrupted 1188 * another entry that already switched to the user CR3 value 1189 * but has not yet returned to userspace. 1190 * 1191 * This is also why CS (stashed in the "iret frame" by the 1192 * hardware at entry) can not be used: this may be a return 1193 * to kernel code, but with a user CR3 value. 1194 */ 1195 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1196 1197 ret 1198END(paranoid_entry) 1199 1200/* 1201 * "Paranoid" exit path from exception stack. This is invoked 1202 * only on return from non-NMI IST interrupts that came 1203 * from kernel space. 1204 * 1205 * We may be returning to very strange contexts (e.g. very early 1206 * in syscall entry), so checking for preemption here would 1207 * be complicated. Fortunately, we there's no good reason 1208 * to try to handle preemption here. 1209 * 1210 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1211 */ 1212ENTRY(paranoid_exit) 1213 UNWIND_HINT_REGS 1214 DISABLE_INTERRUPTS(CLBR_ANY) 1215 TRACE_IRQS_OFF_DEBUG 1216 testl %ebx, %ebx /* swapgs needed? */ 1217 jnz .Lparanoid_exit_no_swapgs 1218 TRACE_IRQS_IRETQ 1219 /* Always restore stashed CR3 value (see paranoid_entry) */ 1220 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1221 SWAPGS_UNSAFE_STACK 1222 jmp .Lparanoid_exit_restore 1223.Lparanoid_exit_no_swapgs: 1224 TRACE_IRQS_IRETQ_DEBUG 1225 /* Always restore stashed CR3 value (see paranoid_entry) */ 1226 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1227.Lparanoid_exit_restore: 1228 jmp restore_regs_and_return_to_kernel 1229END(paranoid_exit) 1230 1231/* 1232 * Save all registers in pt_regs, and switch GS if needed. 1233 */ 1234ENTRY(error_entry) 1235 UNWIND_HINT_FUNC 1236 cld 1237 PUSH_AND_CLEAR_REGS save_ret=1 1238 ENCODE_FRAME_POINTER 8 1239 testb $3, CS+8(%rsp) 1240 jz .Lerror_kernelspace 1241 1242 /* 1243 * We entered from user mode or we're pretending to have entered 1244 * from user mode due to an IRET fault. 1245 */ 1246 SWAPGS 1247 /* We have user CR3. Change to kernel CR3. */ 1248 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1249 1250.Lerror_entry_from_usermode_after_swapgs: 1251 /* Put us onto the real thread stack. */ 1252 popq %r12 /* save return addr in %12 */ 1253 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1254 call sync_regs 1255 movq %rax, %rsp /* switch stack */ 1256 ENCODE_FRAME_POINTER 1257 pushq %r12 1258 1259 /* 1260 * We need to tell lockdep that IRQs are off. We can't do this until 1261 * we fix gsbase, and we should do it before enter_from_user_mode 1262 * (which can take locks). 1263 */ 1264 TRACE_IRQS_OFF 1265 CALL_enter_from_user_mode 1266 ret 1267 1268.Lerror_entry_done: 1269 TRACE_IRQS_OFF 1270 ret 1271 1272 /* 1273 * There are two places in the kernel that can potentially fault with 1274 * usergs. Handle them here. B stepping K8s sometimes report a 1275 * truncated RIP for IRET exceptions returning to compat mode. Check 1276 * for these here too. 1277 */ 1278.Lerror_kernelspace: 1279 leaq native_irq_return_iret(%rip), %rcx 1280 cmpq %rcx, RIP+8(%rsp) 1281 je .Lerror_bad_iret 1282 movl %ecx, %eax /* zero extend */ 1283 cmpq %rax, RIP+8(%rsp) 1284 je .Lbstep_iret 1285 cmpq $.Lgs_change, RIP+8(%rsp) 1286 jne .Lerror_entry_done 1287 1288 /* 1289 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1290 * gsbase and proceed. We'll fix up the exception and land in 1291 * .Lgs_change's error handler with kernel gsbase. 1292 */ 1293 SWAPGS 1294 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1295 jmp .Lerror_entry_done 1296 1297.Lbstep_iret: 1298 /* Fix truncated RIP */ 1299 movq %rcx, RIP+8(%rsp) 1300 /* fall through */ 1301 1302.Lerror_bad_iret: 1303 /* 1304 * We came from an IRET to user mode, so we have user 1305 * gsbase and CR3. Switch to kernel gsbase and CR3: 1306 */ 1307 SWAPGS 1308 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1309 1310 /* 1311 * Pretend that the exception came from user mode: set up pt_regs 1312 * as if we faulted immediately after IRET. 1313 */ 1314 mov %rsp, %rdi 1315 call fixup_bad_iret 1316 mov %rax, %rsp 1317 jmp .Lerror_entry_from_usermode_after_swapgs 1318END(error_entry) 1319 1320ENTRY(error_exit) 1321 UNWIND_HINT_REGS 1322 DISABLE_INTERRUPTS(CLBR_ANY) 1323 TRACE_IRQS_OFF 1324 testb $3, CS(%rsp) 1325 jz retint_kernel 1326 jmp retint_user 1327END(error_exit) 1328 1329/* 1330 * Runs on exception stack. Xen PV does not go through this path at all, 1331 * so we can use real assembly here. 1332 * 1333 * Registers: 1334 * %r14: Used to save/restore the CR3 of the interrupted context 1335 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1336 */ 1337ENTRY(nmi) 1338 UNWIND_HINT_IRET_REGS 1339 1340 /* 1341 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1342 * the iretq it performs will take us out of NMI context. 1343 * This means that we can have nested NMIs where the next 1344 * NMI is using the top of the stack of the previous NMI. We 1345 * can't let it execute because the nested NMI will corrupt the 1346 * stack of the previous NMI. NMI handlers are not re-entrant 1347 * anyway. 1348 * 1349 * To handle this case we do the following: 1350 * Check the a special location on the stack that contains 1351 * a variable that is set when NMIs are executing. 1352 * The interrupted task's stack is also checked to see if it 1353 * is an NMI stack. 1354 * If the variable is not set and the stack is not the NMI 1355 * stack then: 1356 * o Set the special variable on the stack 1357 * o Copy the interrupt frame into an "outermost" location on the 1358 * stack 1359 * o Copy the interrupt frame into an "iret" location on the stack 1360 * o Continue processing the NMI 1361 * If the variable is set or the previous stack is the NMI stack: 1362 * o Modify the "iret" location to jump to the repeat_nmi 1363 * o return back to the first NMI 1364 * 1365 * Now on exit of the first NMI, we first clear the stack variable 1366 * The NMI stack will tell any nested NMIs at that point that it is 1367 * nested. Then we pop the stack normally with iret, and if there was 1368 * a nested NMI that updated the copy interrupt stack frame, a 1369 * jump will be made to the repeat_nmi code that will handle the second 1370 * NMI. 1371 * 1372 * However, espfix prevents us from directly returning to userspace 1373 * with a single IRET instruction. Similarly, IRET to user mode 1374 * can fault. We therefore handle NMIs from user space like 1375 * other IST entries. 1376 */ 1377 1378 ASM_CLAC 1379 1380 /* Use %rdx as our temp variable throughout */ 1381 pushq %rdx 1382 1383 testb $3, CS-RIP+8(%rsp) 1384 jz .Lnmi_from_kernel 1385 1386 /* 1387 * NMI from user mode. We need to run on the thread stack, but we 1388 * can't go through the normal entry paths: NMIs are masked, and 1389 * we don't want to enable interrupts, because then we'll end 1390 * up in an awkward situation in which IRQs are on but NMIs 1391 * are off. 1392 * 1393 * We also must not push anything to the stack before switching 1394 * stacks lest we corrupt the "NMI executing" variable. 1395 */ 1396 1397 swapgs 1398 cld 1399 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1400 movq %rsp, %rdx 1401 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1402 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1403 pushq 5*8(%rdx) /* pt_regs->ss */ 1404 pushq 4*8(%rdx) /* pt_regs->rsp */ 1405 pushq 3*8(%rdx) /* pt_regs->flags */ 1406 pushq 2*8(%rdx) /* pt_regs->cs */ 1407 pushq 1*8(%rdx) /* pt_regs->rip */ 1408 UNWIND_HINT_IRET_REGS 1409 pushq $-1 /* pt_regs->orig_ax */ 1410 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1411 ENCODE_FRAME_POINTER 1412 1413 /* 1414 * At this point we no longer need to worry about stack damage 1415 * due to nesting -- we're on the normal thread stack and we're 1416 * done with the NMI stack. 1417 */ 1418 1419 movq %rsp, %rdi 1420 movq $-1, %rsi 1421 call do_nmi 1422 1423 /* 1424 * Return back to user mode. We must *not* do the normal exit 1425 * work, because we don't want to enable interrupts. 1426 */ 1427 jmp swapgs_restore_regs_and_return_to_usermode 1428 1429.Lnmi_from_kernel: 1430 /* 1431 * Here's what our stack frame will look like: 1432 * +---------------------------------------------------------+ 1433 * | original SS | 1434 * | original Return RSP | 1435 * | original RFLAGS | 1436 * | original CS | 1437 * | original RIP | 1438 * +---------------------------------------------------------+ 1439 * | temp storage for rdx | 1440 * +---------------------------------------------------------+ 1441 * | "NMI executing" variable | 1442 * +---------------------------------------------------------+ 1443 * | iret SS } Copied from "outermost" frame | 1444 * | iret Return RSP } on each loop iteration; overwritten | 1445 * | iret RFLAGS } by a nested NMI to force another | 1446 * | iret CS } iteration if needed. | 1447 * | iret RIP } | 1448 * +---------------------------------------------------------+ 1449 * | outermost SS } initialized in first_nmi; | 1450 * | outermost Return RSP } will not be changed before | 1451 * | outermost RFLAGS } NMI processing is done. | 1452 * | outermost CS } Copied to "iret" frame on each | 1453 * | outermost RIP } iteration. | 1454 * +---------------------------------------------------------+ 1455 * | pt_regs | 1456 * +---------------------------------------------------------+ 1457 * 1458 * The "original" frame is used by hardware. Before re-enabling 1459 * NMIs, we need to be done with it, and we need to leave enough 1460 * space for the asm code here. 1461 * 1462 * We return by executing IRET while RSP points to the "iret" frame. 1463 * That will either return for real or it will loop back into NMI 1464 * processing. 1465 * 1466 * The "outermost" frame is copied to the "iret" frame on each 1467 * iteration of the loop, so each iteration starts with the "iret" 1468 * frame pointing to the final return target. 1469 */ 1470 1471 /* 1472 * Determine whether we're a nested NMI. 1473 * 1474 * If we interrupted kernel code between repeat_nmi and 1475 * end_repeat_nmi, then we are a nested NMI. We must not 1476 * modify the "iret" frame because it's being written by 1477 * the outer NMI. That's okay; the outer NMI handler is 1478 * about to about to call do_nmi anyway, so we can just 1479 * resume the outer NMI. 1480 */ 1481 1482 movq $repeat_nmi, %rdx 1483 cmpq 8(%rsp), %rdx 1484 ja 1f 1485 movq $end_repeat_nmi, %rdx 1486 cmpq 8(%rsp), %rdx 1487 ja nested_nmi_out 14881: 1489 1490 /* 1491 * Now check "NMI executing". If it's set, then we're nested. 1492 * This will not detect if we interrupted an outer NMI just 1493 * before IRET. 1494 */ 1495 cmpl $1, -8(%rsp) 1496 je nested_nmi 1497 1498 /* 1499 * Now test if the previous stack was an NMI stack. This covers 1500 * the case where we interrupt an outer NMI after it clears 1501 * "NMI executing" but before IRET. We need to be careful, though: 1502 * there is one case in which RSP could point to the NMI stack 1503 * despite there being no NMI active: naughty userspace controls 1504 * RSP at the very beginning of the SYSCALL targets. We can 1505 * pull a fast one on naughty userspace, though: we program 1506 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1507 * if it controls the kernel's RSP. We set DF before we clear 1508 * "NMI executing". 1509 */ 1510 lea 6*8(%rsp), %rdx 1511 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1512 cmpq %rdx, 4*8(%rsp) 1513 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1514 ja first_nmi 1515 1516 subq $EXCEPTION_STKSZ, %rdx 1517 cmpq %rdx, 4*8(%rsp) 1518 /* If it is below the NMI stack, it is a normal NMI */ 1519 jb first_nmi 1520 1521 /* Ah, it is within the NMI stack. */ 1522 1523 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1524 jz first_nmi /* RSP was user controlled. */ 1525 1526 /* This is a nested NMI. */ 1527 1528nested_nmi: 1529 /* 1530 * Modify the "iret" frame to point to repeat_nmi, forcing another 1531 * iteration of NMI handling. 1532 */ 1533 subq $8, %rsp 1534 leaq -10*8(%rsp), %rdx 1535 pushq $__KERNEL_DS 1536 pushq %rdx 1537 pushfq 1538 pushq $__KERNEL_CS 1539 pushq $repeat_nmi 1540 1541 /* Put stack back */ 1542 addq $(6*8), %rsp 1543 1544nested_nmi_out: 1545 popq %rdx 1546 1547 /* We are returning to kernel mode, so this cannot result in a fault. */ 1548 iretq 1549 1550first_nmi: 1551 /* Restore rdx. */ 1552 movq (%rsp), %rdx 1553 1554 /* Make room for "NMI executing". */ 1555 pushq $0 1556 1557 /* Leave room for the "iret" frame */ 1558 subq $(5*8), %rsp 1559 1560 /* Copy the "original" frame to the "outermost" frame */ 1561 .rept 5 1562 pushq 11*8(%rsp) 1563 .endr 1564 UNWIND_HINT_IRET_REGS 1565 1566 /* Everything up to here is safe from nested NMIs */ 1567 1568#ifdef CONFIG_DEBUG_ENTRY 1569 /* 1570 * For ease of testing, unmask NMIs right away. Disabled by 1571 * default because IRET is very expensive. 1572 */ 1573 pushq $0 /* SS */ 1574 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1575 addq $8, (%rsp) /* Fix up RSP */ 1576 pushfq /* RFLAGS */ 1577 pushq $__KERNEL_CS /* CS */ 1578 pushq $1f /* RIP */ 1579 iretq /* continues at repeat_nmi below */ 1580 UNWIND_HINT_IRET_REGS 15811: 1582#endif 1583 1584repeat_nmi: 1585 /* 1586 * If there was a nested NMI, the first NMI's iret will return 1587 * here. But NMIs are still enabled and we can take another 1588 * nested NMI. The nested NMI checks the interrupted RIP to see 1589 * if it is between repeat_nmi and end_repeat_nmi, and if so 1590 * it will just return, as we are about to repeat an NMI anyway. 1591 * This makes it safe to copy to the stack frame that a nested 1592 * NMI will update. 1593 * 1594 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1595 * we're repeating an NMI, gsbase has the same value that it had on 1596 * the first iteration. paranoid_entry will load the kernel 1597 * gsbase if needed before we call do_nmi. "NMI executing" 1598 * is zero. 1599 */ 1600 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1601 1602 /* 1603 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1604 * here must not modify the "iret" frame while we're writing to 1605 * it or it will end up containing garbage. 1606 */ 1607 addq $(10*8), %rsp 1608 .rept 5 1609 pushq -6*8(%rsp) 1610 .endr 1611 subq $(5*8), %rsp 1612end_repeat_nmi: 1613 1614 /* 1615 * Everything below this point can be preempted by a nested NMI. 1616 * If this happens, then the inner NMI will change the "iret" 1617 * frame to point back to repeat_nmi. 1618 */ 1619 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1620 1621 /* 1622 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1623 * as we should not be calling schedule in NMI context. 1624 * Even with normal interrupts enabled. An NMI should not be 1625 * setting NEED_RESCHED or anything that normal interrupts and 1626 * exceptions might do. 1627 */ 1628 call paranoid_entry 1629 UNWIND_HINT_REGS 1630 1631 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1632 movq %rsp, %rdi 1633 movq $-1, %rsi 1634 call do_nmi 1635 1636 /* Always restore stashed CR3 value (see paranoid_entry) */ 1637 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1638 1639 testl %ebx, %ebx /* swapgs needed? */ 1640 jnz nmi_restore 1641nmi_swapgs: 1642 SWAPGS_UNSAFE_STACK 1643nmi_restore: 1644 POP_REGS 1645 1646 /* 1647 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1648 * at the "iret" frame. 1649 */ 1650 addq $6*8, %rsp 1651 1652 /* 1653 * Clear "NMI executing". Set DF first so that we can easily 1654 * distinguish the remaining code between here and IRET from 1655 * the SYSCALL entry and exit paths. 1656 * 1657 * We arguably should just inspect RIP instead, but I (Andy) wrote 1658 * this code when I had the misapprehension that Xen PV supported 1659 * NMIs, and Xen PV would break that approach. 1660 */ 1661 std 1662 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1663 1664 /* 1665 * iretq reads the "iret" frame and exits the NMI stack in a 1666 * single instruction. We are returning to kernel mode, so this 1667 * cannot result in a fault. Similarly, we don't need to worry 1668 * about espfix64 on the way back to kernel mode. 1669 */ 1670 iretq 1671END(nmi) 1672 1673ENTRY(ignore_sysret) 1674 UNWIND_HINT_EMPTY 1675 mov $-ENOSYS, %eax 1676 sysret 1677END(ignore_sysret) 1678 1679ENTRY(rewind_stack_do_exit) 1680 UNWIND_HINT_FUNC 1681 /* Prevent any naive code from trying to unwind to our caller. */ 1682 xorl %ebp, %ebp 1683 1684 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1685 leaq -PTREGS_SIZE(%rax), %rsp 1686 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1687 1688 call do_exit 1689END(rewind_stack_do_exit) 1690