1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 1991,1992 Linus Torvalds 4 * 5 * entry_32.S contains the system-call and low-level fault and trap handling routines. 6 * 7 * Stack layout while running C code: 8 * ptrace needs to have all registers on the stack. 9 * If the order here is changed, it needs to be 10 * updated in fork.c:copy_process(), signal.c:do_signal(), 11 * ptrace.c and ptrace.h 12 * 13 * 0(%esp) - %ebx 14 * 4(%esp) - %ecx 15 * 8(%esp) - %edx 16 * C(%esp) - %esi 17 * 10(%esp) - %edi 18 * 14(%esp) - %ebp 19 * 18(%esp) - %eax 20 * 1C(%esp) - %ds 21 * 20(%esp) - %es 22 * 24(%esp) - %fs 23 * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS 24 * 2C(%esp) - orig_eax 25 * 30(%esp) - %eip 26 * 34(%esp) - %cs 27 * 38(%esp) - %eflags 28 * 3C(%esp) - %oldesp 29 * 40(%esp) - %oldss 30 */ 31 32#include <linux/linkage.h> 33#include <linux/err.h> 34#include <asm/thread_info.h> 35#include <asm/irqflags.h> 36#include <asm/errno.h> 37#include <asm/segment.h> 38#include <asm/smp.h> 39#include <asm/percpu.h> 40#include <asm/processor-flags.h> 41#include <asm/irq_vectors.h> 42#include <asm/cpufeatures.h> 43#include <asm/alternative-asm.h> 44#include <asm/asm.h> 45#include <asm/smap.h> 46#include <asm/frame.h> 47#include <asm/nospec-branch.h> 48 49 .section .entry.text, "ax" 50 51/* 52 * We use macros for low-level operations which need to be overridden 53 * for paravirtualization. The following will never clobber any registers: 54 * INTERRUPT_RETURN (aka. "iret") 55 * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax") 56 * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit"). 57 * 58 * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must 59 * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY). 60 * Allowing a register to be clobbered can shrink the paravirt replacement 61 * enough to patch inline, increasing performance. 62 */ 63 64#ifdef CONFIG_PREEMPT 65# define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF 66#else 67# define preempt_stop(clobbers) 68# define resume_kernel restore_all_kernel 69#endif 70 71.macro TRACE_IRQS_IRET 72#ifdef CONFIG_TRACE_IRQFLAGS 73 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off? 74 jz 1f 75 TRACE_IRQS_ON 761: 77#endif 78.endm 79 80#define PTI_SWITCH_MASK (1 << PAGE_SHIFT) 81 82/* 83 * User gs save/restore 84 * 85 * %gs is used for userland TLS and kernel only uses it for stack 86 * canary which is required to be at %gs:20 by gcc. Read the comment 87 * at the top of stackprotector.h for more info. 88 * 89 * Local labels 98 and 99 are used. 90 */ 91#ifdef CONFIG_X86_32_LAZY_GS 92 93 /* unfortunately push/pop can't be no-op */ 94.macro PUSH_GS 95 pushl $0 96.endm 97.macro POP_GS pop=0 98 addl $(4 + \pop), %esp 99.endm 100.macro POP_GS_EX 101.endm 102 103 /* all the rest are no-op */ 104.macro PTGS_TO_GS 105.endm 106.macro PTGS_TO_GS_EX 107.endm 108.macro GS_TO_REG reg 109.endm 110.macro REG_TO_PTGS reg 111.endm 112.macro SET_KERNEL_GS reg 113.endm 114 115#else /* CONFIG_X86_32_LAZY_GS */ 116 117.macro PUSH_GS 118 pushl %gs 119.endm 120 121.macro POP_GS pop=0 12298: popl %gs 123 .if \pop <> 0 124 add $\pop, %esp 125 .endif 126.endm 127.macro POP_GS_EX 128.pushsection .fixup, "ax" 12999: movl $0, (%esp) 130 jmp 98b 131.popsection 132 _ASM_EXTABLE(98b, 99b) 133.endm 134 135.macro PTGS_TO_GS 13698: mov PT_GS(%esp), %gs 137.endm 138.macro PTGS_TO_GS_EX 139.pushsection .fixup, "ax" 14099: movl $0, PT_GS(%esp) 141 jmp 98b 142.popsection 143 _ASM_EXTABLE(98b, 99b) 144.endm 145 146.macro GS_TO_REG reg 147 movl %gs, \reg 148.endm 149.macro REG_TO_PTGS reg 150 movl \reg, PT_GS(%esp) 151.endm 152.macro SET_KERNEL_GS reg 153 movl $(__KERNEL_STACK_CANARY), \reg 154 movl \reg, %gs 155.endm 156 157#endif /* CONFIG_X86_32_LAZY_GS */ 158 159/* Unconditionally switch to user cr3 */ 160.macro SWITCH_TO_USER_CR3 scratch_reg:req 161 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 162 163 movl %cr3, \scratch_reg 164 orl $PTI_SWITCH_MASK, \scratch_reg 165 movl \scratch_reg, %cr3 166.Lend_\@: 167.endm 168 169.macro BUG_IF_WRONG_CR3 no_user_check=0 170#ifdef CONFIG_DEBUG_ENTRY 171 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 172 .if \no_user_check == 0 173 /* coming from usermode? */ 174 testl $SEGMENT_RPL_MASK, PT_CS(%esp) 175 jz .Lend_\@ 176 .endif 177 /* On user-cr3? */ 178 movl %cr3, %eax 179 testl $PTI_SWITCH_MASK, %eax 180 jnz .Lend_\@ 181 /* From userspace with kernel cr3 - BUG */ 182 ud2 183.Lend_\@: 184#endif 185.endm 186 187/* 188 * Switch to kernel cr3 if not already loaded and return current cr3 in 189 * \scratch_reg 190 */ 191.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 192 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 193 movl %cr3, \scratch_reg 194 /* Test if we are already on kernel CR3 */ 195 testl $PTI_SWITCH_MASK, \scratch_reg 196 jz .Lend_\@ 197 andl $(~PTI_SWITCH_MASK), \scratch_reg 198 movl \scratch_reg, %cr3 199 /* Return original CR3 in \scratch_reg */ 200 orl $PTI_SWITCH_MASK, \scratch_reg 201.Lend_\@: 202.endm 203 204.macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 205 cld 206 PUSH_GS 207 pushl %fs 208 pushl %es 209 pushl %ds 210 pushl \pt_regs_ax 211 pushl %ebp 212 pushl %edi 213 pushl %esi 214 pushl %edx 215 pushl %ecx 216 pushl %ebx 217 movl $(__USER_DS), %edx 218 movl %edx, %ds 219 movl %edx, %es 220 movl $(__KERNEL_PERCPU), %edx 221 movl %edx, %fs 222 SET_KERNEL_GS %edx 223 224 /* Switch to kernel stack if necessary */ 225.if \switch_stacks > 0 226 SWITCH_TO_KERNEL_STACK 227.endif 228 229.endm 230 231.macro SAVE_ALL_NMI cr3_reg:req 232 SAVE_ALL 233 234 BUG_IF_WRONG_CR3 235 236 /* 237 * Now switch the CR3 when PTI is enabled. 238 * 239 * We can enter with either user or kernel cr3, the code will 240 * store the old cr3 in \cr3_reg and switches to the kernel cr3 241 * if necessary. 242 */ 243 SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg 244 245.Lend_\@: 246.endm 247 248/* 249 * This is a sneaky trick to help the unwinder find pt_regs on the stack. The 250 * frame pointer is replaced with an encoded pointer to pt_regs. The encoding 251 * is just clearing the MSB, which makes it an invalid stack address and is also 252 * a signal to the unwinder that it's a pt_regs pointer in disguise. 253 * 254 * NOTE: This macro must be used *after* SAVE_ALL because it corrupts the 255 * original rbp. 256 */ 257.macro ENCODE_FRAME_POINTER 258#ifdef CONFIG_FRAME_POINTER 259 mov %esp, %ebp 260 andl $0x7fffffff, %ebp 261#endif 262.endm 263 264.macro RESTORE_INT_REGS 265 popl %ebx 266 popl %ecx 267 popl %edx 268 popl %esi 269 popl %edi 270 popl %ebp 271 popl %eax 272.endm 273 274.macro RESTORE_REGS pop=0 275 RESTORE_INT_REGS 2761: popl %ds 2772: popl %es 2783: popl %fs 279 POP_GS \pop 280.pushsection .fixup, "ax" 2814: movl $0, (%esp) 282 jmp 1b 2835: movl $0, (%esp) 284 jmp 2b 2856: movl $0, (%esp) 286 jmp 3b 287.popsection 288 _ASM_EXTABLE(1b, 4b) 289 _ASM_EXTABLE(2b, 5b) 290 _ASM_EXTABLE(3b, 6b) 291 POP_GS_EX 292.endm 293 294.macro RESTORE_ALL_NMI cr3_reg:req pop=0 295 /* 296 * Now switch the CR3 when PTI is enabled. 297 * 298 * We enter with kernel cr3 and switch the cr3 to the value 299 * stored on \cr3_reg, which is either a user or a kernel cr3. 300 */ 301 ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI 302 303 testl $PTI_SWITCH_MASK, \cr3_reg 304 jz .Lswitched_\@ 305 306 /* User cr3 in \cr3_reg - write it to hardware cr3 */ 307 movl \cr3_reg, %cr3 308 309.Lswitched_\@: 310 311 BUG_IF_WRONG_CR3 312 313 RESTORE_REGS pop=\pop 314.endm 315 316.macro CHECK_AND_APPLY_ESPFIX 317#ifdef CONFIG_X86_ESPFIX32 318#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) 319 320 ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX 321 322 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS 323 /* 324 * Warning: PT_OLDSS(%esp) contains the wrong/random values if we 325 * are returning to the kernel. 326 * See comments in process.c:copy_thread() for details. 327 */ 328 movb PT_OLDSS(%esp), %ah 329 movb PT_CS(%esp), %al 330 andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax 331 cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax 332 jne .Lend_\@ # returning to user-space with LDT SS 333 334 /* 335 * Setup and switch to ESPFIX stack 336 * 337 * We're returning to userspace with a 16 bit stack. The CPU will not 338 * restore the high word of ESP for us on executing iret... This is an 339 * "official" bug of all the x86-compatible CPUs, which we can work 340 * around to make dosemu and wine happy. We do this by preloading the 341 * high word of ESP with the high word of the userspace ESP while 342 * compensating for the offset by changing to the ESPFIX segment with 343 * a base address that matches for the difference. 344 */ 345 mov %esp, %edx /* load kernel esp */ 346 mov PT_OLDESP(%esp), %eax /* load userspace esp */ 347 mov %dx, %ax /* eax: new kernel esp */ 348 sub %eax, %edx /* offset (low word is 0) */ 349 shr $16, %edx 350 mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ 351 mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ 352 pushl $__ESPFIX_SS 353 pushl %eax /* new kernel esp */ 354 /* 355 * Disable interrupts, but do not irqtrace this section: we 356 * will soon execute iret and the tracer was already set to 357 * the irqstate after the IRET: 358 */ 359 DISABLE_INTERRUPTS(CLBR_ANY) 360 lss (%esp), %esp /* switch to espfix segment */ 361.Lend_\@: 362#endif /* CONFIG_X86_ESPFIX32 */ 363.endm 364 365/* 366 * Called with pt_regs fully populated and kernel segments loaded, 367 * so we can access PER_CPU and use the integer registers. 368 * 369 * We need to be very careful here with the %esp switch, because an NMI 370 * can happen everywhere. If the NMI handler finds itself on the 371 * entry-stack, it will overwrite the task-stack and everything we 372 * copied there. So allocate the stack-frame on the task-stack and 373 * switch to it before we do any copying. 374 */ 375 376#define CS_FROM_ENTRY_STACK (1 << 31) 377#define CS_FROM_USER_CR3 (1 << 30) 378 379.macro SWITCH_TO_KERNEL_STACK 380 381 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV 382 383 BUG_IF_WRONG_CR3 384 385 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax 386 387 /* 388 * %eax now contains the entry cr3 and we carry it forward in 389 * that register for the time this macro runs 390 */ 391 392 /* Are we on the entry stack? Bail out if not! */ 393 movl PER_CPU_VAR(cpu_entry_area), %ecx 394 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx 395 subl %esp, %ecx /* ecx = (end of entry_stack) - esp */ 396 cmpl $SIZEOF_entry_stack, %ecx 397 jae .Lend_\@ 398 399 /* Load stack pointer into %esi and %edi */ 400 movl %esp, %esi 401 movl %esi, %edi 402 403 /* Move %edi to the top of the entry stack */ 404 andl $(MASK_entry_stack), %edi 405 addl $(SIZEOF_entry_stack), %edi 406 407 /* Load top of task-stack into %edi */ 408 movl TSS_entry2task_stack(%edi), %edi 409 410 /* 411 * Clear unused upper bits of the dword containing the word-sized CS 412 * slot in pt_regs in case hardware didn't clear it for us. 413 */ 414 andl $(0x0000ffff), PT_CS(%esp) 415 416 /* Special case - entry from kernel mode via entry stack */ 417#ifdef CONFIG_VM86 418 movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS 419 movb PT_CS(%esp), %cl 420 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx 421#else 422 movl PT_CS(%esp), %ecx 423 andl $SEGMENT_RPL_MASK, %ecx 424#endif 425 cmpl $USER_RPL, %ecx 426 jb .Lentry_from_kernel_\@ 427 428 /* Bytes to copy */ 429 movl $PTREGS_SIZE, %ecx 430 431#ifdef CONFIG_VM86 432 testl $X86_EFLAGS_VM, PT_EFLAGS(%esi) 433 jz .Lcopy_pt_regs_\@ 434 435 /* 436 * Stack-frame contains 4 additional segment registers when 437 * coming from VM86 mode 438 */ 439 addl $(4 * 4), %ecx 440 441#endif 442.Lcopy_pt_regs_\@: 443 444 /* Allocate frame on task-stack */ 445 subl %ecx, %edi 446 447 /* Switch to task-stack */ 448 movl %edi, %esp 449 450 /* 451 * We are now on the task-stack and can safely copy over the 452 * stack-frame 453 */ 454 shrl $2, %ecx 455 cld 456 rep movsl 457 458 jmp .Lend_\@ 459 460.Lentry_from_kernel_\@: 461 462 /* 463 * This handles the case when we enter the kernel from 464 * kernel-mode and %esp points to the entry-stack. When this 465 * happens we need to switch to the task-stack to run C code, 466 * but switch back to the entry-stack again when we approach 467 * iret and return to the interrupted code-path. This usually 468 * happens when we hit an exception while restoring user-space 469 * segment registers on the way back to user-space or when the 470 * sysenter handler runs with eflags.tf set. 471 * 472 * When we switch to the task-stack here, we can't trust the 473 * contents of the entry-stack anymore, as the exception handler 474 * might be scheduled out or moved to another CPU. Therefore we 475 * copy the complete entry-stack to the task-stack and set a 476 * marker in the iret-frame (bit 31 of the CS dword) to detect 477 * what we've done on the iret path. 478 * 479 * On the iret path we copy everything back and switch to the 480 * entry-stack, so that the interrupted kernel code-path 481 * continues on the same stack it was interrupted with. 482 * 483 * Be aware that an NMI can happen anytime in this code. 484 * 485 * %esi: Entry-Stack pointer (same as %esp) 486 * %edi: Top of the task stack 487 * %eax: CR3 on kernel entry 488 */ 489 490 /* Calculate number of bytes on the entry stack in %ecx */ 491 movl %esi, %ecx 492 493 /* %ecx to the top of entry-stack */ 494 andl $(MASK_entry_stack), %ecx 495 addl $(SIZEOF_entry_stack), %ecx 496 497 /* Number of bytes on the entry stack to %ecx */ 498 sub %esi, %ecx 499 500 /* Mark stackframe as coming from entry stack */ 501 orl $CS_FROM_ENTRY_STACK, PT_CS(%esp) 502 503 /* 504 * Test the cr3 used to enter the kernel and add a marker 505 * so that we can switch back to it before iret. 506 */ 507 testl $PTI_SWITCH_MASK, %eax 508 jz .Lcopy_pt_regs_\@ 509 orl $CS_FROM_USER_CR3, PT_CS(%esp) 510 511 /* 512 * %esi and %edi are unchanged, %ecx contains the number of 513 * bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate 514 * the stack-frame on task-stack and copy everything over 515 */ 516 jmp .Lcopy_pt_regs_\@ 517 518.Lend_\@: 519.endm 520 521/* 522 * Switch back from the kernel stack to the entry stack. 523 * 524 * The %esp register must point to pt_regs on the task stack. It will 525 * first calculate the size of the stack-frame to copy, depending on 526 * whether we return to VM86 mode or not. With that it uses 'rep movsl' 527 * to copy the contents of the stack over to the entry stack. 528 * 529 * We must be very careful here, as we can't trust the contents of the 530 * task-stack once we switched to the entry-stack. When an NMI happens 531 * while on the entry-stack, the NMI handler will switch back to the top 532 * of the task stack, overwriting our stack-frame we are about to copy. 533 * Therefore we switch the stack only after everything is copied over. 534 */ 535.macro SWITCH_TO_ENTRY_STACK 536 537 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV 538 539 /* Bytes to copy */ 540 movl $PTREGS_SIZE, %ecx 541 542#ifdef CONFIG_VM86 543 testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp) 544 jz .Lcopy_pt_regs_\@ 545 546 /* Additional 4 registers to copy when returning to VM86 mode */ 547 addl $(4 * 4), %ecx 548 549.Lcopy_pt_regs_\@: 550#endif 551 552 /* Initialize source and destination for movsl */ 553 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi 554 subl %ecx, %edi 555 movl %esp, %esi 556 557 /* Save future stack pointer in %ebx */ 558 movl %edi, %ebx 559 560 /* Copy over the stack-frame */ 561 shrl $2, %ecx 562 cld 563 rep movsl 564 565 /* 566 * Switch to entry-stack - needs to happen after everything is 567 * copied because the NMI handler will overwrite the task-stack 568 * when on entry-stack 569 */ 570 movl %ebx, %esp 571 572.Lend_\@: 573.endm 574 575/* 576 * This macro handles the case when we return to kernel-mode on the iret 577 * path and have to switch back to the entry stack and/or user-cr3 578 * 579 * See the comments below the .Lentry_from_kernel_\@ label in the 580 * SWITCH_TO_KERNEL_STACK macro for more details. 581 */ 582.macro PARANOID_EXIT_TO_KERNEL_MODE 583 584 /* 585 * Test if we entered the kernel with the entry-stack. Most 586 * likely we did not, because this code only runs on the 587 * return-to-kernel path. 588 */ 589 testl $CS_FROM_ENTRY_STACK, PT_CS(%esp) 590 jz .Lend_\@ 591 592 /* Unlikely slow-path */ 593 594 /* Clear marker from stack-frame */ 595 andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp) 596 597 /* Copy the remaining task-stack contents to entry-stack */ 598 movl %esp, %esi 599 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi 600 601 /* Bytes on the task-stack to ecx */ 602 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx 603 subl %esi, %ecx 604 605 /* Allocate stack-frame on entry-stack */ 606 subl %ecx, %edi 607 608 /* 609 * Save future stack-pointer, we must not switch until the 610 * copy is done, otherwise the NMI handler could destroy the 611 * contents of the task-stack we are about to copy. 612 */ 613 movl %edi, %ebx 614 615 /* Do the copy */ 616 shrl $2, %ecx 617 cld 618 rep movsl 619 620 /* Safe to switch to entry-stack now */ 621 movl %ebx, %esp 622 623 /* 624 * We came from entry-stack and need to check if we also need to 625 * switch back to user cr3. 626 */ 627 testl $CS_FROM_USER_CR3, PT_CS(%esp) 628 jz .Lend_\@ 629 630 /* Clear marker from stack-frame */ 631 andl $(~CS_FROM_USER_CR3), PT_CS(%esp) 632 633 SWITCH_TO_USER_CR3 scratch_reg=%eax 634 635.Lend_\@: 636.endm 637/* 638 * %eax: prev task 639 * %edx: next task 640 */ 641ENTRY(__switch_to_asm) 642 /* 643 * Save callee-saved registers 644 * This must match the order in struct inactive_task_frame 645 */ 646 pushl %ebp 647 pushl %ebx 648 pushl %edi 649 pushl %esi 650 651 /* switch stack */ 652 movl %esp, TASK_threadsp(%eax) 653 movl TASK_threadsp(%edx), %esp 654 655#ifdef CONFIG_STACKPROTECTOR 656 movl TASK_stack_canary(%edx), %ebx 657 movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset 658#endif 659 660#ifdef CONFIG_RETPOLINE 661 /* 662 * When switching from a shallower to a deeper call stack 663 * the RSB may either underflow or use entries populated 664 * with userspace addresses. On CPUs where those concerns 665 * exist, overwrite the RSB with entries which capture 666 * speculative execution to prevent attack. 667 */ 668 FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 669#endif 670 671 /* restore callee-saved registers */ 672 popl %esi 673 popl %edi 674 popl %ebx 675 popl %ebp 676 677 jmp __switch_to 678END(__switch_to_asm) 679 680/* 681 * The unwinder expects the last frame on the stack to always be at the same 682 * offset from the end of the page, which allows it to validate the stack. 683 * Calling schedule_tail() directly would break that convention because its an 684 * asmlinkage function so its argument has to be pushed on the stack. This 685 * wrapper creates a proper "end of stack" frame header before the call. 686 */ 687ENTRY(schedule_tail_wrapper) 688 FRAME_BEGIN 689 690 pushl %eax 691 call schedule_tail 692 popl %eax 693 694 FRAME_END 695 ret 696ENDPROC(schedule_tail_wrapper) 697/* 698 * A newly forked process directly context switches into this address. 699 * 700 * eax: prev task we switched from 701 * ebx: kernel thread func (NULL for user thread) 702 * edi: kernel thread arg 703 */ 704ENTRY(ret_from_fork) 705 call schedule_tail_wrapper 706 707 testl %ebx, %ebx 708 jnz 1f /* kernel threads are uncommon */ 709 7102: 711 /* When we fork, we trace the syscall return in the child, too. */ 712 movl %esp, %eax 713 call syscall_return_slowpath 714 jmp restore_all 715 716 /* kernel thread */ 7171: movl %edi, %eax 718 CALL_NOSPEC %ebx 719 /* 720 * A kernel thread is allowed to return here after successfully 721 * calling do_execve(). Exit to userspace to complete the execve() 722 * syscall. 723 */ 724 movl $0, PT_EAX(%esp) 725 jmp 2b 726END(ret_from_fork) 727 728/* 729 * Return to user mode is not as complex as all this looks, 730 * but we want the default path for a system call return to 731 * go as quickly as possible which is why some of this is 732 * less clear than it otherwise should be. 733 */ 734 735 # userspace resumption stub bypassing syscall exit tracing 736 ALIGN 737ret_from_exception: 738 preempt_stop(CLBR_ANY) 739ret_from_intr: 740#ifdef CONFIG_VM86 741 movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS 742 movb PT_CS(%esp), %al 743 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax 744#else 745 /* 746 * We can be coming here from child spawned by kernel_thread(). 747 */ 748 movl PT_CS(%esp), %eax 749 andl $SEGMENT_RPL_MASK, %eax 750#endif 751 cmpl $USER_RPL, %eax 752 jb resume_kernel # not returning to v8086 or userspace 753 754ENTRY(resume_userspace) 755 DISABLE_INTERRUPTS(CLBR_ANY) 756 TRACE_IRQS_OFF 757 movl %esp, %eax 758 call prepare_exit_to_usermode 759 jmp restore_all 760END(ret_from_exception) 761 762#ifdef CONFIG_PREEMPT 763ENTRY(resume_kernel) 764 DISABLE_INTERRUPTS(CLBR_ANY) 765.Lneed_resched: 766 cmpl $0, PER_CPU_VAR(__preempt_count) 767 jnz restore_all_kernel 768 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ? 769 jz restore_all_kernel 770 call preempt_schedule_irq 771 jmp .Lneed_resched 772END(resume_kernel) 773#endif 774 775GLOBAL(__begin_SYSENTER_singlestep_region) 776/* 777 * All code from here through __end_SYSENTER_singlestep_region is subject 778 * to being single-stepped if a user program sets TF and executes SYSENTER. 779 * There is absolutely nothing that we can do to prevent this from happening 780 * (thanks Intel!). To keep our handling of this situation as simple as 781 * possible, we handle TF just like AC and NT, except that our #DB handler 782 * will ignore all of the single-step traps generated in this range. 783 */ 784 785#ifdef CONFIG_XEN 786/* 787 * Xen doesn't set %esp to be precisely what the normal SYSENTER 788 * entry point expects, so fix it up before using the normal path. 789 */ 790ENTRY(xen_sysenter_target) 791 addl $5*4, %esp /* remove xen-provided frame */ 792 jmp .Lsysenter_past_esp 793#endif 794 795/* 796 * 32-bit SYSENTER entry. 797 * 798 * 32-bit system calls through the vDSO's __kernel_vsyscall enter here 799 * if X86_FEATURE_SEP is available. This is the preferred system call 800 * entry on 32-bit systems. 801 * 802 * The SYSENTER instruction, in principle, should *only* occur in the 803 * vDSO. In practice, a small number of Android devices were shipped 804 * with a copy of Bionic that inlined a SYSENTER instruction. This 805 * never happened in any of Google's Bionic versions -- it only happened 806 * in a narrow range of Intel-provided versions. 807 * 808 * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs. 809 * IF and VM in RFLAGS are cleared (IOW: interrupts are off). 810 * SYSENTER does not save anything on the stack, 811 * and does not save old EIP (!!!), ESP, or EFLAGS. 812 * 813 * To avoid losing track of EFLAGS.VM (and thus potentially corrupting 814 * user and/or vm86 state), we explicitly disable the SYSENTER 815 * instruction in vm86 mode by reprogramming the MSRs. 816 * 817 * Arguments: 818 * eax system call number 819 * ebx arg1 820 * ecx arg2 821 * edx arg3 822 * esi arg4 823 * edi arg5 824 * ebp user stack 825 * 0(%ebp) arg6 826 */ 827ENTRY(entry_SYSENTER_32) 828 /* 829 * On entry-stack with all userspace-regs live - save and 830 * restore eflags and %eax to use it as scratch-reg for the cr3 831 * switch. 832 */ 833 pushfl 834 pushl %eax 835 BUG_IF_WRONG_CR3 no_user_check=1 836 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax 837 popl %eax 838 popfl 839 840 /* Stack empty again, switch to task stack */ 841 movl TSS_entry2task_stack(%esp), %esp 842 843.Lsysenter_past_esp: 844 pushl $__USER_DS /* pt_regs->ss */ 845 pushl %ebp /* pt_regs->sp (stashed in bp) */ 846 pushfl /* pt_regs->flags (except IF = 0) */ 847 orl $X86_EFLAGS_IF, (%esp) /* Fix IF */ 848 pushl $__USER_CS /* pt_regs->cs */ 849 pushl $0 /* pt_regs->ip = 0 (placeholder) */ 850 pushl %eax /* pt_regs->orig_ax */ 851 SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */ 852 853 /* 854 * SYSENTER doesn't filter flags, so we need to clear NT, AC 855 * and TF ourselves. To save a few cycles, we can check whether 856 * either was set instead of doing an unconditional popfq. 857 * This needs to happen before enabling interrupts so that 858 * we don't get preempted with NT set. 859 * 860 * If TF is set, we will single-step all the way to here -- do_debug 861 * will ignore all the traps. (Yes, this is slow, but so is 862 * single-stepping in general. This allows us to avoid having 863 * a more complicated code to handle the case where a user program 864 * forces us to single-step through the SYSENTER entry code.) 865 * 866 * NB.: .Lsysenter_fix_flags is a label with the code under it moved 867 * out-of-line as an optimization: NT is unlikely to be set in the 868 * majority of the cases and instead of polluting the I$ unnecessarily, 869 * we're keeping that code behind a branch which will predict as 870 * not-taken and therefore its instructions won't be fetched. 871 */ 872 testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp) 873 jnz .Lsysenter_fix_flags 874.Lsysenter_flags_fixed: 875 876 /* 877 * User mode is traced as though IRQs are on, and SYSENTER 878 * turned them off. 879 */ 880 TRACE_IRQS_OFF 881 882 movl %esp, %eax 883 call do_fast_syscall_32 884 /* XEN PV guests always use IRET path */ 885 ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \ 886 "jmp .Lsyscall_32_done", X86_FEATURE_XENPV 887 888/* Opportunistic SYSEXIT */ 889 TRACE_IRQS_ON /* User mode traces as IRQs on. */ 890 891 /* 892 * Setup entry stack - we keep the pointer in %eax and do the 893 * switch after almost all user-state is restored. 894 */ 895 896 /* Load entry stack pointer and allocate frame for eflags/eax */ 897 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax 898 subl $(2*4), %eax 899 900 /* Copy eflags and eax to entry stack */ 901 movl PT_EFLAGS(%esp), %edi 902 movl PT_EAX(%esp), %esi 903 movl %edi, (%eax) 904 movl %esi, 4(%eax) 905 906 /* Restore user registers and segments */ 907 movl PT_EIP(%esp), %edx /* pt_regs->ip */ 908 movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */ 9091: mov PT_FS(%esp), %fs 910 PTGS_TO_GS 911 912 popl %ebx /* pt_regs->bx */ 913 addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */ 914 popl %esi /* pt_regs->si */ 915 popl %edi /* pt_regs->di */ 916 popl %ebp /* pt_regs->bp */ 917 918 /* Switch to entry stack */ 919 movl %eax, %esp 920 921 /* Now ready to switch the cr3 */ 922 SWITCH_TO_USER_CR3 scratch_reg=%eax 923 924 /* 925 * Restore all flags except IF. (We restore IF separately because 926 * STI gives a one-instruction window in which we won't be interrupted, 927 * whereas POPF does not.) 928 */ 929 btrl $X86_EFLAGS_IF_BIT, (%esp) 930 BUG_IF_WRONG_CR3 no_user_check=1 931 popfl 932 popl %eax 933 934 /* 935 * Return back to the vDSO, which will pop ecx and edx. 936 * Don't bother with DS and ES (they already contain __USER_DS). 937 */ 938 sti 939 sysexit 940 941.pushsection .fixup, "ax" 9422: movl $0, PT_FS(%esp) 943 jmp 1b 944.popsection 945 _ASM_EXTABLE(1b, 2b) 946 PTGS_TO_GS_EX 947 948.Lsysenter_fix_flags: 949 pushl $X86_EFLAGS_FIXED 950 popfl 951 jmp .Lsysenter_flags_fixed 952GLOBAL(__end_SYSENTER_singlestep_region) 953ENDPROC(entry_SYSENTER_32) 954 955/* 956 * 32-bit legacy system call entry. 957 * 958 * 32-bit x86 Linux system calls traditionally used the INT $0x80 959 * instruction. INT $0x80 lands here. 960 * 961 * This entry point can be used by any 32-bit perform system calls. 962 * Instances of INT $0x80 can be found inline in various programs and 963 * libraries. It is also used by the vDSO's __kernel_vsyscall 964 * fallback for hardware that doesn't support a faster entry method. 965 * Restarted 32-bit system calls also fall back to INT $0x80 966 * regardless of what instruction was originally used to do the system 967 * call. (64-bit programs can use INT $0x80 as well, but they can 968 * only run on 64-bit kernels and therefore land in 969 * entry_INT80_compat.) 970 * 971 * This is considered a slow path. It is not used by most libc 972 * implementations on modern hardware except during process startup. 973 * 974 * Arguments: 975 * eax system call number 976 * ebx arg1 977 * ecx arg2 978 * edx arg3 979 * esi arg4 980 * edi arg5 981 * ebp arg6 982 */ 983ENTRY(entry_INT80_32) 984 ASM_CLAC 985 pushl %eax /* pt_regs->orig_ax */ 986 987 SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */ 988 989 /* 990 * User mode is traced as though IRQs are on, and the interrupt gate 991 * turned them off. 992 */ 993 TRACE_IRQS_OFF 994 995 movl %esp, %eax 996 call do_int80_syscall_32 997.Lsyscall_32_done: 998 999restore_all: 1000 TRACE_IRQS_IRET 1001 SWITCH_TO_ENTRY_STACK 1002.Lrestore_all_notrace: 1003 CHECK_AND_APPLY_ESPFIX 1004.Lrestore_nocheck: 1005 /* Switch back to user CR3 */ 1006 SWITCH_TO_USER_CR3 scratch_reg=%eax 1007 1008 BUG_IF_WRONG_CR3 1009 1010 /* Restore user state */ 1011 RESTORE_REGS pop=4 # skip orig_eax/error_code 1012.Lirq_return: 1013 /* 1014 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 1015 * when returning from IPI handler and when returning from 1016 * scheduler to user-space. 1017 */ 1018 INTERRUPT_RETURN 1019 1020restore_all_kernel: 1021 TRACE_IRQS_IRET 1022 PARANOID_EXIT_TO_KERNEL_MODE 1023 BUG_IF_WRONG_CR3 1024 RESTORE_REGS 4 1025 jmp .Lirq_return 1026 1027.section .fixup, "ax" 1028ENTRY(iret_exc ) 1029 pushl $0 # no error code 1030 pushl $do_iret_error 1031 1032#ifdef CONFIG_DEBUG_ENTRY 1033 /* 1034 * The stack-frame here is the one that iret faulted on, so its a 1035 * return-to-user frame. We are on kernel-cr3 because we come here from 1036 * the fixup code. This confuses the CR3 checker, so switch to user-cr3 1037 * as the checker expects it. 1038 */ 1039 pushl %eax 1040 SWITCH_TO_USER_CR3 scratch_reg=%eax 1041 popl %eax 1042#endif 1043 1044 jmp common_exception 1045.previous 1046 _ASM_EXTABLE(.Lirq_return, iret_exc) 1047ENDPROC(entry_INT80_32) 1048 1049.macro FIXUP_ESPFIX_STACK 1050/* 1051 * Switch back for ESPFIX stack to the normal zerobased stack 1052 * 1053 * We can't call C functions using the ESPFIX stack. This code reads 1054 * the high word of the segment base from the GDT and swiches to the 1055 * normal stack and adjusts ESP with the matching offset. 1056 */ 1057#ifdef CONFIG_X86_ESPFIX32 1058 /* fixup the stack */ 1059 mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */ 1060 mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */ 1061 shl $16, %eax 1062 addl %esp, %eax /* the adjusted stack pointer */ 1063 pushl $__KERNEL_DS 1064 pushl %eax 1065 lss (%esp), %esp /* switch to the normal stack segment */ 1066#endif 1067.endm 1068.macro UNWIND_ESPFIX_STACK 1069#ifdef CONFIG_X86_ESPFIX32 1070 movl %ss, %eax 1071 /* see if on espfix stack */ 1072 cmpw $__ESPFIX_SS, %ax 1073 jne 27f 1074 movl $__KERNEL_DS, %eax 1075 movl %eax, %ds 1076 movl %eax, %es 1077 /* switch to normal stack */ 1078 FIXUP_ESPFIX_STACK 107927: 1080#endif 1081.endm 1082 1083/* 1084 * Build the entry stubs with some assembler magic. 1085 * We pack 1 stub into every 8-byte block. 1086 */ 1087 .align 8 1088ENTRY(irq_entries_start) 1089 vector=FIRST_EXTERNAL_VECTOR 1090 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 1091 pushl $(~vector+0x80) /* Note: always in signed byte range */ 1092 vector=vector+1 1093 jmp common_interrupt 1094 .align 8 1095 .endr 1096END(irq_entries_start) 1097 1098/* 1099 * the CPU automatically disables interrupts when executing an IRQ vector, 1100 * so IRQ-flags tracing has to follow that: 1101 */ 1102 .p2align CONFIG_X86_L1_CACHE_SHIFT 1103common_interrupt: 1104 ASM_CLAC 1105 addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */ 1106 1107 SAVE_ALL switch_stacks=1 1108 ENCODE_FRAME_POINTER 1109 TRACE_IRQS_OFF 1110 movl %esp, %eax 1111 call do_IRQ 1112 jmp ret_from_intr 1113ENDPROC(common_interrupt) 1114 1115#define BUILD_INTERRUPT3(name, nr, fn) \ 1116ENTRY(name) \ 1117 ASM_CLAC; \ 1118 pushl $~(nr); \ 1119 SAVE_ALL switch_stacks=1; \ 1120 ENCODE_FRAME_POINTER; \ 1121 TRACE_IRQS_OFF \ 1122 movl %esp, %eax; \ 1123 call fn; \ 1124 jmp ret_from_intr; \ 1125ENDPROC(name) 1126 1127#define BUILD_INTERRUPT(name, nr) \ 1128 BUILD_INTERRUPT3(name, nr, smp_##name); \ 1129 1130/* The include is where all of the SMP etc. interrupts come from */ 1131#include <asm/entry_arch.h> 1132 1133ENTRY(coprocessor_error) 1134 ASM_CLAC 1135 pushl $0 1136 pushl $do_coprocessor_error 1137 jmp common_exception 1138END(coprocessor_error) 1139 1140ENTRY(simd_coprocessor_error) 1141 ASM_CLAC 1142 pushl $0 1143#ifdef CONFIG_X86_INVD_BUG 1144 /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */ 1145 ALTERNATIVE "pushl $do_general_protection", \ 1146 "pushl $do_simd_coprocessor_error", \ 1147 X86_FEATURE_XMM 1148#else 1149 pushl $do_simd_coprocessor_error 1150#endif 1151 jmp common_exception 1152END(simd_coprocessor_error) 1153 1154ENTRY(device_not_available) 1155 ASM_CLAC 1156 pushl $-1 # mark this as an int 1157 pushl $do_device_not_available 1158 jmp common_exception 1159END(device_not_available) 1160 1161#ifdef CONFIG_PARAVIRT 1162ENTRY(native_iret) 1163 iret 1164 _ASM_EXTABLE(native_iret, iret_exc) 1165END(native_iret) 1166#endif 1167 1168ENTRY(overflow) 1169 ASM_CLAC 1170 pushl $0 1171 pushl $do_overflow 1172 jmp common_exception 1173END(overflow) 1174 1175ENTRY(bounds) 1176 ASM_CLAC 1177 pushl $0 1178 pushl $do_bounds 1179 jmp common_exception 1180END(bounds) 1181 1182ENTRY(invalid_op) 1183 ASM_CLAC 1184 pushl $0 1185 pushl $do_invalid_op 1186 jmp common_exception 1187END(invalid_op) 1188 1189ENTRY(coprocessor_segment_overrun) 1190 ASM_CLAC 1191 pushl $0 1192 pushl $do_coprocessor_segment_overrun 1193 jmp common_exception 1194END(coprocessor_segment_overrun) 1195 1196ENTRY(invalid_TSS) 1197 ASM_CLAC 1198 pushl $do_invalid_TSS 1199 jmp common_exception 1200END(invalid_TSS) 1201 1202ENTRY(segment_not_present) 1203 ASM_CLAC 1204 pushl $do_segment_not_present 1205 jmp common_exception 1206END(segment_not_present) 1207 1208ENTRY(stack_segment) 1209 ASM_CLAC 1210 pushl $do_stack_segment 1211 jmp common_exception 1212END(stack_segment) 1213 1214ENTRY(alignment_check) 1215 ASM_CLAC 1216 pushl $do_alignment_check 1217 jmp common_exception 1218END(alignment_check) 1219 1220ENTRY(divide_error) 1221 ASM_CLAC 1222 pushl $0 # no error code 1223 pushl $do_divide_error 1224 jmp common_exception 1225END(divide_error) 1226 1227#ifdef CONFIG_X86_MCE 1228ENTRY(machine_check) 1229 ASM_CLAC 1230 pushl $0 1231 pushl machine_check_vector 1232 jmp common_exception 1233END(machine_check) 1234#endif 1235 1236ENTRY(spurious_interrupt_bug) 1237 ASM_CLAC 1238 pushl $0 1239 pushl $do_spurious_interrupt_bug 1240 jmp common_exception 1241END(spurious_interrupt_bug) 1242 1243#ifdef CONFIG_XEN 1244ENTRY(xen_hypervisor_callback) 1245 pushl $-1 /* orig_ax = -1 => not a system call */ 1246 SAVE_ALL 1247 ENCODE_FRAME_POINTER 1248 TRACE_IRQS_OFF 1249 1250 /* 1251 * Check to see if we got the event in the critical 1252 * region in xen_iret_direct, after we've reenabled 1253 * events and checked for pending events. This simulates 1254 * iret instruction's behaviour where it delivers a 1255 * pending interrupt when enabling interrupts: 1256 */ 1257 movl PT_EIP(%esp), %eax 1258 cmpl $xen_iret_start_crit, %eax 1259 jb 1f 1260 cmpl $xen_iret_end_crit, %eax 1261 jae 1f 1262 1263 jmp xen_iret_crit_fixup 1264 1265ENTRY(xen_do_upcall) 12661: mov %esp, %eax 1267 call xen_evtchn_do_upcall 1268#ifndef CONFIG_PREEMPT 1269 call xen_maybe_preempt_hcall 1270#endif 1271 jmp ret_from_intr 1272ENDPROC(xen_hypervisor_callback) 1273 1274/* 1275 * Hypervisor uses this for application faults while it executes. 1276 * We get here for two reasons: 1277 * 1. Fault while reloading DS, ES, FS or GS 1278 * 2. Fault while executing IRET 1279 * Category 1 we fix up by reattempting the load, and zeroing the segment 1280 * register if the load fails. 1281 * Category 2 we fix up by jumping to do_iret_error. We cannot use the 1282 * normal Linux return path in this case because if we use the IRET hypercall 1283 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1284 * We distinguish between categories by maintaining a status value in EAX. 1285 */ 1286ENTRY(xen_failsafe_callback) 1287 pushl %eax 1288 movl $1, %eax 12891: mov 4(%esp), %ds 12902: mov 8(%esp), %es 12913: mov 12(%esp), %fs 12924: mov 16(%esp), %gs 1293 /* EAX == 0 => Category 1 (Bad segment) 1294 EAX != 0 => Category 2 (Bad IRET) */ 1295 testl %eax, %eax 1296 popl %eax 1297 lea 16(%esp), %esp 1298 jz 5f 1299 jmp iret_exc 13005: pushl $-1 /* orig_ax = -1 => not a system call */ 1301 SAVE_ALL 1302 ENCODE_FRAME_POINTER 1303 jmp ret_from_exception 1304 1305.section .fixup, "ax" 13066: xorl %eax, %eax 1307 movl %eax, 4(%esp) 1308 jmp 1b 13097: xorl %eax, %eax 1310 movl %eax, 8(%esp) 1311 jmp 2b 13128: xorl %eax, %eax 1313 movl %eax, 12(%esp) 1314 jmp 3b 13159: xorl %eax, %eax 1316 movl %eax, 16(%esp) 1317 jmp 4b 1318.previous 1319 _ASM_EXTABLE(1b, 6b) 1320 _ASM_EXTABLE(2b, 7b) 1321 _ASM_EXTABLE(3b, 8b) 1322 _ASM_EXTABLE(4b, 9b) 1323ENDPROC(xen_failsafe_callback) 1324 1325BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR, 1326 xen_evtchn_do_upcall) 1327 1328#endif /* CONFIG_XEN */ 1329 1330#if IS_ENABLED(CONFIG_HYPERV) 1331 1332BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR, 1333 hyperv_vector_handler) 1334 1335BUILD_INTERRUPT3(hyperv_reenlightenment_vector, HYPERV_REENLIGHTENMENT_VECTOR, 1336 hyperv_reenlightenment_intr) 1337 1338BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR, 1339 hv_stimer0_vector_handler) 1340 1341#endif /* CONFIG_HYPERV */ 1342 1343ENTRY(page_fault) 1344 ASM_CLAC 1345 pushl $do_page_fault 1346 ALIGN 1347 jmp common_exception 1348END(page_fault) 1349 1350common_exception: 1351 /* the function address is in %gs's slot on the stack */ 1352 pushl %fs 1353 pushl %es 1354 pushl %ds 1355 pushl %eax 1356 movl $(__USER_DS), %eax 1357 movl %eax, %ds 1358 movl %eax, %es 1359 movl $(__KERNEL_PERCPU), %eax 1360 movl %eax, %fs 1361 pushl %ebp 1362 pushl %edi 1363 pushl %esi 1364 pushl %edx 1365 pushl %ecx 1366 pushl %ebx 1367 SWITCH_TO_KERNEL_STACK 1368 ENCODE_FRAME_POINTER 1369 cld 1370 UNWIND_ESPFIX_STACK 1371 GS_TO_REG %ecx 1372 movl PT_GS(%esp), %edi # get the function address 1373 movl PT_ORIG_EAX(%esp), %edx # get the error code 1374 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart 1375 REG_TO_PTGS %ecx 1376 SET_KERNEL_GS %ecx 1377 TRACE_IRQS_OFF 1378 movl %esp, %eax # pt_regs pointer 1379 CALL_NOSPEC %edi 1380 jmp ret_from_exception 1381END(common_exception) 1382 1383ENTRY(debug) 1384 /* 1385 * Entry from sysenter is now handled in common_exception 1386 */ 1387 ASM_CLAC 1388 pushl $-1 # mark this as an int 1389 pushl $do_debug 1390 jmp common_exception 1391END(debug) 1392 1393/* 1394 * NMI is doubly nasty. It can happen on the first instruction of 1395 * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning 1396 * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32 1397 * switched stacks. We handle both conditions by simply checking whether we 1398 * interrupted kernel code running on the SYSENTER stack. 1399 */ 1400ENTRY(nmi) 1401 ASM_CLAC 1402 1403#ifdef CONFIG_X86_ESPFIX32 1404 pushl %eax 1405 movl %ss, %eax 1406 cmpw $__ESPFIX_SS, %ax 1407 popl %eax 1408 je .Lnmi_espfix_stack 1409#endif 1410 1411 pushl %eax # pt_regs->orig_ax 1412 SAVE_ALL_NMI cr3_reg=%edi 1413 ENCODE_FRAME_POINTER 1414 xorl %edx, %edx # zero error code 1415 movl %esp, %eax # pt_regs pointer 1416 1417 /* Are we currently on the SYSENTER stack? */ 1418 movl PER_CPU_VAR(cpu_entry_area), %ecx 1419 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx 1420 subl %eax, %ecx /* ecx = (end of entry_stack) - esp */ 1421 cmpl $SIZEOF_entry_stack, %ecx 1422 jb .Lnmi_from_sysenter_stack 1423 1424 /* Not on SYSENTER stack. */ 1425 call do_nmi 1426 jmp .Lnmi_return 1427 1428.Lnmi_from_sysenter_stack: 1429 /* 1430 * We're on the SYSENTER stack. Switch off. No one (not even debug) 1431 * is using the thread stack right now, so it's safe for us to use it. 1432 */ 1433 movl %esp, %ebx 1434 movl PER_CPU_VAR(cpu_current_top_of_stack), %esp 1435 call do_nmi 1436 movl %ebx, %esp 1437 1438.Lnmi_return: 1439 CHECK_AND_APPLY_ESPFIX 1440 RESTORE_ALL_NMI cr3_reg=%edi pop=4 1441 jmp .Lirq_return 1442 1443#ifdef CONFIG_X86_ESPFIX32 1444.Lnmi_espfix_stack: 1445 /* 1446 * create the pointer to lss back 1447 */ 1448 pushl %ss 1449 pushl %esp 1450 addl $4, (%esp) 1451 /* copy the iret frame of 12 bytes */ 1452 .rept 3 1453 pushl 16(%esp) 1454 .endr 1455 pushl %eax 1456 SAVE_ALL_NMI cr3_reg=%edi 1457 ENCODE_FRAME_POINTER 1458 FIXUP_ESPFIX_STACK # %eax == %esp 1459 xorl %edx, %edx # zero error code 1460 call do_nmi 1461 RESTORE_ALL_NMI cr3_reg=%edi 1462 lss 12+4(%esp), %esp # back to espfix stack 1463 jmp .Lirq_return 1464#endif 1465END(nmi) 1466 1467ENTRY(int3) 1468 ASM_CLAC 1469 pushl $-1 # mark this as an int 1470 1471 SAVE_ALL switch_stacks=1 1472 ENCODE_FRAME_POINTER 1473 TRACE_IRQS_OFF 1474 xorl %edx, %edx # zero error code 1475 movl %esp, %eax # pt_regs pointer 1476 call do_int3 1477 jmp ret_from_exception 1478END(int3) 1479 1480ENTRY(general_protection) 1481 pushl $do_general_protection 1482 jmp common_exception 1483END(general_protection) 1484 1485#ifdef CONFIG_KVM_GUEST 1486ENTRY(async_page_fault) 1487 ASM_CLAC 1488 pushl $do_async_page_fault 1489 jmp common_exception 1490END(async_page_fault) 1491#endif 1492 1493ENTRY(rewind_stack_do_exit) 1494 /* Prevent any naive code from trying to unwind to our caller. */ 1495 xorl %ebp, %ebp 1496 1497 movl PER_CPU_VAR(cpu_current_top_of_stack), %esi 1498 leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp 1499 1500 call do_exit 15011: jmp 1b 1502END(rewind_stack_do_exit) 1503