1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #include <linux/jump_label.h> 3 #include <asm/unwind_hints.h> 4 #include <asm/cpufeatures.h> 5 #include <asm/page_types.h> 6 #include <asm/percpu.h> 7 #include <asm/asm-offsets.h> 8 #include <asm/processor-flags.h> 9 #include <asm/inst.h> 10 11 /* 12 13 x86 function call convention, 64-bit: 14 ------------------------------------- 15 arguments | callee-saved | extra caller-saved | return 16 [callee-clobbered] | | [callee-clobbered] | 17 --------------------------------------------------------------------------- 18 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**] 19 20 ( rsp is obviously invariant across normal function calls. (gcc can 'merge' 21 functions when it sees tail-call optimization possibilities) rflags is 22 clobbered. Leftover arguments are passed over the stack frame.) 23 24 [*] In the frame-pointers case rbp is fixed to the stack frame. 25 26 [**] for struct return values wider than 64 bits the return convention is a 27 bit more complex: up to 128 bits width we return small structures 28 straight in rax, rdx. For structures larger than that (3 words or 29 larger) the caller puts a pointer to an on-stack return struct 30 [allocated in the caller's stack frame] into the first argument - i.e. 31 into rdi. All other arguments shift up by one in this case. 32 Fortunately this case is rare in the kernel. 33 34 For 32-bit we have the following conventions - kernel is built with 35 -mregparm=3 and -freg-struct-return: 36 37 x86 function calling convention, 32-bit: 38 ---------------------------------------- 39 arguments | callee-saved | extra caller-saved | return 40 [callee-clobbered] | | [callee-clobbered] | 41 ------------------------------------------------------------------------- 42 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**] 43 44 ( here too esp is obviously invariant across normal function calls. eflags 45 is clobbered. Leftover arguments are passed over the stack frame. ) 46 47 [*] In the frame-pointers case ebp is fixed to the stack frame. 48 49 [**] We build with -freg-struct-return, which on 32-bit means similar 50 semantics as on 64-bit: edx can be used for a second return value 51 (i.e. covering integer and structure sizes up to 64 bits) - after that 52 it gets more complex and more expensive: 3-word or larger struct returns 53 get done in the caller's frame and the pointer to the return struct goes 54 into regparm0, i.e. eax - the other arguments shift up and the 55 function's register parameters degenerate to regparm=2 in essence. 56 57 */ 58 59 #ifdef CONFIG_X86_64 60 61 /* 62 * 64-bit system call stack frame layout defines and helpers, 63 * for assembly code: 64 */ 65 66 /* The layout forms the "struct pt_regs" on the stack: */ 67 /* 68 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry 69 * unless syscall needs a complete, fully filled "struct pt_regs". 70 */ 71 #define R15 0*8 72 #define R14 1*8 73 #define R13 2*8 74 #define R12 3*8 75 #define RBP 4*8 76 #define RBX 5*8 77 /* These regs are callee-clobbered. Always saved on kernel entry. */ 78 #define R11 6*8 79 #define R10 7*8 80 #define R9 8*8 81 #define R8 9*8 82 #define RAX 10*8 83 #define RCX 11*8 84 #define RDX 12*8 85 #define RSI 13*8 86 #define RDI 14*8 87 /* 88 * On syscall entry, this is syscall#. On CPU exception, this is error code. 89 * On hw interrupt, it's IRQ number: 90 */ 91 #define ORIG_RAX 15*8 92 /* Return frame for iretq */ 93 #define RIP 16*8 94 #define CS 17*8 95 #define EFLAGS 18*8 96 #define RSP 19*8 97 #define SS 20*8 98 99 #define SIZEOF_PTREGS 21*8 100 101 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0 102 /* 103 * Push registers and sanitize registers of values that a 104 * speculation attack might otherwise want to exploit. The 105 * lower registers are likely clobbered well before they 106 * could be put to use in a speculative execution gadget. 107 * Interleave XOR with PUSH for better uop scheduling: 108 */ 109 .if \save_ret 110 pushq %rsi /* pt_regs->si */ 111 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */ 112 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */ 113 .else 114 pushq %rdi /* pt_regs->di */ 115 pushq %rsi /* pt_regs->si */ 116 .endif 117 pushq \rdx /* pt_regs->dx */ 118 xorl %edx, %edx /* nospec dx */ 119 pushq %rcx /* pt_regs->cx */ 120 xorl %ecx, %ecx /* nospec cx */ 121 pushq \rax /* pt_regs->ax */ 122 pushq %r8 /* pt_regs->r8 */ 123 xorl %r8d, %r8d /* nospec r8 */ 124 pushq %r9 /* pt_regs->r9 */ 125 xorl %r9d, %r9d /* nospec r9 */ 126 pushq %r10 /* pt_regs->r10 */ 127 xorl %r10d, %r10d /* nospec r10 */ 128 pushq %r11 /* pt_regs->r11 */ 129 xorl %r11d, %r11d /* nospec r11*/ 130 pushq %rbx /* pt_regs->rbx */ 131 xorl %ebx, %ebx /* nospec rbx*/ 132 pushq %rbp /* pt_regs->rbp */ 133 xorl %ebp, %ebp /* nospec rbp*/ 134 pushq %r12 /* pt_regs->r12 */ 135 xorl %r12d, %r12d /* nospec r12*/ 136 pushq %r13 /* pt_regs->r13 */ 137 xorl %r13d, %r13d /* nospec r13*/ 138 pushq %r14 /* pt_regs->r14 */ 139 xorl %r14d, %r14d /* nospec r14*/ 140 pushq %r15 /* pt_regs->r15 */ 141 xorl %r15d, %r15d /* nospec r15*/ 142 UNWIND_HINT_REGS 143 .if \save_ret 144 pushq %rsi /* return address on top of stack */ 145 .endif 146 .endm 147 148 .macro POP_REGS pop_rdi=1 skip_r11rcx=0 149 popq %r15 150 popq %r14 151 popq %r13 152 popq %r12 153 popq %rbp 154 popq %rbx 155 .if \skip_r11rcx 156 popq %rsi 157 .else 158 popq %r11 159 .endif 160 popq %r10 161 popq %r9 162 popq %r8 163 popq %rax 164 .if \skip_r11rcx 165 popq %rsi 166 .else 167 popq %rcx 168 .endif 169 popq %rdx 170 popq %rsi 171 .if \pop_rdi 172 popq %rdi 173 .endif 174 .endm 175 176 /* 177 * This is a sneaky trick to help the unwinder find pt_regs on the stack. The 178 * frame pointer is replaced with an encoded pointer to pt_regs. The encoding 179 * is just setting the LSB, which makes it an invalid stack address and is also 180 * a signal to the unwinder that it's a pt_regs pointer in disguise. 181 * 182 * NOTE: This macro must be used *after* PUSH_AND_CLEAR_REGS because it corrupts 183 * the original rbp. 184 */ 185 .macro ENCODE_FRAME_POINTER ptregs_offset=0 186 #ifdef CONFIG_FRAME_POINTER 187 leaq 1+\ptregs_offset(%rsp), %rbp 188 #endif 189 .endm 190 191 #ifdef CONFIG_PAGE_TABLE_ISOLATION 192 193 /* 194 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two 195 * halves: 196 */ 197 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT 198 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT) 199 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT 200 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT) 201 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK) 202 203 .macro SET_NOFLUSH_BIT reg:req 204 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg 205 .endm 206 207 .macro ADJUST_KERNEL_CR3 reg:req 208 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID 209 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */ 210 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg 211 .endm 212 213 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 214 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 215 mov %cr3, \scratch_reg 216 ADJUST_KERNEL_CR3 \scratch_reg 217 mov \scratch_reg, %cr3 218 .Lend_\@: 219 .endm 220 221 #define THIS_CPU_user_pcid_flush_mask \ 222 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask 223 224 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 225 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 226 mov %cr3, \scratch_reg 227 228 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 229 230 /* 231 * Test if the ASID needs a flush. 232 */ 233 movq \scratch_reg, \scratch_reg2 234 andq $(0x7FF), \scratch_reg /* mask ASID */ 235 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 236 jnc .Lnoflush_\@ 237 238 /* Flush needed, clear the bit */ 239 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 240 movq \scratch_reg2, \scratch_reg 241 jmp .Lwrcr3_pcid_\@ 242 243 .Lnoflush_\@: 244 movq \scratch_reg2, \scratch_reg 245 SET_NOFLUSH_BIT \scratch_reg 246 247 .Lwrcr3_pcid_\@: 248 /* Flip the ASID to the user version */ 249 orq $(PTI_USER_PCID_MASK), \scratch_reg 250 251 .Lwrcr3_\@: 252 /* Flip the PGD to the user version */ 253 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg 254 mov \scratch_reg, %cr3 255 .Lend_\@: 256 .endm 257 258 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 259 pushq %rax 260 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax 261 popq %rax 262 .endm 263 264 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 265 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI 266 movq %cr3, \scratch_reg 267 movq \scratch_reg, \save_reg 268 /* 269 * Test the user pagetable bit. If set, then the user page tables 270 * are active. If clear CR3 already has the kernel page table 271 * active. 272 */ 273 bt $PTI_USER_PGTABLE_BIT, \scratch_reg 274 jnc .Ldone_\@ 275 276 ADJUST_KERNEL_CR3 \scratch_reg 277 movq \scratch_reg, %cr3 278 279 .Ldone_\@: 280 .endm 281 282 .macro RESTORE_CR3 scratch_reg:req save_reg:req 283 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 284 285 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 286 287 /* 288 * KERNEL pages can always resume with NOFLUSH as we do 289 * explicit flushes. 290 */ 291 bt $PTI_USER_PGTABLE_BIT, \save_reg 292 jnc .Lnoflush_\@ 293 294 /* 295 * Check if there's a pending flush for the user ASID we're 296 * about to set. 297 */ 298 movq \save_reg, \scratch_reg 299 andq $(0x7FF), \scratch_reg 300 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 301 jnc .Lnoflush_\@ 302 303 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 304 jmp .Lwrcr3_\@ 305 306 .Lnoflush_\@: 307 SET_NOFLUSH_BIT \save_reg 308 309 .Lwrcr3_\@: 310 /* 311 * The CR3 write could be avoided when not changing its value, 312 * but would require a CR3 read *and* a scratch register. 313 */ 314 movq \save_reg, %cr3 315 .Lend_\@: 316 .endm 317 318 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */ 319 320 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 321 .endm 322 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 323 .endm 324 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 325 .endm 326 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 327 .endm 328 .macro RESTORE_CR3 scratch_reg:req save_reg:req 329 .endm 330 331 #endif 332 333 .macro STACKLEAK_ERASE_NOCLOBBER 334 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 335 PUSH_AND_CLEAR_REGS 336 call stackleak_erase 337 POP_REGS 338 #endif 339 .endm 340 341 .macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req 342 rdgsbase \save_reg 343 GET_PERCPU_BASE \scratch_reg 344 wrgsbase \scratch_reg 345 .endm 346 347 #endif /* CONFIG_X86_64 */ 348 349 .macro STACKLEAK_ERASE 350 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 351 call stackleak_erase 352 #endif 353 .endm 354 355 #ifdef CONFIG_SMP 356 357 /* 358 * CPU/node NR is loaded from the limit (size) field of a special segment 359 * descriptor entry in GDT. 360 */ 361 .macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req 362 movq $__CPUNODE_SEG, \reg 363 lsl \reg, \reg 364 .endm 365 366 /* 367 * Fetch the per-CPU GSBASE value for this processor and put it in @reg. 368 * We normally use %gs for accessing per-CPU data, but we are setting up 369 * %gs here and obviously can not use %gs itself to access per-CPU data. 370 */ 371 .macro GET_PERCPU_BASE reg:req 372 ALTERNATIVE \ 373 "LOAD_CPU_AND_NODE_SEG_LIMIT \reg", \ 374 "RDPID \reg", \ 375 X86_FEATURE_RDPID 376 andq $VDSO_CPUNODE_MASK, \reg 377 movq __per_cpu_offset(, \reg, 8), \reg 378 .endm 379 380 #else 381 382 .macro GET_PERCPU_BASE reg:req 383 movq pcpu_unit_offsets(%rip), \reg 384 .endm 385 386 #endif /* CONFIG_SMP */ 387 388 /* 389 * This does 'call enter_from_user_mode' unless we can avoid it based on 390 * kernel config or using the static jump infrastructure. 391 */ 392 .macro CALL_enter_from_user_mode 393 #ifdef CONFIG_CONTEXT_TRACKING 394 #ifdef CONFIG_JUMP_LABEL 395 STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0 396 #endif 397 call enter_from_user_mode 398 .Lafter_call_\@: 399 #endif 400 .endm 401