1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2478dc89cSAndy Lutomirski #include <linux/jump_label.h> 38c1f7558SJosh Poimboeuf #include <asm/unwind_hints.h> 48a09317bSDave Hansen #include <asm/cpufeatures.h> 58a09317bSDave Hansen #include <asm/page_types.h> 66fd166aaSPeter Zijlstra #include <asm/percpu.h> 76fd166aaSPeter Zijlstra #include <asm/asm-offsets.h> 86fd166aaSPeter Zijlstra #include <asm/processor-flags.h> 96627eb25SH. Peter Anvin (Intel) #include <asm/ptrace-abi.h> 10478dc89cSAndy Lutomirski 11d36f9479SIngo Molnar /* 12d36f9479SIngo Molnar 13d36f9479SIngo Molnar x86 function call convention, 64-bit: 14d36f9479SIngo Molnar ------------------------------------- 15d36f9479SIngo Molnar arguments | callee-saved | extra caller-saved | return 16d36f9479SIngo Molnar [callee-clobbered] | | [callee-clobbered] | 17d36f9479SIngo Molnar --------------------------------------------------------------------------- 18d36f9479SIngo Molnar rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**] 19d36f9479SIngo Molnar 20d36f9479SIngo Molnar ( rsp is obviously invariant across normal function calls. (gcc can 'merge' 21d36f9479SIngo Molnar functions when it sees tail-call optimization possibilities) rflags is 22d36f9479SIngo Molnar clobbered. Leftover arguments are passed over the stack frame.) 23d36f9479SIngo Molnar 24d36f9479SIngo Molnar [*] In the frame-pointers case rbp is fixed to the stack frame. 25d36f9479SIngo Molnar 26d36f9479SIngo Molnar [**] for struct return values wider than 64 bits the return convention is a 27d36f9479SIngo Molnar bit more complex: up to 128 bits width we return small structures 28d36f9479SIngo Molnar straight in rax, rdx. For structures larger than that (3 words or 29d36f9479SIngo Molnar larger) the caller puts a pointer to an on-stack return struct 30d36f9479SIngo Molnar [allocated in the caller's stack frame] into the first argument - i.e. 31d36f9479SIngo Molnar into rdi. All other arguments shift up by one in this case. 32d36f9479SIngo Molnar Fortunately this case is rare in the kernel. 33d36f9479SIngo Molnar 34d36f9479SIngo Molnar For 32-bit we have the following conventions - kernel is built with 35d36f9479SIngo Molnar -mregparm=3 and -freg-struct-return: 36d36f9479SIngo Molnar 37d36f9479SIngo Molnar x86 function calling convention, 32-bit: 38d36f9479SIngo Molnar ---------------------------------------- 39d36f9479SIngo Molnar arguments | callee-saved | extra caller-saved | return 40d36f9479SIngo Molnar [callee-clobbered] | | [callee-clobbered] | 41d36f9479SIngo Molnar ------------------------------------------------------------------------- 42d36f9479SIngo Molnar eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**] 43d36f9479SIngo Molnar 44d36f9479SIngo Molnar ( here too esp is obviously invariant across normal function calls. eflags 45d36f9479SIngo Molnar is clobbered. Leftover arguments are passed over the stack frame. ) 46d36f9479SIngo Molnar 47d36f9479SIngo Molnar [*] In the frame-pointers case ebp is fixed to the stack frame. 48d36f9479SIngo Molnar 49d36f9479SIngo Molnar [**] We build with -freg-struct-return, which on 32-bit means similar 50d36f9479SIngo Molnar semantics as on 64-bit: edx can be used for a second return value 51d36f9479SIngo Molnar (i.e. covering integer and structure sizes up to 64 bits) - after that 52d36f9479SIngo Molnar it gets more complex and more expensive: 3-word or larger struct returns 53d36f9479SIngo Molnar get done in the caller's frame and the pointer to the return struct goes 54d36f9479SIngo Molnar into regparm0, i.e. eax - the other arguments shift up and the 55d36f9479SIngo Molnar function's register parameters degenerate to regparm=2 in essence. 56d36f9479SIngo Molnar 57d36f9479SIngo Molnar */ 58d36f9479SIngo Molnar 59d36f9479SIngo Molnar #ifdef CONFIG_X86_64 60d36f9479SIngo Molnar 61d36f9479SIngo Molnar /* 62d36f9479SIngo Molnar * 64-bit system call stack frame layout defines and helpers, 63d36f9479SIngo Molnar * for assembly code: 64d36f9479SIngo Molnar */ 65d36f9479SIngo Molnar 6629e97589SH. Peter Anvin (Intel) .macro PUSH_REGS rdx=%rdx rax=%rax save_ret=0 679e809d15SDominik Brodowski .if \save_ret 689e809d15SDominik Brodowski pushq %rsi /* pt_regs->si */ 699e809d15SDominik Brodowski movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */ 709e809d15SDominik Brodowski movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */ 719e809d15SDominik Brodowski .else 723f01daecSDominik Brodowski pushq %rdi /* pt_regs->di */ 733f01daecSDominik Brodowski pushq %rsi /* pt_regs->si */ 749e809d15SDominik Brodowski .endif 7530907fd1SDominik Brodowski pushq \rdx /* pt_regs->dx */ 763f01daecSDominik Brodowski pushq %rcx /* pt_regs->cx */ 7730907fd1SDominik Brodowski pushq \rax /* pt_regs->ax */ 783f01daecSDominik Brodowski pushq %r8 /* pt_regs->r8 */ 793f01daecSDominik Brodowski pushq %r9 /* pt_regs->r9 */ 803f01daecSDominik Brodowski pushq %r10 /* pt_regs->r10 */ 813f01daecSDominik Brodowski pushq %r11 /* pt_regs->r11 */ 823f01daecSDominik Brodowski pushq %rbx /* pt_regs->rbx */ 833f01daecSDominik Brodowski pushq %rbp /* pt_regs->rbp */ 843f01daecSDominik Brodowski pushq %r12 /* pt_regs->r12 */ 853f01daecSDominik Brodowski pushq %r13 /* pt_regs->r13 */ 863f01daecSDominik Brodowski pushq %r14 /* pt_regs->r14 */ 873f01daecSDominik Brodowski pushq %r15 /* pt_regs->r15 */ 883f01daecSDominik Brodowski UNWIND_HINT_REGS 8906a9750eSJosh Poimboeuf 909e809d15SDominik Brodowski .if \save_ret 919e809d15SDominik Brodowski pushq %rsi /* return address on top of stack */ 929e809d15SDominik Brodowski .endif 9329e97589SH. Peter Anvin (Intel) .endm 9406a9750eSJosh Poimboeuf 9529e97589SH. Peter Anvin (Intel) .macro CLEAR_REGS 9606a9750eSJosh Poimboeuf /* 9706a9750eSJosh Poimboeuf * Sanitize registers of values that a speculation attack might 9806a9750eSJosh Poimboeuf * otherwise want to exploit. The lower registers are likely clobbered 9906a9750eSJosh Poimboeuf * well before they could be put to use in a speculative execution 10006a9750eSJosh Poimboeuf * gadget. 10106a9750eSJosh Poimboeuf */ 102*8c42819bSPeter Zijlstra xorl %esi, %esi /* nospec si */ 10306a9750eSJosh Poimboeuf xorl %edx, %edx /* nospec dx */ 10406a9750eSJosh Poimboeuf xorl %ecx, %ecx /* nospec cx */ 10506a9750eSJosh Poimboeuf xorl %r8d, %r8d /* nospec r8 */ 10606a9750eSJosh Poimboeuf xorl %r9d, %r9d /* nospec r9 */ 10706a9750eSJosh Poimboeuf xorl %r10d, %r10d /* nospec r10 */ 10806a9750eSJosh Poimboeuf xorl %r11d, %r11d /* nospec r11 */ 10906a9750eSJosh Poimboeuf xorl %ebx, %ebx /* nospec rbx */ 11006a9750eSJosh Poimboeuf xorl %ebp, %ebp /* nospec rbp */ 11106a9750eSJosh Poimboeuf xorl %r12d, %r12d /* nospec r12 */ 11206a9750eSJosh Poimboeuf xorl %r13d, %r13d /* nospec r13 */ 11306a9750eSJosh Poimboeuf xorl %r14d, %r14d /* nospec r14 */ 11406a9750eSJosh Poimboeuf xorl %r15d, %r15d /* nospec r15 */ 11506a9750eSJosh Poimboeuf 1163f01daecSDominik Brodowski .endm 1173f01daecSDominik Brodowski 11829e97589SH. Peter Anvin (Intel) .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0 11929e97589SH. Peter Anvin (Intel) PUSH_REGS rdx=\rdx, rax=\rax, save_ret=\save_ret 12029e97589SH. Peter Anvin (Intel) CLEAR_REGS 12129e97589SH. Peter Anvin (Intel) .endm 12229e97589SH. Peter Anvin (Intel) 123502af0d7SDominik Brodowski .macro POP_REGS pop_rdi=1 skip_r11rcx=0 124e872045bSAndy Lutomirski popq %r15 125e872045bSAndy Lutomirski popq %r14 126e872045bSAndy Lutomirski popq %r13 127e872045bSAndy Lutomirski popq %r12 128e872045bSAndy Lutomirski popq %rbp 129e872045bSAndy Lutomirski popq %rbx 130502af0d7SDominik Brodowski .if \skip_r11rcx 131502af0d7SDominik Brodowski popq %rsi 132502af0d7SDominik Brodowski .else 133e872045bSAndy Lutomirski popq %r11 134502af0d7SDominik Brodowski .endif 135e872045bSAndy Lutomirski popq %r10 136e872045bSAndy Lutomirski popq %r9 137e872045bSAndy Lutomirski popq %r8 138e872045bSAndy Lutomirski popq %rax 139502af0d7SDominik Brodowski .if \skip_r11rcx 140502af0d7SDominik Brodowski popq %rsi 141502af0d7SDominik Brodowski .else 142e872045bSAndy Lutomirski popq %rcx 143502af0d7SDominik Brodowski .endif 144e872045bSAndy Lutomirski popq %rdx 145e872045bSAndy Lutomirski popq %rsi 146502af0d7SDominik Brodowski .if \pop_rdi 147e872045bSAndy Lutomirski popq %rdi 148502af0d7SDominik Brodowski .endif 149d36f9479SIngo Molnar .endm 150d36f9479SIngo Molnar 1518a09317bSDave Hansen #ifdef CONFIG_PAGE_TABLE_ISOLATION 1528a09317bSDave Hansen 1536fd166aaSPeter Zijlstra /* 1546fd166aaSPeter Zijlstra * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two 1556fd166aaSPeter Zijlstra * halves: 1566fd166aaSPeter Zijlstra */ 157f10ee3dcSThomas Gleixner #define PTI_USER_PGTABLE_BIT PAGE_SHIFT 158f10ee3dcSThomas Gleixner #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT) 159f10ee3dcSThomas Gleixner #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT 160f10ee3dcSThomas Gleixner #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT) 161f10ee3dcSThomas Gleixner #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK) 1628a09317bSDave Hansen 1636fd166aaSPeter Zijlstra .macro SET_NOFLUSH_BIT reg:req 1646fd166aaSPeter Zijlstra bts $X86_CR3_PCID_NOFLUSH_BIT, \reg 1658a09317bSDave Hansen .endm 1668a09317bSDave Hansen 1676fd166aaSPeter Zijlstra .macro ADJUST_KERNEL_CR3 reg:req 1686fd166aaSPeter Zijlstra ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID 1696fd166aaSPeter Zijlstra /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */ 170f10ee3dcSThomas Gleixner andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg 1718a09317bSDave Hansen .endm 1728a09317bSDave Hansen 1738a09317bSDave Hansen .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 174aa8c6248SThomas Gleixner ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 1758a09317bSDave Hansen mov %cr3, \scratch_reg 1768a09317bSDave Hansen ADJUST_KERNEL_CR3 \scratch_reg 1778a09317bSDave Hansen mov \scratch_reg, %cr3 178aa8c6248SThomas Gleixner .Lend_\@: 1798a09317bSDave Hansen .endm 1808a09317bSDave Hansen 1816fd166aaSPeter Zijlstra #define THIS_CPU_user_pcid_flush_mask \ 1826fd166aaSPeter Zijlstra PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask 1836fd166aaSPeter Zijlstra 1846fd166aaSPeter Zijlstra .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 185aa8c6248SThomas Gleixner ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 1868a09317bSDave Hansen mov %cr3, \scratch_reg 1876fd166aaSPeter Zijlstra 1886fd166aaSPeter Zijlstra ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 1896fd166aaSPeter Zijlstra 1906fd166aaSPeter Zijlstra /* 1916fd166aaSPeter Zijlstra * Test if the ASID needs a flush. 1926fd166aaSPeter Zijlstra */ 1936fd166aaSPeter Zijlstra movq \scratch_reg, \scratch_reg2 1946fd166aaSPeter Zijlstra andq $(0x7FF), \scratch_reg /* mask ASID */ 1956fd166aaSPeter Zijlstra bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 1966fd166aaSPeter Zijlstra jnc .Lnoflush_\@ 1976fd166aaSPeter Zijlstra 1986fd166aaSPeter Zijlstra /* Flush needed, clear the bit */ 1996fd166aaSPeter Zijlstra btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 2006fd166aaSPeter Zijlstra movq \scratch_reg2, \scratch_reg 201f10ee3dcSThomas Gleixner jmp .Lwrcr3_pcid_\@ 2026fd166aaSPeter Zijlstra 2036fd166aaSPeter Zijlstra .Lnoflush_\@: 2046fd166aaSPeter Zijlstra movq \scratch_reg2, \scratch_reg 2056fd166aaSPeter Zijlstra SET_NOFLUSH_BIT \scratch_reg 2066fd166aaSPeter Zijlstra 207f10ee3dcSThomas Gleixner .Lwrcr3_pcid_\@: 208f10ee3dcSThomas Gleixner /* Flip the ASID to the user version */ 209f10ee3dcSThomas Gleixner orq $(PTI_USER_PCID_MASK), \scratch_reg 210f10ee3dcSThomas Gleixner 2116fd166aaSPeter Zijlstra .Lwrcr3_\@: 212f10ee3dcSThomas Gleixner /* Flip the PGD to the user version */ 213f10ee3dcSThomas Gleixner orq $(PTI_USER_PGTABLE_MASK), \scratch_reg 2148a09317bSDave Hansen mov \scratch_reg, %cr3 215aa8c6248SThomas Gleixner .Lend_\@: 2168a09317bSDave Hansen .endm 2178a09317bSDave Hansen 2186fd166aaSPeter Zijlstra .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 2196fd166aaSPeter Zijlstra pushq %rax 2206fd166aaSPeter Zijlstra SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax 2216fd166aaSPeter Zijlstra popq %rax 2226fd166aaSPeter Zijlstra .endm 2236fd166aaSPeter Zijlstra 2248a09317bSDave Hansen .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 225aa8c6248SThomas Gleixner ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI 2268a09317bSDave Hansen movq %cr3, \scratch_reg 2278a09317bSDave Hansen movq \scratch_reg, \save_reg 2288a09317bSDave Hansen /* 229f10ee3dcSThomas Gleixner * Test the user pagetable bit. If set, then the user page tables 230f10ee3dcSThomas Gleixner * are active. If clear CR3 already has the kernel page table 231f10ee3dcSThomas Gleixner * active. 2328a09317bSDave Hansen */ 233f10ee3dcSThomas Gleixner bt $PTI_USER_PGTABLE_BIT, \scratch_reg 234f10ee3dcSThomas Gleixner jnc .Ldone_\@ 2358a09317bSDave Hansen 2368a09317bSDave Hansen ADJUST_KERNEL_CR3 \scratch_reg 2378a09317bSDave Hansen movq \scratch_reg, %cr3 2388a09317bSDave Hansen 2398a09317bSDave Hansen .Ldone_\@: 2408a09317bSDave Hansen .endm 2418a09317bSDave Hansen 24221e94459SPeter Zijlstra .macro RESTORE_CR3 scratch_reg:req save_reg:req 243aa8c6248SThomas Gleixner ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI 24421e94459SPeter Zijlstra 24521e94459SPeter Zijlstra ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID 24621e94459SPeter Zijlstra 24721e94459SPeter Zijlstra /* 24821e94459SPeter Zijlstra * KERNEL pages can always resume with NOFLUSH as we do 24921e94459SPeter Zijlstra * explicit flushes. 25021e94459SPeter Zijlstra */ 251f10ee3dcSThomas Gleixner bt $PTI_USER_PGTABLE_BIT, \save_reg 25221e94459SPeter Zijlstra jnc .Lnoflush_\@ 25321e94459SPeter Zijlstra 25421e94459SPeter Zijlstra /* 25521e94459SPeter Zijlstra * Check if there's a pending flush for the user ASID we're 25621e94459SPeter Zijlstra * about to set. 25721e94459SPeter Zijlstra */ 25821e94459SPeter Zijlstra movq \save_reg, \scratch_reg 25921e94459SPeter Zijlstra andq $(0x7FF), \scratch_reg 26021e94459SPeter Zijlstra bt \scratch_reg, THIS_CPU_user_pcid_flush_mask 26121e94459SPeter Zijlstra jnc .Lnoflush_\@ 26221e94459SPeter Zijlstra 26321e94459SPeter Zijlstra btr \scratch_reg, THIS_CPU_user_pcid_flush_mask 26421e94459SPeter Zijlstra jmp .Lwrcr3_\@ 26521e94459SPeter Zijlstra 26621e94459SPeter Zijlstra .Lnoflush_\@: 26721e94459SPeter Zijlstra SET_NOFLUSH_BIT \save_reg 26821e94459SPeter Zijlstra 26921e94459SPeter Zijlstra .Lwrcr3_\@: 2708a09317bSDave Hansen /* 2718a09317bSDave Hansen * The CR3 write could be avoided when not changing its value, 2728a09317bSDave Hansen * but would require a CR3 read *and* a scratch register. 2738a09317bSDave Hansen */ 2748a09317bSDave Hansen movq \save_reg, %cr3 275aa8c6248SThomas Gleixner .Lend_\@: 2768a09317bSDave Hansen .endm 2778a09317bSDave Hansen 2788a09317bSDave Hansen #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */ 2798a09317bSDave Hansen 2808a09317bSDave Hansen .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req 2818a09317bSDave Hansen .endm 2826fd166aaSPeter Zijlstra .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req 2836fd166aaSPeter Zijlstra .endm 2846fd166aaSPeter Zijlstra .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req 2858a09317bSDave Hansen .endm 2868a09317bSDave Hansen .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req 2878a09317bSDave Hansen .endm 28821e94459SPeter Zijlstra .macro RESTORE_CR3 scratch_reg:req save_reg:req 2898a09317bSDave Hansen .endm 2908a09317bSDave Hansen 2918a09317bSDave Hansen #endif 2928a09317bSDave Hansen 29318ec54fdSJosh Poimboeuf /* 29418ec54fdSJosh Poimboeuf * Mitigate Spectre v1 for conditional swapgs code paths. 29518ec54fdSJosh Poimboeuf * 29618ec54fdSJosh Poimboeuf * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to 29718ec54fdSJosh Poimboeuf * prevent a speculative swapgs when coming from kernel space. 29818ec54fdSJosh Poimboeuf * 29918ec54fdSJosh Poimboeuf * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path, 30018ec54fdSJosh Poimboeuf * to prevent the swapgs from getting speculatively skipped when coming from 30118ec54fdSJosh Poimboeuf * user space. 30218ec54fdSJosh Poimboeuf */ 30318ec54fdSJosh Poimboeuf .macro FENCE_SWAPGS_USER_ENTRY 30418ec54fdSJosh Poimboeuf ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER 30518ec54fdSJosh Poimboeuf .endm 30618ec54fdSJosh Poimboeuf .macro FENCE_SWAPGS_KERNEL_ENTRY 30718ec54fdSJosh Poimboeuf ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL 30818ec54fdSJosh Poimboeuf .endm 30918ec54fdSJosh Poimboeuf 310afaef01cSAlexander Popov .macro STACKLEAK_ERASE_NOCLOBBER 311afaef01cSAlexander Popov #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 312afaef01cSAlexander Popov PUSH_AND_CLEAR_REGS 313afaef01cSAlexander Popov call stackleak_erase 314afaef01cSAlexander Popov POP_REGS 315afaef01cSAlexander Popov #endif 316afaef01cSAlexander Popov .endm 317afaef01cSAlexander Popov 318c82965f9SChang S. Bae .macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req 319c82965f9SChang S. Bae rdgsbase \save_reg 320c82965f9SChang S. Bae GET_PERCPU_BASE \scratch_reg 321c82965f9SChang S. Bae wrgsbase \scratch_reg 322c82965f9SChang S. Bae .endm 323c82965f9SChang S. Bae 324633260faSThomas Gleixner #else /* CONFIG_X86_64 */ 325633260faSThomas Gleixner # undef UNWIND_HINT_IRET_REGS 326633260faSThomas Gleixner # define UNWIND_HINT_IRET_REGS 327633260faSThomas Gleixner #endif /* !CONFIG_X86_64 */ 328d36f9479SIngo Molnar 329afaef01cSAlexander Popov .macro STACKLEAK_ERASE 330afaef01cSAlexander Popov #ifdef CONFIG_GCC_PLUGIN_STACKLEAK 331afaef01cSAlexander Popov call stackleak_erase 332afaef01cSAlexander Popov #endif 333afaef01cSAlexander Popov .endm 334eaad9812SChang S. Bae 335eaad9812SChang S. Bae #ifdef CONFIG_SMP 336eaad9812SChang S. Bae 337eaad9812SChang S. Bae /* 338eaad9812SChang S. Bae * CPU/node NR is loaded from the limit (size) field of a special segment 339eaad9812SChang S. Bae * descriptor entry in GDT. 340eaad9812SChang S. Bae */ 341eaad9812SChang S. Bae .macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req 342eaad9812SChang S. Bae movq $__CPUNODE_SEG, \reg 343eaad9812SChang S. Bae lsl \reg, \reg 344eaad9812SChang S. Bae .endm 345eaad9812SChang S. Bae 346eaad9812SChang S. Bae /* 347eaad9812SChang S. Bae * Fetch the per-CPU GSBASE value for this processor and put it in @reg. 348eaad9812SChang S. Bae * We normally use %gs for accessing per-CPU data, but we are setting up 349eaad9812SChang S. Bae * %gs here and obviously can not use %gs itself to access per-CPU data. 3506a3ea3e6SSean Christopherson * 3516a3ea3e6SSean Christopherson * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and 3526a3ea3e6SSean Christopherson * may not restore the host's value until the CPU returns to userspace. 3536a3ea3e6SSean Christopherson * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives 3546a3ea3e6SSean Christopherson * while running KVM's run loop. 355eaad9812SChang S. Bae */ 356eaad9812SChang S. Bae .macro GET_PERCPU_BASE reg:req 3576a3ea3e6SSean Christopherson LOAD_CPU_AND_NODE_SEG_LIMIT \reg 358eaad9812SChang S. Bae andq $VDSO_CPUNODE_MASK, \reg 359eaad9812SChang S. Bae movq __per_cpu_offset(, \reg, 8), \reg 360eaad9812SChang S. Bae .endm 361eaad9812SChang S. Bae 362eaad9812SChang S. Bae #else 363eaad9812SChang S. Bae 364eaad9812SChang S. Bae .macro GET_PERCPU_BASE reg:req 365eaad9812SChang S. Bae movq pcpu_unit_offsets(%rip), \reg 366eaad9812SChang S. Bae .endm 367eaad9812SChang S. Bae 368eaad9812SChang S. Bae #endif /* CONFIG_SMP */ 369