1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/types.h> 3 #include "bitops.h" 4 5 #include <asm/processor-flags.h> 6 #include <asm/required-features.h> 7 #include <asm/msr-index.h> 8 #include "cpuflags.h" 9 10 struct cpu_features cpu; 11 u32 cpu_vendor[3]; 12 13 static bool loaded_flags; 14 15 static int has_fpu(void) 16 { 17 u16 fcw = -1, fsw = -1; 18 unsigned long cr0; 19 20 asm volatile("mov %%cr0,%0" : "=r" (cr0)); 21 if (cr0 & (X86_CR0_EM|X86_CR0_TS)) { 22 cr0 &= ~(X86_CR0_EM|X86_CR0_TS); 23 asm volatile("mov %0,%%cr0" : : "r" (cr0)); 24 } 25 26 asm volatile("fninit ; fnstsw %0 ; fnstcw %1" 27 : "+m" (fsw), "+m" (fcw)); 28 29 return fsw == 0 && (fcw & 0x103f) == 0x003f; 30 } 31 32 /* 33 * For building the 16-bit code we want to explicitly specify 32-bit 34 * push/pop operations, rather than just saying 'pushf' or 'popf' and 35 * letting the compiler choose. But this is also included from the 36 * compressed/ directory where it may be 64-bit code, and thus needs 37 * to be 'pushfq' or 'popfq' in that case. 38 */ 39 #ifdef __x86_64__ 40 #define PUSHF "pushfq" 41 #define POPF "popfq" 42 #else 43 #define PUSHF "pushfl" 44 #define POPF "popfl" 45 #endif 46 47 int has_eflag(unsigned long mask) 48 { 49 unsigned long f0, f1; 50 51 asm volatile(PUSHF " \n\t" 52 PUSHF " \n\t" 53 "pop %0 \n\t" 54 "mov %0,%1 \n\t" 55 "xor %2,%1 \n\t" 56 "push %1 \n\t" 57 POPF " \n\t" 58 PUSHF " \n\t" 59 "pop %1 \n\t" 60 POPF 61 : "=&r" (f0), "=&r" (f1) 62 : "ri" (mask)); 63 64 return !!((f0^f1) & mask); 65 } 66 67 /* Handle x86_32 PIC using ebx. */ 68 #if defined(__i386__) && defined(__PIC__) 69 # define EBX_REG "=r" 70 #else 71 # define EBX_REG "=b" 72 #endif 73 74 static inline void cpuid_count(u32 id, u32 count, 75 u32 *a, u32 *b, u32 *c, u32 *d) 76 { 77 asm volatile(".ifnc %%ebx,%3 ; movl %%ebx,%3 ; .endif \n\t" 78 "cpuid \n\t" 79 ".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif \n\t" 80 : "=a" (*a), "=c" (*c), "=d" (*d), EBX_REG (*b) 81 : "a" (id), "c" (count) 82 ); 83 } 84 85 #define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d) 86 87 void get_cpuflags(void) 88 { 89 u32 max_intel_level, max_amd_level; 90 u32 tfms; 91 u32 ignored; 92 93 if (loaded_flags) 94 return; 95 loaded_flags = true; 96 97 if (has_fpu()) 98 set_bit(X86_FEATURE_FPU, cpu.flags); 99 100 if (has_eflag(X86_EFLAGS_ID)) { 101 cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2], 102 &cpu_vendor[1]); 103 104 if (max_intel_level >= 0x00000001 && 105 max_intel_level <= 0x0000ffff) { 106 cpuid(0x1, &tfms, &ignored, &cpu.flags[4], 107 &cpu.flags[0]); 108 cpu.level = (tfms >> 8) & 15; 109 cpu.family = cpu.level; 110 cpu.model = (tfms >> 4) & 15; 111 if (cpu.level >= 6) 112 cpu.model += ((tfms >> 16) & 0xf) << 4; 113 } 114 115 if (max_intel_level >= 0x00000007) { 116 cpuid_count(0x00000007, 0, &ignored, &ignored, 117 &cpu.flags[16], &ignored); 118 } 119 120 cpuid(0x80000000, &max_amd_level, &ignored, &ignored, 121 &ignored); 122 123 if (max_amd_level >= 0x80000001 && 124 max_amd_level <= 0x8000ffff) { 125 cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6], 126 &cpu.flags[1]); 127 } 128 } 129 } 130