1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AMD Encrypted Register State Support 4 * 5 * Author: Joerg Roedel <jroedel@suse.de> 6 */ 7 8 /* 9 * misc.h needs to be first because it knows how to include the other kernel 10 * headers in the pre-decompression code in a way that does not break 11 * compilation. 12 */ 13 #include "misc.h" 14 15 #include <asm/pgtable_types.h> 16 #include <asm/sev.h> 17 #include <asm/trapnr.h> 18 #include <asm/trap_pf.h> 19 #include <asm/msr-index.h> 20 #include <asm/fpu/xcr.h> 21 #include <asm/ptrace.h> 22 #include <asm/svm.h> 23 24 #include "error.h" 25 26 struct ghcb boot_ghcb_page __aligned(PAGE_SIZE); 27 struct ghcb *boot_ghcb; 28 29 /* 30 * Copy a version of this function here - insn-eval.c can't be used in 31 * pre-decompression code. 32 */ 33 static bool insn_has_rep_prefix(struct insn *insn) 34 { 35 insn_byte_t p; 36 int i; 37 38 insn_get_prefixes(insn); 39 40 for_each_insn_prefix(insn, i, p) { 41 if (p == 0xf2 || p == 0xf3) 42 return true; 43 } 44 45 return false; 46 } 47 48 /* 49 * Only a dummy for insn_get_seg_base() - Early boot-code is 64bit only and 50 * doesn't use segments. 51 */ 52 static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx) 53 { 54 return 0UL; 55 } 56 57 static inline u64 sev_es_rd_ghcb_msr(void) 58 { 59 unsigned long low, high; 60 61 asm volatile("rdmsr" : "=a" (low), "=d" (high) : 62 "c" (MSR_AMD64_SEV_ES_GHCB)); 63 64 return ((high << 32) | low); 65 } 66 67 static inline void sev_es_wr_ghcb_msr(u64 val) 68 { 69 u32 low, high; 70 71 low = val & 0xffffffffUL; 72 high = val >> 32; 73 74 asm volatile("wrmsr" : : "c" (MSR_AMD64_SEV_ES_GHCB), 75 "a"(low), "d" (high) : "memory"); 76 } 77 78 static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) 79 { 80 char buffer[MAX_INSN_SIZE]; 81 int ret; 82 83 memcpy(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE); 84 85 ret = insn_decode(&ctxt->insn, buffer, MAX_INSN_SIZE, INSN_MODE_64); 86 if (ret < 0) 87 return ES_DECODE_FAILED; 88 89 return ES_OK; 90 } 91 92 static enum es_result vc_write_mem(struct es_em_ctxt *ctxt, 93 void *dst, char *buf, size_t size) 94 { 95 memcpy(dst, buf, size); 96 97 return ES_OK; 98 } 99 100 static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, 101 void *src, char *buf, size_t size) 102 { 103 memcpy(buf, src, size); 104 105 return ES_OK; 106 } 107 108 #undef __init 109 #undef __pa 110 #define __init 111 #define __pa(x) ((unsigned long)(x)) 112 113 #define __BOOT_COMPRESSED 114 115 /* Basic instruction decoding support needed */ 116 #include "../../lib/inat.c" 117 #include "../../lib/insn.c" 118 119 /* Include code for early handlers */ 120 #include "../../kernel/sev-shared.c" 121 122 static bool early_setup_sev_es(void) 123 { 124 if (!sev_es_negotiate_protocol()) 125 sev_es_terminate(GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED); 126 127 if (set_page_decrypted((unsigned long)&boot_ghcb_page)) 128 return false; 129 130 /* Page is now mapped decrypted, clear it */ 131 memset(&boot_ghcb_page, 0, sizeof(boot_ghcb_page)); 132 133 boot_ghcb = &boot_ghcb_page; 134 135 /* Initialize lookup tables for the instruction decoder */ 136 inat_init_tables(); 137 138 return true; 139 } 140 141 void sev_es_shutdown_ghcb(void) 142 { 143 if (!boot_ghcb) 144 return; 145 146 if (!sev_es_check_cpu_features()) 147 error("SEV-ES CPU Features missing."); 148 149 /* 150 * GHCB Page must be flushed from the cache and mapped encrypted again. 151 * Otherwise the running kernel will see strange cache effects when 152 * trying to use that page. 153 */ 154 if (set_page_encrypted((unsigned long)&boot_ghcb_page)) 155 error("Can't map GHCB page encrypted"); 156 157 /* 158 * GHCB page is mapped encrypted again and flushed from the cache. 159 * Mark it non-present now to catch bugs when #VC exceptions trigger 160 * after this point. 161 */ 162 if (set_page_non_present((unsigned long)&boot_ghcb_page)) 163 error("Can't unmap GHCB page"); 164 } 165 166 bool sev_es_check_ghcb_fault(unsigned long address) 167 { 168 /* Check whether the fault was on the GHCB page */ 169 return ((address & PAGE_MASK) == (unsigned long)&boot_ghcb_page); 170 } 171 172 void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) 173 { 174 struct es_em_ctxt ctxt; 175 enum es_result result; 176 177 if (!boot_ghcb && !early_setup_sev_es()) 178 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); 179 180 vc_ghcb_invalidate(boot_ghcb); 181 result = vc_init_em_ctxt(&ctxt, regs, exit_code); 182 if (result != ES_OK) 183 goto finish; 184 185 switch (exit_code) { 186 case SVM_EXIT_RDTSC: 187 case SVM_EXIT_RDTSCP: 188 result = vc_handle_rdtsc(boot_ghcb, &ctxt, exit_code); 189 break; 190 case SVM_EXIT_IOIO: 191 result = vc_handle_ioio(boot_ghcb, &ctxt); 192 break; 193 case SVM_EXIT_CPUID: 194 result = vc_handle_cpuid(boot_ghcb, &ctxt); 195 break; 196 default: 197 result = ES_UNSUPPORTED; 198 break; 199 } 200 201 finish: 202 if (result == ES_OK) 203 vc_finish_insn(&ctxt); 204 else if (result != ES_RETRY) 205 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); 206 } 207