1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/boot/head.S 4 * 5 * Copyright (C) 1991, 1992, 1993 Linus Torvalds 6 */ 7 8/* 9 * head.S contains the 32-bit startup code. 10 * 11 * NOTE!!! Startup happens at absolute address 0x00001000, which is also where 12 * the page directory will exist. The startup code will be overwritten by 13 * the page directory. [According to comments etc elsewhere on a compressed 14 * kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC] 15 * 16 * Page 0 is deliberately kept safe, since System Management Mode code in 17 * laptops may need to access the BIOS data stored there. This is also 18 * useful for future device drivers that either access the BIOS via VM86 19 * mode. 20 */ 21 22/* 23 * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996 24 */ 25 .code32 26 .text 27 28#include <linux/init.h> 29#include <linux/linkage.h> 30#include <asm/segment.h> 31#include <asm/boot.h> 32#include <asm/msr.h> 33#include <asm/processor-flags.h> 34#include <asm/asm-offsets.h> 35#include <asm/bootparam.h> 36#include <asm/desc_defs.h> 37#include <asm/trapnr.h> 38#include "pgtable.h" 39 40/* 41 * Locally defined symbols should be marked hidden: 42 */ 43 .hidden _bss 44 .hidden _ebss 45 .hidden _end 46 47 __HEAD 48 49/* 50 * This macro gives the relative virtual address of X, i.e. the offset of X 51 * from startup_32. This is the same as the link-time virtual address of X, 52 * since startup_32 is at 0, but defining it this way tells the 53 * assembler/linker that we do not want the actual run-time address of X. This 54 * prevents the linker from trying to create unwanted run-time relocation 55 * entries for the reference when the compressed kernel is linked as PIE. 56 * 57 * A reference X(%reg) will result in the link-time VA of X being stored with 58 * the instruction, and a run-time R_X86_64_RELATIVE relocation entry that 59 * adds the 64-bit base address where the kernel is loaded. 60 * 61 * Replacing it with (X-startup_32)(%reg) results in the offset being stored, 62 * and no run-time relocation. 63 * 64 * The macro should be used as a displacement with a base register containing 65 * the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate 66 * [$ rva(X)]. 67 * 68 * This macro can only be used from within the .head.text section, since the 69 * expression requires startup_32 to be in the same section as the code being 70 * assembled. 71 */ 72#define rva(X) ((X) - startup_32) 73 74 .code32 75SYM_FUNC_START(startup_32) 76 /* 77 * 32bit entry is 0 and it is ABI so immutable! 78 * If we come here directly from a bootloader, 79 * kernel(text+data+bss+brk) ramdisk, zero_page, command line 80 * all need to be under the 4G limit. 81 */ 82 cld 83 cli 84 85/* 86 * Calculate the delta between where we were compiled to run 87 * at and where we were actually loaded at. This can only be done 88 * with a short local call on x86. Nothing else will tell us what 89 * address we are running at. The reserved chunk of the real-mode 90 * data at 0x1e4 (defined as a scratch field) are used as the stack 91 * for this calculation. Only 4 bytes are needed. 92 */ 93 leal (BP_scratch+4)(%esi), %esp 94 call 1f 951: popl %ebp 96 subl $ rva(1b), %ebp 97 98 /* Load new GDT with the 64bit segments using 32bit descriptor */ 99 leal rva(gdt)(%ebp), %eax 100 movl %eax, 2(%eax) 101 lgdt (%eax) 102 103 /* Load segment registers with our descriptors */ 104 movl $__BOOT_DS, %eax 105 movl %eax, %ds 106 movl %eax, %es 107 movl %eax, %fs 108 movl %eax, %gs 109 movl %eax, %ss 110 111 /* Setup a stack and load CS from current GDT */ 112 leal rva(boot_stack_end)(%ebp), %esp 113 114 pushl $__KERNEL32_CS 115 leal rva(1f)(%ebp), %eax 116 pushl %eax 117 lretl 1181: 119 120 /* Setup Exception handling for SEV-ES */ 121 call startup32_load_idt 122 123 /* Make sure cpu supports long mode. */ 124 call verify_cpu 125 testl %eax, %eax 126 jnz .Lno_longmode 127 128/* 129 * Compute the delta between where we were compiled to run at 130 * and where the code will actually run at. 131 * 132 * %ebp contains the address we are loaded at by the boot loader and %ebx 133 * contains the address where we should move the kernel image temporarily 134 * for safe in-place decompression. 135 */ 136 137#ifdef CONFIG_RELOCATABLE 138 movl %ebp, %ebx 139 140#ifdef CONFIG_EFI_STUB 141/* 142 * If we were loaded via the EFI LoadImage service, startup_32 will be at an 143 * offset to the start of the space allocated for the image. efi_pe_entry will 144 * set up image_offset to tell us where the image actually starts, so that we 145 * can use the full available buffer. 146 * image_offset = startup_32 - image_base 147 * Otherwise image_offset will be zero and has no effect on the calculations. 148 */ 149 subl rva(image_offset)(%ebp), %ebx 150#endif 151 152 movl BP_kernel_alignment(%esi), %eax 153 decl %eax 154 addl %eax, %ebx 155 notl %eax 156 andl %eax, %ebx 157 cmpl $LOAD_PHYSICAL_ADDR, %ebx 158 jae 1f 159#endif 160 movl $LOAD_PHYSICAL_ADDR, %ebx 1611: 162 163 /* Target address to relocate to for decompression */ 164 addl BP_init_size(%esi), %ebx 165 subl $ rva(_end), %ebx 166 167/* 168 * Prepare for entering 64 bit mode 169 */ 170 171 /* Enable PAE mode */ 172 movl %cr4, %eax 173 orl $X86_CR4_PAE, %eax 174 movl %eax, %cr4 175 176 /* 177 * Build early 4G boot pagetable 178 */ 179 /* 180 * If SEV is active then set the encryption mask in the page tables. 181 * This will insure that when the kernel is copied and decompressed 182 * it will be done so encrypted. 183 */ 184 call get_sev_encryption_bit 185 xorl %edx, %edx 186#ifdef CONFIG_AMD_MEM_ENCRYPT 187 testl %eax, %eax 188 jz 1f 189 subl $32, %eax /* Encryption bit is always above bit 31 */ 190 bts %eax, %edx /* Set encryption mask for page tables */ 191 /* 192 * Set MSR_AMD64_SEV_ENABLED_BIT in sev_status so that 193 * startup32_check_sev_cbit() will do a check. sev_enable() will 194 * initialize sev_status with all the bits reported by 195 * MSR_AMD_SEV_STATUS later, but only MSR_AMD64_SEV_ENABLED_BIT 196 * needs to be set for now. 197 */ 198 movl $1, rva(sev_status)(%ebp) 1991: 200#endif 201 202 /* Initialize Page tables to 0 */ 203 leal rva(pgtable)(%ebx), %edi 204 xorl %eax, %eax 205 movl $(BOOT_INIT_PGT_SIZE/4), %ecx 206 rep stosl 207 208 /* Build Level 4 */ 209 leal rva(pgtable + 0)(%ebx), %edi 210 leal 0x1007 (%edi), %eax 211 movl %eax, 0(%edi) 212 addl %edx, 4(%edi) 213 214 /* Build Level 3 */ 215 leal rva(pgtable + 0x1000)(%ebx), %edi 216 leal 0x1007(%edi), %eax 217 movl $4, %ecx 2181: movl %eax, 0x00(%edi) 219 addl %edx, 0x04(%edi) 220 addl $0x00001000, %eax 221 addl $8, %edi 222 decl %ecx 223 jnz 1b 224 225 /* Build Level 2 */ 226 leal rva(pgtable + 0x2000)(%ebx), %edi 227 movl $0x00000183, %eax 228 movl $2048, %ecx 2291: movl %eax, 0(%edi) 230 addl %edx, 4(%edi) 231 addl $0x00200000, %eax 232 addl $8, %edi 233 decl %ecx 234 jnz 1b 235 236 /* Enable the boot page tables */ 237 leal rva(pgtable)(%ebx), %eax 238 movl %eax, %cr3 239 240 /* Enable Long mode in EFER (Extended Feature Enable Register) */ 241 movl $MSR_EFER, %ecx 242 rdmsr 243 btsl $_EFER_LME, %eax 244 wrmsr 245 246 /* After gdt is loaded */ 247 xorl %eax, %eax 248 lldt %ax 249 movl $__BOOT_TSS, %eax 250 ltr %ax 251 252 /* 253 * Setup for the jump to 64bit mode 254 * 255 * When the jump is performed we will be in long mode but 256 * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1 257 * (and in turn EFER.LMA = 1). To jump into 64bit mode we use 258 * the new gdt/idt that has __KERNEL_CS with CS.L = 1. 259 * We place all of the values on our mini stack so lret can 260 * used to perform that far jump. 261 */ 262 leal rva(startup_64)(%ebp), %eax 263#ifdef CONFIG_EFI_MIXED 264 movl rva(efi32_boot_args)(%ebp), %edi 265 testl %edi, %edi 266 jz 1f 267 leal rva(efi64_stub_entry)(%ebp), %eax 268 movl rva(efi32_boot_args+4)(%ebp), %esi 269 movl rva(efi32_boot_args+8)(%ebp), %edx // saved bootparams pointer 270 testl %edx, %edx 271 jnz 1f 272 /* 273 * efi_pe_entry uses MS calling convention, which requires 32 bytes of 274 * shadow space on the stack even if all arguments are passed in 275 * registers. We also need an additional 8 bytes for the space that 276 * would be occupied by the return address, and this also results in 277 * the correct stack alignment for entry. 278 */ 279 subl $40, %esp 280 leal rva(efi_pe_entry)(%ebp), %eax 281 movl %edi, %ecx // MS calling convention 282 movl %esi, %edx 2831: 284#endif 285 /* Check if the C-bit position is correct when SEV is active */ 286 call startup32_check_sev_cbit 287 288 pushl $__KERNEL_CS 289 pushl %eax 290 291 /* Enter paged protected Mode, activating Long Mode */ 292 movl $CR0_STATE, %eax 293 movl %eax, %cr0 294 295 /* Jump from 32bit compatibility mode into 64bit mode. */ 296 lret 297SYM_FUNC_END(startup_32) 298 299#ifdef CONFIG_EFI_MIXED 300 .org 0x190 301SYM_FUNC_START(efi32_stub_entry) 302 add $0x4, %esp /* Discard return address */ 303 popl %ecx 304 popl %edx 305 popl %esi 306 307 call 1f 3081: pop %ebp 309 subl $ rva(1b), %ebp 310 311 movl %esi, rva(efi32_boot_args+8)(%ebp) 312SYM_INNER_LABEL(efi32_pe_stub_entry, SYM_L_LOCAL) 313 movl %ecx, rva(efi32_boot_args)(%ebp) 314 movl %edx, rva(efi32_boot_args+4)(%ebp) 315 movb $0, rva(efi_is64)(%ebp) 316 317 /* Save firmware GDTR and code/data selectors */ 318 sgdtl rva(efi32_boot_gdt)(%ebp) 319 movw %cs, rva(efi32_boot_cs)(%ebp) 320 movw %ds, rva(efi32_boot_ds)(%ebp) 321 322 /* Store firmware IDT descriptor */ 323 sidtl rva(efi32_boot_idt)(%ebp) 324 325 /* Disable paging */ 326 movl %cr0, %eax 327 btrl $X86_CR0_PG_BIT, %eax 328 movl %eax, %cr0 329 330 jmp startup_32 331SYM_FUNC_END(efi32_stub_entry) 332#endif 333 334 .code64 335 .org 0x200 336SYM_CODE_START(startup_64) 337 /* 338 * 64bit entry is 0x200 and it is ABI so immutable! 339 * We come here either from startup_32 or directly from a 340 * 64bit bootloader. 341 * If we come here from a bootloader, kernel(text+data+bss+brk), 342 * ramdisk, zero_page, command line could be above 4G. 343 * We depend on an identity mapped page table being provided 344 * that maps our entire kernel(text+data+bss+brk), zero page 345 * and command line. 346 */ 347 348 cld 349 cli 350 351 /* Setup data segments. */ 352 xorl %eax, %eax 353 movl %eax, %ds 354 movl %eax, %es 355 movl %eax, %ss 356 movl %eax, %fs 357 movl %eax, %gs 358 359 /* 360 * Compute the decompressed kernel start address. It is where 361 * we were loaded at aligned to a 2M boundary. %rbp contains the 362 * decompressed kernel start address. 363 * 364 * If it is a relocatable kernel then decompress and run the kernel 365 * from load address aligned to 2MB addr, otherwise decompress and 366 * run the kernel from LOAD_PHYSICAL_ADDR 367 * 368 * We cannot rely on the calculation done in 32-bit mode, since we 369 * may have been invoked via the 64-bit entry point. 370 */ 371 372 /* Start with the delta to where the kernel will run at. */ 373#ifdef CONFIG_RELOCATABLE 374 leaq startup_32(%rip) /* - $startup_32 */, %rbp 375 376#ifdef CONFIG_EFI_STUB 377/* 378 * If we were loaded via the EFI LoadImage service, startup_32 will be at an 379 * offset to the start of the space allocated for the image. efi_pe_entry will 380 * set up image_offset to tell us where the image actually starts, so that we 381 * can use the full available buffer. 382 * image_offset = startup_32 - image_base 383 * Otherwise image_offset will be zero and has no effect on the calculations. 384 */ 385 movl image_offset(%rip), %eax 386 subq %rax, %rbp 387#endif 388 389 movl BP_kernel_alignment(%rsi), %eax 390 decl %eax 391 addq %rax, %rbp 392 notq %rax 393 andq %rax, %rbp 394 cmpq $LOAD_PHYSICAL_ADDR, %rbp 395 jae 1f 396#endif 397 movq $LOAD_PHYSICAL_ADDR, %rbp 3981: 399 400 /* Target address to relocate to for decompression */ 401 movl BP_init_size(%rsi), %ebx 402 subl $ rva(_end), %ebx 403 addq %rbp, %rbx 404 405 /* Set up the stack */ 406 leaq rva(boot_stack_end)(%rbx), %rsp 407 408 /* 409 * At this point we are in long mode with 4-level paging enabled, 410 * but we might want to enable 5-level paging or vice versa. 411 * 412 * The problem is that we cannot do it directly. Setting or clearing 413 * CR4.LA57 in long mode would trigger #GP. So we need to switch off 414 * long mode and paging first. 415 * 416 * We also need a trampoline in lower memory to switch over from 417 * 4- to 5-level paging for cases when the bootloader puts the kernel 418 * above 4G, but didn't enable 5-level paging for us. 419 * 420 * The same trampoline can be used to switch from 5- to 4-level paging 421 * mode, like when starting 4-level paging kernel via kexec() when 422 * original kernel worked in 5-level paging mode. 423 * 424 * For the trampoline, we need the top page table to reside in lower 425 * memory as we don't have a way to load 64-bit values into CR3 in 426 * 32-bit mode. 427 * 428 * We go though the trampoline even if we don't have to: if we're 429 * already in a desired paging mode. This way the trampoline code gets 430 * tested on every boot. 431 */ 432 433 /* Make sure we have GDT with 32-bit code segment */ 434 leaq gdt64(%rip), %rax 435 addq %rax, 2(%rax) 436 lgdt (%rax) 437 438 /* Reload CS so IRET returns to a CS actually in the GDT */ 439 pushq $__KERNEL_CS 440 leaq .Lon_kernel_cs(%rip), %rax 441 pushq %rax 442 lretq 443 444.Lon_kernel_cs: 445 446 pushq %rsi 447 call load_stage1_idt 448 popq %rsi 449 450#ifdef CONFIG_AMD_MEM_ENCRYPT 451 /* 452 * Now that the stage1 interrupt handlers are set up, #VC exceptions from 453 * CPUID instructions can be properly handled for SEV-ES guests. 454 * 455 * For SEV-SNP, the CPUID table also needs to be set up in advance of any 456 * CPUID instructions being issued, so go ahead and do that now via 457 * sev_enable(), which will also handle the rest of the SEV-related 458 * detection/setup to ensure that has been done in advance of any dependent 459 * code. 460 */ 461 pushq %rsi 462 movq %rsi, %rdi /* real mode address */ 463 call sev_enable 464 popq %rsi 465#endif 466 467 /* 468 * paging_prepare() sets up the trampoline and checks if we need to 469 * enable 5-level paging. 470 * 471 * paging_prepare() returns a two-quadword structure which lands 472 * into RDX:RAX: 473 * - Address of the trampoline is returned in RAX. 474 * - Non zero RDX means trampoline needs to enable 5-level 475 * paging. 476 * 477 * RSI holds real mode data and needs to be preserved across 478 * this function call. 479 */ 480 pushq %rsi 481 movq %rsi, %rdi /* real mode address */ 482 call paging_prepare 483 popq %rsi 484 485 /* Save the trampoline address in RCX */ 486 movq %rax, %rcx 487 488 /* 489 * Load the address of trampoline_return() into RDI. 490 * It will be used by the trampoline to return to the main code. 491 */ 492 leaq trampoline_return(%rip), %rdi 493 494 /* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */ 495 pushq $__KERNEL32_CS 496 leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax 497 pushq %rax 498 lretq 499trampoline_return: 500 /* Restore the stack, the 32-bit trampoline uses its own stack */ 501 leaq rva(boot_stack_end)(%rbx), %rsp 502 503 /* 504 * cleanup_trampoline() would restore trampoline memory. 505 * 506 * RDI is address of the page table to use instead of page table 507 * in trampoline memory (if required). 508 * 509 * RSI holds real mode data and needs to be preserved across 510 * this function call. 511 */ 512 pushq %rsi 513 leaq rva(top_pgtable)(%rbx), %rdi 514 call cleanup_trampoline 515 popq %rsi 516 517 /* Zero EFLAGS */ 518 pushq $0 519 popfq 520 521/* 522 * Copy the compressed kernel to the end of our buffer 523 * where decompression in place becomes safe. 524 */ 525 pushq %rsi 526 leaq (_bss-8)(%rip), %rsi 527 leaq rva(_bss-8)(%rbx), %rdi 528 movl $(_bss - startup_32), %ecx 529 shrl $3, %ecx 530 std 531 rep movsq 532 cld 533 popq %rsi 534 535 /* 536 * The GDT may get overwritten either during the copy we just did or 537 * during extract_kernel below. To avoid any issues, repoint the GDTR 538 * to the new copy of the GDT. 539 */ 540 leaq rva(gdt64)(%rbx), %rax 541 leaq rva(gdt)(%rbx), %rdx 542 movq %rdx, 2(%rax) 543 lgdt (%rax) 544 545/* 546 * Jump to the relocated address. 547 */ 548 leaq rva(.Lrelocated)(%rbx), %rax 549 jmp *%rax 550SYM_CODE_END(startup_64) 551 552#ifdef CONFIG_EFI_STUB 553 .org 0x390 554SYM_FUNC_START(efi64_stub_entry) 555 and $~0xf, %rsp /* realign the stack */ 556 movq %rdx, %rbx /* save boot_params pointer */ 557 call efi_main 558 movq %rbx,%rsi 559 leaq rva(startup_64)(%rax), %rax 560 jmp *%rax 561SYM_FUNC_END(efi64_stub_entry) 562SYM_FUNC_ALIAS(efi_stub_entry, efi64_stub_entry) 563#endif 564 565 .text 566SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) 567 568/* 569 * Clear BSS (stack is currently empty) 570 */ 571 xorl %eax, %eax 572 leaq _bss(%rip), %rdi 573 leaq _ebss(%rip), %rcx 574 subq %rdi, %rcx 575 shrq $3, %rcx 576 rep stosq 577 578 pushq %rsi 579 call load_stage2_idt 580 581 /* Pass boot_params to initialize_identity_maps() */ 582 movq (%rsp), %rdi 583 call initialize_identity_maps 584 popq %rsi 585 586/* 587 * Do the extraction, and jump to the new kernel.. 588 */ 589 pushq %rsi /* Save the real mode argument */ 590 movq %rsi, %rdi /* real mode address */ 591 leaq boot_heap(%rip), %rsi /* malloc area for uncompression */ 592 leaq input_data(%rip), %rdx /* input_data */ 593 movl input_len(%rip), %ecx /* input_len */ 594 movq %rbp, %r8 /* output target address */ 595 movl output_len(%rip), %r9d /* decompressed length, end of relocs */ 596 call extract_kernel /* returns kernel location in %rax */ 597 popq %rsi 598 599/* 600 * Jump to the decompressed kernel. 601 */ 602 jmp *%rax 603SYM_FUNC_END(.Lrelocated) 604 605 .code32 606/* 607 * This is the 32-bit trampoline that will be copied over to low memory. 608 * 609 * RDI contains the return address (might be above 4G). 610 * ECX contains the base address of the trampoline memory. 611 * Non zero RDX means trampoline needs to enable 5-level paging. 612 */ 613SYM_CODE_START(trampoline_32bit_src) 614 /* Set up data and stack segments */ 615 movl $__KERNEL_DS, %eax 616 movl %eax, %ds 617 movl %eax, %ss 618 619 /* Set up new stack */ 620 leal TRAMPOLINE_32BIT_STACK_END(%ecx), %esp 621 622 /* Disable paging */ 623 movl %cr0, %eax 624 btrl $X86_CR0_PG_BIT, %eax 625 movl %eax, %cr0 626 627 /* Check what paging mode we want to be in after the trampoline */ 628 testl %edx, %edx 629 jz 1f 630 631 /* We want 5-level paging: don't touch CR3 if it already points to 5-level page tables */ 632 movl %cr4, %eax 633 testl $X86_CR4_LA57, %eax 634 jnz 3f 635 jmp 2f 6361: 637 /* We want 4-level paging: don't touch CR3 if it already points to 4-level page tables */ 638 movl %cr4, %eax 639 testl $X86_CR4_LA57, %eax 640 jz 3f 6412: 642 /* Point CR3 to the trampoline's new top level page table */ 643 leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%ecx), %eax 644 movl %eax, %cr3 6453: 646 /* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */ 647 pushl %ecx 648 pushl %edx 649 movl $MSR_EFER, %ecx 650 rdmsr 651 btsl $_EFER_LME, %eax 652 /* Avoid writing EFER if no change was made (for TDX guest) */ 653 jc 1f 654 wrmsr 6551: popl %edx 656 popl %ecx 657 658#ifdef CONFIG_X86_MCE 659 /* 660 * Preserve CR4.MCE if the kernel will enable #MC support. 661 * Clearing MCE may fault in some environments (that also force #MC 662 * support). Any machine check that occurs before #MC support is fully 663 * configured will crash the system regardless of the CR4.MCE value set 664 * here. 665 */ 666 movl %cr4, %eax 667 andl $X86_CR4_MCE, %eax 668#else 669 movl $0, %eax 670#endif 671 672 /* Enable PAE and LA57 (if required) paging modes */ 673 orl $X86_CR4_PAE, %eax 674 testl %edx, %edx 675 jz 1f 676 orl $X86_CR4_LA57, %eax 6771: 678 movl %eax, %cr4 679 680 /* Calculate address of paging_enabled() once we are executing in the trampoline */ 681 leal .Lpaging_enabled - trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_OFFSET(%ecx), %eax 682 683 /* Prepare the stack for far return to Long Mode */ 684 pushl $__KERNEL_CS 685 pushl %eax 686 687 /* Enable paging again. */ 688 movl %cr0, %eax 689 btsl $X86_CR0_PG_BIT, %eax 690 movl %eax, %cr0 691 692 lret 693SYM_CODE_END(trampoline_32bit_src) 694 695 .code64 696SYM_FUNC_START_LOCAL_NOALIGN(.Lpaging_enabled) 697 /* Return from the trampoline */ 698 jmp *%rdi 699SYM_FUNC_END(.Lpaging_enabled) 700 701 /* 702 * The trampoline code has a size limit. 703 * Make sure we fail to compile if the trampoline code grows 704 * beyond TRAMPOLINE_32BIT_CODE_SIZE bytes. 705 */ 706 .org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE 707 708 .code32 709SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode) 710 /* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */ 7111: 712 hlt 713 jmp 1b 714SYM_FUNC_END(.Lno_longmode) 715 716#include "../../kernel/verify_cpu.S" 717 718 .data 719SYM_DATA_START_LOCAL(gdt64) 720 .word gdt_end - gdt - 1 721 .quad gdt - gdt64 722SYM_DATA_END(gdt64) 723 .balign 8 724SYM_DATA_START_LOCAL(gdt) 725 .word gdt_end - gdt - 1 726 .long 0 727 .word 0 728 .quad 0x00cf9a000000ffff /* __KERNEL32_CS */ 729 .quad 0x00af9a000000ffff /* __KERNEL_CS */ 730 .quad 0x00cf92000000ffff /* __KERNEL_DS */ 731 .quad 0x0080890000000000 /* TS descriptor */ 732 .quad 0x0000000000000000 /* TS continued */ 733SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end) 734 735SYM_DATA_START(boot_idt_desc) 736 .word boot_idt_end - boot_idt - 1 737 .quad 0 738SYM_DATA_END(boot_idt_desc) 739 .balign 8 740SYM_DATA_START(boot_idt) 741 .rept BOOT_IDT_ENTRIES 742 .quad 0 743 .quad 0 744 .endr 745SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end) 746 747#ifdef CONFIG_AMD_MEM_ENCRYPT 748SYM_DATA_START(boot32_idt_desc) 749 .word boot32_idt_end - boot32_idt - 1 750 .long 0 751SYM_DATA_END(boot32_idt_desc) 752 .balign 8 753SYM_DATA_START(boot32_idt) 754 .rept 32 755 .quad 0 756 .endr 757SYM_DATA_END_LABEL(boot32_idt, SYM_L_GLOBAL, boot32_idt_end) 758#endif 759 760#ifdef CONFIG_EFI_STUB 761SYM_DATA(image_offset, .long 0) 762#endif 763#ifdef CONFIG_EFI_MIXED 764SYM_DATA_LOCAL(efi32_boot_args, .long 0, 0, 0) 765SYM_DATA(efi_is64, .byte 1) 766 767#define ST32_boottime 60 // offsetof(efi_system_table_32_t, boottime) 768#define BS32_handle_protocol 88 // offsetof(efi_boot_services_32_t, handle_protocol) 769#define LI32_image_base 32 // offsetof(efi_loaded_image_32_t, image_base) 770 771 __HEAD 772 .code32 773SYM_FUNC_START(efi32_pe_entry) 774/* 775 * efi_status_t efi32_pe_entry(efi_handle_t image_handle, 776 * efi_system_table_32_t *sys_table) 777 */ 778 779 pushl %ebp 780 movl %esp, %ebp 781 pushl %eax // dummy push to allocate loaded_image 782 783 pushl %ebx // save callee-save registers 784 pushl %edi 785 786 call verify_cpu // check for long mode support 787 testl %eax, %eax 788 movl $0x80000003, %eax // EFI_UNSUPPORTED 789 jnz 2f 790 791 call 1f 7921: pop %ebx 793 subl $ rva(1b), %ebx 794 795 /* Get the loaded image protocol pointer from the image handle */ 796 leal -4(%ebp), %eax 797 pushl %eax // &loaded_image 798 leal rva(loaded_image_proto)(%ebx), %eax 799 pushl %eax // pass the GUID address 800 pushl 8(%ebp) // pass the image handle 801 802 /* 803 * Note the alignment of the stack frame. 804 * sys_table 805 * handle <-- 16-byte aligned on entry by ABI 806 * return address 807 * frame pointer 808 * loaded_image <-- local variable 809 * saved %ebx <-- 16-byte aligned here 810 * saved %edi 811 * &loaded_image 812 * &loaded_image_proto 813 * handle <-- 16-byte aligned for call to handle_protocol 814 */ 815 816 movl 12(%ebp), %eax // sys_table 817 movl ST32_boottime(%eax), %eax // sys_table->boottime 818 call *BS32_handle_protocol(%eax) // sys_table->boottime->handle_protocol 819 addl $12, %esp // restore argument space 820 testl %eax, %eax 821 jnz 2f 822 823 movl 8(%ebp), %ecx // image_handle 824 movl 12(%ebp), %edx // sys_table 825 movl -4(%ebp), %esi // loaded_image 826 movl LI32_image_base(%esi), %esi // loaded_image->image_base 827 movl %ebx, %ebp // startup_32 for efi32_pe_stub_entry 828 /* 829 * We need to set the image_offset variable here since startup_32() will 830 * use it before we get to the 64-bit efi_pe_entry() in C code. 831 */ 832 subl %esi, %ebx 833 movl %ebx, rva(image_offset)(%ebp) // save image_offset 834 jmp efi32_pe_stub_entry 835 8362: popl %edi // restore callee-save registers 837 popl %ebx 838 leave 839 RET 840SYM_FUNC_END(efi32_pe_entry) 841 842 .section ".rodata" 843 /* EFI loaded image protocol GUID */ 844 .balign 4 845SYM_DATA_START_LOCAL(loaded_image_proto) 846 .long 0x5b1b31a1 847 .word 0x9562, 0x11d2 848 .byte 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b 849SYM_DATA_END(loaded_image_proto) 850#endif 851 852#ifdef CONFIG_AMD_MEM_ENCRYPT 853 __HEAD 854 .code32 855/* 856 * Write an IDT entry into boot32_idt 857 * 858 * Parameters: 859 * 860 * %eax: Handler address 861 * %edx: Vector number 862 * 863 * Physical offset is expected in %ebp 864 */ 865SYM_FUNC_START(startup32_set_idt_entry) 866 push %ebx 867 push %ecx 868 869 /* IDT entry address to %ebx */ 870 leal rva(boot32_idt)(%ebp), %ebx 871 shl $3, %edx 872 addl %edx, %ebx 873 874 /* Build IDT entry, lower 4 bytes */ 875 movl %eax, %edx 876 andl $0x0000ffff, %edx # Target code segment offset [15:0] 877 movl $__KERNEL32_CS, %ecx # Target code segment selector 878 shl $16, %ecx 879 orl %ecx, %edx 880 881 /* Store lower 4 bytes to IDT */ 882 movl %edx, (%ebx) 883 884 /* Build IDT entry, upper 4 bytes */ 885 movl %eax, %edx 886 andl $0xffff0000, %edx # Target code segment offset [31:16] 887 orl $0x00008e00, %edx # Present, Type 32-bit Interrupt Gate 888 889 /* Store upper 4 bytes to IDT */ 890 movl %edx, 4(%ebx) 891 892 pop %ecx 893 pop %ebx 894 RET 895SYM_FUNC_END(startup32_set_idt_entry) 896#endif 897 898SYM_FUNC_START(startup32_load_idt) 899#ifdef CONFIG_AMD_MEM_ENCRYPT 900 /* #VC handler */ 901 leal rva(startup32_vc_handler)(%ebp), %eax 902 movl $X86_TRAP_VC, %edx 903 call startup32_set_idt_entry 904 905 /* Load IDT */ 906 leal rva(boot32_idt)(%ebp), %eax 907 movl %eax, rva(boot32_idt_desc+2)(%ebp) 908 lidt rva(boot32_idt_desc)(%ebp) 909#endif 910 RET 911SYM_FUNC_END(startup32_load_idt) 912 913/* 914 * Check for the correct C-bit position when the startup_32 boot-path is used. 915 * 916 * The check makes use of the fact that all memory is encrypted when paging is 917 * disabled. The function creates 64 bits of random data using the RDRAND 918 * instruction. RDRAND is mandatory for SEV guests, so always available. If the 919 * hypervisor violates that the kernel will crash right here. 920 * 921 * The 64 bits of random data are stored to a memory location and at the same 922 * time kept in the %eax and %ebx registers. Since encryption is always active 923 * when paging is off the random data will be stored encrypted in main memory. 924 * 925 * Then paging is enabled. When the C-bit position is correct all memory is 926 * still mapped encrypted and comparing the register values with memory will 927 * succeed. An incorrect C-bit position will map all memory unencrypted, so that 928 * the compare will use the encrypted random data and fail. 929 */ 930SYM_FUNC_START(startup32_check_sev_cbit) 931#ifdef CONFIG_AMD_MEM_ENCRYPT 932 pushl %eax 933 pushl %ebx 934 pushl %ecx 935 pushl %edx 936 937 /* Check for non-zero sev_status */ 938 movl rva(sev_status)(%ebp), %eax 939 testl %eax, %eax 940 jz 4f 941 942 /* 943 * Get two 32-bit random values - Don't bail out if RDRAND fails 944 * because it is better to prevent forward progress if no random value 945 * can be gathered. 946 */ 9471: rdrand %eax 948 jnc 1b 9492: rdrand %ebx 950 jnc 2b 951 952 /* Store to memory and keep it in the registers */ 953 movl %eax, rva(sev_check_data)(%ebp) 954 movl %ebx, rva(sev_check_data+4)(%ebp) 955 956 /* Enable paging to see if encryption is active */ 957 movl %cr0, %edx /* Backup %cr0 in %edx */ 958 movl $(X86_CR0_PG | X86_CR0_PE), %ecx /* Enable Paging and Protected mode */ 959 movl %ecx, %cr0 960 961 cmpl %eax, rva(sev_check_data)(%ebp) 962 jne 3f 963 cmpl %ebx, rva(sev_check_data+4)(%ebp) 964 jne 3f 965 966 movl %edx, %cr0 /* Restore previous %cr0 */ 967 968 jmp 4f 969 9703: /* Check failed - hlt the machine */ 971 hlt 972 jmp 3b 973 9744: 975 popl %edx 976 popl %ecx 977 popl %ebx 978 popl %eax 979#endif 980 RET 981SYM_FUNC_END(startup32_check_sev_cbit) 982 983/* 984 * Stack and heap for uncompression 985 */ 986 .bss 987 .balign 4 988SYM_DATA_LOCAL(boot_heap, .fill BOOT_HEAP_SIZE, 1, 0) 989 990SYM_DATA_START_LOCAL(boot_stack) 991 .fill BOOT_STACK_SIZE, 1, 0 992 .balign 16 993SYM_DATA_END_LABEL(boot_stack, SYM_L_LOCAL, boot_stack_end) 994 995/* 996 * Space for page tables (not in .bss so not zeroed) 997 */ 998 .section ".pgtable","aw",@nobits 999 .balign 4096 1000SYM_DATA_LOCAL(pgtable, .fill BOOT_PGT_SIZE, 1, 0) 1001 1002/* 1003 * The page table is going to be used instead of page table in the trampoline 1004 * memory. 1005 */ 1006SYM_DATA_LOCAL(top_pgtable, .fill PAGE_SIZE, 1, 0) 1007