xref: /openbmc/linux/arch/x86/Kconfig.cpu (revision a1e58bbd) 
1# Put here option for CPU selection and depending optimization
2if !X86_ELAN
3
4choice
5	prompt "Processor family"
6	default M686 if X86_32
7	default GENERIC_CPU if X86_64
8
9config M386
10	bool "386"
11	depends on X86_32 && !UML
12	---help---
13	  This is the processor type of your CPU. This information is used for
14	  optimizing purposes. In order to compile a kernel that can run on
15	  all x86 CPU types (albeit not optimally fast), you can specify
16	  "386" here.
17
18	  The kernel will not necessarily run on earlier architectures than
19	  the one you have chosen, e.g. a Pentium optimized kernel will run on
20	  a PPro, but not necessarily on a i486.
21
22	  Here are the settings recommended for greatest speed:
23	  - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
24	  486DLC/DLC2, UMC 486SX-S and NexGen Nx586.  Only "386" kernels
25	  will run on a 386 class machine.
26	  - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
27	  SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
28	  - "586" for generic Pentium CPUs lacking the TSC
29	  (time stamp counter) register.
30	  - "Pentium-Classic" for the Intel Pentium.
31	  - "Pentium-MMX" for the Intel Pentium MMX.
32	  - "Pentium-Pro" for the Intel Pentium Pro.
33	  - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
34	  - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
35	  - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
36	  - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
37	  - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
38	  - "Crusoe" for the Transmeta Crusoe series.
39	  - "Efficeon" for the Transmeta Efficeon series.
40	  - "Winchip-C6" for original IDT Winchip.
41	  - "Winchip-2" for IDT Winchip 2.
42	  - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
43	  - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
44	  - "Geode GX/LX" For AMD Geode GX and LX processors.
45	  - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
46	  - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
47	  - "VIA C7" for VIA C7.
48
49	  If you don't know what to do, choose "386".
50
51config M486
52	bool "486"
53	depends on X86_32
54	help
55	  Select this for a 486 series processor, either Intel or one of the
56	  compatible processors from AMD, Cyrix, IBM, or Intel.  Includes DX,
57	  DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
58	  U5S.
59
60config M586
61	bool "586/K5/5x86/6x86/6x86MX"
62	depends on X86_32
63	help
64	  Select this for an 586 or 686 series processor such as the AMD K5,
65	  the Cyrix 5x86, 6x86 and 6x86MX.  This choice does not
66	  assume the RDTSC (Read Time Stamp Counter) instruction.
67
68config M586TSC
69	bool "Pentium-Classic"
70	depends on X86_32
71	help
72	  Select this for a Pentium Classic processor with the RDTSC (Read
73	  Time Stamp Counter) instruction for benchmarking.
74
75config M586MMX
76	bool "Pentium-MMX"
77	depends on X86_32
78	help
79	  Select this for a Pentium with the MMX graphics/multimedia
80	  extended instructions.
81
82config M686
83	bool "Pentium-Pro"
84	depends on X86_32
85	help
86	  Select this for Intel Pentium Pro chips.  This enables the use of
87	  Pentium Pro extended instructions, and disables the init-time guard
88	  against the f00f bug found in earlier Pentiums.
89
90config MPENTIUMII
91	bool "Pentium-II/Celeron(pre-Coppermine)"
92	depends on X86_32
93	help
94	  Select this for Intel chips based on the Pentium-II and
95	  pre-Coppermine Celeron core.  This option enables an unaligned
96	  copy optimization, compiles the kernel with optimization flags
97	  tailored for the chip, and applies any applicable Pentium Pro
98	  optimizations.
99
100config MPENTIUMIII
101	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
102	depends on X86_32
103	help
104	  Select this for Intel chips based on the Pentium-III and
105	  Celeron-Coppermine core.  This option enables use of some
106	  extended prefetch instructions in addition to the Pentium II
107	  extensions.
108
109config MPENTIUMM
110	bool "Pentium M"
111	depends on X86_32
112	help
113	  Select this for Intel Pentium M (not Pentium-4 M)
114	  notebook chips.
115
116config MPENTIUM4
117	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
118	depends on X86_32
119	help
120	  Select this for Intel Pentium 4 chips.  This includes the
121	  Pentium 4, Pentium D, P4-based Celeron and Xeon, and
122	  Pentium-4 M (not Pentium M) chips.  This option enables compile
123	  flags optimized for the chip, uses the correct cache line size, and
124	  applies any applicable optimizations.
125
126	  CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
127
128	  Select this for:
129	    Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
130		-Willamette
131		-Northwood
132		-Mobile Pentium 4
133		-Mobile Pentium 4 M
134		-Extreme Edition (Gallatin)
135		-Prescott
136		-Prescott 2M
137		-Cedar Mill
138		-Presler
139		-Smithfiled
140	    Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
141		-Foster
142		-Prestonia
143		-Gallatin
144		-Nocona
145		-Irwindale
146		-Cranford
147		-Potomac
148		-Paxville
149		-Dempsey
150
151
152config MK6
153	bool "K6/K6-II/K6-III"
154	depends on X86_32
155	help
156	  Select this for an AMD K6-family processor.  Enables use of
157	  some extended instructions, and passes appropriate optimization
158	  flags to GCC.
159
160config MK7
161	bool "Athlon/Duron/K7"
162	depends on X86_32
163	help
164	  Select this for an AMD Athlon K7-family processor.  Enables use of
165	  some extended instructions, and passes appropriate optimization
166	  flags to GCC.
167
168config MK8
169	bool "Opteron/Athlon64/Hammer/K8"
170	help
171	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.  Enables
172	  use of some extended instructions, and passes appropriate optimization
173	  flags to GCC.
174
175config MCRUSOE
176	bool "Crusoe"
177	depends on X86_32
178	help
179	  Select this for a Transmeta Crusoe processor.  Treats the processor
180	  like a 586 with TSC, and sets some GCC optimization flags (like a
181	  Pentium Pro with no alignment requirements).
182
183config MEFFICEON
184	bool "Efficeon"
185	depends on X86_32
186	help
187	  Select this for a Transmeta Efficeon processor.
188
189config MWINCHIPC6
190	bool "Winchip-C6"
191	depends on X86_32
192	help
193	  Select this for an IDT Winchip C6 chip.  Linux and GCC
194	  treat this chip as a 586TSC with some extended instructions
195	  and alignment requirements.
196
197config MWINCHIP2
198	bool "Winchip-2"
199	depends on X86_32
200	help
201	  Select this for an IDT Winchip-2.  Linux and GCC
202	  treat this chip as a 586TSC with some extended instructions
203	  and alignment requirements.
204
205config MWINCHIP3D
206	bool "Winchip-2A/Winchip-3"
207	depends on X86_32
208	help
209	  Select this for an IDT Winchip-2A or 3.  Linux and GCC
210	  treat this chip as a 586TSC with some extended instructions
211	  and alignment requirements.  Also enable out of order memory
212	  stores for this CPU, which can increase performance of some
213	  operations.
214
215config MGEODEGX1
216	bool "GeodeGX1"
217	depends on X86_32
218	help
219	  Select this for a Geode GX1 (Cyrix MediaGX) chip.
220
221config MGEODE_LX
222	bool "Geode GX/LX"
223	depends on X86_32
224	help
225	  Select this for AMD Geode GX and LX processors.
226
227config MCYRIXIII
228	bool "CyrixIII/VIA-C3"
229	depends on X86_32
230	help
231	  Select this for a Cyrix III or C3 chip.  Presently Linux and GCC
232	  treat this chip as a generic 586. Whilst the CPU is 686 class,
233	  it lacks the cmov extension which gcc assumes is present when
234	  generating 686 code.
235	  Note that Nehemiah (Model 9) and above will not boot with this
236	  kernel due to them lacking the 3DNow! instructions used in earlier
237	  incarnations of the CPU.
238
239config MVIAC3_2
240	bool "VIA C3-2 (Nehemiah)"
241	depends on X86_32
242	help
243	  Select this for a VIA C3 "Nehemiah". Selecting this enables usage
244	  of SSE and tells gcc to treat the CPU as a 686.
245	  Note, this kernel will not boot on older (pre model 9) C3s.
246
247config MVIAC7
248	bool "VIA C7"
249	depends on X86_32
250	help
251	  Select this for a VIA C7.  Selecting this uses the correct cache
252	  shift and tells gcc to treat the CPU as a 686.
253
254config MPSC
255	bool "Intel P4 / older Netburst based Xeon"
256	depends on X86_64
257	help
258	  Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
259	  Xeon CPUs with Intel 64bit which is compatible with x86-64.
260	  Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
261	  Netburst core and shouldn't use this option. You can distinguish them
262	  using the cpu family field
263	  in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
264
265config MCORE2
266	bool "Core 2/newer Xeon"
267	help
268	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx)
269	  CPUs. You can distinguish newer from older Xeons by the CPU family
270	  in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo)
271
272config GENERIC_CPU
273	bool "Generic-x86-64"
274	depends on X86_64
275	help
276	  Generic x86-64 CPU.
277	  Run equally well on all x86-64 CPUs.
278
279endchoice
280
281config X86_GENERIC
282	bool "Generic x86 support"
283	depends on X86_32
284	help
285	  Instead of just including optimizations for the selected
286	  x86 variant (e.g. PII, Crusoe or Athlon), include some more
287	  generic optimizations as well. This will make the kernel
288	  perform better on x86 CPUs other than that selected.
289
290	  This is really intended for distributors who need more
291	  generic optimizations.
292
293endif
294
295#
296# Define implied options from the CPU selection here
297config X86_L1_CACHE_BYTES
298	int
299	default "128" if GENERIC_CPU || MPSC
300	default "64" if MK8 || MCORE2
301	depends on X86_64
302
303config X86_INTERNODE_CACHE_BYTES
304	int
305	default "4096" if X86_VSMP
306	default X86_L1_CACHE_BYTES if !X86_VSMP
307	depends on X86_64
308
309config X86_CMPXCHG
310	def_bool X86_64 || (X86_32 && !M386)
311
312config X86_L1_CACHE_SHIFT
313	int
314	default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC
315	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
316	default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
317	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7
318
319config X86_XADD
320	def_bool y
321	depends on X86_32 && !M386
322
323config X86_PPRO_FENCE
324	bool "PentiumPro memory ordering errata workaround"
325	depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
326	help
327	  Old PentiumPro multiprocessor systems had errata that could cause memory
328	  operations to violate the x86 ordering standard in rare cases. Enabling this
329	  option will attempt to work around some (but not all) occurances of
330	  this problem, at the cost of much heavier spinlock and memory barrier
331	  operations.
332
333	  If unsure, say n here. Even distro kernels should think twice before enabling
334	  this: there are few systems, and an unlikely bug.
335
336config X86_F00F_BUG
337	def_bool y
338	depends on M586MMX || M586TSC || M586 || M486 || M386
339
340config X86_WP_WORKS_OK
341	def_bool y
342	depends on X86_32 && !M386
343
344config X86_INVLPG
345	def_bool y
346	depends on X86_32 && !M386
347
348config X86_BSWAP
349	def_bool y
350	depends on X86_32 && !M386
351
352config X86_POPAD_OK
353	def_bool y
354	depends on X86_32 && !M386
355
356config X86_ALIGNMENT_16
357	def_bool y
358	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
359
360config X86_GOOD_APIC
361	def_bool y
362	depends on MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8 || MEFFICEON || MCORE2 || MVIAC7 || X86_64
363
364config X86_INTEL_USERCOPY
365	def_bool y
366	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
367
368config X86_USE_PPRO_CHECKSUM
369	def_bool y
370	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2
371
372config X86_USE_3DNOW
373	def_bool y
374	depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
375
376config X86_OOSTORE
377	def_bool y
378	depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR
379
380#
381# P6_NOPs are a relatively minor optimization that require a family >=
382# 6 processor, except that it is broken on certain VIA chips.
383# Furthermore, AMD chips prefer a totally different sequence of NOPs
384# (which work on all CPUs).  As a result, disallow these if we're
385# compiling X86_GENERIC but not X86_64 (these NOPs do work on all
386# x86-64 capable chips); the list of processors in the right-hand clause
387# are the cores that benefit from this optimization.
388#
389config X86_P6_NOP
390	def_bool y
391	depends on (X86_64 || !X86_GENERIC) && (M686 || MPENTIUMII || MPENTIUMIII || MPENTIUMM || MCORE2 || MPENTIUM4)
392
393config X86_TSC
394	def_bool y
395	depends on ((MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
396
397# this should be set for all -march=.. options where the compiler
398# generates cmov.
399config X86_CMOV
400	def_bool y
401	depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7)
402
403config X86_MINIMUM_CPU_FAMILY
404	int
405	default "64" if X86_64
406	default "6" if X86_32 && X86_P6_NOP
407	default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
408	default "3"
409
410config X86_DEBUGCTLMSR
411	def_bool y
412	depends on !(M586MMX || M586TSC || M586 || M486 || M386)
413