1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Intel Corporation 4 * Author: Johannes Berg <johannes@sipsolutions.net> 5 */ 6 #include <linux/module.h> 7 #include <linux/pci.h> 8 #include <linux/virtio.h> 9 #include <linux/virtio_config.h> 10 #include <linux/logic_iomem.h> 11 #include <linux/of_platform.h> 12 #include <linux/irqdomain.h> 13 #include <linux/virtio_pcidev.h> 14 #include <linux/virtio-uml.h> 15 #include <linux/delay.h> 16 #include <linux/msi.h> 17 #include <asm/unaligned.h> 18 #include <irq_kern.h> 19 20 #define MAX_DEVICES 8 21 #define MAX_MSI_VECTORS 32 22 #define CFG_SPACE_SIZE 4096 23 24 /* for MSI-X we have a 32-bit payload */ 25 #define MAX_IRQ_MSG_SIZE (sizeof(struct virtio_pcidev_msg) + sizeof(u32)) 26 #define NUM_IRQ_MSGS 10 27 28 #define HANDLE_NO_FREE(ptr) ((void *)((unsigned long)(ptr) | 1)) 29 #define HANDLE_IS_NO_FREE(ptr) ((unsigned long)(ptr) & 1) 30 31 struct um_pci_device { 32 struct virtio_device *vdev; 33 34 /* for now just standard BARs */ 35 u8 resptr[PCI_STD_NUM_BARS]; 36 37 struct virtqueue *cmd_vq, *irq_vq; 38 39 #define UM_PCI_STAT_WAITING 0 40 unsigned long status; 41 42 int irq; 43 44 bool platform; 45 }; 46 47 struct um_pci_device_reg { 48 struct um_pci_device *dev; 49 void __iomem *iomem; 50 }; 51 52 static struct pci_host_bridge *bridge; 53 static DEFINE_MUTEX(um_pci_mtx); 54 static struct um_pci_device *um_pci_platform_device; 55 static struct um_pci_device_reg um_pci_devices[MAX_DEVICES]; 56 static struct fwnode_handle *um_pci_fwnode; 57 static struct irq_domain *um_pci_inner_domain; 58 static struct irq_domain *um_pci_msi_domain; 59 static unsigned long um_pci_msi_used[BITS_TO_LONGS(MAX_MSI_VECTORS)]; 60 61 static unsigned int um_pci_max_delay_us = 40000; 62 module_param_named(max_delay_us, um_pci_max_delay_us, uint, 0644); 63 64 struct um_pci_message_buffer { 65 struct virtio_pcidev_msg hdr; 66 u8 data[8]; 67 }; 68 69 static struct um_pci_message_buffer __percpu *um_pci_msg_bufs; 70 71 static int um_pci_send_cmd(struct um_pci_device *dev, 72 struct virtio_pcidev_msg *cmd, 73 unsigned int cmd_size, 74 const void *extra, unsigned int extra_size, 75 void *out, unsigned int out_size) 76 { 77 struct scatterlist out_sg, extra_sg, in_sg; 78 struct scatterlist *sgs_list[] = { 79 [0] = &out_sg, 80 [1] = extra ? &extra_sg : &in_sg, 81 [2] = extra ? &in_sg : NULL, 82 }; 83 struct um_pci_message_buffer *buf; 84 int delay_count = 0; 85 int ret, len; 86 bool posted; 87 88 if (WARN_ON(cmd_size < sizeof(*cmd) || cmd_size > sizeof(*buf))) 89 return -EINVAL; 90 91 switch (cmd->op) { 92 case VIRTIO_PCIDEV_OP_CFG_WRITE: 93 case VIRTIO_PCIDEV_OP_MMIO_WRITE: 94 case VIRTIO_PCIDEV_OP_MMIO_MEMSET: 95 /* in PCI, writes are posted, so don't wait */ 96 posted = !out; 97 WARN_ON(!posted); 98 break; 99 default: 100 posted = false; 101 break; 102 } 103 104 buf = get_cpu_var(um_pci_msg_bufs); 105 if (buf) 106 memcpy(buf, cmd, cmd_size); 107 108 if (posted) { 109 u8 *ncmd = kmalloc(cmd_size + extra_size, GFP_ATOMIC); 110 111 if (ncmd) { 112 memcpy(ncmd, cmd, cmd_size); 113 if (extra) 114 memcpy(ncmd + cmd_size, extra, extra_size); 115 cmd = (void *)ncmd; 116 cmd_size += extra_size; 117 extra = NULL; 118 extra_size = 0; 119 } else { 120 /* try without allocating memory */ 121 posted = false; 122 cmd = (void *)buf; 123 } 124 } else { 125 cmd = (void *)buf; 126 } 127 128 sg_init_one(&out_sg, cmd, cmd_size); 129 if (extra) 130 sg_init_one(&extra_sg, extra, extra_size); 131 if (out) 132 sg_init_one(&in_sg, out, out_size); 133 134 /* add to internal virtio queue */ 135 ret = virtqueue_add_sgs(dev->cmd_vq, sgs_list, 136 extra ? 2 : 1, 137 out ? 1 : 0, 138 posted ? cmd : HANDLE_NO_FREE(cmd), 139 GFP_ATOMIC); 140 if (ret) 141 goto out; 142 143 if (posted) { 144 virtqueue_kick(dev->cmd_vq); 145 ret = 0; 146 goto out; 147 } 148 149 /* kick and poll for getting a response on the queue */ 150 set_bit(UM_PCI_STAT_WAITING, &dev->status); 151 virtqueue_kick(dev->cmd_vq); 152 153 while (1) { 154 void *completed = virtqueue_get_buf(dev->cmd_vq, &len); 155 156 if (completed == HANDLE_NO_FREE(cmd)) 157 break; 158 159 if (completed && !HANDLE_IS_NO_FREE(completed)) 160 kfree(completed); 161 162 if (WARN_ONCE(virtqueue_is_broken(dev->cmd_vq) || 163 ++delay_count > um_pci_max_delay_us, 164 "um virt-pci delay: %d", delay_count)) { 165 ret = -EIO; 166 break; 167 } 168 udelay(1); 169 } 170 clear_bit(UM_PCI_STAT_WAITING, &dev->status); 171 172 out: 173 put_cpu_var(um_pci_msg_bufs); 174 return ret; 175 } 176 177 static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset, 178 int size) 179 { 180 struct um_pci_device_reg *reg = priv; 181 struct um_pci_device *dev = reg->dev; 182 struct virtio_pcidev_msg hdr = { 183 .op = VIRTIO_PCIDEV_OP_CFG_READ, 184 .size = size, 185 .addr = offset, 186 }; 187 /* buf->data is maximum size - we may only use parts of it */ 188 struct um_pci_message_buffer *buf; 189 u8 *data; 190 unsigned long ret = ULONG_MAX; 191 size_t bytes = sizeof(buf->data); 192 193 if (!dev) 194 return ULONG_MAX; 195 196 buf = get_cpu_var(um_pci_msg_bufs); 197 data = buf->data; 198 199 if (buf) 200 memset(data, 0xff, bytes); 201 202 switch (size) { 203 case 1: 204 case 2: 205 case 4: 206 #ifdef CONFIG_64BIT 207 case 8: 208 #endif 209 break; 210 default: 211 WARN(1, "invalid config space read size %d\n", size); 212 goto out; 213 } 214 215 if (um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, data, bytes)) 216 goto out; 217 218 switch (size) { 219 case 1: 220 ret = data[0]; 221 break; 222 case 2: 223 ret = le16_to_cpup((void *)data); 224 break; 225 case 4: 226 ret = le32_to_cpup((void *)data); 227 break; 228 #ifdef CONFIG_64BIT 229 case 8: 230 ret = le64_to_cpup((void *)data); 231 break; 232 #endif 233 default: 234 break; 235 } 236 237 out: 238 put_cpu_var(um_pci_msg_bufs); 239 return ret; 240 } 241 242 static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size, 243 unsigned long val) 244 { 245 struct um_pci_device_reg *reg = priv; 246 struct um_pci_device *dev = reg->dev; 247 struct { 248 struct virtio_pcidev_msg hdr; 249 /* maximum size - we may only use parts of it */ 250 u8 data[8]; 251 } msg = { 252 .hdr = { 253 .op = VIRTIO_PCIDEV_OP_CFG_WRITE, 254 .size = size, 255 .addr = offset, 256 }, 257 }; 258 259 if (!dev) 260 return; 261 262 switch (size) { 263 case 1: 264 msg.data[0] = (u8)val; 265 break; 266 case 2: 267 put_unaligned_le16(val, (void *)msg.data); 268 break; 269 case 4: 270 put_unaligned_le32(val, (void *)msg.data); 271 break; 272 #ifdef CONFIG_64BIT 273 case 8: 274 put_unaligned_le64(val, (void *)msg.data); 275 break; 276 #endif 277 default: 278 WARN(1, "invalid config space write size %d\n", size); 279 return; 280 } 281 282 WARN_ON(um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0)); 283 } 284 285 static const struct logic_iomem_ops um_pci_device_cfgspace_ops = { 286 .read = um_pci_cfgspace_read, 287 .write = um_pci_cfgspace_write, 288 }; 289 290 static void um_pci_bar_copy_from(void *priv, void *buffer, 291 unsigned int offset, int size) 292 { 293 u8 *resptr = priv; 294 struct um_pci_device *dev = container_of(resptr - *resptr, 295 struct um_pci_device, 296 resptr[0]); 297 struct virtio_pcidev_msg hdr = { 298 .op = VIRTIO_PCIDEV_OP_MMIO_READ, 299 .bar = *resptr, 300 .size = size, 301 .addr = offset, 302 }; 303 304 memset(buffer, 0xff, size); 305 306 um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, buffer, size); 307 } 308 309 static unsigned long um_pci_bar_read(void *priv, unsigned int offset, 310 int size) 311 { 312 /* buf->data is maximum size - we may only use parts of it */ 313 struct um_pci_message_buffer *buf; 314 u8 *data; 315 unsigned long ret = ULONG_MAX; 316 317 buf = get_cpu_var(um_pci_msg_bufs); 318 data = buf->data; 319 320 switch (size) { 321 case 1: 322 case 2: 323 case 4: 324 #ifdef CONFIG_64BIT 325 case 8: 326 #endif 327 break; 328 default: 329 WARN(1, "invalid config space read size %d\n", size); 330 goto out; 331 } 332 333 um_pci_bar_copy_from(priv, data, offset, size); 334 335 switch (size) { 336 case 1: 337 ret = data[0]; 338 break; 339 case 2: 340 ret = le16_to_cpup((void *)data); 341 break; 342 case 4: 343 ret = le32_to_cpup((void *)data); 344 break; 345 #ifdef CONFIG_64BIT 346 case 8: 347 ret = le64_to_cpup((void *)data); 348 break; 349 #endif 350 default: 351 break; 352 } 353 354 out: 355 put_cpu_var(um_pci_msg_bufs); 356 return ret; 357 } 358 359 static void um_pci_bar_copy_to(void *priv, unsigned int offset, 360 const void *buffer, int size) 361 { 362 u8 *resptr = priv; 363 struct um_pci_device *dev = container_of(resptr - *resptr, 364 struct um_pci_device, 365 resptr[0]); 366 struct virtio_pcidev_msg hdr = { 367 .op = VIRTIO_PCIDEV_OP_MMIO_WRITE, 368 .bar = *resptr, 369 .size = size, 370 .addr = offset, 371 }; 372 373 um_pci_send_cmd(dev, &hdr, sizeof(hdr), buffer, size, NULL, 0); 374 } 375 376 static void um_pci_bar_write(void *priv, unsigned int offset, int size, 377 unsigned long val) 378 { 379 /* maximum size - we may only use parts of it */ 380 u8 data[8]; 381 382 switch (size) { 383 case 1: 384 data[0] = (u8)val; 385 break; 386 case 2: 387 put_unaligned_le16(val, (void *)data); 388 break; 389 case 4: 390 put_unaligned_le32(val, (void *)data); 391 break; 392 #ifdef CONFIG_64BIT 393 case 8: 394 put_unaligned_le64(val, (void *)data); 395 break; 396 #endif 397 default: 398 WARN(1, "invalid config space write size %d\n", size); 399 return; 400 } 401 402 um_pci_bar_copy_to(priv, offset, data, size); 403 } 404 405 static void um_pci_bar_set(void *priv, unsigned int offset, u8 value, int size) 406 { 407 u8 *resptr = priv; 408 struct um_pci_device *dev = container_of(resptr - *resptr, 409 struct um_pci_device, 410 resptr[0]); 411 struct { 412 struct virtio_pcidev_msg hdr; 413 u8 data; 414 } msg = { 415 .hdr = { 416 .op = VIRTIO_PCIDEV_OP_CFG_WRITE, 417 .bar = *resptr, 418 .size = size, 419 .addr = offset, 420 }, 421 .data = value, 422 }; 423 424 um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0); 425 } 426 427 static const struct logic_iomem_ops um_pci_device_bar_ops = { 428 .read = um_pci_bar_read, 429 .write = um_pci_bar_write, 430 .set = um_pci_bar_set, 431 .copy_from = um_pci_bar_copy_from, 432 .copy_to = um_pci_bar_copy_to, 433 }; 434 435 static void __iomem *um_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 436 int where) 437 { 438 struct um_pci_device_reg *dev; 439 unsigned int busn = bus->number; 440 441 if (busn > 0) 442 return NULL; 443 444 /* not allowing functions for now ... */ 445 if (devfn % 8) 446 return NULL; 447 448 if (devfn / 8 >= ARRAY_SIZE(um_pci_devices)) 449 return NULL; 450 451 dev = &um_pci_devices[devfn / 8]; 452 if (!dev) 453 return NULL; 454 455 return (void __iomem *)((unsigned long)dev->iomem + where); 456 } 457 458 static struct pci_ops um_pci_ops = { 459 .map_bus = um_pci_map_bus, 460 .read = pci_generic_config_read, 461 .write = pci_generic_config_write, 462 }; 463 464 static void um_pci_rescan(void) 465 { 466 pci_lock_rescan_remove(); 467 pci_rescan_bus(bridge->bus); 468 pci_unlock_rescan_remove(); 469 } 470 471 static void um_pci_irq_vq_addbuf(struct virtqueue *vq, void *buf, bool kick) 472 { 473 struct scatterlist sg[1]; 474 475 sg_init_one(sg, buf, MAX_IRQ_MSG_SIZE); 476 if (virtqueue_add_inbuf(vq, sg, 1, buf, GFP_ATOMIC)) 477 kfree(buf); 478 else if (kick) 479 virtqueue_kick(vq); 480 } 481 482 static void um_pci_handle_irq_message(struct virtqueue *vq, 483 struct virtio_pcidev_msg *msg) 484 { 485 struct virtio_device *vdev = vq->vdev; 486 struct um_pci_device *dev = vdev->priv; 487 488 if (!dev->irq) 489 return; 490 491 /* we should properly chain interrupts, but on ARCH=um we don't care */ 492 493 switch (msg->op) { 494 case VIRTIO_PCIDEV_OP_INT: 495 generic_handle_irq(dev->irq); 496 break; 497 case VIRTIO_PCIDEV_OP_MSI: 498 /* our MSI message is just the interrupt number */ 499 if (msg->size == sizeof(u32)) 500 generic_handle_irq(le32_to_cpup((void *)msg->data)); 501 else 502 generic_handle_irq(le16_to_cpup((void *)msg->data)); 503 break; 504 case VIRTIO_PCIDEV_OP_PME: 505 /* nothing to do - we already woke up due to the message */ 506 break; 507 default: 508 dev_err(&vdev->dev, "unexpected virt-pci message %d\n", msg->op); 509 break; 510 } 511 } 512 513 static void um_pci_cmd_vq_cb(struct virtqueue *vq) 514 { 515 struct virtio_device *vdev = vq->vdev; 516 struct um_pci_device *dev = vdev->priv; 517 void *cmd; 518 int len; 519 520 if (test_bit(UM_PCI_STAT_WAITING, &dev->status)) 521 return; 522 523 while ((cmd = virtqueue_get_buf(vq, &len))) { 524 if (WARN_ON(HANDLE_IS_NO_FREE(cmd))) 525 continue; 526 kfree(cmd); 527 } 528 } 529 530 static void um_pci_irq_vq_cb(struct virtqueue *vq) 531 { 532 struct virtio_pcidev_msg *msg; 533 int len; 534 535 while ((msg = virtqueue_get_buf(vq, &len))) { 536 if (len >= sizeof(*msg)) 537 um_pci_handle_irq_message(vq, msg); 538 539 /* recycle the message buffer */ 540 um_pci_irq_vq_addbuf(vq, msg, true); 541 } 542 } 543 544 /* Copied from arch/x86/kernel/devicetree.c */ 545 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 546 { 547 struct device_node *np; 548 549 for_each_node_by_type(np, "pci") { 550 const void *prop; 551 unsigned int bus_min; 552 553 prop = of_get_property(np, "bus-range", NULL); 554 if (!prop) 555 continue; 556 bus_min = be32_to_cpup(prop); 557 if (bus->number == bus_min) 558 return np; 559 } 560 return NULL; 561 } 562 563 static int um_pci_init_vqs(struct um_pci_device *dev) 564 { 565 struct virtqueue *vqs[2]; 566 static const char *const names[2] = { "cmd", "irq" }; 567 vq_callback_t *cbs[2] = { um_pci_cmd_vq_cb, um_pci_irq_vq_cb }; 568 int err, i; 569 570 err = virtio_find_vqs(dev->vdev, 2, vqs, cbs, names, NULL); 571 if (err) 572 return err; 573 574 dev->cmd_vq = vqs[0]; 575 dev->irq_vq = vqs[1]; 576 577 virtio_device_ready(dev->vdev); 578 579 for (i = 0; i < NUM_IRQ_MSGS; i++) { 580 void *msg = kzalloc(MAX_IRQ_MSG_SIZE, GFP_KERNEL); 581 582 if (msg) 583 um_pci_irq_vq_addbuf(dev->irq_vq, msg, false); 584 } 585 586 virtqueue_kick(dev->irq_vq); 587 588 return 0; 589 } 590 591 static void __um_pci_virtio_platform_remove(struct virtio_device *vdev, 592 struct um_pci_device *dev) 593 { 594 virtio_reset_device(vdev); 595 vdev->config->del_vqs(vdev); 596 597 mutex_lock(&um_pci_mtx); 598 um_pci_platform_device = NULL; 599 mutex_unlock(&um_pci_mtx); 600 601 kfree(dev); 602 } 603 604 static int um_pci_virtio_platform_probe(struct virtio_device *vdev, 605 struct um_pci_device *dev) 606 { 607 int ret; 608 609 dev->platform = true; 610 611 mutex_lock(&um_pci_mtx); 612 613 if (um_pci_platform_device) { 614 mutex_unlock(&um_pci_mtx); 615 ret = -EBUSY; 616 goto out_free; 617 } 618 619 ret = um_pci_init_vqs(dev); 620 if (ret) { 621 mutex_unlock(&um_pci_mtx); 622 goto out_free; 623 } 624 625 um_pci_platform_device = dev; 626 627 mutex_unlock(&um_pci_mtx); 628 629 ret = of_platform_default_populate(vdev->dev.of_node, NULL, &vdev->dev); 630 if (ret) 631 __um_pci_virtio_platform_remove(vdev, dev); 632 633 return ret; 634 635 out_free: 636 kfree(dev); 637 return ret; 638 } 639 640 static int um_pci_virtio_probe(struct virtio_device *vdev) 641 { 642 struct um_pci_device *dev; 643 int i, free = -1; 644 int err = -ENOSPC; 645 646 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 647 if (!dev) 648 return -ENOMEM; 649 650 dev->vdev = vdev; 651 vdev->priv = dev; 652 653 if (of_device_is_compatible(vdev->dev.of_node, "simple-bus")) 654 return um_pci_virtio_platform_probe(vdev, dev); 655 656 mutex_lock(&um_pci_mtx); 657 for (i = 0; i < MAX_DEVICES; i++) { 658 if (um_pci_devices[i].dev) 659 continue; 660 free = i; 661 break; 662 } 663 664 if (free < 0) 665 goto error; 666 667 err = um_pci_init_vqs(dev); 668 if (err) 669 goto error; 670 671 dev->irq = irq_alloc_desc(numa_node_id()); 672 if (dev->irq < 0) { 673 err = dev->irq; 674 goto err_reset; 675 } 676 um_pci_devices[free].dev = dev; 677 vdev->priv = dev; 678 679 mutex_unlock(&um_pci_mtx); 680 681 device_set_wakeup_enable(&vdev->dev, true); 682 683 /* 684 * In order to do suspend-resume properly, don't allow VQs 685 * to be suspended. 686 */ 687 virtio_uml_set_no_vq_suspend(vdev, true); 688 689 um_pci_rescan(); 690 return 0; 691 err_reset: 692 virtio_reset_device(vdev); 693 vdev->config->del_vqs(vdev); 694 error: 695 mutex_unlock(&um_pci_mtx); 696 kfree(dev); 697 return err; 698 } 699 700 static void um_pci_virtio_remove(struct virtio_device *vdev) 701 { 702 struct um_pci_device *dev = vdev->priv; 703 int i; 704 705 if (dev->platform) { 706 of_platform_depopulate(&vdev->dev); 707 __um_pci_virtio_platform_remove(vdev, dev); 708 return; 709 } 710 711 /* Stop all virtqueues */ 712 virtio_reset_device(vdev); 713 vdev->config->del_vqs(vdev); 714 715 device_set_wakeup_enable(&vdev->dev, false); 716 717 mutex_lock(&um_pci_mtx); 718 for (i = 0; i < MAX_DEVICES; i++) { 719 if (um_pci_devices[i].dev != dev) 720 continue; 721 um_pci_devices[i].dev = NULL; 722 irq_free_desc(dev->irq); 723 } 724 mutex_unlock(&um_pci_mtx); 725 726 um_pci_rescan(); 727 728 kfree(dev); 729 } 730 731 static struct virtio_device_id id_table[] = { 732 { CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID, VIRTIO_DEV_ANY_ID }, 733 { 0 }, 734 }; 735 MODULE_DEVICE_TABLE(virtio, id_table); 736 737 static struct virtio_driver um_pci_virtio_driver = { 738 .driver.name = "virtio-pci", 739 .driver.owner = THIS_MODULE, 740 .id_table = id_table, 741 .probe = um_pci_virtio_probe, 742 .remove = um_pci_virtio_remove, 743 }; 744 745 static struct resource virt_cfgspace_resource = { 746 .name = "PCI config space", 747 .start = 0xf0000000 - MAX_DEVICES * CFG_SPACE_SIZE, 748 .end = 0xf0000000 - 1, 749 .flags = IORESOURCE_MEM, 750 }; 751 752 static long um_pci_map_cfgspace(unsigned long offset, size_t size, 753 const struct logic_iomem_ops **ops, 754 void **priv) 755 { 756 if (WARN_ON(size > CFG_SPACE_SIZE || offset % CFG_SPACE_SIZE)) 757 return -EINVAL; 758 759 if (offset / CFG_SPACE_SIZE < MAX_DEVICES) { 760 *ops = &um_pci_device_cfgspace_ops; 761 *priv = &um_pci_devices[offset / CFG_SPACE_SIZE]; 762 return 0; 763 } 764 765 WARN(1, "cannot map offset 0x%lx/0x%zx\n", offset, size); 766 return -ENOENT; 767 } 768 769 static const struct logic_iomem_region_ops um_pci_cfgspace_ops = { 770 .map = um_pci_map_cfgspace, 771 }; 772 773 static struct resource virt_iomem_resource = { 774 .name = "PCI iomem", 775 .start = 0xf0000000, 776 .end = 0xffffffff, 777 .flags = IORESOURCE_MEM, 778 }; 779 780 struct um_pci_map_iomem_data { 781 unsigned long offset; 782 size_t size; 783 const struct logic_iomem_ops **ops; 784 void **priv; 785 long ret; 786 }; 787 788 static int um_pci_map_iomem_walk(struct pci_dev *pdev, void *_data) 789 { 790 struct um_pci_map_iomem_data *data = _data; 791 struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8]; 792 struct um_pci_device *dev; 793 int i; 794 795 if (!reg->dev) 796 return 0; 797 798 for (i = 0; i < ARRAY_SIZE(dev->resptr); i++) { 799 struct resource *r = &pdev->resource[i]; 800 801 if ((r->flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM) 802 continue; 803 804 /* 805 * must be the whole or part of the resource, 806 * not allowed to only overlap 807 */ 808 if (data->offset < r->start || data->offset > r->end) 809 continue; 810 if (data->offset + data->size - 1 > r->end) 811 continue; 812 813 dev = reg->dev; 814 *data->ops = &um_pci_device_bar_ops; 815 dev->resptr[i] = i; 816 *data->priv = &dev->resptr[i]; 817 data->ret = data->offset - r->start; 818 819 /* no need to continue */ 820 return 1; 821 } 822 823 return 0; 824 } 825 826 static long um_pci_map_iomem(unsigned long offset, size_t size, 827 const struct logic_iomem_ops **ops, 828 void **priv) 829 { 830 struct um_pci_map_iomem_data data = { 831 /* we want the full address here */ 832 .offset = offset + virt_iomem_resource.start, 833 .size = size, 834 .ops = ops, 835 .priv = priv, 836 .ret = -ENOENT, 837 }; 838 839 pci_walk_bus(bridge->bus, um_pci_map_iomem_walk, &data); 840 return data.ret; 841 } 842 843 static const struct logic_iomem_region_ops um_pci_iomem_ops = { 844 .map = um_pci_map_iomem, 845 }; 846 847 static void um_pci_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 848 { 849 /* 850 * This is a very low address and not actually valid 'physical' memory 851 * in UML, so we can simply map MSI(-X) vectors to there, it cannot be 852 * legitimately written to by the device in any other way. 853 * We use the (virtual) IRQ number here as the message to simplify the 854 * code that receives the message, where for now we simply trust the 855 * device to send the correct message. 856 */ 857 msg->address_hi = 0; 858 msg->address_lo = 0xa0000; 859 msg->data = data->irq; 860 } 861 862 static struct irq_chip um_pci_msi_bottom_irq_chip = { 863 .name = "UM virtio MSI", 864 .irq_compose_msi_msg = um_pci_compose_msi_msg, 865 }; 866 867 static int um_pci_inner_domain_alloc(struct irq_domain *domain, 868 unsigned int virq, unsigned int nr_irqs, 869 void *args) 870 { 871 unsigned long bit; 872 873 WARN_ON(nr_irqs != 1); 874 875 mutex_lock(&um_pci_mtx); 876 bit = find_first_zero_bit(um_pci_msi_used, MAX_MSI_VECTORS); 877 if (bit >= MAX_MSI_VECTORS) { 878 mutex_unlock(&um_pci_mtx); 879 return -ENOSPC; 880 } 881 882 set_bit(bit, um_pci_msi_used); 883 mutex_unlock(&um_pci_mtx); 884 885 irq_domain_set_info(domain, virq, bit, &um_pci_msi_bottom_irq_chip, 886 domain->host_data, handle_simple_irq, 887 NULL, NULL); 888 889 return 0; 890 } 891 892 static void um_pci_inner_domain_free(struct irq_domain *domain, 893 unsigned int virq, unsigned int nr_irqs) 894 { 895 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 896 897 mutex_lock(&um_pci_mtx); 898 899 if (!test_bit(d->hwirq, um_pci_msi_used)) 900 pr_err("trying to free unused MSI#%lu\n", d->hwirq); 901 else 902 __clear_bit(d->hwirq, um_pci_msi_used); 903 904 mutex_unlock(&um_pci_mtx); 905 } 906 907 static const struct irq_domain_ops um_pci_inner_domain_ops = { 908 .alloc = um_pci_inner_domain_alloc, 909 .free = um_pci_inner_domain_free, 910 }; 911 912 static struct irq_chip um_pci_msi_irq_chip = { 913 .name = "UM virtio PCIe MSI", 914 .irq_mask = pci_msi_mask_irq, 915 .irq_unmask = pci_msi_unmask_irq, 916 }; 917 918 static struct msi_domain_info um_pci_msi_domain_info = { 919 .flags = MSI_FLAG_USE_DEF_DOM_OPS | 920 MSI_FLAG_USE_DEF_CHIP_OPS | 921 MSI_FLAG_PCI_MSIX, 922 .chip = &um_pci_msi_irq_chip, 923 }; 924 925 static struct resource busn_resource = { 926 .name = "PCI busn", 927 .start = 0, 928 .end = 0, 929 .flags = IORESOURCE_BUS, 930 }; 931 932 static int um_pci_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) 933 { 934 struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8]; 935 936 if (WARN_ON(!reg->dev)) 937 return -EINVAL; 938 939 /* Yes, we map all pins to the same IRQ ... doesn't matter for now. */ 940 return reg->dev->irq; 941 } 942 943 void *pci_root_bus_fwnode(struct pci_bus *bus) 944 { 945 return um_pci_fwnode; 946 } 947 948 static long um_pci_map_platform(unsigned long offset, size_t size, 949 const struct logic_iomem_ops **ops, 950 void **priv) 951 { 952 if (!um_pci_platform_device) 953 return -ENOENT; 954 955 *ops = &um_pci_device_bar_ops; 956 *priv = &um_pci_platform_device->resptr[0]; 957 958 return 0; 959 } 960 961 static const struct logic_iomem_region_ops um_pci_platform_ops = { 962 .map = um_pci_map_platform, 963 }; 964 965 static struct resource virt_platform_resource = { 966 .name = "platform", 967 .start = 0x10000000, 968 .end = 0x1fffffff, 969 .flags = IORESOURCE_MEM, 970 }; 971 972 static int __init um_pci_init(void) 973 { 974 int err, i; 975 976 WARN_ON(logic_iomem_add_region(&virt_cfgspace_resource, 977 &um_pci_cfgspace_ops)); 978 WARN_ON(logic_iomem_add_region(&virt_iomem_resource, 979 &um_pci_iomem_ops)); 980 WARN_ON(logic_iomem_add_region(&virt_platform_resource, 981 &um_pci_platform_ops)); 982 983 if (WARN(CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID < 0, 984 "No virtio device ID configured for PCI - no PCI support\n")) 985 return 0; 986 987 um_pci_msg_bufs = alloc_percpu(struct um_pci_message_buffer); 988 if (!um_pci_msg_bufs) 989 return -ENOMEM; 990 991 bridge = pci_alloc_host_bridge(0); 992 if (!bridge) { 993 err = -ENOMEM; 994 goto free; 995 } 996 997 um_pci_fwnode = irq_domain_alloc_named_fwnode("um-pci"); 998 if (!um_pci_fwnode) { 999 err = -ENOMEM; 1000 goto free; 1001 } 1002 1003 um_pci_inner_domain = __irq_domain_add(um_pci_fwnode, MAX_MSI_VECTORS, 1004 MAX_MSI_VECTORS, 0, 1005 &um_pci_inner_domain_ops, NULL); 1006 if (!um_pci_inner_domain) { 1007 err = -ENOMEM; 1008 goto free; 1009 } 1010 1011 um_pci_msi_domain = pci_msi_create_irq_domain(um_pci_fwnode, 1012 &um_pci_msi_domain_info, 1013 um_pci_inner_domain); 1014 if (!um_pci_msi_domain) { 1015 err = -ENOMEM; 1016 goto free; 1017 } 1018 1019 pci_add_resource(&bridge->windows, &virt_iomem_resource); 1020 pci_add_resource(&bridge->windows, &busn_resource); 1021 bridge->ops = &um_pci_ops; 1022 bridge->map_irq = um_pci_map_irq; 1023 1024 for (i = 0; i < MAX_DEVICES; i++) { 1025 resource_size_t start; 1026 1027 start = virt_cfgspace_resource.start + i * CFG_SPACE_SIZE; 1028 um_pci_devices[i].iomem = ioremap(start, CFG_SPACE_SIZE); 1029 if (WARN(!um_pci_devices[i].iomem, "failed to map %d\n", i)) { 1030 err = -ENOMEM; 1031 goto free; 1032 } 1033 } 1034 1035 err = pci_host_probe(bridge); 1036 if (err) 1037 goto free; 1038 1039 err = register_virtio_driver(&um_pci_virtio_driver); 1040 if (err) 1041 goto free; 1042 return 0; 1043 free: 1044 if (um_pci_inner_domain) 1045 irq_domain_remove(um_pci_inner_domain); 1046 if (um_pci_fwnode) 1047 irq_domain_free_fwnode(um_pci_fwnode); 1048 if (bridge) { 1049 pci_free_resource_list(&bridge->windows); 1050 pci_free_host_bridge(bridge); 1051 } 1052 free_percpu(um_pci_msg_bufs); 1053 return err; 1054 } 1055 module_init(um_pci_init); 1056 1057 static void __exit um_pci_exit(void) 1058 { 1059 unregister_virtio_driver(&um_pci_virtio_driver); 1060 irq_domain_remove(um_pci_msi_domain); 1061 irq_domain_remove(um_pci_inner_domain); 1062 pci_free_resource_list(&bridge->windows); 1063 pci_free_host_bridge(bridge); 1064 free_percpu(um_pci_msg_bufs); 1065 } 1066 module_exit(um_pci_exit); 1067