1/* 2 * swift.S: MicroSparc-II mmu/cache operations. 3 * 4 * Copyright (C) 1999 David S. Miller (davem@redhat.com) 5 */ 6 7#include <asm/psr.h> 8#include <asm/asi.h> 9#include <asm/page.h> 10#include <asm/pgtsrmmu.h> 11#include <asm/asm-offsets.h> 12 13 .text 14 .align 4 15 16#if 1 /* XXX screw this, I can't get the VAC flushes working 17 * XXX reliably... -DaveM 18 */ 19 .globl swift_flush_cache_all, swift_flush_cache_mm 20 .globl swift_flush_cache_range, swift_flush_cache_page 21 .globl swift_flush_page_for_dma 22 .globl swift_flush_page_to_ram 23 24swift_flush_cache_all: 25swift_flush_cache_mm: 26swift_flush_cache_range: 27swift_flush_cache_page: 28swift_flush_page_for_dma: 29swift_flush_page_to_ram: 30 sethi %hi(0x2000), %o0 311: subcc %o0, 0x10, %o0 32 add %o0, %o0, %o1 33 sta %g0, [%o0] ASI_M_DATAC_TAG 34 bne 1b 35 sta %g0, [%o1] ASI_M_TXTC_TAG 36 retl 37 nop 38#else 39 40 .globl swift_flush_cache_all 41swift_flush_cache_all: 42 WINDOW_FLUSH(%g4, %g5) 43 44 /* Just clear out all the tags. */ 45 sethi %hi(16 * 1024), %o0 461: subcc %o0, 16, %o0 47 sta %g0, [%o0] ASI_M_TXTC_TAG 48 bne 1b 49 sta %g0, [%o0] ASI_M_DATAC_TAG 50 retl 51 nop 52 53 .globl swift_flush_cache_mm 54swift_flush_cache_mm: 55 ld [%o0 + AOFF_mm_context], %g2 56 cmp %g2, -1 57 be swift_flush_cache_mm_out 58 WINDOW_FLUSH(%g4, %g5) 59 rd %psr, %g1 60 andn %g1, PSR_ET, %g3 61 wr %g3, 0x0, %psr 62 nop 63 nop 64 mov SRMMU_CTX_REG, %g7 65 lda [%g7] ASI_M_MMUREGS, %g5 66 sta %g2, [%g7] ASI_M_MMUREGS 67 68#if 1 69 sethi %hi(0x2000), %o0 701: subcc %o0, 0x10, %o0 71 sta %g0, [%o0] ASI_M_FLUSH_CTX 72 bne 1b 73 nop 74#else 75 clr %o0 76 or %g0, 2048, %g7 77 or %g0, 2048, %o1 78 add %o1, 2048, %o2 79 add %o2, 2048, %o3 80 mov 16, %o4 81 add %o4, 2048, %o5 82 add %o5, 2048, %g2 83 add %g2, 2048, %g3 841: sta %g0, [%o0 ] ASI_M_FLUSH_CTX 85 sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX 86 sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX 87 sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX 88 sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX 89 sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX 90 sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX 91 sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX 92 subcc %g7, 32, %g7 93 bne 1b 94 add %o0, 32, %o0 95#endif 96 97 mov SRMMU_CTX_REG, %g7 98 sta %g5, [%g7] ASI_M_MMUREGS 99 wr %g1, 0x0, %psr 100 nop 101 nop 102swift_flush_cache_mm_out: 103 retl 104 nop 105 106 .globl swift_flush_cache_range 107swift_flush_cache_range: 108 ld [%o0 + VMA_VM_MM], %o0 109 sub %o2, %o1, %o2 110 sethi %hi(4096), %o3 111 cmp %o2, %o3 112 bgu swift_flush_cache_mm 113 nop 114 b 70f 115 nop 116 117 .globl swift_flush_cache_page 118swift_flush_cache_page: 119 ld [%o0 + VMA_VM_MM], %o0 12070: 121 ld [%o0 + AOFF_mm_context], %g2 122 cmp %g2, -1 123 be swift_flush_cache_page_out 124 WINDOW_FLUSH(%g4, %g5) 125 rd %psr, %g1 126 andn %g1, PSR_ET, %g3 127 wr %g3, 0x0, %psr 128 nop 129 nop 130 mov SRMMU_CTX_REG, %g7 131 lda [%g7] ASI_M_MMUREGS, %g5 132 sta %g2, [%g7] ASI_M_MMUREGS 133 134 andn %o1, (PAGE_SIZE - 1), %o1 135#if 1 136 sethi %hi(0x1000), %o0 1371: subcc %o0, 0x10, %o0 138 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE 139 bne 1b 140 nop 141#else 142 or %g0, 512, %g7 143 or %g0, 512, %o0 144 add %o0, 512, %o2 145 add %o2, 512, %o3 146 add %o3, 512, %o4 147 add %o4, 512, %o5 148 add %o5, 512, %g3 149 add %g3, 512, %g4 1501: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE 151 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE 152 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE 153 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE 154 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE 155 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE 156 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE 157 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE 158 subcc %g7, 16, %g7 159 bne 1b 160 add %o1, 16, %o1 161#endif 162 163 mov SRMMU_CTX_REG, %g7 164 sta %g5, [%g7] ASI_M_MMUREGS 165 wr %g1, 0x0, %psr 166 nop 167 nop 168swift_flush_cache_page_out: 169 retl 170 nop 171 172 /* Swift is write-thru, however it is not 173 * I/O nor TLB-walk coherent. Also it has 174 * caches which are virtually indexed and tagged. 175 */ 176 .globl swift_flush_page_for_dma 177 .globl swift_flush_page_to_ram 178swift_flush_page_for_dma: 179swift_flush_page_to_ram: 180 andn %o0, (PAGE_SIZE - 1), %o1 181#if 1 182 sethi %hi(0x1000), %o0 1831: subcc %o0, 0x10, %o0 184 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE 185 bne 1b 186 nop 187#else 188 or %g0, 512, %g7 189 or %g0, 512, %o0 190 add %o0, 512, %o2 191 add %o2, 512, %o3 192 add %o3, 512, %o4 193 add %o4, 512, %o5 194 add %o5, 512, %g3 195 add %g3, 512, %g4 1961: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE 197 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE 198 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE 199 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE 200 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE 201 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE 202 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE 203 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE 204 subcc %g7, 16, %g7 205 bne 1b 206 add %o1, 16, %o1 207#endif 208 retl 209 nop 210#endif 211 212 .globl swift_flush_sig_insns 213swift_flush_sig_insns: 214 flush %o1 215 retl 216 flush %o1 + 4 217 218 .globl swift_flush_tlb_mm 219 .globl swift_flush_tlb_range 220 .globl swift_flush_tlb_all 221swift_flush_tlb_range: 222 ld [%o0 + VMA_VM_MM], %o0 223swift_flush_tlb_mm: 224 ld [%o0 + AOFF_mm_context], %g2 225 cmp %g2, -1 226 be swift_flush_tlb_all_out 227swift_flush_tlb_all: 228 mov 0x400, %o1 229 sta %g0, [%o1] ASI_M_FLUSH_PROBE 230swift_flush_tlb_all_out: 231 retl 232 nop 233 234 .globl swift_flush_tlb_page 235swift_flush_tlb_page: 236 ld [%o0 + VMA_VM_MM], %o0 237 mov SRMMU_CTX_REG, %g1 238 ld [%o0 + AOFF_mm_context], %o3 239 andn %o1, (PAGE_SIZE - 1), %o1 240 cmp %o3, -1 241 be swift_flush_tlb_page_out 242 nop 243#if 1 244 mov 0x400, %o1 245 sta %g0, [%o1] ASI_M_FLUSH_PROBE 246#else 247 lda [%g1] ASI_M_MMUREGS, %g5 248 sta %o3, [%g1] ASI_M_MMUREGS 249 sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */ 250 sta %g0, [%o1] ASI_M_FLUSH_PROBE 251 sta %g5, [%g1] ASI_M_MMUREGS 252#endif 253swift_flush_tlb_page_out: 254 retl 255 nop 256