1 /* 2 * srmmu.c: SRMMU specific routines for memory management. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com) 6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org) 9 */ 10 11 #include <linux/seq_file.h> 12 #include <linux/spinlock.h> 13 #include <linux/bootmem.h> 14 #include <linux/pagemap.h> 15 #include <linux/vmalloc.h> 16 #include <linux/kdebug.h> 17 #include <linux/export.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/log2.h> 21 #include <linux/gfp.h> 22 #include <linux/fs.h> 23 #include <linux/mm.h> 24 25 #include <asm/mmu_context.h> 26 #include <asm/cacheflush.h> 27 #include <asm/tlbflush.h> 28 #include <asm/io-unit.h> 29 #include <asm/pgalloc.h> 30 #include <asm/pgtable.h> 31 #include <asm/bitext.h> 32 #include <asm/vaddrs.h> 33 #include <asm/cache.h> 34 #include <asm/traps.h> 35 #include <asm/oplib.h> 36 #include <asm/mbus.h> 37 #include <asm/page.h> 38 #include <asm/asi.h> 39 #include <asm/msi.h> 40 #include <asm/smp.h> 41 #include <asm/io.h> 42 43 /* Now the cpu specific definitions. */ 44 #include <asm/turbosparc.h> 45 #include <asm/tsunami.h> 46 #include <asm/viking.h> 47 #include <asm/swift.h> 48 #include <asm/leon.h> 49 #include <asm/mxcc.h> 50 #include <asm/ross.h> 51 52 #include "mm_32.h" 53 54 enum mbus_module srmmu_modtype; 55 static unsigned int hwbug_bitmask; 56 int vac_cache_size; 57 int vac_line_size; 58 59 extern struct resource sparc_iomap; 60 61 extern unsigned long last_valid_pfn; 62 63 static pgd_t *srmmu_swapper_pg_dir; 64 65 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops; 66 EXPORT_SYMBOL(sparc32_cachetlb_ops); 67 68 #ifdef CONFIG_SMP 69 const struct sparc32_cachetlb_ops *local_ops; 70 71 #define FLUSH_BEGIN(mm) 72 #define FLUSH_END 73 #else 74 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) { 75 #define FLUSH_END } 76 #endif 77 78 int flush_page_for_dma_global = 1; 79 80 char *srmmu_name; 81 82 ctxd_t *srmmu_ctx_table_phys; 83 static ctxd_t *srmmu_context_table; 84 85 int viking_mxcc_present; 86 static DEFINE_SPINLOCK(srmmu_context_spinlock); 87 88 static int is_hypersparc; 89 90 static int srmmu_cache_pagetables; 91 92 /* these will be initialized in srmmu_nocache_calcsize() */ 93 static unsigned long srmmu_nocache_size; 94 static unsigned long srmmu_nocache_end; 95 96 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */ 97 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4) 98 99 /* The context table is a nocache user with the biggest alignment needs. */ 100 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS) 101 102 void *srmmu_nocache_pool; 103 static struct bit_map srmmu_nocache_map; 104 105 static inline int srmmu_pmd_none(pmd_t pmd) 106 { return !(pmd_val(pmd) & 0xFFFFFFF); } 107 108 /* XXX should we hyper_flush_whole_icache here - Anton */ 109 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp) 110 { set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); } 111 112 void pmd_set(pmd_t *pmdp, pte_t *ptep) 113 { 114 unsigned long ptp; /* Physical address, shifted right by 4 */ 115 int i; 116 117 ptp = __nocache_pa((unsigned long) ptep) >> 4; 118 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { 119 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); 120 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4); 121 } 122 } 123 124 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) 125 { 126 unsigned long ptp; /* Physical address, shifted right by 4 */ 127 int i; 128 129 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */ 130 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { 131 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); 132 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4); 133 } 134 } 135 136 /* Find an entry in the third-level page table.. */ 137 pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address) 138 { 139 void *pte; 140 141 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4); 142 return (pte_t *) pte + 143 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); 144 } 145 146 /* 147 * size: bytes to allocate in the nocache area. 148 * align: bytes, number to align at. 149 * Returns the virtual address of the allocated area. 150 */ 151 static void *__srmmu_get_nocache(int size, int align) 152 { 153 int offset; 154 unsigned long addr; 155 156 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { 157 printk(KERN_ERR "Size 0x%x too small for nocache request\n", 158 size); 159 size = SRMMU_NOCACHE_BITMAP_SHIFT; 160 } 161 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) { 162 printk(KERN_ERR "Size 0x%x unaligned int nocache request\n", 163 size); 164 size += SRMMU_NOCACHE_BITMAP_SHIFT - 1; 165 } 166 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX); 167 168 offset = bit_map_string_get(&srmmu_nocache_map, 169 size >> SRMMU_NOCACHE_BITMAP_SHIFT, 170 align >> SRMMU_NOCACHE_BITMAP_SHIFT); 171 if (offset == -1) { 172 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n", 173 size, (int) srmmu_nocache_size, 174 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); 175 return NULL; 176 } 177 178 addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT); 179 return (void *)addr; 180 } 181 182 void *srmmu_get_nocache(int size, int align) 183 { 184 void *tmp; 185 186 tmp = __srmmu_get_nocache(size, align); 187 188 if (tmp) 189 memset(tmp, 0, size); 190 191 return tmp; 192 } 193 194 void srmmu_free_nocache(void *addr, int size) 195 { 196 unsigned long vaddr; 197 int offset; 198 199 vaddr = (unsigned long)addr; 200 if (vaddr < SRMMU_NOCACHE_VADDR) { 201 printk("Vaddr %lx is smaller than nocache base 0x%lx\n", 202 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR); 203 BUG(); 204 } 205 if (vaddr + size > srmmu_nocache_end) { 206 printk("Vaddr %lx is bigger than nocache end 0x%lx\n", 207 vaddr, srmmu_nocache_end); 208 BUG(); 209 } 210 if (!is_power_of_2(size)) { 211 printk("Size 0x%x is not a power of 2\n", size); 212 BUG(); 213 } 214 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { 215 printk("Size 0x%x is too small\n", size); 216 BUG(); 217 } 218 if (vaddr & (size - 1)) { 219 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size); 220 BUG(); 221 } 222 223 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT; 224 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT; 225 226 bit_map_clear(&srmmu_nocache_map, offset, size); 227 } 228 229 static void srmmu_early_allocate_ptable_skeleton(unsigned long start, 230 unsigned long end); 231 232 /* Return how much physical memory we have. */ 233 static unsigned long __init probe_memory(void) 234 { 235 unsigned long total = 0; 236 int i; 237 238 for (i = 0; sp_banks[i].num_bytes; i++) 239 total += sp_banks[i].num_bytes; 240 241 return total; 242 } 243 244 /* 245 * Reserve nocache dynamically proportionally to the amount of 246 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002 247 */ 248 static void __init srmmu_nocache_calcsize(void) 249 { 250 unsigned long sysmemavail = probe_memory() / 1024; 251 int srmmu_nocache_npages; 252 253 srmmu_nocache_npages = 254 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256; 255 256 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */ 257 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256; 258 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES) 259 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES; 260 261 /* anything above 1280 blows up */ 262 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES) 263 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES; 264 265 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE; 266 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size; 267 } 268 269 static void __init srmmu_nocache_init(void) 270 { 271 void *srmmu_nocache_bitmap; 272 unsigned int bitmap_bits; 273 pgd_t *pgd; 274 pmd_t *pmd; 275 pte_t *pte; 276 unsigned long paddr, vaddr; 277 unsigned long pteval; 278 279 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT; 280 281 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size, 282 SRMMU_NOCACHE_ALIGN_MAX, 0UL); 283 memset(srmmu_nocache_pool, 0, srmmu_nocache_size); 284 285 srmmu_nocache_bitmap = 286 __alloc_bootmem(BITS_TO_LONGS(bitmap_bits) * sizeof(long), 287 SMP_CACHE_BYTES, 0UL); 288 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits); 289 290 srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); 291 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE); 292 init_mm.pgd = srmmu_swapper_pg_dir; 293 294 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end); 295 296 paddr = __pa((unsigned long)srmmu_nocache_pool); 297 vaddr = SRMMU_NOCACHE_VADDR; 298 299 while (vaddr < srmmu_nocache_end) { 300 pgd = pgd_offset_k(vaddr); 301 pmd = pmd_offset(__nocache_fix(pgd), vaddr); 302 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr); 303 304 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV); 305 306 if (srmmu_cache_pagetables) 307 pteval |= SRMMU_CACHE; 308 309 set_pte(__nocache_fix(pte), __pte(pteval)); 310 311 vaddr += PAGE_SIZE; 312 paddr += PAGE_SIZE; 313 } 314 315 flush_cache_all(); 316 flush_tlb_all(); 317 } 318 319 pgd_t *get_pgd_fast(void) 320 { 321 pgd_t *pgd = NULL; 322 323 pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); 324 if (pgd) { 325 pgd_t *init = pgd_offset_k(0); 326 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); 327 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, 328 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); 329 } 330 331 return pgd; 332 } 333 334 /* 335 * Hardware needs alignment to 256 only, but we align to whole page size 336 * to reduce fragmentation problems due to the buddy principle. 337 * XXX Provide actual fragmentation statistics in /proc. 338 * 339 * Alignments up to the page size are the same for physical and virtual 340 * addresses of the nocache area. 341 */ 342 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) 343 { 344 unsigned long pte; 345 struct page *page; 346 347 if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0) 348 return NULL; 349 page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT); 350 if (!pgtable_page_ctor(page)) { 351 __free_page(page); 352 return NULL; 353 } 354 return page; 355 } 356 357 void pte_free(struct mm_struct *mm, pgtable_t pte) 358 { 359 unsigned long p; 360 361 pgtable_page_dtor(pte); 362 p = (unsigned long)page_address(pte); /* Cached address (for test) */ 363 if (p == 0) 364 BUG(); 365 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */ 366 367 /* free non cached virtual address*/ 368 srmmu_free_nocache(__nocache_va(p), PTE_SIZE); 369 } 370 371 /* context handling - a dynamically sized pool is used */ 372 #define NO_CONTEXT -1 373 374 struct ctx_list { 375 struct ctx_list *next; 376 struct ctx_list *prev; 377 unsigned int ctx_number; 378 struct mm_struct *ctx_mm; 379 }; 380 381 static struct ctx_list *ctx_list_pool; 382 static struct ctx_list ctx_free; 383 static struct ctx_list ctx_used; 384 385 /* At boot time we determine the number of contexts */ 386 static int num_contexts; 387 388 static inline void remove_from_ctx_list(struct ctx_list *entry) 389 { 390 entry->next->prev = entry->prev; 391 entry->prev->next = entry->next; 392 } 393 394 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry) 395 { 396 entry->next = head; 397 (entry->prev = head->prev)->next = entry; 398 head->prev = entry; 399 } 400 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry) 401 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry) 402 403 404 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm) 405 { 406 struct ctx_list *ctxp; 407 408 ctxp = ctx_free.next; 409 if (ctxp != &ctx_free) { 410 remove_from_ctx_list(ctxp); 411 add_to_used_ctxlist(ctxp); 412 mm->context = ctxp->ctx_number; 413 ctxp->ctx_mm = mm; 414 return; 415 } 416 ctxp = ctx_used.next; 417 if (ctxp->ctx_mm == old_mm) 418 ctxp = ctxp->next; 419 if (ctxp == &ctx_used) 420 panic("out of mmu contexts"); 421 flush_cache_mm(ctxp->ctx_mm); 422 flush_tlb_mm(ctxp->ctx_mm); 423 remove_from_ctx_list(ctxp); 424 add_to_used_ctxlist(ctxp); 425 ctxp->ctx_mm->context = NO_CONTEXT; 426 ctxp->ctx_mm = mm; 427 mm->context = ctxp->ctx_number; 428 } 429 430 static inline void free_context(int context) 431 { 432 struct ctx_list *ctx_old; 433 434 ctx_old = ctx_list_pool + context; 435 remove_from_ctx_list(ctx_old); 436 add_to_free_ctxlist(ctx_old); 437 } 438 439 static void __init sparc_context_init(int numctx) 440 { 441 int ctx; 442 unsigned long size; 443 444 size = numctx * sizeof(struct ctx_list); 445 ctx_list_pool = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL); 446 447 for (ctx = 0; ctx < numctx; ctx++) { 448 struct ctx_list *clist; 449 450 clist = (ctx_list_pool + ctx); 451 clist->ctx_number = ctx; 452 clist->ctx_mm = NULL; 453 } 454 ctx_free.next = ctx_free.prev = &ctx_free; 455 ctx_used.next = ctx_used.prev = &ctx_used; 456 for (ctx = 0; ctx < numctx; ctx++) 457 add_to_free_ctxlist(ctx_list_pool + ctx); 458 } 459 460 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, 461 struct task_struct *tsk) 462 { 463 if (mm->context == NO_CONTEXT) { 464 spin_lock(&srmmu_context_spinlock); 465 alloc_context(old_mm, mm); 466 spin_unlock(&srmmu_context_spinlock); 467 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd); 468 } 469 470 if (sparc_cpu_model == sparc_leon) 471 leon_switch_mm(); 472 473 if (is_hypersparc) 474 hyper_flush_whole_icache(); 475 476 srmmu_set_context(mm->context); 477 } 478 479 /* Low level IO area allocation on the SRMMU. */ 480 static inline void srmmu_mapioaddr(unsigned long physaddr, 481 unsigned long virt_addr, int bus_type) 482 { 483 pgd_t *pgdp; 484 pmd_t *pmdp; 485 pte_t *ptep; 486 unsigned long tmp; 487 488 physaddr &= PAGE_MASK; 489 pgdp = pgd_offset_k(virt_addr); 490 pmdp = pmd_offset(pgdp, virt_addr); 491 ptep = pte_offset_kernel(pmdp, virt_addr); 492 tmp = (physaddr >> 4) | SRMMU_ET_PTE; 493 494 /* I need to test whether this is consistent over all 495 * sun4m's. The bus_type represents the upper 4 bits of 496 * 36-bit physical address on the I/O space lines... 497 */ 498 tmp |= (bus_type << 28); 499 tmp |= SRMMU_PRIV; 500 __flush_page_to_ram(virt_addr); 501 set_pte(ptep, __pte(tmp)); 502 } 503 504 void srmmu_mapiorange(unsigned int bus, unsigned long xpa, 505 unsigned long xva, unsigned int len) 506 { 507 while (len != 0) { 508 len -= PAGE_SIZE; 509 srmmu_mapioaddr(xpa, xva, bus); 510 xva += PAGE_SIZE; 511 xpa += PAGE_SIZE; 512 } 513 flush_tlb_all(); 514 } 515 516 static inline void srmmu_unmapioaddr(unsigned long virt_addr) 517 { 518 pgd_t *pgdp; 519 pmd_t *pmdp; 520 pte_t *ptep; 521 522 pgdp = pgd_offset_k(virt_addr); 523 pmdp = pmd_offset(pgdp, virt_addr); 524 ptep = pte_offset_kernel(pmdp, virt_addr); 525 526 /* No need to flush uncacheable page. */ 527 __pte_clear(ptep); 528 } 529 530 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) 531 { 532 while (len != 0) { 533 len -= PAGE_SIZE; 534 srmmu_unmapioaddr(virt_addr); 535 virt_addr += PAGE_SIZE; 536 } 537 flush_tlb_all(); 538 } 539 540 /* tsunami.S */ 541 extern void tsunami_flush_cache_all(void); 542 extern void tsunami_flush_cache_mm(struct mm_struct *mm); 543 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 544 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 545 extern void tsunami_flush_page_to_ram(unsigned long page); 546 extern void tsunami_flush_page_for_dma(unsigned long page); 547 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 548 extern void tsunami_flush_tlb_all(void); 549 extern void tsunami_flush_tlb_mm(struct mm_struct *mm); 550 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 551 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 552 extern void tsunami_setup_blockops(void); 553 554 /* swift.S */ 555 extern void swift_flush_cache_all(void); 556 extern void swift_flush_cache_mm(struct mm_struct *mm); 557 extern void swift_flush_cache_range(struct vm_area_struct *vma, 558 unsigned long start, unsigned long end); 559 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 560 extern void swift_flush_page_to_ram(unsigned long page); 561 extern void swift_flush_page_for_dma(unsigned long page); 562 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 563 extern void swift_flush_tlb_all(void); 564 extern void swift_flush_tlb_mm(struct mm_struct *mm); 565 extern void swift_flush_tlb_range(struct vm_area_struct *vma, 566 unsigned long start, unsigned long end); 567 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 568 569 #if 0 /* P3: deadwood to debug precise flushes on Swift. */ 570 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 571 { 572 int cctx, ctx1; 573 574 page &= PAGE_MASK; 575 if ((ctx1 = vma->vm_mm->context) != -1) { 576 cctx = srmmu_get_context(); 577 /* Is context # ever different from current context? P3 */ 578 if (cctx != ctx1) { 579 printk("flush ctx %02x curr %02x\n", ctx1, cctx); 580 srmmu_set_context(ctx1); 581 swift_flush_page(page); 582 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 583 "r" (page), "i" (ASI_M_FLUSH_PROBE)); 584 srmmu_set_context(cctx); 585 } else { 586 /* Rm. prot. bits from virt. c. */ 587 /* swift_flush_cache_all(); */ 588 /* swift_flush_cache_page(vma, page); */ 589 swift_flush_page(page); 590 591 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 592 "r" (page), "i" (ASI_M_FLUSH_PROBE)); 593 /* same as above: srmmu_flush_tlb_page() */ 594 } 595 } 596 } 597 #endif 598 599 /* 600 * The following are all MBUS based SRMMU modules, and therefore could 601 * be found in a multiprocessor configuration. On the whole, these 602 * chips seems to be much more touchy about DVMA and page tables 603 * with respect to cache coherency. 604 */ 605 606 /* viking.S */ 607 extern void viking_flush_cache_all(void); 608 extern void viking_flush_cache_mm(struct mm_struct *mm); 609 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start, 610 unsigned long end); 611 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 612 extern void viking_flush_page_to_ram(unsigned long page); 613 extern void viking_flush_page_for_dma(unsigned long page); 614 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr); 615 extern void viking_flush_page(unsigned long page); 616 extern void viking_mxcc_flush_page(unsigned long page); 617 extern void viking_flush_tlb_all(void); 618 extern void viking_flush_tlb_mm(struct mm_struct *mm); 619 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 620 unsigned long end); 621 extern void viking_flush_tlb_page(struct vm_area_struct *vma, 622 unsigned long page); 623 extern void sun4dsmp_flush_tlb_all(void); 624 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm); 625 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 626 unsigned long end); 627 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma, 628 unsigned long page); 629 630 /* hypersparc.S */ 631 extern void hypersparc_flush_cache_all(void); 632 extern void hypersparc_flush_cache_mm(struct mm_struct *mm); 633 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 634 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 635 extern void hypersparc_flush_page_to_ram(unsigned long page); 636 extern void hypersparc_flush_page_for_dma(unsigned long page); 637 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 638 extern void hypersparc_flush_tlb_all(void); 639 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm); 640 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 641 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 642 extern void hypersparc_setup_blockops(void); 643 644 /* 645 * NOTE: All of this startup code assumes the low 16mb (approx.) of 646 * kernel mappings are done with one single contiguous chunk of 647 * ram. On small ram machines (classics mainly) we only get 648 * around 8mb mapped for us. 649 */ 650 651 static void __init early_pgtable_allocfail(char *type) 652 { 653 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type); 654 prom_halt(); 655 } 656 657 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, 658 unsigned long end) 659 { 660 pgd_t *pgdp; 661 pmd_t *pmdp; 662 pte_t *ptep; 663 664 while (start < end) { 665 pgdp = pgd_offset_k(start); 666 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { 667 pmdp = __srmmu_get_nocache( 668 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 669 if (pmdp == NULL) 670 early_pgtable_allocfail("pmd"); 671 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); 672 pgd_set(__nocache_fix(pgdp), pmdp); 673 } 674 pmdp = pmd_offset(__nocache_fix(pgdp), start); 675 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { 676 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); 677 if (ptep == NULL) 678 early_pgtable_allocfail("pte"); 679 memset(__nocache_fix(ptep), 0, PTE_SIZE); 680 pmd_set(__nocache_fix(pmdp), ptep); 681 } 682 if (start > (0xffffffffUL - PMD_SIZE)) 683 break; 684 start = (start + PMD_SIZE) & PMD_MASK; 685 } 686 } 687 688 static void __init srmmu_allocate_ptable_skeleton(unsigned long start, 689 unsigned long end) 690 { 691 pgd_t *pgdp; 692 pmd_t *pmdp; 693 pte_t *ptep; 694 695 while (start < end) { 696 pgdp = pgd_offset_k(start); 697 if (pgd_none(*pgdp)) { 698 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 699 if (pmdp == NULL) 700 early_pgtable_allocfail("pmd"); 701 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE); 702 pgd_set(pgdp, pmdp); 703 } 704 pmdp = pmd_offset(pgdp, start); 705 if (srmmu_pmd_none(*pmdp)) { 706 ptep = __srmmu_get_nocache(PTE_SIZE, 707 PTE_SIZE); 708 if (ptep == NULL) 709 early_pgtable_allocfail("pte"); 710 memset(ptep, 0, PTE_SIZE); 711 pmd_set(pmdp, ptep); 712 } 713 if (start > (0xffffffffUL - PMD_SIZE)) 714 break; 715 start = (start + PMD_SIZE) & PMD_MASK; 716 } 717 } 718 719 /* These flush types are not available on all chips... */ 720 static inline unsigned long srmmu_probe(unsigned long vaddr) 721 { 722 unsigned long retval; 723 724 if (sparc_cpu_model != sparc_leon) { 725 726 vaddr &= PAGE_MASK; 727 __asm__ __volatile__("lda [%1] %2, %0\n\t" : 728 "=r" (retval) : 729 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE)); 730 } else { 731 retval = leon_swprobe(vaddr, NULL); 732 } 733 return retval; 734 } 735 736 /* 737 * This is much cleaner than poking around physical address space 738 * looking at the prom's page table directly which is what most 739 * other OS's do. Yuck... this is much better. 740 */ 741 static void __init srmmu_inherit_prom_mappings(unsigned long start, 742 unsigned long end) 743 { 744 unsigned long probed; 745 unsigned long addr; 746 pgd_t *pgdp; 747 pmd_t *pmdp; 748 pte_t *ptep; 749 int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */ 750 751 while (start <= end) { 752 if (start == 0) 753 break; /* probably wrap around */ 754 if (start == 0xfef00000) 755 start = KADB_DEBUGGER_BEGVM; 756 probed = srmmu_probe(start); 757 if (!probed) { 758 /* continue probing until we find an entry */ 759 start += PAGE_SIZE; 760 continue; 761 } 762 763 /* A red snapper, see what it really is. */ 764 what = 0; 765 addr = start - PAGE_SIZE; 766 767 if (!(start & ~(SRMMU_REAL_PMD_MASK))) { 768 if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed) 769 what = 1; 770 } 771 772 if (!(start & ~(SRMMU_PGDIR_MASK))) { 773 if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed) 774 what = 2; 775 } 776 777 pgdp = pgd_offset_k(start); 778 if (what == 2) { 779 *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed); 780 start += SRMMU_PGDIR_SIZE; 781 continue; 782 } 783 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { 784 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, 785 SRMMU_PMD_TABLE_SIZE); 786 if (pmdp == NULL) 787 early_pgtable_allocfail("pmd"); 788 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); 789 pgd_set(__nocache_fix(pgdp), pmdp); 790 } 791 pmdp = pmd_offset(__nocache_fix(pgdp), start); 792 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { 793 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); 794 if (ptep == NULL) 795 early_pgtable_allocfail("pte"); 796 memset(__nocache_fix(ptep), 0, PTE_SIZE); 797 pmd_set(__nocache_fix(pmdp), ptep); 798 } 799 if (what == 1) { 800 /* We bend the rule where all 16 PTPs in a pmd_t point 801 * inside the same PTE page, and we leak a perfectly 802 * good hardware PTE piece. Alternatives seem worse. 803 */ 804 unsigned int x; /* Index of HW PMD in soft cluster */ 805 unsigned long *val; 806 x = (start >> PMD_SHIFT) & 15; 807 val = &pmdp->pmdv[x]; 808 *(unsigned long *)__nocache_fix(val) = probed; 809 start += SRMMU_REAL_PMD_SIZE; 810 continue; 811 } 812 ptep = pte_offset_kernel(__nocache_fix(pmdp), start); 813 *(pte_t *)__nocache_fix(ptep) = __pte(probed); 814 start += PAGE_SIZE; 815 } 816 } 817 818 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID) 819 820 /* Create a third-level SRMMU 16MB page mapping. */ 821 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base) 822 { 823 pgd_t *pgdp = pgd_offset_k(vaddr); 824 unsigned long big_pte; 825 826 big_pte = KERNEL_PTE(phys_base >> 4); 827 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte); 828 } 829 830 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */ 831 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry) 832 { 833 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK); 834 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK); 835 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes); 836 /* Map "low" memory only */ 837 const unsigned long min_vaddr = PAGE_OFFSET; 838 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM; 839 840 if (vstart < min_vaddr || vstart >= max_vaddr) 841 return vstart; 842 843 if (vend > max_vaddr || vend < min_vaddr) 844 vend = max_vaddr; 845 846 while (vstart < vend) { 847 do_large_mapping(vstart, pstart); 848 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE; 849 } 850 return vstart; 851 } 852 853 static void __init map_kernel(void) 854 { 855 int i; 856 857 if (phys_base > 0) { 858 do_large_mapping(PAGE_OFFSET, phys_base); 859 } 860 861 for (i = 0; sp_banks[i].num_bytes != 0; i++) { 862 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i); 863 } 864 } 865 866 void (*poke_srmmu)(void) = NULL; 867 868 void __init srmmu_paging_init(void) 869 { 870 int i; 871 phandle cpunode; 872 char node_str[128]; 873 pgd_t *pgd; 874 pmd_t *pmd; 875 pte_t *pte; 876 unsigned long pages_avail; 877 878 init_mm.context = (unsigned long) NO_CONTEXT; 879 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */ 880 881 if (sparc_cpu_model == sun4d) 882 num_contexts = 65536; /* We know it is Viking */ 883 else { 884 /* Find the number of contexts on the srmmu. */ 885 cpunode = prom_getchild(prom_root_node); 886 num_contexts = 0; 887 while (cpunode != 0) { 888 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); 889 if (!strcmp(node_str, "cpu")) { 890 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8); 891 break; 892 } 893 cpunode = prom_getsibling(cpunode); 894 } 895 } 896 897 if (!num_contexts) { 898 prom_printf("Something wrong, can't find cpu node in paging_init.\n"); 899 prom_halt(); 900 } 901 902 pages_avail = 0; 903 last_valid_pfn = bootmem_init(&pages_avail); 904 905 srmmu_nocache_calcsize(); 906 srmmu_nocache_init(); 907 srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE)); 908 map_kernel(); 909 910 /* ctx table has to be physically aligned to its size */ 911 srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t)); 912 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table); 913 914 for (i = 0; i < num_contexts; i++) 915 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir); 916 917 flush_cache_all(); 918 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys); 919 #ifdef CONFIG_SMP 920 /* Stop from hanging here... */ 921 local_ops->tlb_all(); 922 #else 923 flush_tlb_all(); 924 #endif 925 poke_srmmu(); 926 927 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END); 928 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END); 929 930 srmmu_allocate_ptable_skeleton( 931 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP); 932 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END); 933 934 pgd = pgd_offset_k(PKMAP_BASE); 935 pmd = pmd_offset(pgd, PKMAP_BASE); 936 pte = pte_offset_kernel(pmd, PKMAP_BASE); 937 pkmap_page_table = pte; 938 939 flush_cache_all(); 940 flush_tlb_all(); 941 942 sparc_context_init(num_contexts); 943 944 kmap_init(); 945 946 { 947 unsigned long zones_size[MAX_NR_ZONES]; 948 unsigned long zholes_size[MAX_NR_ZONES]; 949 unsigned long npages; 950 int znum; 951 952 for (znum = 0; znum < MAX_NR_ZONES; znum++) 953 zones_size[znum] = zholes_size[znum] = 0; 954 955 npages = max_low_pfn - pfn_base; 956 957 zones_size[ZONE_DMA] = npages; 958 zholes_size[ZONE_DMA] = npages - pages_avail; 959 960 npages = highend_pfn - max_low_pfn; 961 zones_size[ZONE_HIGHMEM] = npages; 962 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages(); 963 964 free_area_init_node(0, zones_size, pfn_base, zholes_size); 965 } 966 } 967 968 void mmu_info(struct seq_file *m) 969 { 970 seq_printf(m, 971 "MMU type\t: %s\n" 972 "contexts\t: %d\n" 973 "nocache total\t: %ld\n" 974 "nocache used\t: %d\n", 975 srmmu_name, 976 num_contexts, 977 srmmu_nocache_size, 978 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); 979 } 980 981 int init_new_context(struct task_struct *tsk, struct mm_struct *mm) 982 { 983 mm->context = NO_CONTEXT; 984 return 0; 985 } 986 987 void destroy_context(struct mm_struct *mm) 988 { 989 990 if (mm->context != NO_CONTEXT) { 991 flush_cache_mm(mm); 992 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir); 993 flush_tlb_mm(mm); 994 spin_lock(&srmmu_context_spinlock); 995 free_context(mm->context); 996 spin_unlock(&srmmu_context_spinlock); 997 mm->context = NO_CONTEXT; 998 } 999 } 1000 1001 /* Init various srmmu chip types. */ 1002 static void __init srmmu_is_bad(void) 1003 { 1004 prom_printf("Could not determine SRMMU chip type.\n"); 1005 prom_halt(); 1006 } 1007 1008 static void __init init_vac_layout(void) 1009 { 1010 phandle nd; 1011 int cache_lines; 1012 char node_str[128]; 1013 #ifdef CONFIG_SMP 1014 int cpu = 0; 1015 unsigned long max_size = 0; 1016 unsigned long min_line_size = 0x10000000; 1017 #endif 1018 1019 nd = prom_getchild(prom_root_node); 1020 while ((nd = prom_getsibling(nd)) != 0) { 1021 prom_getstring(nd, "device_type", node_str, sizeof(node_str)); 1022 if (!strcmp(node_str, "cpu")) { 1023 vac_line_size = prom_getint(nd, "cache-line-size"); 1024 if (vac_line_size == -1) { 1025 prom_printf("can't determine cache-line-size, halting.\n"); 1026 prom_halt(); 1027 } 1028 cache_lines = prom_getint(nd, "cache-nlines"); 1029 if (cache_lines == -1) { 1030 prom_printf("can't determine cache-nlines, halting.\n"); 1031 prom_halt(); 1032 } 1033 1034 vac_cache_size = cache_lines * vac_line_size; 1035 #ifdef CONFIG_SMP 1036 if (vac_cache_size > max_size) 1037 max_size = vac_cache_size; 1038 if (vac_line_size < min_line_size) 1039 min_line_size = vac_line_size; 1040 //FIXME: cpus not contiguous!! 1041 cpu++; 1042 if (cpu >= nr_cpu_ids || !cpu_online(cpu)) 1043 break; 1044 #else 1045 break; 1046 #endif 1047 } 1048 } 1049 if (nd == 0) { 1050 prom_printf("No CPU nodes found, halting.\n"); 1051 prom_halt(); 1052 } 1053 #ifdef CONFIG_SMP 1054 vac_cache_size = max_size; 1055 vac_line_size = min_line_size; 1056 #endif 1057 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n", 1058 (int)vac_cache_size, (int)vac_line_size); 1059 } 1060 1061 static void poke_hypersparc(void) 1062 { 1063 volatile unsigned long clear; 1064 unsigned long mreg = srmmu_get_mmureg(); 1065 1066 hyper_flush_unconditional_combined(); 1067 1068 mreg &= ~(HYPERSPARC_CWENABLE); 1069 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE); 1070 mreg |= (HYPERSPARC_CMODE); 1071 1072 srmmu_set_mmureg(mreg); 1073 1074 #if 0 /* XXX I think this is bad news... -DaveM */ 1075 hyper_clear_all_tags(); 1076 #endif 1077 1078 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE); 1079 hyper_flush_whole_icache(); 1080 clear = srmmu_get_faddr(); 1081 clear = srmmu_get_fstatus(); 1082 } 1083 1084 static const struct sparc32_cachetlb_ops hypersparc_ops = { 1085 .cache_all = hypersparc_flush_cache_all, 1086 .cache_mm = hypersparc_flush_cache_mm, 1087 .cache_page = hypersparc_flush_cache_page, 1088 .cache_range = hypersparc_flush_cache_range, 1089 .tlb_all = hypersparc_flush_tlb_all, 1090 .tlb_mm = hypersparc_flush_tlb_mm, 1091 .tlb_page = hypersparc_flush_tlb_page, 1092 .tlb_range = hypersparc_flush_tlb_range, 1093 .page_to_ram = hypersparc_flush_page_to_ram, 1094 .sig_insns = hypersparc_flush_sig_insns, 1095 .page_for_dma = hypersparc_flush_page_for_dma, 1096 }; 1097 1098 static void __init init_hypersparc(void) 1099 { 1100 srmmu_name = "ROSS HyperSparc"; 1101 srmmu_modtype = HyperSparc; 1102 1103 init_vac_layout(); 1104 1105 is_hypersparc = 1; 1106 sparc32_cachetlb_ops = &hypersparc_ops; 1107 1108 poke_srmmu = poke_hypersparc; 1109 1110 hypersparc_setup_blockops(); 1111 } 1112 1113 static void poke_swift(void) 1114 { 1115 unsigned long mreg; 1116 1117 /* Clear any crap from the cache or else... */ 1118 swift_flush_cache_all(); 1119 1120 /* Enable I & D caches */ 1121 mreg = srmmu_get_mmureg(); 1122 mreg |= (SWIFT_IE | SWIFT_DE); 1123 /* 1124 * The Swift branch folding logic is completely broken. At 1125 * trap time, if things are just right, if can mistakenly 1126 * think that a trap is coming from kernel mode when in fact 1127 * it is coming from user mode (it mis-executes the branch in 1128 * the trap code). So you see things like crashme completely 1129 * hosing your machine which is completely unacceptable. Turn 1130 * this shit off... nice job Fujitsu. 1131 */ 1132 mreg &= ~(SWIFT_BF); 1133 srmmu_set_mmureg(mreg); 1134 } 1135 1136 static const struct sparc32_cachetlb_ops swift_ops = { 1137 .cache_all = swift_flush_cache_all, 1138 .cache_mm = swift_flush_cache_mm, 1139 .cache_page = swift_flush_cache_page, 1140 .cache_range = swift_flush_cache_range, 1141 .tlb_all = swift_flush_tlb_all, 1142 .tlb_mm = swift_flush_tlb_mm, 1143 .tlb_page = swift_flush_tlb_page, 1144 .tlb_range = swift_flush_tlb_range, 1145 .page_to_ram = swift_flush_page_to_ram, 1146 .sig_insns = swift_flush_sig_insns, 1147 .page_for_dma = swift_flush_page_for_dma, 1148 }; 1149 1150 #define SWIFT_MASKID_ADDR 0x10003018 1151 static void __init init_swift(void) 1152 { 1153 unsigned long swift_rev; 1154 1155 __asm__ __volatile__("lda [%1] %2, %0\n\t" 1156 "srl %0, 0x18, %0\n\t" : 1157 "=r" (swift_rev) : 1158 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS)); 1159 srmmu_name = "Fujitsu Swift"; 1160 switch (swift_rev) { 1161 case 0x11: 1162 case 0x20: 1163 case 0x23: 1164 case 0x30: 1165 srmmu_modtype = Swift_lots_o_bugs; 1166 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN); 1167 /* 1168 * Gee george, I wonder why Sun is so hush hush about 1169 * this hardware bug... really braindamage stuff going 1170 * on here. However I think we can find a way to avoid 1171 * all of the workaround overhead under Linux. Basically, 1172 * any page fault can cause kernel pages to become user 1173 * accessible (the mmu gets confused and clears some of 1174 * the ACC bits in kernel ptes). Aha, sounds pretty 1175 * horrible eh? But wait, after extensive testing it appears 1176 * that if you use pgd_t level large kernel pte's (like the 1177 * 4MB pages on the Pentium) the bug does not get tripped 1178 * at all. This avoids almost all of the major overhead. 1179 * Welcome to a world where your vendor tells you to, 1180 * "apply this kernel patch" instead of "sorry for the 1181 * broken hardware, send it back and we'll give you 1182 * properly functioning parts" 1183 */ 1184 break; 1185 case 0x25: 1186 case 0x31: 1187 srmmu_modtype = Swift_bad_c; 1188 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN; 1189 /* 1190 * You see Sun allude to this hardware bug but never 1191 * admit things directly, they'll say things like, 1192 * "the Swift chip cache problems" or similar. 1193 */ 1194 break; 1195 default: 1196 srmmu_modtype = Swift_ok; 1197 break; 1198 } 1199 1200 sparc32_cachetlb_ops = &swift_ops; 1201 flush_page_for_dma_global = 0; 1202 1203 /* 1204 * Are you now convinced that the Swift is one of the 1205 * biggest VLSI abortions of all time? Bravo Fujitsu! 1206 * Fujitsu, the !#?!%$'d up processor people. I bet if 1207 * you examined the microcode of the Swift you'd find 1208 * XXX's all over the place. 1209 */ 1210 poke_srmmu = poke_swift; 1211 } 1212 1213 static void turbosparc_flush_cache_all(void) 1214 { 1215 flush_user_windows(); 1216 turbosparc_idflash_clear(); 1217 } 1218 1219 static void turbosparc_flush_cache_mm(struct mm_struct *mm) 1220 { 1221 FLUSH_BEGIN(mm) 1222 flush_user_windows(); 1223 turbosparc_idflash_clear(); 1224 FLUSH_END 1225 } 1226 1227 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 1228 { 1229 FLUSH_BEGIN(vma->vm_mm) 1230 flush_user_windows(); 1231 turbosparc_idflash_clear(); 1232 FLUSH_END 1233 } 1234 1235 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page) 1236 { 1237 FLUSH_BEGIN(vma->vm_mm) 1238 flush_user_windows(); 1239 if (vma->vm_flags & VM_EXEC) 1240 turbosparc_flush_icache(); 1241 turbosparc_flush_dcache(); 1242 FLUSH_END 1243 } 1244 1245 /* TurboSparc is copy-back, if we turn it on, but this does not work. */ 1246 static void turbosparc_flush_page_to_ram(unsigned long page) 1247 { 1248 #ifdef TURBOSPARC_WRITEBACK 1249 volatile unsigned long clear; 1250 1251 if (srmmu_probe(page)) 1252 turbosparc_flush_page_cache(page); 1253 clear = srmmu_get_fstatus(); 1254 #endif 1255 } 1256 1257 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) 1258 { 1259 } 1260 1261 static void turbosparc_flush_page_for_dma(unsigned long page) 1262 { 1263 turbosparc_flush_dcache(); 1264 } 1265 1266 static void turbosparc_flush_tlb_all(void) 1267 { 1268 srmmu_flush_whole_tlb(); 1269 } 1270 1271 static void turbosparc_flush_tlb_mm(struct mm_struct *mm) 1272 { 1273 FLUSH_BEGIN(mm) 1274 srmmu_flush_whole_tlb(); 1275 FLUSH_END 1276 } 1277 1278 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 1279 { 1280 FLUSH_BEGIN(vma->vm_mm) 1281 srmmu_flush_whole_tlb(); 1282 FLUSH_END 1283 } 1284 1285 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 1286 { 1287 FLUSH_BEGIN(vma->vm_mm) 1288 srmmu_flush_whole_tlb(); 1289 FLUSH_END 1290 } 1291 1292 1293 static void poke_turbosparc(void) 1294 { 1295 unsigned long mreg = srmmu_get_mmureg(); 1296 unsigned long ccreg; 1297 1298 /* Clear any crap from the cache or else... */ 1299 turbosparc_flush_cache_all(); 1300 /* Temporarily disable I & D caches */ 1301 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); 1302 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */ 1303 srmmu_set_mmureg(mreg); 1304 1305 ccreg = turbosparc_get_ccreg(); 1306 1307 #ifdef TURBOSPARC_WRITEBACK 1308 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */ 1309 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE); 1310 /* Write-back D-cache, emulate VLSI 1311 * abortion number three, not number one */ 1312 #else 1313 /* For now let's play safe, optimize later */ 1314 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE); 1315 /* Do DVMA snooping in Dcache, Write-thru D-cache */ 1316 ccreg &= ~(TURBOSPARC_uS2); 1317 /* Emulate VLSI abortion number three, not number one */ 1318 #endif 1319 1320 switch (ccreg & 7) { 1321 case 0: /* No SE cache */ 1322 case 7: /* Test mode */ 1323 break; 1324 default: 1325 ccreg |= (TURBOSPARC_SCENABLE); 1326 } 1327 turbosparc_set_ccreg(ccreg); 1328 1329 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */ 1330 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */ 1331 srmmu_set_mmureg(mreg); 1332 } 1333 1334 static const struct sparc32_cachetlb_ops turbosparc_ops = { 1335 .cache_all = turbosparc_flush_cache_all, 1336 .cache_mm = turbosparc_flush_cache_mm, 1337 .cache_page = turbosparc_flush_cache_page, 1338 .cache_range = turbosparc_flush_cache_range, 1339 .tlb_all = turbosparc_flush_tlb_all, 1340 .tlb_mm = turbosparc_flush_tlb_mm, 1341 .tlb_page = turbosparc_flush_tlb_page, 1342 .tlb_range = turbosparc_flush_tlb_range, 1343 .page_to_ram = turbosparc_flush_page_to_ram, 1344 .sig_insns = turbosparc_flush_sig_insns, 1345 .page_for_dma = turbosparc_flush_page_for_dma, 1346 }; 1347 1348 static void __init init_turbosparc(void) 1349 { 1350 srmmu_name = "Fujitsu TurboSparc"; 1351 srmmu_modtype = TurboSparc; 1352 sparc32_cachetlb_ops = &turbosparc_ops; 1353 poke_srmmu = poke_turbosparc; 1354 } 1355 1356 static void poke_tsunami(void) 1357 { 1358 unsigned long mreg = srmmu_get_mmureg(); 1359 1360 tsunami_flush_icache(); 1361 tsunami_flush_dcache(); 1362 mreg &= ~TSUNAMI_ITD; 1363 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB); 1364 srmmu_set_mmureg(mreg); 1365 } 1366 1367 static const struct sparc32_cachetlb_ops tsunami_ops = { 1368 .cache_all = tsunami_flush_cache_all, 1369 .cache_mm = tsunami_flush_cache_mm, 1370 .cache_page = tsunami_flush_cache_page, 1371 .cache_range = tsunami_flush_cache_range, 1372 .tlb_all = tsunami_flush_tlb_all, 1373 .tlb_mm = tsunami_flush_tlb_mm, 1374 .tlb_page = tsunami_flush_tlb_page, 1375 .tlb_range = tsunami_flush_tlb_range, 1376 .page_to_ram = tsunami_flush_page_to_ram, 1377 .sig_insns = tsunami_flush_sig_insns, 1378 .page_for_dma = tsunami_flush_page_for_dma, 1379 }; 1380 1381 static void __init init_tsunami(void) 1382 { 1383 /* 1384 * Tsunami's pretty sane, Sun and TI actually got it 1385 * somewhat right this time. Fujitsu should have 1386 * taken some lessons from them. 1387 */ 1388 1389 srmmu_name = "TI Tsunami"; 1390 srmmu_modtype = Tsunami; 1391 sparc32_cachetlb_ops = &tsunami_ops; 1392 poke_srmmu = poke_tsunami; 1393 1394 tsunami_setup_blockops(); 1395 } 1396 1397 static void poke_viking(void) 1398 { 1399 unsigned long mreg = srmmu_get_mmureg(); 1400 static int smp_catch; 1401 1402 if (viking_mxcc_present) { 1403 unsigned long mxcc_control = mxcc_get_creg(); 1404 1405 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE); 1406 mxcc_control &= ~(MXCC_CTL_RRC); 1407 mxcc_set_creg(mxcc_control); 1408 1409 /* 1410 * We don't need memory parity checks. 1411 * XXX This is a mess, have to dig out later. ecd. 1412 viking_mxcc_turn_off_parity(&mreg, &mxcc_control); 1413 */ 1414 1415 /* We do cache ptables on MXCC. */ 1416 mreg |= VIKING_TCENABLE; 1417 } else { 1418 unsigned long bpreg; 1419 1420 mreg &= ~(VIKING_TCENABLE); 1421 if (smp_catch++) { 1422 /* Must disable mixed-cmd mode here for other cpu's. */ 1423 bpreg = viking_get_bpreg(); 1424 bpreg &= ~(VIKING_ACTION_MIX); 1425 viking_set_bpreg(bpreg); 1426 1427 /* Just in case PROM does something funny. */ 1428 msi_set_sync(); 1429 } 1430 } 1431 1432 mreg |= VIKING_SPENABLE; 1433 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE); 1434 mreg |= VIKING_SBENABLE; 1435 mreg &= ~(VIKING_ACENABLE); 1436 srmmu_set_mmureg(mreg); 1437 } 1438 1439 static struct sparc32_cachetlb_ops viking_ops = { 1440 .cache_all = viking_flush_cache_all, 1441 .cache_mm = viking_flush_cache_mm, 1442 .cache_page = viking_flush_cache_page, 1443 .cache_range = viking_flush_cache_range, 1444 .tlb_all = viking_flush_tlb_all, 1445 .tlb_mm = viking_flush_tlb_mm, 1446 .tlb_page = viking_flush_tlb_page, 1447 .tlb_range = viking_flush_tlb_range, 1448 .page_to_ram = viking_flush_page_to_ram, 1449 .sig_insns = viking_flush_sig_insns, 1450 .page_for_dma = viking_flush_page_for_dma, 1451 }; 1452 1453 #ifdef CONFIG_SMP 1454 /* On sun4d the cpu broadcasts local TLB flushes, so we can just 1455 * perform the local TLB flush and all the other cpus will see it. 1456 * But, unfortunately, there is a bug in the sun4d XBUS backplane 1457 * that requires that we add some synchronization to these flushes. 1458 * 1459 * The bug is that the fifo which keeps track of all the pending TLB 1460 * broadcasts in the system is an entry or two too small, so if we 1461 * have too many going at once we'll overflow that fifo and lose a TLB 1462 * flush resulting in corruption. 1463 * 1464 * Our workaround is to take a global spinlock around the TLB flushes, 1465 * which guarentees we won't ever have too many pending. It's a big 1466 * hammer, but a semaphore like system to make sure we only have N TLB 1467 * flushes going at once will require SMP locking anyways so there's 1468 * no real value in trying any harder than this. 1469 */ 1470 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = { 1471 .cache_all = viking_flush_cache_all, 1472 .cache_mm = viking_flush_cache_mm, 1473 .cache_page = viking_flush_cache_page, 1474 .cache_range = viking_flush_cache_range, 1475 .tlb_all = sun4dsmp_flush_tlb_all, 1476 .tlb_mm = sun4dsmp_flush_tlb_mm, 1477 .tlb_page = sun4dsmp_flush_tlb_page, 1478 .tlb_range = sun4dsmp_flush_tlb_range, 1479 .page_to_ram = viking_flush_page_to_ram, 1480 .sig_insns = viking_flush_sig_insns, 1481 .page_for_dma = viking_flush_page_for_dma, 1482 }; 1483 #endif 1484 1485 static void __init init_viking(void) 1486 { 1487 unsigned long mreg = srmmu_get_mmureg(); 1488 1489 /* Ahhh, the viking. SRMMU VLSI abortion number two... */ 1490 if (mreg & VIKING_MMODE) { 1491 srmmu_name = "TI Viking"; 1492 viking_mxcc_present = 0; 1493 msi_set_sync(); 1494 1495 /* 1496 * We need this to make sure old viking takes no hits 1497 * on it's cache for dma snoops to workaround the 1498 * "load from non-cacheable memory" interrupt bug. 1499 * This is only necessary because of the new way in 1500 * which we use the IOMMU. 1501 */ 1502 viking_ops.page_for_dma = viking_flush_page; 1503 #ifdef CONFIG_SMP 1504 viking_sun4d_smp_ops.page_for_dma = viking_flush_page; 1505 #endif 1506 flush_page_for_dma_global = 0; 1507 } else { 1508 srmmu_name = "TI Viking/MXCC"; 1509 viking_mxcc_present = 1; 1510 srmmu_cache_pagetables = 1; 1511 } 1512 1513 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) 1514 &viking_ops; 1515 #ifdef CONFIG_SMP 1516 if (sparc_cpu_model == sun4d) 1517 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) 1518 &viking_sun4d_smp_ops; 1519 #endif 1520 1521 poke_srmmu = poke_viking; 1522 } 1523 1524 /* Probe for the srmmu chip version. */ 1525 static void __init get_srmmu_type(void) 1526 { 1527 unsigned long mreg, psr; 1528 unsigned long mod_typ, mod_rev, psr_typ, psr_vers; 1529 1530 srmmu_modtype = SRMMU_INVAL_MOD; 1531 hwbug_bitmask = 0; 1532 1533 mreg = srmmu_get_mmureg(); psr = get_psr(); 1534 mod_typ = (mreg & 0xf0000000) >> 28; 1535 mod_rev = (mreg & 0x0f000000) >> 24; 1536 psr_typ = (psr >> 28) & 0xf; 1537 psr_vers = (psr >> 24) & 0xf; 1538 1539 /* First, check for sparc-leon. */ 1540 if (sparc_cpu_model == sparc_leon) { 1541 init_leon(); 1542 return; 1543 } 1544 1545 /* Second, check for HyperSparc or Cypress. */ 1546 if (mod_typ == 1) { 1547 switch (mod_rev) { 1548 case 7: 1549 /* UP or MP Hypersparc */ 1550 init_hypersparc(); 1551 break; 1552 case 0: 1553 case 2: 1554 case 10: 1555 case 11: 1556 case 12: 1557 case 13: 1558 case 14: 1559 case 15: 1560 default: 1561 prom_printf("Sparc-Linux Cypress support does not longer exit.\n"); 1562 prom_halt(); 1563 break; 1564 } 1565 return; 1566 } 1567 1568 /* Now Fujitsu TurboSparc. It might happen that it is 1569 * in Swift emulation mode, so we will check later... 1570 */ 1571 if (psr_typ == 0 && psr_vers == 5) { 1572 init_turbosparc(); 1573 return; 1574 } 1575 1576 /* Next check for Fujitsu Swift. */ 1577 if (psr_typ == 0 && psr_vers == 4) { 1578 phandle cpunode; 1579 char node_str[128]; 1580 1581 /* Look if it is not a TurboSparc emulating Swift... */ 1582 cpunode = prom_getchild(prom_root_node); 1583 while ((cpunode = prom_getsibling(cpunode)) != 0) { 1584 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); 1585 if (!strcmp(node_str, "cpu")) { 1586 if (!prom_getintdefault(cpunode, "psr-implementation", 1) && 1587 prom_getintdefault(cpunode, "psr-version", 1) == 5) { 1588 init_turbosparc(); 1589 return; 1590 } 1591 break; 1592 } 1593 } 1594 1595 init_swift(); 1596 return; 1597 } 1598 1599 /* Now the Viking family of srmmu. */ 1600 if (psr_typ == 4 && 1601 ((psr_vers == 0) || 1602 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) { 1603 init_viking(); 1604 return; 1605 } 1606 1607 /* Finally the Tsunami. */ 1608 if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) { 1609 init_tsunami(); 1610 return; 1611 } 1612 1613 /* Oh well */ 1614 srmmu_is_bad(); 1615 } 1616 1617 #ifdef CONFIG_SMP 1618 /* Local cross-calls. */ 1619 static void smp_flush_page_for_dma(unsigned long page) 1620 { 1621 xc1((smpfunc_t) local_ops->page_for_dma, page); 1622 local_ops->page_for_dma(page); 1623 } 1624 1625 static void smp_flush_cache_all(void) 1626 { 1627 xc0((smpfunc_t) local_ops->cache_all); 1628 local_ops->cache_all(); 1629 } 1630 1631 static void smp_flush_tlb_all(void) 1632 { 1633 xc0((smpfunc_t) local_ops->tlb_all); 1634 local_ops->tlb_all(); 1635 } 1636 1637 static void smp_flush_cache_mm(struct mm_struct *mm) 1638 { 1639 if (mm->context != NO_CONTEXT) { 1640 cpumask_t cpu_mask; 1641 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1642 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1643 if (!cpumask_empty(&cpu_mask)) 1644 xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm); 1645 local_ops->cache_mm(mm); 1646 } 1647 } 1648 1649 static void smp_flush_tlb_mm(struct mm_struct *mm) 1650 { 1651 if (mm->context != NO_CONTEXT) { 1652 cpumask_t cpu_mask; 1653 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1654 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1655 if (!cpumask_empty(&cpu_mask)) { 1656 xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm); 1657 if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm) 1658 cpumask_copy(mm_cpumask(mm), 1659 cpumask_of(smp_processor_id())); 1660 } 1661 local_ops->tlb_mm(mm); 1662 } 1663 } 1664 1665 static void smp_flush_cache_range(struct vm_area_struct *vma, 1666 unsigned long start, 1667 unsigned long end) 1668 { 1669 struct mm_struct *mm = vma->vm_mm; 1670 1671 if (mm->context != NO_CONTEXT) { 1672 cpumask_t cpu_mask; 1673 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1674 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1675 if (!cpumask_empty(&cpu_mask)) 1676 xc3((smpfunc_t) local_ops->cache_range, 1677 (unsigned long) vma, start, end); 1678 local_ops->cache_range(vma, start, end); 1679 } 1680 } 1681 1682 static void smp_flush_tlb_range(struct vm_area_struct *vma, 1683 unsigned long start, 1684 unsigned long end) 1685 { 1686 struct mm_struct *mm = vma->vm_mm; 1687 1688 if (mm->context != NO_CONTEXT) { 1689 cpumask_t cpu_mask; 1690 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1691 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1692 if (!cpumask_empty(&cpu_mask)) 1693 xc3((smpfunc_t) local_ops->tlb_range, 1694 (unsigned long) vma, start, end); 1695 local_ops->tlb_range(vma, start, end); 1696 } 1697 } 1698 1699 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) 1700 { 1701 struct mm_struct *mm = vma->vm_mm; 1702 1703 if (mm->context != NO_CONTEXT) { 1704 cpumask_t cpu_mask; 1705 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1706 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1707 if (!cpumask_empty(&cpu_mask)) 1708 xc2((smpfunc_t) local_ops->cache_page, 1709 (unsigned long) vma, page); 1710 local_ops->cache_page(vma, page); 1711 } 1712 } 1713 1714 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 1715 { 1716 struct mm_struct *mm = vma->vm_mm; 1717 1718 if (mm->context != NO_CONTEXT) { 1719 cpumask_t cpu_mask; 1720 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1721 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1722 if (!cpumask_empty(&cpu_mask)) 1723 xc2((smpfunc_t) local_ops->tlb_page, 1724 (unsigned long) vma, page); 1725 local_ops->tlb_page(vma, page); 1726 } 1727 } 1728 1729 static void smp_flush_page_to_ram(unsigned long page) 1730 { 1731 /* Current theory is that those who call this are the one's 1732 * who have just dirtied their cache with the pages contents 1733 * in kernel space, therefore we only run this on local cpu. 1734 * 1735 * XXX This experiment failed, research further... -DaveM 1736 */ 1737 #if 1 1738 xc1((smpfunc_t) local_ops->page_to_ram, page); 1739 #endif 1740 local_ops->page_to_ram(page); 1741 } 1742 1743 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) 1744 { 1745 cpumask_t cpu_mask; 1746 cpumask_copy(&cpu_mask, mm_cpumask(mm)); 1747 cpumask_clear_cpu(smp_processor_id(), &cpu_mask); 1748 if (!cpumask_empty(&cpu_mask)) 1749 xc2((smpfunc_t) local_ops->sig_insns, 1750 (unsigned long) mm, insn_addr); 1751 local_ops->sig_insns(mm, insn_addr); 1752 } 1753 1754 static struct sparc32_cachetlb_ops smp_cachetlb_ops = { 1755 .cache_all = smp_flush_cache_all, 1756 .cache_mm = smp_flush_cache_mm, 1757 .cache_page = smp_flush_cache_page, 1758 .cache_range = smp_flush_cache_range, 1759 .tlb_all = smp_flush_tlb_all, 1760 .tlb_mm = smp_flush_tlb_mm, 1761 .tlb_page = smp_flush_tlb_page, 1762 .tlb_range = smp_flush_tlb_range, 1763 .page_to_ram = smp_flush_page_to_ram, 1764 .sig_insns = smp_flush_sig_insns, 1765 .page_for_dma = smp_flush_page_for_dma, 1766 }; 1767 #endif 1768 1769 /* Load up routines and constants for sun4m and sun4d mmu */ 1770 void __init load_mmu(void) 1771 { 1772 /* Functions */ 1773 get_srmmu_type(); 1774 1775 #ifdef CONFIG_SMP 1776 /* El switcheroo... */ 1777 local_ops = sparc32_cachetlb_ops; 1778 1779 if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) { 1780 smp_cachetlb_ops.tlb_all = local_ops->tlb_all; 1781 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm; 1782 smp_cachetlb_ops.tlb_range = local_ops->tlb_range; 1783 smp_cachetlb_ops.tlb_page = local_ops->tlb_page; 1784 } 1785 1786 if (poke_srmmu == poke_viking) { 1787 /* Avoid unnecessary cross calls. */ 1788 smp_cachetlb_ops.cache_all = local_ops->cache_all; 1789 smp_cachetlb_ops.cache_mm = local_ops->cache_mm; 1790 smp_cachetlb_ops.cache_range = local_ops->cache_range; 1791 smp_cachetlb_ops.cache_page = local_ops->cache_page; 1792 1793 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram; 1794 smp_cachetlb_ops.sig_insns = local_ops->sig_insns; 1795 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma; 1796 } 1797 1798 /* It really is const after this point. */ 1799 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) 1800 &smp_cachetlb_ops; 1801 #endif 1802 1803 if (sparc_cpu_model == sun4d) 1804 ld_mmu_iounit(); 1805 else 1806 ld_mmu_iommu(); 1807 #ifdef CONFIG_SMP 1808 if (sparc_cpu_model == sun4d) 1809 sun4d_init_smp(); 1810 else if (sparc_cpu_model == sparc_leon) 1811 leon_init_smp(); 1812 else 1813 sun4m_init_smp(); 1814 #endif 1815 } 1816