1 /* 2 * srmmu.c: SRMMU specific routines for memory management. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com) 6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org) 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/mm.h> 13 #include <linux/slab.h> 14 #include <linux/vmalloc.h> 15 #include <linux/pagemap.h> 16 #include <linux/init.h> 17 #include <linux/spinlock.h> 18 #include <linux/bootmem.h> 19 #include <linux/fs.h> 20 #include <linux/seq_file.h> 21 #include <linux/kdebug.h> 22 23 #include <asm/bitext.h> 24 #include <asm/page.h> 25 #include <asm/pgalloc.h> 26 #include <asm/pgtable.h> 27 #include <asm/io.h> 28 #include <asm/vaddrs.h> 29 #include <asm/traps.h> 30 #include <asm/smp.h> 31 #include <asm/mbus.h> 32 #include <asm/cache.h> 33 #include <asm/oplib.h> 34 #include <asm/sbus.h> 35 #include <asm/asi.h> 36 #include <asm/msi.h> 37 #include <asm/a.out.h> 38 #include <asm/mmu_context.h> 39 #include <asm/io-unit.h> 40 #include <asm/cacheflush.h> 41 #include <asm/tlbflush.h> 42 43 /* Now the cpu specific definitions. */ 44 #include <asm/viking.h> 45 #include <asm/mxcc.h> 46 #include <asm/ross.h> 47 #include <asm/tsunami.h> 48 #include <asm/swift.h> 49 #include <asm/turbosparc.h> 50 51 #include <asm/btfixup.h> 52 53 enum mbus_module srmmu_modtype; 54 unsigned int hwbug_bitmask; 55 int vac_cache_size; 56 int vac_line_size; 57 58 extern struct resource sparc_iomap; 59 60 extern unsigned long last_valid_pfn; 61 62 extern unsigned long page_kernel; 63 64 pgd_t *srmmu_swapper_pg_dir; 65 66 #ifdef CONFIG_SMP 67 #define FLUSH_BEGIN(mm) 68 #define FLUSH_END 69 #else 70 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) { 71 #define FLUSH_END } 72 #endif 73 74 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long) 75 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page) 76 77 int flush_page_for_dma_global = 1; 78 79 #ifdef CONFIG_SMP 80 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long) 81 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page) 82 #endif 83 84 char *srmmu_name; 85 86 ctxd_t *srmmu_ctx_table_phys; 87 ctxd_t *srmmu_context_table; 88 89 int viking_mxcc_present; 90 static DEFINE_SPINLOCK(srmmu_context_spinlock); 91 92 int is_hypersparc; 93 94 /* 95 * In general all page table modifications should use the V8 atomic 96 * swap instruction. This insures the mmu and the cpu are in sync 97 * with respect to ref/mod bits in the page tables. 98 */ 99 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value) 100 { 101 __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr)); 102 return value; 103 } 104 105 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval) 106 { 107 srmmu_swap((unsigned long *)ptep, pte_val(pteval)); 108 } 109 110 /* The very generic SRMMU page table operations. */ 111 static inline int srmmu_device_memory(unsigned long x) 112 { 113 return ((x & 0xF0000000) != 0); 114 } 115 116 int srmmu_cache_pagetables; 117 118 /* these will be initialized in srmmu_nocache_calcsize() */ 119 unsigned long srmmu_nocache_size; 120 unsigned long srmmu_nocache_end; 121 122 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */ 123 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4) 124 125 /* The context table is a nocache user with the biggest alignment needs. */ 126 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS) 127 128 void *srmmu_nocache_pool; 129 void *srmmu_nocache_bitmap; 130 static struct bit_map srmmu_nocache_map; 131 132 static unsigned long srmmu_pte_pfn(pte_t pte) 133 { 134 if (srmmu_device_memory(pte_val(pte))) { 135 /* Just return something that will cause 136 * pfn_valid() to return false. This makes 137 * copy_one_pte() to just directly copy to 138 * PTE over. 139 */ 140 return ~0UL; 141 } 142 return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4); 143 } 144 145 static struct page *srmmu_pmd_page(pmd_t pmd) 146 { 147 148 if (srmmu_device_memory(pmd_val(pmd))) 149 BUG(); 150 return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4)); 151 } 152 153 static inline unsigned long srmmu_pgd_page(pgd_t pgd) 154 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); } 155 156 157 static inline int srmmu_pte_none(pte_t pte) 158 { return !(pte_val(pte) & 0xFFFFFFF); } 159 160 static inline int srmmu_pte_present(pte_t pte) 161 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); } 162 163 static inline void srmmu_pte_clear(pte_t *ptep) 164 { srmmu_set_pte(ptep, __pte(0)); } 165 166 static inline int srmmu_pmd_none(pmd_t pmd) 167 { return !(pmd_val(pmd) & 0xFFFFFFF); } 168 169 static inline int srmmu_pmd_bad(pmd_t pmd) 170 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; } 171 172 static inline int srmmu_pmd_present(pmd_t pmd) 173 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); } 174 175 static inline void srmmu_pmd_clear(pmd_t *pmdp) { 176 int i; 177 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) 178 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0)); 179 } 180 181 static inline int srmmu_pgd_none(pgd_t pgd) 182 { return !(pgd_val(pgd) & 0xFFFFFFF); } 183 184 static inline int srmmu_pgd_bad(pgd_t pgd) 185 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; } 186 187 static inline int srmmu_pgd_present(pgd_t pgd) 188 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); } 189 190 static inline void srmmu_pgd_clear(pgd_t * pgdp) 191 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); } 192 193 static inline pte_t srmmu_pte_wrprotect(pte_t pte) 194 { return __pte(pte_val(pte) & ~SRMMU_WRITE);} 195 196 static inline pte_t srmmu_pte_mkclean(pte_t pte) 197 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);} 198 199 static inline pte_t srmmu_pte_mkold(pte_t pte) 200 { return __pte(pte_val(pte) & ~SRMMU_REF);} 201 202 static inline pte_t srmmu_pte_mkwrite(pte_t pte) 203 { return __pte(pte_val(pte) | SRMMU_WRITE);} 204 205 static inline pte_t srmmu_pte_mkdirty(pte_t pte) 206 { return __pte(pte_val(pte) | SRMMU_DIRTY);} 207 208 static inline pte_t srmmu_pte_mkyoung(pte_t pte) 209 { return __pte(pte_val(pte) | SRMMU_REF);} 210 211 /* 212 * Conversion functions: convert a page and protection to a page entry, 213 * and a page entry and page directory to the page they refer to. 214 */ 215 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot) 216 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); } 217 218 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot) 219 { return __pte(((page) >> 4) | pgprot_val(pgprot)); } 220 221 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space) 222 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); } 223 224 /* XXX should we hyper_flush_whole_icache here - Anton */ 225 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp) 226 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); } 227 228 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp) 229 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); } 230 231 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep) 232 { 233 unsigned long ptp; /* Physical address, shifted right by 4 */ 234 int i; 235 236 ptp = __nocache_pa((unsigned long) ptep) >> 4; 237 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { 238 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); 239 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4); 240 } 241 } 242 243 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep) 244 { 245 unsigned long ptp; /* Physical address, shifted right by 4 */ 246 int i; 247 248 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */ 249 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { 250 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp); 251 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4); 252 } 253 } 254 255 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot) 256 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); } 257 258 /* to find an entry in a top-level page table... */ 259 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address) 260 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); } 261 262 /* Find an entry in the second-level page table.. */ 263 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address) 264 { 265 return (pmd_t *) srmmu_pgd_page(*dir) + 266 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); 267 } 268 269 /* Find an entry in the third-level page table.. */ 270 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address) 271 { 272 void *pte; 273 274 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4); 275 return (pte_t *) pte + 276 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); 277 } 278 279 static unsigned long srmmu_swp_type(swp_entry_t entry) 280 { 281 return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK; 282 } 283 284 static unsigned long srmmu_swp_offset(swp_entry_t entry) 285 { 286 return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK; 287 } 288 289 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset) 290 { 291 return (swp_entry_t) { 292 (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT 293 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT }; 294 } 295 296 /* 297 * size: bytes to allocate in the nocache area. 298 * align: bytes, number to align at. 299 * Returns the virtual address of the allocated area. 300 */ 301 static unsigned long __srmmu_get_nocache(int size, int align) 302 { 303 int offset; 304 305 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { 306 printk("Size 0x%x too small for nocache request\n", size); 307 size = SRMMU_NOCACHE_BITMAP_SHIFT; 308 } 309 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) { 310 printk("Size 0x%x unaligned int nocache request\n", size); 311 size += SRMMU_NOCACHE_BITMAP_SHIFT-1; 312 } 313 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX); 314 315 offset = bit_map_string_get(&srmmu_nocache_map, 316 size >> SRMMU_NOCACHE_BITMAP_SHIFT, 317 align >> SRMMU_NOCACHE_BITMAP_SHIFT); 318 if (offset == -1) { 319 printk("srmmu: out of nocache %d: %d/%d\n", 320 size, (int) srmmu_nocache_size, 321 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); 322 return 0; 323 } 324 325 return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT)); 326 } 327 328 unsigned inline long srmmu_get_nocache(int size, int align) 329 { 330 unsigned long tmp; 331 332 tmp = __srmmu_get_nocache(size, align); 333 334 if (tmp) 335 memset((void *)tmp, 0, size); 336 337 return tmp; 338 } 339 340 void srmmu_free_nocache(unsigned long vaddr, int size) 341 { 342 int offset; 343 344 if (vaddr < SRMMU_NOCACHE_VADDR) { 345 printk("Vaddr %lx is smaller than nocache base 0x%lx\n", 346 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR); 347 BUG(); 348 } 349 if (vaddr+size > srmmu_nocache_end) { 350 printk("Vaddr %lx is bigger than nocache end 0x%lx\n", 351 vaddr, srmmu_nocache_end); 352 BUG(); 353 } 354 if (size & (size-1)) { 355 printk("Size 0x%x is not a power of 2\n", size); 356 BUG(); 357 } 358 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { 359 printk("Size 0x%x is too small\n", size); 360 BUG(); 361 } 362 if (vaddr & (size-1)) { 363 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size); 364 BUG(); 365 } 366 367 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT; 368 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT; 369 370 bit_map_clear(&srmmu_nocache_map, offset, size); 371 } 372 373 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end); 374 375 extern unsigned long probe_memory(void); /* in fault.c */ 376 377 /* 378 * Reserve nocache dynamically proportionally to the amount of 379 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002 380 */ 381 void srmmu_nocache_calcsize(void) 382 { 383 unsigned long sysmemavail = probe_memory() / 1024; 384 int srmmu_nocache_npages; 385 386 srmmu_nocache_npages = 387 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256; 388 389 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */ 390 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256; 391 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES) 392 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES; 393 394 /* anything above 1280 blows up */ 395 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES) 396 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES; 397 398 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE; 399 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size; 400 } 401 402 void __init srmmu_nocache_init(void) 403 { 404 unsigned int bitmap_bits; 405 pgd_t *pgd; 406 pmd_t *pmd; 407 pte_t *pte; 408 unsigned long paddr, vaddr; 409 unsigned long pteval; 410 411 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT; 412 413 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size, 414 SRMMU_NOCACHE_ALIGN_MAX, 0UL); 415 memset(srmmu_nocache_pool, 0, srmmu_nocache_size); 416 417 srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL); 418 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits); 419 420 srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); 421 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE); 422 init_mm.pgd = srmmu_swapper_pg_dir; 423 424 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end); 425 426 paddr = __pa((unsigned long)srmmu_nocache_pool); 427 vaddr = SRMMU_NOCACHE_VADDR; 428 429 while (vaddr < srmmu_nocache_end) { 430 pgd = pgd_offset_k(vaddr); 431 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr); 432 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr); 433 434 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV); 435 436 if (srmmu_cache_pagetables) 437 pteval |= SRMMU_CACHE; 438 439 srmmu_set_pte(__nocache_fix(pte), __pte(pteval)); 440 441 vaddr += PAGE_SIZE; 442 paddr += PAGE_SIZE; 443 } 444 445 flush_cache_all(); 446 flush_tlb_all(); 447 } 448 449 static inline pgd_t *srmmu_get_pgd_fast(void) 450 { 451 pgd_t *pgd = NULL; 452 453 pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); 454 if (pgd) { 455 pgd_t *init = pgd_offset_k(0); 456 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); 457 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, 458 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); 459 } 460 461 return pgd; 462 } 463 464 static void srmmu_free_pgd_fast(pgd_t *pgd) 465 { 466 srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE); 467 } 468 469 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address) 470 { 471 return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 472 } 473 474 static void srmmu_pmd_free(pmd_t * pmd) 475 { 476 srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE); 477 } 478 479 /* 480 * Hardware needs alignment to 256 only, but we align to whole page size 481 * to reduce fragmentation problems due to the buddy principle. 482 * XXX Provide actual fragmentation statistics in /proc. 483 * 484 * Alignments up to the page size are the same for physical and virtual 485 * addresses of the nocache area. 486 */ 487 static pte_t * 488 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) 489 { 490 return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE); 491 } 492 493 static struct page * 494 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address) 495 { 496 unsigned long pte; 497 498 if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0) 499 return NULL; 500 return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT ); 501 } 502 503 static void srmmu_free_pte_fast(pte_t *pte) 504 { 505 srmmu_free_nocache((unsigned long)pte, PTE_SIZE); 506 } 507 508 static void srmmu_pte_free(struct page *pte) 509 { 510 unsigned long p; 511 512 p = (unsigned long)page_address(pte); /* Cached address (for test) */ 513 if (p == 0) 514 BUG(); 515 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */ 516 p = (unsigned long) __nocache_va(p); /* Nocached virtual */ 517 srmmu_free_nocache(p, PTE_SIZE); 518 } 519 520 /* 521 */ 522 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm) 523 { 524 struct ctx_list *ctxp; 525 526 ctxp = ctx_free.next; 527 if(ctxp != &ctx_free) { 528 remove_from_ctx_list(ctxp); 529 add_to_used_ctxlist(ctxp); 530 mm->context = ctxp->ctx_number; 531 ctxp->ctx_mm = mm; 532 return; 533 } 534 ctxp = ctx_used.next; 535 if(ctxp->ctx_mm == old_mm) 536 ctxp = ctxp->next; 537 if(ctxp == &ctx_used) 538 panic("out of mmu contexts"); 539 flush_cache_mm(ctxp->ctx_mm); 540 flush_tlb_mm(ctxp->ctx_mm); 541 remove_from_ctx_list(ctxp); 542 add_to_used_ctxlist(ctxp); 543 ctxp->ctx_mm->context = NO_CONTEXT; 544 ctxp->ctx_mm = mm; 545 mm->context = ctxp->ctx_number; 546 } 547 548 static inline void free_context(int context) 549 { 550 struct ctx_list *ctx_old; 551 552 ctx_old = ctx_list_pool + context; 553 remove_from_ctx_list(ctx_old); 554 add_to_free_ctxlist(ctx_old); 555 } 556 557 558 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, 559 struct task_struct *tsk, int cpu) 560 { 561 if(mm->context == NO_CONTEXT) { 562 spin_lock(&srmmu_context_spinlock); 563 alloc_context(old_mm, mm); 564 spin_unlock(&srmmu_context_spinlock); 565 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd); 566 } 567 568 if (is_hypersparc) 569 hyper_flush_whole_icache(); 570 571 srmmu_set_context(mm->context); 572 } 573 574 /* Low level IO area allocation on the SRMMU. */ 575 static inline void srmmu_mapioaddr(unsigned long physaddr, 576 unsigned long virt_addr, int bus_type) 577 { 578 pgd_t *pgdp; 579 pmd_t *pmdp; 580 pte_t *ptep; 581 unsigned long tmp; 582 583 physaddr &= PAGE_MASK; 584 pgdp = pgd_offset_k(virt_addr); 585 pmdp = srmmu_pmd_offset(pgdp, virt_addr); 586 ptep = srmmu_pte_offset(pmdp, virt_addr); 587 tmp = (physaddr >> 4) | SRMMU_ET_PTE; 588 589 /* 590 * I need to test whether this is consistent over all 591 * sun4m's. The bus_type represents the upper 4 bits of 592 * 36-bit physical address on the I/O space lines... 593 */ 594 tmp |= (bus_type << 28); 595 tmp |= SRMMU_PRIV; 596 __flush_page_to_ram(virt_addr); 597 srmmu_set_pte(ptep, __pte(tmp)); 598 } 599 600 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa, 601 unsigned long xva, unsigned int len) 602 { 603 while (len != 0) { 604 len -= PAGE_SIZE; 605 srmmu_mapioaddr(xpa, xva, bus); 606 xva += PAGE_SIZE; 607 xpa += PAGE_SIZE; 608 } 609 flush_tlb_all(); 610 } 611 612 static inline void srmmu_unmapioaddr(unsigned long virt_addr) 613 { 614 pgd_t *pgdp; 615 pmd_t *pmdp; 616 pte_t *ptep; 617 618 pgdp = pgd_offset_k(virt_addr); 619 pmdp = srmmu_pmd_offset(pgdp, virt_addr); 620 ptep = srmmu_pte_offset(pmdp, virt_addr); 621 622 /* No need to flush uncacheable page. */ 623 srmmu_pte_clear(ptep); 624 } 625 626 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) 627 { 628 while (len != 0) { 629 len -= PAGE_SIZE; 630 srmmu_unmapioaddr(virt_addr); 631 virt_addr += PAGE_SIZE; 632 } 633 flush_tlb_all(); 634 } 635 636 /* 637 * On the SRMMU we do not have the problems with limited tlb entries 638 * for mapping kernel pages, so we just take things from the free page 639 * pool. As a side effect we are putting a little too much pressure 640 * on the gfp() subsystem. This setup also makes the logic of the 641 * iommu mapping code a lot easier as we can transparently handle 642 * mappings on the kernel stack without any special code as we did 643 * need on the sun4c. 644 */ 645 struct thread_info *srmmu_alloc_thread_info(void) 646 { 647 struct thread_info *ret; 648 649 ret = (struct thread_info *)__get_free_pages(GFP_KERNEL, 650 THREAD_INFO_ORDER); 651 #ifdef CONFIG_DEBUG_STACK_USAGE 652 if (ret) 653 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER); 654 #endif /* DEBUG_STACK_USAGE */ 655 656 return ret; 657 } 658 659 static void srmmu_free_thread_info(struct thread_info *ti) 660 { 661 free_pages((unsigned long)ti, THREAD_INFO_ORDER); 662 } 663 664 /* tsunami.S */ 665 extern void tsunami_flush_cache_all(void); 666 extern void tsunami_flush_cache_mm(struct mm_struct *mm); 667 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 668 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 669 extern void tsunami_flush_page_to_ram(unsigned long page); 670 extern void tsunami_flush_page_for_dma(unsigned long page); 671 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 672 extern void tsunami_flush_tlb_all(void); 673 extern void tsunami_flush_tlb_mm(struct mm_struct *mm); 674 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 675 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 676 extern void tsunami_setup_blockops(void); 677 678 /* 679 * Workaround, until we find what's going on with Swift. When low on memory, 680 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find 681 * out it is already in page tables/ fault again on the same instruction. 682 * I really don't understand it, have checked it and contexts 683 * are right, flush_tlb_all is done as well, and it faults again... 684 * Strange. -jj 685 * 686 * The following code is a deadwood that may be necessary when 687 * we start to make precise page flushes again. --zaitcev 688 */ 689 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte) 690 { 691 #if 0 692 static unsigned long last; 693 unsigned int val; 694 /* unsigned int n; */ 695 696 if (address == last) { 697 val = srmmu_hwprobe(address); 698 if (val != 0 && pte_val(pte) != val) { 699 printk("swift_update_mmu_cache: " 700 "addr %lx put %08x probed %08x from %p\n", 701 address, pte_val(pte), val, 702 __builtin_return_address(0)); 703 srmmu_flush_whole_tlb(); 704 } 705 } 706 last = address; 707 #endif 708 } 709 710 /* swift.S */ 711 extern void swift_flush_cache_all(void); 712 extern void swift_flush_cache_mm(struct mm_struct *mm); 713 extern void swift_flush_cache_range(struct vm_area_struct *vma, 714 unsigned long start, unsigned long end); 715 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 716 extern void swift_flush_page_to_ram(unsigned long page); 717 extern void swift_flush_page_for_dma(unsigned long page); 718 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 719 extern void swift_flush_tlb_all(void); 720 extern void swift_flush_tlb_mm(struct mm_struct *mm); 721 extern void swift_flush_tlb_range(struct vm_area_struct *vma, 722 unsigned long start, unsigned long end); 723 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 724 725 #if 0 /* P3: deadwood to debug precise flushes on Swift. */ 726 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 727 { 728 int cctx, ctx1; 729 730 page &= PAGE_MASK; 731 if ((ctx1 = vma->vm_mm->context) != -1) { 732 cctx = srmmu_get_context(); 733 /* Is context # ever different from current context? P3 */ 734 if (cctx != ctx1) { 735 printk("flush ctx %02x curr %02x\n", ctx1, cctx); 736 srmmu_set_context(ctx1); 737 swift_flush_page(page); 738 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 739 "r" (page), "i" (ASI_M_FLUSH_PROBE)); 740 srmmu_set_context(cctx); 741 } else { 742 /* Rm. prot. bits from virt. c. */ 743 /* swift_flush_cache_all(); */ 744 /* swift_flush_cache_page(vma, page); */ 745 swift_flush_page(page); 746 747 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : 748 "r" (page), "i" (ASI_M_FLUSH_PROBE)); 749 /* same as above: srmmu_flush_tlb_page() */ 750 } 751 } 752 } 753 #endif 754 755 /* 756 * The following are all MBUS based SRMMU modules, and therefore could 757 * be found in a multiprocessor configuration. On the whole, these 758 * chips seems to be much more touchy about DVMA and page tables 759 * with respect to cache coherency. 760 */ 761 762 /* Cypress flushes. */ 763 static void cypress_flush_cache_all(void) 764 { 765 volatile unsigned long cypress_sucks; 766 unsigned long faddr, tagval; 767 768 flush_user_windows(); 769 for(faddr = 0; faddr < 0x10000; faddr += 0x20) { 770 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" : 771 "=r" (tagval) : 772 "r" (faddr), "r" (0x40000), 773 "i" (ASI_M_DATAC_TAG)); 774 775 /* If modified and valid, kick it. */ 776 if((tagval & 0x60) == 0x60) 777 cypress_sucks = *(unsigned long *)(0xf0020000 + faddr); 778 } 779 } 780 781 static void cypress_flush_cache_mm(struct mm_struct *mm) 782 { 783 register unsigned long a, b, c, d, e, f, g; 784 unsigned long flags, faddr; 785 int octx; 786 787 FLUSH_BEGIN(mm) 788 flush_user_windows(); 789 local_irq_save(flags); 790 octx = srmmu_get_context(); 791 srmmu_set_context(mm->context); 792 a = 0x20; b = 0x40; c = 0x60; 793 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; 794 795 faddr = (0x10000 - 0x100); 796 goto inside; 797 do { 798 faddr -= 0x100; 799 inside: 800 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" 801 "sta %%g0, [%0 + %2] %1\n\t" 802 "sta %%g0, [%0 + %3] %1\n\t" 803 "sta %%g0, [%0 + %4] %1\n\t" 804 "sta %%g0, [%0 + %5] %1\n\t" 805 "sta %%g0, [%0 + %6] %1\n\t" 806 "sta %%g0, [%0 + %7] %1\n\t" 807 "sta %%g0, [%0 + %8] %1\n\t" : : 808 "r" (faddr), "i" (ASI_M_FLUSH_CTX), 809 "r" (a), "r" (b), "r" (c), "r" (d), 810 "r" (e), "r" (f), "r" (g)); 811 } while(faddr); 812 srmmu_set_context(octx); 813 local_irq_restore(flags); 814 FLUSH_END 815 } 816 817 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 818 { 819 struct mm_struct *mm = vma->vm_mm; 820 register unsigned long a, b, c, d, e, f, g; 821 unsigned long flags, faddr; 822 int octx; 823 824 FLUSH_BEGIN(mm) 825 flush_user_windows(); 826 local_irq_save(flags); 827 octx = srmmu_get_context(); 828 srmmu_set_context(mm->context); 829 a = 0x20; b = 0x40; c = 0x60; 830 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; 831 832 start &= SRMMU_REAL_PMD_MASK; 833 while(start < end) { 834 faddr = (start + (0x10000 - 0x100)); 835 goto inside; 836 do { 837 faddr -= 0x100; 838 inside: 839 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" 840 "sta %%g0, [%0 + %2] %1\n\t" 841 "sta %%g0, [%0 + %3] %1\n\t" 842 "sta %%g0, [%0 + %4] %1\n\t" 843 "sta %%g0, [%0 + %5] %1\n\t" 844 "sta %%g0, [%0 + %6] %1\n\t" 845 "sta %%g0, [%0 + %7] %1\n\t" 846 "sta %%g0, [%0 + %8] %1\n\t" : : 847 "r" (faddr), 848 "i" (ASI_M_FLUSH_SEG), 849 "r" (a), "r" (b), "r" (c), "r" (d), 850 "r" (e), "r" (f), "r" (g)); 851 } while (faddr != start); 852 start += SRMMU_REAL_PMD_SIZE; 853 } 854 srmmu_set_context(octx); 855 local_irq_restore(flags); 856 FLUSH_END 857 } 858 859 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page) 860 { 861 register unsigned long a, b, c, d, e, f, g; 862 struct mm_struct *mm = vma->vm_mm; 863 unsigned long flags, line; 864 int octx; 865 866 FLUSH_BEGIN(mm) 867 flush_user_windows(); 868 local_irq_save(flags); 869 octx = srmmu_get_context(); 870 srmmu_set_context(mm->context); 871 a = 0x20; b = 0x40; c = 0x60; 872 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; 873 874 page &= PAGE_MASK; 875 line = (page + PAGE_SIZE) - 0x100; 876 goto inside; 877 do { 878 line -= 0x100; 879 inside: 880 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" 881 "sta %%g0, [%0 + %2] %1\n\t" 882 "sta %%g0, [%0 + %3] %1\n\t" 883 "sta %%g0, [%0 + %4] %1\n\t" 884 "sta %%g0, [%0 + %5] %1\n\t" 885 "sta %%g0, [%0 + %6] %1\n\t" 886 "sta %%g0, [%0 + %7] %1\n\t" 887 "sta %%g0, [%0 + %8] %1\n\t" : : 888 "r" (line), 889 "i" (ASI_M_FLUSH_PAGE), 890 "r" (a), "r" (b), "r" (c), "r" (d), 891 "r" (e), "r" (f), "r" (g)); 892 } while(line != page); 893 srmmu_set_context(octx); 894 local_irq_restore(flags); 895 FLUSH_END 896 } 897 898 /* Cypress is copy-back, at least that is how we configure it. */ 899 static void cypress_flush_page_to_ram(unsigned long page) 900 { 901 register unsigned long a, b, c, d, e, f, g; 902 unsigned long line; 903 904 a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0; 905 page &= PAGE_MASK; 906 line = (page + PAGE_SIZE) - 0x100; 907 goto inside; 908 do { 909 line -= 0x100; 910 inside: 911 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" 912 "sta %%g0, [%0 + %2] %1\n\t" 913 "sta %%g0, [%0 + %3] %1\n\t" 914 "sta %%g0, [%0 + %4] %1\n\t" 915 "sta %%g0, [%0 + %5] %1\n\t" 916 "sta %%g0, [%0 + %6] %1\n\t" 917 "sta %%g0, [%0 + %7] %1\n\t" 918 "sta %%g0, [%0 + %8] %1\n\t" : : 919 "r" (line), 920 "i" (ASI_M_FLUSH_PAGE), 921 "r" (a), "r" (b), "r" (c), "r" (d), 922 "r" (e), "r" (f), "r" (g)); 923 } while(line != page); 924 } 925 926 /* Cypress is also IO cache coherent. */ 927 static void cypress_flush_page_for_dma(unsigned long page) 928 { 929 } 930 931 /* Cypress has unified L2 VIPT, from which both instructions and data 932 * are stored. It does not have an onboard icache of any sort, therefore 933 * no flush is necessary. 934 */ 935 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) 936 { 937 } 938 939 static void cypress_flush_tlb_all(void) 940 { 941 srmmu_flush_whole_tlb(); 942 } 943 944 static void cypress_flush_tlb_mm(struct mm_struct *mm) 945 { 946 FLUSH_BEGIN(mm) 947 __asm__ __volatile__( 948 "lda [%0] %3, %%g5\n\t" 949 "sta %2, [%0] %3\n\t" 950 "sta %%g0, [%1] %4\n\t" 951 "sta %%g5, [%0] %3\n" 952 : /* no outputs */ 953 : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context), 954 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE) 955 : "g5"); 956 FLUSH_END 957 } 958 959 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 960 { 961 struct mm_struct *mm = vma->vm_mm; 962 unsigned long size; 963 964 FLUSH_BEGIN(mm) 965 start &= SRMMU_PGDIR_MASK; 966 size = SRMMU_PGDIR_ALIGN(end) - start; 967 __asm__ __volatile__( 968 "lda [%0] %5, %%g5\n\t" 969 "sta %1, [%0] %5\n" 970 "1:\n\t" 971 "subcc %3, %4, %3\n\t" 972 "bne 1b\n\t" 973 " sta %%g0, [%2 + %3] %6\n\t" 974 "sta %%g5, [%0] %5\n" 975 : /* no outputs */ 976 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200), 977 "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS), 978 "i" (ASI_M_FLUSH_PROBE) 979 : "g5", "cc"); 980 FLUSH_END 981 } 982 983 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 984 { 985 struct mm_struct *mm = vma->vm_mm; 986 987 FLUSH_BEGIN(mm) 988 __asm__ __volatile__( 989 "lda [%0] %3, %%g5\n\t" 990 "sta %1, [%0] %3\n\t" 991 "sta %%g0, [%2] %4\n\t" 992 "sta %%g5, [%0] %3\n" 993 : /* no outputs */ 994 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK), 995 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE) 996 : "g5"); 997 FLUSH_END 998 } 999 1000 /* viking.S */ 1001 extern void viking_flush_cache_all(void); 1002 extern void viking_flush_cache_mm(struct mm_struct *mm); 1003 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start, 1004 unsigned long end); 1005 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 1006 extern void viking_flush_page_to_ram(unsigned long page); 1007 extern void viking_flush_page_for_dma(unsigned long page); 1008 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr); 1009 extern void viking_flush_page(unsigned long page); 1010 extern void viking_mxcc_flush_page(unsigned long page); 1011 extern void viking_flush_tlb_all(void); 1012 extern void viking_flush_tlb_mm(struct mm_struct *mm); 1013 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 1014 unsigned long end); 1015 extern void viking_flush_tlb_page(struct vm_area_struct *vma, 1016 unsigned long page); 1017 extern void sun4dsmp_flush_tlb_all(void); 1018 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm); 1019 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 1020 unsigned long end); 1021 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma, 1022 unsigned long page); 1023 1024 /* hypersparc.S */ 1025 extern void hypersparc_flush_cache_all(void); 1026 extern void hypersparc_flush_cache_mm(struct mm_struct *mm); 1027 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 1028 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page); 1029 extern void hypersparc_flush_page_to_ram(unsigned long page); 1030 extern void hypersparc_flush_page_for_dma(unsigned long page); 1031 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); 1032 extern void hypersparc_flush_tlb_all(void); 1033 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm); 1034 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 1035 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 1036 extern void hypersparc_setup_blockops(void); 1037 1038 /* 1039 * NOTE: All of this startup code assumes the low 16mb (approx.) of 1040 * kernel mappings are done with one single contiguous chunk of 1041 * ram. On small ram machines (classics mainly) we only get 1042 * around 8mb mapped for us. 1043 */ 1044 1045 void __init early_pgtable_allocfail(char *type) 1046 { 1047 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type); 1048 prom_halt(); 1049 } 1050 1051 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end) 1052 { 1053 pgd_t *pgdp; 1054 pmd_t *pmdp; 1055 pte_t *ptep; 1056 1057 while(start < end) { 1058 pgdp = pgd_offset_k(start); 1059 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { 1060 pmdp = (pmd_t *) __srmmu_get_nocache( 1061 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 1062 if (pmdp == NULL) 1063 early_pgtable_allocfail("pmd"); 1064 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); 1065 srmmu_pgd_set(__nocache_fix(pgdp), pmdp); 1066 } 1067 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start); 1068 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { 1069 ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE); 1070 if (ptep == NULL) 1071 early_pgtable_allocfail("pte"); 1072 memset(__nocache_fix(ptep), 0, PTE_SIZE); 1073 srmmu_pmd_set(__nocache_fix(pmdp), ptep); 1074 } 1075 if (start > (0xffffffffUL - PMD_SIZE)) 1076 break; 1077 start = (start + PMD_SIZE) & PMD_MASK; 1078 } 1079 } 1080 1081 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end) 1082 { 1083 pgd_t *pgdp; 1084 pmd_t *pmdp; 1085 pte_t *ptep; 1086 1087 while(start < end) { 1088 pgdp = pgd_offset_k(start); 1089 if(srmmu_pgd_none(*pgdp)) { 1090 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 1091 if (pmdp == NULL) 1092 early_pgtable_allocfail("pmd"); 1093 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE); 1094 srmmu_pgd_set(pgdp, pmdp); 1095 } 1096 pmdp = srmmu_pmd_offset(pgdp, start); 1097 if(srmmu_pmd_none(*pmdp)) { 1098 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE, 1099 PTE_SIZE); 1100 if (ptep == NULL) 1101 early_pgtable_allocfail("pte"); 1102 memset(ptep, 0, PTE_SIZE); 1103 srmmu_pmd_set(pmdp, ptep); 1104 } 1105 if (start > (0xffffffffUL - PMD_SIZE)) 1106 break; 1107 start = (start + PMD_SIZE) & PMD_MASK; 1108 } 1109 } 1110 1111 /* 1112 * This is much cleaner than poking around physical address space 1113 * looking at the prom's page table directly which is what most 1114 * other OS's do. Yuck... this is much better. 1115 */ 1116 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end) 1117 { 1118 pgd_t *pgdp; 1119 pmd_t *pmdp; 1120 pte_t *ptep; 1121 int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */ 1122 unsigned long prompte; 1123 1124 while(start <= end) { 1125 if (start == 0) 1126 break; /* probably wrap around */ 1127 if(start == 0xfef00000) 1128 start = KADB_DEBUGGER_BEGVM; 1129 if(!(prompte = srmmu_hwprobe(start))) { 1130 start += PAGE_SIZE; 1131 continue; 1132 } 1133 1134 /* A red snapper, see what it really is. */ 1135 what = 0; 1136 1137 if(!(start & ~(SRMMU_REAL_PMD_MASK))) { 1138 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte) 1139 what = 1; 1140 } 1141 1142 if(!(start & ~(SRMMU_PGDIR_MASK))) { 1143 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) == 1144 prompte) 1145 what = 2; 1146 } 1147 1148 pgdp = pgd_offset_k(start); 1149 if(what == 2) { 1150 *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte); 1151 start += SRMMU_PGDIR_SIZE; 1152 continue; 1153 } 1154 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { 1155 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); 1156 if (pmdp == NULL) 1157 early_pgtable_allocfail("pmd"); 1158 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); 1159 srmmu_pgd_set(__nocache_fix(pgdp), pmdp); 1160 } 1161 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start); 1162 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { 1163 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE, 1164 PTE_SIZE); 1165 if (ptep == NULL) 1166 early_pgtable_allocfail("pte"); 1167 memset(__nocache_fix(ptep), 0, PTE_SIZE); 1168 srmmu_pmd_set(__nocache_fix(pmdp), ptep); 1169 } 1170 if(what == 1) { 1171 /* 1172 * We bend the rule where all 16 PTPs in a pmd_t point 1173 * inside the same PTE page, and we leak a perfectly 1174 * good hardware PTE piece. Alternatives seem worse. 1175 */ 1176 unsigned int x; /* Index of HW PMD in soft cluster */ 1177 x = (start >> PMD_SHIFT) & 15; 1178 *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte; 1179 start += SRMMU_REAL_PMD_SIZE; 1180 continue; 1181 } 1182 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start); 1183 *(pte_t *)__nocache_fix(ptep) = __pte(prompte); 1184 start += PAGE_SIZE; 1185 } 1186 } 1187 1188 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID) 1189 1190 /* Create a third-level SRMMU 16MB page mapping. */ 1191 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base) 1192 { 1193 pgd_t *pgdp = pgd_offset_k(vaddr); 1194 unsigned long big_pte; 1195 1196 big_pte = KERNEL_PTE(phys_base >> 4); 1197 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte); 1198 } 1199 1200 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */ 1201 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry) 1202 { 1203 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK); 1204 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK); 1205 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes); 1206 /* Map "low" memory only */ 1207 const unsigned long min_vaddr = PAGE_OFFSET; 1208 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM; 1209 1210 if (vstart < min_vaddr || vstart >= max_vaddr) 1211 return vstart; 1212 1213 if (vend > max_vaddr || vend < min_vaddr) 1214 vend = max_vaddr; 1215 1216 while(vstart < vend) { 1217 do_large_mapping(vstart, pstart); 1218 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE; 1219 } 1220 return vstart; 1221 } 1222 1223 static inline void memprobe_error(char *msg) 1224 { 1225 prom_printf(msg); 1226 prom_printf("Halting now...\n"); 1227 prom_halt(); 1228 } 1229 1230 static inline void map_kernel(void) 1231 { 1232 int i; 1233 1234 if (phys_base > 0) { 1235 do_large_mapping(PAGE_OFFSET, phys_base); 1236 } 1237 1238 for (i = 0; sp_banks[i].num_bytes != 0; i++) { 1239 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i); 1240 } 1241 1242 BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE); 1243 } 1244 1245 /* Paging initialization on the Sparc Reference MMU. */ 1246 extern void sparc_context_init(int); 1247 1248 void (*poke_srmmu)(void) __initdata = NULL; 1249 1250 extern unsigned long bootmem_init(unsigned long *pages_avail); 1251 1252 void __init srmmu_paging_init(void) 1253 { 1254 int i, cpunode; 1255 char node_str[128]; 1256 pgd_t *pgd; 1257 pmd_t *pmd; 1258 pte_t *pte; 1259 unsigned long pages_avail; 1260 1261 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */ 1262 1263 if (sparc_cpu_model == sun4d) 1264 num_contexts = 65536; /* We know it is Viking */ 1265 else { 1266 /* Find the number of contexts on the srmmu. */ 1267 cpunode = prom_getchild(prom_root_node); 1268 num_contexts = 0; 1269 while(cpunode != 0) { 1270 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); 1271 if(!strcmp(node_str, "cpu")) { 1272 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8); 1273 break; 1274 } 1275 cpunode = prom_getsibling(cpunode); 1276 } 1277 } 1278 1279 if(!num_contexts) { 1280 prom_printf("Something wrong, can't find cpu node in paging_init.\n"); 1281 prom_halt(); 1282 } 1283 1284 pages_avail = 0; 1285 last_valid_pfn = bootmem_init(&pages_avail); 1286 1287 srmmu_nocache_calcsize(); 1288 srmmu_nocache_init(); 1289 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE)); 1290 map_kernel(); 1291 1292 /* ctx table has to be physically aligned to its size */ 1293 srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t)); 1294 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table); 1295 1296 for(i = 0; i < num_contexts; i++) 1297 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir); 1298 1299 flush_cache_all(); 1300 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys); 1301 #ifdef CONFIG_SMP 1302 /* Stop from hanging here... */ 1303 local_flush_tlb_all(); 1304 #else 1305 flush_tlb_all(); 1306 #endif 1307 poke_srmmu(); 1308 1309 #ifdef CONFIG_SUN_IO 1310 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END); 1311 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END); 1312 #endif 1313 1314 srmmu_allocate_ptable_skeleton( 1315 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP); 1316 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END); 1317 1318 pgd = pgd_offset_k(PKMAP_BASE); 1319 pmd = srmmu_pmd_offset(pgd, PKMAP_BASE); 1320 pte = srmmu_pte_offset(pmd, PKMAP_BASE); 1321 pkmap_page_table = pte; 1322 1323 flush_cache_all(); 1324 flush_tlb_all(); 1325 1326 sparc_context_init(num_contexts); 1327 1328 kmap_init(); 1329 1330 { 1331 unsigned long zones_size[MAX_NR_ZONES]; 1332 unsigned long zholes_size[MAX_NR_ZONES]; 1333 unsigned long npages; 1334 int znum; 1335 1336 for (znum = 0; znum < MAX_NR_ZONES; znum++) 1337 zones_size[znum] = zholes_size[znum] = 0; 1338 1339 npages = max_low_pfn - pfn_base; 1340 1341 zones_size[ZONE_DMA] = npages; 1342 zholes_size[ZONE_DMA] = npages - pages_avail; 1343 1344 npages = highend_pfn - max_low_pfn; 1345 zones_size[ZONE_HIGHMEM] = npages; 1346 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages(); 1347 1348 free_area_init_node(0, &contig_page_data, zones_size, 1349 pfn_base, zholes_size); 1350 } 1351 } 1352 1353 static void srmmu_mmu_info(struct seq_file *m) 1354 { 1355 seq_printf(m, 1356 "MMU type\t: %s\n" 1357 "contexts\t: %d\n" 1358 "nocache total\t: %ld\n" 1359 "nocache used\t: %d\n", 1360 srmmu_name, 1361 num_contexts, 1362 srmmu_nocache_size, 1363 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); 1364 } 1365 1366 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte) 1367 { 1368 } 1369 1370 static void srmmu_destroy_context(struct mm_struct *mm) 1371 { 1372 1373 if(mm->context != NO_CONTEXT) { 1374 flush_cache_mm(mm); 1375 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir); 1376 flush_tlb_mm(mm); 1377 spin_lock(&srmmu_context_spinlock); 1378 free_context(mm->context); 1379 spin_unlock(&srmmu_context_spinlock); 1380 mm->context = NO_CONTEXT; 1381 } 1382 } 1383 1384 /* Init various srmmu chip types. */ 1385 static void __init srmmu_is_bad(void) 1386 { 1387 prom_printf("Could not determine SRMMU chip type.\n"); 1388 prom_halt(); 1389 } 1390 1391 static void __init init_vac_layout(void) 1392 { 1393 int nd, cache_lines; 1394 char node_str[128]; 1395 #ifdef CONFIG_SMP 1396 int cpu = 0; 1397 unsigned long max_size = 0; 1398 unsigned long min_line_size = 0x10000000; 1399 #endif 1400 1401 nd = prom_getchild(prom_root_node); 1402 while((nd = prom_getsibling(nd)) != 0) { 1403 prom_getstring(nd, "device_type", node_str, sizeof(node_str)); 1404 if(!strcmp(node_str, "cpu")) { 1405 vac_line_size = prom_getint(nd, "cache-line-size"); 1406 if (vac_line_size == -1) { 1407 prom_printf("can't determine cache-line-size, " 1408 "halting.\n"); 1409 prom_halt(); 1410 } 1411 cache_lines = prom_getint(nd, "cache-nlines"); 1412 if (cache_lines == -1) { 1413 prom_printf("can't determine cache-nlines, halting.\n"); 1414 prom_halt(); 1415 } 1416 1417 vac_cache_size = cache_lines * vac_line_size; 1418 #ifdef CONFIG_SMP 1419 if(vac_cache_size > max_size) 1420 max_size = vac_cache_size; 1421 if(vac_line_size < min_line_size) 1422 min_line_size = vac_line_size; 1423 //FIXME: cpus not contiguous!! 1424 cpu++; 1425 if (cpu >= NR_CPUS || !cpu_online(cpu)) 1426 break; 1427 #else 1428 break; 1429 #endif 1430 } 1431 } 1432 if(nd == 0) { 1433 prom_printf("No CPU nodes found, halting.\n"); 1434 prom_halt(); 1435 } 1436 #ifdef CONFIG_SMP 1437 vac_cache_size = max_size; 1438 vac_line_size = min_line_size; 1439 #endif 1440 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n", 1441 (int)vac_cache_size, (int)vac_line_size); 1442 } 1443 1444 static void __init poke_hypersparc(void) 1445 { 1446 volatile unsigned long clear; 1447 unsigned long mreg = srmmu_get_mmureg(); 1448 1449 hyper_flush_unconditional_combined(); 1450 1451 mreg &= ~(HYPERSPARC_CWENABLE); 1452 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE); 1453 mreg |= (HYPERSPARC_CMODE); 1454 1455 srmmu_set_mmureg(mreg); 1456 1457 #if 0 /* XXX I think this is bad news... -DaveM */ 1458 hyper_clear_all_tags(); 1459 #endif 1460 1461 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE); 1462 hyper_flush_whole_icache(); 1463 clear = srmmu_get_faddr(); 1464 clear = srmmu_get_fstatus(); 1465 } 1466 1467 static void __init init_hypersparc(void) 1468 { 1469 srmmu_name = "ROSS HyperSparc"; 1470 srmmu_modtype = HyperSparc; 1471 1472 init_vac_layout(); 1473 1474 is_hypersparc = 1; 1475 1476 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM); 1477 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM); 1478 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM); 1479 BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM); 1480 BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM); 1481 BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM); 1482 BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM); 1483 1484 BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM); 1485 BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM); 1486 BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM); 1487 BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM); 1488 1489 BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM); 1490 BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM); 1491 BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP); 1492 1493 1494 poke_srmmu = poke_hypersparc; 1495 1496 hypersparc_setup_blockops(); 1497 } 1498 1499 static void __init poke_cypress(void) 1500 { 1501 unsigned long mreg = srmmu_get_mmureg(); 1502 unsigned long faddr, tagval; 1503 volatile unsigned long cypress_sucks; 1504 volatile unsigned long clear; 1505 1506 clear = srmmu_get_faddr(); 1507 clear = srmmu_get_fstatus(); 1508 1509 if (!(mreg & CYPRESS_CENABLE)) { 1510 for(faddr = 0x0; faddr < 0x10000; faddr += 20) { 1511 __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t" 1512 "sta %%g0, [%0] %2\n\t" : : 1513 "r" (faddr), "r" (0x40000), 1514 "i" (ASI_M_DATAC_TAG)); 1515 } 1516 } else { 1517 for(faddr = 0; faddr < 0x10000; faddr += 0x20) { 1518 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" : 1519 "=r" (tagval) : 1520 "r" (faddr), "r" (0x40000), 1521 "i" (ASI_M_DATAC_TAG)); 1522 1523 /* If modified and valid, kick it. */ 1524 if((tagval & 0x60) == 0x60) 1525 cypress_sucks = *(unsigned long *) 1526 (0xf0020000 + faddr); 1527 } 1528 } 1529 1530 /* And one more, for our good neighbor, Mr. Broken Cypress. */ 1531 clear = srmmu_get_faddr(); 1532 clear = srmmu_get_fstatus(); 1533 1534 mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE); 1535 srmmu_set_mmureg(mreg); 1536 } 1537 1538 static void __init init_cypress_common(void) 1539 { 1540 init_vac_layout(); 1541 1542 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM); 1543 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM); 1544 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM); 1545 BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM); 1546 BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM); 1547 BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM); 1548 BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM); 1549 1550 BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM); 1551 BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM); 1552 BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM); 1553 BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM); 1554 1555 1556 BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM); 1557 BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP); 1558 BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP); 1559 1560 poke_srmmu = poke_cypress; 1561 } 1562 1563 static void __init init_cypress_604(void) 1564 { 1565 srmmu_name = "ROSS Cypress-604(UP)"; 1566 srmmu_modtype = Cypress; 1567 init_cypress_common(); 1568 } 1569 1570 static void __init init_cypress_605(unsigned long mrev) 1571 { 1572 srmmu_name = "ROSS Cypress-605(MP)"; 1573 if(mrev == 0xe) { 1574 srmmu_modtype = Cypress_vE; 1575 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN; 1576 } else { 1577 if(mrev == 0xd) { 1578 srmmu_modtype = Cypress_vD; 1579 hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN; 1580 } else { 1581 srmmu_modtype = Cypress; 1582 } 1583 } 1584 init_cypress_common(); 1585 } 1586 1587 static void __init poke_swift(void) 1588 { 1589 unsigned long mreg; 1590 1591 /* Clear any crap from the cache or else... */ 1592 swift_flush_cache_all(); 1593 1594 /* Enable I & D caches */ 1595 mreg = srmmu_get_mmureg(); 1596 mreg |= (SWIFT_IE | SWIFT_DE); 1597 /* 1598 * The Swift branch folding logic is completely broken. At 1599 * trap time, if things are just right, if can mistakenly 1600 * think that a trap is coming from kernel mode when in fact 1601 * it is coming from user mode (it mis-executes the branch in 1602 * the trap code). So you see things like crashme completely 1603 * hosing your machine which is completely unacceptable. Turn 1604 * this shit off... nice job Fujitsu. 1605 */ 1606 mreg &= ~(SWIFT_BF); 1607 srmmu_set_mmureg(mreg); 1608 } 1609 1610 #define SWIFT_MASKID_ADDR 0x10003018 1611 static void __init init_swift(void) 1612 { 1613 unsigned long swift_rev; 1614 1615 __asm__ __volatile__("lda [%1] %2, %0\n\t" 1616 "srl %0, 0x18, %0\n\t" : 1617 "=r" (swift_rev) : 1618 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS)); 1619 srmmu_name = "Fujitsu Swift"; 1620 switch(swift_rev) { 1621 case 0x11: 1622 case 0x20: 1623 case 0x23: 1624 case 0x30: 1625 srmmu_modtype = Swift_lots_o_bugs; 1626 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN); 1627 /* 1628 * Gee george, I wonder why Sun is so hush hush about 1629 * this hardware bug... really braindamage stuff going 1630 * on here. However I think we can find a way to avoid 1631 * all of the workaround overhead under Linux. Basically, 1632 * any page fault can cause kernel pages to become user 1633 * accessible (the mmu gets confused and clears some of 1634 * the ACC bits in kernel ptes). Aha, sounds pretty 1635 * horrible eh? But wait, after extensive testing it appears 1636 * that if you use pgd_t level large kernel pte's (like the 1637 * 4MB pages on the Pentium) the bug does not get tripped 1638 * at all. This avoids almost all of the major overhead. 1639 * Welcome to a world where your vendor tells you to, 1640 * "apply this kernel patch" instead of "sorry for the 1641 * broken hardware, send it back and we'll give you 1642 * properly functioning parts" 1643 */ 1644 break; 1645 case 0x25: 1646 case 0x31: 1647 srmmu_modtype = Swift_bad_c; 1648 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN; 1649 /* 1650 * You see Sun allude to this hardware bug but never 1651 * admit things directly, they'll say things like, 1652 * "the Swift chip cache problems" or similar. 1653 */ 1654 break; 1655 default: 1656 srmmu_modtype = Swift_ok; 1657 break; 1658 }; 1659 1660 BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM); 1661 BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM); 1662 BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM); 1663 BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM); 1664 1665 1666 BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM); 1667 BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM); 1668 BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM); 1669 BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM); 1670 1671 BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM); 1672 BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM); 1673 BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM); 1674 1675 BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM); 1676 1677 flush_page_for_dma_global = 0; 1678 1679 /* 1680 * Are you now convinced that the Swift is one of the 1681 * biggest VLSI abortions of all time? Bravo Fujitsu! 1682 * Fujitsu, the !#?!%$'d up processor people. I bet if 1683 * you examined the microcode of the Swift you'd find 1684 * XXX's all over the place. 1685 */ 1686 poke_srmmu = poke_swift; 1687 } 1688 1689 static void turbosparc_flush_cache_all(void) 1690 { 1691 flush_user_windows(); 1692 turbosparc_idflash_clear(); 1693 } 1694 1695 static void turbosparc_flush_cache_mm(struct mm_struct *mm) 1696 { 1697 FLUSH_BEGIN(mm) 1698 flush_user_windows(); 1699 turbosparc_idflash_clear(); 1700 FLUSH_END 1701 } 1702 1703 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 1704 { 1705 FLUSH_BEGIN(vma->vm_mm) 1706 flush_user_windows(); 1707 turbosparc_idflash_clear(); 1708 FLUSH_END 1709 } 1710 1711 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page) 1712 { 1713 FLUSH_BEGIN(vma->vm_mm) 1714 flush_user_windows(); 1715 if (vma->vm_flags & VM_EXEC) 1716 turbosparc_flush_icache(); 1717 turbosparc_flush_dcache(); 1718 FLUSH_END 1719 } 1720 1721 /* TurboSparc is copy-back, if we turn it on, but this does not work. */ 1722 static void turbosparc_flush_page_to_ram(unsigned long page) 1723 { 1724 #ifdef TURBOSPARC_WRITEBACK 1725 volatile unsigned long clear; 1726 1727 if (srmmu_hwprobe(page)) 1728 turbosparc_flush_page_cache(page); 1729 clear = srmmu_get_fstatus(); 1730 #endif 1731 } 1732 1733 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) 1734 { 1735 } 1736 1737 static void turbosparc_flush_page_for_dma(unsigned long page) 1738 { 1739 turbosparc_flush_dcache(); 1740 } 1741 1742 static void turbosparc_flush_tlb_all(void) 1743 { 1744 srmmu_flush_whole_tlb(); 1745 } 1746 1747 static void turbosparc_flush_tlb_mm(struct mm_struct *mm) 1748 { 1749 FLUSH_BEGIN(mm) 1750 srmmu_flush_whole_tlb(); 1751 FLUSH_END 1752 } 1753 1754 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 1755 { 1756 FLUSH_BEGIN(vma->vm_mm) 1757 srmmu_flush_whole_tlb(); 1758 FLUSH_END 1759 } 1760 1761 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 1762 { 1763 FLUSH_BEGIN(vma->vm_mm) 1764 srmmu_flush_whole_tlb(); 1765 FLUSH_END 1766 } 1767 1768 1769 static void __init poke_turbosparc(void) 1770 { 1771 unsigned long mreg = srmmu_get_mmureg(); 1772 unsigned long ccreg; 1773 1774 /* Clear any crap from the cache or else... */ 1775 turbosparc_flush_cache_all(); 1776 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */ 1777 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */ 1778 srmmu_set_mmureg(mreg); 1779 1780 ccreg = turbosparc_get_ccreg(); 1781 1782 #ifdef TURBOSPARC_WRITEBACK 1783 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */ 1784 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE); 1785 /* Write-back D-cache, emulate VLSI 1786 * abortion number three, not number one */ 1787 #else 1788 /* For now let's play safe, optimize later */ 1789 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE); 1790 /* Do DVMA snooping in Dcache, Write-thru D-cache */ 1791 ccreg &= ~(TURBOSPARC_uS2); 1792 /* Emulate VLSI abortion number three, not number one */ 1793 #endif 1794 1795 switch (ccreg & 7) { 1796 case 0: /* No SE cache */ 1797 case 7: /* Test mode */ 1798 break; 1799 default: 1800 ccreg |= (TURBOSPARC_SCENABLE); 1801 } 1802 turbosparc_set_ccreg (ccreg); 1803 1804 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */ 1805 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */ 1806 srmmu_set_mmureg(mreg); 1807 } 1808 1809 static void __init init_turbosparc(void) 1810 { 1811 srmmu_name = "Fujitsu TurboSparc"; 1812 srmmu_modtype = TurboSparc; 1813 1814 BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM); 1815 BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM); 1816 BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM); 1817 BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM); 1818 1819 BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM); 1820 BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM); 1821 BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM); 1822 BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM); 1823 1824 BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM); 1825 1826 BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP); 1827 BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM); 1828 1829 poke_srmmu = poke_turbosparc; 1830 } 1831 1832 static void __init poke_tsunami(void) 1833 { 1834 unsigned long mreg = srmmu_get_mmureg(); 1835 1836 tsunami_flush_icache(); 1837 tsunami_flush_dcache(); 1838 mreg &= ~TSUNAMI_ITD; 1839 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB); 1840 srmmu_set_mmureg(mreg); 1841 } 1842 1843 static void __init init_tsunami(void) 1844 { 1845 /* 1846 * Tsunami's pretty sane, Sun and TI actually got it 1847 * somewhat right this time. Fujitsu should have 1848 * taken some lessons from them. 1849 */ 1850 1851 srmmu_name = "TI Tsunami"; 1852 srmmu_modtype = Tsunami; 1853 1854 BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM); 1855 BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM); 1856 BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM); 1857 BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM); 1858 1859 1860 BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM); 1861 BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM); 1862 BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM); 1863 BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM); 1864 1865 BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP); 1866 BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM); 1867 BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM); 1868 1869 poke_srmmu = poke_tsunami; 1870 1871 tsunami_setup_blockops(); 1872 } 1873 1874 static void __init poke_viking(void) 1875 { 1876 unsigned long mreg = srmmu_get_mmureg(); 1877 static int smp_catch; 1878 1879 if(viking_mxcc_present) { 1880 unsigned long mxcc_control = mxcc_get_creg(); 1881 1882 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE); 1883 mxcc_control &= ~(MXCC_CTL_RRC); 1884 mxcc_set_creg(mxcc_control); 1885 1886 /* 1887 * We don't need memory parity checks. 1888 * XXX This is a mess, have to dig out later. ecd. 1889 viking_mxcc_turn_off_parity(&mreg, &mxcc_control); 1890 */ 1891 1892 /* We do cache ptables on MXCC. */ 1893 mreg |= VIKING_TCENABLE; 1894 } else { 1895 unsigned long bpreg; 1896 1897 mreg &= ~(VIKING_TCENABLE); 1898 if(smp_catch++) { 1899 /* Must disable mixed-cmd mode here for other cpu's. */ 1900 bpreg = viking_get_bpreg(); 1901 bpreg &= ~(VIKING_ACTION_MIX); 1902 viking_set_bpreg(bpreg); 1903 1904 /* Just in case PROM does something funny. */ 1905 msi_set_sync(); 1906 } 1907 } 1908 1909 mreg |= VIKING_SPENABLE; 1910 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE); 1911 mreg |= VIKING_SBENABLE; 1912 mreg &= ~(VIKING_ACENABLE); 1913 srmmu_set_mmureg(mreg); 1914 1915 #ifdef CONFIG_SMP 1916 /* Avoid unnecessary cross calls. */ 1917 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all); 1918 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm); 1919 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range); 1920 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page); 1921 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram); 1922 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns); 1923 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma); 1924 btfixup(); 1925 #endif 1926 } 1927 1928 static void __init init_viking(void) 1929 { 1930 unsigned long mreg = srmmu_get_mmureg(); 1931 1932 /* Ahhh, the viking. SRMMU VLSI abortion number two... */ 1933 if(mreg & VIKING_MMODE) { 1934 srmmu_name = "TI Viking"; 1935 viking_mxcc_present = 0; 1936 msi_set_sync(); 1937 1938 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM); 1939 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM); 1940 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM); 1941 1942 /* 1943 * We need this to make sure old viking takes no hits 1944 * on it's cache for dma snoops to workaround the 1945 * "load from non-cacheable memory" interrupt bug. 1946 * This is only necessary because of the new way in 1947 * which we use the IOMMU. 1948 */ 1949 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM); 1950 1951 flush_page_for_dma_global = 0; 1952 } else { 1953 srmmu_name = "TI Viking/MXCC"; 1954 viking_mxcc_present = 1; 1955 1956 srmmu_cache_pagetables = 1; 1957 1958 /* MXCC vikings lack the DMA snooping bug. */ 1959 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP); 1960 } 1961 1962 BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM); 1963 BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM); 1964 BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM); 1965 BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM); 1966 1967 #ifdef CONFIG_SMP 1968 if (sparc_cpu_model == sun4d) { 1969 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM); 1970 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM); 1971 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM); 1972 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM); 1973 } else 1974 #endif 1975 { 1976 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM); 1977 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM); 1978 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM); 1979 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM); 1980 } 1981 1982 BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP); 1983 BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP); 1984 1985 poke_srmmu = poke_viking; 1986 } 1987 1988 /* Probe for the srmmu chip version. */ 1989 static void __init get_srmmu_type(void) 1990 { 1991 unsigned long mreg, psr; 1992 unsigned long mod_typ, mod_rev, psr_typ, psr_vers; 1993 1994 srmmu_modtype = SRMMU_INVAL_MOD; 1995 hwbug_bitmask = 0; 1996 1997 mreg = srmmu_get_mmureg(); psr = get_psr(); 1998 mod_typ = (mreg & 0xf0000000) >> 28; 1999 mod_rev = (mreg & 0x0f000000) >> 24; 2000 psr_typ = (psr >> 28) & 0xf; 2001 psr_vers = (psr >> 24) & 0xf; 2002 2003 /* First, check for HyperSparc or Cypress. */ 2004 if(mod_typ == 1) { 2005 switch(mod_rev) { 2006 case 7: 2007 /* UP or MP Hypersparc */ 2008 init_hypersparc(); 2009 break; 2010 case 0: 2011 case 2: 2012 /* Uniprocessor Cypress */ 2013 init_cypress_604(); 2014 break; 2015 case 10: 2016 case 11: 2017 case 12: 2018 /* _REALLY OLD_ Cypress MP chips... */ 2019 case 13: 2020 case 14: 2021 case 15: 2022 /* MP Cypress mmu/cache-controller */ 2023 init_cypress_605(mod_rev); 2024 break; 2025 default: 2026 /* Some other Cypress revision, assume a 605. */ 2027 init_cypress_605(mod_rev); 2028 break; 2029 }; 2030 return; 2031 } 2032 2033 /* 2034 * Now Fujitsu TurboSparc. It might happen that it is 2035 * in Swift emulation mode, so we will check later... 2036 */ 2037 if (psr_typ == 0 && psr_vers == 5) { 2038 init_turbosparc(); 2039 return; 2040 } 2041 2042 /* Next check for Fujitsu Swift. */ 2043 if(psr_typ == 0 && psr_vers == 4) { 2044 int cpunode; 2045 char node_str[128]; 2046 2047 /* Look if it is not a TurboSparc emulating Swift... */ 2048 cpunode = prom_getchild(prom_root_node); 2049 while((cpunode = prom_getsibling(cpunode)) != 0) { 2050 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); 2051 if(!strcmp(node_str, "cpu")) { 2052 if (!prom_getintdefault(cpunode, "psr-implementation", 1) && 2053 prom_getintdefault(cpunode, "psr-version", 1) == 5) { 2054 init_turbosparc(); 2055 return; 2056 } 2057 break; 2058 } 2059 } 2060 2061 init_swift(); 2062 return; 2063 } 2064 2065 /* Now the Viking family of srmmu. */ 2066 if(psr_typ == 4 && 2067 ((psr_vers == 0) || 2068 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) { 2069 init_viking(); 2070 return; 2071 } 2072 2073 /* Finally the Tsunami. */ 2074 if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) { 2075 init_tsunami(); 2076 return; 2077 } 2078 2079 /* Oh well */ 2080 srmmu_is_bad(); 2081 } 2082 2083 /* don't laugh, static pagetables */ 2084 static void srmmu_check_pgt_cache(int low, int high) 2085 { 2086 } 2087 2088 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme, 2089 tsetup_mmu_patchme, rtrap_mmu_patchme; 2090 2091 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk, 2092 tsetup_srmmu_stackchk, srmmu_rett_stackchk; 2093 2094 extern unsigned long srmmu_fault; 2095 2096 #define PATCH_BRANCH(insn, dest) do { \ 2097 iaddr = &(insn); \ 2098 daddr = &(dest); \ 2099 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \ 2100 } while(0) 2101 2102 static void __init patch_window_trap_handlers(void) 2103 { 2104 unsigned long *iaddr, *daddr; 2105 2106 PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk); 2107 PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk); 2108 PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk); 2109 PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk); 2110 PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault); 2111 PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault); 2112 PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault); 2113 } 2114 2115 #ifdef CONFIG_SMP 2116 /* Local cross-calls. */ 2117 static void smp_flush_page_for_dma(unsigned long page) 2118 { 2119 xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page); 2120 local_flush_page_for_dma(page); 2121 } 2122 2123 #endif 2124 2125 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff) 2126 { 2127 return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE); 2128 } 2129 2130 static unsigned long srmmu_pte_to_pgoff(pte_t pte) 2131 { 2132 return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT; 2133 } 2134 2135 static pgprot_t srmmu_pgprot_noncached(pgprot_t prot) 2136 { 2137 prot &= ~__pgprot(SRMMU_CACHE); 2138 2139 return prot; 2140 } 2141 2142 /* Load up routines and constants for sun4m and sun4d mmu */ 2143 void __init ld_mmu_srmmu(void) 2144 { 2145 extern void ld_mmu_iommu(void); 2146 extern void ld_mmu_iounit(void); 2147 extern void ___xchg32_sun4md(void); 2148 2149 BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT); 2150 BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE); 2151 BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK); 2152 2153 BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD); 2154 BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD); 2155 2156 BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE)); 2157 PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED); 2158 BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY)); 2159 BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY)); 2160 BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL)); 2161 page_kernel = pgprot_val(SRMMU_PAGE_KERNEL); 2162 2163 /* Functions */ 2164 BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM); 2165 #ifndef CONFIG_SMP 2166 BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2); 2167 #endif 2168 BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP); 2169 2170 BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1); 2171 BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM); 2172 2173 BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM); 2174 BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM); 2175 BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM); 2176 2177 BTFIXUPSET_SETHI(none_mask, 0xF0000000); 2178 2179 BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM); 2180 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0); 2181 2182 BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM); 2183 BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM); 2184 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0); 2185 2186 BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM); 2187 BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM); 2188 BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM); 2189 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0); 2190 2191 BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM); 2192 BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM); 2193 BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM); 2194 BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM); 2195 BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM); 2196 BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM); 2197 2198 BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK); 2199 BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM); 2200 BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM); 2201 2202 BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM); 2203 BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM); 2204 BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM); 2205 BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM); 2206 BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM); 2207 BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM); 2208 BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM); 2209 BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM); 2210 2211 BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE); 2212 BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY); 2213 BTFIXUPSET_HALF(pte_youngi, SRMMU_REF); 2214 BTFIXUPSET_HALF(pte_filei, SRMMU_FILE); 2215 BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE); 2216 BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY); 2217 BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF); 2218 BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE)); 2219 BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY)); 2220 BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF)); 2221 BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP); 2222 BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM); 2223 2224 BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM); 2225 BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM); 2226 2227 BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM); 2228 BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM); 2229 BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM); 2230 2231 BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM); 2232 2233 BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM); 2234 BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM); 2235 2236 BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM); 2237 BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM); 2238 2239 get_srmmu_type(); 2240 patch_window_trap_handlers(); 2241 2242 #ifdef CONFIG_SMP 2243 /* El switcheroo... */ 2244 2245 BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all); 2246 BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm); 2247 BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range); 2248 BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page); 2249 BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all); 2250 BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm); 2251 BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range); 2252 BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page); 2253 BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram); 2254 BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns); 2255 BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma); 2256 2257 BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM); 2258 BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM); 2259 BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM); 2260 BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM); 2261 if (sparc_cpu_model != sun4d) { 2262 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM); 2263 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM); 2264 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM); 2265 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM); 2266 } 2267 BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM); 2268 BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM); 2269 BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM); 2270 #endif 2271 2272 if (sparc_cpu_model == sun4d) 2273 ld_mmu_iounit(); 2274 else 2275 ld_mmu_iommu(); 2276 #ifdef CONFIG_SMP 2277 if (sparc_cpu_model == sun4d) 2278 sun4d_init_smp(); 2279 else 2280 sun4m_init_smp(); 2281 #endif 2282 } 2283