1 /* 2 * arch/sparc64/mm/init.c 3 * 4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/sched.h> 11 #include <linux/string.h> 12 #include <linux/init.h> 13 #include <linux/bootmem.h> 14 #include <linux/mm.h> 15 #include <linux/hugetlb.h> 16 #include <linux/slab.h> 17 #include <linux/initrd.h> 18 #include <linux/swap.h> 19 #include <linux/pagemap.h> 20 #include <linux/poison.h> 21 #include <linux/fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/kprobes.h> 24 #include <linux/cache.h> 25 #include <linux/sort.h> 26 #include <linux/percpu.h> 27 #include <linux/lmb.h> 28 #include <linux/mmzone.h> 29 30 #include <asm/head.h> 31 #include <asm/system.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/pgtable.h> 35 #include <asm/oplib.h> 36 #include <asm/iommu.h> 37 #include <asm/io.h> 38 #include <asm/uaccess.h> 39 #include <asm/mmu_context.h> 40 #include <asm/tlbflush.h> 41 #include <asm/dma.h> 42 #include <asm/starfire.h> 43 #include <asm/tlb.h> 44 #include <asm/spitfire.h> 45 #include <asm/sections.h> 46 #include <asm/tsb.h> 47 #include <asm/hypervisor.h> 48 #include <asm/prom.h> 49 #include <asm/mdesc.h> 50 #include <asm/cpudata.h> 51 #include <asm/irq.h> 52 53 #include "init_64.h" 54 55 unsigned long kern_linear_pte_xor[2] __read_mostly; 56 57 /* A bitmap, one bit for every 256MB of physical memory. If the bit 58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else 59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]). 60 */ 61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)]; 62 63 #ifndef CONFIG_DEBUG_PAGEALLOC 64 /* A special kernel TSB for 4MB and 256MB linear mappings. 65 * Space is allocated for this right after the trap table 66 * in arch/sparc64/kernel/head.S 67 */ 68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 69 #endif 70 71 #define MAX_BANKS 32 72 73 static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata; 74 static int pavail_ents __devinitdata; 75 76 static int cmp_p64(const void *a, const void *b) 77 { 78 const struct linux_prom64_registers *x = a, *y = b; 79 80 if (x->phys_addr > y->phys_addr) 81 return 1; 82 if (x->phys_addr < y->phys_addr) 83 return -1; 84 return 0; 85 } 86 87 static void __init read_obp_memory(const char *property, 88 struct linux_prom64_registers *regs, 89 int *num_ents) 90 { 91 int node = prom_finddevice("/memory"); 92 int prop_size = prom_getproplen(node, property); 93 int ents, ret, i; 94 95 ents = prop_size / sizeof(struct linux_prom64_registers); 96 if (ents > MAX_BANKS) { 97 prom_printf("The machine has more %s property entries than " 98 "this kernel can support (%d).\n", 99 property, MAX_BANKS); 100 prom_halt(); 101 } 102 103 ret = prom_getproperty(node, property, (char *) regs, prop_size); 104 if (ret == -1) { 105 prom_printf("Couldn't get %s property from /memory.\n"); 106 prom_halt(); 107 } 108 109 /* Sanitize what we got from the firmware, by page aligning 110 * everything. 111 */ 112 for (i = 0; i < ents; i++) { 113 unsigned long base, size; 114 115 base = regs[i].phys_addr; 116 size = regs[i].reg_size; 117 118 size &= PAGE_MASK; 119 if (base & ~PAGE_MASK) { 120 unsigned long new_base = PAGE_ALIGN(base); 121 122 size -= new_base - base; 123 if ((long) size < 0L) 124 size = 0UL; 125 base = new_base; 126 } 127 if (size == 0UL) { 128 /* If it is empty, simply get rid of it. 129 * This simplifies the logic of the other 130 * functions that process these arrays. 131 */ 132 memmove(®s[i], ®s[i + 1], 133 (ents - i - 1) * sizeof(regs[0])); 134 i--; 135 ents--; 136 continue; 137 } 138 regs[i].phys_addr = base; 139 regs[i].reg_size = size; 140 } 141 142 *num_ents = ents; 143 144 sort(regs, ents, sizeof(struct linux_prom64_registers), 145 cmp_p64, NULL); 146 } 147 148 unsigned long *sparc64_valid_addr_bitmap __read_mostly; 149 EXPORT_SYMBOL(sparc64_valid_addr_bitmap); 150 151 /* Kernel physical address base and size in bytes. */ 152 unsigned long kern_base __read_mostly; 153 unsigned long kern_size __read_mostly; 154 155 /* Initial ramdisk setup */ 156 extern unsigned long sparc_ramdisk_image64; 157 extern unsigned int sparc_ramdisk_image; 158 extern unsigned int sparc_ramdisk_size; 159 160 struct page *mem_map_zero __read_mostly; 161 EXPORT_SYMBOL(mem_map_zero); 162 163 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 164 165 unsigned long sparc64_kern_pri_context __read_mostly; 166 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 167 unsigned long sparc64_kern_sec_context __read_mostly; 168 169 int num_kernel_image_mappings; 170 171 #ifdef CONFIG_DEBUG_DCFLUSH 172 atomic_t dcpage_flushes = ATOMIC_INIT(0); 173 #ifdef CONFIG_SMP 174 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 175 #endif 176 #endif 177 178 inline void flush_dcache_page_impl(struct page *page) 179 { 180 BUG_ON(tlb_type == hypervisor); 181 #ifdef CONFIG_DEBUG_DCFLUSH 182 atomic_inc(&dcpage_flushes); 183 #endif 184 185 #ifdef DCACHE_ALIASING_POSSIBLE 186 __flush_dcache_page(page_address(page), 187 ((tlb_type == spitfire) && 188 page_mapping(page) != NULL)); 189 #else 190 if (page_mapping(page) != NULL && 191 tlb_type == spitfire) 192 __flush_icache_page(__pa(page_address(page))); 193 #endif 194 } 195 196 #define PG_dcache_dirty PG_arch_1 197 #define PG_dcache_cpu_shift 32UL 198 #define PG_dcache_cpu_mask \ 199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 200 201 #define dcache_dirty_cpu(page) \ 202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 203 204 static inline void set_dcache_dirty(struct page *page, int this_cpu) 205 { 206 unsigned long mask = this_cpu; 207 unsigned long non_cpu_bits; 208 209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 211 212 __asm__ __volatile__("1:\n\t" 213 "ldx [%2], %%g7\n\t" 214 "and %%g7, %1, %%g1\n\t" 215 "or %%g1, %0, %%g1\n\t" 216 "casx [%2], %%g7, %%g1\n\t" 217 "cmp %%g7, %%g1\n\t" 218 "bne,pn %%xcc, 1b\n\t" 219 " nop" 220 : /* no outputs */ 221 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 222 : "g1", "g7"); 223 } 224 225 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) 226 { 227 unsigned long mask = (1UL << PG_dcache_dirty); 228 229 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 230 "1:\n\t" 231 "ldx [%2], %%g7\n\t" 232 "srlx %%g7, %4, %%g1\n\t" 233 "and %%g1, %3, %%g1\n\t" 234 "cmp %%g1, %0\n\t" 235 "bne,pn %%icc, 2f\n\t" 236 " andn %%g7, %1, %%g1\n\t" 237 "casx [%2], %%g7, %%g1\n\t" 238 "cmp %%g7, %%g1\n\t" 239 "bne,pn %%xcc, 1b\n\t" 240 " nop\n" 241 "2:" 242 : /* no outputs */ 243 : "r" (cpu), "r" (mask), "r" (&page->flags), 244 "i" (PG_dcache_cpu_mask), 245 "i" (PG_dcache_cpu_shift) 246 : "g1", "g7"); 247 } 248 249 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 250 { 251 unsigned long tsb_addr = (unsigned long) ent; 252 253 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 254 tsb_addr = __pa(tsb_addr); 255 256 __tsb_insert(tsb_addr, tag, pte); 257 } 258 259 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 260 unsigned long _PAGE_SZBITS __read_mostly; 261 262 static void flush_dcache(unsigned long pfn) 263 { 264 struct page *page; 265 266 page = pfn_to_page(pfn); 267 if (page && page_mapping(page)) { 268 unsigned long pg_flags; 269 270 pg_flags = page->flags; 271 if (pg_flags & (1UL << PG_dcache_dirty)) { 272 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 273 PG_dcache_cpu_mask); 274 int this_cpu = get_cpu(); 275 276 /* This is just to optimize away some function calls 277 * in the SMP case. 278 */ 279 if (cpu == this_cpu) 280 flush_dcache_page_impl(page); 281 else 282 smp_flush_dcache_page_impl(page, cpu); 283 284 clear_dcache_dirty_cpu(page, cpu); 285 286 put_cpu(); 287 } 288 } 289 } 290 291 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 292 { 293 struct mm_struct *mm; 294 struct tsb *tsb; 295 unsigned long tag, flags; 296 unsigned long tsb_index, tsb_hash_shift; 297 298 if (tlb_type != hypervisor) { 299 unsigned long pfn = pte_pfn(pte); 300 301 if (pfn_valid(pfn)) 302 flush_dcache(pfn); 303 } 304 305 mm = vma->vm_mm; 306 307 tsb_index = MM_TSB_BASE; 308 tsb_hash_shift = PAGE_SHIFT; 309 310 spin_lock_irqsave(&mm->context.lock, flags); 311 312 #ifdef CONFIG_HUGETLB_PAGE 313 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) { 314 if ((tlb_type == hypervisor && 315 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) || 316 (tlb_type != hypervisor && 317 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) { 318 tsb_index = MM_TSB_HUGE; 319 tsb_hash_shift = HPAGE_SHIFT; 320 } 321 } 322 #endif 323 324 tsb = mm->context.tsb_block[tsb_index].tsb; 325 tsb += ((address >> tsb_hash_shift) & 326 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 327 tag = (address >> 22UL); 328 tsb_insert(tsb, tag, pte_val(pte)); 329 330 spin_unlock_irqrestore(&mm->context.lock, flags); 331 } 332 333 void flush_dcache_page(struct page *page) 334 { 335 struct address_space *mapping; 336 int this_cpu; 337 338 if (tlb_type == hypervisor) 339 return; 340 341 /* Do not bother with the expensive D-cache flush if it 342 * is merely the zero page. The 'bigcore' testcase in GDB 343 * causes this case to run millions of times. 344 */ 345 if (page == ZERO_PAGE(0)) 346 return; 347 348 this_cpu = get_cpu(); 349 350 mapping = page_mapping(page); 351 if (mapping && !mapping_mapped(mapping)) { 352 int dirty = test_bit(PG_dcache_dirty, &page->flags); 353 if (dirty) { 354 int dirty_cpu = dcache_dirty_cpu(page); 355 356 if (dirty_cpu == this_cpu) 357 goto out; 358 smp_flush_dcache_page_impl(page, dirty_cpu); 359 } 360 set_dcache_dirty(page, this_cpu); 361 } else { 362 /* We could delay the flush for the !page_mapping 363 * case too. But that case is for exec env/arg 364 * pages and those are %99 certainly going to get 365 * faulted into the tlb (and thus flushed) anyways. 366 */ 367 flush_dcache_page_impl(page); 368 } 369 370 out: 371 put_cpu(); 372 } 373 EXPORT_SYMBOL(flush_dcache_page); 374 375 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 376 { 377 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 378 if (tlb_type == spitfire) { 379 unsigned long kaddr; 380 381 /* This code only runs on Spitfire cpus so this is 382 * why we can assume _PAGE_PADDR_4U. 383 */ 384 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 385 unsigned long paddr, mask = _PAGE_PADDR_4U; 386 387 if (kaddr >= PAGE_OFFSET) 388 paddr = kaddr & mask; 389 else { 390 pgd_t *pgdp = pgd_offset_k(kaddr); 391 pud_t *pudp = pud_offset(pgdp, kaddr); 392 pmd_t *pmdp = pmd_offset(pudp, kaddr); 393 pte_t *ptep = pte_offset_kernel(pmdp, kaddr); 394 395 paddr = pte_val(*ptep) & mask; 396 } 397 __flush_icache_page(paddr); 398 } 399 } 400 } 401 EXPORT_SYMBOL(flush_icache_range); 402 403 void mmu_info(struct seq_file *m) 404 { 405 if (tlb_type == cheetah) 406 seq_printf(m, "MMU Type\t: Cheetah\n"); 407 else if (tlb_type == cheetah_plus) 408 seq_printf(m, "MMU Type\t: Cheetah+\n"); 409 else if (tlb_type == spitfire) 410 seq_printf(m, "MMU Type\t: Spitfire\n"); 411 else if (tlb_type == hypervisor) 412 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 413 else 414 seq_printf(m, "MMU Type\t: ???\n"); 415 416 #ifdef CONFIG_DEBUG_DCFLUSH 417 seq_printf(m, "DCPageFlushes\t: %d\n", 418 atomic_read(&dcpage_flushes)); 419 #ifdef CONFIG_SMP 420 seq_printf(m, "DCPageFlushesXC\t: %d\n", 421 atomic_read(&dcpage_flushes_xcall)); 422 #endif /* CONFIG_SMP */ 423 #endif /* CONFIG_DEBUG_DCFLUSH */ 424 } 425 426 struct linux_prom_translation prom_trans[512] __read_mostly; 427 unsigned int prom_trans_ents __read_mostly; 428 429 unsigned long kern_locked_tte_data; 430 431 /* The obp translations are saved based on 8k pagesize, since obp can 432 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 433 * HI_OBP_ADDRESS range are handled in ktlb.S. 434 */ 435 static inline int in_obp_range(unsigned long vaddr) 436 { 437 return (vaddr >= LOW_OBP_ADDRESS && 438 vaddr < HI_OBP_ADDRESS); 439 } 440 441 static int cmp_ptrans(const void *a, const void *b) 442 { 443 const struct linux_prom_translation *x = a, *y = b; 444 445 if (x->virt > y->virt) 446 return 1; 447 if (x->virt < y->virt) 448 return -1; 449 return 0; 450 } 451 452 /* Read OBP translations property into 'prom_trans[]'. */ 453 static void __init read_obp_translations(void) 454 { 455 int n, node, ents, first, last, i; 456 457 node = prom_finddevice("/virtual-memory"); 458 n = prom_getproplen(node, "translations"); 459 if (unlikely(n == 0 || n == -1)) { 460 prom_printf("prom_mappings: Couldn't get size.\n"); 461 prom_halt(); 462 } 463 if (unlikely(n > sizeof(prom_trans))) { 464 prom_printf("prom_mappings: Size %Zd is too big.\n", n); 465 prom_halt(); 466 } 467 468 if ((n = prom_getproperty(node, "translations", 469 (char *)&prom_trans[0], 470 sizeof(prom_trans))) == -1) { 471 prom_printf("prom_mappings: Couldn't get property.\n"); 472 prom_halt(); 473 } 474 475 n = n / sizeof(struct linux_prom_translation); 476 477 ents = n; 478 479 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 480 cmp_ptrans, NULL); 481 482 /* Now kick out all the non-OBP entries. */ 483 for (i = 0; i < ents; i++) { 484 if (in_obp_range(prom_trans[i].virt)) 485 break; 486 } 487 first = i; 488 for (; i < ents; i++) { 489 if (!in_obp_range(prom_trans[i].virt)) 490 break; 491 } 492 last = i; 493 494 for (i = 0; i < (last - first); i++) { 495 struct linux_prom_translation *src = &prom_trans[i + first]; 496 struct linux_prom_translation *dest = &prom_trans[i]; 497 498 *dest = *src; 499 } 500 for (; i < ents; i++) { 501 struct linux_prom_translation *dest = &prom_trans[i]; 502 dest->virt = dest->size = dest->data = 0x0UL; 503 } 504 505 prom_trans_ents = last - first; 506 507 if (tlb_type == spitfire) { 508 /* Clear diag TTE bits. */ 509 for (i = 0; i < prom_trans_ents; i++) 510 prom_trans[i].data &= ~0x0003fe0000000000UL; 511 } 512 } 513 514 static void __init hypervisor_tlb_lock(unsigned long vaddr, 515 unsigned long pte, 516 unsigned long mmu) 517 { 518 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 519 520 if (ret != 0) { 521 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: " 522 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 523 prom_halt(); 524 } 525 } 526 527 static unsigned long kern_large_tte(unsigned long paddr); 528 529 static void __init remap_kernel(void) 530 { 531 unsigned long phys_page, tte_vaddr, tte_data; 532 int i, tlb_ent = sparc64_highest_locked_tlbent(); 533 534 tte_vaddr = (unsigned long) KERNBASE; 535 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL; 536 tte_data = kern_large_tte(phys_page); 537 538 kern_locked_tte_data = tte_data; 539 540 /* Now lock us into the TLBs via Hypervisor or OBP. */ 541 if (tlb_type == hypervisor) { 542 for (i = 0; i < num_kernel_image_mappings; i++) { 543 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 544 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 545 tte_vaddr += 0x400000; 546 tte_data += 0x400000; 547 } 548 } else { 549 for (i = 0; i < num_kernel_image_mappings; i++) { 550 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 551 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 552 tte_vaddr += 0x400000; 553 tte_data += 0x400000; 554 } 555 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 556 } 557 if (tlb_type == cheetah_plus) { 558 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 559 CTX_CHEETAH_PLUS_NUC); 560 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 561 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 562 } 563 } 564 565 566 static void __init inherit_prom_mappings(void) 567 { 568 /* Now fixup OBP's idea about where we really are mapped. */ 569 printk("Remapping the kernel... "); 570 remap_kernel(); 571 printk("done.\n"); 572 } 573 574 void prom_world(int enter) 575 { 576 if (!enter) 577 set_fs((mm_segment_t) { get_thread_current_ds() }); 578 579 __asm__ __volatile__("flushw"); 580 } 581 582 void __flush_dcache_range(unsigned long start, unsigned long end) 583 { 584 unsigned long va; 585 586 if (tlb_type == spitfire) { 587 int n = 0; 588 589 for (va = start; va < end; va += 32) { 590 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 591 if (++n >= 512) 592 break; 593 } 594 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 595 start = __pa(start); 596 end = __pa(end); 597 for (va = start; va < end; va += 32) 598 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 599 "membar #Sync" 600 : /* no outputs */ 601 : "r" (va), 602 "i" (ASI_DCACHE_INVALIDATE)); 603 } 604 } 605 EXPORT_SYMBOL(__flush_dcache_range); 606 607 /* get_new_mmu_context() uses "cache + 1". */ 608 DEFINE_SPINLOCK(ctx_alloc_lock); 609 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; 610 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 611 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 612 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 613 614 /* Caller does TLB context flushing on local CPU if necessary. 615 * The caller also ensures that CTX_VALID(mm->context) is false. 616 * 617 * We must be careful about boundary cases so that we never 618 * let the user have CTX 0 (nucleus) or we ever use a CTX 619 * version of zero (and thus NO_CONTEXT would not be caught 620 * by version mis-match tests in mmu_context.h). 621 * 622 * Always invoked with interrupts disabled. 623 */ 624 void get_new_mmu_context(struct mm_struct *mm) 625 { 626 unsigned long ctx, new_ctx; 627 unsigned long orig_pgsz_bits; 628 unsigned long flags; 629 int new_version; 630 631 spin_lock_irqsave(&ctx_alloc_lock, flags); 632 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 633 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 634 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 635 new_version = 0; 636 if (new_ctx >= (1 << CTX_NR_BITS)) { 637 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 638 if (new_ctx >= ctx) { 639 int i; 640 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + 641 CTX_FIRST_VERSION; 642 if (new_ctx == 1) 643 new_ctx = CTX_FIRST_VERSION; 644 645 /* Don't call memset, for 16 entries that's just 646 * plain silly... 647 */ 648 mmu_context_bmap[0] = 3; 649 mmu_context_bmap[1] = 0; 650 mmu_context_bmap[2] = 0; 651 mmu_context_bmap[3] = 0; 652 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { 653 mmu_context_bmap[i + 0] = 0; 654 mmu_context_bmap[i + 1] = 0; 655 mmu_context_bmap[i + 2] = 0; 656 mmu_context_bmap[i + 3] = 0; 657 } 658 new_version = 1; 659 goto out; 660 } 661 } 662 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 663 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 664 out: 665 tlb_context_cache = new_ctx; 666 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 667 spin_unlock_irqrestore(&ctx_alloc_lock, flags); 668 669 if (unlikely(new_version)) 670 smp_new_mmu_context_version(); 671 } 672 673 static int numa_enabled = 1; 674 static int numa_debug; 675 676 static int __init early_numa(char *p) 677 { 678 if (!p) 679 return 0; 680 681 if (strstr(p, "off")) 682 numa_enabled = 0; 683 684 if (strstr(p, "debug")) 685 numa_debug = 1; 686 687 return 0; 688 } 689 early_param("numa", early_numa); 690 691 #define numadbg(f, a...) \ 692 do { if (numa_debug) \ 693 printk(KERN_INFO f, ## a); \ 694 } while (0) 695 696 static void __init find_ramdisk(unsigned long phys_base) 697 { 698 #ifdef CONFIG_BLK_DEV_INITRD 699 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 700 unsigned long ramdisk_image; 701 702 /* Older versions of the bootloader only supported a 703 * 32-bit physical address for the ramdisk image 704 * location, stored at sparc_ramdisk_image. Newer 705 * SILO versions set sparc_ramdisk_image to zero and 706 * provide a full 64-bit physical address at 707 * sparc_ramdisk_image64. 708 */ 709 ramdisk_image = sparc_ramdisk_image; 710 if (!ramdisk_image) 711 ramdisk_image = sparc_ramdisk_image64; 712 713 /* Another bootloader quirk. The bootloader normalizes 714 * the physical address to KERNBASE, so we have to 715 * factor that back out and add in the lowest valid 716 * physical page address to get the true physical address. 717 */ 718 ramdisk_image -= KERNBASE; 719 ramdisk_image += phys_base; 720 721 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 722 ramdisk_image, sparc_ramdisk_size); 723 724 initrd_start = ramdisk_image; 725 initrd_end = ramdisk_image + sparc_ramdisk_size; 726 727 lmb_reserve(initrd_start, sparc_ramdisk_size); 728 729 initrd_start += PAGE_OFFSET; 730 initrd_end += PAGE_OFFSET; 731 } 732 #endif 733 } 734 735 struct node_mem_mask { 736 unsigned long mask; 737 unsigned long val; 738 unsigned long bootmem_paddr; 739 }; 740 static struct node_mem_mask node_masks[MAX_NUMNODES]; 741 static int num_node_masks; 742 743 int numa_cpu_lookup_table[NR_CPUS]; 744 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 745 746 #ifdef CONFIG_NEED_MULTIPLE_NODES 747 748 struct mdesc_mblock { 749 u64 base; 750 u64 size; 751 u64 offset; /* RA-to-PA */ 752 }; 753 static struct mdesc_mblock *mblocks; 754 static int num_mblocks; 755 756 static unsigned long ra_to_pa(unsigned long addr) 757 { 758 int i; 759 760 for (i = 0; i < num_mblocks; i++) { 761 struct mdesc_mblock *m = &mblocks[i]; 762 763 if (addr >= m->base && 764 addr < (m->base + m->size)) { 765 addr += m->offset; 766 break; 767 } 768 } 769 return addr; 770 } 771 772 static int find_node(unsigned long addr) 773 { 774 int i; 775 776 addr = ra_to_pa(addr); 777 for (i = 0; i < num_node_masks; i++) { 778 struct node_mem_mask *p = &node_masks[i]; 779 780 if ((addr & p->mask) == p->val) 781 return i; 782 } 783 return -1; 784 } 785 786 static unsigned long long nid_range(unsigned long long start, 787 unsigned long long end, int *nid) 788 { 789 *nid = find_node(start); 790 start += PAGE_SIZE; 791 while (start < end) { 792 int n = find_node(start); 793 794 if (n != *nid) 795 break; 796 start += PAGE_SIZE; 797 } 798 799 if (start > end) 800 start = end; 801 802 return start; 803 } 804 #else 805 static unsigned long long nid_range(unsigned long long start, 806 unsigned long long end, int *nid) 807 { 808 *nid = 0; 809 return end; 810 } 811 #endif 812 813 /* This must be invoked after performing all of the necessary 814 * add_active_range() calls for 'nid'. We need to be able to get 815 * correct data from get_pfn_range_for_nid(). 816 */ 817 static void __init allocate_node_data(int nid) 818 { 819 unsigned long paddr, num_pages, start_pfn, end_pfn; 820 struct pglist_data *p; 821 822 #ifdef CONFIG_NEED_MULTIPLE_NODES 823 paddr = lmb_alloc_nid(sizeof(struct pglist_data), 824 SMP_CACHE_BYTES, nid, nid_range); 825 if (!paddr) { 826 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); 827 prom_halt(); 828 } 829 NODE_DATA(nid) = __va(paddr); 830 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); 831 832 NODE_DATA(nid)->bdata = &bootmem_node_data[nid]; 833 #endif 834 835 p = NODE_DATA(nid); 836 837 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 838 p->node_start_pfn = start_pfn; 839 p->node_spanned_pages = end_pfn - start_pfn; 840 841 if (p->node_spanned_pages) { 842 num_pages = bootmem_bootmap_pages(p->node_spanned_pages); 843 844 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid, 845 nid_range); 846 if (!paddr) { 847 prom_printf("Cannot allocate bootmap for nid[%d]\n", 848 nid); 849 prom_halt(); 850 } 851 node_masks[nid].bootmem_paddr = paddr; 852 } 853 } 854 855 static void init_node_masks_nonnuma(void) 856 { 857 int i; 858 859 numadbg("Initializing tables for non-numa.\n"); 860 861 node_masks[0].mask = node_masks[0].val = 0; 862 num_node_masks = 1; 863 864 for (i = 0; i < NR_CPUS; i++) 865 numa_cpu_lookup_table[i] = 0; 866 867 numa_cpumask_lookup_table[0] = CPU_MASK_ALL; 868 } 869 870 #ifdef CONFIG_NEED_MULTIPLE_NODES 871 struct pglist_data *node_data[MAX_NUMNODES]; 872 873 EXPORT_SYMBOL(numa_cpu_lookup_table); 874 EXPORT_SYMBOL(numa_cpumask_lookup_table); 875 EXPORT_SYMBOL(node_data); 876 877 struct mdesc_mlgroup { 878 u64 node; 879 u64 latency; 880 u64 match; 881 u64 mask; 882 }; 883 static struct mdesc_mlgroup *mlgroups; 884 static int num_mlgroups; 885 886 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 887 u32 cfg_handle) 888 { 889 u64 arc; 890 891 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 892 u64 target = mdesc_arc_target(md, arc); 893 const u64 *val; 894 895 val = mdesc_get_property(md, target, 896 "cfg-handle", NULL); 897 if (val && *val == cfg_handle) 898 return 0; 899 } 900 return -ENODEV; 901 } 902 903 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 904 u32 cfg_handle) 905 { 906 u64 arc, candidate, best_latency = ~(u64)0; 907 908 candidate = MDESC_NODE_NULL; 909 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 910 u64 target = mdesc_arc_target(md, arc); 911 const char *name = mdesc_node_name(md, target); 912 const u64 *val; 913 914 if (strcmp(name, "pio-latency-group")) 915 continue; 916 917 val = mdesc_get_property(md, target, "latency", NULL); 918 if (!val) 919 continue; 920 921 if (*val < best_latency) { 922 candidate = target; 923 best_latency = *val; 924 } 925 } 926 927 if (candidate == MDESC_NODE_NULL) 928 return -ENODEV; 929 930 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 931 } 932 933 int of_node_to_nid(struct device_node *dp) 934 { 935 const struct linux_prom64_registers *regs; 936 struct mdesc_handle *md; 937 u32 cfg_handle; 938 int count, nid; 939 u64 grp; 940 941 /* This is the right thing to do on currently supported 942 * SUN4U NUMA platforms as well, as the PCI controller does 943 * not sit behind any particular memory controller. 944 */ 945 if (!mlgroups) 946 return -1; 947 948 regs = of_get_property(dp, "reg", NULL); 949 if (!regs) 950 return -1; 951 952 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 953 954 md = mdesc_grab(); 955 956 count = 0; 957 nid = -1; 958 mdesc_for_each_node_by_name(md, grp, "group") { 959 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 960 nid = count; 961 break; 962 } 963 count++; 964 } 965 966 mdesc_release(md); 967 968 return nid; 969 } 970 971 static void __init add_node_ranges(void) 972 { 973 int i; 974 975 for (i = 0; i < lmb.memory.cnt; i++) { 976 unsigned long size = lmb_size_bytes(&lmb.memory, i); 977 unsigned long start, end; 978 979 start = lmb.memory.region[i].base; 980 end = start + size; 981 while (start < end) { 982 unsigned long this_end; 983 int nid; 984 985 this_end = nid_range(start, end, &nid); 986 987 numadbg("Adding active range nid[%d] " 988 "start[%lx] end[%lx]\n", 989 nid, start, this_end); 990 991 add_active_range(nid, 992 start >> PAGE_SHIFT, 993 this_end >> PAGE_SHIFT); 994 995 start = this_end; 996 } 997 } 998 } 999 1000 static int __init grab_mlgroups(struct mdesc_handle *md) 1001 { 1002 unsigned long paddr; 1003 int count = 0; 1004 u64 node; 1005 1006 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1007 count++; 1008 if (!count) 1009 return -ENOENT; 1010 1011 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup), 1012 SMP_CACHE_BYTES); 1013 if (!paddr) 1014 return -ENOMEM; 1015 1016 mlgroups = __va(paddr); 1017 num_mlgroups = count; 1018 1019 count = 0; 1020 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1021 struct mdesc_mlgroup *m = &mlgroups[count++]; 1022 const u64 *val; 1023 1024 m->node = node; 1025 1026 val = mdesc_get_property(md, node, "latency", NULL); 1027 m->latency = *val; 1028 val = mdesc_get_property(md, node, "address-match", NULL); 1029 m->match = *val; 1030 val = mdesc_get_property(md, node, "address-mask", NULL); 1031 m->mask = *val; 1032 1033 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1034 "match[%llx] mask[%llx]\n", 1035 count - 1, m->node, m->latency, m->match, m->mask); 1036 } 1037 1038 return 0; 1039 } 1040 1041 static int __init grab_mblocks(struct mdesc_handle *md) 1042 { 1043 unsigned long paddr; 1044 int count = 0; 1045 u64 node; 1046 1047 mdesc_for_each_node_by_name(md, node, "mblock") 1048 count++; 1049 if (!count) 1050 return -ENOENT; 1051 1052 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock), 1053 SMP_CACHE_BYTES); 1054 if (!paddr) 1055 return -ENOMEM; 1056 1057 mblocks = __va(paddr); 1058 num_mblocks = count; 1059 1060 count = 0; 1061 mdesc_for_each_node_by_name(md, node, "mblock") { 1062 struct mdesc_mblock *m = &mblocks[count++]; 1063 const u64 *val; 1064 1065 val = mdesc_get_property(md, node, "base", NULL); 1066 m->base = *val; 1067 val = mdesc_get_property(md, node, "size", NULL); 1068 m->size = *val; 1069 val = mdesc_get_property(md, node, 1070 "address-congruence-offset", NULL); 1071 m->offset = *val; 1072 1073 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1074 count - 1, m->base, m->size, m->offset); 1075 } 1076 1077 return 0; 1078 } 1079 1080 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1081 u64 grp, cpumask_t *mask) 1082 { 1083 u64 arc; 1084 1085 cpus_clear(*mask); 1086 1087 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1088 u64 target = mdesc_arc_target(md, arc); 1089 const char *name = mdesc_node_name(md, target); 1090 const u64 *id; 1091 1092 if (strcmp(name, "cpu")) 1093 continue; 1094 id = mdesc_get_property(md, target, "id", NULL); 1095 if (*id < nr_cpu_ids) 1096 cpu_set(*id, *mask); 1097 } 1098 } 1099 1100 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1101 { 1102 int i; 1103 1104 for (i = 0; i < num_mlgroups; i++) { 1105 struct mdesc_mlgroup *m = &mlgroups[i]; 1106 if (m->node == node) 1107 return m; 1108 } 1109 return NULL; 1110 } 1111 1112 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1113 int index) 1114 { 1115 struct mdesc_mlgroup *candidate = NULL; 1116 u64 arc, best_latency = ~(u64)0; 1117 struct node_mem_mask *n; 1118 1119 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1120 u64 target = mdesc_arc_target(md, arc); 1121 struct mdesc_mlgroup *m = find_mlgroup(target); 1122 if (!m) 1123 continue; 1124 if (m->latency < best_latency) { 1125 candidate = m; 1126 best_latency = m->latency; 1127 } 1128 } 1129 if (!candidate) 1130 return -ENOENT; 1131 1132 if (num_node_masks != index) { 1133 printk(KERN_ERR "Inconsistent NUMA state, " 1134 "index[%d] != num_node_masks[%d]\n", 1135 index, num_node_masks); 1136 return -EINVAL; 1137 } 1138 1139 n = &node_masks[num_node_masks++]; 1140 1141 n->mask = candidate->mask; 1142 n->val = candidate->match; 1143 1144 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n", 1145 index, n->mask, n->val, candidate->latency); 1146 1147 return 0; 1148 } 1149 1150 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1151 int index) 1152 { 1153 cpumask_t mask; 1154 int cpu; 1155 1156 numa_parse_mdesc_group_cpus(md, grp, &mask); 1157 1158 for_each_cpu_mask(cpu, mask) 1159 numa_cpu_lookup_table[cpu] = index; 1160 numa_cpumask_lookup_table[index] = mask; 1161 1162 if (numa_debug) { 1163 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1164 for_each_cpu_mask(cpu, mask) 1165 printk("%d ", cpu); 1166 printk("]\n"); 1167 } 1168 1169 return numa_attach_mlgroup(md, grp, index); 1170 } 1171 1172 static int __init numa_parse_mdesc(void) 1173 { 1174 struct mdesc_handle *md = mdesc_grab(); 1175 int i, err, count; 1176 u64 node; 1177 1178 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1179 if (node == MDESC_NODE_NULL) { 1180 mdesc_release(md); 1181 return -ENOENT; 1182 } 1183 1184 err = grab_mblocks(md); 1185 if (err < 0) 1186 goto out; 1187 1188 err = grab_mlgroups(md); 1189 if (err < 0) 1190 goto out; 1191 1192 count = 0; 1193 mdesc_for_each_node_by_name(md, node, "group") { 1194 err = numa_parse_mdesc_group(md, node, count); 1195 if (err < 0) 1196 break; 1197 count++; 1198 } 1199 1200 add_node_ranges(); 1201 1202 for (i = 0; i < num_node_masks; i++) { 1203 allocate_node_data(i); 1204 node_set_online(i); 1205 } 1206 1207 err = 0; 1208 out: 1209 mdesc_release(md); 1210 return err; 1211 } 1212 1213 static int __init numa_parse_jbus(void) 1214 { 1215 unsigned long cpu, index; 1216 1217 /* NUMA node id is encoded in bits 36 and higher, and there is 1218 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1219 */ 1220 index = 0; 1221 for_each_present_cpu(cpu) { 1222 numa_cpu_lookup_table[cpu] = index; 1223 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu); 1224 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1225 node_masks[index].val = cpu << 36UL; 1226 1227 index++; 1228 } 1229 num_node_masks = index; 1230 1231 add_node_ranges(); 1232 1233 for (index = 0; index < num_node_masks; index++) { 1234 allocate_node_data(index); 1235 node_set_online(index); 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int __init numa_parse_sun4u(void) 1242 { 1243 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1244 unsigned long ver; 1245 1246 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1247 if ((ver >> 32UL) == __JALAPENO_ID || 1248 (ver >> 32UL) == __SERRANO_ID) 1249 return numa_parse_jbus(); 1250 } 1251 return -1; 1252 } 1253 1254 static int __init bootmem_init_numa(void) 1255 { 1256 int err = -1; 1257 1258 numadbg("bootmem_init_numa()\n"); 1259 1260 if (numa_enabled) { 1261 if (tlb_type == hypervisor) 1262 err = numa_parse_mdesc(); 1263 else 1264 err = numa_parse_sun4u(); 1265 } 1266 return err; 1267 } 1268 1269 #else 1270 1271 static int bootmem_init_numa(void) 1272 { 1273 return -1; 1274 } 1275 1276 #endif 1277 1278 static void __init bootmem_init_nonnuma(void) 1279 { 1280 unsigned long top_of_ram = lmb_end_of_DRAM(); 1281 unsigned long total_ram = lmb_phys_mem_size(); 1282 unsigned int i; 1283 1284 numadbg("bootmem_init_nonnuma()\n"); 1285 1286 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1287 top_of_ram, total_ram); 1288 printk(KERN_INFO "Memory hole size: %ldMB\n", 1289 (top_of_ram - total_ram) >> 20); 1290 1291 init_node_masks_nonnuma(); 1292 1293 for (i = 0; i < lmb.memory.cnt; i++) { 1294 unsigned long size = lmb_size_bytes(&lmb.memory, i); 1295 unsigned long start_pfn, end_pfn; 1296 1297 if (!size) 1298 continue; 1299 1300 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT; 1301 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i); 1302 add_active_range(0, start_pfn, end_pfn); 1303 } 1304 1305 allocate_node_data(0); 1306 1307 node_set_online(0); 1308 } 1309 1310 static void __init reserve_range_in_node(int nid, unsigned long start, 1311 unsigned long end) 1312 { 1313 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n", 1314 nid, start, end); 1315 while (start < end) { 1316 unsigned long this_end; 1317 int n; 1318 1319 this_end = nid_range(start, end, &n); 1320 if (n == nid) { 1321 numadbg(" MATCH reserving range [%lx:%lx]\n", 1322 start, this_end); 1323 reserve_bootmem_node(NODE_DATA(nid), start, 1324 (this_end - start), BOOTMEM_DEFAULT); 1325 } else 1326 numadbg(" NO MATCH, advancing start to %lx\n", 1327 this_end); 1328 1329 start = this_end; 1330 } 1331 } 1332 1333 static void __init trim_reserved_in_node(int nid) 1334 { 1335 int i; 1336 1337 numadbg(" trim_reserved_in_node(%d)\n", nid); 1338 1339 for (i = 0; i < lmb.reserved.cnt; i++) { 1340 unsigned long start = lmb.reserved.region[i].base; 1341 unsigned long size = lmb_size_bytes(&lmb.reserved, i); 1342 unsigned long end = start + size; 1343 1344 reserve_range_in_node(nid, start, end); 1345 } 1346 } 1347 1348 static void __init bootmem_init_one_node(int nid) 1349 { 1350 struct pglist_data *p; 1351 1352 numadbg("bootmem_init_one_node(%d)\n", nid); 1353 1354 p = NODE_DATA(nid); 1355 1356 if (p->node_spanned_pages) { 1357 unsigned long paddr = node_masks[nid].bootmem_paddr; 1358 unsigned long end_pfn; 1359 1360 end_pfn = p->node_start_pfn + p->node_spanned_pages; 1361 1362 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n", 1363 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn); 1364 1365 init_bootmem_node(p, paddr >> PAGE_SHIFT, 1366 p->node_start_pfn, end_pfn); 1367 1368 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n", 1369 nid, end_pfn); 1370 free_bootmem_with_active_regions(nid, end_pfn); 1371 1372 trim_reserved_in_node(nid); 1373 1374 numadbg(" sparse_memory_present_with_active_regions(%d)\n", 1375 nid); 1376 sparse_memory_present_with_active_regions(nid); 1377 } 1378 } 1379 1380 static unsigned long __init bootmem_init(unsigned long phys_base) 1381 { 1382 unsigned long end_pfn; 1383 int nid; 1384 1385 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT; 1386 max_pfn = max_low_pfn = end_pfn; 1387 min_low_pfn = (phys_base >> PAGE_SHIFT); 1388 1389 if (bootmem_init_numa() < 0) 1390 bootmem_init_nonnuma(); 1391 1392 /* XXX cpu notifier XXX */ 1393 1394 for_each_online_node(nid) 1395 bootmem_init_one_node(nid); 1396 1397 sparse_init(); 1398 1399 return end_pfn; 1400 } 1401 1402 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1403 static int pall_ents __initdata; 1404 1405 #ifdef CONFIG_DEBUG_PAGEALLOC 1406 static unsigned long __ref kernel_map_range(unsigned long pstart, 1407 unsigned long pend, pgprot_t prot) 1408 { 1409 unsigned long vstart = PAGE_OFFSET + pstart; 1410 unsigned long vend = PAGE_OFFSET + pend; 1411 unsigned long alloc_bytes = 0UL; 1412 1413 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1414 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1415 vstart, vend); 1416 prom_halt(); 1417 } 1418 1419 while (vstart < vend) { 1420 unsigned long this_end, paddr = __pa(vstart); 1421 pgd_t *pgd = pgd_offset_k(vstart); 1422 pud_t *pud; 1423 pmd_t *pmd; 1424 pte_t *pte; 1425 1426 pud = pud_offset(pgd, vstart); 1427 if (pud_none(*pud)) { 1428 pmd_t *new; 1429 1430 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1431 alloc_bytes += PAGE_SIZE; 1432 pud_populate(&init_mm, pud, new); 1433 } 1434 1435 pmd = pmd_offset(pud, vstart); 1436 if (!pmd_present(*pmd)) { 1437 pte_t *new; 1438 1439 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1440 alloc_bytes += PAGE_SIZE; 1441 pmd_populate_kernel(&init_mm, pmd, new); 1442 } 1443 1444 pte = pte_offset_kernel(pmd, vstart); 1445 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1446 if (this_end > vend) 1447 this_end = vend; 1448 1449 while (vstart < this_end) { 1450 pte_val(*pte) = (paddr | pgprot_val(prot)); 1451 1452 vstart += PAGE_SIZE; 1453 paddr += PAGE_SIZE; 1454 pte++; 1455 } 1456 } 1457 1458 return alloc_bytes; 1459 } 1460 1461 extern unsigned int kvmap_linear_patch[1]; 1462 #endif /* CONFIG_DEBUG_PAGEALLOC */ 1463 1464 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end) 1465 { 1466 const unsigned long shift_256MB = 28; 1467 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL); 1468 const unsigned long size_256MB = (1UL << shift_256MB); 1469 1470 while (start < end) { 1471 long remains; 1472 1473 remains = end - start; 1474 if (remains < size_256MB) 1475 break; 1476 1477 if (start & mask_256MB) { 1478 start = (start + size_256MB) & ~mask_256MB; 1479 continue; 1480 } 1481 1482 while (remains >= size_256MB) { 1483 unsigned long index = start >> shift_256MB; 1484 1485 __set_bit(index, kpte_linear_bitmap); 1486 1487 start += size_256MB; 1488 remains -= size_256MB; 1489 } 1490 } 1491 } 1492 1493 static void __init init_kpte_bitmap(void) 1494 { 1495 unsigned long i; 1496 1497 for (i = 0; i < pall_ents; i++) { 1498 unsigned long phys_start, phys_end; 1499 1500 phys_start = pall[i].phys_addr; 1501 phys_end = phys_start + pall[i].reg_size; 1502 1503 mark_kpte_bitmap(phys_start, phys_end); 1504 } 1505 } 1506 1507 static void __init kernel_physical_mapping_init(void) 1508 { 1509 #ifdef CONFIG_DEBUG_PAGEALLOC 1510 unsigned long i, mem_alloced = 0UL; 1511 1512 for (i = 0; i < pall_ents; i++) { 1513 unsigned long phys_start, phys_end; 1514 1515 phys_start = pall[i].phys_addr; 1516 phys_end = phys_start + pall[i].reg_size; 1517 1518 mem_alloced += kernel_map_range(phys_start, phys_end, 1519 PAGE_KERNEL); 1520 } 1521 1522 printk("Allocated %ld bytes for kernel page tables.\n", 1523 mem_alloced); 1524 1525 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1526 flushi(&kvmap_linear_patch[0]); 1527 1528 __flush_tlb_all(); 1529 #endif 1530 } 1531 1532 #ifdef CONFIG_DEBUG_PAGEALLOC 1533 void kernel_map_pages(struct page *page, int numpages, int enable) 1534 { 1535 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1536 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1537 1538 kernel_map_range(phys_start, phys_end, 1539 (enable ? PAGE_KERNEL : __pgprot(0))); 1540 1541 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1542 PAGE_OFFSET + phys_end); 1543 1544 /* we should perform an IPI and flush all tlbs, 1545 * but that can deadlock->flush only current cpu. 1546 */ 1547 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1548 PAGE_OFFSET + phys_end); 1549 } 1550 #endif 1551 1552 unsigned long __init find_ecache_flush_span(unsigned long size) 1553 { 1554 int i; 1555 1556 for (i = 0; i < pavail_ents; i++) { 1557 if (pavail[i].reg_size >= size) 1558 return pavail[i].phys_addr; 1559 } 1560 1561 return ~0UL; 1562 } 1563 1564 static void __init tsb_phys_patch(void) 1565 { 1566 struct tsb_ldquad_phys_patch_entry *pquad; 1567 struct tsb_phys_patch_entry *p; 1568 1569 pquad = &__tsb_ldquad_phys_patch; 1570 while (pquad < &__tsb_ldquad_phys_patch_end) { 1571 unsigned long addr = pquad->addr; 1572 1573 if (tlb_type == hypervisor) 1574 *(unsigned int *) addr = pquad->sun4v_insn; 1575 else 1576 *(unsigned int *) addr = pquad->sun4u_insn; 1577 wmb(); 1578 __asm__ __volatile__("flush %0" 1579 : /* no outputs */ 1580 : "r" (addr)); 1581 1582 pquad++; 1583 } 1584 1585 p = &__tsb_phys_patch; 1586 while (p < &__tsb_phys_patch_end) { 1587 unsigned long addr = p->addr; 1588 1589 *(unsigned int *) addr = p->insn; 1590 wmb(); 1591 __asm__ __volatile__("flush %0" 1592 : /* no outputs */ 1593 : "r" (addr)); 1594 1595 p++; 1596 } 1597 } 1598 1599 /* Don't mark as init, we give this to the Hypervisor. */ 1600 #ifndef CONFIG_DEBUG_PAGEALLOC 1601 #define NUM_KTSB_DESCR 2 1602 #else 1603 #define NUM_KTSB_DESCR 1 1604 #endif 1605 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 1606 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 1607 1608 static void __init sun4v_ktsb_init(void) 1609 { 1610 unsigned long ktsb_pa; 1611 1612 /* First KTSB for PAGE_SIZE mappings. */ 1613 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 1614 1615 switch (PAGE_SIZE) { 1616 case 8 * 1024: 1617 default: 1618 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 1619 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 1620 break; 1621 1622 case 64 * 1024: 1623 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 1624 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 1625 break; 1626 1627 case 512 * 1024: 1628 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 1629 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 1630 break; 1631 1632 case 4 * 1024 * 1024: 1633 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 1634 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 1635 break; 1636 }; 1637 1638 ktsb_descr[0].assoc = 1; 1639 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 1640 ktsb_descr[0].ctx_idx = 0; 1641 ktsb_descr[0].tsb_base = ktsb_pa; 1642 ktsb_descr[0].resv = 0; 1643 1644 #ifndef CONFIG_DEBUG_PAGEALLOC 1645 /* Second KTSB for 4MB/256MB mappings. */ 1646 ktsb_pa = (kern_base + 1647 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 1648 1649 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 1650 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB | 1651 HV_PGSZ_MASK_256MB); 1652 ktsb_descr[1].assoc = 1; 1653 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 1654 ktsb_descr[1].ctx_idx = 0; 1655 ktsb_descr[1].tsb_base = ktsb_pa; 1656 ktsb_descr[1].resv = 0; 1657 #endif 1658 } 1659 1660 void __cpuinit sun4v_ktsb_register(void) 1661 { 1662 unsigned long pa, ret; 1663 1664 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 1665 1666 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 1667 if (ret != 0) { 1668 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 1669 "errors with %lx\n", pa, ret); 1670 prom_halt(); 1671 } 1672 } 1673 1674 /* paging_init() sets up the page tables */ 1675 1676 static unsigned long last_valid_pfn; 1677 pgd_t swapper_pg_dir[2048]; 1678 1679 static void sun4u_pgprot_init(void); 1680 static void sun4v_pgprot_init(void); 1681 1682 /* Dummy function */ 1683 void __init setup_per_cpu_areas(void) 1684 { 1685 } 1686 1687 void __init paging_init(void) 1688 { 1689 unsigned long end_pfn, shift, phys_base; 1690 unsigned long real_end, i; 1691 1692 /* These build time checkes make sure that the dcache_dirty_cpu() 1693 * page->flags usage will work. 1694 * 1695 * When a page gets marked as dcache-dirty, we store the 1696 * cpu number starting at bit 32 in the page->flags. Also, 1697 * functions like clear_dcache_dirty_cpu use the cpu mask 1698 * in 13-bit signed-immediate instruction fields. 1699 */ 1700 1701 /* 1702 * Page flags must not reach into upper 32 bits that are used 1703 * for the cpu number 1704 */ 1705 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 1706 1707 /* 1708 * The bit fields placed in the high range must not reach below 1709 * the 32 bit boundary. Otherwise we cannot place the cpu field 1710 * at the 32 bit boundary. 1711 */ 1712 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 1713 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 1714 1715 BUILD_BUG_ON(NR_CPUS > 4096); 1716 1717 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL; 1718 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 1719 1720 /* Invalidate both kernel TSBs. */ 1721 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 1722 #ifndef CONFIG_DEBUG_PAGEALLOC 1723 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 1724 #endif 1725 1726 if (tlb_type == hypervisor) 1727 sun4v_pgprot_init(); 1728 else 1729 sun4u_pgprot_init(); 1730 1731 if (tlb_type == cheetah_plus || 1732 tlb_type == hypervisor) 1733 tsb_phys_patch(); 1734 1735 if (tlb_type == hypervisor) { 1736 sun4v_patch_tlb_handlers(); 1737 sun4v_ktsb_init(); 1738 } 1739 1740 lmb_init(); 1741 1742 /* Find available physical memory... 1743 * 1744 * Read it twice in order to work around a bug in openfirmware. 1745 * The call to grab this table itself can cause openfirmware to 1746 * allocate memory, which in turn can take away some space from 1747 * the list of available memory. Reading it twice makes sure 1748 * we really do get the final value. 1749 */ 1750 read_obp_translations(); 1751 read_obp_memory("reg", &pall[0], &pall_ents); 1752 read_obp_memory("available", &pavail[0], &pavail_ents); 1753 read_obp_memory("available", &pavail[0], &pavail_ents); 1754 1755 phys_base = 0xffffffffffffffffUL; 1756 for (i = 0; i < pavail_ents; i++) { 1757 phys_base = min(phys_base, pavail[i].phys_addr); 1758 lmb_add(pavail[i].phys_addr, pavail[i].reg_size); 1759 } 1760 1761 lmb_reserve(kern_base, kern_size); 1762 1763 find_ramdisk(phys_base); 1764 1765 lmb_enforce_memory_limit(cmdline_memory_size); 1766 1767 lmb_analyze(); 1768 lmb_dump_all(); 1769 1770 set_bit(0, mmu_context_bmap); 1771 1772 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 1773 1774 real_end = (unsigned long)_end; 1775 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22); 1776 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 1777 num_kernel_image_mappings); 1778 1779 /* Set kernel pgd to upper alias so physical page computations 1780 * work. 1781 */ 1782 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 1783 1784 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir)); 1785 1786 /* Now can init the kernel/bad page tables. */ 1787 pud_set(pud_offset(&swapper_pg_dir[0], 0), 1788 swapper_low_pmd_dir + (shift / sizeof(pgd_t))); 1789 1790 inherit_prom_mappings(); 1791 1792 init_kpte_bitmap(); 1793 1794 /* Ok, we can use our TLB miss and window trap handlers safely. */ 1795 setup_tba(); 1796 1797 __flush_tlb_all(); 1798 1799 if (tlb_type == hypervisor) 1800 sun4v_ktsb_register(); 1801 1802 /* We must setup the per-cpu areas before we pull in the 1803 * PROM and the MDESC. The code there fills in cpu and 1804 * other information into per-cpu data structures. 1805 */ 1806 real_setup_per_cpu_areas(); 1807 1808 prom_build_devicetree(); 1809 1810 if (tlb_type == hypervisor) 1811 sun4v_mdesc_init(); 1812 1813 /* Once the OF device tree and MDESC have been setup, we know 1814 * the list of possible cpus. Therefore we can allocate the 1815 * IRQ stacks. 1816 */ 1817 for_each_possible_cpu(i) { 1818 /* XXX Use node local allocations... XXX */ 1819 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); 1820 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); 1821 } 1822 1823 /* Setup bootmem... */ 1824 last_valid_pfn = end_pfn = bootmem_init(phys_base); 1825 1826 #ifndef CONFIG_NEED_MULTIPLE_NODES 1827 max_mapnr = last_valid_pfn; 1828 #endif 1829 kernel_physical_mapping_init(); 1830 1831 { 1832 unsigned long max_zone_pfns[MAX_NR_ZONES]; 1833 1834 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 1835 1836 max_zone_pfns[ZONE_NORMAL] = end_pfn; 1837 1838 free_area_init_nodes(max_zone_pfns); 1839 } 1840 1841 printk("Booting Linux...\n"); 1842 } 1843 1844 int __devinit page_in_phys_avail(unsigned long paddr) 1845 { 1846 int i; 1847 1848 paddr &= PAGE_MASK; 1849 1850 for (i = 0; i < pavail_ents; i++) { 1851 unsigned long start, end; 1852 1853 start = pavail[i].phys_addr; 1854 end = start + pavail[i].reg_size; 1855 1856 if (paddr >= start && paddr < end) 1857 return 1; 1858 } 1859 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 1860 return 1; 1861 #ifdef CONFIG_BLK_DEV_INITRD 1862 if (paddr >= __pa(initrd_start) && 1863 paddr < __pa(PAGE_ALIGN(initrd_end))) 1864 return 1; 1865 #endif 1866 1867 return 0; 1868 } 1869 1870 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata; 1871 static int pavail_rescan_ents __initdata; 1872 1873 /* Certain OBP calls, such as fetching "available" properties, can 1874 * claim physical memory. So, along with initializing the valid 1875 * address bitmap, what we do here is refetch the physical available 1876 * memory list again, and make sure it provides at least as much 1877 * memory as 'pavail' does. 1878 */ 1879 static void __init setup_valid_addr_bitmap_from_pavail(void) 1880 { 1881 int i; 1882 1883 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents); 1884 1885 for (i = 0; i < pavail_ents; i++) { 1886 unsigned long old_start, old_end; 1887 1888 old_start = pavail[i].phys_addr; 1889 old_end = old_start + pavail[i].reg_size; 1890 while (old_start < old_end) { 1891 int n; 1892 1893 for (n = 0; n < pavail_rescan_ents; n++) { 1894 unsigned long new_start, new_end; 1895 1896 new_start = pavail_rescan[n].phys_addr; 1897 new_end = new_start + 1898 pavail_rescan[n].reg_size; 1899 1900 if (new_start <= old_start && 1901 new_end >= (old_start + PAGE_SIZE)) { 1902 set_bit(old_start >> 22, 1903 sparc64_valid_addr_bitmap); 1904 goto do_next_page; 1905 } 1906 } 1907 1908 prom_printf("mem_init: Lost memory in pavail\n"); 1909 prom_printf("mem_init: OLD start[%lx] size[%lx]\n", 1910 pavail[i].phys_addr, 1911 pavail[i].reg_size); 1912 prom_printf("mem_init: NEW start[%lx] size[%lx]\n", 1913 pavail_rescan[i].phys_addr, 1914 pavail_rescan[i].reg_size); 1915 prom_printf("mem_init: Cannot continue, aborting.\n"); 1916 prom_halt(); 1917 1918 do_next_page: 1919 old_start += PAGE_SIZE; 1920 } 1921 } 1922 } 1923 1924 void __init mem_init(void) 1925 { 1926 unsigned long codepages, datapages, initpages; 1927 unsigned long addr, last; 1928 int i; 1929 1930 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6); 1931 i += 1; 1932 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3); 1933 if (sparc64_valid_addr_bitmap == NULL) { 1934 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n"); 1935 prom_halt(); 1936 } 1937 memset(sparc64_valid_addr_bitmap, 0, i << 3); 1938 1939 addr = PAGE_OFFSET + kern_base; 1940 last = PAGE_ALIGN(kern_size) + addr; 1941 while (addr < last) { 1942 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap); 1943 addr += PAGE_SIZE; 1944 } 1945 1946 setup_valid_addr_bitmap_from_pavail(); 1947 1948 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 1949 1950 #ifdef CONFIG_NEED_MULTIPLE_NODES 1951 for_each_online_node(i) { 1952 if (NODE_DATA(i)->node_spanned_pages != 0) { 1953 totalram_pages += 1954 free_all_bootmem_node(NODE_DATA(i)); 1955 } 1956 } 1957 #else 1958 totalram_pages = free_all_bootmem(); 1959 #endif 1960 1961 /* We subtract one to account for the mem_map_zero page 1962 * allocated below. 1963 */ 1964 totalram_pages -= 1; 1965 num_physpages = totalram_pages; 1966 1967 /* 1968 * Set up the zero page, mark it reserved, so that page count 1969 * is not manipulated when freeing the page from user ptes. 1970 */ 1971 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 1972 if (mem_map_zero == NULL) { 1973 prom_printf("paging_init: Cannot alloc zero page.\n"); 1974 prom_halt(); 1975 } 1976 SetPageReserved(mem_map_zero); 1977 1978 codepages = (((unsigned long) _etext) - ((unsigned long) _start)); 1979 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT; 1980 datapages = (((unsigned long) _edata) - ((unsigned long) _etext)); 1981 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT; 1982 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); 1983 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; 1984 1985 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", 1986 nr_free_pages() << (PAGE_SHIFT-10), 1987 codepages << (PAGE_SHIFT-10), 1988 datapages << (PAGE_SHIFT-10), 1989 initpages << (PAGE_SHIFT-10), 1990 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT)); 1991 1992 if (tlb_type == cheetah || tlb_type == cheetah_plus) 1993 cheetah_ecache_flush_init(); 1994 } 1995 1996 void free_initmem(void) 1997 { 1998 unsigned long addr, initend; 1999 int do_free = 1; 2000 2001 /* If the physical memory maps were trimmed by kernel command 2002 * line options, don't even try freeing this initmem stuff up. 2003 * The kernel image could have been in the trimmed out region 2004 * and if so the freeing below will free invalid page structs. 2005 */ 2006 if (cmdline_memory_size) 2007 do_free = 0; 2008 2009 /* 2010 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2011 */ 2012 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2013 initend = (unsigned long)(__init_end) & PAGE_MASK; 2014 for (; addr < initend; addr += PAGE_SIZE) { 2015 unsigned long page; 2016 struct page *p; 2017 2018 page = (addr + 2019 ((unsigned long) __va(kern_base)) - 2020 ((unsigned long) KERNBASE)); 2021 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2022 2023 if (do_free) { 2024 p = virt_to_page(page); 2025 2026 ClearPageReserved(p); 2027 init_page_count(p); 2028 __free_page(p); 2029 num_physpages++; 2030 totalram_pages++; 2031 } 2032 } 2033 } 2034 2035 #ifdef CONFIG_BLK_DEV_INITRD 2036 void free_initrd_mem(unsigned long start, unsigned long end) 2037 { 2038 if (start < end) 2039 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); 2040 for (; start < end; start += PAGE_SIZE) { 2041 struct page *p = virt_to_page(start); 2042 2043 ClearPageReserved(p); 2044 init_page_count(p); 2045 __free_page(p); 2046 num_physpages++; 2047 totalram_pages++; 2048 } 2049 } 2050 #endif 2051 2052 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2053 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2054 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2055 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2056 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2057 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2058 2059 pgprot_t PAGE_KERNEL __read_mostly; 2060 EXPORT_SYMBOL(PAGE_KERNEL); 2061 2062 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2063 pgprot_t PAGE_COPY __read_mostly; 2064 2065 pgprot_t PAGE_SHARED __read_mostly; 2066 EXPORT_SYMBOL(PAGE_SHARED); 2067 2068 unsigned long pg_iobits __read_mostly; 2069 2070 unsigned long _PAGE_IE __read_mostly; 2071 EXPORT_SYMBOL(_PAGE_IE); 2072 2073 unsigned long _PAGE_E __read_mostly; 2074 EXPORT_SYMBOL(_PAGE_E); 2075 2076 unsigned long _PAGE_CACHE __read_mostly; 2077 EXPORT_SYMBOL(_PAGE_CACHE); 2078 2079 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2080 unsigned long vmemmap_table[VMEMMAP_SIZE]; 2081 2082 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node) 2083 { 2084 unsigned long vstart = (unsigned long) start; 2085 unsigned long vend = (unsigned long) (start + nr); 2086 unsigned long phys_start = (vstart - VMEMMAP_BASE); 2087 unsigned long phys_end = (vend - VMEMMAP_BASE); 2088 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK; 2089 unsigned long end = VMEMMAP_ALIGN(phys_end); 2090 unsigned long pte_base; 2091 2092 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2093 _PAGE_CP_4U | _PAGE_CV_4U | 2094 _PAGE_P_4U | _PAGE_W_4U); 2095 if (tlb_type == hypervisor) 2096 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2097 _PAGE_CP_4V | _PAGE_CV_4V | 2098 _PAGE_P_4V | _PAGE_W_4V); 2099 2100 for (; addr < end; addr += VMEMMAP_CHUNK) { 2101 unsigned long *vmem_pp = 2102 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT); 2103 void *block; 2104 2105 if (!(*vmem_pp & _PAGE_VALID)) { 2106 block = vmemmap_alloc_block(1UL << 22, node); 2107 if (!block) 2108 return -ENOMEM; 2109 2110 *vmem_pp = pte_base | __pa(block); 2111 2112 printk(KERN_INFO "[%p-%p] page_structs=%lu " 2113 "node=%d entry=%lu/%lu\n", start, block, nr, 2114 node, 2115 addr >> VMEMMAP_CHUNK_SHIFT, 2116 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT); 2117 } 2118 } 2119 return 0; 2120 } 2121 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2122 2123 static void prot_init_common(unsigned long page_none, 2124 unsigned long page_shared, 2125 unsigned long page_copy, 2126 unsigned long page_readonly, 2127 unsigned long page_exec_bit) 2128 { 2129 PAGE_COPY = __pgprot(page_copy); 2130 PAGE_SHARED = __pgprot(page_shared); 2131 2132 protection_map[0x0] = __pgprot(page_none); 2133 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2134 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2135 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2136 protection_map[0x4] = __pgprot(page_readonly); 2137 protection_map[0x5] = __pgprot(page_readonly); 2138 protection_map[0x6] = __pgprot(page_copy); 2139 protection_map[0x7] = __pgprot(page_copy); 2140 protection_map[0x8] = __pgprot(page_none); 2141 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2142 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2143 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2144 protection_map[0xc] = __pgprot(page_readonly); 2145 protection_map[0xd] = __pgprot(page_readonly); 2146 protection_map[0xe] = __pgprot(page_shared); 2147 protection_map[0xf] = __pgprot(page_shared); 2148 } 2149 2150 static void __init sun4u_pgprot_init(void) 2151 { 2152 unsigned long page_none, page_shared, page_copy, page_readonly; 2153 unsigned long page_exec_bit; 2154 2155 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2156 _PAGE_CACHE_4U | _PAGE_P_4U | 2157 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2158 _PAGE_EXEC_4U); 2159 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2160 _PAGE_CACHE_4U | _PAGE_P_4U | 2161 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2162 _PAGE_EXEC_4U | _PAGE_L_4U); 2163 2164 _PAGE_IE = _PAGE_IE_4U; 2165 _PAGE_E = _PAGE_E_4U; 2166 _PAGE_CACHE = _PAGE_CACHE_4U; 2167 2168 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2169 __ACCESS_BITS_4U | _PAGE_E_4U); 2170 2171 #ifdef CONFIG_DEBUG_PAGEALLOC 2172 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^ 2173 0xfffff80000000000UL; 2174 #else 2175 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2176 0xfffff80000000000UL; 2177 #endif 2178 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2179 _PAGE_P_4U | _PAGE_W_4U); 2180 2181 /* XXX Should use 256MB on Panther. XXX */ 2182 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2183 2184 _PAGE_SZBITS = _PAGE_SZBITS_4U; 2185 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2186 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2187 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2188 2189 2190 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2191 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2192 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2193 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2194 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2195 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2196 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2197 2198 page_exec_bit = _PAGE_EXEC_4U; 2199 2200 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2201 page_exec_bit); 2202 } 2203 2204 static void __init sun4v_pgprot_init(void) 2205 { 2206 unsigned long page_none, page_shared, page_copy, page_readonly; 2207 unsigned long page_exec_bit; 2208 2209 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2210 _PAGE_CACHE_4V | _PAGE_P_4V | 2211 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2212 _PAGE_EXEC_4V); 2213 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2214 2215 _PAGE_IE = _PAGE_IE_4V; 2216 _PAGE_E = _PAGE_E_4V; 2217 _PAGE_CACHE = _PAGE_CACHE_4V; 2218 2219 #ifdef CONFIG_DEBUG_PAGEALLOC 2220 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ 2221 0xfffff80000000000UL; 2222 #else 2223 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2224 0xfffff80000000000UL; 2225 #endif 2226 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | 2227 _PAGE_P_4V | _PAGE_W_4V); 2228 2229 #ifdef CONFIG_DEBUG_PAGEALLOC 2230 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ 2231 0xfffff80000000000UL; 2232 #else 2233 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2234 0xfffff80000000000UL; 2235 #endif 2236 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | 2237 _PAGE_P_4V | _PAGE_W_4V); 2238 2239 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2240 __ACCESS_BITS_4V | _PAGE_E_4V); 2241 2242 _PAGE_SZBITS = _PAGE_SZBITS_4V; 2243 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2244 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2245 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2246 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2247 2248 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V; 2249 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | 2250 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2251 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | 2252 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2253 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | 2254 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2255 2256 page_exec_bit = _PAGE_EXEC_4V; 2257 2258 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2259 page_exec_bit); 2260 } 2261 2262 unsigned long pte_sz_bits(unsigned long sz) 2263 { 2264 if (tlb_type == hypervisor) { 2265 switch (sz) { 2266 case 8 * 1024: 2267 default: 2268 return _PAGE_SZ8K_4V; 2269 case 64 * 1024: 2270 return _PAGE_SZ64K_4V; 2271 case 512 * 1024: 2272 return _PAGE_SZ512K_4V; 2273 case 4 * 1024 * 1024: 2274 return _PAGE_SZ4MB_4V; 2275 }; 2276 } else { 2277 switch (sz) { 2278 case 8 * 1024: 2279 default: 2280 return _PAGE_SZ8K_4U; 2281 case 64 * 1024: 2282 return _PAGE_SZ64K_4U; 2283 case 512 * 1024: 2284 return _PAGE_SZ512K_4U; 2285 case 4 * 1024 * 1024: 2286 return _PAGE_SZ4MB_4U; 2287 }; 2288 } 2289 } 2290 2291 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2292 { 2293 pte_t pte; 2294 2295 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2296 pte_val(pte) |= (((unsigned long)space) << 32); 2297 pte_val(pte) |= pte_sz_bits(page_size); 2298 2299 return pte; 2300 } 2301 2302 static unsigned long kern_large_tte(unsigned long paddr) 2303 { 2304 unsigned long val; 2305 2306 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2307 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2308 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2309 if (tlb_type == hypervisor) 2310 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2311 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V | 2312 _PAGE_EXEC_4V | _PAGE_W_4V); 2313 2314 return val | paddr; 2315 } 2316 2317 /* If not locked, zap it. */ 2318 void __flush_tlb_all(void) 2319 { 2320 unsigned long pstate; 2321 int i; 2322 2323 __asm__ __volatile__("flushw\n\t" 2324 "rdpr %%pstate, %0\n\t" 2325 "wrpr %0, %1, %%pstate" 2326 : "=r" (pstate) 2327 : "i" (PSTATE_IE)); 2328 if (tlb_type == hypervisor) { 2329 sun4v_mmu_demap_all(); 2330 } else if (tlb_type == spitfire) { 2331 for (i = 0; i < 64; i++) { 2332 /* Spitfire Errata #32 workaround */ 2333 /* NOTE: Always runs on spitfire, so no 2334 * cheetah+ page size encodings. 2335 */ 2336 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2337 "flush %%g6" 2338 : /* No outputs */ 2339 : "r" (0), 2340 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2341 2342 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2343 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2344 "membar #Sync" 2345 : /* no outputs */ 2346 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2347 spitfire_put_dtlb_data(i, 0x0UL); 2348 } 2349 2350 /* Spitfire Errata #32 workaround */ 2351 /* NOTE: Always runs on spitfire, so no 2352 * cheetah+ page size encodings. 2353 */ 2354 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2355 "flush %%g6" 2356 : /* No outputs */ 2357 : "r" (0), 2358 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2359 2360 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2361 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2362 "membar #Sync" 2363 : /* no outputs */ 2364 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2365 spitfire_put_itlb_data(i, 0x0UL); 2366 } 2367 } 2368 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2369 cheetah_flush_dtlb_all(); 2370 cheetah_flush_itlb_all(); 2371 } 2372 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2373 : : "r" (pstate)); 2374 } 2375