1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sparc64/mm/init.c 4 * 5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #include <linux/extable.h> 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/string.h> 13 #include <linux/init.h> 14 #include <linux/memblock.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h> 17 #include <linux/initrd.h> 18 #include <linux/swap.h> 19 #include <linux/pagemap.h> 20 #include <linux/poison.h> 21 #include <linux/fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/kprobes.h> 24 #include <linux/cache.h> 25 #include <linux/sort.h> 26 #include <linux/ioport.h> 27 #include <linux/percpu.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 31 #include <asm/head.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/pgtable.h> 35 #include <asm/oplib.h> 36 #include <asm/iommu.h> 37 #include <asm/io.h> 38 #include <linux/uaccess.h> 39 #include <asm/mmu_context.h> 40 #include <asm/tlbflush.h> 41 #include <asm/dma.h> 42 #include <asm/starfire.h> 43 #include <asm/tlb.h> 44 #include <asm/spitfire.h> 45 #include <asm/sections.h> 46 #include <asm/tsb.h> 47 #include <asm/hypervisor.h> 48 #include <asm/prom.h> 49 #include <asm/mdesc.h> 50 #include <asm/cpudata.h> 51 #include <asm/setup.h> 52 #include <asm/irq.h> 53 54 #include "init_64.h" 55 56 unsigned long kern_linear_pte_xor[4] __read_mostly; 57 static unsigned long page_cache4v_flag; 58 59 /* A bitmap, two bits for every 256MB of physical memory. These two 60 * bits determine what page size we use for kernel linear 61 * translations. They form an index into kern_linear_pte_xor[]. The 62 * value in the indexed slot is XOR'd with the TLB miss virtual 63 * address to form the resulting TTE. The mapping is: 64 * 65 * 0 ==> 4MB 66 * 1 ==> 256MB 67 * 2 ==> 2GB 68 * 3 ==> 16GB 69 * 70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 71 * support 2GB pages, and hopefully future cpus will support the 16GB 72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 73 * if these larger page sizes are not supported by the cpu. 74 * 75 * It would be nice to determine this from the machine description 76 * 'cpu' properties, but we need to have this table setup before the 77 * MDESC is initialized. 78 */ 79 80 #ifndef CONFIG_DEBUG_PAGEALLOC 81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 82 * Space is allocated for this right after the trap table in 83 * arch/sparc64/kernel/head.S 84 */ 85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 86 #endif 87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 88 89 static unsigned long cpu_pgsz_mask; 90 91 #define MAX_BANKS 1024 92 93 static struct linux_prom64_registers pavail[MAX_BANKS]; 94 static int pavail_ents; 95 96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 97 98 static int cmp_p64(const void *a, const void *b) 99 { 100 const struct linux_prom64_registers *x = a, *y = b; 101 102 if (x->phys_addr > y->phys_addr) 103 return 1; 104 if (x->phys_addr < y->phys_addr) 105 return -1; 106 return 0; 107 } 108 109 static void __init read_obp_memory(const char *property, 110 struct linux_prom64_registers *regs, 111 int *num_ents) 112 { 113 phandle node = prom_finddevice("/memory"); 114 int prop_size = prom_getproplen(node, property); 115 int ents, ret, i; 116 117 ents = prop_size / sizeof(struct linux_prom64_registers); 118 if (ents > MAX_BANKS) { 119 prom_printf("The machine has more %s property entries than " 120 "this kernel can support (%d).\n", 121 property, MAX_BANKS); 122 prom_halt(); 123 } 124 125 ret = prom_getproperty(node, property, (char *) regs, prop_size); 126 if (ret == -1) { 127 prom_printf("Couldn't get %s property from /memory.\n", 128 property); 129 prom_halt(); 130 } 131 132 /* Sanitize what we got from the firmware, by page aligning 133 * everything. 134 */ 135 for (i = 0; i < ents; i++) { 136 unsigned long base, size; 137 138 base = regs[i].phys_addr; 139 size = regs[i].reg_size; 140 141 size &= PAGE_MASK; 142 if (base & ~PAGE_MASK) { 143 unsigned long new_base = PAGE_ALIGN(base); 144 145 size -= new_base - base; 146 if ((long) size < 0L) 147 size = 0UL; 148 base = new_base; 149 } 150 if (size == 0UL) { 151 /* If it is empty, simply get rid of it. 152 * This simplifies the logic of the other 153 * functions that process these arrays. 154 */ 155 memmove(®s[i], ®s[i + 1], 156 (ents - i - 1) * sizeof(regs[0])); 157 i--; 158 ents--; 159 continue; 160 } 161 regs[i].phys_addr = base; 162 regs[i].reg_size = size; 163 } 164 165 *num_ents = ents; 166 167 sort(regs, ents, sizeof(struct linux_prom64_registers), 168 cmp_p64, NULL); 169 } 170 171 /* Kernel physical address base and size in bytes. */ 172 unsigned long kern_base __read_mostly; 173 unsigned long kern_size __read_mostly; 174 175 /* Initial ramdisk setup */ 176 extern unsigned long sparc_ramdisk_image64; 177 extern unsigned int sparc_ramdisk_image; 178 extern unsigned int sparc_ramdisk_size; 179 180 struct page *mem_map_zero __read_mostly; 181 EXPORT_SYMBOL(mem_map_zero); 182 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 184 185 unsigned long sparc64_kern_pri_context __read_mostly; 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 187 unsigned long sparc64_kern_sec_context __read_mostly; 188 189 int num_kernel_image_mappings; 190 191 #ifdef CONFIG_DEBUG_DCFLUSH 192 atomic_t dcpage_flushes = ATOMIC_INIT(0); 193 #ifdef CONFIG_SMP 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 195 #endif 196 #endif 197 198 inline void flush_dcache_page_impl(struct page *page) 199 { 200 BUG_ON(tlb_type == hypervisor); 201 #ifdef CONFIG_DEBUG_DCFLUSH 202 atomic_inc(&dcpage_flushes); 203 #endif 204 205 #ifdef DCACHE_ALIASING_POSSIBLE 206 __flush_dcache_page(page_address(page), 207 ((tlb_type == spitfire) && 208 page_mapping_file(page) != NULL)); 209 #else 210 if (page_mapping_file(page) != NULL && 211 tlb_type == spitfire) 212 __flush_icache_page(__pa(page_address(page))); 213 #endif 214 } 215 216 #define PG_dcache_dirty PG_arch_1 217 #define PG_dcache_cpu_shift 32UL 218 #define PG_dcache_cpu_mask \ 219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 220 221 #define dcache_dirty_cpu(page) \ 222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 223 224 static inline void set_dcache_dirty(struct page *page, int this_cpu) 225 { 226 unsigned long mask = this_cpu; 227 unsigned long non_cpu_bits; 228 229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 231 232 __asm__ __volatile__("1:\n\t" 233 "ldx [%2], %%g7\n\t" 234 "and %%g7, %1, %%g1\n\t" 235 "or %%g1, %0, %%g1\n\t" 236 "casx [%2], %%g7, %%g1\n\t" 237 "cmp %%g7, %%g1\n\t" 238 "bne,pn %%xcc, 1b\n\t" 239 " nop" 240 : /* no outputs */ 241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 242 : "g1", "g7"); 243 } 244 245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) 246 { 247 unsigned long mask = (1UL << PG_dcache_dirty); 248 249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 250 "1:\n\t" 251 "ldx [%2], %%g7\n\t" 252 "srlx %%g7, %4, %%g1\n\t" 253 "and %%g1, %3, %%g1\n\t" 254 "cmp %%g1, %0\n\t" 255 "bne,pn %%icc, 2f\n\t" 256 " andn %%g7, %1, %%g1\n\t" 257 "casx [%2], %%g7, %%g1\n\t" 258 "cmp %%g7, %%g1\n\t" 259 "bne,pn %%xcc, 1b\n\t" 260 " nop\n" 261 "2:" 262 : /* no outputs */ 263 : "r" (cpu), "r" (mask), "r" (&page->flags), 264 "i" (PG_dcache_cpu_mask), 265 "i" (PG_dcache_cpu_shift) 266 : "g1", "g7"); 267 } 268 269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 270 { 271 unsigned long tsb_addr = (unsigned long) ent; 272 273 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 274 tsb_addr = __pa(tsb_addr); 275 276 __tsb_insert(tsb_addr, tag, pte); 277 } 278 279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 280 281 static void flush_dcache(unsigned long pfn) 282 { 283 struct page *page; 284 285 page = pfn_to_page(pfn); 286 if (page) { 287 unsigned long pg_flags; 288 289 pg_flags = page->flags; 290 if (pg_flags & (1UL << PG_dcache_dirty)) { 291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 292 PG_dcache_cpu_mask); 293 int this_cpu = get_cpu(); 294 295 /* This is just to optimize away some function calls 296 * in the SMP case. 297 */ 298 if (cpu == this_cpu) 299 flush_dcache_page_impl(page); 300 else 301 smp_flush_dcache_page_impl(page, cpu); 302 303 clear_dcache_dirty_cpu(page, cpu); 304 305 put_cpu(); 306 } 307 } 308 } 309 310 /* mm->context.lock must be held */ 311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 312 unsigned long tsb_hash_shift, unsigned long address, 313 unsigned long tte) 314 { 315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 316 unsigned long tag; 317 318 if (unlikely(!tsb)) 319 return; 320 321 tsb += ((address >> tsb_hash_shift) & 322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 323 tag = (address >> 22UL); 324 tsb_insert(tsb, tag, tte); 325 } 326 327 #ifdef CONFIG_HUGETLB_PAGE 328 static int __init hugetlbpage_init(void) 329 { 330 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT); 331 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT); 332 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT); 333 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT); 334 335 return 0; 336 } 337 338 arch_initcall(hugetlbpage_init); 339 340 static void __init pud_huge_patch(void) 341 { 342 struct pud_huge_patch_entry *p; 343 unsigned long addr; 344 345 p = &__pud_huge_patch; 346 addr = p->addr; 347 *(unsigned int *)addr = p->insn; 348 349 __asm__ __volatile__("flush %0" : : "r" (addr)); 350 } 351 352 bool __init arch_hugetlb_valid_size(unsigned long size) 353 { 354 unsigned int hugepage_shift = ilog2(size); 355 unsigned short hv_pgsz_idx; 356 unsigned int hv_pgsz_mask; 357 358 switch (hugepage_shift) { 359 case HPAGE_16GB_SHIFT: 360 hv_pgsz_mask = HV_PGSZ_MASK_16GB; 361 hv_pgsz_idx = HV_PGSZ_IDX_16GB; 362 pud_huge_patch(); 363 break; 364 case HPAGE_2GB_SHIFT: 365 hv_pgsz_mask = HV_PGSZ_MASK_2GB; 366 hv_pgsz_idx = HV_PGSZ_IDX_2GB; 367 break; 368 case HPAGE_256MB_SHIFT: 369 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 370 hv_pgsz_idx = HV_PGSZ_IDX_256MB; 371 break; 372 case HPAGE_SHIFT: 373 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 374 hv_pgsz_idx = HV_PGSZ_IDX_4MB; 375 break; 376 case HPAGE_64K_SHIFT: 377 hv_pgsz_mask = HV_PGSZ_MASK_64K; 378 hv_pgsz_idx = HV_PGSZ_IDX_64K; 379 break; 380 default: 381 hv_pgsz_mask = 0; 382 } 383 384 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) 385 return false; 386 387 return true; 388 } 389 #endif /* CONFIG_HUGETLB_PAGE */ 390 391 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 392 { 393 struct mm_struct *mm; 394 unsigned long flags; 395 bool is_huge_tsb; 396 pte_t pte = *ptep; 397 398 if (tlb_type != hypervisor) { 399 unsigned long pfn = pte_pfn(pte); 400 401 if (pfn_valid(pfn)) 402 flush_dcache(pfn); 403 } 404 405 mm = vma->vm_mm; 406 407 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 408 if (!pte_accessible(mm, pte)) 409 return; 410 411 spin_lock_irqsave(&mm->context.lock, flags); 412 413 is_huge_tsb = false; 414 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 415 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) { 416 unsigned long hugepage_size = PAGE_SIZE; 417 418 if (is_vm_hugetlb_page(vma)) 419 hugepage_size = huge_page_size(hstate_vma(vma)); 420 421 if (hugepage_size >= PUD_SIZE) { 422 unsigned long mask = 0x1ffc00000UL; 423 424 /* Transfer bits [32:22] from address to resolve 425 * at 4M granularity. 426 */ 427 pte_val(pte) &= ~mask; 428 pte_val(pte) |= (address & mask); 429 } else if (hugepage_size >= PMD_SIZE) { 430 /* We are fabricating 8MB pages using 4MB 431 * real hw pages. 432 */ 433 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 434 } 435 436 if (hugepage_size >= PMD_SIZE) { 437 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, 438 REAL_HPAGE_SHIFT, address, pte_val(pte)); 439 is_huge_tsb = true; 440 } 441 } 442 #endif 443 if (!is_huge_tsb) 444 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 445 address, pte_val(pte)); 446 447 spin_unlock_irqrestore(&mm->context.lock, flags); 448 } 449 450 void flush_dcache_page(struct page *page) 451 { 452 struct address_space *mapping; 453 int this_cpu; 454 455 if (tlb_type == hypervisor) 456 return; 457 458 /* Do not bother with the expensive D-cache flush if it 459 * is merely the zero page. The 'bigcore' testcase in GDB 460 * causes this case to run millions of times. 461 */ 462 if (page == ZERO_PAGE(0)) 463 return; 464 465 this_cpu = get_cpu(); 466 467 mapping = page_mapping_file(page); 468 if (mapping && !mapping_mapped(mapping)) { 469 int dirty = test_bit(PG_dcache_dirty, &page->flags); 470 if (dirty) { 471 int dirty_cpu = dcache_dirty_cpu(page); 472 473 if (dirty_cpu == this_cpu) 474 goto out; 475 smp_flush_dcache_page_impl(page, dirty_cpu); 476 } 477 set_dcache_dirty(page, this_cpu); 478 } else { 479 /* We could delay the flush for the !page_mapping 480 * case too. But that case is for exec env/arg 481 * pages and those are %99 certainly going to get 482 * faulted into the tlb (and thus flushed) anyways. 483 */ 484 flush_dcache_page_impl(page); 485 } 486 487 out: 488 put_cpu(); 489 } 490 EXPORT_SYMBOL(flush_dcache_page); 491 492 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 493 { 494 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 495 if (tlb_type == spitfire) { 496 unsigned long kaddr; 497 498 /* This code only runs on Spitfire cpus so this is 499 * why we can assume _PAGE_PADDR_4U. 500 */ 501 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 502 unsigned long paddr, mask = _PAGE_PADDR_4U; 503 504 if (kaddr >= PAGE_OFFSET) 505 paddr = kaddr & mask; 506 else { 507 pgd_t *pgdp = pgd_offset_k(kaddr); 508 p4d_t *p4dp = p4d_offset(pgdp, kaddr); 509 pud_t *pudp = pud_offset(p4dp, kaddr); 510 pmd_t *pmdp = pmd_offset(pudp, kaddr); 511 pte_t *ptep = pte_offset_kernel(pmdp, kaddr); 512 513 paddr = pte_val(*ptep) & mask; 514 } 515 __flush_icache_page(paddr); 516 } 517 } 518 } 519 EXPORT_SYMBOL(flush_icache_range); 520 521 void mmu_info(struct seq_file *m) 522 { 523 static const char *pgsz_strings[] = { 524 "8K", "64K", "512K", "4MB", "32MB", 525 "256MB", "2GB", "16GB", 526 }; 527 int i, printed; 528 529 if (tlb_type == cheetah) 530 seq_printf(m, "MMU Type\t: Cheetah\n"); 531 else if (tlb_type == cheetah_plus) 532 seq_printf(m, "MMU Type\t: Cheetah+\n"); 533 else if (tlb_type == spitfire) 534 seq_printf(m, "MMU Type\t: Spitfire\n"); 535 else if (tlb_type == hypervisor) 536 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 537 else 538 seq_printf(m, "MMU Type\t: ???\n"); 539 540 seq_printf(m, "MMU PGSZs\t: "); 541 printed = 0; 542 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 543 if (cpu_pgsz_mask & (1UL << i)) { 544 seq_printf(m, "%s%s", 545 printed ? "," : "", pgsz_strings[i]); 546 printed++; 547 } 548 } 549 seq_putc(m, '\n'); 550 551 #ifdef CONFIG_DEBUG_DCFLUSH 552 seq_printf(m, "DCPageFlushes\t: %d\n", 553 atomic_read(&dcpage_flushes)); 554 #ifdef CONFIG_SMP 555 seq_printf(m, "DCPageFlushesXC\t: %d\n", 556 atomic_read(&dcpage_flushes_xcall)); 557 #endif /* CONFIG_SMP */ 558 #endif /* CONFIG_DEBUG_DCFLUSH */ 559 } 560 561 struct linux_prom_translation prom_trans[512] __read_mostly; 562 unsigned int prom_trans_ents __read_mostly; 563 564 unsigned long kern_locked_tte_data; 565 566 /* The obp translations are saved based on 8k pagesize, since obp can 567 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 568 * HI_OBP_ADDRESS range are handled in ktlb.S. 569 */ 570 static inline int in_obp_range(unsigned long vaddr) 571 { 572 return (vaddr >= LOW_OBP_ADDRESS && 573 vaddr < HI_OBP_ADDRESS); 574 } 575 576 static int cmp_ptrans(const void *a, const void *b) 577 { 578 const struct linux_prom_translation *x = a, *y = b; 579 580 if (x->virt > y->virt) 581 return 1; 582 if (x->virt < y->virt) 583 return -1; 584 return 0; 585 } 586 587 /* Read OBP translations property into 'prom_trans[]'. */ 588 static void __init read_obp_translations(void) 589 { 590 int n, node, ents, first, last, i; 591 592 node = prom_finddevice("/virtual-memory"); 593 n = prom_getproplen(node, "translations"); 594 if (unlikely(n == 0 || n == -1)) { 595 prom_printf("prom_mappings: Couldn't get size.\n"); 596 prom_halt(); 597 } 598 if (unlikely(n > sizeof(prom_trans))) { 599 prom_printf("prom_mappings: Size %d is too big.\n", n); 600 prom_halt(); 601 } 602 603 if ((n = prom_getproperty(node, "translations", 604 (char *)&prom_trans[0], 605 sizeof(prom_trans))) == -1) { 606 prom_printf("prom_mappings: Couldn't get property.\n"); 607 prom_halt(); 608 } 609 610 n = n / sizeof(struct linux_prom_translation); 611 612 ents = n; 613 614 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 615 cmp_ptrans, NULL); 616 617 /* Now kick out all the non-OBP entries. */ 618 for (i = 0; i < ents; i++) { 619 if (in_obp_range(prom_trans[i].virt)) 620 break; 621 } 622 first = i; 623 for (; i < ents; i++) { 624 if (!in_obp_range(prom_trans[i].virt)) 625 break; 626 } 627 last = i; 628 629 for (i = 0; i < (last - first); i++) { 630 struct linux_prom_translation *src = &prom_trans[i + first]; 631 struct linux_prom_translation *dest = &prom_trans[i]; 632 633 *dest = *src; 634 } 635 for (; i < ents; i++) { 636 struct linux_prom_translation *dest = &prom_trans[i]; 637 dest->virt = dest->size = dest->data = 0x0UL; 638 } 639 640 prom_trans_ents = last - first; 641 642 if (tlb_type == spitfire) { 643 /* Clear diag TTE bits. */ 644 for (i = 0; i < prom_trans_ents; i++) 645 prom_trans[i].data &= ~0x0003fe0000000000UL; 646 } 647 648 /* Force execute bit on. */ 649 for (i = 0; i < prom_trans_ents; i++) 650 prom_trans[i].data |= (tlb_type == hypervisor ? 651 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 652 } 653 654 static void __init hypervisor_tlb_lock(unsigned long vaddr, 655 unsigned long pte, 656 unsigned long mmu) 657 { 658 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 659 660 if (ret != 0) { 661 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 662 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 663 prom_halt(); 664 } 665 } 666 667 static unsigned long kern_large_tte(unsigned long paddr); 668 669 static void __init remap_kernel(void) 670 { 671 unsigned long phys_page, tte_vaddr, tte_data; 672 int i, tlb_ent = sparc64_highest_locked_tlbent(); 673 674 tte_vaddr = (unsigned long) KERNBASE; 675 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 676 tte_data = kern_large_tte(phys_page); 677 678 kern_locked_tte_data = tte_data; 679 680 /* Now lock us into the TLBs via Hypervisor or OBP. */ 681 if (tlb_type == hypervisor) { 682 for (i = 0; i < num_kernel_image_mappings; i++) { 683 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 684 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 685 tte_vaddr += 0x400000; 686 tte_data += 0x400000; 687 } 688 } else { 689 for (i = 0; i < num_kernel_image_mappings; i++) { 690 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 691 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 692 tte_vaddr += 0x400000; 693 tte_data += 0x400000; 694 } 695 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 696 } 697 if (tlb_type == cheetah_plus) { 698 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 699 CTX_CHEETAH_PLUS_NUC); 700 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 701 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 702 } 703 } 704 705 706 static void __init inherit_prom_mappings(void) 707 { 708 /* Now fixup OBP's idea about where we really are mapped. */ 709 printk("Remapping the kernel... "); 710 remap_kernel(); 711 printk("done.\n"); 712 } 713 714 void prom_world(int enter) 715 { 716 if (!enter) 717 set_fs(get_fs()); 718 719 __asm__ __volatile__("flushw"); 720 } 721 722 void __flush_dcache_range(unsigned long start, unsigned long end) 723 { 724 unsigned long va; 725 726 if (tlb_type == spitfire) { 727 int n = 0; 728 729 for (va = start; va < end; va += 32) { 730 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 731 if (++n >= 512) 732 break; 733 } 734 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 735 start = __pa(start); 736 end = __pa(end); 737 for (va = start; va < end; va += 32) 738 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 739 "membar #Sync" 740 : /* no outputs */ 741 : "r" (va), 742 "i" (ASI_DCACHE_INVALIDATE)); 743 } 744 } 745 EXPORT_SYMBOL(__flush_dcache_range); 746 747 /* get_new_mmu_context() uses "cache + 1". */ 748 DEFINE_SPINLOCK(ctx_alloc_lock); 749 unsigned long tlb_context_cache = CTX_FIRST_VERSION; 750 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 751 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 752 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 753 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; 754 755 static void mmu_context_wrap(void) 756 { 757 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; 758 unsigned long new_ver, new_ctx, old_ctx; 759 struct mm_struct *mm; 760 int cpu; 761 762 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); 763 764 /* Reserve kernel context */ 765 set_bit(0, mmu_context_bmap); 766 767 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; 768 if (unlikely(new_ver == 0)) 769 new_ver = CTX_FIRST_VERSION; 770 tlb_context_cache = new_ver; 771 772 /* 773 * Make sure that any new mm that are added into per_cpu_secondary_mm, 774 * are going to go through get_new_mmu_context() path. 775 */ 776 mb(); 777 778 /* 779 * Updated versions to current on those CPUs that had valid secondary 780 * contexts 781 */ 782 for_each_online_cpu(cpu) { 783 /* 784 * If a new mm is stored after we took this mm from the array, 785 * it will go into get_new_mmu_context() path, because we 786 * already bumped the version in tlb_context_cache. 787 */ 788 mm = per_cpu(per_cpu_secondary_mm, cpu); 789 790 if (unlikely(!mm || mm == &init_mm)) 791 continue; 792 793 old_ctx = mm->context.sparc64_ctx_val; 794 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { 795 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; 796 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); 797 mm->context.sparc64_ctx_val = new_ctx; 798 } 799 } 800 } 801 802 /* Caller does TLB context flushing on local CPU if necessary. 803 * The caller also ensures that CTX_VALID(mm->context) is false. 804 * 805 * We must be careful about boundary cases so that we never 806 * let the user have CTX 0 (nucleus) or we ever use a CTX 807 * version of zero (and thus NO_CONTEXT would not be caught 808 * by version mis-match tests in mmu_context.h). 809 * 810 * Always invoked with interrupts disabled. 811 */ 812 void get_new_mmu_context(struct mm_struct *mm) 813 { 814 unsigned long ctx, new_ctx; 815 unsigned long orig_pgsz_bits; 816 817 spin_lock(&ctx_alloc_lock); 818 retry: 819 /* wrap might have happened, test again if our context became valid */ 820 if (unlikely(CTX_VALID(mm->context))) 821 goto out; 822 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 823 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 824 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 825 if (new_ctx >= (1 << CTX_NR_BITS)) { 826 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 827 if (new_ctx >= ctx) { 828 mmu_context_wrap(); 829 goto retry; 830 } 831 } 832 if (mm->context.sparc64_ctx_val) 833 cpumask_clear(mm_cpumask(mm)); 834 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 835 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 836 tlb_context_cache = new_ctx; 837 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 838 out: 839 spin_unlock(&ctx_alloc_lock); 840 } 841 842 static int numa_enabled = 1; 843 static int numa_debug; 844 845 static int __init early_numa(char *p) 846 { 847 if (!p) 848 return 0; 849 850 if (strstr(p, "off")) 851 numa_enabled = 0; 852 853 if (strstr(p, "debug")) 854 numa_debug = 1; 855 856 return 0; 857 } 858 early_param("numa", early_numa); 859 860 #define numadbg(f, a...) \ 861 do { if (numa_debug) \ 862 printk(KERN_INFO f, ## a); \ 863 } while (0) 864 865 static void __init find_ramdisk(unsigned long phys_base) 866 { 867 #ifdef CONFIG_BLK_DEV_INITRD 868 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 869 unsigned long ramdisk_image; 870 871 /* Older versions of the bootloader only supported a 872 * 32-bit physical address for the ramdisk image 873 * location, stored at sparc_ramdisk_image. Newer 874 * SILO versions set sparc_ramdisk_image to zero and 875 * provide a full 64-bit physical address at 876 * sparc_ramdisk_image64. 877 */ 878 ramdisk_image = sparc_ramdisk_image; 879 if (!ramdisk_image) 880 ramdisk_image = sparc_ramdisk_image64; 881 882 /* Another bootloader quirk. The bootloader normalizes 883 * the physical address to KERNBASE, so we have to 884 * factor that back out and add in the lowest valid 885 * physical page address to get the true physical address. 886 */ 887 ramdisk_image -= KERNBASE; 888 ramdisk_image += phys_base; 889 890 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 891 ramdisk_image, sparc_ramdisk_size); 892 893 initrd_start = ramdisk_image; 894 initrd_end = ramdisk_image + sparc_ramdisk_size; 895 896 memblock_reserve(initrd_start, sparc_ramdisk_size); 897 898 initrd_start += PAGE_OFFSET; 899 initrd_end += PAGE_OFFSET; 900 } 901 #endif 902 } 903 904 struct node_mem_mask { 905 unsigned long mask; 906 unsigned long match; 907 }; 908 static struct node_mem_mask node_masks[MAX_NUMNODES]; 909 static int num_node_masks; 910 911 #ifdef CONFIG_NEED_MULTIPLE_NODES 912 913 struct mdesc_mlgroup { 914 u64 node; 915 u64 latency; 916 u64 match; 917 u64 mask; 918 }; 919 920 static struct mdesc_mlgroup *mlgroups; 921 static int num_mlgroups; 922 923 int numa_cpu_lookup_table[NR_CPUS]; 924 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 925 926 struct mdesc_mblock { 927 u64 base; 928 u64 size; 929 u64 offset; /* RA-to-PA */ 930 }; 931 static struct mdesc_mblock *mblocks; 932 static int num_mblocks; 933 934 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 935 { 936 struct mdesc_mblock *m = NULL; 937 int i; 938 939 for (i = 0; i < num_mblocks; i++) { 940 m = &mblocks[i]; 941 942 if (addr >= m->base && 943 addr < (m->base + m->size)) { 944 break; 945 } 946 } 947 948 return m; 949 } 950 951 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 952 { 953 int prev_nid, new_nid; 954 955 prev_nid = NUMA_NO_NODE; 956 for ( ; start < end; start += PAGE_SIZE) { 957 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 958 struct node_mem_mask *p = &node_masks[new_nid]; 959 960 if ((start & p->mask) == p->match) { 961 if (prev_nid == NUMA_NO_NODE) 962 prev_nid = new_nid; 963 break; 964 } 965 } 966 967 if (new_nid == num_node_masks) { 968 prev_nid = 0; 969 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 970 start); 971 break; 972 } 973 974 if (prev_nid != new_nid) 975 break; 976 } 977 *nid = prev_nid; 978 979 return start > end ? end : start; 980 } 981 982 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 983 { 984 u64 ret_end, pa_start, m_mask, m_match, m_end; 985 struct mdesc_mblock *mblock; 986 int _nid, i; 987 988 if (tlb_type != hypervisor) 989 return memblock_nid_range_sun4u(start, end, nid); 990 991 mblock = addr_to_mblock(start); 992 if (!mblock) { 993 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 994 start); 995 996 _nid = 0; 997 ret_end = end; 998 goto done; 999 } 1000 1001 pa_start = start + mblock->offset; 1002 m_match = 0; 1003 m_mask = 0; 1004 1005 for (_nid = 0; _nid < num_node_masks; _nid++) { 1006 struct node_mem_mask *const m = &node_masks[_nid]; 1007 1008 if ((pa_start & m->mask) == m->match) { 1009 m_match = m->match; 1010 m_mask = m->mask; 1011 break; 1012 } 1013 } 1014 1015 if (num_node_masks == _nid) { 1016 /* We could not find NUMA group, so default to 0, but lets 1017 * search for latency group, so we could calculate the correct 1018 * end address that we return 1019 */ 1020 _nid = 0; 1021 1022 for (i = 0; i < num_mlgroups; i++) { 1023 struct mdesc_mlgroup *const m = &mlgroups[i]; 1024 1025 if ((pa_start & m->mask) == m->match) { 1026 m_match = m->match; 1027 m_mask = m->mask; 1028 break; 1029 } 1030 } 1031 1032 if (i == num_mlgroups) { 1033 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 1034 start); 1035 1036 ret_end = end; 1037 goto done; 1038 } 1039 } 1040 1041 /* 1042 * Each latency group has match and mask, and each memory block has an 1043 * offset. An address belongs to a latency group if its address matches 1044 * the following formula: ((addr + offset) & mask) == match 1045 * It is, however, slow to check every single page if it matches a 1046 * particular latency group. As optimization we calculate end value by 1047 * using bit arithmetics. 1048 */ 1049 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 1050 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 1051 ret_end = m_end > end ? end : m_end; 1052 1053 done: 1054 *nid = _nid; 1055 return ret_end; 1056 } 1057 #endif 1058 1059 /* This must be invoked after performing all of the necessary 1060 * memblock_set_node() calls for 'nid'. We need to be able to get 1061 * correct data from get_pfn_range_for_nid(). 1062 */ 1063 static void __init allocate_node_data(int nid) 1064 { 1065 struct pglist_data *p; 1066 unsigned long start_pfn, end_pfn; 1067 #ifdef CONFIG_NEED_MULTIPLE_NODES 1068 1069 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data), 1070 SMP_CACHE_BYTES, nid); 1071 if (!NODE_DATA(nid)) { 1072 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); 1073 prom_halt(); 1074 } 1075 1076 NODE_DATA(nid)->node_id = nid; 1077 #endif 1078 1079 p = NODE_DATA(nid); 1080 1081 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1082 p->node_start_pfn = start_pfn; 1083 p->node_spanned_pages = end_pfn - start_pfn; 1084 } 1085 1086 static void init_node_masks_nonnuma(void) 1087 { 1088 #ifdef CONFIG_NEED_MULTIPLE_NODES 1089 int i; 1090 #endif 1091 1092 numadbg("Initializing tables for non-numa.\n"); 1093 1094 node_masks[0].mask = 0; 1095 node_masks[0].match = 0; 1096 num_node_masks = 1; 1097 1098 #ifdef CONFIG_NEED_MULTIPLE_NODES 1099 for (i = 0; i < NR_CPUS; i++) 1100 numa_cpu_lookup_table[i] = 0; 1101 1102 cpumask_setall(&numa_cpumask_lookup_table[0]); 1103 #endif 1104 } 1105 1106 #ifdef CONFIG_NEED_MULTIPLE_NODES 1107 struct pglist_data *node_data[MAX_NUMNODES]; 1108 1109 EXPORT_SYMBOL(numa_cpu_lookup_table); 1110 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1111 EXPORT_SYMBOL(node_data); 1112 1113 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1114 u32 cfg_handle) 1115 { 1116 u64 arc; 1117 1118 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1119 u64 target = mdesc_arc_target(md, arc); 1120 const u64 *val; 1121 1122 val = mdesc_get_property(md, target, 1123 "cfg-handle", NULL); 1124 if (val && *val == cfg_handle) 1125 return 0; 1126 } 1127 return -ENODEV; 1128 } 1129 1130 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1131 u32 cfg_handle) 1132 { 1133 u64 arc, candidate, best_latency = ~(u64)0; 1134 1135 candidate = MDESC_NODE_NULL; 1136 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1137 u64 target = mdesc_arc_target(md, arc); 1138 const char *name = mdesc_node_name(md, target); 1139 const u64 *val; 1140 1141 if (strcmp(name, "pio-latency-group")) 1142 continue; 1143 1144 val = mdesc_get_property(md, target, "latency", NULL); 1145 if (!val) 1146 continue; 1147 1148 if (*val < best_latency) { 1149 candidate = target; 1150 best_latency = *val; 1151 } 1152 } 1153 1154 if (candidate == MDESC_NODE_NULL) 1155 return -ENODEV; 1156 1157 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1158 } 1159 1160 int of_node_to_nid(struct device_node *dp) 1161 { 1162 const struct linux_prom64_registers *regs; 1163 struct mdesc_handle *md; 1164 u32 cfg_handle; 1165 int count, nid; 1166 u64 grp; 1167 1168 /* This is the right thing to do on currently supported 1169 * SUN4U NUMA platforms as well, as the PCI controller does 1170 * not sit behind any particular memory controller. 1171 */ 1172 if (!mlgroups) 1173 return -1; 1174 1175 regs = of_get_property(dp, "reg", NULL); 1176 if (!regs) 1177 return -1; 1178 1179 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1180 1181 md = mdesc_grab(); 1182 1183 count = 0; 1184 nid = NUMA_NO_NODE; 1185 mdesc_for_each_node_by_name(md, grp, "group") { 1186 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1187 nid = count; 1188 break; 1189 } 1190 count++; 1191 } 1192 1193 mdesc_release(md); 1194 1195 return nid; 1196 } 1197 1198 static void __init add_node_ranges(void) 1199 { 1200 struct memblock_region *reg; 1201 unsigned long prev_max; 1202 1203 memblock_resized: 1204 prev_max = memblock.memory.max; 1205 1206 for_each_memblock(memory, reg) { 1207 unsigned long size = reg->size; 1208 unsigned long start, end; 1209 1210 start = reg->base; 1211 end = start + size; 1212 while (start < end) { 1213 unsigned long this_end; 1214 int nid; 1215 1216 this_end = memblock_nid_range(start, end, &nid); 1217 1218 numadbg("Setting memblock NUMA node nid[%d] " 1219 "start[%lx] end[%lx]\n", 1220 nid, start, this_end); 1221 1222 memblock_set_node(start, this_end - start, 1223 &memblock.memory, nid); 1224 if (memblock.memory.max != prev_max) 1225 goto memblock_resized; 1226 start = this_end; 1227 } 1228 } 1229 } 1230 1231 static int __init grab_mlgroups(struct mdesc_handle *md) 1232 { 1233 unsigned long paddr; 1234 int count = 0; 1235 u64 node; 1236 1237 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1238 count++; 1239 if (!count) 1240 return -ENOENT; 1241 1242 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup), 1243 SMP_CACHE_BYTES); 1244 if (!paddr) 1245 return -ENOMEM; 1246 1247 mlgroups = __va(paddr); 1248 num_mlgroups = count; 1249 1250 count = 0; 1251 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1252 struct mdesc_mlgroup *m = &mlgroups[count++]; 1253 const u64 *val; 1254 1255 m->node = node; 1256 1257 val = mdesc_get_property(md, node, "latency", NULL); 1258 m->latency = *val; 1259 val = mdesc_get_property(md, node, "address-match", NULL); 1260 m->match = *val; 1261 val = mdesc_get_property(md, node, "address-mask", NULL); 1262 m->mask = *val; 1263 1264 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1265 "match[%llx] mask[%llx]\n", 1266 count - 1, m->node, m->latency, m->match, m->mask); 1267 } 1268 1269 return 0; 1270 } 1271 1272 static int __init grab_mblocks(struct mdesc_handle *md) 1273 { 1274 unsigned long paddr; 1275 int count = 0; 1276 u64 node; 1277 1278 mdesc_for_each_node_by_name(md, node, "mblock") 1279 count++; 1280 if (!count) 1281 return -ENOENT; 1282 1283 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock), 1284 SMP_CACHE_BYTES); 1285 if (!paddr) 1286 return -ENOMEM; 1287 1288 mblocks = __va(paddr); 1289 num_mblocks = count; 1290 1291 count = 0; 1292 mdesc_for_each_node_by_name(md, node, "mblock") { 1293 struct mdesc_mblock *m = &mblocks[count++]; 1294 const u64 *val; 1295 1296 val = mdesc_get_property(md, node, "base", NULL); 1297 m->base = *val; 1298 val = mdesc_get_property(md, node, "size", NULL); 1299 m->size = *val; 1300 val = mdesc_get_property(md, node, 1301 "address-congruence-offset", NULL); 1302 1303 /* The address-congruence-offset property is optional. 1304 * Explicity zero it be identifty this. 1305 */ 1306 if (val) 1307 m->offset = *val; 1308 else 1309 m->offset = 0UL; 1310 1311 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1312 count - 1, m->base, m->size, m->offset); 1313 } 1314 1315 return 0; 1316 } 1317 1318 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1319 u64 grp, cpumask_t *mask) 1320 { 1321 u64 arc; 1322 1323 cpumask_clear(mask); 1324 1325 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1326 u64 target = mdesc_arc_target(md, arc); 1327 const char *name = mdesc_node_name(md, target); 1328 const u64 *id; 1329 1330 if (strcmp(name, "cpu")) 1331 continue; 1332 id = mdesc_get_property(md, target, "id", NULL); 1333 if (*id < nr_cpu_ids) 1334 cpumask_set_cpu(*id, mask); 1335 } 1336 } 1337 1338 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1339 { 1340 int i; 1341 1342 for (i = 0; i < num_mlgroups; i++) { 1343 struct mdesc_mlgroup *m = &mlgroups[i]; 1344 if (m->node == node) 1345 return m; 1346 } 1347 return NULL; 1348 } 1349 1350 int __node_distance(int from, int to) 1351 { 1352 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1353 pr_warn("Returning default NUMA distance value for %d->%d\n", 1354 from, to); 1355 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1356 } 1357 return numa_latency[from][to]; 1358 } 1359 EXPORT_SYMBOL(__node_distance); 1360 1361 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1362 { 1363 int i; 1364 1365 for (i = 0; i < MAX_NUMNODES; i++) { 1366 struct node_mem_mask *n = &node_masks[i]; 1367 1368 if ((grp->mask == n->mask) && (grp->match == n->match)) 1369 break; 1370 } 1371 return i; 1372 } 1373 1374 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1375 u64 grp, int index) 1376 { 1377 u64 arc; 1378 1379 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1380 int tnode; 1381 u64 target = mdesc_arc_target(md, arc); 1382 struct mdesc_mlgroup *m = find_mlgroup(target); 1383 1384 if (!m) 1385 continue; 1386 tnode = find_best_numa_node_for_mlgroup(m); 1387 if (tnode == MAX_NUMNODES) 1388 continue; 1389 numa_latency[index][tnode] = m->latency; 1390 } 1391 } 1392 1393 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1394 int index) 1395 { 1396 struct mdesc_mlgroup *candidate = NULL; 1397 u64 arc, best_latency = ~(u64)0; 1398 struct node_mem_mask *n; 1399 1400 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1401 u64 target = mdesc_arc_target(md, arc); 1402 struct mdesc_mlgroup *m = find_mlgroup(target); 1403 if (!m) 1404 continue; 1405 if (m->latency < best_latency) { 1406 candidate = m; 1407 best_latency = m->latency; 1408 } 1409 } 1410 if (!candidate) 1411 return -ENOENT; 1412 1413 if (num_node_masks != index) { 1414 printk(KERN_ERR "Inconsistent NUMA state, " 1415 "index[%d] != num_node_masks[%d]\n", 1416 index, num_node_masks); 1417 return -EINVAL; 1418 } 1419 1420 n = &node_masks[num_node_masks++]; 1421 1422 n->mask = candidate->mask; 1423 n->match = candidate->match; 1424 1425 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1426 index, n->mask, n->match, candidate->latency); 1427 1428 return 0; 1429 } 1430 1431 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1432 int index) 1433 { 1434 cpumask_t mask; 1435 int cpu; 1436 1437 numa_parse_mdesc_group_cpus(md, grp, &mask); 1438 1439 for_each_cpu(cpu, &mask) 1440 numa_cpu_lookup_table[cpu] = index; 1441 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1442 1443 if (numa_debug) { 1444 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1445 for_each_cpu(cpu, &mask) 1446 printk("%d ", cpu); 1447 printk("]\n"); 1448 } 1449 1450 return numa_attach_mlgroup(md, grp, index); 1451 } 1452 1453 static int __init numa_parse_mdesc(void) 1454 { 1455 struct mdesc_handle *md = mdesc_grab(); 1456 int i, j, err, count; 1457 u64 node; 1458 1459 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1460 if (node == MDESC_NODE_NULL) { 1461 mdesc_release(md); 1462 return -ENOENT; 1463 } 1464 1465 err = grab_mblocks(md); 1466 if (err < 0) 1467 goto out; 1468 1469 err = grab_mlgroups(md); 1470 if (err < 0) 1471 goto out; 1472 1473 count = 0; 1474 mdesc_for_each_node_by_name(md, node, "group") { 1475 err = numa_parse_mdesc_group(md, node, count); 1476 if (err < 0) 1477 break; 1478 count++; 1479 } 1480 1481 count = 0; 1482 mdesc_for_each_node_by_name(md, node, "group") { 1483 find_numa_latencies_for_group(md, node, count); 1484 count++; 1485 } 1486 1487 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1488 for (i = 0; i < MAX_NUMNODES; i++) { 1489 u64 self_latency = numa_latency[i][i]; 1490 1491 for (j = 0; j < MAX_NUMNODES; j++) { 1492 numa_latency[i][j] = 1493 (numa_latency[i][j] * LOCAL_DISTANCE) / 1494 self_latency; 1495 } 1496 } 1497 1498 add_node_ranges(); 1499 1500 for (i = 0; i < num_node_masks; i++) { 1501 allocate_node_data(i); 1502 node_set_online(i); 1503 } 1504 1505 err = 0; 1506 out: 1507 mdesc_release(md); 1508 return err; 1509 } 1510 1511 static int __init numa_parse_jbus(void) 1512 { 1513 unsigned long cpu, index; 1514 1515 /* NUMA node id is encoded in bits 36 and higher, and there is 1516 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1517 */ 1518 index = 0; 1519 for_each_present_cpu(cpu) { 1520 numa_cpu_lookup_table[cpu] = index; 1521 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1522 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1523 node_masks[index].match = cpu << 36UL; 1524 1525 index++; 1526 } 1527 num_node_masks = index; 1528 1529 add_node_ranges(); 1530 1531 for (index = 0; index < num_node_masks; index++) { 1532 allocate_node_data(index); 1533 node_set_online(index); 1534 } 1535 1536 return 0; 1537 } 1538 1539 static int __init numa_parse_sun4u(void) 1540 { 1541 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1542 unsigned long ver; 1543 1544 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1545 if ((ver >> 32UL) == __JALAPENO_ID || 1546 (ver >> 32UL) == __SERRANO_ID) 1547 return numa_parse_jbus(); 1548 } 1549 return -1; 1550 } 1551 1552 static int __init bootmem_init_numa(void) 1553 { 1554 int i, j; 1555 int err = -1; 1556 1557 numadbg("bootmem_init_numa()\n"); 1558 1559 /* Some sane defaults for numa latency values */ 1560 for (i = 0; i < MAX_NUMNODES; i++) { 1561 for (j = 0; j < MAX_NUMNODES; j++) 1562 numa_latency[i][j] = (i == j) ? 1563 LOCAL_DISTANCE : REMOTE_DISTANCE; 1564 } 1565 1566 if (numa_enabled) { 1567 if (tlb_type == hypervisor) 1568 err = numa_parse_mdesc(); 1569 else 1570 err = numa_parse_sun4u(); 1571 } 1572 return err; 1573 } 1574 1575 #else 1576 1577 static int bootmem_init_numa(void) 1578 { 1579 return -1; 1580 } 1581 1582 #endif 1583 1584 static void __init bootmem_init_nonnuma(void) 1585 { 1586 unsigned long top_of_ram = memblock_end_of_DRAM(); 1587 unsigned long total_ram = memblock_phys_mem_size(); 1588 1589 numadbg("bootmem_init_nonnuma()\n"); 1590 1591 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1592 top_of_ram, total_ram); 1593 printk(KERN_INFO "Memory hole size: %ldMB\n", 1594 (top_of_ram - total_ram) >> 20); 1595 1596 init_node_masks_nonnuma(); 1597 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0); 1598 allocate_node_data(0); 1599 node_set_online(0); 1600 } 1601 1602 static unsigned long __init bootmem_init(unsigned long phys_base) 1603 { 1604 unsigned long end_pfn; 1605 1606 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1607 max_pfn = max_low_pfn = end_pfn; 1608 min_low_pfn = (phys_base >> PAGE_SHIFT); 1609 1610 if (bootmem_init_numa() < 0) 1611 bootmem_init_nonnuma(); 1612 1613 /* Dump memblock with node info. */ 1614 memblock_dump_all(); 1615 1616 /* XXX cpu notifier XXX */ 1617 1618 sparse_memory_present_with_active_regions(MAX_NUMNODES); 1619 sparse_init(); 1620 1621 return end_pfn; 1622 } 1623 1624 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1625 static int pall_ents __initdata; 1626 1627 static unsigned long max_phys_bits = 40; 1628 1629 bool kern_addr_valid(unsigned long addr) 1630 { 1631 pgd_t *pgd; 1632 p4d_t *p4d; 1633 pud_t *pud; 1634 pmd_t *pmd; 1635 pte_t *pte; 1636 1637 if ((long)addr < 0L) { 1638 unsigned long pa = __pa(addr); 1639 1640 if ((pa >> max_phys_bits) != 0UL) 1641 return false; 1642 1643 return pfn_valid(pa >> PAGE_SHIFT); 1644 } 1645 1646 if (addr >= (unsigned long) KERNBASE && 1647 addr < (unsigned long)&_end) 1648 return true; 1649 1650 pgd = pgd_offset_k(addr); 1651 if (pgd_none(*pgd)) 1652 return 0; 1653 1654 p4d = p4d_offset(pgd, addr); 1655 if (p4d_none(*p4d)) 1656 return 0; 1657 1658 pud = pud_offset(p4d, addr); 1659 if (pud_none(*pud)) 1660 return 0; 1661 1662 if (pud_large(*pud)) 1663 return pfn_valid(pud_pfn(*pud)); 1664 1665 pmd = pmd_offset(pud, addr); 1666 if (pmd_none(*pmd)) 1667 return 0; 1668 1669 if (pmd_large(*pmd)) 1670 return pfn_valid(pmd_pfn(*pmd)); 1671 1672 pte = pte_offset_kernel(pmd, addr); 1673 if (pte_none(*pte)) 1674 return 0; 1675 1676 return pfn_valid(pte_pfn(*pte)); 1677 } 1678 EXPORT_SYMBOL(kern_addr_valid); 1679 1680 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1681 unsigned long vend, 1682 pud_t *pud) 1683 { 1684 const unsigned long mask16gb = (1UL << 34) - 1UL; 1685 u64 pte_val = vstart; 1686 1687 /* Each PUD is 8GB */ 1688 if ((vstart & mask16gb) || 1689 (vend - vstart <= mask16gb)) { 1690 pte_val ^= kern_linear_pte_xor[2]; 1691 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1692 1693 return vstart + PUD_SIZE; 1694 } 1695 1696 pte_val ^= kern_linear_pte_xor[3]; 1697 pte_val |= _PAGE_PUD_HUGE; 1698 1699 vend = vstart + mask16gb + 1UL; 1700 while (vstart < vend) { 1701 pud_val(*pud) = pte_val; 1702 1703 pte_val += PUD_SIZE; 1704 vstart += PUD_SIZE; 1705 pud++; 1706 } 1707 return vstart; 1708 } 1709 1710 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1711 bool guard) 1712 { 1713 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1714 return true; 1715 1716 return false; 1717 } 1718 1719 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1720 unsigned long vend, 1721 pmd_t *pmd) 1722 { 1723 const unsigned long mask256mb = (1UL << 28) - 1UL; 1724 const unsigned long mask2gb = (1UL << 31) - 1UL; 1725 u64 pte_val = vstart; 1726 1727 /* Each PMD is 8MB */ 1728 if ((vstart & mask256mb) || 1729 (vend - vstart <= mask256mb)) { 1730 pte_val ^= kern_linear_pte_xor[0]; 1731 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1732 1733 return vstart + PMD_SIZE; 1734 } 1735 1736 if ((vstart & mask2gb) || 1737 (vend - vstart <= mask2gb)) { 1738 pte_val ^= kern_linear_pte_xor[1]; 1739 pte_val |= _PAGE_PMD_HUGE; 1740 vend = vstart + mask256mb + 1UL; 1741 } else { 1742 pte_val ^= kern_linear_pte_xor[2]; 1743 pte_val |= _PAGE_PMD_HUGE; 1744 vend = vstart + mask2gb + 1UL; 1745 } 1746 1747 while (vstart < vend) { 1748 pmd_val(*pmd) = pte_val; 1749 1750 pte_val += PMD_SIZE; 1751 vstart += PMD_SIZE; 1752 pmd++; 1753 } 1754 1755 return vstart; 1756 } 1757 1758 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1759 bool guard) 1760 { 1761 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1762 return true; 1763 1764 return false; 1765 } 1766 1767 static unsigned long __ref kernel_map_range(unsigned long pstart, 1768 unsigned long pend, pgprot_t prot, 1769 bool use_huge) 1770 { 1771 unsigned long vstart = PAGE_OFFSET + pstart; 1772 unsigned long vend = PAGE_OFFSET + pend; 1773 unsigned long alloc_bytes = 0UL; 1774 1775 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1776 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1777 vstart, vend); 1778 prom_halt(); 1779 } 1780 1781 while (vstart < vend) { 1782 unsigned long this_end, paddr = __pa(vstart); 1783 pgd_t *pgd = pgd_offset_k(vstart); 1784 p4d_t *p4d; 1785 pud_t *pud; 1786 pmd_t *pmd; 1787 pte_t *pte; 1788 1789 if (pgd_none(*pgd)) { 1790 pud_t *new; 1791 1792 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1793 PAGE_SIZE); 1794 if (!new) 1795 goto err_alloc; 1796 alloc_bytes += PAGE_SIZE; 1797 pgd_populate(&init_mm, pgd, new); 1798 } 1799 1800 p4d = p4d_offset(pgd, vstart); 1801 if (p4d_none(*p4d)) { 1802 pud_t *new; 1803 1804 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1805 PAGE_SIZE); 1806 if (!new) 1807 goto err_alloc; 1808 alloc_bytes += PAGE_SIZE; 1809 p4d_populate(&init_mm, p4d, new); 1810 } 1811 1812 pud = pud_offset(p4d, vstart); 1813 if (pud_none(*pud)) { 1814 pmd_t *new; 1815 1816 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1817 vstart = kernel_map_hugepud(vstart, vend, pud); 1818 continue; 1819 } 1820 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1821 PAGE_SIZE); 1822 if (!new) 1823 goto err_alloc; 1824 alloc_bytes += PAGE_SIZE; 1825 pud_populate(&init_mm, pud, new); 1826 } 1827 1828 pmd = pmd_offset(pud, vstart); 1829 if (pmd_none(*pmd)) { 1830 pte_t *new; 1831 1832 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1833 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1834 continue; 1835 } 1836 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1837 PAGE_SIZE); 1838 if (!new) 1839 goto err_alloc; 1840 alloc_bytes += PAGE_SIZE; 1841 pmd_populate_kernel(&init_mm, pmd, new); 1842 } 1843 1844 pte = pte_offset_kernel(pmd, vstart); 1845 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1846 if (this_end > vend) 1847 this_end = vend; 1848 1849 while (vstart < this_end) { 1850 pte_val(*pte) = (paddr | pgprot_val(prot)); 1851 1852 vstart += PAGE_SIZE; 1853 paddr += PAGE_SIZE; 1854 pte++; 1855 } 1856 } 1857 1858 return alloc_bytes; 1859 1860 err_alloc: 1861 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n", 1862 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1863 return -ENOMEM; 1864 } 1865 1866 static void __init flush_all_kernel_tsbs(void) 1867 { 1868 int i; 1869 1870 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1871 struct tsb *ent = &swapper_tsb[i]; 1872 1873 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1874 } 1875 #ifndef CONFIG_DEBUG_PAGEALLOC 1876 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1877 struct tsb *ent = &swapper_4m_tsb[i]; 1878 1879 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1880 } 1881 #endif 1882 } 1883 1884 extern unsigned int kvmap_linear_patch[1]; 1885 1886 static void __init kernel_physical_mapping_init(void) 1887 { 1888 unsigned long i, mem_alloced = 0UL; 1889 bool use_huge = true; 1890 1891 #ifdef CONFIG_DEBUG_PAGEALLOC 1892 use_huge = false; 1893 #endif 1894 for (i = 0; i < pall_ents; i++) { 1895 unsigned long phys_start, phys_end; 1896 1897 phys_start = pall[i].phys_addr; 1898 phys_end = phys_start + pall[i].reg_size; 1899 1900 mem_alloced += kernel_map_range(phys_start, phys_end, 1901 PAGE_KERNEL, use_huge); 1902 } 1903 1904 printk("Allocated %ld bytes for kernel page tables.\n", 1905 mem_alloced); 1906 1907 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1908 flushi(&kvmap_linear_patch[0]); 1909 1910 flush_all_kernel_tsbs(); 1911 1912 __flush_tlb_all(); 1913 } 1914 1915 #ifdef CONFIG_DEBUG_PAGEALLOC 1916 void __kernel_map_pages(struct page *page, int numpages, int enable) 1917 { 1918 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1919 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1920 1921 kernel_map_range(phys_start, phys_end, 1922 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1923 1924 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1925 PAGE_OFFSET + phys_end); 1926 1927 /* we should perform an IPI and flush all tlbs, 1928 * but that can deadlock->flush only current cpu. 1929 */ 1930 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1931 PAGE_OFFSET + phys_end); 1932 } 1933 #endif 1934 1935 unsigned long __init find_ecache_flush_span(unsigned long size) 1936 { 1937 int i; 1938 1939 for (i = 0; i < pavail_ents; i++) { 1940 if (pavail[i].reg_size >= size) 1941 return pavail[i].phys_addr; 1942 } 1943 1944 return ~0UL; 1945 } 1946 1947 unsigned long PAGE_OFFSET; 1948 EXPORT_SYMBOL(PAGE_OFFSET); 1949 1950 unsigned long VMALLOC_END = 0x0000010000000000UL; 1951 EXPORT_SYMBOL(VMALLOC_END); 1952 1953 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1954 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1955 1956 static void __init setup_page_offset(void) 1957 { 1958 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1959 /* Cheetah/Panther support a full 64-bit virtual 1960 * address, so we can use all that our page tables 1961 * support. 1962 */ 1963 sparc64_va_hole_top = 0xfff0000000000000UL; 1964 sparc64_va_hole_bottom = 0x0010000000000000UL; 1965 1966 max_phys_bits = 42; 1967 } else if (tlb_type == hypervisor) { 1968 switch (sun4v_chip_type) { 1969 case SUN4V_CHIP_NIAGARA1: 1970 case SUN4V_CHIP_NIAGARA2: 1971 /* T1 and T2 support 48-bit virtual addresses. */ 1972 sparc64_va_hole_top = 0xffff800000000000UL; 1973 sparc64_va_hole_bottom = 0x0000800000000000UL; 1974 1975 max_phys_bits = 39; 1976 break; 1977 case SUN4V_CHIP_NIAGARA3: 1978 /* T3 supports 48-bit virtual addresses. */ 1979 sparc64_va_hole_top = 0xffff800000000000UL; 1980 sparc64_va_hole_bottom = 0x0000800000000000UL; 1981 1982 max_phys_bits = 43; 1983 break; 1984 case SUN4V_CHIP_NIAGARA4: 1985 case SUN4V_CHIP_NIAGARA5: 1986 case SUN4V_CHIP_SPARC64X: 1987 case SUN4V_CHIP_SPARC_M6: 1988 /* T4 and later support 52-bit virtual addresses. */ 1989 sparc64_va_hole_top = 0xfff8000000000000UL; 1990 sparc64_va_hole_bottom = 0x0008000000000000UL; 1991 max_phys_bits = 47; 1992 break; 1993 case SUN4V_CHIP_SPARC_M7: 1994 case SUN4V_CHIP_SPARC_SN: 1995 /* M7 and later support 52-bit virtual addresses. */ 1996 sparc64_va_hole_top = 0xfff8000000000000UL; 1997 sparc64_va_hole_bottom = 0x0008000000000000UL; 1998 max_phys_bits = 49; 1999 break; 2000 case SUN4V_CHIP_SPARC_M8: 2001 default: 2002 /* M8 and later support 54-bit virtual addresses. 2003 * However, restricting M8 and above VA bits to 53 2004 * as 4-level page table cannot support more than 2005 * 53 VA bits. 2006 */ 2007 sparc64_va_hole_top = 0xfff0000000000000UL; 2008 sparc64_va_hole_bottom = 0x0010000000000000UL; 2009 max_phys_bits = 51; 2010 break; 2011 } 2012 } 2013 2014 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 2015 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 2016 max_phys_bits); 2017 prom_halt(); 2018 } 2019 2020 PAGE_OFFSET = sparc64_va_hole_top; 2021 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 2022 (sparc64_va_hole_bottom >> 2)); 2023 2024 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 2025 PAGE_OFFSET, max_phys_bits); 2026 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 2027 VMALLOC_START, VMALLOC_END); 2028 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 2029 VMEMMAP_BASE, VMEMMAP_BASE << 1); 2030 } 2031 2032 static void __init tsb_phys_patch(void) 2033 { 2034 struct tsb_ldquad_phys_patch_entry *pquad; 2035 struct tsb_phys_patch_entry *p; 2036 2037 pquad = &__tsb_ldquad_phys_patch; 2038 while (pquad < &__tsb_ldquad_phys_patch_end) { 2039 unsigned long addr = pquad->addr; 2040 2041 if (tlb_type == hypervisor) 2042 *(unsigned int *) addr = pquad->sun4v_insn; 2043 else 2044 *(unsigned int *) addr = pquad->sun4u_insn; 2045 wmb(); 2046 __asm__ __volatile__("flush %0" 2047 : /* no outputs */ 2048 : "r" (addr)); 2049 2050 pquad++; 2051 } 2052 2053 p = &__tsb_phys_patch; 2054 while (p < &__tsb_phys_patch_end) { 2055 unsigned long addr = p->addr; 2056 2057 *(unsigned int *) addr = p->insn; 2058 wmb(); 2059 __asm__ __volatile__("flush %0" 2060 : /* no outputs */ 2061 : "r" (addr)); 2062 2063 p++; 2064 } 2065 } 2066 2067 /* Don't mark as init, we give this to the Hypervisor. */ 2068 #ifndef CONFIG_DEBUG_PAGEALLOC 2069 #define NUM_KTSB_DESCR 2 2070 #else 2071 #define NUM_KTSB_DESCR 1 2072 #endif 2073 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 2074 2075 /* The swapper TSBs are loaded with a base sequence of: 2076 * 2077 * sethi %uhi(SYMBOL), REG1 2078 * sethi %hi(SYMBOL), REG2 2079 * or REG1, %ulo(SYMBOL), REG1 2080 * or REG2, %lo(SYMBOL), REG2 2081 * sllx REG1, 32, REG1 2082 * or REG1, REG2, REG1 2083 * 2084 * When we use physical addressing for the TSB accesses, we patch the 2085 * first four instructions in the above sequence. 2086 */ 2087 2088 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 2089 { 2090 unsigned long high_bits, low_bits; 2091 2092 high_bits = (pa >> 32) & 0xffffffff; 2093 low_bits = (pa >> 0) & 0xffffffff; 2094 2095 while (start < end) { 2096 unsigned int *ia = (unsigned int *)(unsigned long)*start; 2097 2098 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 2099 __asm__ __volatile__("flush %0" : : "r" (ia)); 2100 2101 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 2102 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 2103 2104 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 2105 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 2106 2107 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 2108 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 2109 2110 start++; 2111 } 2112 } 2113 2114 static void ktsb_phys_patch(void) 2115 { 2116 extern unsigned int __swapper_tsb_phys_patch; 2117 extern unsigned int __swapper_tsb_phys_patch_end; 2118 unsigned long ktsb_pa; 2119 2120 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2121 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2122 &__swapper_tsb_phys_patch_end, ktsb_pa); 2123 #ifndef CONFIG_DEBUG_PAGEALLOC 2124 { 2125 extern unsigned int __swapper_4m_tsb_phys_patch; 2126 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2127 ktsb_pa = (kern_base + 2128 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2129 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2130 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2131 } 2132 #endif 2133 } 2134 2135 static void __init sun4v_ktsb_init(void) 2136 { 2137 unsigned long ktsb_pa; 2138 2139 /* First KTSB for PAGE_SIZE mappings. */ 2140 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2141 2142 switch (PAGE_SIZE) { 2143 case 8 * 1024: 2144 default: 2145 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2146 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2147 break; 2148 2149 case 64 * 1024: 2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2152 break; 2153 2154 case 512 * 1024: 2155 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2156 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2157 break; 2158 2159 case 4 * 1024 * 1024: 2160 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2161 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2162 break; 2163 } 2164 2165 ktsb_descr[0].assoc = 1; 2166 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2167 ktsb_descr[0].ctx_idx = 0; 2168 ktsb_descr[0].tsb_base = ktsb_pa; 2169 ktsb_descr[0].resv = 0; 2170 2171 #ifndef CONFIG_DEBUG_PAGEALLOC 2172 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2173 ktsb_pa = (kern_base + 2174 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2175 2176 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2177 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2178 HV_PGSZ_MASK_256MB | 2179 HV_PGSZ_MASK_2GB | 2180 HV_PGSZ_MASK_16GB) & 2181 cpu_pgsz_mask); 2182 ktsb_descr[1].assoc = 1; 2183 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2184 ktsb_descr[1].ctx_idx = 0; 2185 ktsb_descr[1].tsb_base = ktsb_pa; 2186 ktsb_descr[1].resv = 0; 2187 #endif 2188 } 2189 2190 void sun4v_ktsb_register(void) 2191 { 2192 unsigned long pa, ret; 2193 2194 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2195 2196 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2197 if (ret != 0) { 2198 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2199 "errors with %lx\n", pa, ret); 2200 prom_halt(); 2201 } 2202 } 2203 2204 static void __init sun4u_linear_pte_xor_finalize(void) 2205 { 2206 #ifndef CONFIG_DEBUG_PAGEALLOC 2207 /* This is where we would add Panther support for 2208 * 32MB and 256MB pages. 2209 */ 2210 #endif 2211 } 2212 2213 static void __init sun4v_linear_pte_xor_finalize(void) 2214 { 2215 unsigned long pagecv_flag; 2216 2217 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2218 * enables MCD error. Do not set bit 9 on M7 processor. 2219 */ 2220 switch (sun4v_chip_type) { 2221 case SUN4V_CHIP_SPARC_M7: 2222 case SUN4V_CHIP_SPARC_M8: 2223 case SUN4V_CHIP_SPARC_SN: 2224 pagecv_flag = 0x00; 2225 break; 2226 default: 2227 pagecv_flag = _PAGE_CV_4V; 2228 break; 2229 } 2230 #ifndef CONFIG_DEBUG_PAGEALLOC 2231 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2232 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2233 PAGE_OFFSET; 2234 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2235 _PAGE_P_4V | _PAGE_W_4V); 2236 } else { 2237 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2238 } 2239 2240 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2241 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2242 PAGE_OFFSET; 2243 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2244 _PAGE_P_4V | _PAGE_W_4V); 2245 } else { 2246 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2247 } 2248 2249 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2250 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2251 PAGE_OFFSET; 2252 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2253 _PAGE_P_4V | _PAGE_W_4V); 2254 } else { 2255 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2256 } 2257 #endif 2258 } 2259 2260 /* paging_init() sets up the page tables */ 2261 2262 static unsigned long last_valid_pfn; 2263 2264 static void sun4u_pgprot_init(void); 2265 static void sun4v_pgprot_init(void); 2266 2267 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2268 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2269 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2270 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2271 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2272 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2273 2274 /* We need to exclude reserved regions. This exclusion will include 2275 * vmlinux and initrd. To be more precise the initrd size could be used to 2276 * compute a new lower limit because it is freed later during initialization. 2277 */ 2278 static void __init reduce_memory(phys_addr_t limit_ram) 2279 { 2280 limit_ram += memblock_reserved_size(); 2281 memblock_enforce_memory_limit(limit_ram); 2282 } 2283 2284 void __init paging_init(void) 2285 { 2286 unsigned long end_pfn, shift, phys_base; 2287 unsigned long real_end, i; 2288 2289 setup_page_offset(); 2290 2291 /* These build time checkes make sure that the dcache_dirty_cpu() 2292 * page->flags usage will work. 2293 * 2294 * When a page gets marked as dcache-dirty, we store the 2295 * cpu number starting at bit 32 in the page->flags. Also, 2296 * functions like clear_dcache_dirty_cpu use the cpu mask 2297 * in 13-bit signed-immediate instruction fields. 2298 */ 2299 2300 /* 2301 * Page flags must not reach into upper 32 bits that are used 2302 * for the cpu number 2303 */ 2304 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2305 2306 /* 2307 * The bit fields placed in the high range must not reach below 2308 * the 32 bit boundary. Otherwise we cannot place the cpu field 2309 * at the 32 bit boundary. 2310 */ 2311 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2312 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2313 2314 BUILD_BUG_ON(NR_CPUS > 4096); 2315 2316 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2317 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2318 2319 /* Invalidate both kernel TSBs. */ 2320 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2321 #ifndef CONFIG_DEBUG_PAGEALLOC 2322 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2323 #endif 2324 2325 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2326 * bit on M7 processor. This is a conflicting usage of the same 2327 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2328 * Detection error on all pages and this will lead to problems 2329 * later. Kernel does not run with MCD enabled and hence rest 2330 * of the required steps to fully configure memory corruption 2331 * detection are not taken. We need to ensure TTE.mcde is not 2332 * set on M7 processor. Compute the value of cacheability 2333 * flag for use later taking this into consideration. 2334 */ 2335 switch (sun4v_chip_type) { 2336 case SUN4V_CHIP_SPARC_M7: 2337 case SUN4V_CHIP_SPARC_M8: 2338 case SUN4V_CHIP_SPARC_SN: 2339 page_cache4v_flag = _PAGE_CP_4V; 2340 break; 2341 default: 2342 page_cache4v_flag = _PAGE_CACHE_4V; 2343 break; 2344 } 2345 2346 if (tlb_type == hypervisor) 2347 sun4v_pgprot_init(); 2348 else 2349 sun4u_pgprot_init(); 2350 2351 if (tlb_type == cheetah_plus || 2352 tlb_type == hypervisor) { 2353 tsb_phys_patch(); 2354 ktsb_phys_patch(); 2355 } 2356 2357 if (tlb_type == hypervisor) 2358 sun4v_patch_tlb_handlers(); 2359 2360 /* Find available physical memory... 2361 * 2362 * Read it twice in order to work around a bug in openfirmware. 2363 * The call to grab this table itself can cause openfirmware to 2364 * allocate memory, which in turn can take away some space from 2365 * the list of available memory. Reading it twice makes sure 2366 * we really do get the final value. 2367 */ 2368 read_obp_translations(); 2369 read_obp_memory("reg", &pall[0], &pall_ents); 2370 read_obp_memory("available", &pavail[0], &pavail_ents); 2371 read_obp_memory("available", &pavail[0], &pavail_ents); 2372 2373 phys_base = 0xffffffffffffffffUL; 2374 for (i = 0; i < pavail_ents; i++) { 2375 phys_base = min(phys_base, pavail[i].phys_addr); 2376 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2377 } 2378 2379 memblock_reserve(kern_base, kern_size); 2380 2381 find_ramdisk(phys_base); 2382 2383 if (cmdline_memory_size) 2384 reduce_memory(cmdline_memory_size); 2385 2386 memblock_allow_resize(); 2387 memblock_dump_all(); 2388 2389 set_bit(0, mmu_context_bmap); 2390 2391 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2392 2393 real_end = (unsigned long)_end; 2394 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2395 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2396 num_kernel_image_mappings); 2397 2398 /* Set kernel pgd to upper alias so physical page computations 2399 * work. 2400 */ 2401 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2402 2403 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2404 2405 inherit_prom_mappings(); 2406 2407 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2408 setup_tba(); 2409 2410 __flush_tlb_all(); 2411 2412 prom_build_devicetree(); 2413 of_populate_present_mask(); 2414 #ifndef CONFIG_SMP 2415 of_fill_in_cpu_data(); 2416 #endif 2417 2418 if (tlb_type == hypervisor) { 2419 sun4v_mdesc_init(); 2420 mdesc_populate_present_mask(cpu_all_mask); 2421 #ifndef CONFIG_SMP 2422 mdesc_fill_in_cpu_data(cpu_all_mask); 2423 #endif 2424 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2425 2426 sun4v_linear_pte_xor_finalize(); 2427 2428 sun4v_ktsb_init(); 2429 sun4v_ktsb_register(); 2430 } else { 2431 unsigned long impl, ver; 2432 2433 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2434 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2435 2436 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2437 impl = ((ver >> 32) & 0xffff); 2438 if (impl == PANTHER_IMPL) 2439 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2440 HV_PGSZ_MASK_256MB); 2441 2442 sun4u_linear_pte_xor_finalize(); 2443 } 2444 2445 /* Flush the TLBs and the 4M TSB so that the updated linear 2446 * pte XOR settings are realized for all mappings. 2447 */ 2448 __flush_tlb_all(); 2449 #ifndef CONFIG_DEBUG_PAGEALLOC 2450 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2451 #endif 2452 __flush_tlb_all(); 2453 2454 /* Setup bootmem... */ 2455 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2456 2457 kernel_physical_mapping_init(); 2458 2459 { 2460 unsigned long max_zone_pfns[MAX_NR_ZONES]; 2461 2462 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 2463 2464 max_zone_pfns[ZONE_NORMAL] = end_pfn; 2465 2466 free_area_init(max_zone_pfns); 2467 } 2468 2469 printk("Booting Linux...\n"); 2470 } 2471 2472 int page_in_phys_avail(unsigned long paddr) 2473 { 2474 int i; 2475 2476 paddr &= PAGE_MASK; 2477 2478 for (i = 0; i < pavail_ents; i++) { 2479 unsigned long start, end; 2480 2481 start = pavail[i].phys_addr; 2482 end = start + pavail[i].reg_size; 2483 2484 if (paddr >= start && paddr < end) 2485 return 1; 2486 } 2487 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2488 return 1; 2489 #ifdef CONFIG_BLK_DEV_INITRD 2490 if (paddr >= __pa(initrd_start) && 2491 paddr < __pa(PAGE_ALIGN(initrd_end))) 2492 return 1; 2493 #endif 2494 2495 return 0; 2496 } 2497 2498 static void __init register_page_bootmem_info(void) 2499 { 2500 #ifdef CONFIG_NEED_MULTIPLE_NODES 2501 int i; 2502 2503 for_each_online_node(i) 2504 if (NODE_DATA(i)->node_spanned_pages) 2505 register_page_bootmem_info_node(NODE_DATA(i)); 2506 #endif 2507 } 2508 void __init mem_init(void) 2509 { 2510 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 2511 2512 memblock_free_all(); 2513 2514 /* 2515 * Must be done after boot memory is put on freelist, because here we 2516 * might set fields in deferred struct pages that have not yet been 2517 * initialized, and memblock_free_all() initializes all the reserved 2518 * deferred pages for us. 2519 */ 2520 register_page_bootmem_info(); 2521 2522 /* 2523 * Set up the zero page, mark it reserved, so that page count 2524 * is not manipulated when freeing the page from user ptes. 2525 */ 2526 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 2527 if (mem_map_zero == NULL) { 2528 prom_printf("paging_init: Cannot alloc zero page.\n"); 2529 prom_halt(); 2530 } 2531 mark_page_reserved(mem_map_zero); 2532 2533 mem_init_print_info(NULL); 2534 2535 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2536 cheetah_ecache_flush_init(); 2537 } 2538 2539 void free_initmem(void) 2540 { 2541 unsigned long addr, initend; 2542 int do_free = 1; 2543 2544 /* If the physical memory maps were trimmed by kernel command 2545 * line options, don't even try freeing this initmem stuff up. 2546 * The kernel image could have been in the trimmed out region 2547 * and if so the freeing below will free invalid page structs. 2548 */ 2549 if (cmdline_memory_size) 2550 do_free = 0; 2551 2552 /* 2553 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2554 */ 2555 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2556 initend = (unsigned long)(__init_end) & PAGE_MASK; 2557 for (; addr < initend; addr += PAGE_SIZE) { 2558 unsigned long page; 2559 2560 page = (addr + 2561 ((unsigned long) __va(kern_base)) - 2562 ((unsigned long) KERNBASE)); 2563 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2564 2565 if (do_free) 2566 free_reserved_page(virt_to_page(page)); 2567 } 2568 } 2569 2570 pgprot_t PAGE_KERNEL __read_mostly; 2571 EXPORT_SYMBOL(PAGE_KERNEL); 2572 2573 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2574 pgprot_t PAGE_COPY __read_mostly; 2575 2576 pgprot_t PAGE_SHARED __read_mostly; 2577 EXPORT_SYMBOL(PAGE_SHARED); 2578 2579 unsigned long pg_iobits __read_mostly; 2580 2581 unsigned long _PAGE_IE __read_mostly; 2582 EXPORT_SYMBOL(_PAGE_IE); 2583 2584 unsigned long _PAGE_E __read_mostly; 2585 EXPORT_SYMBOL(_PAGE_E); 2586 2587 unsigned long _PAGE_CACHE __read_mostly; 2588 EXPORT_SYMBOL(_PAGE_CACHE); 2589 2590 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2591 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2592 int node, struct vmem_altmap *altmap) 2593 { 2594 unsigned long pte_base; 2595 2596 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2597 _PAGE_CP_4U | _PAGE_CV_4U | 2598 _PAGE_P_4U | _PAGE_W_4U); 2599 if (tlb_type == hypervisor) 2600 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2601 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2602 2603 pte_base |= _PAGE_PMD_HUGE; 2604 2605 vstart = vstart & PMD_MASK; 2606 vend = ALIGN(vend, PMD_SIZE); 2607 for (; vstart < vend; vstart += PMD_SIZE) { 2608 pgd_t *pgd = vmemmap_pgd_populate(vstart, node); 2609 unsigned long pte; 2610 p4d_t *p4d; 2611 pud_t *pud; 2612 pmd_t *pmd; 2613 2614 if (!pgd) 2615 return -ENOMEM; 2616 2617 p4d = vmemmap_p4d_populate(pgd, vstart, node); 2618 if (!p4d) 2619 return -ENOMEM; 2620 2621 pud = vmemmap_pud_populate(p4d, vstart, node); 2622 if (!pud) 2623 return -ENOMEM; 2624 2625 pmd = pmd_offset(pud, vstart); 2626 pte = pmd_val(*pmd); 2627 if (!(pte & _PAGE_VALID)) { 2628 void *block = vmemmap_alloc_block(PMD_SIZE, node); 2629 2630 if (!block) 2631 return -ENOMEM; 2632 2633 pmd_val(*pmd) = pte_base | __pa(block); 2634 } 2635 } 2636 2637 return 0; 2638 } 2639 2640 void vmemmap_free(unsigned long start, unsigned long end, 2641 struct vmem_altmap *altmap) 2642 { 2643 } 2644 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2645 2646 static void prot_init_common(unsigned long page_none, 2647 unsigned long page_shared, 2648 unsigned long page_copy, 2649 unsigned long page_readonly, 2650 unsigned long page_exec_bit) 2651 { 2652 PAGE_COPY = __pgprot(page_copy); 2653 PAGE_SHARED = __pgprot(page_shared); 2654 2655 protection_map[0x0] = __pgprot(page_none); 2656 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2657 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2658 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2659 protection_map[0x4] = __pgprot(page_readonly); 2660 protection_map[0x5] = __pgprot(page_readonly); 2661 protection_map[0x6] = __pgprot(page_copy); 2662 protection_map[0x7] = __pgprot(page_copy); 2663 protection_map[0x8] = __pgprot(page_none); 2664 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2665 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2666 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2667 protection_map[0xc] = __pgprot(page_readonly); 2668 protection_map[0xd] = __pgprot(page_readonly); 2669 protection_map[0xe] = __pgprot(page_shared); 2670 protection_map[0xf] = __pgprot(page_shared); 2671 } 2672 2673 static void __init sun4u_pgprot_init(void) 2674 { 2675 unsigned long page_none, page_shared, page_copy, page_readonly; 2676 unsigned long page_exec_bit; 2677 int i; 2678 2679 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2680 _PAGE_CACHE_4U | _PAGE_P_4U | 2681 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2682 _PAGE_EXEC_4U); 2683 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2684 _PAGE_CACHE_4U | _PAGE_P_4U | 2685 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2686 _PAGE_EXEC_4U | _PAGE_L_4U); 2687 2688 _PAGE_IE = _PAGE_IE_4U; 2689 _PAGE_E = _PAGE_E_4U; 2690 _PAGE_CACHE = _PAGE_CACHE_4U; 2691 2692 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2693 __ACCESS_BITS_4U | _PAGE_E_4U); 2694 2695 #ifdef CONFIG_DEBUG_PAGEALLOC 2696 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2697 #else 2698 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2699 PAGE_OFFSET; 2700 #endif 2701 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2702 _PAGE_P_4U | _PAGE_W_4U); 2703 2704 for (i = 1; i < 4; i++) 2705 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2706 2707 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2708 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2709 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2710 2711 2712 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2713 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2714 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2715 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2716 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2717 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2718 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2719 2720 page_exec_bit = _PAGE_EXEC_4U; 2721 2722 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2723 page_exec_bit); 2724 } 2725 2726 static void __init sun4v_pgprot_init(void) 2727 { 2728 unsigned long page_none, page_shared, page_copy, page_readonly; 2729 unsigned long page_exec_bit; 2730 int i; 2731 2732 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2733 page_cache4v_flag | _PAGE_P_4V | 2734 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2735 _PAGE_EXEC_4V); 2736 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2737 2738 _PAGE_IE = _PAGE_IE_4V; 2739 _PAGE_E = _PAGE_E_4V; 2740 _PAGE_CACHE = page_cache4v_flag; 2741 2742 #ifdef CONFIG_DEBUG_PAGEALLOC 2743 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2744 #else 2745 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2746 PAGE_OFFSET; 2747 #endif 2748 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2749 _PAGE_W_4V); 2750 2751 for (i = 1; i < 4; i++) 2752 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2753 2754 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2755 __ACCESS_BITS_4V | _PAGE_E_4V); 2756 2757 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2758 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2759 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2760 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2761 2762 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2763 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2764 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2765 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2766 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2767 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2768 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2769 2770 page_exec_bit = _PAGE_EXEC_4V; 2771 2772 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2773 page_exec_bit); 2774 } 2775 2776 unsigned long pte_sz_bits(unsigned long sz) 2777 { 2778 if (tlb_type == hypervisor) { 2779 switch (sz) { 2780 case 8 * 1024: 2781 default: 2782 return _PAGE_SZ8K_4V; 2783 case 64 * 1024: 2784 return _PAGE_SZ64K_4V; 2785 case 512 * 1024: 2786 return _PAGE_SZ512K_4V; 2787 case 4 * 1024 * 1024: 2788 return _PAGE_SZ4MB_4V; 2789 } 2790 } else { 2791 switch (sz) { 2792 case 8 * 1024: 2793 default: 2794 return _PAGE_SZ8K_4U; 2795 case 64 * 1024: 2796 return _PAGE_SZ64K_4U; 2797 case 512 * 1024: 2798 return _PAGE_SZ512K_4U; 2799 case 4 * 1024 * 1024: 2800 return _PAGE_SZ4MB_4U; 2801 } 2802 } 2803 } 2804 2805 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2806 { 2807 pte_t pte; 2808 2809 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2810 pte_val(pte) |= (((unsigned long)space) << 32); 2811 pte_val(pte) |= pte_sz_bits(page_size); 2812 2813 return pte; 2814 } 2815 2816 static unsigned long kern_large_tte(unsigned long paddr) 2817 { 2818 unsigned long val; 2819 2820 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2821 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2822 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2823 if (tlb_type == hypervisor) 2824 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2825 page_cache4v_flag | _PAGE_P_4V | 2826 _PAGE_EXEC_4V | _PAGE_W_4V); 2827 2828 return val | paddr; 2829 } 2830 2831 /* If not locked, zap it. */ 2832 void __flush_tlb_all(void) 2833 { 2834 unsigned long pstate; 2835 int i; 2836 2837 __asm__ __volatile__("flushw\n\t" 2838 "rdpr %%pstate, %0\n\t" 2839 "wrpr %0, %1, %%pstate" 2840 : "=r" (pstate) 2841 : "i" (PSTATE_IE)); 2842 if (tlb_type == hypervisor) { 2843 sun4v_mmu_demap_all(); 2844 } else if (tlb_type == spitfire) { 2845 for (i = 0; i < 64; i++) { 2846 /* Spitfire Errata #32 workaround */ 2847 /* NOTE: Always runs on spitfire, so no 2848 * cheetah+ page size encodings. 2849 */ 2850 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2851 "flush %%g6" 2852 : /* No outputs */ 2853 : "r" (0), 2854 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2855 2856 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2857 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2858 "membar #Sync" 2859 : /* no outputs */ 2860 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2861 spitfire_put_dtlb_data(i, 0x0UL); 2862 } 2863 2864 /* Spitfire Errata #32 workaround */ 2865 /* NOTE: Always runs on spitfire, so no 2866 * cheetah+ page size encodings. 2867 */ 2868 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2869 "flush %%g6" 2870 : /* No outputs */ 2871 : "r" (0), 2872 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2873 2874 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2875 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2876 "membar #Sync" 2877 : /* no outputs */ 2878 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2879 spitfire_put_itlb_data(i, 0x0UL); 2880 } 2881 } 2882 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2883 cheetah_flush_dtlb_all(); 2884 cheetah_flush_itlb_all(); 2885 } 2886 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2887 : : "r" (pstate)); 2888 } 2889 2890 pte_t *pte_alloc_one_kernel(struct mm_struct *mm) 2891 { 2892 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 2893 pte_t *pte = NULL; 2894 2895 if (page) 2896 pte = (pte_t *) page_address(page); 2897 2898 return pte; 2899 } 2900 2901 pgtable_t pte_alloc_one(struct mm_struct *mm) 2902 { 2903 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 2904 if (!page) 2905 return NULL; 2906 if (!pgtable_pte_page_ctor(page)) { 2907 free_unref_page(page); 2908 return NULL; 2909 } 2910 return (pte_t *) page_address(page); 2911 } 2912 2913 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2914 { 2915 free_page((unsigned long)pte); 2916 } 2917 2918 static void __pte_free(pgtable_t pte) 2919 { 2920 struct page *page = virt_to_page(pte); 2921 2922 pgtable_pte_page_dtor(page); 2923 __free_page(page); 2924 } 2925 2926 void pte_free(struct mm_struct *mm, pgtable_t pte) 2927 { 2928 __pte_free(pte); 2929 } 2930 2931 void pgtable_free(void *table, bool is_page) 2932 { 2933 if (is_page) 2934 __pte_free(table); 2935 else 2936 kmem_cache_free(pgtable_cache, table); 2937 } 2938 2939 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2940 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2941 pmd_t *pmd) 2942 { 2943 unsigned long pte, flags; 2944 struct mm_struct *mm; 2945 pmd_t entry = *pmd; 2946 2947 if (!pmd_large(entry) || !pmd_young(entry)) 2948 return; 2949 2950 pte = pmd_val(entry); 2951 2952 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2953 if (!(pte & _PAGE_VALID)) 2954 return; 2955 2956 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2957 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2958 2959 mm = vma->vm_mm; 2960 2961 spin_lock_irqsave(&mm->context.lock, flags); 2962 2963 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 2964 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 2965 addr, pte); 2966 2967 spin_unlock_irqrestore(&mm->context.lock, flags); 2968 } 2969 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 2970 2971 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 2972 static void context_reload(void *__data) 2973 { 2974 struct mm_struct *mm = __data; 2975 2976 if (mm == current->mm) 2977 load_secondary_context(mm); 2978 } 2979 2980 void hugetlb_setup(struct pt_regs *regs) 2981 { 2982 struct mm_struct *mm = current->mm; 2983 struct tsb_config *tp; 2984 2985 if (faulthandler_disabled() || !mm) { 2986 const struct exception_table_entry *entry; 2987 2988 entry = search_exception_tables(regs->tpc); 2989 if (entry) { 2990 regs->tpc = entry->fixup; 2991 regs->tnpc = regs->tpc + 4; 2992 return; 2993 } 2994 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 2995 die_if_kernel("HugeTSB in atomic", regs); 2996 } 2997 2998 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 2999 if (likely(tp->tsb == NULL)) 3000 tsb_grow(mm, MM_TSB_HUGE, 0); 3001 3002 tsb_context_switch(mm); 3003 smp_tsb_sync(mm); 3004 3005 /* On UltraSPARC-III+ and later, configure the second half of 3006 * the Data-TLB for huge pages. 3007 */ 3008 if (tlb_type == cheetah_plus) { 3009 bool need_context_reload = false; 3010 unsigned long ctx; 3011 3012 spin_lock_irq(&ctx_alloc_lock); 3013 ctx = mm->context.sparc64_ctx_val; 3014 ctx &= ~CTX_PGSZ_MASK; 3015 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 3016 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 3017 3018 if (ctx != mm->context.sparc64_ctx_val) { 3019 /* When changing the page size fields, we 3020 * must perform a context flush so that no 3021 * stale entries match. This flush must 3022 * occur with the original context register 3023 * settings. 3024 */ 3025 do_flush_tlb_mm(mm); 3026 3027 /* Reload the context register of all processors 3028 * also executing in this address space. 3029 */ 3030 mm->context.sparc64_ctx_val = ctx; 3031 need_context_reload = true; 3032 } 3033 spin_unlock_irq(&ctx_alloc_lock); 3034 3035 if (need_context_reload) 3036 on_each_cpu(context_reload, mm, 0); 3037 } 3038 } 3039 #endif 3040 3041 static struct resource code_resource = { 3042 .name = "Kernel code", 3043 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3044 }; 3045 3046 static struct resource data_resource = { 3047 .name = "Kernel data", 3048 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3049 }; 3050 3051 static struct resource bss_resource = { 3052 .name = "Kernel bss", 3053 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3054 }; 3055 3056 static inline resource_size_t compute_kern_paddr(void *addr) 3057 { 3058 return (resource_size_t) (addr - KERNBASE + kern_base); 3059 } 3060 3061 static void __init kernel_lds_init(void) 3062 { 3063 code_resource.start = compute_kern_paddr(_text); 3064 code_resource.end = compute_kern_paddr(_etext - 1); 3065 data_resource.start = compute_kern_paddr(_etext); 3066 data_resource.end = compute_kern_paddr(_edata - 1); 3067 bss_resource.start = compute_kern_paddr(__bss_start); 3068 bss_resource.end = compute_kern_paddr(_end - 1); 3069 } 3070 3071 static int __init report_memory(void) 3072 { 3073 int i; 3074 struct resource *res; 3075 3076 kernel_lds_init(); 3077 3078 for (i = 0; i < pavail_ents; i++) { 3079 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 3080 3081 if (!res) { 3082 pr_warn("Failed to allocate source.\n"); 3083 break; 3084 } 3085 3086 res->name = "System RAM"; 3087 res->start = pavail[i].phys_addr; 3088 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3089 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3090 3091 if (insert_resource(&iomem_resource, res) < 0) { 3092 pr_warn("Resource insertion failed.\n"); 3093 break; 3094 } 3095 3096 insert_resource(res, &code_resource); 3097 insert_resource(res, &data_resource); 3098 insert_resource(res, &bss_resource); 3099 } 3100 3101 return 0; 3102 } 3103 arch_initcall(report_memory); 3104 3105 #ifdef CONFIG_SMP 3106 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3107 #else 3108 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3109 #endif 3110 3111 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3112 { 3113 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3114 if (start < LOW_OBP_ADDRESS) { 3115 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3116 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3117 } 3118 if (end > HI_OBP_ADDRESS) { 3119 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3120 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3121 } 3122 } else { 3123 flush_tsb_kernel_range(start, end); 3124 do_flush_tlb_kernel_range(start, end); 3125 } 3126 } 3127 3128 void copy_user_highpage(struct page *to, struct page *from, 3129 unsigned long vaddr, struct vm_area_struct *vma) 3130 { 3131 char *vfrom, *vto; 3132 3133 vfrom = kmap_atomic(from); 3134 vto = kmap_atomic(to); 3135 copy_user_page(vto, vfrom, vaddr, to); 3136 kunmap_atomic(vto); 3137 kunmap_atomic(vfrom); 3138 3139 /* If this page has ADI enabled, copy over any ADI tags 3140 * as well 3141 */ 3142 if (vma->vm_flags & VM_SPARC_ADI) { 3143 unsigned long pfrom, pto, i, adi_tag; 3144 3145 pfrom = page_to_phys(from); 3146 pto = page_to_phys(to); 3147 3148 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3149 asm volatile("ldxa [%1] %2, %0\n\t" 3150 : "=r" (adi_tag) 3151 : "r" (i), "i" (ASI_MCD_REAL)); 3152 asm volatile("stxa %0, [%1] %2\n\t" 3153 : 3154 : "r" (adi_tag), "r" (pto), 3155 "i" (ASI_MCD_REAL)); 3156 pto += adi_blksize(); 3157 } 3158 asm volatile("membar #Sync\n\t"); 3159 } 3160 } 3161 EXPORT_SYMBOL(copy_user_highpage); 3162 3163 void copy_highpage(struct page *to, struct page *from) 3164 { 3165 char *vfrom, *vto; 3166 3167 vfrom = kmap_atomic(from); 3168 vto = kmap_atomic(to); 3169 copy_page(vto, vfrom); 3170 kunmap_atomic(vto); 3171 kunmap_atomic(vfrom); 3172 3173 /* If this platform is ADI enabled, copy any ADI tags 3174 * as well 3175 */ 3176 if (adi_capable()) { 3177 unsigned long pfrom, pto, i, adi_tag; 3178 3179 pfrom = page_to_phys(from); 3180 pto = page_to_phys(to); 3181 3182 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3183 asm volatile("ldxa [%1] %2, %0\n\t" 3184 : "=r" (adi_tag) 3185 : "r" (i), "i" (ASI_MCD_REAL)); 3186 asm volatile("stxa %0, [%1] %2\n\t" 3187 : 3188 : "r" (adi_tag), "r" (pto), 3189 "i" (ASI_MCD_REAL)); 3190 pto += adi_blksize(); 3191 } 3192 asm volatile("membar #Sync\n\t"); 3193 } 3194 } 3195 EXPORT_SYMBOL(copy_highpage); 3196