xref: /openbmc/linux/arch/sparc/mm/init_64.c (revision 97da55fc)
1 /*
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7 
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/percpu.h>
26 #include <linux/memblock.h>
27 #include <linux/mmzone.h>
28 #include <linux/gfp.h>
29 
30 #include <asm/head.h>
31 #include <asm/page.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
36 #include <asm/io.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/dma.h>
41 #include <asm/starfire.h>
42 #include <asm/tlb.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
45 #include <asm/tsb.h>
46 #include <asm/hypervisor.h>
47 #include <asm/prom.h>
48 #include <asm/mdesc.h>
49 #include <asm/cpudata.h>
50 #include <asm/irq.h>
51 
52 #include "init_64.h"
53 
54 unsigned long kern_linear_pte_xor[4] __read_mostly;
55 
56 /* A bitmap, two bits for every 256MB of physical memory.  These two
57  * bits determine what page size we use for kernel linear
58  * translations.  They form an index into kern_linear_pte_xor[].  The
59  * value in the indexed slot is XOR'd with the TLB miss virtual
60  * address to form the resulting TTE.  The mapping is:
61  *
62  *	0	==>	4MB
63  *	1	==>	256MB
64  *	2	==>	2GB
65  *	3	==>	16GB
66  *
67  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
68  * support 2GB pages, and hopefully future cpus will support the 16GB
69  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
70  * if these larger page sizes are not supported by the cpu.
71  *
72  * It would be nice to determine this from the machine description
73  * 'cpu' properties, but we need to have this table setup before the
74  * MDESC is initialized.
75  */
76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
77 
78 #ifndef CONFIG_DEBUG_PAGEALLOC
79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
80  * Space is allocated for this right after the trap table in
81  * arch/sparc64/kernel/head.S
82  */
83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
84 #endif
85 
86 static unsigned long cpu_pgsz_mask;
87 
88 #define MAX_BANKS	32
89 
90 static struct linux_prom64_registers pavail[MAX_BANKS];
91 static int pavail_ents;
92 
93 static int cmp_p64(const void *a, const void *b)
94 {
95 	const struct linux_prom64_registers *x = a, *y = b;
96 
97 	if (x->phys_addr > y->phys_addr)
98 		return 1;
99 	if (x->phys_addr < y->phys_addr)
100 		return -1;
101 	return 0;
102 }
103 
104 static void __init read_obp_memory(const char *property,
105 				   struct linux_prom64_registers *regs,
106 				   int *num_ents)
107 {
108 	phandle node = prom_finddevice("/memory");
109 	int prop_size = prom_getproplen(node, property);
110 	int ents, ret, i;
111 
112 	ents = prop_size / sizeof(struct linux_prom64_registers);
113 	if (ents > MAX_BANKS) {
114 		prom_printf("The machine has more %s property entries than "
115 			    "this kernel can support (%d).\n",
116 			    property, MAX_BANKS);
117 		prom_halt();
118 	}
119 
120 	ret = prom_getproperty(node, property, (char *) regs, prop_size);
121 	if (ret == -1) {
122 		prom_printf("Couldn't get %s property from /memory.\n",
123 				property);
124 		prom_halt();
125 	}
126 
127 	/* Sanitize what we got from the firmware, by page aligning
128 	 * everything.
129 	 */
130 	for (i = 0; i < ents; i++) {
131 		unsigned long base, size;
132 
133 		base = regs[i].phys_addr;
134 		size = regs[i].reg_size;
135 
136 		size &= PAGE_MASK;
137 		if (base & ~PAGE_MASK) {
138 			unsigned long new_base = PAGE_ALIGN(base);
139 
140 			size -= new_base - base;
141 			if ((long) size < 0L)
142 				size = 0UL;
143 			base = new_base;
144 		}
145 		if (size == 0UL) {
146 			/* If it is empty, simply get rid of it.
147 			 * This simplifies the logic of the other
148 			 * functions that process these arrays.
149 			 */
150 			memmove(&regs[i], &regs[i + 1],
151 				(ents - i - 1) * sizeof(regs[0]));
152 			i--;
153 			ents--;
154 			continue;
155 		}
156 		regs[i].phys_addr = base;
157 		regs[i].reg_size = size;
158 	}
159 
160 	*num_ents = ents;
161 
162 	sort(regs, ents, sizeof(struct linux_prom64_registers),
163 	     cmp_p64, NULL);
164 }
165 
166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
167 					sizeof(unsigned long)];
168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
169 
170 /* Kernel physical address base and size in bytes.  */
171 unsigned long kern_base __read_mostly;
172 unsigned long kern_size __read_mostly;
173 
174 /* Initial ramdisk setup */
175 extern unsigned long sparc_ramdisk_image64;
176 extern unsigned int sparc_ramdisk_image;
177 extern unsigned int sparc_ramdisk_size;
178 
179 struct page *mem_map_zero __read_mostly;
180 EXPORT_SYMBOL(mem_map_zero);
181 
182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
183 
184 unsigned long sparc64_kern_pri_context __read_mostly;
185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186 unsigned long sparc64_kern_sec_context __read_mostly;
187 
188 int num_kernel_image_mappings;
189 
190 #ifdef CONFIG_DEBUG_DCFLUSH
191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
192 #ifdef CONFIG_SMP
193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
194 #endif
195 #endif
196 
197 inline void flush_dcache_page_impl(struct page *page)
198 {
199 	BUG_ON(tlb_type == hypervisor);
200 #ifdef CONFIG_DEBUG_DCFLUSH
201 	atomic_inc(&dcpage_flushes);
202 #endif
203 
204 #ifdef DCACHE_ALIASING_POSSIBLE
205 	__flush_dcache_page(page_address(page),
206 			    ((tlb_type == spitfire) &&
207 			     page_mapping(page) != NULL));
208 #else
209 	if (page_mapping(page) != NULL &&
210 	    tlb_type == spitfire)
211 		__flush_icache_page(__pa(page_address(page)));
212 #endif
213 }
214 
215 #define PG_dcache_dirty		PG_arch_1
216 #define PG_dcache_cpu_shift	32UL
217 #define PG_dcache_cpu_mask	\
218 	((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
219 
220 #define dcache_dirty_cpu(page) \
221 	(((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
222 
223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
224 {
225 	unsigned long mask = this_cpu;
226 	unsigned long non_cpu_bits;
227 
228 	non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229 	mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
230 
231 	__asm__ __volatile__("1:\n\t"
232 			     "ldx	[%2], %%g7\n\t"
233 			     "and	%%g7, %1, %%g1\n\t"
234 			     "or	%%g1, %0, %%g1\n\t"
235 			     "casx	[%2], %%g7, %%g1\n\t"
236 			     "cmp	%%g7, %%g1\n\t"
237 			     "bne,pn	%%xcc, 1b\n\t"
238 			     " nop"
239 			     : /* no outputs */
240 			     : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
241 			     : "g1", "g7");
242 }
243 
244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
245 {
246 	unsigned long mask = (1UL << PG_dcache_dirty);
247 
248 	__asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249 			     "1:\n\t"
250 			     "ldx	[%2], %%g7\n\t"
251 			     "srlx	%%g7, %4, %%g1\n\t"
252 			     "and	%%g1, %3, %%g1\n\t"
253 			     "cmp	%%g1, %0\n\t"
254 			     "bne,pn	%%icc, 2f\n\t"
255 			     " andn	%%g7, %1, %%g1\n\t"
256 			     "casx	[%2], %%g7, %%g1\n\t"
257 			     "cmp	%%g7, %%g1\n\t"
258 			     "bne,pn	%%xcc, 1b\n\t"
259 			     " nop\n"
260 			     "2:"
261 			     : /* no outputs */
262 			     : "r" (cpu), "r" (mask), "r" (&page->flags),
263 			       "i" (PG_dcache_cpu_mask),
264 			       "i" (PG_dcache_cpu_shift)
265 			     : "g1", "g7");
266 }
267 
268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269 {
270 	unsigned long tsb_addr = (unsigned long) ent;
271 
272 	if (tlb_type == cheetah_plus || tlb_type == hypervisor)
273 		tsb_addr = __pa(tsb_addr);
274 
275 	__tsb_insert(tsb_addr, tag, pte);
276 }
277 
278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279 
280 static void flush_dcache(unsigned long pfn)
281 {
282 	struct page *page;
283 
284 	page = pfn_to_page(pfn);
285 	if (page) {
286 		unsigned long pg_flags;
287 
288 		pg_flags = page->flags;
289 		if (pg_flags & (1UL << PG_dcache_dirty)) {
290 			int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291 				   PG_dcache_cpu_mask);
292 			int this_cpu = get_cpu();
293 
294 			/* This is just to optimize away some function calls
295 			 * in the SMP case.
296 			 */
297 			if (cpu == this_cpu)
298 				flush_dcache_page_impl(page);
299 			else
300 				smp_flush_dcache_page_impl(page, cpu);
301 
302 			clear_dcache_dirty_cpu(page, cpu);
303 
304 			put_cpu();
305 		}
306 	}
307 }
308 
309 /* mm->context.lock must be held */
310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
311 				    unsigned long tsb_hash_shift, unsigned long address,
312 				    unsigned long tte)
313 {
314 	struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
315 	unsigned long tag;
316 
317 	if (unlikely(!tsb))
318 		return;
319 
320 	tsb += ((address >> tsb_hash_shift) &
321 		(mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 	tag = (address >> 22UL);
323 	tsb_insert(tsb, tag, tte);
324 }
325 
326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
327 static inline bool is_hugetlb_pte(pte_t pte)
328 {
329 	if ((tlb_type == hypervisor &&
330 	     (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
331 	    (tlb_type != hypervisor &&
332 	     (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
333 		return true;
334 	return false;
335 }
336 #endif
337 
338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
339 {
340 	struct mm_struct *mm;
341 	unsigned long flags;
342 	pte_t pte = *ptep;
343 
344 	if (tlb_type != hypervisor) {
345 		unsigned long pfn = pte_pfn(pte);
346 
347 		if (pfn_valid(pfn))
348 			flush_dcache(pfn);
349 	}
350 
351 	mm = vma->vm_mm;
352 
353 	spin_lock_irqsave(&mm->context.lock, flags);
354 
355 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
356 	if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
357 		__update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
358 					address, pte_val(pte));
359 	else
360 #endif
361 		__update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
362 					address, pte_val(pte));
363 
364 	spin_unlock_irqrestore(&mm->context.lock, flags);
365 }
366 
367 void flush_dcache_page(struct page *page)
368 {
369 	struct address_space *mapping;
370 	int this_cpu;
371 
372 	if (tlb_type == hypervisor)
373 		return;
374 
375 	/* Do not bother with the expensive D-cache flush if it
376 	 * is merely the zero page.  The 'bigcore' testcase in GDB
377 	 * causes this case to run millions of times.
378 	 */
379 	if (page == ZERO_PAGE(0))
380 		return;
381 
382 	this_cpu = get_cpu();
383 
384 	mapping = page_mapping(page);
385 	if (mapping && !mapping_mapped(mapping)) {
386 		int dirty = test_bit(PG_dcache_dirty, &page->flags);
387 		if (dirty) {
388 			int dirty_cpu = dcache_dirty_cpu(page);
389 
390 			if (dirty_cpu == this_cpu)
391 				goto out;
392 			smp_flush_dcache_page_impl(page, dirty_cpu);
393 		}
394 		set_dcache_dirty(page, this_cpu);
395 	} else {
396 		/* We could delay the flush for the !page_mapping
397 		 * case too.  But that case is for exec env/arg
398 		 * pages and those are %99 certainly going to get
399 		 * faulted into the tlb (and thus flushed) anyways.
400 		 */
401 		flush_dcache_page_impl(page);
402 	}
403 
404 out:
405 	put_cpu();
406 }
407 EXPORT_SYMBOL(flush_dcache_page);
408 
409 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
410 {
411 	/* Cheetah and Hypervisor platform cpus have coherent I-cache. */
412 	if (tlb_type == spitfire) {
413 		unsigned long kaddr;
414 
415 		/* This code only runs on Spitfire cpus so this is
416 		 * why we can assume _PAGE_PADDR_4U.
417 		 */
418 		for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
419 			unsigned long paddr, mask = _PAGE_PADDR_4U;
420 
421 			if (kaddr >= PAGE_OFFSET)
422 				paddr = kaddr & mask;
423 			else {
424 				pgd_t *pgdp = pgd_offset_k(kaddr);
425 				pud_t *pudp = pud_offset(pgdp, kaddr);
426 				pmd_t *pmdp = pmd_offset(pudp, kaddr);
427 				pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
428 
429 				paddr = pte_val(*ptep) & mask;
430 			}
431 			__flush_icache_page(paddr);
432 		}
433 	}
434 }
435 EXPORT_SYMBOL(flush_icache_range);
436 
437 void mmu_info(struct seq_file *m)
438 {
439 	static const char *pgsz_strings[] = {
440 		"8K", "64K", "512K", "4MB", "32MB",
441 		"256MB", "2GB", "16GB",
442 	};
443 	int i, printed;
444 
445 	if (tlb_type == cheetah)
446 		seq_printf(m, "MMU Type\t: Cheetah\n");
447 	else if (tlb_type == cheetah_plus)
448 		seq_printf(m, "MMU Type\t: Cheetah+\n");
449 	else if (tlb_type == spitfire)
450 		seq_printf(m, "MMU Type\t: Spitfire\n");
451 	else if (tlb_type == hypervisor)
452 		seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
453 	else
454 		seq_printf(m, "MMU Type\t: ???\n");
455 
456 	seq_printf(m, "MMU PGSZs\t: ");
457 	printed = 0;
458 	for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
459 		if (cpu_pgsz_mask & (1UL << i)) {
460 			seq_printf(m, "%s%s",
461 				   printed ? "," : "", pgsz_strings[i]);
462 			printed++;
463 		}
464 	}
465 	seq_putc(m, '\n');
466 
467 #ifdef CONFIG_DEBUG_DCFLUSH
468 	seq_printf(m, "DCPageFlushes\t: %d\n",
469 		   atomic_read(&dcpage_flushes));
470 #ifdef CONFIG_SMP
471 	seq_printf(m, "DCPageFlushesXC\t: %d\n",
472 		   atomic_read(&dcpage_flushes_xcall));
473 #endif /* CONFIG_SMP */
474 #endif /* CONFIG_DEBUG_DCFLUSH */
475 }
476 
477 struct linux_prom_translation prom_trans[512] __read_mostly;
478 unsigned int prom_trans_ents __read_mostly;
479 
480 unsigned long kern_locked_tte_data;
481 
482 /* The obp translations are saved based on 8k pagesize, since obp can
483  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
484  * HI_OBP_ADDRESS range are handled in ktlb.S.
485  */
486 static inline int in_obp_range(unsigned long vaddr)
487 {
488 	return (vaddr >= LOW_OBP_ADDRESS &&
489 		vaddr < HI_OBP_ADDRESS);
490 }
491 
492 static int cmp_ptrans(const void *a, const void *b)
493 {
494 	const struct linux_prom_translation *x = a, *y = b;
495 
496 	if (x->virt > y->virt)
497 		return 1;
498 	if (x->virt < y->virt)
499 		return -1;
500 	return 0;
501 }
502 
503 /* Read OBP translations property into 'prom_trans[]'.  */
504 static void __init read_obp_translations(void)
505 {
506 	int n, node, ents, first, last, i;
507 
508 	node = prom_finddevice("/virtual-memory");
509 	n = prom_getproplen(node, "translations");
510 	if (unlikely(n == 0 || n == -1)) {
511 		prom_printf("prom_mappings: Couldn't get size.\n");
512 		prom_halt();
513 	}
514 	if (unlikely(n > sizeof(prom_trans))) {
515 		prom_printf("prom_mappings: Size %d is too big.\n", n);
516 		prom_halt();
517 	}
518 
519 	if ((n = prom_getproperty(node, "translations",
520 				  (char *)&prom_trans[0],
521 				  sizeof(prom_trans))) == -1) {
522 		prom_printf("prom_mappings: Couldn't get property.\n");
523 		prom_halt();
524 	}
525 
526 	n = n / sizeof(struct linux_prom_translation);
527 
528 	ents = n;
529 
530 	sort(prom_trans, ents, sizeof(struct linux_prom_translation),
531 	     cmp_ptrans, NULL);
532 
533 	/* Now kick out all the non-OBP entries.  */
534 	for (i = 0; i < ents; i++) {
535 		if (in_obp_range(prom_trans[i].virt))
536 			break;
537 	}
538 	first = i;
539 	for (; i < ents; i++) {
540 		if (!in_obp_range(prom_trans[i].virt))
541 			break;
542 	}
543 	last = i;
544 
545 	for (i = 0; i < (last - first); i++) {
546 		struct linux_prom_translation *src = &prom_trans[i + first];
547 		struct linux_prom_translation *dest = &prom_trans[i];
548 
549 		*dest = *src;
550 	}
551 	for (; i < ents; i++) {
552 		struct linux_prom_translation *dest = &prom_trans[i];
553 		dest->virt = dest->size = dest->data = 0x0UL;
554 	}
555 
556 	prom_trans_ents = last - first;
557 
558 	if (tlb_type == spitfire) {
559 		/* Clear diag TTE bits. */
560 		for (i = 0; i < prom_trans_ents; i++)
561 			prom_trans[i].data &= ~0x0003fe0000000000UL;
562 	}
563 
564 	/* Force execute bit on.  */
565 	for (i = 0; i < prom_trans_ents; i++)
566 		prom_trans[i].data |= (tlb_type == hypervisor ?
567 				       _PAGE_EXEC_4V : _PAGE_EXEC_4U);
568 }
569 
570 static void __init hypervisor_tlb_lock(unsigned long vaddr,
571 				       unsigned long pte,
572 				       unsigned long mmu)
573 {
574 	unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
575 
576 	if (ret != 0) {
577 		prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
578 			    "errors with %lx\n", vaddr, 0, pte, mmu, ret);
579 		prom_halt();
580 	}
581 }
582 
583 static unsigned long kern_large_tte(unsigned long paddr);
584 
585 static void __init remap_kernel(void)
586 {
587 	unsigned long phys_page, tte_vaddr, tte_data;
588 	int i, tlb_ent = sparc64_highest_locked_tlbent();
589 
590 	tte_vaddr = (unsigned long) KERNBASE;
591 	phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
592 	tte_data = kern_large_tte(phys_page);
593 
594 	kern_locked_tte_data = tte_data;
595 
596 	/* Now lock us into the TLBs via Hypervisor or OBP. */
597 	if (tlb_type == hypervisor) {
598 		for (i = 0; i < num_kernel_image_mappings; i++) {
599 			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
600 			hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
601 			tte_vaddr += 0x400000;
602 			tte_data += 0x400000;
603 		}
604 	} else {
605 		for (i = 0; i < num_kernel_image_mappings; i++) {
606 			prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
607 			prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
608 			tte_vaddr += 0x400000;
609 			tte_data += 0x400000;
610 		}
611 		sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
612 	}
613 	if (tlb_type == cheetah_plus) {
614 		sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
615 					    CTX_CHEETAH_PLUS_NUC);
616 		sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
617 		sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
618 	}
619 }
620 
621 
622 static void __init inherit_prom_mappings(void)
623 {
624 	/* Now fixup OBP's idea about where we really are mapped. */
625 	printk("Remapping the kernel... ");
626 	remap_kernel();
627 	printk("done.\n");
628 }
629 
630 void prom_world(int enter)
631 {
632 	if (!enter)
633 		set_fs(get_fs());
634 
635 	__asm__ __volatile__("flushw");
636 }
637 
638 void __flush_dcache_range(unsigned long start, unsigned long end)
639 {
640 	unsigned long va;
641 
642 	if (tlb_type == spitfire) {
643 		int n = 0;
644 
645 		for (va = start; va < end; va += 32) {
646 			spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
647 			if (++n >= 512)
648 				break;
649 		}
650 	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
651 		start = __pa(start);
652 		end = __pa(end);
653 		for (va = start; va < end; va += 32)
654 			__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
655 					     "membar #Sync"
656 					     : /* no outputs */
657 					     : "r" (va),
658 					       "i" (ASI_DCACHE_INVALIDATE));
659 	}
660 }
661 EXPORT_SYMBOL(__flush_dcache_range);
662 
663 /* get_new_mmu_context() uses "cache + 1".  */
664 DEFINE_SPINLOCK(ctx_alloc_lock);
665 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
666 #define MAX_CTX_NR	(1UL << CTX_NR_BITS)
667 #define CTX_BMAP_SLOTS	BITS_TO_LONGS(MAX_CTX_NR)
668 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
669 
670 /* Caller does TLB context flushing on local CPU if necessary.
671  * The caller also ensures that CTX_VALID(mm->context) is false.
672  *
673  * We must be careful about boundary cases so that we never
674  * let the user have CTX 0 (nucleus) or we ever use a CTX
675  * version of zero (and thus NO_CONTEXT would not be caught
676  * by version mis-match tests in mmu_context.h).
677  *
678  * Always invoked with interrupts disabled.
679  */
680 void get_new_mmu_context(struct mm_struct *mm)
681 {
682 	unsigned long ctx, new_ctx;
683 	unsigned long orig_pgsz_bits;
684 	unsigned long flags;
685 	int new_version;
686 
687 	spin_lock_irqsave(&ctx_alloc_lock, flags);
688 	orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
689 	ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
690 	new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
691 	new_version = 0;
692 	if (new_ctx >= (1 << CTX_NR_BITS)) {
693 		new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
694 		if (new_ctx >= ctx) {
695 			int i;
696 			new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
697 				CTX_FIRST_VERSION;
698 			if (new_ctx == 1)
699 				new_ctx = CTX_FIRST_VERSION;
700 
701 			/* Don't call memset, for 16 entries that's just
702 			 * plain silly...
703 			 */
704 			mmu_context_bmap[0] = 3;
705 			mmu_context_bmap[1] = 0;
706 			mmu_context_bmap[2] = 0;
707 			mmu_context_bmap[3] = 0;
708 			for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
709 				mmu_context_bmap[i + 0] = 0;
710 				mmu_context_bmap[i + 1] = 0;
711 				mmu_context_bmap[i + 2] = 0;
712 				mmu_context_bmap[i + 3] = 0;
713 			}
714 			new_version = 1;
715 			goto out;
716 		}
717 	}
718 	mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
719 	new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
720 out:
721 	tlb_context_cache = new_ctx;
722 	mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
723 	spin_unlock_irqrestore(&ctx_alloc_lock, flags);
724 
725 	if (unlikely(new_version))
726 		smp_new_mmu_context_version();
727 }
728 
729 static int numa_enabled = 1;
730 static int numa_debug;
731 
732 static int __init early_numa(char *p)
733 {
734 	if (!p)
735 		return 0;
736 
737 	if (strstr(p, "off"))
738 		numa_enabled = 0;
739 
740 	if (strstr(p, "debug"))
741 		numa_debug = 1;
742 
743 	return 0;
744 }
745 early_param("numa", early_numa);
746 
747 #define numadbg(f, a...) \
748 do {	if (numa_debug) \
749 		printk(KERN_INFO f, ## a); \
750 } while (0)
751 
752 static void __init find_ramdisk(unsigned long phys_base)
753 {
754 #ifdef CONFIG_BLK_DEV_INITRD
755 	if (sparc_ramdisk_image || sparc_ramdisk_image64) {
756 		unsigned long ramdisk_image;
757 
758 		/* Older versions of the bootloader only supported a
759 		 * 32-bit physical address for the ramdisk image
760 		 * location, stored at sparc_ramdisk_image.  Newer
761 		 * SILO versions set sparc_ramdisk_image to zero and
762 		 * provide a full 64-bit physical address at
763 		 * sparc_ramdisk_image64.
764 		 */
765 		ramdisk_image = sparc_ramdisk_image;
766 		if (!ramdisk_image)
767 			ramdisk_image = sparc_ramdisk_image64;
768 
769 		/* Another bootloader quirk.  The bootloader normalizes
770 		 * the physical address to KERNBASE, so we have to
771 		 * factor that back out and add in the lowest valid
772 		 * physical page address to get the true physical address.
773 		 */
774 		ramdisk_image -= KERNBASE;
775 		ramdisk_image += phys_base;
776 
777 		numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
778 			ramdisk_image, sparc_ramdisk_size);
779 
780 		initrd_start = ramdisk_image;
781 		initrd_end = ramdisk_image + sparc_ramdisk_size;
782 
783 		memblock_reserve(initrd_start, sparc_ramdisk_size);
784 
785 		initrd_start += PAGE_OFFSET;
786 		initrd_end += PAGE_OFFSET;
787 	}
788 #endif
789 }
790 
791 struct node_mem_mask {
792 	unsigned long mask;
793 	unsigned long val;
794 };
795 static struct node_mem_mask node_masks[MAX_NUMNODES];
796 static int num_node_masks;
797 
798 int numa_cpu_lookup_table[NR_CPUS];
799 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
800 
801 #ifdef CONFIG_NEED_MULTIPLE_NODES
802 
803 struct mdesc_mblock {
804 	u64	base;
805 	u64	size;
806 	u64	offset; /* RA-to-PA */
807 };
808 static struct mdesc_mblock *mblocks;
809 static int num_mblocks;
810 
811 static unsigned long ra_to_pa(unsigned long addr)
812 {
813 	int i;
814 
815 	for (i = 0; i < num_mblocks; i++) {
816 		struct mdesc_mblock *m = &mblocks[i];
817 
818 		if (addr >= m->base &&
819 		    addr < (m->base + m->size)) {
820 			addr += m->offset;
821 			break;
822 		}
823 	}
824 	return addr;
825 }
826 
827 static int find_node(unsigned long addr)
828 {
829 	int i;
830 
831 	addr = ra_to_pa(addr);
832 	for (i = 0; i < num_node_masks; i++) {
833 		struct node_mem_mask *p = &node_masks[i];
834 
835 		if ((addr & p->mask) == p->val)
836 			return i;
837 	}
838 	return -1;
839 }
840 
841 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
842 {
843 	*nid = find_node(start);
844 	start += PAGE_SIZE;
845 	while (start < end) {
846 		int n = find_node(start);
847 
848 		if (n != *nid)
849 			break;
850 		start += PAGE_SIZE;
851 	}
852 
853 	if (start > end)
854 		start = end;
855 
856 	return start;
857 }
858 #endif
859 
860 /* This must be invoked after performing all of the necessary
861  * memblock_set_node() calls for 'nid'.  We need to be able to get
862  * correct data from get_pfn_range_for_nid().
863  */
864 static void __init allocate_node_data(int nid)
865 {
866 	struct pglist_data *p;
867 	unsigned long start_pfn, end_pfn;
868 #ifdef CONFIG_NEED_MULTIPLE_NODES
869 	unsigned long paddr;
870 
871 	paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
872 	if (!paddr) {
873 		prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
874 		prom_halt();
875 	}
876 	NODE_DATA(nid) = __va(paddr);
877 	memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
878 
879 	NODE_DATA(nid)->node_id = nid;
880 #endif
881 
882 	p = NODE_DATA(nid);
883 
884 	get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
885 	p->node_start_pfn = start_pfn;
886 	p->node_spanned_pages = end_pfn - start_pfn;
887 }
888 
889 static void init_node_masks_nonnuma(void)
890 {
891 	int i;
892 
893 	numadbg("Initializing tables for non-numa.\n");
894 
895 	node_masks[0].mask = node_masks[0].val = 0;
896 	num_node_masks = 1;
897 
898 	for (i = 0; i < NR_CPUS; i++)
899 		numa_cpu_lookup_table[i] = 0;
900 
901 	cpumask_setall(&numa_cpumask_lookup_table[0]);
902 }
903 
904 #ifdef CONFIG_NEED_MULTIPLE_NODES
905 struct pglist_data *node_data[MAX_NUMNODES];
906 
907 EXPORT_SYMBOL(numa_cpu_lookup_table);
908 EXPORT_SYMBOL(numa_cpumask_lookup_table);
909 EXPORT_SYMBOL(node_data);
910 
911 struct mdesc_mlgroup {
912 	u64	node;
913 	u64	latency;
914 	u64	match;
915 	u64	mask;
916 };
917 static struct mdesc_mlgroup *mlgroups;
918 static int num_mlgroups;
919 
920 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
921 				   u32 cfg_handle)
922 {
923 	u64 arc;
924 
925 	mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
926 		u64 target = mdesc_arc_target(md, arc);
927 		const u64 *val;
928 
929 		val = mdesc_get_property(md, target,
930 					 "cfg-handle", NULL);
931 		if (val && *val == cfg_handle)
932 			return 0;
933 	}
934 	return -ENODEV;
935 }
936 
937 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
938 				    u32 cfg_handle)
939 {
940 	u64 arc, candidate, best_latency = ~(u64)0;
941 
942 	candidate = MDESC_NODE_NULL;
943 	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
944 		u64 target = mdesc_arc_target(md, arc);
945 		const char *name = mdesc_node_name(md, target);
946 		const u64 *val;
947 
948 		if (strcmp(name, "pio-latency-group"))
949 			continue;
950 
951 		val = mdesc_get_property(md, target, "latency", NULL);
952 		if (!val)
953 			continue;
954 
955 		if (*val < best_latency) {
956 			candidate = target;
957 			best_latency = *val;
958 		}
959 	}
960 
961 	if (candidate == MDESC_NODE_NULL)
962 		return -ENODEV;
963 
964 	return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
965 }
966 
967 int of_node_to_nid(struct device_node *dp)
968 {
969 	const struct linux_prom64_registers *regs;
970 	struct mdesc_handle *md;
971 	u32 cfg_handle;
972 	int count, nid;
973 	u64 grp;
974 
975 	/* This is the right thing to do on currently supported
976 	 * SUN4U NUMA platforms as well, as the PCI controller does
977 	 * not sit behind any particular memory controller.
978 	 */
979 	if (!mlgroups)
980 		return -1;
981 
982 	regs = of_get_property(dp, "reg", NULL);
983 	if (!regs)
984 		return -1;
985 
986 	cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
987 
988 	md = mdesc_grab();
989 
990 	count = 0;
991 	nid = -1;
992 	mdesc_for_each_node_by_name(md, grp, "group") {
993 		if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
994 			nid = count;
995 			break;
996 		}
997 		count++;
998 	}
999 
1000 	mdesc_release(md);
1001 
1002 	return nid;
1003 }
1004 
1005 static void __init add_node_ranges(void)
1006 {
1007 	struct memblock_region *reg;
1008 
1009 	for_each_memblock(memory, reg) {
1010 		unsigned long size = reg->size;
1011 		unsigned long start, end;
1012 
1013 		start = reg->base;
1014 		end = start + size;
1015 		while (start < end) {
1016 			unsigned long this_end;
1017 			int nid;
1018 
1019 			this_end = memblock_nid_range(start, end, &nid);
1020 
1021 			numadbg("Setting memblock NUMA node nid[%d] "
1022 				"start[%lx] end[%lx]\n",
1023 				nid, start, this_end);
1024 
1025 			memblock_set_node(start, this_end - start, nid);
1026 			start = this_end;
1027 		}
1028 	}
1029 }
1030 
1031 static int __init grab_mlgroups(struct mdesc_handle *md)
1032 {
1033 	unsigned long paddr;
1034 	int count = 0;
1035 	u64 node;
1036 
1037 	mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1038 		count++;
1039 	if (!count)
1040 		return -ENOENT;
1041 
1042 	paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1043 			  SMP_CACHE_BYTES);
1044 	if (!paddr)
1045 		return -ENOMEM;
1046 
1047 	mlgroups = __va(paddr);
1048 	num_mlgroups = count;
1049 
1050 	count = 0;
1051 	mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1052 		struct mdesc_mlgroup *m = &mlgroups[count++];
1053 		const u64 *val;
1054 
1055 		m->node = node;
1056 
1057 		val = mdesc_get_property(md, node, "latency", NULL);
1058 		m->latency = *val;
1059 		val = mdesc_get_property(md, node, "address-match", NULL);
1060 		m->match = *val;
1061 		val = mdesc_get_property(md, node, "address-mask", NULL);
1062 		m->mask = *val;
1063 
1064 		numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1065 			"match[%llx] mask[%llx]\n",
1066 			count - 1, m->node, m->latency, m->match, m->mask);
1067 	}
1068 
1069 	return 0;
1070 }
1071 
1072 static int __init grab_mblocks(struct mdesc_handle *md)
1073 {
1074 	unsigned long paddr;
1075 	int count = 0;
1076 	u64 node;
1077 
1078 	mdesc_for_each_node_by_name(md, node, "mblock")
1079 		count++;
1080 	if (!count)
1081 		return -ENOENT;
1082 
1083 	paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1084 			  SMP_CACHE_BYTES);
1085 	if (!paddr)
1086 		return -ENOMEM;
1087 
1088 	mblocks = __va(paddr);
1089 	num_mblocks = count;
1090 
1091 	count = 0;
1092 	mdesc_for_each_node_by_name(md, node, "mblock") {
1093 		struct mdesc_mblock *m = &mblocks[count++];
1094 		const u64 *val;
1095 
1096 		val = mdesc_get_property(md, node, "base", NULL);
1097 		m->base = *val;
1098 		val = mdesc_get_property(md, node, "size", NULL);
1099 		m->size = *val;
1100 		val = mdesc_get_property(md, node,
1101 					 "address-congruence-offset", NULL);
1102 		m->offset = *val;
1103 
1104 		numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1105 			count - 1, m->base, m->size, m->offset);
1106 	}
1107 
1108 	return 0;
1109 }
1110 
1111 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1112 					       u64 grp, cpumask_t *mask)
1113 {
1114 	u64 arc;
1115 
1116 	cpumask_clear(mask);
1117 
1118 	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1119 		u64 target = mdesc_arc_target(md, arc);
1120 		const char *name = mdesc_node_name(md, target);
1121 		const u64 *id;
1122 
1123 		if (strcmp(name, "cpu"))
1124 			continue;
1125 		id = mdesc_get_property(md, target, "id", NULL);
1126 		if (*id < nr_cpu_ids)
1127 			cpumask_set_cpu(*id, mask);
1128 	}
1129 }
1130 
1131 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1132 {
1133 	int i;
1134 
1135 	for (i = 0; i < num_mlgroups; i++) {
1136 		struct mdesc_mlgroup *m = &mlgroups[i];
1137 		if (m->node == node)
1138 			return m;
1139 	}
1140 	return NULL;
1141 }
1142 
1143 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1144 				      int index)
1145 {
1146 	struct mdesc_mlgroup *candidate = NULL;
1147 	u64 arc, best_latency = ~(u64)0;
1148 	struct node_mem_mask *n;
1149 
1150 	mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1151 		u64 target = mdesc_arc_target(md, arc);
1152 		struct mdesc_mlgroup *m = find_mlgroup(target);
1153 		if (!m)
1154 			continue;
1155 		if (m->latency < best_latency) {
1156 			candidate = m;
1157 			best_latency = m->latency;
1158 		}
1159 	}
1160 	if (!candidate)
1161 		return -ENOENT;
1162 
1163 	if (num_node_masks != index) {
1164 		printk(KERN_ERR "Inconsistent NUMA state, "
1165 		       "index[%d] != num_node_masks[%d]\n",
1166 		       index, num_node_masks);
1167 		return -EINVAL;
1168 	}
1169 
1170 	n = &node_masks[num_node_masks++];
1171 
1172 	n->mask = candidate->mask;
1173 	n->val = candidate->match;
1174 
1175 	numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1176 		index, n->mask, n->val, candidate->latency);
1177 
1178 	return 0;
1179 }
1180 
1181 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1182 					 int index)
1183 {
1184 	cpumask_t mask;
1185 	int cpu;
1186 
1187 	numa_parse_mdesc_group_cpus(md, grp, &mask);
1188 
1189 	for_each_cpu(cpu, &mask)
1190 		numa_cpu_lookup_table[cpu] = index;
1191 	cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1192 
1193 	if (numa_debug) {
1194 		printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1195 		for_each_cpu(cpu, &mask)
1196 			printk("%d ", cpu);
1197 		printk("]\n");
1198 	}
1199 
1200 	return numa_attach_mlgroup(md, grp, index);
1201 }
1202 
1203 static int __init numa_parse_mdesc(void)
1204 {
1205 	struct mdesc_handle *md = mdesc_grab();
1206 	int i, err, count;
1207 	u64 node;
1208 
1209 	node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1210 	if (node == MDESC_NODE_NULL) {
1211 		mdesc_release(md);
1212 		return -ENOENT;
1213 	}
1214 
1215 	err = grab_mblocks(md);
1216 	if (err < 0)
1217 		goto out;
1218 
1219 	err = grab_mlgroups(md);
1220 	if (err < 0)
1221 		goto out;
1222 
1223 	count = 0;
1224 	mdesc_for_each_node_by_name(md, node, "group") {
1225 		err = numa_parse_mdesc_group(md, node, count);
1226 		if (err < 0)
1227 			break;
1228 		count++;
1229 	}
1230 
1231 	add_node_ranges();
1232 
1233 	for (i = 0; i < num_node_masks; i++) {
1234 		allocate_node_data(i);
1235 		node_set_online(i);
1236 	}
1237 
1238 	err = 0;
1239 out:
1240 	mdesc_release(md);
1241 	return err;
1242 }
1243 
1244 static int __init numa_parse_jbus(void)
1245 {
1246 	unsigned long cpu, index;
1247 
1248 	/* NUMA node id is encoded in bits 36 and higher, and there is
1249 	 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1250 	 */
1251 	index = 0;
1252 	for_each_present_cpu(cpu) {
1253 		numa_cpu_lookup_table[cpu] = index;
1254 		cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1255 		node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1256 		node_masks[index].val = cpu << 36UL;
1257 
1258 		index++;
1259 	}
1260 	num_node_masks = index;
1261 
1262 	add_node_ranges();
1263 
1264 	for (index = 0; index < num_node_masks; index++) {
1265 		allocate_node_data(index);
1266 		node_set_online(index);
1267 	}
1268 
1269 	return 0;
1270 }
1271 
1272 static int __init numa_parse_sun4u(void)
1273 {
1274 	if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1275 		unsigned long ver;
1276 
1277 		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
1278 		if ((ver >> 32UL) == __JALAPENO_ID ||
1279 		    (ver >> 32UL) == __SERRANO_ID)
1280 			return numa_parse_jbus();
1281 	}
1282 	return -1;
1283 }
1284 
1285 static int __init bootmem_init_numa(void)
1286 {
1287 	int err = -1;
1288 
1289 	numadbg("bootmem_init_numa()\n");
1290 
1291 	if (numa_enabled) {
1292 		if (tlb_type == hypervisor)
1293 			err = numa_parse_mdesc();
1294 		else
1295 			err = numa_parse_sun4u();
1296 	}
1297 	return err;
1298 }
1299 
1300 #else
1301 
1302 static int bootmem_init_numa(void)
1303 {
1304 	return -1;
1305 }
1306 
1307 #endif
1308 
1309 static void __init bootmem_init_nonnuma(void)
1310 {
1311 	unsigned long top_of_ram = memblock_end_of_DRAM();
1312 	unsigned long total_ram = memblock_phys_mem_size();
1313 
1314 	numadbg("bootmem_init_nonnuma()\n");
1315 
1316 	printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1317 	       top_of_ram, total_ram);
1318 	printk(KERN_INFO "Memory hole size: %ldMB\n",
1319 	       (top_of_ram - total_ram) >> 20);
1320 
1321 	init_node_masks_nonnuma();
1322 	memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
1323 	allocate_node_data(0);
1324 	node_set_online(0);
1325 }
1326 
1327 static unsigned long __init bootmem_init(unsigned long phys_base)
1328 {
1329 	unsigned long end_pfn;
1330 
1331 	end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1332 	max_pfn = max_low_pfn = end_pfn;
1333 	min_low_pfn = (phys_base >> PAGE_SHIFT);
1334 
1335 	if (bootmem_init_numa() < 0)
1336 		bootmem_init_nonnuma();
1337 
1338 	/* Dump memblock with node info. */
1339 	memblock_dump_all();
1340 
1341 	/* XXX cpu notifier XXX */
1342 
1343 	sparse_memory_present_with_active_regions(MAX_NUMNODES);
1344 	sparse_init();
1345 
1346 	return end_pfn;
1347 }
1348 
1349 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1350 static int pall_ents __initdata;
1351 
1352 #ifdef CONFIG_DEBUG_PAGEALLOC
1353 static unsigned long __ref kernel_map_range(unsigned long pstart,
1354 					    unsigned long pend, pgprot_t prot)
1355 {
1356 	unsigned long vstart = PAGE_OFFSET + pstart;
1357 	unsigned long vend = PAGE_OFFSET + pend;
1358 	unsigned long alloc_bytes = 0UL;
1359 
1360 	if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1361 		prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1362 			    vstart, vend);
1363 		prom_halt();
1364 	}
1365 
1366 	while (vstart < vend) {
1367 		unsigned long this_end, paddr = __pa(vstart);
1368 		pgd_t *pgd = pgd_offset_k(vstart);
1369 		pud_t *pud;
1370 		pmd_t *pmd;
1371 		pte_t *pte;
1372 
1373 		pud = pud_offset(pgd, vstart);
1374 		if (pud_none(*pud)) {
1375 			pmd_t *new;
1376 
1377 			new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1378 			alloc_bytes += PAGE_SIZE;
1379 			pud_populate(&init_mm, pud, new);
1380 		}
1381 
1382 		pmd = pmd_offset(pud, vstart);
1383 		if (!pmd_present(*pmd)) {
1384 			pte_t *new;
1385 
1386 			new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1387 			alloc_bytes += PAGE_SIZE;
1388 			pmd_populate_kernel(&init_mm, pmd, new);
1389 		}
1390 
1391 		pte = pte_offset_kernel(pmd, vstart);
1392 		this_end = (vstart + PMD_SIZE) & PMD_MASK;
1393 		if (this_end > vend)
1394 			this_end = vend;
1395 
1396 		while (vstart < this_end) {
1397 			pte_val(*pte) = (paddr | pgprot_val(prot));
1398 
1399 			vstart += PAGE_SIZE;
1400 			paddr += PAGE_SIZE;
1401 			pte++;
1402 		}
1403 	}
1404 
1405 	return alloc_bytes;
1406 }
1407 
1408 extern unsigned int kvmap_linear_patch[1];
1409 #endif /* CONFIG_DEBUG_PAGEALLOC */
1410 
1411 static void __init kpte_set_val(unsigned long index, unsigned long val)
1412 {
1413 	unsigned long *ptr = kpte_linear_bitmap;
1414 
1415 	val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1416 	ptr += (index / (BITS_PER_LONG / 2));
1417 
1418 	*ptr |= val;
1419 }
1420 
1421 static const unsigned long kpte_shift_min = 28; /* 256MB */
1422 static const unsigned long kpte_shift_max = 34; /* 16GB */
1423 static const unsigned long kpte_shift_incr = 3;
1424 
1425 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1426 					   unsigned long shift)
1427 {
1428 	unsigned long size = (1UL << shift);
1429 	unsigned long mask = (size - 1UL);
1430 	unsigned long remains = end - start;
1431 	unsigned long val;
1432 
1433 	if (remains < size || (start & mask))
1434 		return start;
1435 
1436 	/* VAL maps:
1437 	 *
1438 	 *	shift 28 --> kern_linear_pte_xor index 1
1439 	 *	shift 31 --> kern_linear_pte_xor index 2
1440 	 *	shift 34 --> kern_linear_pte_xor index 3
1441 	 */
1442 	val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1443 
1444 	remains &= ~mask;
1445 	if (shift != kpte_shift_max)
1446 		remains = size;
1447 
1448 	while (remains) {
1449 		unsigned long index = start >> kpte_shift_min;
1450 
1451 		kpte_set_val(index, val);
1452 
1453 		start += 1UL << kpte_shift_min;
1454 		remains -= 1UL << kpte_shift_min;
1455 	}
1456 
1457 	return start;
1458 }
1459 
1460 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1461 {
1462 	unsigned long smallest_size, smallest_mask;
1463 	unsigned long s;
1464 
1465 	smallest_size = (1UL << kpte_shift_min);
1466 	smallest_mask = (smallest_size - 1UL);
1467 
1468 	while (start < end) {
1469 		unsigned long orig_start = start;
1470 
1471 		for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1472 			start = kpte_mark_using_shift(start, end, s);
1473 
1474 			if (start != orig_start)
1475 				break;
1476 		}
1477 
1478 		if (start == orig_start)
1479 			start = (start + smallest_size) & ~smallest_mask;
1480 	}
1481 }
1482 
1483 static void __init init_kpte_bitmap(void)
1484 {
1485 	unsigned long i;
1486 
1487 	for (i = 0; i < pall_ents; i++) {
1488 		unsigned long phys_start, phys_end;
1489 
1490 		phys_start = pall[i].phys_addr;
1491 		phys_end = phys_start + pall[i].reg_size;
1492 
1493 		mark_kpte_bitmap(phys_start, phys_end);
1494 	}
1495 }
1496 
1497 static void __init kernel_physical_mapping_init(void)
1498 {
1499 #ifdef CONFIG_DEBUG_PAGEALLOC
1500 	unsigned long i, mem_alloced = 0UL;
1501 
1502 	for (i = 0; i < pall_ents; i++) {
1503 		unsigned long phys_start, phys_end;
1504 
1505 		phys_start = pall[i].phys_addr;
1506 		phys_end = phys_start + pall[i].reg_size;
1507 
1508 		mem_alloced += kernel_map_range(phys_start, phys_end,
1509 						PAGE_KERNEL);
1510 	}
1511 
1512 	printk("Allocated %ld bytes for kernel page tables.\n",
1513 	       mem_alloced);
1514 
1515 	kvmap_linear_patch[0] = 0x01000000; /* nop */
1516 	flushi(&kvmap_linear_patch[0]);
1517 
1518 	__flush_tlb_all();
1519 #endif
1520 }
1521 
1522 #ifdef CONFIG_DEBUG_PAGEALLOC
1523 void kernel_map_pages(struct page *page, int numpages, int enable)
1524 {
1525 	unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1526 	unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1527 
1528 	kernel_map_range(phys_start, phys_end,
1529 			 (enable ? PAGE_KERNEL : __pgprot(0)));
1530 
1531 	flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1532 			       PAGE_OFFSET + phys_end);
1533 
1534 	/* we should perform an IPI and flush all tlbs,
1535 	 * but that can deadlock->flush only current cpu.
1536 	 */
1537 	__flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1538 				 PAGE_OFFSET + phys_end);
1539 }
1540 #endif
1541 
1542 unsigned long __init find_ecache_flush_span(unsigned long size)
1543 {
1544 	int i;
1545 
1546 	for (i = 0; i < pavail_ents; i++) {
1547 		if (pavail[i].reg_size >= size)
1548 			return pavail[i].phys_addr;
1549 	}
1550 
1551 	return ~0UL;
1552 }
1553 
1554 static void __init tsb_phys_patch(void)
1555 {
1556 	struct tsb_ldquad_phys_patch_entry *pquad;
1557 	struct tsb_phys_patch_entry *p;
1558 
1559 	pquad = &__tsb_ldquad_phys_patch;
1560 	while (pquad < &__tsb_ldquad_phys_patch_end) {
1561 		unsigned long addr = pquad->addr;
1562 
1563 		if (tlb_type == hypervisor)
1564 			*(unsigned int *) addr = pquad->sun4v_insn;
1565 		else
1566 			*(unsigned int *) addr = pquad->sun4u_insn;
1567 		wmb();
1568 		__asm__ __volatile__("flush	%0"
1569 				     : /* no outputs */
1570 				     : "r" (addr));
1571 
1572 		pquad++;
1573 	}
1574 
1575 	p = &__tsb_phys_patch;
1576 	while (p < &__tsb_phys_patch_end) {
1577 		unsigned long addr = p->addr;
1578 
1579 		*(unsigned int *) addr = p->insn;
1580 		wmb();
1581 		__asm__ __volatile__("flush	%0"
1582 				     : /* no outputs */
1583 				     : "r" (addr));
1584 
1585 		p++;
1586 	}
1587 }
1588 
1589 /* Don't mark as init, we give this to the Hypervisor.  */
1590 #ifndef CONFIG_DEBUG_PAGEALLOC
1591 #define NUM_KTSB_DESCR	2
1592 #else
1593 #define NUM_KTSB_DESCR	1
1594 #endif
1595 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1596 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1597 
1598 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1599 {
1600 	pa >>= KTSB_PHYS_SHIFT;
1601 
1602 	while (start < end) {
1603 		unsigned int *ia = (unsigned int *)(unsigned long)*start;
1604 
1605 		ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1606 		__asm__ __volatile__("flush	%0" : : "r" (ia));
1607 
1608 		ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1609 		__asm__ __volatile__("flush	%0" : : "r" (ia + 1));
1610 
1611 		start++;
1612 	}
1613 }
1614 
1615 static void ktsb_phys_patch(void)
1616 {
1617 	extern unsigned int __swapper_tsb_phys_patch;
1618 	extern unsigned int __swapper_tsb_phys_patch_end;
1619 	unsigned long ktsb_pa;
1620 
1621 	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1622 	patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1623 			    &__swapper_tsb_phys_patch_end, ktsb_pa);
1624 #ifndef CONFIG_DEBUG_PAGEALLOC
1625 	{
1626 	extern unsigned int __swapper_4m_tsb_phys_patch;
1627 	extern unsigned int __swapper_4m_tsb_phys_patch_end;
1628 	ktsb_pa = (kern_base +
1629 		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1630 	patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1631 			    &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1632 	}
1633 #endif
1634 }
1635 
1636 static void __init sun4v_ktsb_init(void)
1637 {
1638 	unsigned long ktsb_pa;
1639 
1640 	/* First KTSB for PAGE_SIZE mappings.  */
1641 	ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1642 
1643 	switch (PAGE_SIZE) {
1644 	case 8 * 1024:
1645 	default:
1646 		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1647 		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1648 		break;
1649 
1650 	case 64 * 1024:
1651 		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1652 		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1653 		break;
1654 
1655 	case 512 * 1024:
1656 		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1657 		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1658 		break;
1659 
1660 	case 4 * 1024 * 1024:
1661 		ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1662 		ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1663 		break;
1664 	}
1665 
1666 	ktsb_descr[0].assoc = 1;
1667 	ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1668 	ktsb_descr[0].ctx_idx = 0;
1669 	ktsb_descr[0].tsb_base = ktsb_pa;
1670 	ktsb_descr[0].resv = 0;
1671 
1672 #ifndef CONFIG_DEBUG_PAGEALLOC
1673 	/* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1674 	ktsb_pa = (kern_base +
1675 		   ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1676 
1677 	ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1678 	ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1679 				    HV_PGSZ_MASK_256MB |
1680 				    HV_PGSZ_MASK_2GB |
1681 				    HV_PGSZ_MASK_16GB) &
1682 				   cpu_pgsz_mask);
1683 	ktsb_descr[1].assoc = 1;
1684 	ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1685 	ktsb_descr[1].ctx_idx = 0;
1686 	ktsb_descr[1].tsb_base = ktsb_pa;
1687 	ktsb_descr[1].resv = 0;
1688 #endif
1689 }
1690 
1691 void __cpuinit sun4v_ktsb_register(void)
1692 {
1693 	unsigned long pa, ret;
1694 
1695 	pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1696 
1697 	ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1698 	if (ret != 0) {
1699 		prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1700 			    "errors with %lx\n", pa, ret);
1701 		prom_halt();
1702 	}
1703 }
1704 
1705 static void __init sun4u_linear_pte_xor_finalize(void)
1706 {
1707 #ifndef CONFIG_DEBUG_PAGEALLOC
1708 	/* This is where we would add Panther support for
1709 	 * 32MB and 256MB pages.
1710 	 */
1711 #endif
1712 }
1713 
1714 static void __init sun4v_linear_pte_xor_finalize(void)
1715 {
1716 #ifndef CONFIG_DEBUG_PAGEALLOC
1717 	if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1718 		kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1719 			0xfffff80000000000UL;
1720 		kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1721 					   _PAGE_P_4V | _PAGE_W_4V);
1722 	} else {
1723 		kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1724 	}
1725 
1726 	if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1727 		kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1728 			0xfffff80000000000UL;
1729 		kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1730 					   _PAGE_P_4V | _PAGE_W_4V);
1731 	} else {
1732 		kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1733 	}
1734 
1735 	if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1736 		kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1737 			0xfffff80000000000UL;
1738 		kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1739 					   _PAGE_P_4V | _PAGE_W_4V);
1740 	} else {
1741 		kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1742 	}
1743 #endif
1744 }
1745 
1746 /* paging_init() sets up the page tables */
1747 
1748 static unsigned long last_valid_pfn;
1749 pgd_t swapper_pg_dir[2048];
1750 
1751 static void sun4u_pgprot_init(void);
1752 static void sun4v_pgprot_init(void);
1753 
1754 void __init paging_init(void)
1755 {
1756 	unsigned long end_pfn, shift, phys_base;
1757 	unsigned long real_end, i;
1758 	int node;
1759 
1760 	/* These build time checkes make sure that the dcache_dirty_cpu()
1761 	 * page->flags usage will work.
1762 	 *
1763 	 * When a page gets marked as dcache-dirty, we store the
1764 	 * cpu number starting at bit 32 in the page->flags.  Also,
1765 	 * functions like clear_dcache_dirty_cpu use the cpu mask
1766 	 * in 13-bit signed-immediate instruction fields.
1767 	 */
1768 
1769 	/*
1770 	 * Page flags must not reach into upper 32 bits that are used
1771 	 * for the cpu number
1772 	 */
1773 	BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1774 
1775 	/*
1776 	 * The bit fields placed in the high range must not reach below
1777 	 * the 32 bit boundary. Otherwise we cannot place the cpu field
1778 	 * at the 32 bit boundary.
1779 	 */
1780 	BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1781 		ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1782 
1783 	BUILD_BUG_ON(NR_CPUS > 4096);
1784 
1785 	kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1786 	kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1787 
1788 	/* Invalidate both kernel TSBs.  */
1789 	memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1790 #ifndef CONFIG_DEBUG_PAGEALLOC
1791 	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1792 #endif
1793 
1794 	if (tlb_type == hypervisor)
1795 		sun4v_pgprot_init();
1796 	else
1797 		sun4u_pgprot_init();
1798 
1799 	if (tlb_type == cheetah_plus ||
1800 	    tlb_type == hypervisor) {
1801 		tsb_phys_patch();
1802 		ktsb_phys_patch();
1803 	}
1804 
1805 	if (tlb_type == hypervisor)
1806 		sun4v_patch_tlb_handlers();
1807 
1808 	/* Find available physical memory...
1809 	 *
1810 	 * Read it twice in order to work around a bug in openfirmware.
1811 	 * The call to grab this table itself can cause openfirmware to
1812 	 * allocate memory, which in turn can take away some space from
1813 	 * the list of available memory.  Reading it twice makes sure
1814 	 * we really do get the final value.
1815 	 */
1816 	read_obp_translations();
1817 	read_obp_memory("reg", &pall[0], &pall_ents);
1818 	read_obp_memory("available", &pavail[0], &pavail_ents);
1819 	read_obp_memory("available", &pavail[0], &pavail_ents);
1820 
1821 	phys_base = 0xffffffffffffffffUL;
1822 	for (i = 0; i < pavail_ents; i++) {
1823 		phys_base = min(phys_base, pavail[i].phys_addr);
1824 		memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1825 	}
1826 
1827 	memblock_reserve(kern_base, kern_size);
1828 
1829 	find_ramdisk(phys_base);
1830 
1831 	memblock_enforce_memory_limit(cmdline_memory_size);
1832 
1833 	memblock_allow_resize();
1834 	memblock_dump_all();
1835 
1836 	set_bit(0, mmu_context_bmap);
1837 
1838 	shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1839 
1840 	real_end = (unsigned long)_end;
1841 	num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1842 	printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1843 	       num_kernel_image_mappings);
1844 
1845 	/* Set kernel pgd to upper alias so physical page computations
1846 	 * work.
1847 	 */
1848 	init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1849 
1850 	memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1851 
1852 	/* Now can init the kernel/bad page tables. */
1853 	pud_set(pud_offset(&swapper_pg_dir[0], 0),
1854 		swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1855 
1856 	inherit_prom_mappings();
1857 
1858 	init_kpte_bitmap();
1859 
1860 	/* Ok, we can use our TLB miss and window trap handlers safely.  */
1861 	setup_tba();
1862 
1863 	__flush_tlb_all();
1864 
1865 	prom_build_devicetree();
1866 	of_populate_present_mask();
1867 #ifndef CONFIG_SMP
1868 	of_fill_in_cpu_data();
1869 #endif
1870 
1871 	if (tlb_type == hypervisor) {
1872 		sun4v_mdesc_init();
1873 		mdesc_populate_present_mask(cpu_all_mask);
1874 #ifndef CONFIG_SMP
1875 		mdesc_fill_in_cpu_data(cpu_all_mask);
1876 #endif
1877 		mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1878 
1879 		sun4v_linear_pte_xor_finalize();
1880 
1881 		sun4v_ktsb_init();
1882 		sun4v_ktsb_register();
1883 	} else {
1884 		unsigned long impl, ver;
1885 
1886 		cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1887 				 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1888 
1889 		__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1890 		impl = ((ver >> 32) & 0xffff);
1891 		if (impl == PANTHER_IMPL)
1892 			cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1893 					  HV_PGSZ_MASK_256MB);
1894 
1895 		sun4u_linear_pte_xor_finalize();
1896 	}
1897 
1898 	/* Flush the TLBs and the 4M TSB so that the updated linear
1899 	 * pte XOR settings are realized for all mappings.
1900 	 */
1901 	__flush_tlb_all();
1902 #ifndef CONFIG_DEBUG_PAGEALLOC
1903 	memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1904 #endif
1905 	__flush_tlb_all();
1906 
1907 	/* Setup bootmem... */
1908 	last_valid_pfn = end_pfn = bootmem_init(phys_base);
1909 
1910 	/* Once the OF device tree and MDESC have been setup, we know
1911 	 * the list of possible cpus.  Therefore we can allocate the
1912 	 * IRQ stacks.
1913 	 */
1914 	for_each_possible_cpu(i) {
1915 		node = cpu_to_node(i);
1916 
1917 		softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1918 							THREAD_SIZE,
1919 							THREAD_SIZE, 0);
1920 		hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1921 							THREAD_SIZE,
1922 							THREAD_SIZE, 0);
1923 	}
1924 
1925 	kernel_physical_mapping_init();
1926 
1927 	{
1928 		unsigned long max_zone_pfns[MAX_NR_ZONES];
1929 
1930 		memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1931 
1932 		max_zone_pfns[ZONE_NORMAL] = end_pfn;
1933 
1934 		free_area_init_nodes(max_zone_pfns);
1935 	}
1936 
1937 	printk("Booting Linux...\n");
1938 }
1939 
1940 int page_in_phys_avail(unsigned long paddr)
1941 {
1942 	int i;
1943 
1944 	paddr &= PAGE_MASK;
1945 
1946 	for (i = 0; i < pavail_ents; i++) {
1947 		unsigned long start, end;
1948 
1949 		start = pavail[i].phys_addr;
1950 		end = start + pavail[i].reg_size;
1951 
1952 		if (paddr >= start && paddr < end)
1953 			return 1;
1954 	}
1955 	if (paddr >= kern_base && paddr < (kern_base + kern_size))
1956 		return 1;
1957 #ifdef CONFIG_BLK_DEV_INITRD
1958 	if (paddr >= __pa(initrd_start) &&
1959 	    paddr < __pa(PAGE_ALIGN(initrd_end)))
1960 		return 1;
1961 #endif
1962 
1963 	return 0;
1964 }
1965 
1966 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1967 static int pavail_rescan_ents __initdata;
1968 
1969 /* Certain OBP calls, such as fetching "available" properties, can
1970  * claim physical memory.  So, along with initializing the valid
1971  * address bitmap, what we do here is refetch the physical available
1972  * memory list again, and make sure it provides at least as much
1973  * memory as 'pavail' does.
1974  */
1975 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1976 {
1977 	int i;
1978 
1979 	read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1980 
1981 	for (i = 0; i < pavail_ents; i++) {
1982 		unsigned long old_start, old_end;
1983 
1984 		old_start = pavail[i].phys_addr;
1985 		old_end = old_start + pavail[i].reg_size;
1986 		while (old_start < old_end) {
1987 			int n;
1988 
1989 			for (n = 0; n < pavail_rescan_ents; n++) {
1990 				unsigned long new_start, new_end;
1991 
1992 				new_start = pavail_rescan[n].phys_addr;
1993 				new_end = new_start +
1994 					pavail_rescan[n].reg_size;
1995 
1996 				if (new_start <= old_start &&
1997 				    new_end >= (old_start + PAGE_SIZE)) {
1998 					set_bit(old_start >> 22, bitmap);
1999 					goto do_next_page;
2000 				}
2001 			}
2002 
2003 			prom_printf("mem_init: Lost memory in pavail\n");
2004 			prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2005 				    pavail[i].phys_addr,
2006 				    pavail[i].reg_size);
2007 			prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2008 				    pavail_rescan[i].phys_addr,
2009 				    pavail_rescan[i].reg_size);
2010 			prom_printf("mem_init: Cannot continue, aborting.\n");
2011 			prom_halt();
2012 
2013 		do_next_page:
2014 			old_start += PAGE_SIZE;
2015 		}
2016 	}
2017 }
2018 
2019 static void __init patch_tlb_miss_handler_bitmap(void)
2020 {
2021 	extern unsigned int valid_addr_bitmap_insn[];
2022 	extern unsigned int valid_addr_bitmap_patch[];
2023 
2024 	valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2025 	mb();
2026 	valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2027 	flushi(&valid_addr_bitmap_insn[0]);
2028 }
2029 
2030 static void __init register_page_bootmem_info(void)
2031 {
2032 #ifdef CONFIG_NEED_MULTIPLE_NODES
2033 	int i;
2034 
2035 	for_each_online_node(i)
2036 		if (NODE_DATA(i)->node_spanned_pages)
2037 			register_page_bootmem_info_node(NODE_DATA(i));
2038 #endif
2039 }
2040 void __init mem_init(void)
2041 {
2042 	unsigned long codepages, datapages, initpages;
2043 	unsigned long addr, last;
2044 
2045 	addr = PAGE_OFFSET + kern_base;
2046 	last = PAGE_ALIGN(kern_size) + addr;
2047 	while (addr < last) {
2048 		set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2049 		addr += PAGE_SIZE;
2050 	}
2051 
2052 	setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2053 	patch_tlb_miss_handler_bitmap();
2054 
2055 	high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2056 
2057 	register_page_bootmem_info();
2058 	totalram_pages = free_all_bootmem();
2059 
2060 	/* We subtract one to account for the mem_map_zero page
2061 	 * allocated below.
2062 	 */
2063 	totalram_pages -= 1;
2064 	num_physpages = totalram_pages;
2065 
2066 	/*
2067 	 * Set up the zero page, mark it reserved, so that page count
2068 	 * is not manipulated when freeing the page from user ptes.
2069 	 */
2070 	mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2071 	if (mem_map_zero == NULL) {
2072 		prom_printf("paging_init: Cannot alloc zero page.\n");
2073 		prom_halt();
2074 	}
2075 	SetPageReserved(mem_map_zero);
2076 
2077 	codepages = (((unsigned long) _etext) - ((unsigned long) _start));
2078 	codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
2079 	datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
2080 	datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
2081 	initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
2082 	initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
2083 
2084 	printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
2085 	       nr_free_pages() << (PAGE_SHIFT-10),
2086 	       codepages << (PAGE_SHIFT-10),
2087 	       datapages << (PAGE_SHIFT-10),
2088 	       initpages << (PAGE_SHIFT-10),
2089 	       PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2090 
2091 	if (tlb_type == cheetah || tlb_type == cheetah_plus)
2092 		cheetah_ecache_flush_init();
2093 }
2094 
2095 void free_initmem(void)
2096 {
2097 	unsigned long addr, initend;
2098 	int do_free = 1;
2099 
2100 	/* If the physical memory maps were trimmed by kernel command
2101 	 * line options, don't even try freeing this initmem stuff up.
2102 	 * The kernel image could have been in the trimmed out region
2103 	 * and if so the freeing below will free invalid page structs.
2104 	 */
2105 	if (cmdline_memory_size)
2106 		do_free = 0;
2107 
2108 	/*
2109 	 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2110 	 */
2111 	addr = PAGE_ALIGN((unsigned long)(__init_begin));
2112 	initend = (unsigned long)(__init_end) & PAGE_MASK;
2113 	for (; addr < initend; addr += PAGE_SIZE) {
2114 		unsigned long page;
2115 		struct page *p;
2116 
2117 		page = (addr +
2118 			((unsigned long) __va(kern_base)) -
2119 			((unsigned long) KERNBASE));
2120 		memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2121 
2122 		if (do_free) {
2123 			p = virt_to_page(page);
2124 
2125 			ClearPageReserved(p);
2126 			init_page_count(p);
2127 			__free_page(p);
2128 			num_physpages++;
2129 			totalram_pages++;
2130 		}
2131 	}
2132 }
2133 
2134 #ifdef CONFIG_BLK_DEV_INITRD
2135 void free_initrd_mem(unsigned long start, unsigned long end)
2136 {
2137 	if (start < end)
2138 		printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2139 	for (; start < end; start += PAGE_SIZE) {
2140 		struct page *p = virt_to_page(start);
2141 
2142 		ClearPageReserved(p);
2143 		init_page_count(p);
2144 		__free_page(p);
2145 		num_physpages++;
2146 		totalram_pages++;
2147 	}
2148 }
2149 #endif
2150 
2151 #define _PAGE_CACHE_4U	(_PAGE_CP_4U | _PAGE_CV_4U)
2152 #define _PAGE_CACHE_4V	(_PAGE_CP_4V | _PAGE_CV_4V)
2153 #define __DIRTY_BITS_4U	 (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2154 #define __DIRTY_BITS_4V	 (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2155 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2156 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2157 
2158 pgprot_t PAGE_KERNEL __read_mostly;
2159 EXPORT_SYMBOL(PAGE_KERNEL);
2160 
2161 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2162 pgprot_t PAGE_COPY __read_mostly;
2163 
2164 pgprot_t PAGE_SHARED __read_mostly;
2165 EXPORT_SYMBOL(PAGE_SHARED);
2166 
2167 unsigned long pg_iobits __read_mostly;
2168 
2169 unsigned long _PAGE_IE __read_mostly;
2170 EXPORT_SYMBOL(_PAGE_IE);
2171 
2172 unsigned long _PAGE_E __read_mostly;
2173 EXPORT_SYMBOL(_PAGE_E);
2174 
2175 unsigned long _PAGE_CACHE __read_mostly;
2176 EXPORT_SYMBOL(_PAGE_CACHE);
2177 
2178 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2179 unsigned long vmemmap_table[VMEMMAP_SIZE];
2180 
2181 static long __meminitdata addr_start, addr_end;
2182 static int __meminitdata node_start;
2183 
2184 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2185 {
2186 	unsigned long vstart = (unsigned long) start;
2187 	unsigned long vend = (unsigned long) (start + nr);
2188 	unsigned long phys_start = (vstart - VMEMMAP_BASE);
2189 	unsigned long phys_end = (vend - VMEMMAP_BASE);
2190 	unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2191 	unsigned long end = VMEMMAP_ALIGN(phys_end);
2192 	unsigned long pte_base;
2193 
2194 	pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2195 		    _PAGE_CP_4U | _PAGE_CV_4U |
2196 		    _PAGE_P_4U | _PAGE_W_4U);
2197 	if (tlb_type == hypervisor)
2198 		pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2199 			    _PAGE_CP_4V | _PAGE_CV_4V |
2200 			    _PAGE_P_4V | _PAGE_W_4V);
2201 
2202 	for (; addr < end; addr += VMEMMAP_CHUNK) {
2203 		unsigned long *vmem_pp =
2204 			vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2205 		void *block;
2206 
2207 		if (!(*vmem_pp & _PAGE_VALID)) {
2208 			block = vmemmap_alloc_block(1UL << 22, node);
2209 			if (!block)
2210 				return -ENOMEM;
2211 
2212 			*vmem_pp = pte_base | __pa(block);
2213 
2214 			/* check to see if we have contiguous blocks */
2215 			if (addr_end != addr || node_start != node) {
2216 				if (addr_start)
2217 					printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2218 					       addr_start, addr_end-1, node_start);
2219 				addr_start = addr;
2220 				node_start = node;
2221 			}
2222 			addr_end = addr + VMEMMAP_CHUNK;
2223 		}
2224 	}
2225 	return 0;
2226 }
2227 
2228 void __meminit vmemmap_populate_print_last(void)
2229 {
2230 	if (addr_start) {
2231 		printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2232 		       addr_start, addr_end-1, node_start);
2233 		addr_start = 0;
2234 		addr_end = 0;
2235 		node_start = 0;
2236 	}
2237 }
2238 
2239 void vmemmap_free(struct page *memmap, unsigned long nr_pages)
2240 {
2241 }
2242 
2243 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2244 
2245 static void prot_init_common(unsigned long page_none,
2246 			     unsigned long page_shared,
2247 			     unsigned long page_copy,
2248 			     unsigned long page_readonly,
2249 			     unsigned long page_exec_bit)
2250 {
2251 	PAGE_COPY = __pgprot(page_copy);
2252 	PAGE_SHARED = __pgprot(page_shared);
2253 
2254 	protection_map[0x0] = __pgprot(page_none);
2255 	protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2256 	protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2257 	protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2258 	protection_map[0x4] = __pgprot(page_readonly);
2259 	protection_map[0x5] = __pgprot(page_readonly);
2260 	protection_map[0x6] = __pgprot(page_copy);
2261 	protection_map[0x7] = __pgprot(page_copy);
2262 	protection_map[0x8] = __pgprot(page_none);
2263 	protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2264 	protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2265 	protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2266 	protection_map[0xc] = __pgprot(page_readonly);
2267 	protection_map[0xd] = __pgprot(page_readonly);
2268 	protection_map[0xe] = __pgprot(page_shared);
2269 	protection_map[0xf] = __pgprot(page_shared);
2270 }
2271 
2272 static void __init sun4u_pgprot_init(void)
2273 {
2274 	unsigned long page_none, page_shared, page_copy, page_readonly;
2275 	unsigned long page_exec_bit;
2276 	int i;
2277 
2278 	PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2279 				_PAGE_CACHE_4U | _PAGE_P_4U |
2280 				__ACCESS_BITS_4U | __DIRTY_BITS_4U |
2281 				_PAGE_EXEC_4U);
2282 	PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2283 				       _PAGE_CACHE_4U | _PAGE_P_4U |
2284 				       __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2285 				       _PAGE_EXEC_4U | _PAGE_L_4U);
2286 
2287 	_PAGE_IE = _PAGE_IE_4U;
2288 	_PAGE_E = _PAGE_E_4U;
2289 	_PAGE_CACHE = _PAGE_CACHE_4U;
2290 
2291 	pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2292 		     __ACCESS_BITS_4U | _PAGE_E_4U);
2293 
2294 #ifdef CONFIG_DEBUG_PAGEALLOC
2295 	kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2296 #else
2297 	kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2298 		0xfffff80000000000UL;
2299 #endif
2300 	kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2301 				   _PAGE_P_4U | _PAGE_W_4U);
2302 
2303 	for (i = 1; i < 4; i++)
2304 		kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2305 
2306 	_PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2307 			      _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2308 			      _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2309 
2310 
2311 	page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2312 	page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2313 		       __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2314 	page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2315 		       __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2316 	page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2317 			   __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2318 
2319 	page_exec_bit = _PAGE_EXEC_4U;
2320 
2321 	prot_init_common(page_none, page_shared, page_copy, page_readonly,
2322 			 page_exec_bit);
2323 }
2324 
2325 static void __init sun4v_pgprot_init(void)
2326 {
2327 	unsigned long page_none, page_shared, page_copy, page_readonly;
2328 	unsigned long page_exec_bit;
2329 	int i;
2330 
2331 	PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2332 				_PAGE_CACHE_4V | _PAGE_P_4V |
2333 				__ACCESS_BITS_4V | __DIRTY_BITS_4V |
2334 				_PAGE_EXEC_4V);
2335 	PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2336 
2337 	_PAGE_IE = _PAGE_IE_4V;
2338 	_PAGE_E = _PAGE_E_4V;
2339 	_PAGE_CACHE = _PAGE_CACHE_4V;
2340 
2341 #ifdef CONFIG_DEBUG_PAGEALLOC
2342 	kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2343 #else
2344 	kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2345 		0xfffff80000000000UL;
2346 #endif
2347 	kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2348 				   _PAGE_P_4V | _PAGE_W_4V);
2349 
2350 	for (i = 1; i < 4; i++)
2351 		kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2352 
2353 	pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2354 		     __ACCESS_BITS_4V | _PAGE_E_4V);
2355 
2356 	_PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2357 			     _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2358 			     _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2359 			     _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2360 
2361 	page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2362 	page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2363 		       __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2364 	page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2365 		       __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2366 	page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2367 			 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2368 
2369 	page_exec_bit = _PAGE_EXEC_4V;
2370 
2371 	prot_init_common(page_none, page_shared, page_copy, page_readonly,
2372 			 page_exec_bit);
2373 }
2374 
2375 unsigned long pte_sz_bits(unsigned long sz)
2376 {
2377 	if (tlb_type == hypervisor) {
2378 		switch (sz) {
2379 		case 8 * 1024:
2380 		default:
2381 			return _PAGE_SZ8K_4V;
2382 		case 64 * 1024:
2383 			return _PAGE_SZ64K_4V;
2384 		case 512 * 1024:
2385 			return _PAGE_SZ512K_4V;
2386 		case 4 * 1024 * 1024:
2387 			return _PAGE_SZ4MB_4V;
2388 		}
2389 	} else {
2390 		switch (sz) {
2391 		case 8 * 1024:
2392 		default:
2393 			return _PAGE_SZ8K_4U;
2394 		case 64 * 1024:
2395 			return _PAGE_SZ64K_4U;
2396 		case 512 * 1024:
2397 			return _PAGE_SZ512K_4U;
2398 		case 4 * 1024 * 1024:
2399 			return _PAGE_SZ4MB_4U;
2400 		}
2401 	}
2402 }
2403 
2404 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2405 {
2406 	pte_t pte;
2407 
2408 	pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2409 	pte_val(pte) |= (((unsigned long)space) << 32);
2410 	pte_val(pte) |= pte_sz_bits(page_size);
2411 
2412 	return pte;
2413 }
2414 
2415 static unsigned long kern_large_tte(unsigned long paddr)
2416 {
2417 	unsigned long val;
2418 
2419 	val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2420 	       _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2421 	       _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2422 	if (tlb_type == hypervisor)
2423 		val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2424 		       _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2425 		       _PAGE_EXEC_4V | _PAGE_W_4V);
2426 
2427 	return val | paddr;
2428 }
2429 
2430 /* If not locked, zap it. */
2431 void __flush_tlb_all(void)
2432 {
2433 	unsigned long pstate;
2434 	int i;
2435 
2436 	__asm__ __volatile__("flushw\n\t"
2437 			     "rdpr	%%pstate, %0\n\t"
2438 			     "wrpr	%0, %1, %%pstate"
2439 			     : "=r" (pstate)
2440 			     : "i" (PSTATE_IE));
2441 	if (tlb_type == hypervisor) {
2442 		sun4v_mmu_demap_all();
2443 	} else if (tlb_type == spitfire) {
2444 		for (i = 0; i < 64; i++) {
2445 			/* Spitfire Errata #32 workaround */
2446 			/* NOTE: Always runs on spitfire, so no
2447 			 *       cheetah+ page size encodings.
2448 			 */
2449 			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
2450 					     "flush	%%g6"
2451 					     : /* No outputs */
2452 					     : "r" (0),
2453 					     "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2454 
2455 			if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2456 				__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2457 						     "membar #Sync"
2458 						     : /* no outputs */
2459 						     : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2460 				spitfire_put_dtlb_data(i, 0x0UL);
2461 			}
2462 
2463 			/* Spitfire Errata #32 workaround */
2464 			/* NOTE: Always runs on spitfire, so no
2465 			 *       cheetah+ page size encodings.
2466 			 */
2467 			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
2468 					     "flush	%%g6"
2469 					     : /* No outputs */
2470 					     : "r" (0),
2471 					     "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2472 
2473 			if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2474 				__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2475 						     "membar #Sync"
2476 						     : /* no outputs */
2477 						     : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2478 				spitfire_put_itlb_data(i, 0x0UL);
2479 			}
2480 		}
2481 	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2482 		cheetah_flush_dtlb_all();
2483 		cheetah_flush_itlb_all();
2484 	}
2485 	__asm__ __volatile__("wrpr	%0, 0, %%pstate"
2486 			     : : "r" (pstate));
2487 }
2488 
2489 static pte_t *get_from_cache(struct mm_struct *mm)
2490 {
2491 	struct page *page;
2492 	pte_t *ret;
2493 
2494 	spin_lock(&mm->page_table_lock);
2495 	page = mm->context.pgtable_page;
2496 	ret = NULL;
2497 	if (page) {
2498 		void *p = page_address(page);
2499 
2500 		mm->context.pgtable_page = NULL;
2501 
2502 		ret = (pte_t *) (p + (PAGE_SIZE / 2));
2503 	}
2504 	spin_unlock(&mm->page_table_lock);
2505 
2506 	return ret;
2507 }
2508 
2509 static struct page *__alloc_for_cache(struct mm_struct *mm)
2510 {
2511 	struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2512 				       __GFP_REPEAT | __GFP_ZERO);
2513 
2514 	if (page) {
2515 		spin_lock(&mm->page_table_lock);
2516 		if (!mm->context.pgtable_page) {
2517 			atomic_set(&page->_count, 2);
2518 			mm->context.pgtable_page = page;
2519 		}
2520 		spin_unlock(&mm->page_table_lock);
2521 	}
2522 	return page;
2523 }
2524 
2525 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2526 			    unsigned long address)
2527 {
2528 	struct page *page;
2529 	pte_t *pte;
2530 
2531 	pte = get_from_cache(mm);
2532 	if (pte)
2533 		return pte;
2534 
2535 	page = __alloc_for_cache(mm);
2536 	if (page)
2537 		pte = (pte_t *) page_address(page);
2538 
2539 	return pte;
2540 }
2541 
2542 pgtable_t pte_alloc_one(struct mm_struct *mm,
2543 			unsigned long address)
2544 {
2545 	struct page *page;
2546 	pte_t *pte;
2547 
2548 	pte = get_from_cache(mm);
2549 	if (pte)
2550 		return pte;
2551 
2552 	page = __alloc_for_cache(mm);
2553 	if (page) {
2554 		pgtable_page_ctor(page);
2555 		pte = (pte_t *) page_address(page);
2556 	}
2557 
2558 	return pte;
2559 }
2560 
2561 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2562 {
2563 	struct page *page = virt_to_page(pte);
2564 	if (put_page_testzero(page))
2565 		free_hot_cold_page(page, 0);
2566 }
2567 
2568 static void __pte_free(pgtable_t pte)
2569 {
2570 	struct page *page = virt_to_page(pte);
2571 	if (put_page_testzero(page)) {
2572 		pgtable_page_dtor(page);
2573 		free_hot_cold_page(page, 0);
2574 	}
2575 }
2576 
2577 void pte_free(struct mm_struct *mm, pgtable_t pte)
2578 {
2579 	__pte_free(pte);
2580 }
2581 
2582 void pgtable_free(void *table, bool is_page)
2583 {
2584 	if (is_page)
2585 		__pte_free(table);
2586 	else
2587 		kmem_cache_free(pgtable_cache, table);
2588 }
2589 
2590 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2591 static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot, bool for_modify)
2592 {
2593 	if (pgprot_val(pgprot) & _PAGE_VALID)
2594 		pmd_val(pmd) |= PMD_HUGE_PRESENT;
2595 	if (tlb_type == hypervisor) {
2596 		if (pgprot_val(pgprot) & _PAGE_WRITE_4V)
2597 			pmd_val(pmd) |= PMD_HUGE_WRITE;
2598 		if (pgprot_val(pgprot) & _PAGE_EXEC_4V)
2599 			pmd_val(pmd) |= PMD_HUGE_EXEC;
2600 
2601 		if (!for_modify) {
2602 			if (pgprot_val(pgprot) & _PAGE_ACCESSED_4V)
2603 				pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2604 			if (pgprot_val(pgprot) & _PAGE_MODIFIED_4V)
2605 				pmd_val(pmd) |= PMD_HUGE_DIRTY;
2606 		}
2607 	} else {
2608 		if (pgprot_val(pgprot) & _PAGE_WRITE_4U)
2609 			pmd_val(pmd) |= PMD_HUGE_WRITE;
2610 		if (pgprot_val(pgprot) & _PAGE_EXEC_4U)
2611 			pmd_val(pmd) |= PMD_HUGE_EXEC;
2612 
2613 		if (!for_modify) {
2614 			if (pgprot_val(pgprot) & _PAGE_ACCESSED_4U)
2615 				pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2616 			if (pgprot_val(pgprot) & _PAGE_MODIFIED_4U)
2617 				pmd_val(pmd) |= PMD_HUGE_DIRTY;
2618 		}
2619 	}
2620 
2621 	return pmd;
2622 }
2623 
2624 pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
2625 {
2626 	pmd_t pmd;
2627 
2628 	pmd_val(pmd) = (page_nr << ((PAGE_SHIFT - PMD_PADDR_SHIFT)));
2629 	pmd_val(pmd) |= PMD_ISHUGE;
2630 	pmd = pmd_set_protbits(pmd, pgprot, false);
2631 	return pmd;
2632 }
2633 
2634 pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
2635 {
2636 	pmd_val(pmd) &= ~(PMD_HUGE_PRESENT |
2637 			  PMD_HUGE_WRITE |
2638 			  PMD_HUGE_EXEC);
2639 	pmd = pmd_set_protbits(pmd, newprot, true);
2640 	return pmd;
2641 }
2642 
2643 pgprot_t pmd_pgprot(pmd_t entry)
2644 {
2645 	unsigned long pte = 0;
2646 
2647 	if (pmd_val(entry) & PMD_HUGE_PRESENT)
2648 		pte |= _PAGE_VALID;
2649 
2650 	if (tlb_type == hypervisor) {
2651 		if (pmd_val(entry) & PMD_HUGE_PRESENT)
2652 			pte |= _PAGE_PRESENT_4V;
2653 		if (pmd_val(entry) & PMD_HUGE_EXEC)
2654 			pte |= _PAGE_EXEC_4V;
2655 		if (pmd_val(entry) & PMD_HUGE_WRITE)
2656 			pte |= _PAGE_W_4V;
2657 		if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2658 			pte |= _PAGE_ACCESSED_4V;
2659 		if (pmd_val(entry) & PMD_HUGE_DIRTY)
2660 			pte |= _PAGE_MODIFIED_4V;
2661 		pte |= _PAGE_CP_4V|_PAGE_CV_4V;
2662 	} else {
2663 		if (pmd_val(entry) & PMD_HUGE_PRESENT)
2664 			pte |= _PAGE_PRESENT_4U;
2665 		if (pmd_val(entry) & PMD_HUGE_EXEC)
2666 			pte |= _PAGE_EXEC_4U;
2667 		if (pmd_val(entry) & PMD_HUGE_WRITE)
2668 			pte |= _PAGE_W_4U;
2669 		if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2670 			pte |= _PAGE_ACCESSED_4U;
2671 		if (pmd_val(entry) & PMD_HUGE_DIRTY)
2672 			pte |= _PAGE_MODIFIED_4U;
2673 		pte |= _PAGE_CP_4U|_PAGE_CV_4U;
2674 	}
2675 
2676 	return __pgprot(pte);
2677 }
2678 
2679 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2680 			  pmd_t *pmd)
2681 {
2682 	unsigned long pte, flags;
2683 	struct mm_struct *mm;
2684 	pmd_t entry = *pmd;
2685 	pgprot_t prot;
2686 
2687 	if (!pmd_large(entry) || !pmd_young(entry))
2688 		return;
2689 
2690 	pte = (pmd_val(entry) & ~PMD_HUGE_PROTBITS);
2691 	pte <<= PMD_PADDR_SHIFT;
2692 	pte |= _PAGE_VALID;
2693 
2694 	prot = pmd_pgprot(entry);
2695 
2696 	if (tlb_type == hypervisor)
2697 		pgprot_val(prot) |= _PAGE_SZHUGE_4V;
2698 	else
2699 		pgprot_val(prot) |= _PAGE_SZHUGE_4U;
2700 
2701 	pte |= pgprot_val(prot);
2702 
2703 	mm = vma->vm_mm;
2704 
2705 	spin_lock_irqsave(&mm->context.lock, flags);
2706 
2707 	if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2708 		__update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
2709 					addr, pte);
2710 
2711 	spin_unlock_irqrestore(&mm->context.lock, flags);
2712 }
2713 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2714 
2715 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2716 static void context_reload(void *__data)
2717 {
2718 	struct mm_struct *mm = __data;
2719 
2720 	if (mm == current->mm)
2721 		load_secondary_context(mm);
2722 }
2723 
2724 void hugetlb_setup(struct pt_regs *regs)
2725 {
2726 	struct mm_struct *mm = current->mm;
2727 	struct tsb_config *tp;
2728 
2729 	if (in_atomic() || !mm) {
2730 		const struct exception_table_entry *entry;
2731 
2732 		entry = search_exception_tables(regs->tpc);
2733 		if (entry) {
2734 			regs->tpc = entry->fixup;
2735 			regs->tnpc = regs->tpc + 4;
2736 			return;
2737 		}
2738 		pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2739 		die_if_kernel("HugeTSB in atomic", regs);
2740 	}
2741 
2742 	tp = &mm->context.tsb_block[MM_TSB_HUGE];
2743 	if (likely(tp->tsb == NULL))
2744 		tsb_grow(mm, MM_TSB_HUGE, 0);
2745 
2746 	tsb_context_switch(mm);
2747 	smp_tsb_sync(mm);
2748 
2749 	/* On UltraSPARC-III+ and later, configure the second half of
2750 	 * the Data-TLB for huge pages.
2751 	 */
2752 	if (tlb_type == cheetah_plus) {
2753 		unsigned long ctx;
2754 
2755 		spin_lock(&ctx_alloc_lock);
2756 		ctx = mm->context.sparc64_ctx_val;
2757 		ctx &= ~CTX_PGSZ_MASK;
2758 		ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2759 		ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2760 
2761 		if (ctx != mm->context.sparc64_ctx_val) {
2762 			/* When changing the page size fields, we
2763 			 * must perform a context flush so that no
2764 			 * stale entries match.  This flush must
2765 			 * occur with the original context register
2766 			 * settings.
2767 			 */
2768 			do_flush_tlb_mm(mm);
2769 
2770 			/* Reload the context register of all processors
2771 			 * also executing in this address space.
2772 			 */
2773 			mm->context.sparc64_ctx_val = ctx;
2774 			on_each_cpu(context_reload, mm, 0);
2775 		}
2776 		spin_unlock(&ctx_alloc_lock);
2777 	}
2778 }
2779 #endif
2780