1 /* 2 * arch/sparc64/mm/init.c 3 * 4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #include <linux/extable.h> 9 #include <linux/kernel.h> 10 #include <linux/sched.h> 11 #include <linux/string.h> 12 #include <linux/init.h> 13 #include <linux/bootmem.h> 14 #include <linux/mm.h> 15 #include <linux/hugetlb.h> 16 #include <linux/initrd.h> 17 #include <linux/swap.h> 18 #include <linux/pagemap.h> 19 #include <linux/poison.h> 20 #include <linux/fs.h> 21 #include <linux/seq_file.h> 22 #include <linux/kprobes.h> 23 #include <linux/cache.h> 24 #include <linux/sort.h> 25 #include <linux/ioport.h> 26 #include <linux/percpu.h> 27 #include <linux/memblock.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 31 #include <asm/head.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/pgtable.h> 35 #include <asm/oplib.h> 36 #include <asm/iommu.h> 37 #include <asm/io.h> 38 #include <linux/uaccess.h> 39 #include <asm/mmu_context.h> 40 #include <asm/tlbflush.h> 41 #include <asm/dma.h> 42 #include <asm/starfire.h> 43 #include <asm/tlb.h> 44 #include <asm/spitfire.h> 45 #include <asm/sections.h> 46 #include <asm/tsb.h> 47 #include <asm/hypervisor.h> 48 #include <asm/prom.h> 49 #include <asm/mdesc.h> 50 #include <asm/cpudata.h> 51 #include <asm/setup.h> 52 #include <asm/irq.h> 53 54 #include "init_64.h" 55 56 unsigned long kern_linear_pte_xor[4] __read_mostly; 57 static unsigned long page_cache4v_flag; 58 59 /* A bitmap, two bits for every 256MB of physical memory. These two 60 * bits determine what page size we use for kernel linear 61 * translations. They form an index into kern_linear_pte_xor[]. The 62 * value in the indexed slot is XOR'd with the TLB miss virtual 63 * address to form the resulting TTE. The mapping is: 64 * 65 * 0 ==> 4MB 66 * 1 ==> 256MB 67 * 2 ==> 2GB 68 * 3 ==> 16GB 69 * 70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 71 * support 2GB pages, and hopefully future cpus will support the 16GB 72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 73 * if these larger page sizes are not supported by the cpu. 74 * 75 * It would be nice to determine this from the machine description 76 * 'cpu' properties, but we need to have this table setup before the 77 * MDESC is initialized. 78 */ 79 80 #ifndef CONFIG_DEBUG_PAGEALLOC 81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 82 * Space is allocated for this right after the trap table in 83 * arch/sparc64/kernel/head.S 84 */ 85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 86 #endif 87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 88 89 static unsigned long cpu_pgsz_mask; 90 91 #define MAX_BANKS 1024 92 93 static struct linux_prom64_registers pavail[MAX_BANKS]; 94 static int pavail_ents; 95 96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 97 98 static int cmp_p64(const void *a, const void *b) 99 { 100 const struct linux_prom64_registers *x = a, *y = b; 101 102 if (x->phys_addr > y->phys_addr) 103 return 1; 104 if (x->phys_addr < y->phys_addr) 105 return -1; 106 return 0; 107 } 108 109 static void __init read_obp_memory(const char *property, 110 struct linux_prom64_registers *regs, 111 int *num_ents) 112 { 113 phandle node = prom_finddevice("/memory"); 114 int prop_size = prom_getproplen(node, property); 115 int ents, ret, i; 116 117 ents = prop_size / sizeof(struct linux_prom64_registers); 118 if (ents > MAX_BANKS) { 119 prom_printf("The machine has more %s property entries than " 120 "this kernel can support (%d).\n", 121 property, MAX_BANKS); 122 prom_halt(); 123 } 124 125 ret = prom_getproperty(node, property, (char *) regs, prop_size); 126 if (ret == -1) { 127 prom_printf("Couldn't get %s property from /memory.\n", 128 property); 129 prom_halt(); 130 } 131 132 /* Sanitize what we got from the firmware, by page aligning 133 * everything. 134 */ 135 for (i = 0; i < ents; i++) { 136 unsigned long base, size; 137 138 base = regs[i].phys_addr; 139 size = regs[i].reg_size; 140 141 size &= PAGE_MASK; 142 if (base & ~PAGE_MASK) { 143 unsigned long new_base = PAGE_ALIGN(base); 144 145 size -= new_base - base; 146 if ((long) size < 0L) 147 size = 0UL; 148 base = new_base; 149 } 150 if (size == 0UL) { 151 /* If it is empty, simply get rid of it. 152 * This simplifies the logic of the other 153 * functions that process these arrays. 154 */ 155 memmove(®s[i], ®s[i + 1], 156 (ents - i - 1) * sizeof(regs[0])); 157 i--; 158 ents--; 159 continue; 160 } 161 regs[i].phys_addr = base; 162 regs[i].reg_size = size; 163 } 164 165 *num_ents = ents; 166 167 sort(regs, ents, sizeof(struct linux_prom64_registers), 168 cmp_p64, NULL); 169 } 170 171 /* Kernel physical address base and size in bytes. */ 172 unsigned long kern_base __read_mostly; 173 unsigned long kern_size __read_mostly; 174 175 /* Initial ramdisk setup */ 176 extern unsigned long sparc_ramdisk_image64; 177 extern unsigned int sparc_ramdisk_image; 178 extern unsigned int sparc_ramdisk_size; 179 180 struct page *mem_map_zero __read_mostly; 181 EXPORT_SYMBOL(mem_map_zero); 182 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 184 185 unsigned long sparc64_kern_pri_context __read_mostly; 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 187 unsigned long sparc64_kern_sec_context __read_mostly; 188 189 int num_kernel_image_mappings; 190 191 #ifdef CONFIG_DEBUG_DCFLUSH 192 atomic_t dcpage_flushes = ATOMIC_INIT(0); 193 #ifdef CONFIG_SMP 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 195 #endif 196 #endif 197 198 inline void flush_dcache_page_impl(struct page *page) 199 { 200 BUG_ON(tlb_type == hypervisor); 201 #ifdef CONFIG_DEBUG_DCFLUSH 202 atomic_inc(&dcpage_flushes); 203 #endif 204 205 #ifdef DCACHE_ALIASING_POSSIBLE 206 __flush_dcache_page(page_address(page), 207 ((tlb_type == spitfire) && 208 page_mapping(page) != NULL)); 209 #else 210 if (page_mapping(page) != NULL && 211 tlb_type == spitfire) 212 __flush_icache_page(__pa(page_address(page))); 213 #endif 214 } 215 216 #define PG_dcache_dirty PG_arch_1 217 #define PG_dcache_cpu_shift 32UL 218 #define PG_dcache_cpu_mask \ 219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 220 221 #define dcache_dirty_cpu(page) \ 222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 223 224 static inline void set_dcache_dirty(struct page *page, int this_cpu) 225 { 226 unsigned long mask = this_cpu; 227 unsigned long non_cpu_bits; 228 229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 231 232 __asm__ __volatile__("1:\n\t" 233 "ldx [%2], %%g7\n\t" 234 "and %%g7, %1, %%g1\n\t" 235 "or %%g1, %0, %%g1\n\t" 236 "casx [%2], %%g7, %%g1\n\t" 237 "cmp %%g7, %%g1\n\t" 238 "bne,pn %%xcc, 1b\n\t" 239 " nop" 240 : /* no outputs */ 241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 242 : "g1", "g7"); 243 } 244 245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) 246 { 247 unsigned long mask = (1UL << PG_dcache_dirty); 248 249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 250 "1:\n\t" 251 "ldx [%2], %%g7\n\t" 252 "srlx %%g7, %4, %%g1\n\t" 253 "and %%g1, %3, %%g1\n\t" 254 "cmp %%g1, %0\n\t" 255 "bne,pn %%icc, 2f\n\t" 256 " andn %%g7, %1, %%g1\n\t" 257 "casx [%2], %%g7, %%g1\n\t" 258 "cmp %%g7, %%g1\n\t" 259 "bne,pn %%xcc, 1b\n\t" 260 " nop\n" 261 "2:" 262 : /* no outputs */ 263 : "r" (cpu), "r" (mask), "r" (&page->flags), 264 "i" (PG_dcache_cpu_mask), 265 "i" (PG_dcache_cpu_shift) 266 : "g1", "g7"); 267 } 268 269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 270 { 271 unsigned long tsb_addr = (unsigned long) ent; 272 273 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 274 tsb_addr = __pa(tsb_addr); 275 276 __tsb_insert(tsb_addr, tag, pte); 277 } 278 279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 280 281 static void flush_dcache(unsigned long pfn) 282 { 283 struct page *page; 284 285 page = pfn_to_page(pfn); 286 if (page) { 287 unsigned long pg_flags; 288 289 pg_flags = page->flags; 290 if (pg_flags & (1UL << PG_dcache_dirty)) { 291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 292 PG_dcache_cpu_mask); 293 int this_cpu = get_cpu(); 294 295 /* This is just to optimize away some function calls 296 * in the SMP case. 297 */ 298 if (cpu == this_cpu) 299 flush_dcache_page_impl(page); 300 else 301 smp_flush_dcache_page_impl(page, cpu); 302 303 clear_dcache_dirty_cpu(page, cpu); 304 305 put_cpu(); 306 } 307 } 308 } 309 310 /* mm->context.lock must be held */ 311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 312 unsigned long tsb_hash_shift, unsigned long address, 313 unsigned long tte) 314 { 315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 316 unsigned long tag; 317 318 if (unlikely(!tsb)) 319 return; 320 321 tsb += ((address >> tsb_hash_shift) & 322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 323 tag = (address >> 22UL); 324 tsb_insert(tsb, tag, tte); 325 } 326 327 #ifdef CONFIG_HUGETLB_PAGE 328 static int __init setup_hugepagesz(char *string) 329 { 330 unsigned long long hugepage_size; 331 unsigned int hugepage_shift; 332 unsigned short hv_pgsz_idx; 333 unsigned int hv_pgsz_mask; 334 int rc = 0; 335 336 hugepage_size = memparse(string, &string); 337 hugepage_shift = ilog2(hugepage_size); 338 339 switch (hugepage_shift) { 340 case HPAGE_256MB_SHIFT: 341 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 342 hv_pgsz_idx = HV_PGSZ_IDX_256MB; 343 break; 344 case HPAGE_SHIFT: 345 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 346 hv_pgsz_idx = HV_PGSZ_IDX_4MB; 347 break; 348 case HPAGE_64K_SHIFT: 349 hv_pgsz_mask = HV_PGSZ_MASK_64K; 350 hv_pgsz_idx = HV_PGSZ_IDX_64K; 351 break; 352 default: 353 hv_pgsz_mask = 0; 354 } 355 356 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) { 357 pr_warn("hugepagesz=%llu not supported by MMU.\n", 358 hugepage_size); 359 goto out; 360 } 361 362 hugetlb_add_hstate(hugepage_shift - PAGE_SHIFT); 363 rc = 1; 364 365 out: 366 return rc; 367 } 368 __setup("hugepagesz=", setup_hugepagesz); 369 #endif /* CONFIG_HUGETLB_PAGE */ 370 371 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 372 { 373 struct mm_struct *mm; 374 unsigned long flags; 375 pte_t pte = *ptep; 376 377 if (tlb_type != hypervisor) { 378 unsigned long pfn = pte_pfn(pte); 379 380 if (pfn_valid(pfn)) 381 flush_dcache(pfn); 382 } 383 384 mm = vma->vm_mm; 385 386 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 387 if (!pte_accessible(mm, pte)) 388 return; 389 390 spin_lock_irqsave(&mm->context.lock, flags); 391 392 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 393 if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) && 394 is_hugetlb_pmd(__pmd(pte_val(pte)))) { 395 /* We are fabricating 8MB pages using 4MB real hw pages. */ 396 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 397 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 398 address, pte_val(pte)); 399 } else 400 #endif 401 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 402 address, pte_val(pte)); 403 404 spin_unlock_irqrestore(&mm->context.lock, flags); 405 } 406 407 void flush_dcache_page(struct page *page) 408 { 409 struct address_space *mapping; 410 int this_cpu; 411 412 if (tlb_type == hypervisor) 413 return; 414 415 /* Do not bother with the expensive D-cache flush if it 416 * is merely the zero page. The 'bigcore' testcase in GDB 417 * causes this case to run millions of times. 418 */ 419 if (page == ZERO_PAGE(0)) 420 return; 421 422 this_cpu = get_cpu(); 423 424 mapping = page_mapping(page); 425 if (mapping && !mapping_mapped(mapping)) { 426 int dirty = test_bit(PG_dcache_dirty, &page->flags); 427 if (dirty) { 428 int dirty_cpu = dcache_dirty_cpu(page); 429 430 if (dirty_cpu == this_cpu) 431 goto out; 432 smp_flush_dcache_page_impl(page, dirty_cpu); 433 } 434 set_dcache_dirty(page, this_cpu); 435 } else { 436 /* We could delay the flush for the !page_mapping 437 * case too. But that case is for exec env/arg 438 * pages and those are %99 certainly going to get 439 * faulted into the tlb (and thus flushed) anyways. 440 */ 441 flush_dcache_page_impl(page); 442 } 443 444 out: 445 put_cpu(); 446 } 447 EXPORT_SYMBOL(flush_dcache_page); 448 449 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 450 { 451 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 452 if (tlb_type == spitfire) { 453 unsigned long kaddr; 454 455 /* This code only runs on Spitfire cpus so this is 456 * why we can assume _PAGE_PADDR_4U. 457 */ 458 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 459 unsigned long paddr, mask = _PAGE_PADDR_4U; 460 461 if (kaddr >= PAGE_OFFSET) 462 paddr = kaddr & mask; 463 else { 464 pgd_t *pgdp = pgd_offset_k(kaddr); 465 pud_t *pudp = pud_offset(pgdp, kaddr); 466 pmd_t *pmdp = pmd_offset(pudp, kaddr); 467 pte_t *ptep = pte_offset_kernel(pmdp, kaddr); 468 469 paddr = pte_val(*ptep) & mask; 470 } 471 __flush_icache_page(paddr); 472 } 473 } 474 } 475 EXPORT_SYMBOL(flush_icache_range); 476 477 void mmu_info(struct seq_file *m) 478 { 479 static const char *pgsz_strings[] = { 480 "8K", "64K", "512K", "4MB", "32MB", 481 "256MB", "2GB", "16GB", 482 }; 483 int i, printed; 484 485 if (tlb_type == cheetah) 486 seq_printf(m, "MMU Type\t: Cheetah\n"); 487 else if (tlb_type == cheetah_plus) 488 seq_printf(m, "MMU Type\t: Cheetah+\n"); 489 else if (tlb_type == spitfire) 490 seq_printf(m, "MMU Type\t: Spitfire\n"); 491 else if (tlb_type == hypervisor) 492 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 493 else 494 seq_printf(m, "MMU Type\t: ???\n"); 495 496 seq_printf(m, "MMU PGSZs\t: "); 497 printed = 0; 498 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 499 if (cpu_pgsz_mask & (1UL << i)) { 500 seq_printf(m, "%s%s", 501 printed ? "," : "", pgsz_strings[i]); 502 printed++; 503 } 504 } 505 seq_putc(m, '\n'); 506 507 #ifdef CONFIG_DEBUG_DCFLUSH 508 seq_printf(m, "DCPageFlushes\t: %d\n", 509 atomic_read(&dcpage_flushes)); 510 #ifdef CONFIG_SMP 511 seq_printf(m, "DCPageFlushesXC\t: %d\n", 512 atomic_read(&dcpage_flushes_xcall)); 513 #endif /* CONFIG_SMP */ 514 #endif /* CONFIG_DEBUG_DCFLUSH */ 515 } 516 517 struct linux_prom_translation prom_trans[512] __read_mostly; 518 unsigned int prom_trans_ents __read_mostly; 519 520 unsigned long kern_locked_tte_data; 521 522 /* The obp translations are saved based on 8k pagesize, since obp can 523 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 524 * HI_OBP_ADDRESS range are handled in ktlb.S. 525 */ 526 static inline int in_obp_range(unsigned long vaddr) 527 { 528 return (vaddr >= LOW_OBP_ADDRESS && 529 vaddr < HI_OBP_ADDRESS); 530 } 531 532 static int cmp_ptrans(const void *a, const void *b) 533 { 534 const struct linux_prom_translation *x = a, *y = b; 535 536 if (x->virt > y->virt) 537 return 1; 538 if (x->virt < y->virt) 539 return -1; 540 return 0; 541 } 542 543 /* Read OBP translations property into 'prom_trans[]'. */ 544 static void __init read_obp_translations(void) 545 { 546 int n, node, ents, first, last, i; 547 548 node = prom_finddevice("/virtual-memory"); 549 n = prom_getproplen(node, "translations"); 550 if (unlikely(n == 0 || n == -1)) { 551 prom_printf("prom_mappings: Couldn't get size.\n"); 552 prom_halt(); 553 } 554 if (unlikely(n > sizeof(prom_trans))) { 555 prom_printf("prom_mappings: Size %d is too big.\n", n); 556 prom_halt(); 557 } 558 559 if ((n = prom_getproperty(node, "translations", 560 (char *)&prom_trans[0], 561 sizeof(prom_trans))) == -1) { 562 prom_printf("prom_mappings: Couldn't get property.\n"); 563 prom_halt(); 564 } 565 566 n = n / sizeof(struct linux_prom_translation); 567 568 ents = n; 569 570 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 571 cmp_ptrans, NULL); 572 573 /* Now kick out all the non-OBP entries. */ 574 for (i = 0; i < ents; i++) { 575 if (in_obp_range(prom_trans[i].virt)) 576 break; 577 } 578 first = i; 579 for (; i < ents; i++) { 580 if (!in_obp_range(prom_trans[i].virt)) 581 break; 582 } 583 last = i; 584 585 for (i = 0; i < (last - first); i++) { 586 struct linux_prom_translation *src = &prom_trans[i + first]; 587 struct linux_prom_translation *dest = &prom_trans[i]; 588 589 *dest = *src; 590 } 591 for (; i < ents; i++) { 592 struct linux_prom_translation *dest = &prom_trans[i]; 593 dest->virt = dest->size = dest->data = 0x0UL; 594 } 595 596 prom_trans_ents = last - first; 597 598 if (tlb_type == spitfire) { 599 /* Clear diag TTE bits. */ 600 for (i = 0; i < prom_trans_ents; i++) 601 prom_trans[i].data &= ~0x0003fe0000000000UL; 602 } 603 604 /* Force execute bit on. */ 605 for (i = 0; i < prom_trans_ents; i++) 606 prom_trans[i].data |= (tlb_type == hypervisor ? 607 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 608 } 609 610 static void __init hypervisor_tlb_lock(unsigned long vaddr, 611 unsigned long pte, 612 unsigned long mmu) 613 { 614 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 615 616 if (ret != 0) { 617 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 618 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 619 prom_halt(); 620 } 621 } 622 623 static unsigned long kern_large_tte(unsigned long paddr); 624 625 static void __init remap_kernel(void) 626 { 627 unsigned long phys_page, tte_vaddr, tte_data; 628 int i, tlb_ent = sparc64_highest_locked_tlbent(); 629 630 tte_vaddr = (unsigned long) KERNBASE; 631 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 632 tte_data = kern_large_tte(phys_page); 633 634 kern_locked_tte_data = tte_data; 635 636 /* Now lock us into the TLBs via Hypervisor or OBP. */ 637 if (tlb_type == hypervisor) { 638 for (i = 0; i < num_kernel_image_mappings; i++) { 639 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 640 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 641 tte_vaddr += 0x400000; 642 tte_data += 0x400000; 643 } 644 } else { 645 for (i = 0; i < num_kernel_image_mappings; i++) { 646 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 647 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 648 tte_vaddr += 0x400000; 649 tte_data += 0x400000; 650 } 651 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 652 } 653 if (tlb_type == cheetah_plus) { 654 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 655 CTX_CHEETAH_PLUS_NUC); 656 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 657 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 658 } 659 } 660 661 662 static void __init inherit_prom_mappings(void) 663 { 664 /* Now fixup OBP's idea about where we really are mapped. */ 665 printk("Remapping the kernel... "); 666 remap_kernel(); 667 printk("done.\n"); 668 } 669 670 void prom_world(int enter) 671 { 672 if (!enter) 673 set_fs(get_fs()); 674 675 __asm__ __volatile__("flushw"); 676 } 677 678 void __flush_dcache_range(unsigned long start, unsigned long end) 679 { 680 unsigned long va; 681 682 if (tlb_type == spitfire) { 683 int n = 0; 684 685 for (va = start; va < end; va += 32) { 686 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 687 if (++n >= 512) 688 break; 689 } 690 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 691 start = __pa(start); 692 end = __pa(end); 693 for (va = start; va < end; va += 32) 694 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 695 "membar #Sync" 696 : /* no outputs */ 697 : "r" (va), 698 "i" (ASI_DCACHE_INVALIDATE)); 699 } 700 } 701 EXPORT_SYMBOL(__flush_dcache_range); 702 703 /* get_new_mmu_context() uses "cache + 1". */ 704 DEFINE_SPINLOCK(ctx_alloc_lock); 705 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; 706 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 707 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 708 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 709 710 /* Caller does TLB context flushing on local CPU if necessary. 711 * The caller also ensures that CTX_VALID(mm->context) is false. 712 * 713 * We must be careful about boundary cases so that we never 714 * let the user have CTX 0 (nucleus) or we ever use a CTX 715 * version of zero (and thus NO_CONTEXT would not be caught 716 * by version mis-match tests in mmu_context.h). 717 * 718 * Always invoked with interrupts disabled. 719 */ 720 void get_new_mmu_context(struct mm_struct *mm) 721 { 722 unsigned long ctx, new_ctx; 723 unsigned long orig_pgsz_bits; 724 int new_version; 725 726 spin_lock(&ctx_alloc_lock); 727 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 728 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 729 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 730 new_version = 0; 731 if (new_ctx >= (1 << CTX_NR_BITS)) { 732 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 733 if (new_ctx >= ctx) { 734 int i; 735 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + 736 CTX_FIRST_VERSION; 737 if (new_ctx == 1) 738 new_ctx = CTX_FIRST_VERSION; 739 740 /* Don't call memset, for 16 entries that's just 741 * plain silly... 742 */ 743 mmu_context_bmap[0] = 3; 744 mmu_context_bmap[1] = 0; 745 mmu_context_bmap[2] = 0; 746 mmu_context_bmap[3] = 0; 747 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { 748 mmu_context_bmap[i + 0] = 0; 749 mmu_context_bmap[i + 1] = 0; 750 mmu_context_bmap[i + 2] = 0; 751 mmu_context_bmap[i + 3] = 0; 752 } 753 new_version = 1; 754 goto out; 755 } 756 } 757 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 758 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 759 out: 760 tlb_context_cache = new_ctx; 761 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 762 spin_unlock(&ctx_alloc_lock); 763 764 if (unlikely(new_version)) 765 smp_new_mmu_context_version(); 766 } 767 768 static int numa_enabled = 1; 769 static int numa_debug; 770 771 static int __init early_numa(char *p) 772 { 773 if (!p) 774 return 0; 775 776 if (strstr(p, "off")) 777 numa_enabled = 0; 778 779 if (strstr(p, "debug")) 780 numa_debug = 1; 781 782 return 0; 783 } 784 early_param("numa", early_numa); 785 786 #define numadbg(f, a...) \ 787 do { if (numa_debug) \ 788 printk(KERN_INFO f, ## a); \ 789 } while (0) 790 791 static void __init find_ramdisk(unsigned long phys_base) 792 { 793 #ifdef CONFIG_BLK_DEV_INITRD 794 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 795 unsigned long ramdisk_image; 796 797 /* Older versions of the bootloader only supported a 798 * 32-bit physical address for the ramdisk image 799 * location, stored at sparc_ramdisk_image. Newer 800 * SILO versions set sparc_ramdisk_image to zero and 801 * provide a full 64-bit physical address at 802 * sparc_ramdisk_image64. 803 */ 804 ramdisk_image = sparc_ramdisk_image; 805 if (!ramdisk_image) 806 ramdisk_image = sparc_ramdisk_image64; 807 808 /* Another bootloader quirk. The bootloader normalizes 809 * the physical address to KERNBASE, so we have to 810 * factor that back out and add in the lowest valid 811 * physical page address to get the true physical address. 812 */ 813 ramdisk_image -= KERNBASE; 814 ramdisk_image += phys_base; 815 816 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 817 ramdisk_image, sparc_ramdisk_size); 818 819 initrd_start = ramdisk_image; 820 initrd_end = ramdisk_image + sparc_ramdisk_size; 821 822 memblock_reserve(initrd_start, sparc_ramdisk_size); 823 824 initrd_start += PAGE_OFFSET; 825 initrd_end += PAGE_OFFSET; 826 } 827 #endif 828 } 829 830 struct node_mem_mask { 831 unsigned long mask; 832 unsigned long match; 833 }; 834 static struct node_mem_mask node_masks[MAX_NUMNODES]; 835 static int num_node_masks; 836 837 #ifdef CONFIG_NEED_MULTIPLE_NODES 838 839 struct mdesc_mlgroup { 840 u64 node; 841 u64 latency; 842 u64 match; 843 u64 mask; 844 }; 845 846 static struct mdesc_mlgroup *mlgroups; 847 static int num_mlgroups; 848 849 int numa_cpu_lookup_table[NR_CPUS]; 850 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 851 852 struct mdesc_mblock { 853 u64 base; 854 u64 size; 855 u64 offset; /* RA-to-PA */ 856 }; 857 static struct mdesc_mblock *mblocks; 858 static int num_mblocks; 859 860 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 861 { 862 struct mdesc_mblock *m = NULL; 863 int i; 864 865 for (i = 0; i < num_mblocks; i++) { 866 m = &mblocks[i]; 867 868 if (addr >= m->base && 869 addr < (m->base + m->size)) { 870 break; 871 } 872 } 873 874 return m; 875 } 876 877 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 878 { 879 int prev_nid, new_nid; 880 881 prev_nid = -1; 882 for ( ; start < end; start += PAGE_SIZE) { 883 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 884 struct node_mem_mask *p = &node_masks[new_nid]; 885 886 if ((start & p->mask) == p->match) { 887 if (prev_nid == -1) 888 prev_nid = new_nid; 889 break; 890 } 891 } 892 893 if (new_nid == num_node_masks) { 894 prev_nid = 0; 895 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 896 start); 897 break; 898 } 899 900 if (prev_nid != new_nid) 901 break; 902 } 903 *nid = prev_nid; 904 905 return start > end ? end : start; 906 } 907 908 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 909 { 910 u64 ret_end, pa_start, m_mask, m_match, m_end; 911 struct mdesc_mblock *mblock; 912 int _nid, i; 913 914 if (tlb_type != hypervisor) 915 return memblock_nid_range_sun4u(start, end, nid); 916 917 mblock = addr_to_mblock(start); 918 if (!mblock) { 919 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 920 start); 921 922 _nid = 0; 923 ret_end = end; 924 goto done; 925 } 926 927 pa_start = start + mblock->offset; 928 m_match = 0; 929 m_mask = 0; 930 931 for (_nid = 0; _nid < num_node_masks; _nid++) { 932 struct node_mem_mask *const m = &node_masks[_nid]; 933 934 if ((pa_start & m->mask) == m->match) { 935 m_match = m->match; 936 m_mask = m->mask; 937 break; 938 } 939 } 940 941 if (num_node_masks == _nid) { 942 /* We could not find NUMA group, so default to 0, but lets 943 * search for latency group, so we could calculate the correct 944 * end address that we return 945 */ 946 _nid = 0; 947 948 for (i = 0; i < num_mlgroups; i++) { 949 struct mdesc_mlgroup *const m = &mlgroups[i]; 950 951 if ((pa_start & m->mask) == m->match) { 952 m_match = m->match; 953 m_mask = m->mask; 954 break; 955 } 956 } 957 958 if (i == num_mlgroups) { 959 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 960 start); 961 962 ret_end = end; 963 goto done; 964 } 965 } 966 967 /* 968 * Each latency group has match and mask, and each memory block has an 969 * offset. An address belongs to a latency group if its address matches 970 * the following formula: ((addr + offset) & mask) == match 971 * It is, however, slow to check every single page if it matches a 972 * particular latency group. As optimization we calculate end value by 973 * using bit arithmetics. 974 */ 975 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 976 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 977 ret_end = m_end > end ? end : m_end; 978 979 done: 980 *nid = _nid; 981 return ret_end; 982 } 983 #endif 984 985 /* This must be invoked after performing all of the necessary 986 * memblock_set_node() calls for 'nid'. We need to be able to get 987 * correct data from get_pfn_range_for_nid(). 988 */ 989 static void __init allocate_node_data(int nid) 990 { 991 struct pglist_data *p; 992 unsigned long start_pfn, end_pfn; 993 #ifdef CONFIG_NEED_MULTIPLE_NODES 994 unsigned long paddr; 995 996 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); 997 if (!paddr) { 998 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); 999 prom_halt(); 1000 } 1001 NODE_DATA(nid) = __va(paddr); 1002 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); 1003 1004 NODE_DATA(nid)->node_id = nid; 1005 #endif 1006 1007 p = NODE_DATA(nid); 1008 1009 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1010 p->node_start_pfn = start_pfn; 1011 p->node_spanned_pages = end_pfn - start_pfn; 1012 } 1013 1014 static void init_node_masks_nonnuma(void) 1015 { 1016 #ifdef CONFIG_NEED_MULTIPLE_NODES 1017 int i; 1018 #endif 1019 1020 numadbg("Initializing tables for non-numa.\n"); 1021 1022 node_masks[0].mask = 0; 1023 node_masks[0].match = 0; 1024 num_node_masks = 1; 1025 1026 #ifdef CONFIG_NEED_MULTIPLE_NODES 1027 for (i = 0; i < NR_CPUS; i++) 1028 numa_cpu_lookup_table[i] = 0; 1029 1030 cpumask_setall(&numa_cpumask_lookup_table[0]); 1031 #endif 1032 } 1033 1034 #ifdef CONFIG_NEED_MULTIPLE_NODES 1035 struct pglist_data *node_data[MAX_NUMNODES]; 1036 1037 EXPORT_SYMBOL(numa_cpu_lookup_table); 1038 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1039 EXPORT_SYMBOL(node_data); 1040 1041 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1042 u32 cfg_handle) 1043 { 1044 u64 arc; 1045 1046 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1047 u64 target = mdesc_arc_target(md, arc); 1048 const u64 *val; 1049 1050 val = mdesc_get_property(md, target, 1051 "cfg-handle", NULL); 1052 if (val && *val == cfg_handle) 1053 return 0; 1054 } 1055 return -ENODEV; 1056 } 1057 1058 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1059 u32 cfg_handle) 1060 { 1061 u64 arc, candidate, best_latency = ~(u64)0; 1062 1063 candidate = MDESC_NODE_NULL; 1064 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1065 u64 target = mdesc_arc_target(md, arc); 1066 const char *name = mdesc_node_name(md, target); 1067 const u64 *val; 1068 1069 if (strcmp(name, "pio-latency-group")) 1070 continue; 1071 1072 val = mdesc_get_property(md, target, "latency", NULL); 1073 if (!val) 1074 continue; 1075 1076 if (*val < best_latency) { 1077 candidate = target; 1078 best_latency = *val; 1079 } 1080 } 1081 1082 if (candidate == MDESC_NODE_NULL) 1083 return -ENODEV; 1084 1085 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1086 } 1087 1088 int of_node_to_nid(struct device_node *dp) 1089 { 1090 const struct linux_prom64_registers *regs; 1091 struct mdesc_handle *md; 1092 u32 cfg_handle; 1093 int count, nid; 1094 u64 grp; 1095 1096 /* This is the right thing to do on currently supported 1097 * SUN4U NUMA platforms as well, as the PCI controller does 1098 * not sit behind any particular memory controller. 1099 */ 1100 if (!mlgroups) 1101 return -1; 1102 1103 regs = of_get_property(dp, "reg", NULL); 1104 if (!regs) 1105 return -1; 1106 1107 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1108 1109 md = mdesc_grab(); 1110 1111 count = 0; 1112 nid = -1; 1113 mdesc_for_each_node_by_name(md, grp, "group") { 1114 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1115 nid = count; 1116 break; 1117 } 1118 count++; 1119 } 1120 1121 mdesc_release(md); 1122 1123 return nid; 1124 } 1125 1126 static void __init add_node_ranges(void) 1127 { 1128 struct memblock_region *reg; 1129 unsigned long prev_max; 1130 1131 memblock_resized: 1132 prev_max = memblock.memory.max; 1133 1134 for_each_memblock(memory, reg) { 1135 unsigned long size = reg->size; 1136 unsigned long start, end; 1137 1138 start = reg->base; 1139 end = start + size; 1140 while (start < end) { 1141 unsigned long this_end; 1142 int nid; 1143 1144 this_end = memblock_nid_range(start, end, &nid); 1145 1146 numadbg("Setting memblock NUMA node nid[%d] " 1147 "start[%lx] end[%lx]\n", 1148 nid, start, this_end); 1149 1150 memblock_set_node(start, this_end - start, 1151 &memblock.memory, nid); 1152 if (memblock.memory.max != prev_max) 1153 goto memblock_resized; 1154 start = this_end; 1155 } 1156 } 1157 } 1158 1159 static int __init grab_mlgroups(struct mdesc_handle *md) 1160 { 1161 unsigned long paddr; 1162 int count = 0; 1163 u64 node; 1164 1165 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1166 count++; 1167 if (!count) 1168 return -ENOENT; 1169 1170 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup), 1171 SMP_CACHE_BYTES); 1172 if (!paddr) 1173 return -ENOMEM; 1174 1175 mlgroups = __va(paddr); 1176 num_mlgroups = count; 1177 1178 count = 0; 1179 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1180 struct mdesc_mlgroup *m = &mlgroups[count++]; 1181 const u64 *val; 1182 1183 m->node = node; 1184 1185 val = mdesc_get_property(md, node, "latency", NULL); 1186 m->latency = *val; 1187 val = mdesc_get_property(md, node, "address-match", NULL); 1188 m->match = *val; 1189 val = mdesc_get_property(md, node, "address-mask", NULL); 1190 m->mask = *val; 1191 1192 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1193 "match[%llx] mask[%llx]\n", 1194 count - 1, m->node, m->latency, m->match, m->mask); 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int __init grab_mblocks(struct mdesc_handle *md) 1201 { 1202 unsigned long paddr; 1203 int count = 0; 1204 u64 node; 1205 1206 mdesc_for_each_node_by_name(md, node, "mblock") 1207 count++; 1208 if (!count) 1209 return -ENOENT; 1210 1211 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock), 1212 SMP_CACHE_BYTES); 1213 if (!paddr) 1214 return -ENOMEM; 1215 1216 mblocks = __va(paddr); 1217 num_mblocks = count; 1218 1219 count = 0; 1220 mdesc_for_each_node_by_name(md, node, "mblock") { 1221 struct mdesc_mblock *m = &mblocks[count++]; 1222 const u64 *val; 1223 1224 val = mdesc_get_property(md, node, "base", NULL); 1225 m->base = *val; 1226 val = mdesc_get_property(md, node, "size", NULL); 1227 m->size = *val; 1228 val = mdesc_get_property(md, node, 1229 "address-congruence-offset", NULL); 1230 1231 /* The address-congruence-offset property is optional. 1232 * Explicity zero it be identifty this. 1233 */ 1234 if (val) 1235 m->offset = *val; 1236 else 1237 m->offset = 0UL; 1238 1239 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1240 count - 1, m->base, m->size, m->offset); 1241 } 1242 1243 return 0; 1244 } 1245 1246 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1247 u64 grp, cpumask_t *mask) 1248 { 1249 u64 arc; 1250 1251 cpumask_clear(mask); 1252 1253 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1254 u64 target = mdesc_arc_target(md, arc); 1255 const char *name = mdesc_node_name(md, target); 1256 const u64 *id; 1257 1258 if (strcmp(name, "cpu")) 1259 continue; 1260 id = mdesc_get_property(md, target, "id", NULL); 1261 if (*id < nr_cpu_ids) 1262 cpumask_set_cpu(*id, mask); 1263 } 1264 } 1265 1266 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1267 { 1268 int i; 1269 1270 for (i = 0; i < num_mlgroups; i++) { 1271 struct mdesc_mlgroup *m = &mlgroups[i]; 1272 if (m->node == node) 1273 return m; 1274 } 1275 return NULL; 1276 } 1277 1278 int __node_distance(int from, int to) 1279 { 1280 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1281 pr_warn("Returning default NUMA distance value for %d->%d\n", 1282 from, to); 1283 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1284 } 1285 return numa_latency[from][to]; 1286 } 1287 1288 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1289 { 1290 int i; 1291 1292 for (i = 0; i < MAX_NUMNODES; i++) { 1293 struct node_mem_mask *n = &node_masks[i]; 1294 1295 if ((grp->mask == n->mask) && (grp->match == n->match)) 1296 break; 1297 } 1298 return i; 1299 } 1300 1301 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1302 u64 grp, int index) 1303 { 1304 u64 arc; 1305 1306 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1307 int tnode; 1308 u64 target = mdesc_arc_target(md, arc); 1309 struct mdesc_mlgroup *m = find_mlgroup(target); 1310 1311 if (!m) 1312 continue; 1313 tnode = find_best_numa_node_for_mlgroup(m); 1314 if (tnode == MAX_NUMNODES) 1315 continue; 1316 numa_latency[index][tnode] = m->latency; 1317 } 1318 } 1319 1320 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1321 int index) 1322 { 1323 struct mdesc_mlgroup *candidate = NULL; 1324 u64 arc, best_latency = ~(u64)0; 1325 struct node_mem_mask *n; 1326 1327 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1328 u64 target = mdesc_arc_target(md, arc); 1329 struct mdesc_mlgroup *m = find_mlgroup(target); 1330 if (!m) 1331 continue; 1332 if (m->latency < best_latency) { 1333 candidate = m; 1334 best_latency = m->latency; 1335 } 1336 } 1337 if (!candidate) 1338 return -ENOENT; 1339 1340 if (num_node_masks != index) { 1341 printk(KERN_ERR "Inconsistent NUMA state, " 1342 "index[%d] != num_node_masks[%d]\n", 1343 index, num_node_masks); 1344 return -EINVAL; 1345 } 1346 1347 n = &node_masks[num_node_masks++]; 1348 1349 n->mask = candidate->mask; 1350 n->match = candidate->match; 1351 1352 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1353 index, n->mask, n->match, candidate->latency); 1354 1355 return 0; 1356 } 1357 1358 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1359 int index) 1360 { 1361 cpumask_t mask; 1362 int cpu; 1363 1364 numa_parse_mdesc_group_cpus(md, grp, &mask); 1365 1366 for_each_cpu(cpu, &mask) 1367 numa_cpu_lookup_table[cpu] = index; 1368 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1369 1370 if (numa_debug) { 1371 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1372 for_each_cpu(cpu, &mask) 1373 printk("%d ", cpu); 1374 printk("]\n"); 1375 } 1376 1377 return numa_attach_mlgroup(md, grp, index); 1378 } 1379 1380 static int __init numa_parse_mdesc(void) 1381 { 1382 struct mdesc_handle *md = mdesc_grab(); 1383 int i, j, err, count; 1384 u64 node; 1385 1386 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1387 if (node == MDESC_NODE_NULL) { 1388 mdesc_release(md); 1389 return -ENOENT; 1390 } 1391 1392 err = grab_mblocks(md); 1393 if (err < 0) 1394 goto out; 1395 1396 err = grab_mlgroups(md); 1397 if (err < 0) 1398 goto out; 1399 1400 count = 0; 1401 mdesc_for_each_node_by_name(md, node, "group") { 1402 err = numa_parse_mdesc_group(md, node, count); 1403 if (err < 0) 1404 break; 1405 count++; 1406 } 1407 1408 count = 0; 1409 mdesc_for_each_node_by_name(md, node, "group") { 1410 find_numa_latencies_for_group(md, node, count); 1411 count++; 1412 } 1413 1414 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1415 for (i = 0; i < MAX_NUMNODES; i++) { 1416 u64 self_latency = numa_latency[i][i]; 1417 1418 for (j = 0; j < MAX_NUMNODES; j++) { 1419 numa_latency[i][j] = 1420 (numa_latency[i][j] * LOCAL_DISTANCE) / 1421 self_latency; 1422 } 1423 } 1424 1425 add_node_ranges(); 1426 1427 for (i = 0; i < num_node_masks; i++) { 1428 allocate_node_data(i); 1429 node_set_online(i); 1430 } 1431 1432 err = 0; 1433 out: 1434 mdesc_release(md); 1435 return err; 1436 } 1437 1438 static int __init numa_parse_jbus(void) 1439 { 1440 unsigned long cpu, index; 1441 1442 /* NUMA node id is encoded in bits 36 and higher, and there is 1443 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1444 */ 1445 index = 0; 1446 for_each_present_cpu(cpu) { 1447 numa_cpu_lookup_table[cpu] = index; 1448 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1449 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1450 node_masks[index].match = cpu << 36UL; 1451 1452 index++; 1453 } 1454 num_node_masks = index; 1455 1456 add_node_ranges(); 1457 1458 for (index = 0; index < num_node_masks; index++) { 1459 allocate_node_data(index); 1460 node_set_online(index); 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int __init numa_parse_sun4u(void) 1467 { 1468 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1469 unsigned long ver; 1470 1471 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1472 if ((ver >> 32UL) == __JALAPENO_ID || 1473 (ver >> 32UL) == __SERRANO_ID) 1474 return numa_parse_jbus(); 1475 } 1476 return -1; 1477 } 1478 1479 static int __init bootmem_init_numa(void) 1480 { 1481 int i, j; 1482 int err = -1; 1483 1484 numadbg("bootmem_init_numa()\n"); 1485 1486 /* Some sane defaults for numa latency values */ 1487 for (i = 0; i < MAX_NUMNODES; i++) { 1488 for (j = 0; j < MAX_NUMNODES; j++) 1489 numa_latency[i][j] = (i == j) ? 1490 LOCAL_DISTANCE : REMOTE_DISTANCE; 1491 } 1492 1493 if (numa_enabled) { 1494 if (tlb_type == hypervisor) 1495 err = numa_parse_mdesc(); 1496 else 1497 err = numa_parse_sun4u(); 1498 } 1499 return err; 1500 } 1501 1502 #else 1503 1504 static int bootmem_init_numa(void) 1505 { 1506 return -1; 1507 } 1508 1509 #endif 1510 1511 static void __init bootmem_init_nonnuma(void) 1512 { 1513 unsigned long top_of_ram = memblock_end_of_DRAM(); 1514 unsigned long total_ram = memblock_phys_mem_size(); 1515 1516 numadbg("bootmem_init_nonnuma()\n"); 1517 1518 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1519 top_of_ram, total_ram); 1520 printk(KERN_INFO "Memory hole size: %ldMB\n", 1521 (top_of_ram - total_ram) >> 20); 1522 1523 init_node_masks_nonnuma(); 1524 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0); 1525 allocate_node_data(0); 1526 node_set_online(0); 1527 } 1528 1529 static unsigned long __init bootmem_init(unsigned long phys_base) 1530 { 1531 unsigned long end_pfn; 1532 1533 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1534 max_pfn = max_low_pfn = end_pfn; 1535 min_low_pfn = (phys_base >> PAGE_SHIFT); 1536 1537 if (bootmem_init_numa() < 0) 1538 bootmem_init_nonnuma(); 1539 1540 /* Dump memblock with node info. */ 1541 memblock_dump_all(); 1542 1543 /* XXX cpu notifier XXX */ 1544 1545 sparse_memory_present_with_active_regions(MAX_NUMNODES); 1546 sparse_init(); 1547 1548 return end_pfn; 1549 } 1550 1551 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1552 static int pall_ents __initdata; 1553 1554 static unsigned long max_phys_bits = 40; 1555 1556 bool kern_addr_valid(unsigned long addr) 1557 { 1558 pgd_t *pgd; 1559 pud_t *pud; 1560 pmd_t *pmd; 1561 pte_t *pte; 1562 1563 if ((long)addr < 0L) { 1564 unsigned long pa = __pa(addr); 1565 1566 if ((addr >> max_phys_bits) != 0UL) 1567 return false; 1568 1569 return pfn_valid(pa >> PAGE_SHIFT); 1570 } 1571 1572 if (addr >= (unsigned long) KERNBASE && 1573 addr < (unsigned long)&_end) 1574 return true; 1575 1576 pgd = pgd_offset_k(addr); 1577 if (pgd_none(*pgd)) 1578 return 0; 1579 1580 pud = pud_offset(pgd, addr); 1581 if (pud_none(*pud)) 1582 return 0; 1583 1584 if (pud_large(*pud)) 1585 return pfn_valid(pud_pfn(*pud)); 1586 1587 pmd = pmd_offset(pud, addr); 1588 if (pmd_none(*pmd)) 1589 return 0; 1590 1591 if (pmd_large(*pmd)) 1592 return pfn_valid(pmd_pfn(*pmd)); 1593 1594 pte = pte_offset_kernel(pmd, addr); 1595 if (pte_none(*pte)) 1596 return 0; 1597 1598 return pfn_valid(pte_pfn(*pte)); 1599 } 1600 EXPORT_SYMBOL(kern_addr_valid); 1601 1602 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1603 unsigned long vend, 1604 pud_t *pud) 1605 { 1606 const unsigned long mask16gb = (1UL << 34) - 1UL; 1607 u64 pte_val = vstart; 1608 1609 /* Each PUD is 8GB */ 1610 if ((vstart & mask16gb) || 1611 (vend - vstart <= mask16gb)) { 1612 pte_val ^= kern_linear_pte_xor[2]; 1613 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1614 1615 return vstart + PUD_SIZE; 1616 } 1617 1618 pte_val ^= kern_linear_pte_xor[3]; 1619 pte_val |= _PAGE_PUD_HUGE; 1620 1621 vend = vstart + mask16gb + 1UL; 1622 while (vstart < vend) { 1623 pud_val(*pud) = pte_val; 1624 1625 pte_val += PUD_SIZE; 1626 vstart += PUD_SIZE; 1627 pud++; 1628 } 1629 return vstart; 1630 } 1631 1632 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1633 bool guard) 1634 { 1635 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1636 return true; 1637 1638 return false; 1639 } 1640 1641 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1642 unsigned long vend, 1643 pmd_t *pmd) 1644 { 1645 const unsigned long mask256mb = (1UL << 28) - 1UL; 1646 const unsigned long mask2gb = (1UL << 31) - 1UL; 1647 u64 pte_val = vstart; 1648 1649 /* Each PMD is 8MB */ 1650 if ((vstart & mask256mb) || 1651 (vend - vstart <= mask256mb)) { 1652 pte_val ^= kern_linear_pte_xor[0]; 1653 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1654 1655 return vstart + PMD_SIZE; 1656 } 1657 1658 if ((vstart & mask2gb) || 1659 (vend - vstart <= mask2gb)) { 1660 pte_val ^= kern_linear_pte_xor[1]; 1661 pte_val |= _PAGE_PMD_HUGE; 1662 vend = vstart + mask256mb + 1UL; 1663 } else { 1664 pte_val ^= kern_linear_pte_xor[2]; 1665 pte_val |= _PAGE_PMD_HUGE; 1666 vend = vstart + mask2gb + 1UL; 1667 } 1668 1669 while (vstart < vend) { 1670 pmd_val(*pmd) = pte_val; 1671 1672 pte_val += PMD_SIZE; 1673 vstart += PMD_SIZE; 1674 pmd++; 1675 } 1676 1677 return vstart; 1678 } 1679 1680 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1681 bool guard) 1682 { 1683 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1684 return true; 1685 1686 return false; 1687 } 1688 1689 static unsigned long __ref kernel_map_range(unsigned long pstart, 1690 unsigned long pend, pgprot_t prot, 1691 bool use_huge) 1692 { 1693 unsigned long vstart = PAGE_OFFSET + pstart; 1694 unsigned long vend = PAGE_OFFSET + pend; 1695 unsigned long alloc_bytes = 0UL; 1696 1697 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1698 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1699 vstart, vend); 1700 prom_halt(); 1701 } 1702 1703 while (vstart < vend) { 1704 unsigned long this_end, paddr = __pa(vstart); 1705 pgd_t *pgd = pgd_offset_k(vstart); 1706 pud_t *pud; 1707 pmd_t *pmd; 1708 pte_t *pte; 1709 1710 if (pgd_none(*pgd)) { 1711 pud_t *new; 1712 1713 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1714 alloc_bytes += PAGE_SIZE; 1715 pgd_populate(&init_mm, pgd, new); 1716 } 1717 pud = pud_offset(pgd, vstart); 1718 if (pud_none(*pud)) { 1719 pmd_t *new; 1720 1721 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1722 vstart = kernel_map_hugepud(vstart, vend, pud); 1723 continue; 1724 } 1725 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1726 alloc_bytes += PAGE_SIZE; 1727 pud_populate(&init_mm, pud, new); 1728 } 1729 1730 pmd = pmd_offset(pud, vstart); 1731 if (pmd_none(*pmd)) { 1732 pte_t *new; 1733 1734 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1735 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1736 continue; 1737 } 1738 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1739 alloc_bytes += PAGE_SIZE; 1740 pmd_populate_kernel(&init_mm, pmd, new); 1741 } 1742 1743 pte = pte_offset_kernel(pmd, vstart); 1744 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1745 if (this_end > vend) 1746 this_end = vend; 1747 1748 while (vstart < this_end) { 1749 pte_val(*pte) = (paddr | pgprot_val(prot)); 1750 1751 vstart += PAGE_SIZE; 1752 paddr += PAGE_SIZE; 1753 pte++; 1754 } 1755 } 1756 1757 return alloc_bytes; 1758 } 1759 1760 static void __init flush_all_kernel_tsbs(void) 1761 { 1762 int i; 1763 1764 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1765 struct tsb *ent = &swapper_tsb[i]; 1766 1767 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1768 } 1769 #ifndef CONFIG_DEBUG_PAGEALLOC 1770 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1771 struct tsb *ent = &swapper_4m_tsb[i]; 1772 1773 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1774 } 1775 #endif 1776 } 1777 1778 extern unsigned int kvmap_linear_patch[1]; 1779 1780 static void __init kernel_physical_mapping_init(void) 1781 { 1782 unsigned long i, mem_alloced = 0UL; 1783 bool use_huge = true; 1784 1785 #ifdef CONFIG_DEBUG_PAGEALLOC 1786 use_huge = false; 1787 #endif 1788 for (i = 0; i < pall_ents; i++) { 1789 unsigned long phys_start, phys_end; 1790 1791 phys_start = pall[i].phys_addr; 1792 phys_end = phys_start + pall[i].reg_size; 1793 1794 mem_alloced += kernel_map_range(phys_start, phys_end, 1795 PAGE_KERNEL, use_huge); 1796 } 1797 1798 printk("Allocated %ld bytes for kernel page tables.\n", 1799 mem_alloced); 1800 1801 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1802 flushi(&kvmap_linear_patch[0]); 1803 1804 flush_all_kernel_tsbs(); 1805 1806 __flush_tlb_all(); 1807 } 1808 1809 #ifdef CONFIG_DEBUG_PAGEALLOC 1810 void __kernel_map_pages(struct page *page, int numpages, int enable) 1811 { 1812 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1813 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1814 1815 kernel_map_range(phys_start, phys_end, 1816 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1817 1818 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1819 PAGE_OFFSET + phys_end); 1820 1821 /* we should perform an IPI and flush all tlbs, 1822 * but that can deadlock->flush only current cpu. 1823 */ 1824 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1825 PAGE_OFFSET + phys_end); 1826 } 1827 #endif 1828 1829 unsigned long __init find_ecache_flush_span(unsigned long size) 1830 { 1831 int i; 1832 1833 for (i = 0; i < pavail_ents; i++) { 1834 if (pavail[i].reg_size >= size) 1835 return pavail[i].phys_addr; 1836 } 1837 1838 return ~0UL; 1839 } 1840 1841 unsigned long PAGE_OFFSET; 1842 EXPORT_SYMBOL(PAGE_OFFSET); 1843 1844 unsigned long VMALLOC_END = 0x0000010000000000UL; 1845 EXPORT_SYMBOL(VMALLOC_END); 1846 1847 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1848 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1849 1850 static void __init setup_page_offset(void) 1851 { 1852 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1853 /* Cheetah/Panther support a full 64-bit virtual 1854 * address, so we can use all that our page tables 1855 * support. 1856 */ 1857 sparc64_va_hole_top = 0xfff0000000000000UL; 1858 sparc64_va_hole_bottom = 0x0010000000000000UL; 1859 1860 max_phys_bits = 42; 1861 } else if (tlb_type == hypervisor) { 1862 switch (sun4v_chip_type) { 1863 case SUN4V_CHIP_NIAGARA1: 1864 case SUN4V_CHIP_NIAGARA2: 1865 /* T1 and T2 support 48-bit virtual addresses. */ 1866 sparc64_va_hole_top = 0xffff800000000000UL; 1867 sparc64_va_hole_bottom = 0x0000800000000000UL; 1868 1869 max_phys_bits = 39; 1870 break; 1871 case SUN4V_CHIP_NIAGARA3: 1872 /* T3 supports 48-bit virtual addresses. */ 1873 sparc64_va_hole_top = 0xffff800000000000UL; 1874 sparc64_va_hole_bottom = 0x0000800000000000UL; 1875 1876 max_phys_bits = 43; 1877 break; 1878 case SUN4V_CHIP_NIAGARA4: 1879 case SUN4V_CHIP_NIAGARA5: 1880 case SUN4V_CHIP_SPARC64X: 1881 case SUN4V_CHIP_SPARC_M6: 1882 /* T4 and later support 52-bit virtual addresses. */ 1883 sparc64_va_hole_top = 0xfff8000000000000UL; 1884 sparc64_va_hole_bottom = 0x0008000000000000UL; 1885 max_phys_bits = 47; 1886 break; 1887 case SUN4V_CHIP_SPARC_M7: 1888 case SUN4V_CHIP_SPARC_SN: 1889 default: 1890 /* M7 and later support 52-bit virtual addresses. */ 1891 sparc64_va_hole_top = 0xfff8000000000000UL; 1892 sparc64_va_hole_bottom = 0x0008000000000000UL; 1893 max_phys_bits = 49; 1894 break; 1895 } 1896 } 1897 1898 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 1899 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 1900 max_phys_bits); 1901 prom_halt(); 1902 } 1903 1904 PAGE_OFFSET = sparc64_va_hole_top; 1905 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 1906 (sparc64_va_hole_bottom >> 2)); 1907 1908 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 1909 PAGE_OFFSET, max_phys_bits); 1910 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 1911 VMALLOC_START, VMALLOC_END); 1912 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 1913 VMEMMAP_BASE, VMEMMAP_BASE << 1); 1914 } 1915 1916 static void __init tsb_phys_patch(void) 1917 { 1918 struct tsb_ldquad_phys_patch_entry *pquad; 1919 struct tsb_phys_patch_entry *p; 1920 1921 pquad = &__tsb_ldquad_phys_patch; 1922 while (pquad < &__tsb_ldquad_phys_patch_end) { 1923 unsigned long addr = pquad->addr; 1924 1925 if (tlb_type == hypervisor) 1926 *(unsigned int *) addr = pquad->sun4v_insn; 1927 else 1928 *(unsigned int *) addr = pquad->sun4u_insn; 1929 wmb(); 1930 __asm__ __volatile__("flush %0" 1931 : /* no outputs */ 1932 : "r" (addr)); 1933 1934 pquad++; 1935 } 1936 1937 p = &__tsb_phys_patch; 1938 while (p < &__tsb_phys_patch_end) { 1939 unsigned long addr = p->addr; 1940 1941 *(unsigned int *) addr = p->insn; 1942 wmb(); 1943 __asm__ __volatile__("flush %0" 1944 : /* no outputs */ 1945 : "r" (addr)); 1946 1947 p++; 1948 } 1949 } 1950 1951 /* Don't mark as init, we give this to the Hypervisor. */ 1952 #ifndef CONFIG_DEBUG_PAGEALLOC 1953 #define NUM_KTSB_DESCR 2 1954 #else 1955 #define NUM_KTSB_DESCR 1 1956 #endif 1957 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 1958 1959 /* The swapper TSBs are loaded with a base sequence of: 1960 * 1961 * sethi %uhi(SYMBOL), REG1 1962 * sethi %hi(SYMBOL), REG2 1963 * or REG1, %ulo(SYMBOL), REG1 1964 * or REG2, %lo(SYMBOL), REG2 1965 * sllx REG1, 32, REG1 1966 * or REG1, REG2, REG1 1967 * 1968 * When we use physical addressing for the TSB accesses, we patch the 1969 * first four instructions in the above sequence. 1970 */ 1971 1972 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 1973 { 1974 unsigned long high_bits, low_bits; 1975 1976 high_bits = (pa >> 32) & 0xffffffff; 1977 low_bits = (pa >> 0) & 0xffffffff; 1978 1979 while (start < end) { 1980 unsigned int *ia = (unsigned int *)(unsigned long)*start; 1981 1982 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 1983 __asm__ __volatile__("flush %0" : : "r" (ia)); 1984 1985 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 1986 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 1987 1988 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 1989 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 1990 1991 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 1992 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 1993 1994 start++; 1995 } 1996 } 1997 1998 static void ktsb_phys_patch(void) 1999 { 2000 extern unsigned int __swapper_tsb_phys_patch; 2001 extern unsigned int __swapper_tsb_phys_patch_end; 2002 unsigned long ktsb_pa; 2003 2004 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2005 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2006 &__swapper_tsb_phys_patch_end, ktsb_pa); 2007 #ifndef CONFIG_DEBUG_PAGEALLOC 2008 { 2009 extern unsigned int __swapper_4m_tsb_phys_patch; 2010 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2011 ktsb_pa = (kern_base + 2012 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2013 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2014 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2015 } 2016 #endif 2017 } 2018 2019 static void __init sun4v_ktsb_init(void) 2020 { 2021 unsigned long ktsb_pa; 2022 2023 /* First KTSB for PAGE_SIZE mappings. */ 2024 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2025 2026 switch (PAGE_SIZE) { 2027 case 8 * 1024: 2028 default: 2029 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2030 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2031 break; 2032 2033 case 64 * 1024: 2034 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2035 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2036 break; 2037 2038 case 512 * 1024: 2039 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2040 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2041 break; 2042 2043 case 4 * 1024 * 1024: 2044 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2045 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2046 break; 2047 } 2048 2049 ktsb_descr[0].assoc = 1; 2050 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2051 ktsb_descr[0].ctx_idx = 0; 2052 ktsb_descr[0].tsb_base = ktsb_pa; 2053 ktsb_descr[0].resv = 0; 2054 2055 #ifndef CONFIG_DEBUG_PAGEALLOC 2056 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2057 ktsb_pa = (kern_base + 2058 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2059 2060 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2061 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2062 HV_PGSZ_MASK_256MB | 2063 HV_PGSZ_MASK_2GB | 2064 HV_PGSZ_MASK_16GB) & 2065 cpu_pgsz_mask); 2066 ktsb_descr[1].assoc = 1; 2067 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2068 ktsb_descr[1].ctx_idx = 0; 2069 ktsb_descr[1].tsb_base = ktsb_pa; 2070 ktsb_descr[1].resv = 0; 2071 #endif 2072 } 2073 2074 void sun4v_ktsb_register(void) 2075 { 2076 unsigned long pa, ret; 2077 2078 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2079 2080 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2081 if (ret != 0) { 2082 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2083 "errors with %lx\n", pa, ret); 2084 prom_halt(); 2085 } 2086 } 2087 2088 static void __init sun4u_linear_pte_xor_finalize(void) 2089 { 2090 #ifndef CONFIG_DEBUG_PAGEALLOC 2091 /* This is where we would add Panther support for 2092 * 32MB and 256MB pages. 2093 */ 2094 #endif 2095 } 2096 2097 static void __init sun4v_linear_pte_xor_finalize(void) 2098 { 2099 unsigned long pagecv_flag; 2100 2101 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2102 * enables MCD error. Do not set bit 9 on M7 processor. 2103 */ 2104 switch (sun4v_chip_type) { 2105 case SUN4V_CHIP_SPARC_M7: 2106 case SUN4V_CHIP_SPARC_SN: 2107 pagecv_flag = 0x00; 2108 break; 2109 default: 2110 pagecv_flag = _PAGE_CV_4V; 2111 break; 2112 } 2113 #ifndef CONFIG_DEBUG_PAGEALLOC 2114 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2115 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2116 PAGE_OFFSET; 2117 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2118 _PAGE_P_4V | _PAGE_W_4V); 2119 } else { 2120 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2121 } 2122 2123 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2124 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2125 PAGE_OFFSET; 2126 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2127 _PAGE_P_4V | _PAGE_W_4V); 2128 } else { 2129 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2130 } 2131 2132 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2133 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2134 PAGE_OFFSET; 2135 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2136 _PAGE_P_4V | _PAGE_W_4V); 2137 } else { 2138 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2139 } 2140 #endif 2141 } 2142 2143 /* paging_init() sets up the page tables */ 2144 2145 static unsigned long last_valid_pfn; 2146 2147 static void sun4u_pgprot_init(void); 2148 static void sun4v_pgprot_init(void); 2149 2150 static phys_addr_t __init available_memory(void) 2151 { 2152 phys_addr_t available = 0ULL; 2153 phys_addr_t pa_start, pa_end; 2154 u64 i; 2155 2156 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, 2157 &pa_end, NULL) 2158 available = available + (pa_end - pa_start); 2159 2160 return available; 2161 } 2162 2163 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2164 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2165 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2166 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2167 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2168 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2169 2170 /* We need to exclude reserved regions. This exclusion will include 2171 * vmlinux and initrd. To be more precise the initrd size could be used to 2172 * compute a new lower limit because it is freed later during initialization. 2173 */ 2174 static void __init reduce_memory(phys_addr_t limit_ram) 2175 { 2176 phys_addr_t avail_ram = available_memory(); 2177 phys_addr_t pa_start, pa_end; 2178 u64 i; 2179 2180 if (limit_ram >= avail_ram) 2181 return; 2182 2183 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, 2184 &pa_end, NULL) { 2185 phys_addr_t region_size = pa_end - pa_start; 2186 phys_addr_t clip_start = pa_start; 2187 2188 avail_ram = avail_ram - region_size; 2189 /* Are we consuming too much? */ 2190 if (avail_ram < limit_ram) { 2191 phys_addr_t give_back = limit_ram - avail_ram; 2192 2193 region_size = region_size - give_back; 2194 clip_start = clip_start + give_back; 2195 } 2196 2197 memblock_remove(clip_start, region_size); 2198 2199 if (avail_ram <= limit_ram) 2200 break; 2201 i = 0UL; 2202 } 2203 } 2204 2205 void __init paging_init(void) 2206 { 2207 unsigned long end_pfn, shift, phys_base; 2208 unsigned long real_end, i; 2209 2210 setup_page_offset(); 2211 2212 /* These build time checkes make sure that the dcache_dirty_cpu() 2213 * page->flags usage will work. 2214 * 2215 * When a page gets marked as dcache-dirty, we store the 2216 * cpu number starting at bit 32 in the page->flags. Also, 2217 * functions like clear_dcache_dirty_cpu use the cpu mask 2218 * in 13-bit signed-immediate instruction fields. 2219 */ 2220 2221 /* 2222 * Page flags must not reach into upper 32 bits that are used 2223 * for the cpu number 2224 */ 2225 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2226 2227 /* 2228 * The bit fields placed in the high range must not reach below 2229 * the 32 bit boundary. Otherwise we cannot place the cpu field 2230 * at the 32 bit boundary. 2231 */ 2232 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2233 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2234 2235 BUILD_BUG_ON(NR_CPUS > 4096); 2236 2237 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2238 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2239 2240 /* Invalidate both kernel TSBs. */ 2241 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2242 #ifndef CONFIG_DEBUG_PAGEALLOC 2243 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2244 #endif 2245 2246 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2247 * bit on M7 processor. This is a conflicting usage of the same 2248 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2249 * Detection error on all pages and this will lead to problems 2250 * later. Kernel does not run with MCD enabled and hence rest 2251 * of the required steps to fully configure memory corruption 2252 * detection are not taken. We need to ensure TTE.mcde is not 2253 * set on M7 processor. Compute the value of cacheability 2254 * flag for use later taking this into consideration. 2255 */ 2256 switch (sun4v_chip_type) { 2257 case SUN4V_CHIP_SPARC_M7: 2258 case SUN4V_CHIP_SPARC_SN: 2259 page_cache4v_flag = _PAGE_CP_4V; 2260 break; 2261 default: 2262 page_cache4v_flag = _PAGE_CACHE_4V; 2263 break; 2264 } 2265 2266 if (tlb_type == hypervisor) 2267 sun4v_pgprot_init(); 2268 else 2269 sun4u_pgprot_init(); 2270 2271 if (tlb_type == cheetah_plus || 2272 tlb_type == hypervisor) { 2273 tsb_phys_patch(); 2274 ktsb_phys_patch(); 2275 } 2276 2277 if (tlb_type == hypervisor) 2278 sun4v_patch_tlb_handlers(); 2279 2280 /* Find available physical memory... 2281 * 2282 * Read it twice in order to work around a bug in openfirmware. 2283 * The call to grab this table itself can cause openfirmware to 2284 * allocate memory, which in turn can take away some space from 2285 * the list of available memory. Reading it twice makes sure 2286 * we really do get the final value. 2287 */ 2288 read_obp_translations(); 2289 read_obp_memory("reg", &pall[0], &pall_ents); 2290 read_obp_memory("available", &pavail[0], &pavail_ents); 2291 read_obp_memory("available", &pavail[0], &pavail_ents); 2292 2293 phys_base = 0xffffffffffffffffUL; 2294 for (i = 0; i < pavail_ents; i++) { 2295 phys_base = min(phys_base, pavail[i].phys_addr); 2296 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2297 } 2298 2299 memblock_reserve(kern_base, kern_size); 2300 2301 find_ramdisk(phys_base); 2302 2303 if (cmdline_memory_size) 2304 reduce_memory(cmdline_memory_size); 2305 2306 memblock_allow_resize(); 2307 memblock_dump_all(); 2308 2309 set_bit(0, mmu_context_bmap); 2310 2311 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2312 2313 real_end = (unsigned long)_end; 2314 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2315 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2316 num_kernel_image_mappings); 2317 2318 /* Set kernel pgd to upper alias so physical page computations 2319 * work. 2320 */ 2321 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2322 2323 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2324 2325 inherit_prom_mappings(); 2326 2327 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2328 setup_tba(); 2329 2330 __flush_tlb_all(); 2331 2332 prom_build_devicetree(); 2333 of_populate_present_mask(); 2334 #ifndef CONFIG_SMP 2335 of_fill_in_cpu_data(); 2336 #endif 2337 2338 if (tlb_type == hypervisor) { 2339 sun4v_mdesc_init(); 2340 mdesc_populate_present_mask(cpu_all_mask); 2341 #ifndef CONFIG_SMP 2342 mdesc_fill_in_cpu_data(cpu_all_mask); 2343 #endif 2344 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2345 2346 sun4v_linear_pte_xor_finalize(); 2347 2348 sun4v_ktsb_init(); 2349 sun4v_ktsb_register(); 2350 } else { 2351 unsigned long impl, ver; 2352 2353 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2354 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2355 2356 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2357 impl = ((ver >> 32) & 0xffff); 2358 if (impl == PANTHER_IMPL) 2359 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2360 HV_PGSZ_MASK_256MB); 2361 2362 sun4u_linear_pte_xor_finalize(); 2363 } 2364 2365 /* Flush the TLBs and the 4M TSB so that the updated linear 2366 * pte XOR settings are realized for all mappings. 2367 */ 2368 __flush_tlb_all(); 2369 #ifndef CONFIG_DEBUG_PAGEALLOC 2370 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2371 #endif 2372 __flush_tlb_all(); 2373 2374 /* Setup bootmem... */ 2375 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2376 2377 kernel_physical_mapping_init(); 2378 2379 { 2380 unsigned long max_zone_pfns[MAX_NR_ZONES]; 2381 2382 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 2383 2384 max_zone_pfns[ZONE_NORMAL] = end_pfn; 2385 2386 free_area_init_nodes(max_zone_pfns); 2387 } 2388 2389 printk("Booting Linux...\n"); 2390 } 2391 2392 int page_in_phys_avail(unsigned long paddr) 2393 { 2394 int i; 2395 2396 paddr &= PAGE_MASK; 2397 2398 for (i = 0; i < pavail_ents; i++) { 2399 unsigned long start, end; 2400 2401 start = pavail[i].phys_addr; 2402 end = start + pavail[i].reg_size; 2403 2404 if (paddr >= start && paddr < end) 2405 return 1; 2406 } 2407 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2408 return 1; 2409 #ifdef CONFIG_BLK_DEV_INITRD 2410 if (paddr >= __pa(initrd_start) && 2411 paddr < __pa(PAGE_ALIGN(initrd_end))) 2412 return 1; 2413 #endif 2414 2415 return 0; 2416 } 2417 2418 static void __init register_page_bootmem_info(void) 2419 { 2420 #ifdef CONFIG_NEED_MULTIPLE_NODES 2421 int i; 2422 2423 for_each_online_node(i) 2424 if (NODE_DATA(i)->node_spanned_pages) 2425 register_page_bootmem_info_node(NODE_DATA(i)); 2426 #endif 2427 } 2428 void __init mem_init(void) 2429 { 2430 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 2431 2432 register_page_bootmem_info(); 2433 free_all_bootmem(); 2434 2435 /* 2436 * Set up the zero page, mark it reserved, so that page count 2437 * is not manipulated when freeing the page from user ptes. 2438 */ 2439 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 2440 if (mem_map_zero == NULL) { 2441 prom_printf("paging_init: Cannot alloc zero page.\n"); 2442 prom_halt(); 2443 } 2444 mark_page_reserved(mem_map_zero); 2445 2446 mem_init_print_info(NULL); 2447 2448 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2449 cheetah_ecache_flush_init(); 2450 } 2451 2452 void free_initmem(void) 2453 { 2454 unsigned long addr, initend; 2455 int do_free = 1; 2456 2457 /* If the physical memory maps were trimmed by kernel command 2458 * line options, don't even try freeing this initmem stuff up. 2459 * The kernel image could have been in the trimmed out region 2460 * and if so the freeing below will free invalid page structs. 2461 */ 2462 if (cmdline_memory_size) 2463 do_free = 0; 2464 2465 /* 2466 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2467 */ 2468 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2469 initend = (unsigned long)(__init_end) & PAGE_MASK; 2470 for (; addr < initend; addr += PAGE_SIZE) { 2471 unsigned long page; 2472 2473 page = (addr + 2474 ((unsigned long) __va(kern_base)) - 2475 ((unsigned long) KERNBASE)); 2476 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2477 2478 if (do_free) 2479 free_reserved_page(virt_to_page(page)); 2480 } 2481 } 2482 2483 #ifdef CONFIG_BLK_DEV_INITRD 2484 void free_initrd_mem(unsigned long start, unsigned long end) 2485 { 2486 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, 2487 "initrd"); 2488 } 2489 #endif 2490 2491 pgprot_t PAGE_KERNEL __read_mostly; 2492 EXPORT_SYMBOL(PAGE_KERNEL); 2493 2494 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2495 pgprot_t PAGE_COPY __read_mostly; 2496 2497 pgprot_t PAGE_SHARED __read_mostly; 2498 EXPORT_SYMBOL(PAGE_SHARED); 2499 2500 unsigned long pg_iobits __read_mostly; 2501 2502 unsigned long _PAGE_IE __read_mostly; 2503 EXPORT_SYMBOL(_PAGE_IE); 2504 2505 unsigned long _PAGE_E __read_mostly; 2506 EXPORT_SYMBOL(_PAGE_E); 2507 2508 unsigned long _PAGE_CACHE __read_mostly; 2509 EXPORT_SYMBOL(_PAGE_CACHE); 2510 2511 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2512 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2513 int node) 2514 { 2515 unsigned long pte_base; 2516 2517 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2518 _PAGE_CP_4U | _PAGE_CV_4U | 2519 _PAGE_P_4U | _PAGE_W_4U); 2520 if (tlb_type == hypervisor) 2521 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2522 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2523 2524 pte_base |= _PAGE_PMD_HUGE; 2525 2526 vstart = vstart & PMD_MASK; 2527 vend = ALIGN(vend, PMD_SIZE); 2528 for (; vstart < vend; vstart += PMD_SIZE) { 2529 pgd_t *pgd = pgd_offset_k(vstart); 2530 unsigned long pte; 2531 pud_t *pud; 2532 pmd_t *pmd; 2533 2534 if (pgd_none(*pgd)) { 2535 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node); 2536 2537 if (!new) 2538 return -ENOMEM; 2539 pgd_populate(&init_mm, pgd, new); 2540 } 2541 2542 pud = pud_offset(pgd, vstart); 2543 if (pud_none(*pud)) { 2544 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node); 2545 2546 if (!new) 2547 return -ENOMEM; 2548 pud_populate(&init_mm, pud, new); 2549 } 2550 2551 pmd = pmd_offset(pud, vstart); 2552 2553 pte = pmd_val(*pmd); 2554 if (!(pte & _PAGE_VALID)) { 2555 void *block = vmemmap_alloc_block(PMD_SIZE, node); 2556 2557 if (!block) 2558 return -ENOMEM; 2559 2560 pmd_val(*pmd) = pte_base | __pa(block); 2561 } 2562 } 2563 2564 return 0; 2565 } 2566 2567 void vmemmap_free(unsigned long start, unsigned long end) 2568 { 2569 } 2570 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2571 2572 static void prot_init_common(unsigned long page_none, 2573 unsigned long page_shared, 2574 unsigned long page_copy, 2575 unsigned long page_readonly, 2576 unsigned long page_exec_bit) 2577 { 2578 PAGE_COPY = __pgprot(page_copy); 2579 PAGE_SHARED = __pgprot(page_shared); 2580 2581 protection_map[0x0] = __pgprot(page_none); 2582 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2583 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2584 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2585 protection_map[0x4] = __pgprot(page_readonly); 2586 protection_map[0x5] = __pgprot(page_readonly); 2587 protection_map[0x6] = __pgprot(page_copy); 2588 protection_map[0x7] = __pgprot(page_copy); 2589 protection_map[0x8] = __pgprot(page_none); 2590 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2591 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2592 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2593 protection_map[0xc] = __pgprot(page_readonly); 2594 protection_map[0xd] = __pgprot(page_readonly); 2595 protection_map[0xe] = __pgprot(page_shared); 2596 protection_map[0xf] = __pgprot(page_shared); 2597 } 2598 2599 static void __init sun4u_pgprot_init(void) 2600 { 2601 unsigned long page_none, page_shared, page_copy, page_readonly; 2602 unsigned long page_exec_bit; 2603 int i; 2604 2605 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2606 _PAGE_CACHE_4U | _PAGE_P_4U | 2607 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2608 _PAGE_EXEC_4U); 2609 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2610 _PAGE_CACHE_4U | _PAGE_P_4U | 2611 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2612 _PAGE_EXEC_4U | _PAGE_L_4U); 2613 2614 _PAGE_IE = _PAGE_IE_4U; 2615 _PAGE_E = _PAGE_E_4U; 2616 _PAGE_CACHE = _PAGE_CACHE_4U; 2617 2618 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2619 __ACCESS_BITS_4U | _PAGE_E_4U); 2620 2621 #ifdef CONFIG_DEBUG_PAGEALLOC 2622 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2623 #else 2624 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2625 PAGE_OFFSET; 2626 #endif 2627 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2628 _PAGE_P_4U | _PAGE_W_4U); 2629 2630 for (i = 1; i < 4; i++) 2631 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2632 2633 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2634 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2635 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2636 2637 2638 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2639 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2640 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2641 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2642 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2643 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2644 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2645 2646 page_exec_bit = _PAGE_EXEC_4U; 2647 2648 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2649 page_exec_bit); 2650 } 2651 2652 static void __init sun4v_pgprot_init(void) 2653 { 2654 unsigned long page_none, page_shared, page_copy, page_readonly; 2655 unsigned long page_exec_bit; 2656 int i; 2657 2658 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2659 page_cache4v_flag | _PAGE_P_4V | 2660 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2661 _PAGE_EXEC_4V); 2662 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2663 2664 _PAGE_IE = _PAGE_IE_4V; 2665 _PAGE_E = _PAGE_E_4V; 2666 _PAGE_CACHE = page_cache4v_flag; 2667 2668 #ifdef CONFIG_DEBUG_PAGEALLOC 2669 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2670 #else 2671 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2672 PAGE_OFFSET; 2673 #endif 2674 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2675 _PAGE_W_4V); 2676 2677 for (i = 1; i < 4; i++) 2678 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2679 2680 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2681 __ACCESS_BITS_4V | _PAGE_E_4V); 2682 2683 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2684 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2685 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2686 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2687 2688 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2689 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2690 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2691 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2692 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2693 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2694 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2695 2696 page_exec_bit = _PAGE_EXEC_4V; 2697 2698 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2699 page_exec_bit); 2700 } 2701 2702 unsigned long pte_sz_bits(unsigned long sz) 2703 { 2704 if (tlb_type == hypervisor) { 2705 switch (sz) { 2706 case 8 * 1024: 2707 default: 2708 return _PAGE_SZ8K_4V; 2709 case 64 * 1024: 2710 return _PAGE_SZ64K_4V; 2711 case 512 * 1024: 2712 return _PAGE_SZ512K_4V; 2713 case 4 * 1024 * 1024: 2714 return _PAGE_SZ4MB_4V; 2715 } 2716 } else { 2717 switch (sz) { 2718 case 8 * 1024: 2719 default: 2720 return _PAGE_SZ8K_4U; 2721 case 64 * 1024: 2722 return _PAGE_SZ64K_4U; 2723 case 512 * 1024: 2724 return _PAGE_SZ512K_4U; 2725 case 4 * 1024 * 1024: 2726 return _PAGE_SZ4MB_4U; 2727 } 2728 } 2729 } 2730 2731 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2732 { 2733 pte_t pte; 2734 2735 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2736 pte_val(pte) |= (((unsigned long)space) << 32); 2737 pte_val(pte) |= pte_sz_bits(page_size); 2738 2739 return pte; 2740 } 2741 2742 static unsigned long kern_large_tte(unsigned long paddr) 2743 { 2744 unsigned long val; 2745 2746 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2747 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2748 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2749 if (tlb_type == hypervisor) 2750 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2751 page_cache4v_flag | _PAGE_P_4V | 2752 _PAGE_EXEC_4V | _PAGE_W_4V); 2753 2754 return val | paddr; 2755 } 2756 2757 /* If not locked, zap it. */ 2758 void __flush_tlb_all(void) 2759 { 2760 unsigned long pstate; 2761 int i; 2762 2763 __asm__ __volatile__("flushw\n\t" 2764 "rdpr %%pstate, %0\n\t" 2765 "wrpr %0, %1, %%pstate" 2766 : "=r" (pstate) 2767 : "i" (PSTATE_IE)); 2768 if (tlb_type == hypervisor) { 2769 sun4v_mmu_demap_all(); 2770 } else if (tlb_type == spitfire) { 2771 for (i = 0; i < 64; i++) { 2772 /* Spitfire Errata #32 workaround */ 2773 /* NOTE: Always runs on spitfire, so no 2774 * cheetah+ page size encodings. 2775 */ 2776 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2777 "flush %%g6" 2778 : /* No outputs */ 2779 : "r" (0), 2780 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2781 2782 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2783 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2784 "membar #Sync" 2785 : /* no outputs */ 2786 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2787 spitfire_put_dtlb_data(i, 0x0UL); 2788 } 2789 2790 /* Spitfire Errata #32 workaround */ 2791 /* NOTE: Always runs on spitfire, so no 2792 * cheetah+ page size encodings. 2793 */ 2794 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2795 "flush %%g6" 2796 : /* No outputs */ 2797 : "r" (0), 2798 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2799 2800 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2801 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2802 "membar #Sync" 2803 : /* no outputs */ 2804 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2805 spitfire_put_itlb_data(i, 0x0UL); 2806 } 2807 } 2808 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2809 cheetah_flush_dtlb_all(); 2810 cheetah_flush_itlb_all(); 2811 } 2812 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2813 : : "r" (pstate)); 2814 } 2815 2816 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 2817 unsigned long address) 2818 { 2819 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); 2820 pte_t *pte = NULL; 2821 2822 if (page) 2823 pte = (pte_t *) page_address(page); 2824 2825 return pte; 2826 } 2827 2828 pgtable_t pte_alloc_one(struct mm_struct *mm, 2829 unsigned long address) 2830 { 2831 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); 2832 if (!page) 2833 return NULL; 2834 if (!pgtable_page_ctor(page)) { 2835 free_hot_cold_page(page, 0); 2836 return NULL; 2837 } 2838 return (pte_t *) page_address(page); 2839 } 2840 2841 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2842 { 2843 free_page((unsigned long)pte); 2844 } 2845 2846 static void __pte_free(pgtable_t pte) 2847 { 2848 struct page *page = virt_to_page(pte); 2849 2850 pgtable_page_dtor(page); 2851 __free_page(page); 2852 } 2853 2854 void pte_free(struct mm_struct *mm, pgtable_t pte) 2855 { 2856 __pte_free(pte); 2857 } 2858 2859 void pgtable_free(void *table, bool is_page) 2860 { 2861 if (is_page) 2862 __pte_free(table); 2863 else 2864 kmem_cache_free(pgtable_cache, table); 2865 } 2866 2867 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2868 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2869 pmd_t *pmd) 2870 { 2871 unsigned long pte, flags; 2872 struct mm_struct *mm; 2873 pmd_t entry = *pmd; 2874 2875 if (!pmd_large(entry) || !pmd_young(entry)) 2876 return; 2877 2878 pte = pmd_val(entry); 2879 2880 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2881 if (!(pte & _PAGE_VALID)) 2882 return; 2883 2884 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2885 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2886 2887 mm = vma->vm_mm; 2888 2889 spin_lock_irqsave(&mm->context.lock, flags); 2890 2891 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 2892 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 2893 addr, pte); 2894 2895 spin_unlock_irqrestore(&mm->context.lock, flags); 2896 } 2897 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 2898 2899 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 2900 static void context_reload(void *__data) 2901 { 2902 struct mm_struct *mm = __data; 2903 2904 if (mm == current->mm) 2905 load_secondary_context(mm); 2906 } 2907 2908 void hugetlb_setup(struct pt_regs *regs) 2909 { 2910 struct mm_struct *mm = current->mm; 2911 struct tsb_config *tp; 2912 2913 if (faulthandler_disabled() || !mm) { 2914 const struct exception_table_entry *entry; 2915 2916 entry = search_exception_tables(regs->tpc); 2917 if (entry) { 2918 regs->tpc = entry->fixup; 2919 regs->tnpc = regs->tpc + 4; 2920 return; 2921 } 2922 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 2923 die_if_kernel("HugeTSB in atomic", regs); 2924 } 2925 2926 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 2927 if (likely(tp->tsb == NULL)) 2928 tsb_grow(mm, MM_TSB_HUGE, 0); 2929 2930 tsb_context_switch(mm); 2931 smp_tsb_sync(mm); 2932 2933 /* On UltraSPARC-III+ and later, configure the second half of 2934 * the Data-TLB for huge pages. 2935 */ 2936 if (tlb_type == cheetah_plus) { 2937 bool need_context_reload = false; 2938 unsigned long ctx; 2939 2940 spin_lock_irq(&ctx_alloc_lock); 2941 ctx = mm->context.sparc64_ctx_val; 2942 ctx &= ~CTX_PGSZ_MASK; 2943 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 2944 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 2945 2946 if (ctx != mm->context.sparc64_ctx_val) { 2947 /* When changing the page size fields, we 2948 * must perform a context flush so that no 2949 * stale entries match. This flush must 2950 * occur with the original context register 2951 * settings. 2952 */ 2953 do_flush_tlb_mm(mm); 2954 2955 /* Reload the context register of all processors 2956 * also executing in this address space. 2957 */ 2958 mm->context.sparc64_ctx_val = ctx; 2959 need_context_reload = true; 2960 } 2961 spin_unlock_irq(&ctx_alloc_lock); 2962 2963 if (need_context_reload) 2964 on_each_cpu(context_reload, mm, 0); 2965 } 2966 } 2967 #endif 2968 2969 static struct resource code_resource = { 2970 .name = "Kernel code", 2971 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 2972 }; 2973 2974 static struct resource data_resource = { 2975 .name = "Kernel data", 2976 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 2977 }; 2978 2979 static struct resource bss_resource = { 2980 .name = "Kernel bss", 2981 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 2982 }; 2983 2984 static inline resource_size_t compute_kern_paddr(void *addr) 2985 { 2986 return (resource_size_t) (addr - KERNBASE + kern_base); 2987 } 2988 2989 static void __init kernel_lds_init(void) 2990 { 2991 code_resource.start = compute_kern_paddr(_text); 2992 code_resource.end = compute_kern_paddr(_etext - 1); 2993 data_resource.start = compute_kern_paddr(_etext); 2994 data_resource.end = compute_kern_paddr(_edata - 1); 2995 bss_resource.start = compute_kern_paddr(__bss_start); 2996 bss_resource.end = compute_kern_paddr(_end - 1); 2997 } 2998 2999 static int __init report_memory(void) 3000 { 3001 int i; 3002 struct resource *res; 3003 3004 kernel_lds_init(); 3005 3006 for (i = 0; i < pavail_ents; i++) { 3007 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 3008 3009 if (!res) { 3010 pr_warn("Failed to allocate source.\n"); 3011 break; 3012 } 3013 3014 res->name = "System RAM"; 3015 res->start = pavail[i].phys_addr; 3016 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3017 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3018 3019 if (insert_resource(&iomem_resource, res) < 0) { 3020 pr_warn("Resource insertion failed.\n"); 3021 break; 3022 } 3023 3024 insert_resource(res, &code_resource); 3025 insert_resource(res, &data_resource); 3026 insert_resource(res, &bss_resource); 3027 } 3028 3029 return 0; 3030 } 3031 arch_initcall(report_memory); 3032 3033 #ifdef CONFIG_SMP 3034 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3035 #else 3036 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3037 #endif 3038 3039 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3040 { 3041 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3042 if (start < LOW_OBP_ADDRESS) { 3043 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3044 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3045 } 3046 if (end > HI_OBP_ADDRESS) { 3047 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3048 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3049 } 3050 } else { 3051 flush_tsb_kernel_range(start, end); 3052 do_flush_tlb_kernel_range(start, end); 3053 } 3054 } 3055